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create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewd create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewp create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/project.eww create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvoptx create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.h create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.py create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/template.ewp create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvoptx create mode 100644 bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvprojx diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/MCXN236.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/MCXN236.h new file mode 100644 index 0000000000..113e97967e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/MCXN236.h @@ -0,0 +1,70367 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240409 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXN236 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN236.h + * @version 1.0 + * @date 2023-10-01 + * @brief CMSIS Peripheral Access Layer for MCXN236 + * + * CMSIS Peripheral Access Layer for MCXN236 + */ + +#if !defined(MCXN236_H_) +#define MCXN236_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 172 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + OR_IRQn = 0, /**< OR IRQ */ + EDMA_0_CH0_IRQn = 1, /**< eDMA_0_CH0 error or transfer complete */ + EDMA_0_CH1_IRQn = 2, /**< eDMA_0_CH1 error or transfer complete */ + EDMA_0_CH2_IRQn = 3, /**< eDMA_0_CH2 error or transfer complete */ + EDMA_0_CH3_IRQn = 4, /**< eDMA_0_CH3 error or transfer complete */ + EDMA_0_CH4_IRQn = 5, /**< eDMA_0_CH4 error or transfer complete */ + EDMA_0_CH5_IRQn = 6, /**< eDMA_0_CH5 error or transfer complete */ + EDMA_0_CH6_IRQn = 7, /**< eDMA_0_CH6 error or transfer complete */ + EDMA_0_CH7_IRQn = 8, /**< eDMA_0_CH7 error or transfer complete */ + EDMA_0_CH8_IRQn = 9, /**< eDMA_0_CH8 error or transfer complete */ + EDMA_0_CH9_IRQn = 10, /**< eDMA_0_CH9 error or transfer complete */ + EDMA_0_CH10_IRQn = 11, /**< eDMA_0_CH10 error or transfer complete */ + EDMA_0_CH11_IRQn = 12, /**< eDMA_0_CH11 error or transfer complete */ + EDMA_0_CH12_IRQn = 13, /**< eDMA_0_CH12 error or transfer complete */ + EDMA_0_CH13_IRQn = 14, /**< eDMA_0_CH13 error or transfer complete */ + EDMA_0_CH14_IRQn = 15, /**< eDMA_0_CH14 error or transfer complete */ + EDMA_0_CH15_IRQn = 16, /**< eDMA_0_CH15 error or transfer complete */ + GPIO00_IRQn = 17, /**< GPIO0 interrupt 0 */ + GPIO01_IRQn = 18, /**< GPIO0 interrupt 1 */ + GPIO10_IRQn = 19, /**< GPIO1 interrupt 0 */ + GPIO11_IRQn = 20, /**< GPIO1 interrupt 1 */ + GPIO20_IRQn = 21, /**< GPIO2 interrupt 0 */ + GPIO21_IRQn = 22, /**< GPIO2 interrupt 1 */ + GPIO30_IRQn = 23, /**< GPIO3 interrupt 0 */ + GPIO31_IRQn = 24, /**< GPIO3 interrupt 1 */ + GPIO40_IRQn = 25, /**< GPIO4 interrupt 0 */ + GPIO41_IRQn = 26, /**< GPIO4 interrupt 1 */ + GPIO50_IRQn = 27, /**< GPIO5 interrupt 0 */ + GPIO51_IRQn = 28, /**< GPIO5 interrupt 1 */ + UTICK0_IRQn = 29, /**< Micro-Tick Timer interrupt */ + MRT0_IRQn = 30, /**< Multi-Rate Timer interrupt */ + CTIMER0_IRQn = 31, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 32, /**< Standard counter/timer 1 interrupt */ + Reserved49_IRQn = 33, /**< Reserved interrupt */ + CTIMER2_IRQn = 34, /**< Standard counter/timer 2 interrupt */ + LP_FLEXCOMM0_IRQn = 35, /**< LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM1_IRQn = 36, /**< LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM2_IRQn = 37, /**< LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM3_IRQn = 38, /**< LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM4_IRQn = 39, /**< LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM5_IRQn = 40, /**< LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM6_IRQn = 41, /**< LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + LP_FLEXCOMM7_IRQn = 42, /**< LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + ADC0_IRQn = 45, /**< Analog-to-Digital Converter 0 - General Purpose interrupt */ + ADC1_IRQn = 46, /**< Analog-to-Digital Converter 1 - General Purpose interrupt */ + PINT0_IRQn = 47, /**< Pin Interrupt Pattern Match Interrupt */ + PDM_EVENT_IRQn = 48, /**< Microphone Interface interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + Reserved66_IRQn = 50, /**< Reserved interrupt */ + USB0_DCD_IRQn = 51, /**< Universal Serial Bus - Device Charge Detect interrupt */ + RTC_IRQn = 52, /**< RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) */ + SMARTDMA_IRQn = 53, /**< SmartDMA_IRQ */ + Reserved70_IRQn = 54, /**< Reserved interrupt */ + CTIMER3_IRQn = 55, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 56, /**< Standard counter/timer 4 interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + Reserved74_IRQn = 58, /**< Reserved interrupt */ + SAI0_IRQn = 59, /**< Serial Audio Interface 0 interrupt */ + SAI1_IRQn = 60, /**< Serial Audio Interface 1 interrupt */ + Reserved77_IRQn = 61, /**< Reserved interrupt */ + CAN0_IRQn = 62, /**< Controller Area Network 0 interrupt */ + CAN1_IRQn = 63, /**< Controller Area Network 1 interrupt */ + Reserved80_IRQn = 64, /**< Reserved interrupt */ + Reserved81_IRQn = 65, /**< Reserved interrupt */ + USB1_HS_PHY_IRQn = 66, /**< USBHS DCD or USBHS Phy interrupt */ + USB1_HS_IRQn = 67, /**< USB High Speed OTG Controller interrupt */ + SEC_HYPERVISOR_CALL_IRQn = 68, /**< AHB Secure Controller hypervisor call interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Freqme_IRQn = 71, /**< Frequency Measurement interrupt */ + SEC_VIO_IRQn = 72, /**< Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) */ + ELS_IRQn = 73, /**< ELS interrupt */ + PKC_IRQn = 74, /**< PKC interrupt */ + PUF_IRQn = 75, /**< Physical Unclonable Function interrupt */ + Reserved92_IRQn = 76, /**< Reserved interrupt */ + EDMA_1_CH0_IRQn = 77, /**< eDMA_1_CH0 error or transfer complete */ + EDMA_1_CH1_IRQn = 78, /**< eDMA_1_CH1 error or transfer complete */ + EDMA_1_CH2_IRQn = 79, /**< eDMA_1_CH2 error or transfer complete */ + EDMA_1_CH3_IRQn = 80, /**< eDMA_1_CH3 error or transfer complete */ + EDMA_1_CH4_IRQn = 81, /**< eDMA_1_CH4 error or transfer complete */ + EDMA_1_CH5_IRQn = 82, /**< eDMA_1_CH5 error or transfer complete */ + EDMA_1_CH6_IRQn = 83, /**< eDMA_1_CH6 error or transfer complete */ + EDMA_1_CH7_IRQn = 84, /**< eDMA_1_CH7 error or transfer complete */ + Reserved101_IRQn = 85, /**< Reserved interrupt */ + Reserved102_IRQn = 86, /**< Reserved interrupt */ + Reserved103_IRQn = 87, /**< Reserved interrupt */ + Reserved104_IRQn = 88, /**< Reserved interrupt */ + Reserved105_IRQn = 89, /**< Reserved interrupt */ + Reserved106_IRQn = 90, /**< Reserved interrupt */ + Reserved107_IRQn = 91, /**< Reserved interrupt */ + Reserved108_IRQn = 92, /**< Reserved interrupt */ + CDOG0_IRQn = 93, /**< Code Watchdog Timer 0 interrupt */ + CDOG1_IRQn = 94, /**< Code Watchdog Timer 1 interrupt */ + I3C0_IRQn = 95, /**< Improved Inter Integrated Circuit interrupt 0 */ + I3C1_IRQn = 96, /**< Improved Inter Integrated Circuit interrupt 1 */ + Reserved113_IRQn = 97, /**< Reserved interrupt */ + GDET_IRQn = 98, /**< Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt */ + VBAT0_IRQn = 99, /**< VBAT interrupt( VBAT interrupt or digital tamper interrupt) */ + EWM0_IRQn = 100, /**< External Watchdog Monitor interrupt */ + Reserved117_IRQn = 101, /**< Reserved interrupt */ + Reserved118_IRQn = 102, /**< Reserved interrupt */ + Reserved119_IRQn = 103, /**< Reserved interrupt */ + Reserved120_IRQn = 104, /**< Reserved interrupt */ + FLEXIO_IRQn = 105, /**< Flexible Input/Output interrupt */ + Reserved122_IRQn = 106, /**< Reserved interrupt */ + Reserved123_IRQn = 107, /**< Reserved interrupt */ + Reserved124_IRQn = 108, /**< Reserved interrupt */ + HSCMP0_IRQn = 109, /**< High-Speed comparator0 interrupt */ + HSCMP1_IRQn = 110, /**< High-Speed comparator1 interrupt */ + Reserved127_IRQn = 111, /**< Reserved interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 112, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 113, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 114, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 115, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 116, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE3_IRQn = 117, /**< FlexPWM0 Submodule 3 capture/compare/reload interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 118, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 119, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 120, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 121, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 122, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE3_IRQn = 123, /**< FlexPWM1 Submodule 3 capture/compare/reload interrupt */ + QDC0_COMPARE_IRQn = 124, /**< QDC0_Compare interrupt */ + QDC0_HOME_IRQn = 125, /**< QDC0_Home interrupt */ + QDC0_WDG_SAB_IRQn = 126, /**< QDC0_WDG_IRQ/SAB interrupt */ + QDC0_IDX_IRQn = 127, /**< QDC0_IDX interrupt */ + QDC1_COMPARE_IRQn = 128, /**< QDC1_Compare interrupt */ + QDC1_HOME_IRQn = 129, /**< QDC1_Home interrupt */ + QDC1_WDG_SAB_IRQn = 130, /**< QDC1_WDG_IRQ/SAB interrupt */ + QDC1_IDX_IRQn = 131, /**< QDC1_IDX interrupt */ + ITRC0_IRQn = 132, /**< Intrusion and Tamper Response Controller interrupt */ + Reserved149_IRQn = 133, /**< Reserved interrupt */ + ELS_ERR_IRQn = 134, /**< ELS error interrupt */ + PKC_ERR_IRQn = 135, /**< PKC error interrupt */ + ERM_SINGLE_BIT_ERROR_IRQn = 136, /**< ERM Single Bit error interrupt */ + ERM_MULTI_BIT_ERROR_IRQn = 137, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 138, /**< Flash Management Unit interrupt */ + Reserved155_IRQn = 139, /**< Reserved interrupt */ + Reserved156_IRQn = 140, /**< Reserved interrupt */ + Reserved157_IRQn = 141, /**< Reserved interrupt */ + Reserved158_IRQn = 142, /**< Reserved interrupt */ + LPTMR0_IRQn = 143, /**< Low Power Timer 0 interrupt */ + LPTMR1_IRQn = 144, /**< Low Power Timer 1 interrupt */ + SCG_IRQn = 145, /**< System Clock Generator interrupt */ + SPC_IRQn = 146, /**< System Power Controller interrupt */ + WUU_IRQn = 147, /**< Wake Up Unit interrupt */ + PORT_EFT_IRQn = 148, /**< PORT0~5 EFT interrupt */ + Reserved165_IRQn = 149, /**< Reserved interrupt */ + Reserved166_IRQn = 150, /**< Reserved interrupt */ + Reserved167_IRQn = 151, /**< Reserved interrupt */ + WWDT0_IRQn = 152, /**< Windowed Watchdog Timer 0 interrupt */ + WWDT1_IRQn = 153, /**< Windowed Watchdog Timer 1 interrupt */ + CMC0_IRQn = 154, /**< Core Mode Controller interrupt */ + Reserved171_IRQn = 155 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 1 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXN236.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup eim_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_memory_channel + * + * Defines the structure for the EIM resource collections. + */ + +typedef enum _eim_memory_channel +{ + kEIM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ + kEIM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ + kEIM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ + kEIM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ + kEIM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ + kEIM_MemoryChannelRAME = 5U, /**< Memory RAME */ + kEIM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ + kEIM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ + kEIM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ +} eim_memory_channel_t; + +/* @} */ + +/*! + * @addtogroup eim_error_injection_channel_enable + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_error_injection_channel_enable + * + * Defines the structure for the EIM error injection resource collections. + */ + +typedef enum _eim_error_injection_channel_enable +{ + kEIM_MemoryChannelRAMXEnable = 0x80000000U, /**< Memory channel 0(RAMX) error injection enable */ + kEIM_MemoryChannelRAMAEnable = 0x40000000U, /**< Memory channel 1(RAMA) error injection enable */ + kEIM_MemoryChannelRAMBEnable = 0x20000000U, /**< Memory channel 2(RAMB) error injection enable */ + kEIM_MemoryChannelRAMCEnable = 0x10000000U, /**< Memory channel 3(RAMC) error injection enable */ + kEIM_MemoryChannelRAMDEnable = 0x8000000U, /**< Memory channel 4(RAMD) error injection enable */ + kEIM_MemoryChannelRAMEEnable = 0x4000000U, /**< Memory channel 5(RAME) error injection enable */ + kEIM_MemoryChannelRAMFEnable = 0x2000000U, /**< Memory channel 6(RAMF) error injection enable */ + kEIM_MemoryChannelLPCACRAMEnable = 0x1000000U, /**< Memory channel 7(LPCACRAM) error injection enable */ + kEIM_MemoryChannelPKCRAMEnable = 0x800000U, /**< Memory channel 8(PKCRAM) error injection enable */ +} eim_error_injection_channel_enable_t; + +/* @} */ + +/*! + * @addtogroup erm_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the erm_memory_channel + * + * Defines the structure for the ERM resource collections. + */ + +typedef enum _erm_memory_channel +{ + kERM_MemoryChannelRAMX = 0U, /**< Memory RAMX */ + kERM_MemoryChannelRAMA = 1U, /**< Memory RAMA */ + kERM_MemoryChannelRAMB = 2U, /**< Memory RAMB */ + kERM_MemoryChannelRAMC = 3U, /**< Memory RAMC */ + kERM_MemoryChannelRAMD = 4U, /**< Memory RAMD */ + kERM_MemoryChannelRAME = 5U, /**< Memory RAME */ + kERM_MemoryChannelRAMF = 6U, /**< Memory RAMF */ + kERM_MemoryChannelLPCACRAM = 7U, /**< Memory LPCACRAM */ + kERM_MemoryChannelPKCRAM = 8U, /**< Memory PKCRAM */ + kERM_MemoryChannelFLASH = 9U, /**< Memory FLASH */ +} erm_memory_channel_t; + +/* @} */ + +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma1RequestMuxPinInt0 = 3U, /**< PINT0 INT0 */ + kDma0RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma1RequestMuxPinInt1 = 4U, /**< PINT0 INT1 */ + kDma0RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma1RequestMuxPinInt2 = 5U, /**< PINT0 INT2 */ + kDma0RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma1RequestMuxPinInt3 = 6U, /**< PINT0 INT3 */ + kDma0RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma1RequestMuxCtimer0M0 = 7U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma1RequestMuxCtimer0M1 = 8U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma1RequestMuxCtimer1M0 = 9U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma1RequestMuxCtimer1M1 = 10U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma1RequestMuxCtimer2M0 = 11U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma1RequestMuxCtimer2M1 = 12U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma1RequestMuxCtimer3M0 = 13U, /**< CTIMER3 Match channel 0 request */ + kDma0RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma1RequestMuxCtimer3M1 = 14U, /**< CTIMER3 Match channel 1 request */ + kDma0RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma1RequestMuxCtimer4M0 = 15U, /**< CTIMER4 Match channel 0 request */ + kDma0RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma1RequestMuxCtimer4M1 = 16U, /**< CTIMER4 Match channel 1 request */ + kDma0RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma1RequestMuxWuu0 = 17U, /**< WUU0 Wake up event */ + kDma0RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma1RequestMuxMicfil0FifoRequest = 18U, /**< MICFIL0 FIFO_request */ + kDma0RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma1RequestMuxAdc0FifoARequest = 21U, /**< ADC0 FIFO A request */ + kDma0RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma1RequestMuxAdc0FifoBRequest = 22U, /**< ADC0 FIFO B request */ + kDma0RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma1RequestMuxAdc1FifoARequest = 23U, /**< ADC1 FIFO A request */ + kDma0RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma1RequestMuxAdc1FifoBRequest = 24U, /**< ADC1 FIFO B request */ + kDma0RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma1RequestMuxHsCmp0DmaRequest = 28U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma1RequestMuxHsCmp1DmaRequest = 29U, /**< CMP1 DMA_request */ + kDma0RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma1RequestMuxEvtg0Out0A = 31U, /**< EVTG0 OUT0A */ + kDma0RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma1RequestMuxEvtg0Out0B = 32U, /**< EVTG0 OUT0B */ + kDma0RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma1RequestMuxEvtg0Out1A = 33U, /**< EVTG0 OUT1A */ + kDma0RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma1RequestMuxEvtg0Out1B = 34U, /**< EVTG0 OUT1B */ + kDma0RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma1RequestMuxEvtg0Out2A = 35U, /**< EVTG0 OUT2A */ + kDma0RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma1RequestMuxEvtg0Out2B = 36U, /**< EVTG0 OUT2B */ + kDma0RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma1RequestMuxEvtg0Out3A = 37U, /**< EVTG0 OUT3A */ + kDma0RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma1RequestMuxEvtg0Out3B = 38U, /**< EVTG0 OUT3B */ + kDma0RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma1RequestMuxFlexPwm0ReqCapt0 = 39U, /**< PWM0 capture0 request */ + kDma0RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma1RequestMuxFlexPwm0ReqCapt1 = 40U, /**< PWM0 capture1 request */ + kDma0RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma1RequestMuxFlexPwm0ReqCapt2 = 41U, /**< PWM0 capture2 request */ + kDma0RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma1RequestMuxFlexPwm0ReqCapt3 = 42U, /**< PWM0 capture3 request */ + kDma0RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma1RequestMuxFlexPwm0ReqVal0 = 43U, /**< PWM0 value0 request */ + kDma0RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma1RequestMuxFlexPwm0ReqVal1 = 44U, /**< PWM0 value1 request */ + kDma0RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma1RequestMuxFlexPwm0ReqVal2 = 45U, /**< PWM0 value2 request */ + kDma0RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm0ReqVal3 = 46U, /**< PWM0 value3 request */ + kDma0RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma1RequestMuxFlexPwm1ReqCapt0 = 47U, /**< PWM1 capture0 request */ + kDma0RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma1RequestMuxFlexPwm1ReqCapt1 = 48U, /**< PWM1 capture1 request */ + kDma0RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma1RequestMuxFlexPwm1ReqCapt2 = 49U, /**< PWM1 capture2 request */ + kDma0RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma1RequestMuxFlexPwm1ReqCapt3 = 50U, /**< PWM1 capture3 request */ + kDma0RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma1RequestMuxFlexPwm1ReqVal0 = 51U, /**< PWM1 value0 request */ + kDma0RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma1RequestMuxFlexPwm1ReqVal1 = 52U, /**< PWM1 value1 request */ + kDma0RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma1RequestMuxFlexPwm1ReqVal2 = 53U, /**< PWM1 value2 request */ + kDma0RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma1RequestMuxFlexPwm1ReqVal3 = 54U, /**< PWM0 value3 request */ + kDma0RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma1RequestMuxLptmr0 = 57U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma1RequestMuxLptmr1 = 58U, /**< LPTMR1 Counter match event */ + kDma0RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma1RequestMuxFlexCan0DmaRequest = 59U, /**< CAN0 DMA request */ + kDma0RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma1RequestMuxFlexCan1DmaRequest = 60U, /**< CAN1 DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister0Request = 61U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister1Request = 62U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister2Request = 63U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister3Request = 64U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister4Request = 65U, /**< FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister5Request = 66U, /**< FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister6Request = 67U, /**< FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma1RequestMuxFlexIO0ShiftRegister7Request = 68U, /**< FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request */ + kDma0RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma1RequestMuxLpFlexcomm0Rx = 69U, /**< LP_FLEXCOMM0 Receive request */ + kDma0RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma1RequestMuxLpFlexcomm0Tx = 70U, /**< LP_FLEXCOMM0 Transmit request */ + kDma0RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma1RequestMuxLpFlexcomm1Rx = 71U, /**< LP_FLEXCOMM1 Receive request */ + kDma0RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma1RequestMuxLpFlexcomm1Tx = 72U, /**< LP_FLEXCOMM1 Transmit request */ + kDma0RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma1RequestMuxLpFlexcomm2Rx = 73U, /**< LP_FLEXCOMM2 Receive request */ + kDma0RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma1RequestMuxLpFlexcomm2Tx = 74U, /**< LP_FLEXCOMM2 Transmit request */ + kDma0RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma1RequestMuxLpFlexcomm3Rx = 75U, /**< LP_FLEXCOMM3 Receive request */ + kDma0RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma1RequestMuxLpFlexcomm3Tx = 76U, /**< LP_FLEXCOMM3 Transmit request */ + kDma0RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma1RequestMuxLpFlexcomm4Rx = 77U, /**< LP_FLEXCOMM4 Receive request */ + kDma0RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma1RequestMuxLpFlexcomm4Tx = 78U, /**< LP_FLEXCOMM4 Transmit request */ + kDma0RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma1RequestMuxLpFlexcomm5Rx = 79U, /**< LP_FLEXCOMM5 Receive request */ + kDma0RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma1RequestMuxLpFlexcomm5Tx = 80U, /**< LP_FLEXCOMM5 Transmit request */ + kDma0RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma1RequestMuxLpFlexcomm6Rx = 81U, /**< LP_FLEXCOMM6 Receive request */ + kDma0RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma1RequestMuxLpFlexcomm6Tx = 82U, /**< LP_FLEXCOMM6 Transmit request */ + kDma0RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma1RequestMuxLpFlexcomm7Rx = 83U, /**< LP_FLEXCOMM7 Receive request */ + kDma0RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma1RequestMuxLpFlexcomm7Tx = 84U, /**< LP_FLEXCOMM7 Transmit request */ + kDma0RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma1RequestMuxI3c0Rx = 95U, /**< I3C0 Receive request */ + kDma0RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma1RequestMuxI3c0Tx = 96U, /**< I3C0 Transmit request */ + kDma0RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma1RequestMuxI3c1Rx = 97U, /**< I3C1 Receive request */ + kDma0RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma1RequestMuxI3c1Tx = 98U, /**< I3C1 Transmit request */ + kDma0RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma1RequestMuxSai0Rx = 99U, /**< SAI0 Receive request */ + kDma0RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma1RequestMuxSai0Tx = 100U, /**< SAI0 Transmit request */ + kDma0RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma1RequestMuxSai1Rx = 101U, /**< SAI1 Receive request */ + kDma0RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma1RequestMuxSai1Tx = 102U, /**< SAI1 Transmit request */ + kDma0RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma1RequestMuxGpio0PinEventRequest0 = 108U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma1RequestMuxGpio0PinEventRequest1 = 109U, /**< GPIO0 Pin event request 1 */ + kDma0RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma1RequestMuxGpio1PinEventRequest0 = 110U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma1RequestMuxGpio1PinEventRequest1 = 111U, /**< GPIO1 Pin event request 1 */ + kDma0RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma1RequestMuxGpio2PinEventRequest0 = 112U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma1RequestMuxGpio2PinEventRequest1 = 113U, /**< GPIO2 Pin event request 1 */ + kDma0RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma1RequestMuxGpio3PinEventRequest0 = 114U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma1RequestMuxGpio3PinEventRequest1 = 115U, /**< GPIO3 Pin event request 1 */ + kDma0RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma1RequestMuxGpio4PinEventRequest0 = 116U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma1RequestMuxGpio4PinEventRequest1 = 117U, /**< GPIO4 Pin event request 1 */ + kDma0RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma1RequestMuxGpio5PinEventRequest0 = 118U, /**< GPIO5 Pin event request 0 */ + kDma0RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ + kDma1RequestMuxGpio5PinEventRequest1 = 119U, /**< GPIO5 Pin event request 1 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[92]; + __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_4[48]; + __IO uint32_t FCTRL[2]; /**< FIFO Control Register, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_5[8]; + __I uint32_t GCC[2]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + __IO uint32_t GCR[2]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[15]; + uint8_t RESERVED_6[136]; + __IO uint32_t CV[15]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_7[196]; + __I uint32_t RESFIFO[2]; /**< Data Result FIFO Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[248]; + __IO uint32_t CAL_GAR0; /**< Calibration General A-Side Registers, offset: 0x400 */ + __IO uint32_t CAL_GAR1; /**< Calibration General A-Side Registers, offset: 0x404 */ + __IO uint32_t CAL_GAR2; /**< Calibration General A-Side Registers, offset: 0x408 */ + __IO uint32_t CAL_GAR3; /**< Calibration General A-Side Registers, offset: 0x40C */ + __IO uint32_t CAL_GAR4; /**< Calibration General A-Side Registers, offset: 0x410 */ + __IO uint32_t CAL_GAR5; /**< Calibration General A-Side Registers, offset: 0x414 */ + __IO uint32_t CAL_GAR6; /**< Calibration General A-Side Registers, offset: 0x418 */ + __IO uint32_t CAL_GAR7; /**< Calibration General A-Side Registers, offset: 0x41C */ + __IO uint32_t CAL_GAR8; /**< Calibration General A-Side Registers, offset: 0x420 */ + __IO uint32_t CAL_GAR9; /**< Calibration General A-Side Registers, offset: 0x424 */ + __IO uint32_t CAL_GAR10; /**< Calibration General A-Side Registers, offset: 0x428 */ + __IO uint32_t CAL_GAR11; /**< Calibration General A-Side Registers, offset: 0x42C */ + __IO uint32_t CAL_GAR12; /**< Calibration General A-Side Registers, offset: 0x430 */ + __IO uint32_t CAL_GAR13; /**< Calibration General A-Side Registers, offset: 0x434 */ + __IO uint32_t CAL_GAR14; /**< Calibration General A-Side Registers, offset: 0x438 */ + __IO uint32_t CAL_GAR15; /**< Calibration General A-Side Registers, offset: 0x43C */ + __IO uint32_t CAL_GAR16; /**< Calibration General A-Side Registers, offset: 0x440 */ + __IO uint32_t CAL_GAR17; /**< Calibration General A-Side Registers, offset: 0x444 */ + __IO uint32_t CAL_GAR18; /**< Calibration General A-Side Registers, offset: 0x448 */ + __IO uint32_t CAL_GAR19; /**< Calibration General A-Side Registers, offset: 0x44C */ + __IO uint32_t CAL_GAR20; /**< Calibration General A-Side Registers, offset: 0x450 */ + __IO uint32_t CAL_GAR21; /**< Calibration General A-Side Registers, offset: 0x454 */ + __IO uint32_t CAL_GAR22; /**< Calibration General A-Side Registers, offset: 0x458 */ + __IO uint32_t CAL_GAR23; /**< Calibration General A-Side Registers, offset: 0x45C */ + __IO uint32_t CAL_GAR24; /**< Calibration General A-Side Registers, offset: 0x460 */ + __IO uint32_t CAL_GAR25; /**< Calibration General A-Side Registers, offset: 0x464 */ + __IO uint32_t CAL_GAR26; /**< Calibration General A-Side Registers, offset: 0x468 */ + __IO uint32_t CAL_GAR27; /**< Calibration General A-Side Registers, offset: 0x46C */ + __IO uint32_t CAL_GAR28; /**< Calibration General A-Side Registers, offset: 0x470 */ + __IO uint32_t CAL_GAR29; /**< Calibration General A-Side Registers, offset: 0x474 */ + __IO uint32_t CAL_GAR30; /**< Calibration General A-Side Registers, offset: 0x478 */ + __IO uint32_t CAL_GAR31; /**< Calibration General A-Side Registers, offset: 0x47C */ + __IO uint32_t CAL_GAR32; /**< Calibration General A-Side Registers, offset: 0x480 */ + uint8_t RESERVED_9[124]; + __IO uint32_t CAL_GBR0; /**< Calibration General B-Side Registers, offset: 0x500 */ + __IO uint32_t CAL_GBR1; /**< Calibration General B-Side Registers, offset: 0x504 */ + __IO uint32_t CAL_GBR2; /**< Calibration General B-Side Registers, offset: 0x508 */ + __IO uint32_t CAL_GBR3; /**< Calibration General B-Side Registers, offset: 0x50C */ + __IO uint32_t CAL_GBR4; /**< Calibration General B-Side Registers, offset: 0x510 */ + __IO uint32_t CAL_GBR5; /**< Calibration General B-Side Registers, offset: 0x514 */ + __IO uint32_t CAL_GBR6; /**< Calibration General B-Side Registers, offset: 0x518 */ + __IO uint32_t CAL_GBR7; /**< Calibration General B-Side Registers, offset: 0x51C */ + __IO uint32_t CAL_GBR8; /**< Calibration General B-Side Registers, offset: 0x520 */ + __IO uint32_t CAL_GBR9; /**< Calibration General B-Side Registers, offset: 0x524 */ + __IO uint32_t CAL_GBR10; /**< Calibration General B-Side Registers, offset: 0x528 */ + __IO uint32_t CAL_GBR11; /**< Calibration General B-Side Registers, offset: 0x52C */ + __IO uint32_t CAL_GBR12; /**< Calibration General B-Side Registers, offset: 0x530 */ + __IO uint32_t CAL_GBR13; /**< Calibration General B-Side Registers, offset: 0x534 */ + __IO uint32_t CAL_GBR14; /**< Calibration General B-Side Registers, offset: 0x538 */ + __IO uint32_t CAL_GBR15; /**< Calibration General B-Side Registers, offset: 0x53C */ + __IO uint32_t CAL_GBR16; /**< Calibration General B-Side Registers, offset: 0x540 */ + __IO uint32_t CAL_GBR17; /**< Calibration General B-Side Registers, offset: 0x544 */ + __IO uint32_t CAL_GBR18; /**< Calibration General B-Side Registers, offset: 0x548 */ + __IO uint32_t CAL_GBR19; /**< Calibration General B-Side Registers, offset: 0x54C */ + __IO uint32_t CAL_GBR20; /**< Calibration General B-Side Registers, offset: 0x550 */ + __IO uint32_t CAL_GBR21; /**< Calibration General B-Side Registers, offset: 0x554 */ + __IO uint32_t CAL_GBR22; /**< Calibration General B-Side Registers, offset: 0x558 */ + __IO uint32_t CAL_GBR23; /**< Calibration General B-Side Registers, offset: 0x55C */ + __IO uint32_t CAL_GBR24; /**< Calibration General B-Side Registers, offset: 0x560 */ + __IO uint32_t CAL_GBR25; /**< Calibration General B-Side Registers, offset: 0x564 */ + __IO uint32_t CAL_GBR26; /**< Calibration General B-Side Registers, offset: 0x568 */ + __IO uint32_t CAL_GBR27; /**< Calibration General B-Side Registers, offset: 0x56C */ + __IO uint32_t CAL_GBR28; /**< Calibration General B-Side Registers, offset: 0x570 */ + __IO uint32_t CAL_GBR29; /**< Calibration General B-Side Registers, offset: 0x574 */ + __IO uint32_t CAL_GBR30; /**< Calibration General B-Side Registers, offset: 0x578 */ + __IO uint32_t CAL_GBR31; /**< Calibration General B-Side Registers, offset: 0x57C */ + __IO uint32_t CAL_GBR32; /**< Calibration General B-Side Registers, offset: 0x580 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 13-bit differential or 12-bit single-ended resolution supported. + * 0b1..Up to 16-bit differential or 16-bit single-ended resolution supported. CMDLn[MODE] available for + * selecting the resolution of conversions for the associated command. + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Not supported + * 0b1..Supported. CMDLn[CTYPE] controls fields implemented. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multiple Vref Implemented + * 0b0..Single VREFH input supported. + * 0b1..Multiple VREFH inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Not supported. + * 0b001..Supported with one-bit CSCALE control field. + * 0b110..Supported with six-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. + * 0b1..Range control required. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock Implemented + * 0b0..Not implemented + * 0b1..Implemented + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Not implemented + * 0b1..Implemented + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single-Ended Outputs Supported + * 0b0..One + * 0b1..Two + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..One + * 0b010..Two + * 0b011..Three + * 0b100..Four + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..2 + * 0b00000100..4 + * 0b00001000..8 + * 0b00010000..16 + * 0b00100000..32 + * 0b01000000..64 + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in low-power mode. + * 0b1..ADC is disabled in low-power mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request made. + * 0b1..Request has been made. + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Offset Calibration Request + * 0b0..Calibration function disabled + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_RSTFIFO1_MASK (0x200U) +#define ADC_CTRL_RSTFIFO1_SHIFT (9U) +/*! RSTFIFO1 - Reset FIFO 1 + * 0b0..No effect. + * 0b1..FIFO 1 is reset. + */ +#define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0xF0000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Not above watermark + * 0b1..Above watermark + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time that the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time that the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_RDY1_MASK (0x4U) +#define ADC_STAT_RDY1_SHIFT (2U) +/*! RDY1 - Result FIFO1 Ready Flag + * 0b0..Not above watermark + * 0b1..Above watermark + */ +#define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + +#define ADC_STAT_FOF1_MASK (0x8U) +#define ADC_STAT_FOF1_SHIFT (3U) +/*! FOF1 - Result FIFO1 Overflow Flag + * 0b0..No result FIFO1 overflow has occurred since the last time that the flag was cleared. + * 0b1..At least one result FIFO1 overflow has occurred since the last time that the flag was cleared. + */ +#define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High-Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgment. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] = 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or has not been run. + * 0b1..ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..ADC is idle. There are no pending triggers to service and no active commands are being processed. + * 0b1..ADC is processing a conversion, running through the power-up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0x30000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b00..Command (sequence) associated with Trigger 0 currently being executed. + * 0b01..Command (sequence) associated with Trigger 1 currently being executed. + * 0b10..Command (sequence) associated with Trigger 2 currently being executed. + * 0b11..Command (sequence) associated with Trigger 3 currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0xF000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b0000..No command currently in progress. + * 0b0001..Command 1 currently being executed. + * 0b0010..Command 2 currently being executed. + * 0b0011-0b1111..Associated command number currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_FWMIE1_MASK (0x4U) +#define ADC_IE_FWMIE1_SHIFT (2U) +/*! FWMIE1 - FIFO1 Watermark Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + +#define ADC_IE_FOFIE1_MASK (0x8U) +#define ADC_IE_FOFIE1_SHIFT (3U) +/*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000..All disabled + * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0011-0b1110..Associated trigger completion interrupts are enabled. + * 0b1111..All enabled + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + +#define ADC_DE_FWMDE1_MASK (0x2U) +#define ADC_DE_FWMDE1_SHIFT (1U) +/*! FWMDE1 - FIFO1 Watermark DMA Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_DE_FWMDE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE1_SHIFT)) & ADC_DE_FWMDE1_MASK) +/*! @} */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC Trigger Priority Control + * 0b00..Current conversion is aborted and the new command specified by the trigger is started. + * 0b01..Current command is stopped after completing the current conversion. If averaging is enabled, the + * averaging loop is completed. CMDHn[LOOP] is ignored and the higher-priority trigger is serviced. + * 0b10..Current command is completed (averaging, looping, compare) before servicing the higher-priority trigger. + * 0b11.. + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x30U) +#define ADC_CFG_PWRSEL_SHIFT (4U) +/*! PWRSEL - Power Configuration Select + * 0b0x..Low power + * 0b1x..High power + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Option 1 + * 0b01..Option 2 + * 0b10..Option 3 + * 0b11.. + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Not automatically resumed or restarted + * 0b1..Automatically resumed or restarted + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequence automatically restarted. + * 0b1..Trigger sequence resumed from the command that was executed prior to the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High-Priority Trigger Exception Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power-up Delay */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Analog startup delays affect performance. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays, at the cost + * of higher DC current consumption. A single power-up delay (CFG[PUDLY]) is executed immediately once PWREN + * is set. No detected triggers begin ADC operation until the power-up delay time has passed. After this + * initial delay expires, the analog circuits remain pre-enabled, and no additional delays are executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - Pause Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software Trigger 0 + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software Trigger 1 + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software Trigger 2 + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software Trigger 3 + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000..No triggers have been interrupted by a high-priority exception. + * 0b0001..Trigger 0 has been interrupted by a high-priority exception. + * 0b0010..Trigger 1 has been interrupted by a high-priority exception. + * 0b0011-0b1110..Associated trigger sequence has interrupted by a high-priority exception. + * 0b1111..Every trigger sequence has been interrupted by a high-priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts. + * 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts. + * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) +#define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + +#define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) +#define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) +#define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) +/*! FIFO_SEL_A - SAR Result Destination for Channel A + * 0b0..FIFO 0 + * 0b1..FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + +#define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) +#define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) +/*! FIFO_SEL_B - SAR Result Destination for Channel B + * 0b0..FIFO 0 + * 0b1..FIFO 1 + */ +#define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + +#define ADC_TCTRL_TPRI_MASK (0x300U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger Priority Setting + * 0b00..Highest priority, Level 1 + * 0b01-0b10..Set to corresponding priority level. + * 0b11..Lowest priority, Level 4 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + * 0b0..Disable + * 0b1..Enable + */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger Delay Select */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TCMD_MASK (0xF000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger Command Select + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..CMD1 + * 0b0010-0b1110..Corresponding CMD is executed + * 0b1111..CMD15 + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (4U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0x1FU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO Counter */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0xF0000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark Level Selection */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/* The count of ADC_FCTRL */ +#define ADC_FCTRL_COUNT (2U) + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..Invalid + * 0b1..Valid + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (2U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0xFFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..Invalid + * 0b1..Valid + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (2U) + +/*! @name CMDL - Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b00000..CH0A or CH0B or CH0A/CH0B pair. + * 0b00001..CH1A or CH1B or CH1A/CH1B pair. + * 0b00010..CH2A or CH2B or CH2A/CH2B pair. + * 0b00011..CH3A or CH3B or CH3A/CH3B pair. + * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. + * 0b11110..CH30A or CH30B or CH30A/CH30B pair. + * 0b11111..CH31A or CH31B or CH31A/CH31B pair. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended mode. Only A-side channel is converted. + * 0b01..Single-Ended mode. Only B-side channel is converted. + * 0b10..Differential mode. A-B. + * 0b11..Dual-Single-Ended mode. Both A-side and B-side channels are converted independently. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select Resolution of Conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion; differential 13-bit conversion with 2's complement output. + * 0b1..High resolution. Single-ended 16-bit conversion; differential 16-bit conversion with 2's complement output. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) + +#define ADC_CMDL_ALTB_ADCH_MASK (0x1F0000U) +#define ADC_CMDL_ALTB_ADCH_SHIFT (16U) +/*! ALTB_ADCH - Alternate Channel B Input Channel Select + * 0b00000..Select CH0B + * 0b00001..Select CH1B + * 0b00010..Select CH2B + * 0b00011..Select CH3B + * 0b00100-0b11101..Select corresponding channel CHnB + * 0b11110..Select CH30B + * 0b11111..Select CH31B + */ +#define ADC_CMDL_ALTB_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTB_ADCH_SHIFT)) & ADC_CMDL_ALTB_ADCH_MASK) + +#define ADC_CMDL_ALTBEN_MASK (0x200000U) +#define ADC_CMDL_ALTBEN_SHIFT (21U) +/*! ALTBEN - Alternate Channel B Select Enable + * 0b0..ALTBEN_ADCH disabled. Channel-A and Channel-B inputs are selected based on ADCH settings. + * 0b1..ALTBEN_ADCH enabled. Channel-A inputs are selected by ADCH setting and Channel-B inputs are selected by ALTB_ADCH setting. + */ +#define ADC_CMDL_ALTBEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ALTBEN_SHIFT)) & ADC_CMDL_ALTBEN_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (15U) + +/*! @name CMDH - Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Disabled + * 0b01.. + * 0b10..Enabled. Store on true. + * 0b11..Enabled. Repeat channel acquisition (sample, convert, and compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for Trigger Assertion Before Execution + * 0b0..Command executes automatically. + * 0b1..Active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Disabled + * 0b1..Enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3.5 ADCK cycles. + * 0b001..5.5 ADCK cycles + * 0b010..7.5 ADCK cycles + * 0b011..11.5 ADCK cycles + * 0b100..19.5 ADCK cycles + * 0b101..35.5 ADCK cycles + * 0b110..67.5 ADCK cycles + * 0b111..131.5 ADCK cycles + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0xF000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b0000..Single conversion + * 0b0001..2 + * 0b0010..4 + * 0b0011..8 + * 0b0100..16 + * 0b0101..32 + * 0b0110..64 + * 0b0111..128 + * 0b1000..256 + * 0b1001..512 + * 0b1010..1024 + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes one time. + * 0b0001..Loop one time. Command executes two times. + * 0b0010..Loop two times. Command executes three times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP + 1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0xF000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b0001..CMD1 + * 0b0010-0b1110..Select corresponding CMD command buffer register as next command + * 0b1111..CMD15 + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (15U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (15U) + +/*! @name RESFIFO - Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data Result */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0x30000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b00..Trigger source 0 + * 0b01..Trigger source 1 + * 0b10..Trigger source 2 + * 0b11..Trigger source 3 + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop Count Value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from (LOOPCNT + 1) conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b0000..Not a valid value CMDSRC value for a data word in RESFIFO. 0h is only found in the initial FIFO state, + * prior to the storage of an ADC conversion result into a RESFIFO buffer. + * 0b0001..CMD1 + * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. + * 0b1111..CMD15 + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO Entry is Valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO contains data. FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/* The count of ADC_RESFIFO */ +#define ADC_RESFIFO_COUNT (2U) + +/*! @name CAL_GAR0 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR0_CAL_GAR_VAL_MASK (0x7FFU) +#define ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR0_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR0_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR1 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR1_CAL_GAR_VAL_MASK (0xFFFU) +#define ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR1_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR1_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR2 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR2_CAL_GAR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR2_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR2_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR3 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR3_CAL_GAR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR3_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR3_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR4 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR4_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR4_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR4_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR5 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR5_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR5_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR5_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR6 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR6_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR6_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR6_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR7 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR7_CAL_GAR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR7_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR7_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR8 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR8_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR8_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR8_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR9 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR9_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR9_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR9_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR10 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR10_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR10_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR10_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR11 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR11_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR11_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR11_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR12 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR12_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR12_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR12_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR13 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR13_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR13_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR13_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR14 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR14_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR14_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR14_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR15 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR15_CAL_GAR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR15_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR15_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR16 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR16_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR16_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR16_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR17 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR17_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR17_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR17_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR18 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR18_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR18_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR18_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR19 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR19_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR19_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR19_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR20 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR20_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR20_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR20_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR21 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR21_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR21_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR21_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR22 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR22_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR22_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR22_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR23 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR23_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR23_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR23_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR24 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR24_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR24_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR24_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR25 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR25_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR25_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR25_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR26 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR26_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR26_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR26_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR27 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR27_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR27_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR27_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR28 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR28_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR28_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR28_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR29 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR29_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR29_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR29_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR30 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR30_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR30_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR30_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR31 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR31_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR31_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR31_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR32 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR32_CAL_GAR_VAL_MASK (0x7FFU) +#define ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR32_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR32_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR0 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR0_CAL_GBR_VAL_MASK (0x7FFU) +#define ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR0_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR0_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR0_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR1 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR1_CAL_GBR_VAL_MASK (0xFFFU) +#define ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR1_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR1_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR1_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR2 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR2_CAL_GBR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR2_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR2_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR2_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR3 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR3_CAL_GBR_VAL_MASK (0x1FFFU) +#define ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR3_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR3_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR3_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR4 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR4_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR4_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR4_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR4_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR5 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR5_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR5_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR5_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR5_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR6 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR6_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR6_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR6_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR6_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR7 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR7_CAL_GBR_VAL_MASK (0x3FFFU) +#define ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR7_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR7_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR7_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR8 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR8_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR8_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR8_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR8_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR9 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR9_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR9_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR9_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR9_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR10 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR10_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR10_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR10_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR10_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR11 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR11_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR11_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR11_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR11_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR12 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR12_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR12_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR12_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR12_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR13 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR13_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR13_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR13_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR13_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR14 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR14_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR14_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR14_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR14_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR15 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR15_CAL_GBR_VAL_MASK (0x7FFFU) +#define ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR15_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR15_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR15_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR16 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR16_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR16_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR16_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR16_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR17 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR17_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR17_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR17_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR17_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR18 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR18_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR18_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR18_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR18_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR19 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR19_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR19_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR19_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR19_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR20 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR20_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR20_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR20_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR20_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR21 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR21_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR21_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR21_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR21_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR22 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR22_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR22_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR22_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR22_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR23 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR23_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR23_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR23_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR23_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR24 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR24_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR24_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR24_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR24_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR25 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR25_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR25_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR25_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR25_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR26 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR26_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR26_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR26_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR26_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR27 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR27_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR27_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR27_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR27_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR28 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR28_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR28_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR28_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR28_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR29 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR29_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR29_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR29_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR29_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR30 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR30_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR30_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR30_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR30_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR31 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR31_CAL_GBR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR31_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR31_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR31_CAL_GBR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GBR32 - Calibration General B-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GBR32_CAL_GBR_VAL_MASK (0x7FFU) +#define ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element */ +#define ADC_CAL_GBR32_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR32_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR32_CAL_GBR_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x5010D000u) + /** Peripheral ADC0 base address */ + #define ADC0_BASE_NS (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC0 base pointer */ + #define ADC0_NS ((ADC_Type *)ADC0_BASE_NS) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x5010E000u) + /** Peripheral ADC1 base address */ + #define ADC1_BASE_NS (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Peripheral ADC1 base pointer */ + #define ADC1_NS ((ADC_Type *)ADC1_BASE_NS) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS_NS { ADC0_BASE_NS, ADC1_BASE_NS } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS_NS { ADC0_NS, ADC1_NS } +#else + /** Peripheral ADC0 base address */ + #define ADC0_BASE (0x4010D000u) + /** Peripheral ADC0 base pointer */ + #define ADC0 ((ADC_Type *)ADC0_BASE) + /** Peripheral ADC1 base address */ + #define ADC1_BASE (0x4010E000u) + /** Peripheral ADC1 base pointer */ + #define ADC1 ((ADC_Type *)ADC1_BASE) + /** Array initializer of ADC peripheral base addresses */ + #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } + /** Array initializer of ADC peripheral base pointers */ + #define ADC_BASE_PTRS { ADC0, ADC1 } +#endif +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AHBSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHBSC_Peripheral_Access_Layer AHBSC Peripheral Access Layer + * @{ + */ + +/** AHBSC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t FLASH00_MEM_RULE[4]; /**< Flash Memory Rule, array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t FLASH02_MEM_RULE; /**< Flash Memory Rule, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t FLASH03_MEM_RULE; /**< Flash Memory Rule, offset: 0x40 */ + uint8_t RESERVED_3[28]; + __IO uint32_t ROM_MEM_RULE[4]; /**< ROM Memory Rule, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RAMX_MEM_RULE[3]; /**< RAMX Memory Rule, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_5[20]; + __IO uint32_t RAMA_MEM_RULE; /**< RAMA Memory Rule 0, offset: 0xA0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RAMB_MEM_RULE; /**< RAMB Memory Rule, offset: 0xC0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t RAMC_MEM_RULE[2]; /**< RAMC Memory Rule, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_8[24]; + __IO uint32_t RAMD_MEM_RULE[2]; /**< RAMD Memory Rule, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_9[24]; + __IO uint32_t RAME_MEM_RULE[2]; /**< RAME Memory Rule, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE0; /**< APB Bridge Group 0 Memory Rule 0, offset: 0x1A0 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE1; /**< APB Bridge Group 0 Memory Rule 1, offset: 0x1A4 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE2; /**< APB Bridge Group 0 Rule 2, offset: 0x1A8 */ + __IO uint32_t APB_PERIPHERAL_GROUP0_MEM_RULE3; /**< APB Bridge Group 0 Memory Rule 3, offset: 0x1AC */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE0; /**< APB Bridge Group 1 Memory Rule 0, offset: 0x1B0 */ + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE1; /**< APB Bridge Group 1 Memory Rule 1, offset: 0x1B4 */ + uint8_t RESERVED_11[4]; + __IO uint32_t APB_PERIPHERAL_GROUP1_MEM_RULE2; /**< APB Bridge Group 1 Memory Rule 2, offset: 0x1BC */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE0; /**< AIPS Bridge Group 0 Memory Rule 0, offset: 0x1C0 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE1; /**< AIPS Bridge Group 0 Memory Rule 1, offset: 0x1C4 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE2; /**< AIPS Bridge Group 0 Memory Rule 2, offset: 0x1C8 */ + __IO uint32_t AIPS_BRIDGE_GROUP0_MEM_RULE3; /**< AIPS Bridge Group 0 Memory Rule 3, offset: 0x1CC */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 0, offset: 0x1D0 */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 1, offset: 0x1D4 */ + __IO uint32_t AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2; /**< AHB Peripheral 0 Slave Port 12 Slave Rule 2, offset: 0x1D8 */ + uint8_t RESERVED_12[4]; + __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE0; /**< AIPS Bridge Group 1 Rule 0, offset: 0x1E0 */ + __IO uint32_t AIPS_BRIDGE_GROUP1_MEM_RULE1; /**< AIPS Bridge Group 1 Rule 1, offset: 0x1E4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 0, offset: 0x1F0 */ + __IO uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 1, offset: 0x1F4 */ + uint32_t AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE2; /**< AHB Peripheral 1 Slave Port 13 Slave Rule 2, offset: 0x1F8 */ + uint8_t RESERVED_14[4]; + __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE0; /**< AIPS Bridge Group 2 Rule 0, offset: 0x200 */ + __IO uint32_t AIPS_BRIDGE_GROUP2_MEM_RULE1; /**< AIPS Bridge Group 2 Memory Rule 1, offset: 0x204 */ + uint8_t RESERVED_15[24]; + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE0; /**< AIPS Bridge Group 3 Rule 0, offset: 0x220 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE1; /**< AIPS Bridge Group 3 Memory Rule 1, offset: 0x224 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE2; /**< AIPS Bridge Group 3 Rule 2, offset: 0x228 */ + __IO uint32_t AIPS_BRIDGE_GROUP3_MEM_RULE3; /**< AIPS Bridge Group 3 Rule 3, offset: 0x22C */ + uint8_t RESERVED_16[16]; + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE0; /**< AIPS Bridge Group 4 Rule 0, offset: 0x240 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE1; /**< AIPS Bridge Group 4 Rule 1, offset: 0x244 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE2; /**< AIPS Bridge Group 4 Rule 2, offset: 0x248 */ + __IO uint32_t AIPS_BRIDGE_GROUP4_MEM_RULE3; /**< AIPS Bridge Group 4 Rule 3, offset: 0x24C */ + __IO uint32_t AHB_SECURE_CTRL_PERIPHERAL_RULE0; /**< AHB Secure Control Peripheral Rule 0, offset: 0x250 */ + uint8_t RESERVED_17[2988]; + __I uint32_t SEC_VIO_ADDR[32]; /**< Security Violation Address, array offset: 0xE00, array step: 0x4 */ + __I uint32_t SEC_VIO_MISC_INFO[32]; /**< Security Violation Miscellaneous Information at Address, array offset: 0xE80, array step: 0x4 */ + __IO uint32_t SEC_VIO_INFO_VALID; /**< Security Violation Info Validity for Address, offset: 0xF00 */ + uint8_t RESERVED_18[124]; + __IO uint32_t SEC_GPIO_MASK[2]; /**< GPIO Mask for Port 0..GPIO Mask for Port 1, array offset: 0xF80, array step: 0x4 */ + uint8_t RESERVED_19[72]; + __IO uint32_t MASTER_SEC_LEVEL; /**< Master Secure Level, offset: 0xFD0 */ + __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< Master Secure Level, offset: 0xFD4 */ + uint8_t RESERVED_20[20]; + __IO uint32_t CPU0_LOCK_REG; /**< Miscellaneous CPU0 Control Signals, offset: 0xFEC */ + uint8_t RESERVED_21[8]; + __IO uint32_t MISC_CTRL_DP_REG; /**< Secure Control Duplicate, offset: 0xFF8 */ + __IO uint32_t MISC_CTRL_REG; /**< Secure Control, offset: 0xFFC */ +} AHBSC_Type; + +/* ---------------------------------------------------------------------------- + -- AHBSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AHBSC_Register_Masks AHBSC Register Masks + * @{ + */ + +/*! @name FLASH00_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH00_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE3_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE4_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE5_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE6_MASK) + +#define AHBSC_FLASH00_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH00_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH00_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH00_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_FLASH00_MEM_RULE */ +#define AHBSC_FLASH00_MEM_RULE_COUNT (4U) + +/*! @name FLASH02_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH02_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH02_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH02_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH02_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH02_MEM_RULE_RULE3_MASK) +/*! @} */ + +/*! @name FLASH03_MEM_RULE - Flash Memory Rule */ +/*! @{ */ + +#define AHBSC_FLASH03_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE0_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE0_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE1_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE1_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE2_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE2_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE3_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE3_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE4_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE4_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE5_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE5_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE6_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE6_MASK) + +#define AHBSC_FLASH03_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_FLASH03_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_FLASH03_MEM_RULE_RULE7_SHIFT)) & AHBSC_FLASH03_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name ROM_MEM_RULE - ROM Memory Rule */ +/*! @{ */ + +#define AHBSC_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_ROM_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE0_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE0_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_ROM_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE1_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE1_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_ROM_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE2_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE2_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_ROM_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE3_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE3_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_ROM_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE4_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE4_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_ROM_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE5_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE5_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_ROM_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE6_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE6_MASK) + +#define AHBSC_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_ROM_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_ROM_MEM_RULE_RULE7_SHIFT)) & AHBSC_ROM_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_ROM_MEM_RULE */ +#define AHBSC_ROM_MEM_RULE_COUNT (4U) + +/*! @name RAMX_MEM_RULE0_RAMX_MEM_RULE - RAMX Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE */ +#define AHBSC_RAMX_MEM_RULE0_RAMX_MEM_RULE_COUNT (3U) + +/*! @name RAMA_MEM_RULE - RAMA Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_RAMA_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMA_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMA_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMA_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMA_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMA_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMA_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMA_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMA_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMA_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMA_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMA_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMA_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name RAMB_MEM_RULE - RAMB Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMB_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMB_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMB_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMB_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMB_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMB_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMB_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMB_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMB_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMB_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMB_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMB_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMB_MEM_RULE_RULE7_MASK) +/*! @} */ + +/*! @name RAMC_MEM_RULE - RAMC Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMC_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMC_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMC_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMC_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMC_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMC_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMC_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMC_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMC_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMC_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMC_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMC_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMC_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMC_MEM_RULE */ +#define AHBSC_RAMC_MEM_RULE_COUNT (2U) + +/*! @name RAMD_MEM_RULE - RAMD Memory Rule */ +/*! @{ */ + +#define AHBSC_RAMD_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAMD_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAMD_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAMD_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAMD_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAMD_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAMD_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAMD_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAMD_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAMD_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAMD_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAMD_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAMD_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAMD_MEM_RULE */ +#define AHBSC_RAMD_MEM_RULE_COUNT (2U) + +/*! @name RAME_MEM_RULE - RAME Memory Rule */ +/*! @{ */ + +#define AHBSC_RAME_MEM_RULE_RULE0_MASK (0x3U) +#define AHBSC_RAME_MEM_RULE_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE0_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE0_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE1_MASK (0x30U) +#define AHBSC_RAME_MEM_RULE_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE1_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE1_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE2_MASK (0x300U) +#define AHBSC_RAME_MEM_RULE_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE2_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE2_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE3_MASK (0x3000U) +#define AHBSC_RAME_MEM_RULE_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE3_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE3_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE4_MASK (0x30000U) +#define AHBSC_RAME_MEM_RULE_RULE4_SHIFT (16U) +/*! RULE4 - Rule 4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE4_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE4_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE5_MASK (0x300000U) +#define AHBSC_RAME_MEM_RULE_RULE5_SHIFT (20U) +/*! RULE5 - Rule 5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE5_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE5_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHBSC_RAME_MEM_RULE_RULE6_SHIFT (24U) +/*! RULE6 - Rule 6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE6_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE6_MASK) + +#define AHBSC_RAME_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHBSC_RAME_MEM_RULE_RULE7_SHIFT (28U) +/*! RULE7 - Rule 7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_RAME_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_RAME_MEM_RULE_RULE7_SHIFT)) & AHBSC_RAME_MEM_RULE_RULE7_MASK) +/*! @} */ + +/* The count of AHBSC_RAME_MEM_RULE */ +#define AHBSC_RAME_MEM_RULE_COUNT (2U) + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE0 - APB Bridge Group 0 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK (0x3U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT (0U) +/*! SYSCON - SYSCON + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_SYSCON_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT (16U) +/*! PINT0 - PINT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_PINT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT (24U) +/*! INPUTMUX - INPUTMUX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE0_INPUTMUX_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE1 - APB Bridge Group 0 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT (16U) +/*! CTIMER0 - CTIMER0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT (20U) +/*! CTIMER1 - CTIMER1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT (24U) +/*! CTIMER2 - CTIMER2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER2_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT (28U) +/*! CTIMER3 - CTIMER3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE1_CTIMER3_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE2 - APB Bridge Group 0 Rule 2 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK (0x3U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT (0U) +/*! CTIMER4 - CTIMER4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_CTIMER4_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK (0x30U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT (4U) +/*! FREQME0 - FREQME0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_FREQME0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT (8U) +/*! UTCIK0 - UTCIK0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_UTCIK0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT (12U) +/*! MRT0 - MRT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_MRT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT (16U) +/*! OSTIMER0 - OSTIMER0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_OSTIMER0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT (24U) +/*! WWDT0 - WWDT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT (28U) +/*! WWDT1 - WWDT1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE2_WWDT1_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP0_MEM_RULE3 - APB Bridge Group 0 Memory Rule 3 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT (12U) +/*! CACHE64_POLSEL0 - CACHE64_POLSEL0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP0_MEM_RULE3_CACHE64_POLSEL0_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE0 - APB Bridge Group 1 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK (0x30U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT (4U) +/*! I3C0 - I3C0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT (8U) +/*! I3C1 - I3C1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_I3C1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT (20U) +/*! GDET - GDET + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_GDET_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT (24U) +/*! ITRC - ITRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE0_ITRC_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE1 - APB Bridge Group 1 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT (12U) +/*! PKC - PKC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PKC_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT (16U) +/*! PUF_ALIAS0 - PUF_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS0_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK (0x300000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT (20U) +/*! PUF_ALIAS1 - PUF_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS1_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK (0x3000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT (24U) +/*! PUF_ALIAS2 - PUF_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS2_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK (0x30000000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT (28U) +/*! PUF_ALIAS3 - PUF_ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE1_PUF_ALIAS3_MASK) +/*! @} */ + +/*! @name APB_PERIPHERAL_GROUP1_MEM_RULE2 - APB Bridge Group 1 Memory Rule 2 */ +/*! @{ */ + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK (0x300U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT (8U) +/*! COOLFLUX - COOLFLUX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_COOLFLUX_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK (0x3000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT (12U) +/*! SMARTDMA - SmartDMA + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_SMARTDMA_MASK) + +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK (0x30000U) +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT (16U) +/*! PLU - PLU + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_SHIFT)) & AHBSC_APB_PERIPHERAL_GROUP1_MEM_RULE2_PLU_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE0 - AIPS Bridge Group 0 Memory Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT (0U) +/*! GPIO5_ALIAS0 - GPIO5_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT (4U) +/*! GPIO5_ALIAS1 - GPIO5_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_GPIO5_ALIAS1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT (8U) +/*! PORT5 - PORT5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_PORT5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT (12U) +/*! FMU0 - FMU0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_FMU0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT (16U) +/*! SCG0 - SCG0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SCG0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT (20U) +/*! SPC0 - SPC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_SPC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT (24U) +/*! WUU0 - WUU0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE0_WUU0_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE1 - AIPS Bridge Group 0 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT (8U) +/*! LPTMR0 - LPTMR0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT (12U) +/*! LPTMR1 - LPTMR1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_LPTMR1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT (16U) +/*! RTC - RTC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_RTC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT (24U) +/*! FMU_TEST - FMU_TEST + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE1_FMU_TEST_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE2 - AIPS Bridge Group 0 Memory Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT (0U) +/*! TSI - TSI + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_TSI_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT (4U) +/*! CMP0 - CMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT (8U) +/*! CMP1 - CMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT (12U) +/*! CMP2 - CMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_CMP2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT (16U) +/*! ELS - ELS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT (20U) +/*! ELS_ALIAS1 - ELS_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT (24U) +/*! ELS_ALIAS2 - ELS_ALIAS2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT (28U) +/*! ELS_ALIAS3 - ELS_ALIAS3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE2_ELS_ALIAS3_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP0_MEM_RULE3 - AIPS Bridge Group 0 Memory Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT (0U) +/*! DIGTMP - DIGTMP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_DIGTMP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT (4U) +/*! VBAT - VBAT + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_VBAT_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT (8U) +/*! TRNG - TRNG + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_TRNG_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT (12U) +/*! EIM0 - EIM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_EIM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT (16U) +/*! ERM0 - ERM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_ERM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT (20U) +/*! INTM0 - INTM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP0_MEM_RULE3_INTM0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0 - AHB Peripheral 0 Slave Port 12 Slave Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT (4U) +/*! eDMA0_CH15 - eDMA0_CH15 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_EDMA0_CH15_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT (8U) +/*! SCT0 - SCT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_SCT0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT (12U) +/*! LP_FLEXCOMM0 - LP_FLEXCOMM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT (16U) +/*! LP_FLEXCOMM1 - LP_FLEXCOMM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT (20U) +/*! LP_FLEXCOMM2 - LP_FLEXCOMM2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM2_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT (24U) +/*! LP_FLEXCOMM3 - LP_FLEXCOMM3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_LP_FLEXCOMM3_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT (28U) +/*! GPIO0_ALIAS0 - GPIO0_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE0_GPIO0_ALIAS0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1 - AHB Peripheral 0 Slave Port 12 Slave Rule 1 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT (0U) +/*! GPIO0_ALIAS1 - GPIO0_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO0_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT (4U) +/*! GPIO1_ALIAS0 - GPIO1_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT (8U) +/*! GPIO1_ALIAS1 - GPIO1_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO1_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT (12U) +/*! GPIO2_ALIAS0 - GPIO2_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT (16U) +/*! GPIO2_ALIAS1 - GPIO2_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO2_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT (20U) +/*! GPIO3_ALIAS0 - GPIO3_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS0_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT (24U) +/*! GPIO3_ALIAS1 - GPIO3_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO3_ALIAS1_MASK) + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT (28U) +/*! GPIO4_ALIAS0 - GPIO4_ALIAS0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE1_GPIO4_ALIAS0_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2 - AHB Peripheral 0 Slave Port 12 Slave Rule 2 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT (0U) +/*! GPIO4_ALIAS1 - GPIO4_ALIAS1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_SHIFT)) & AHBSC_AHB_PERIPHERAL0_SLAVE_PORT_P12_SLAVE_RULE2_GPIO4_ALIAS1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_MEM_RULE0 - AIPS Bridge Group 1 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT (0U) +/*! eDMA0_MP - eDMA0_MP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_MP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT (4U) +/*! eDMA0_CH0 - eDMA0_CH0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT (8U) +/*! eDMA0_CH1 - eDMA0_CH1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT (12U) +/*! eDMA0_CH2 - eDMA0_CH2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT (16U) +/*! eDMA0_CH3 - FLEXSPI0 Registers + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT (20U) +/*! eDMA0_CH4 - eDMA0_CH4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT (24U) +/*! eDMA0_CH5 - eDMA0_CH5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT (28U) +/*! eDMA0_CH6 - eDMA0_CH6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE0_EDMA0_CH6_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP1_MEM_RULE1 - AIPS Bridge Group 1 Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT (0U) +/*! eDMA0_CH7 - eDMA0_CH7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH7_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT (4U) +/*! eDMA0_CH8 - eDMA0_CH8 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH8_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT (8U) +/*! eDMA0_CH9 - eDMA0_CH9 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH9_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT (12U) +/*! eDMA0_CH10 - eDMA0_CH10 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH10_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT (16U) +/*! eDMA0_CH11 - FLEXSPI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH11_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT (20U) +/*! eDMA0_CH12 - eDMA0_CH12 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH12_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT (24U) +/*! eDMA0_CH13 - eDMA0_CH13 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH13_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT (28U) +/*! eDMA0_CH14 - eDMA0_CH14 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP1_MEM_RULE1_EDMA0_CH14_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0 - AHB Peripheral 1 Slave Port 13 Slave Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT (4U) +/*! eDMA1_CH15 - eDMA1_CH15 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_EDMA1_CH15_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT (8U) +/*! SEMA42 - SEMA42 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_SEMA42_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT (12U) +/*! MAILBOX - MAILBOX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_MAILBOX_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT (16U) +/*! PKC_RAM - PKC_RAM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_PKC_RAM_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT (20U) +/*! FLEXCOMM4 - FLEXCOMM4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM4_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT (24U) +/*! FLEXCOMM5 - FLEXCOMM5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM5_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT (28U) +/*! FLEXCOMM6 - FLEXCOMM6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE0_FLEXCOMM6_MASK) +/*! @} */ + +/*! @name AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1 - AHB Peripheral 1 Slave Port 13 Slave Rule 1 */ +/*! @{ */ + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK (0x3U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT (0U) +/*! FLEXCOMM7 - FLEXCOMM7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM7_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK (0x30U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT (4U) +/*! FLEXCOMM8 - FLEXCOMM8 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM8_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK (0x300U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT (8U) +/*! FLEXCOMM9 - FLEXCOMM9 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_FLEXCOMM9_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK (0x3000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT (12U) +/*! USB_FS_OTG_RAM - USB FS OTG RAM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_USB_FS_OTG_RAM_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK (0x30000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT (16U) +/*! CDOG0 - CDOG0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG0_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK (0x300000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT (20U) +/*! CDOG1 - CDOG1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_CDOG1_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK (0x3000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT (24U) +/*! DEBUG_MAILBOX - DEBUG_MAILBOX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_DEBUG_MAILBOX_MASK) + +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK (0x30000000U) +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT (28U) +/*! NPU - NPU + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_SHIFT)) & AHBSC_AHB_PERIPHERAL1_SLAVE_PORT_P13_SLAVE_RULE1_NPU_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP2_MEM_RULE0 - AIPS Bridge Group 2 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT (0U) +/*! eDMA1_MP - eDMA1_MP + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_MP_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT (4U) +/*! eDMA1_CH0 - eDMA1_CH0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT (8U) +/*! eDMA1_CH1 - eDMA1_CH1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT (12U) +/*! eDMA1_CH2 - eDMA1_CH2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT (16U) +/*! eDMA1_CH3 - eDMA1_CH3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT (20U) +/*! eDMA1_CH4 - eDMA1_CH4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT (24U) +/*! eDMA1_CH5 - eDMA1_CH5 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH5_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT (28U) +/*! eDMA1_CH6 - eDMA1_CH6 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE0_EDMA1_CH6_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP2_MEM_RULE1 - AIPS Bridge Group 2 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT (0U) +/*! eDMA1_CH7 - eDMA1_CH7 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP2_MEM_RULE1_EDMA1_CH7_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE0 - AIPS Bridge Group 3 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT (0U) +/*! EWM0 - EWM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_EWM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT (4U) +/*! LPCAC - LPCAC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_LPCAC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT (8U) +/*! FLEXSPI_CMX - FLEXSPI_CMX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_FLEXSPI_CMX_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT (20U) +/*! SFA - SFA + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_SFA_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT (28U) +/*! MBC - MBC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE0_MBC_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE1 - AIPS Bridge Group 3 Memory Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT (0U) +/*! FLEXSPI - FLEXSPI + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_FLEXSPI_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT (4U) +/*! OTPC - OTPC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_OTPC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT (12U) +/*! CRC - CRC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_CRC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT (16U) +/*! NPX - NPX + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_NPX_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT (24U) +/*! PWM - PWM + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_PWM_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_SHIFT (28U) +/*! QDC - QDC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE1_QDC_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE2 - AIPS Bridge Group 3 Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT (0U) +/*! PWM1 - PWM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_PWM1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_SHIFT (4U) +/*! QDC1 - QDC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_QDC1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT (8U) +/*! EVTG - EVTG + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_EVTG_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT (16U) +/*! CAN0_RULE0 - CAN0 RULE0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT (20U) +/*! CAN0_RULE1 - CAN0 RULE1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT (24U) +/*! CAN0_RULE2 - CAN0 RULE2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT (28U) +/*! CAN0_RULE3 - CAN0 RULE3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE2_CAN0_RULE3_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP3_MEM_RULE3 - AIPS Bridge Group 3 Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT (0U) +/*! CAN1_RULE0 - CAN1 RULE0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT (4U) +/*! CAN1_RULE1 - CAN1 RULE1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT (8U) +/*! CAN1_RULE2 - CAN1 RULE2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT (12U) +/*! CAN1_RULE3 - CAN1 RULE3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_CAN1_RULE3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT (16U) +/*! USBDCD - USBDCD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBDCD_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT (20U) +/*! USBFS - USBFS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP3_MEM_RULE3_USBFS_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE0 - AIPS Bridge Group 4 Rule 0 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK (0xFU) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT (0U) +/*! ENET - ENET + * 0b0000..Non-secure and non-privilege user access allowed + * 0b0001..Non-secure and privilege access allowed + * 0b0010..Secure and non-privilege user access allowed + * 0b0011..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_ENET_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT (12U) +/*! EMVSIM0 - EMVSIM0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT (16U) +/*! EMVSIM1 - EMVSIM1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_EMVSIM1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT (20U) +/*! FLEXIO - FLEXIO + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_FLEXIO_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT (24U) +/*! SAI0 - SAI0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT (28U) +/*! SAI1 - SAI1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE0_SAI1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE1 - AIPS Bridge Group 4 Rule 1 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT (0U) +/*! SINC0 - SINC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_SINC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT (4U) +/*! uSDHC0 - uSDHC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USDHC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT (8U) +/*! USBHSPHY - USBHSPHY + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHSPHY_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT (12U) +/*! USBHS - USBHS + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_USBHS_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT (16U) +/*! MICD - MICD + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_MICD_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT (20U) +/*! ADC0 - ADC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT (24U) +/*! ADC1 - ADC1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_ADC1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT (28U) +/*! DAC0 - DAC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE1_DAC0_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE2 - AIPS Bridge Group 4 Rule 2 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT (0U) +/*! OPAMP0 - OPAMP0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT (4U) +/*! VREF - VREF + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_VREF_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT (8U) +/*! DAC - DAC + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_DAC_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK (0x3000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT (12U) +/*! OPAMP1 - OPAMP1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP1_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK (0x30000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT (16U) +/*! HPDAC0 - HPDAC0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_HPDAC0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK (0x300000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT (20U) +/*! OPAMP2 - OPAMP2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_OPAMP2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT (24U) +/*! PORT0 - PORT0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT (28U) +/*! PORT1 - PORT1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE2_PORT1_MASK) +/*! @} */ + +/*! @name AIPS_BRIDGE_GROUP4_MEM_RULE3 - AIPS Bridge Group 4 Rule 3 */ +/*! @{ */ + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK (0x3U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT (0U) +/*! PORT2 - PORT2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT2_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK (0x30U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT (4U) +/*! PORT3 - PORT3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT3_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK (0x300U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT (8U) +/*! PORT4 - PORT4 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_PORT4_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK (0x3000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT (24U) +/*! MTR0 - MTR0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_MTR0_MASK) + +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK (0x30000000U) +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT (28U) +/*! ATX0 - ATX0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_SHIFT)) & AHBSC_AIPS_BRIDGE_GROUP4_MEM_RULE3_ATX0_MASK) +/*! @} */ + +/*! @name AHB_SECURE_CTRL_PERIPHERAL_RULE0 - AHB Secure Control Peripheral Rule 0 */ +/*! @{ */ + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK (0x3U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT (0U) +/*! RULE0 - Rule 0 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE0_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK (0x30U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT (4U) +/*! RULE1 - Rule 1 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE1_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK (0x300U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT (8U) +/*! RULE2 - Rule 2 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE2_MASK) + +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK (0x3000U) +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT (12U) +/*! RULE3 - Rule 3 + * 0b00..Non-secure and non-privilege user access allowed + * 0b01..Non-secure and privilege access allowed + * 0b10..Secure and non-privilege user access allowed + * 0b11..Secure and privilege user access allowed + */ +#define AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_SHIFT)) & AHBSC_AHB_SECURE_CTRL_PERIPHERAL_RULE0_RULE3_MASK) +/*! @} */ + +/*! @name SEC_VIO_ADDRN_SEC_VIO_ADDR - Security Violation Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - Security violation address for AHB layer a reset value 0 */ +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR */ +#define AHBSC_SEC_VIO_ADDRN_SEC_VIO_ADDR_COUNT (32U) + +/*! @name SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO - Security Violation Miscellaneous Information at Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) +/*! SEC_VIO_INFO_WRITE - Security violation access read/write indicator + * 0b0..Read access + * 0b1..Write access + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) +/*! SEC_VIO_INFO_DATA_ACCESS - Security Violation Info Data Access + * 0b0..Code + * 0b1..Data + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - Security Violation Info Master Security Level */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0x1F00U) +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) +/*! SEC_VIO_INFO_MASTER - Security violation master number + * 0b00000..M33 Code + * 0b00001..M33 System + * 0b00011..SMARTDMA Instruction + * 0b00101..SMARTDMA Data + * 0b00110..eDMA0 + * 0b00111..eDMA1 + * 0b01000..PKC + * 0b01001..ELS S50 + * 0b01010..PKC M0 + * 0b01011..NPU Operands + * 0b01100..DSP Instruction + * 0b01101..DSPX + * 0b01110..DSPY + * 0b10000..NPU Data + * 0b10010..Ethernet + * 0b10011..USB HS + */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT)) & AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO */ +#define AHBSC_SEC_VIO_MISC_INFON_SEC_VIO_MISC_INFO_COUNT (32U) + +/*! @name SEC_VIO_INFO_VALID - Security Violation Info Validity for Address */ +/*! @{ */ + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) +/*! VIO_INFO_VALID0 - Violation information valid flag for AHB port 0 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) +/*! VIO_INFO_VALID1 - Violation information valid flag for AHB port 1 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) +/*! VIO_INFO_VALID2 - Violation information valid flag for AHB port 2 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) +/*! VIO_INFO_VALID3 - Violation information valid flag for AHB port 3 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) +/*! VIO_INFO_VALID4 - Violation information valid flag for AHB port 4 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) +/*! VIO_INFO_VALID5 - Violation information valid flag for AHB port 5 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) +/*! VIO_INFO_VALID6 - Violation information valid flag for AHB port 6 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) +/*! VIO_INFO_VALID7 - Violation information valid flag for AHB port 7 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) +/*! VIO_INFO_VALID8 - Violation information valid flag for AHB port 8 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) +/*! VIO_INFO_VALID9 - Violation information valid flag for AHB port 9 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) +/*! VIO_INFO_VALID10 - Violation information valid flag for AHB port 10 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) +/*! VIO_INFO_VALID11 - Violation information valid flag for AHB port 11 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK (0x1000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT (12U) +/*! VIO_INFO_VALID12 - Violation information valid flag for AHB port 12 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID12_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK (0x2000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT (13U) +/*! VIO_INFO_VALID13 - Violation information valid flag for AHB port 13 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID13_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK (0x4000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT (14U) +/*! VIO_INFO_VALID14 - Violation information valid flag for AHB port 14 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID14_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK (0x8000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT (15U) +/*! VIO_INFO_VALID15 - Violation information valid flag for AHB port 15 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID15_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK (0x10000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT (16U) +/*! VIO_INFO_VALID16 - Violation information valid flag for AHB port 16 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID16_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK (0x20000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT (17U) +/*! VIO_INFO_VALID17 - Violation information valid flag for AHB port 17 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID17_MASK) + +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK (0x40000U) +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT (18U) +/*! VIO_INFO_VALID18 - Violation information valid flag for AHB port 18 + * 0b0..Not valid + * 0b1..Valid + */ +#define AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_SHIFT)) & AHBSC_SEC_VIO_INFO_VALID_VIO_INFO_VALID18_MASK) +/*! @} */ + +/*! @name SEC_GPIO_MASKN_SEC_GPIO_MASK - GPIO Mask for Port 0..GPIO Mask for Port 1 */ +/*! @{ */ + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK (0x1U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO0_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN0_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK (0x1U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT (0U) +/*! PIO1_PIN0_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN0_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK (0x2U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO0_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN1_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK (0x2U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT (1U) +/*! PIO1_PIN1_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN1_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK (0x4U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO0_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN2_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK (0x4U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT (2U) +/*! PIO1_PIN2_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN2_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK (0x8U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO0_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN3_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK (0x8U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT (3U) +/*! PIO1_PIN3_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN3_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK (0x10U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO0_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN4_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK (0x10U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT (4U) +/*! PIO1_PIN4_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN4_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK (0x20U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO0_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN5_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK (0x20U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT (5U) +/*! PIO1_PIN5_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN5_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK (0x40U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO0_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN6_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK (0x40U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT (6U) +/*! PIO1_PIN6_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN6_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK (0x80U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO0_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN7_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK (0x80U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT (7U) +/*! PIO1_PIN7_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN7_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK (0x100U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO0_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN8_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK (0x100U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT (8U) +/*! PIO1_PIN8_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN8_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK (0x200U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO0_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN9_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK (0x200U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT (9U) +/*! PIO1_PIN9_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN9_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK (0x400U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO0_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN10_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK (0x400U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT (10U) +/*! PIO1_PIN10_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN10_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK (0x800U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO0_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN11_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK (0x800U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT (11U) +/*! PIO1_PIN11_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN11_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK (0x1000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO0_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN12_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK (0x1000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT (12U) +/*! PIO1_PIN12_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN12_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK (0x2000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO0_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN13_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK (0x2000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT (13U) +/*! PIO1_PIN13_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN13_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK (0x4000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO0_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN14_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK (0x4000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT (14U) +/*! PIO1_PIN14_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN14_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK (0x8000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO0_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN15_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK (0x8000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT (15U) +/*! PIO1_PIN15_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN15_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK (0x10000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO0_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN16_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK (0x10000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT (16U) +/*! PIO1_PIN16_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN16_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK (0x20000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO0_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN17_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK (0x20000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT (17U) +/*! PIO1_PIN17_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN17_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK (0x40000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO0_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN18_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK (0x40000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT (18U) +/*! PIO1_PIN18_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN18_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK (0x80000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO0_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN19_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK (0x80000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT (19U) +/*! PIO1_PIN19_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN19_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK (0x100000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO0_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN20_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK (0x100000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT (20U) +/*! PIO1_PIN20_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN20_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK (0x200000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO0_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN21_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK (0x200000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT (21U) +/*! PIO1_PIN21_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN21_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK (0x400000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO0_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN22_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK (0x400000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT (22U) +/*! PIO1_PIN22_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN22_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK (0x800000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO0_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN23_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK (0x800000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT (23U) +/*! PIO1_PIN23_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN23_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO0_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN24_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT (24U) +/*! PIO1_PIN24_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN24_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO0_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN25_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT (25U) +/*! PIO1_PIN25_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN25_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO0_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN26_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT (26U) +/*! PIO1_PIN26_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN26_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO0_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN27_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT (27U) +/*! PIO1_PIN27_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN27_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO0_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN28_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT (28U) +/*! PIO1_PIN28_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN28_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO0_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN29_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT (29U) +/*! PIO1_PIN29_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN29_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO0_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN30_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT (30U) +/*! PIO1_PIN30_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN30_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO0_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO0_PIN31_SEC_MASK_MASK) + +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT (31U) +/*! PIO1_PIN31_SEC_MASK - Mask bit + * 0b0..Masked + * 0b1..Not masked + */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_SHIFT)) & AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_PIO1_PIN31_SEC_MASK_MASK) +/*! @} */ + +/* The count of AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK */ +#define AHBSC_SEC_GPIO_MASKN_SEC_GPIO_MASK_COUNT (2U) + +/*! @name MASTER_SEC_LEVEL - Master Secure Level */ +/*! @{ */ + +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK (0x30U) +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT (4U) +/*! SMARTDMA - SMARTDMA Data + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_SMARTDMA_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK (0xC0U) +#define AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT (6U) +/*! eDMA0 - eDMA0 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA0_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK (0x300U) +#define AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT (8U) +/*! eDMA1 - eDMA1 + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_EDMA1_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_PKC_MASK (0xC00U) +#define AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT (10U) +/*! PKC - PKC + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_PKC_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_PKC_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK (0xC000000U) +#define AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT (26U) +/*! USB_HS - USB HS + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define AHBSC_MASTER_SEC_LEVEL_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_USB_HS_MASK) + +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_LOCK - Master SEC Level Lock + * 0b00..Reserved + * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written + * 0b10..MASTER_SEC_LEVEL_LOCK can be written + * 0b11..Reserved + */ +#define AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK) +/*! @} */ + +/*! @name MASTER_SEC_ANTI_POL_REG - Master Secure Level */ +/*! @{ */ + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK (0x30U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT (4U) +/*! SMARTDMA - SMARTDMA Data + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_SMARTDMA_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK (0xC0U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT (6U) +/*! eDMA0 - eDMA0 + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA0_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK (0x300U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT (8U) +/*! eDMA1 - eDMA1 + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_EDMA1_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK (0xC00U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT (10U) +/*! PKC - PKC + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_PKC(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_PKC_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK (0xC000000U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT (26U) +/*! USB_HS - USB HS + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_USB_HS_MASK) + +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) +/*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - Master SEC Level Antipol Lock + * 0b00..Reserved + * 0b01..MASTER_SEC_LEVEL_LOCK cannot be written + * 0b10..MASTER_SEC_LEVEL_LOCK can be written + * 0b11..Reserved + */ +#define AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHBSC_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) +/*! @} */ + +/*! @name CPU0_LOCK_REG - Miscellaneous CPU0 Control Signals */ +/*! @{ */ + +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - LOCK_NS_VTOR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCKNSVTOR is 1 + * 0b10..CM33 (CPU0) LOCKNSVTOR is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - LOCK_NS_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_NS_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_NS_MPU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - LOCK_S_VTAIRCR + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_VTAIRCR is 1 + * 0b10..CM33 (CPU0) LOCK_S_VTAIRCR is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - LOCK_S_MPU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_S_MPU is 1 + * 0b10..CM33 (CPU0) LOCK_S_MPU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - LOCK_SAU + * 0b00..Reserved + * 0b01..CM33 (CPU0) LOCK_SAU is 1 + * 0b10..CM33 (CPU0) LOCK_SAU is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHBSC_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) +/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG_LOCK + * 0b00..Reserved + * 0b01..CM33_LOCK_REG_LOCK is 1 + * 0b10..CM33_LOCK_REG_LOCK is 0 + * 0b11..Reserved + */ +#define AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHBSC_CPU0_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +/*! @} */ + +/*! @name MISC_CTRL_DP_REG - Secure Control Duplicate */ +/*! @{ */ + +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not + * meet the security rule of the slave or memory to be accessed. + * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security + * rule of the slave or memory, it will not be detected as a violation. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables the privilege checking of secure mode access. + * 0b10..Disables the privilege checking of secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables the privilege checking of non-secure mode access. + * 0b10..Disables the privilege checking of non-secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..Reserved + * 0b01..Master can access memories and peripherals at the same level or below that level. + * 0b10..Master can access memories and peripherals at same level only + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_DISABLE_STRICT_MODE_MASK) + +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK) +/*! @} */ + +/*! @name MISC_CTRL_REG - Secure Control */ +/*! @{ */ + +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) +/*! WRITE_LOCK - Write Lock + * 0b00..Reserved + * 0b01..Writes to this register and to the Memory and Peripheral RULE registers are not allowed + * 0b10..Writes to this register and to the Memory and Peripheral RULE registers are allowed + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHBSC_MISC_CTRL_REG_WRITE_LOCK_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) +/*! ENABLE_SECURE_CHECKING - Enable Secure Checking + * 0b00..Reserved + * 0b01..Enables secure checking. Violation can be detected when the security level of a transaction does not + * meet the security rule of the slave or memory to be accessed. + * 0b10..Disables secure checking. Even if the security level of a transaction does not conform to the security + * rule of the slave or memory, it will not be detected as a violation. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) +/*! ENABLE_S_PRIV_CHECK - Enable Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables privilege checking of secure mode access. + * 0b10..Disables privilege checking of secure mode access. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) +/*! ENABLE_NS_PRIV_CHECK - Enable Non-Secure Privilege Checking + * 0b00..Reserved + * 0b01..Enables privilege checking of non-secure mode access. + * 0b10..Disables privilege checking of non-secure mode access is disabled. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHBSC_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) +/*! DISABLE_VIOLATION_ABORT - Disable Violation Abort + * 0b00..Reserved + * 0b01..The violation detected by the secure checker will not cause an abort, but a secure_violation_irq + * (interrupt request) will still be asserted and serviced by ISR. + * 0b10..The violation detected by the secure checker will cause an abort. + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK (0xC00U) +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT (10U) +/*! DISABLE_STRICT_MODE - Disable Strict Mode + * 0b00..Reserved + * 0b01..Master strict mode is on and can access memories and peripherals at the same level or below that level + * 0b10..Master strict mode is disabled and can access memories and peripherals at same level only + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_SHIFT)) & AHBSC_MISC_CTRL_REG_DISABLE_STRICT_MODE_MASK) + +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) +/*! IDAU_ALL_NS - IDAU All Non-Secure + * 0b00..Reserved + * 0b01..IDAU is disabled, which means that all memories are attributed as non-secure memory. + * 0b10..IDAU is enabled (restrictive mode) + * 0b11..Reserved + */ +#define AHBSC_MISC_CTRL_REG_IDAU_ALL_NS(x) (((uint32_t)(((uint32_t)(x)) << AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT)) & AHBSC_MISC_CTRL_REG_IDAU_ALL_NS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AHBSC_Register_Masks */ + + +/* AHBSC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x50120000u) + /** Peripheral AHBSC base address */ + #define AHBSC_BASE_NS (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC base pointer */ + #define AHBSC_NS ((AHBSC_Type *)AHBSC_BASE_NS) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x50121000u) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE_NS (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1_NS ((AHBSC_Type *)AHBSC_ALIAS1_BASE_NS) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x50122000u) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE_NS (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2_NS ((AHBSC_Type *)AHBSC_ALIAS2_BASE_NS) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x50123000u) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE_NS (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3_NS ((AHBSC_Type *)AHBSC_ALIAS3_BASE_NS) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS_NS { AHBSC_BASE_NS, AHBSC_ALIAS1_BASE_NS, AHBSC_ALIAS2_BASE_NS, AHBSC_ALIAS3_BASE_NS } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS_NS { AHBSC_NS, AHBSC_ALIAS1_NS, AHBSC_ALIAS2_NS, AHBSC_ALIAS3_NS } +#else + /** Peripheral AHBSC base address */ + #define AHBSC_BASE (0x40120000u) + /** Peripheral AHBSC base pointer */ + #define AHBSC ((AHBSC_Type *)AHBSC_BASE) + /** Peripheral AHBSC_ALIAS1 base address */ + #define AHBSC_ALIAS1_BASE (0x40121000u) + /** Peripheral AHBSC_ALIAS1 base pointer */ + #define AHBSC_ALIAS1 ((AHBSC_Type *)AHBSC_ALIAS1_BASE) + /** Peripheral AHBSC_ALIAS2 base address */ + #define AHBSC_ALIAS2_BASE (0x40122000u) + /** Peripheral AHBSC_ALIAS2 base pointer */ + #define AHBSC_ALIAS2 ((AHBSC_Type *)AHBSC_ALIAS2_BASE) + /** Peripheral AHBSC_ALIAS3 base address */ + #define AHBSC_ALIAS3_BASE (0x40123000u) + /** Peripheral AHBSC_ALIAS3 base pointer */ + #define AHBSC_ALIAS3 ((AHBSC_Type *)AHBSC_ALIAS3_BASE) + /** Array initializer of AHBSC peripheral base addresses */ + #define AHBSC_BASE_ADDRS { AHBSC_BASE, AHBSC_ALIAS1_BASE, AHBSC_ALIAS2_BASE, AHBSC_ALIAS3_BASE } + /** Array initializer of AHBSC peripheral base pointers */ + #define AHBSC_BASE_PTRS { AHBSC, AHBSC_ALIAS1, AHBSC_ALIAS2, AHBSC_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group AHBSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_4[44]; + union { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ + } MB_8B[32]; + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B[21]; + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B[12]; + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B[7]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[32]; + }; + uint8_t RESERVED_5[1536]; + __IO uint32_t RXIMR[32]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_6[512]; + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ + uint8_t RESERVED_7[24]; + struct { /* offset: 0xB40, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + } WMB[4]; + uint8_t RESERVED_8[112]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_9[9192]; + __IO uint32_t ERFFEL[32]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b1..Enable + * 0b0..Disable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_PNET_EN_MASK (0x4000U) +#define CAN_MCR_PNET_EN_SHIFT (14U) +/*! PNET_EN - Pretended Networking Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB8B (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B2 (2U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B (12U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B2 (8U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ +/*! @{ */ + +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by + * the FlexCAN module itself, as part of the message buffer matching and arbitration process. + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. + * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + */ +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B (7U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ +/*! @{ */ + +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B (7U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ +/*! @{ */ + +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B (7U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B2 (16U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (32U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ +/*! @{ */ + +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) + +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) + +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) + +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (32U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ +/*! @{ */ + +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) + +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) + +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) + +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (32U) + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (32U) + +/*! @name CTRL1_PN - Pretended Networking Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PN_FCS_MASK (0x3U) +#define CAN_CTRL1_PN_FCS_SHIFT (0U) +/*! FCS - Filtering Combination Selection + * 0b00..Message ID filtering only + * 0b01..Message ID filtering and payload filtering + * 0b10..Message ID filtering occurring a specified number of times + * 0b11..Message ID filtering and payload filtering a specified number of times + */ +#define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) + +#define CAN_CTRL1_PN_IDFS_MASK (0xCU) +#define CAN_CTRL1_PN_IDFS_SHIFT (2U) +/*! IDFS - ID Filtering Selection + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) + +#define CAN_CTRL1_PN_PLFS_MASK (0x30U) +#define CAN_CTRL1_PN_PLFS_SHIFT (4U) +/*! PLFS - Payload Filtering Selection + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) + +#define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) +#define CAN_CTRL1_PN_NMATCH_SHIFT (8U) +/*! NMATCH - Number of Messages Matching the Same Filtering Criteria + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times + */ +#define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) + +#define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) +#define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) + +#define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) +#define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) +/*! @} */ + +/*! @name CTRL2_PN - Pretended Networking Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) +#define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) +/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */ +#define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) +/*! @} */ + +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ +/*! @{ */ + +#define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) +#define CAN_WU_MTC_MCOUNTER_SHIFT (8U) +/*! MCOUNTER - Number of Matches in Pretended Networking */ +#define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) + +#define CAN_WU_MTC_WUMF_MASK (0x10000U) +#define CAN_WU_MTC_WUMF_SHIFT (16U) +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) + +#define CAN_WU_MTC_WTOF_MASK (0x20000U) +#define CAN_WU_MTC_WTOF_SHIFT (17U) +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) +/*! @} */ + +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ +/*! @{ */ + +#define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) +/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */ +#define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) + +#define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) +#define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) +/*! FLT_RTR - Remote Transmission Request Filter + * 0b0..Reject remote frame (accept data frame) + * 0b1..Accept remote frame + */ +#define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) + +#define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) +#define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) +/*! FLT_IDE - ID Extended Filter + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) +/*! @} */ + +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ +/*! @{ */ + +#define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) +#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) +/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) + +#define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) +#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) +/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) +/*! @} */ + +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ +/*! @{ */ + +#define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL1_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data byte 3 */ +#define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) + +#define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL1_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data byte 2 */ +#define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) + +#define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL1_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data byte 1 */ +#define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) + +#define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL1_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data byte 0 */ +#define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ +/*! @{ */ + +#define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL1_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data byte 7 */ +#define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) + +#define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL1_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data byte 6 */ +#define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) + +#define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL1_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data byte 5 */ +#define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) + +#define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL1_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data byte 4 */ +#define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ +/*! @{ */ + +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) + +#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) +#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) + +#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) +#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name WMB_CS - Wake-Up Message Buffer */ +/*! @{ */ + +#define CAN_WMB_CS_DLC_MASK (0xF0000U) +#define CAN_WMB_CS_DLC_SHIFT (16U) +/*! DLC - Length of Data in Bytes */ +#define CAN_WMB_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK) + +#define CAN_WMB_CS_RTR_MASK (0x100000U) +#define CAN_WMB_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote + */ +#define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) + +#define CAN_WMB_CS_IDE_MASK (0x200000U) +#define CAN_WMB_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended Bit + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) + +#define CAN_WMB_CS_SRR_MASK (0x400000U) +#define CAN_WMB_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ +#define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) +/*! @} */ + +/* The count of CAN_WMB_CS */ +#define CAN_WMB_CS_COUNT (4U) + +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ +/*! @{ */ + +#define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) +#define CAN_WMB_ID_ID_SHIFT (0U) +/*! ID - Received ID in Pretended Networking Mode */ +#define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) +/*! @} */ + +/* The count of CAN_WMB_ID */ +#define CAN_WMB_ID_COUNT (4U) + +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ +/*! @{ */ + +#define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) +#define CAN_WMB_D03_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) + +#define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) +#define CAN_WMB_D03_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) + +#define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) +#define CAN_WMB_D03_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) + +#define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) +#define CAN_WMB_D03_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) +/*! @} */ + +/* The count of CAN_WMB_D03 */ +#define CAN_WMB_D03_COUNT (4U) + +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ +/*! @{ */ + +#define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) +#define CAN_WMB_D47_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) + +#define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) +#define CAN_WMB_D47_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) + +#define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) +#define CAN_WMB_D47_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) + +#define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) +#define CAN_WMB_D47_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) +/*! @} */ + +/* The count of CAN_WMB_D47 */ +#define CAN_WMB_D47_COUNT (4U) + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + +/* The count of CAN_ERFFEL */ +#define CAN_ERFFEL_COUNT (32U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x500D4000u) + /** Peripheral CAN0 base address */ + #define CAN0_BASE_NS (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN0 base pointer */ + #define CAN0_NS ((CAN_Type *)CAN0_BASE_NS) + /** Peripheral CAN1 base address */ + #define CAN1_BASE (0x500D8000u) + /** Peripheral CAN1 base address */ + #define CAN1_BASE_NS (0x400D8000u) + /** Peripheral CAN1 base pointer */ + #define CAN1 ((CAN_Type *)CAN1_BASE) + /** Peripheral CAN1 base pointer */ + #define CAN1_NS ((CAN_Type *)CAN1_BASE_NS) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0, CAN1 } + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS_NS { CAN0_BASE_NS, CAN1_BASE_NS } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS_NS { CAN0_NS, CAN1_NS } +#else + /** Peripheral CAN0 base address */ + #define CAN0_BASE (0x400D4000u) + /** Peripheral CAN0 base pointer */ + #define CAN0 ((CAN_Type *)CAN0_BASE) + /** Peripheral CAN1 base address */ + #define CAN1_BASE (0x400D8000u) + /** Peripheral CAN1 base pointer */ + #define CAN1 ((CAN_Type *)CAN1_BASE) + /** Array initializer of CAN peripheral base addresses */ + #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } + /** Array initializer of CAN peripheral base pointers */ + #define CAN_BASE_PTRS { CAN0, CAN1 } +#endif +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn, CAN1_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn, CAN1_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */ + __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */ + __O uint32_t START; /**< START Command Register, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */ + __O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - Control Register */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction Timer Reload Register */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - Instruction Timer Register */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 Register */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults since the last POR */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults since the last POR */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) +/*! @} */ + +/*! @name STATUS2 - Status 2 Register */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults since the last POR */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults since the last POR */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults since the last POR */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) +/*! @} */ + +/*! @name FLAGS - Flags Register */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent Data Storage Register */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - START Command Register */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - STOP Command Register */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - RESTART Command Register */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - ADD Command Register */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - ADD1 Command Register */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - ADD16 Command Register */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - ADD256 Command Register */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - SUB Command Register */ +/*! @{ */ + +#define CDOG_SUB_SB_MASK (0xFFFFFFFFU) +#define CDOG_SUB_SB_SHIFT (0U) +/*! SB - Subtract Write Value */ +#define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK) +/*! @} */ + +/*! @name SUB1 - SUB1 Command Register */ +/*! @{ */ + +#define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_SB1_SHIFT (0U) +/*! SB1 - Subtract 1 */ +#define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK) +/*! @} */ + +/*! @name SUB16 - SUB16 Command Register */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - SUB256 Command Register */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + +/*! @name ASSERT16 - ASSERT16 Command Register */ +/*! @{ */ + +#define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU) +#define CDOG_ASSERT16_AST16_SHIFT (0U) +/*! AST16 - ASSERT16 Command */ +#define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/* CDOG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x500BB000u) + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE_NS (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG0 base pointer */ + #define CDOG0_NS ((CDOG_Type *)CDOG0_BASE_NS) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x500BC000u) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE_NS (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Peripheral CDOG1 base pointer */ + #define CDOG1_NS ((CDOG_Type *)CDOG1_BASE_NS) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS_NS { CDOG0_BASE_NS, CDOG1_BASE_NS } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS_NS { CDOG0_NS, CDOG1_NS } +#else + /** Peripheral CDOG0 base address */ + #define CDOG0_BASE (0x400BB000u) + /** Peripheral CDOG0 base pointer */ + #define CDOG0 ((CDOG_Type *)CDOG0_BASE) + /** Peripheral CDOG1 base address */ + #define CDOG1_BASE (0x400BC000u) + /** Peripheral CDOG1 base pointer */ + #define CDOG1 ((CDOG_Type *)CDOG1_BASE) + /** Array initializer of CDOG peripheral base addresses */ + #define CDOG_BASE_ADDRS { CDOG0_BASE, CDOG1_BASE } + /** Array initializer of CDOG peripheral base pointers */ + #define CDOG_BASE_PTRS { CDOG0, CDOG1 } +#endif +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn, CDOG1_IRQn } + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer + * @{ + */ + +/** CMC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */ + __IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */ + __IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */ + __O uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */ + __IO uint32_t PMCTRL[2]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[88]; + __I uint32_t SRS; /**< System Reset Status, offset: 0x80 */ + __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */ + __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */ + __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */ + __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */ + uint8_t RESERVED_2[8]; + __I uint32_t RSTCNT; /**< Reset Count Register, offset: 0x9C */ + __IO uint32_t MR[1]; /**< Mode, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FM[1]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SRAMDIS[1]; /**< SRAM Disable, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[12]; + __IO uint32_t SRAMRET[1]; /**< SRAM Retention, array offset: 0xD0, array step: 0x4 */ + uint8_t RESERVED_6[12]; + __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ + uint8_t RESERVED_7[28]; + __IO uint32_t BSR; /**< BootROM Status Register, offset: 0x100 */ + uint8_t RESERVED_8[8]; + __IO uint32_t BLR; /**< BootROM Lock Register, offset: 0x10C */ + __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */ +} CMC_Type; + +/* ---------------------------------------------------------------------------- + -- CMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Register_Masks CMC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define CMC_VERID_FEATURE_MASK (0xFFFFU) +#define CMC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK) + +#define CMC_VERID_MINOR_MASK (0xFF0000U) +#define CMC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK) + +#define CMC_VERID_MAJOR_MASK (0xFF000000U) +#define CMC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CKCTRL - Clock Control */ +/*! @{ */ + +#define CMC_CKCTRL_CKMODE_MASK (0xFU) +#define CMC_CKCTRL_CKMODE_SHIFT (0U) +/*! CKMODE - Clocking Mode + * 0b0000..No clock gating + * 0b0001..Core clock is gated + * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode. + */ +#define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) + +#define CMC_CKCTRL_LOCK_MASK (0x80000000U) +#define CMC_CKCTRL_LOCK_SHIFT (31U) +/*! LOCK - Lock + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK) +/*! @} */ + +/*! @name CKSTAT - Clock Status */ +/*! @{ */ + +#define CMC_CKSTAT_CKMODE_MASK (0xFU) +#define CMC_CKSTAT_CKMODE_SHIFT (0U) +/*! CKMODE - Low Power Status + * 0b0000..Core clock not gated + * 0b0001..Core clock was gated + * 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode + * *.. + */ +#define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK) + +#define CMC_CKSTAT_WAKEUP_MASK (0xFF00U) +#define CMC_CKSTAT_WAKEUP_SHIFT (8U) +/*! WAKEUP - Wake-up Source */ +#define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK) + +#define CMC_CKSTAT_VALID_MASK (0x80000000U) +#define CMC_CKSTAT_VALID_SHIFT (31U) +/*! VALID - Clock Status Valid + * 0b0..Core clock not gated + * 0b1..Core clock was gated due to Low-Power mode entry + */ +#define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK) +/*! @} */ + +/*! @name PMPROT - Power Mode Protection */ +/*! @{ */ + +#define CMC_PMPROT_LPMODE_MASK (0xFU) +#define CMC_PMPROT_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Not allowed + * 0b0001..Allowed + * 0b0010..Allowed + * 0b0011..Allowed + * 0b0100..Allowed + * 0b0101..Allowed + * 0b0110..Allowed + * 0b0111..Allowed + * 0b1000..Allowed + * 0b1001..Allowed + * 0b1010..Allowed + * 0b1011..Allowed + * 0b1100..Allowed + * 0b1101..Allowed + * 0b1110..Allowed + * 0b1111..Allowed + */ +#define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK) + +#define CMC_PMPROT_LOCK_MASK (0x80000000U) +#define CMC_PMPROT_LOCK_SHIFT (31U) +/*! LOCK - Lock Register + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK) +/*! @} */ + +/*! @name GPMCTRL - Global Power Mode Control */ +/*! @{ */ + +#define CMC_GPMCTRL_LPMODE_MASK (0xFU) +#define CMC_GPMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode */ +#define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name PMCTRL - Power Mode Control */ +/*! @{ */ + +#define CMC_PMCTRL_LPMODE_MASK (0xFU) +#define CMC_PMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Active/Sleep + * 0b0001..Deep Sleep + * 0b0011..Power Down + * 0b0111..Reserved + * 0b1111..Deep-Power Down + */ +#define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK) +/*! @} */ + +/* The count of CMC_PMCTRL */ +#define CMC_PMCTRL_COUNT (2U) + +/*! @name SRS - System Reset Status */ +/*! @{ */ + +#define CMC_SRS_WAKEUP_MASK (0x1U) +#define CMC_SRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK) + +#define CMC_SRS_POR_MASK (0x2U) +#define CMC_SRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK) + +#define CMC_SRS_VD_MASK (0x4U) +#define CMC_SRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK) + +#define CMC_SRS_WARM_MASK (0x10U) +#define CMC_SRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK) + +#define CMC_SRS_FATAL_MASK (0x20U) +#define CMC_SRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK) + +#define CMC_SRS_PIN_MASK (0x100U) +#define CMC_SRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK) + +#define CMC_SRS_DAP_MASK (0x200U) +#define CMC_SRS_DAP_SHIFT (9U) +/*! DAP - Debug Access Port Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK) + +#define CMC_SRS_RSTACK_MASK (0x400U) +#define CMC_SRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK) + +#define CMC_SRS_LPACK_MASK (0x800U) +#define CMC_SRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK) + +#define CMC_SRS_SCG_MASK (0x1000U) +#define CMC_SRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK) + +#define CMC_SRS_WWDT0_MASK (0x2000U) +#define CMC_SRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK) + +#define CMC_SRS_SW_MASK (0x4000U) +#define CMC_SRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK) + +#define CMC_SRS_LOCKUP_MASK (0x8000U) +#define CMC_SRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK) + +#define CMC_SRS_CPU1_MASK (0x10000U) +#define CMC_SRS_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CPU1_SHIFT)) & CMC_SRS_CPU1_MASK) + +#define CMC_SRS_VBAT_MASK (0x1000000U) +#define CMC_SRS_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VBAT_SHIFT)) & CMC_SRS_VBAT_MASK) + +#define CMC_SRS_WWDT1_MASK (0x2000000U) +#define CMC_SRS_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT1_SHIFT)) & CMC_SRS_WWDT1_MASK) + +#define CMC_SRS_CDOG0_MASK (0x4000000U) +#define CMC_SRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK) + +#define CMC_SRS_CDOG1_MASK (0x8000000U) +#define CMC_SRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG1_SHIFT)) & CMC_SRS_CDOG1_MASK) + +#define CMC_SRS_JTAG_MASK (0x10000000U) +#define CMC_SRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK) + +#define CMC_SRS_SECVIO_MASK (0x40000000U) +#define CMC_SRS_SECVIO_SHIFT (30U) +/*! SECVIO - Security Violation Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SECVIO_SHIFT)) & CMC_SRS_SECVIO_MASK) + +#define CMC_SRS_TAMPER_MASK (0x80000000U) +#define CMC_SRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_TAMPER_SHIFT)) & CMC_SRS_TAMPER_MASK) +/*! @} */ + +/*! @name RPC - Reset Pin Control */ +/*! @{ */ + +#define CMC_RPC_FILTCFG_MASK (0x1FU) +#define CMC_RPC_FILTCFG_SHIFT (0U) +/*! FILTCFG - Reset Filter Configuration */ +#define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK) + +#define CMC_RPC_FILTEN_MASK (0x100U) +#define CMC_RPC_FILTEN_SHIFT (8U) +/*! FILTEN - Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK) + +#define CMC_RPC_LPFEN_MASK (0x200U) +#define CMC_RPC_LPFEN_SHIFT (9U) +/*! LPFEN - Low-Power Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK) +/*! @} */ + +/*! @name SSRS - Sticky System Reset Status */ +/*! @{ */ + +#define CMC_SSRS_WAKEUP_MASK (0x1U) +#define CMC_SSRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK) + +#define CMC_SSRS_POR_MASK (0x2U) +#define CMC_SSRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK) + +#define CMC_SSRS_VD_MASK (0x4U) +#define CMC_SSRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK) + +#define CMC_SSRS_WARM_MASK (0x10U) +#define CMC_SSRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK) + +#define CMC_SSRS_FATAL_MASK (0x20U) +#define CMC_SSRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK) + +#define CMC_SSRS_PIN_MASK (0x100U) +#define CMC_SSRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK) + +#define CMC_SSRS_DAP_MASK (0x200U) +#define CMC_SSRS_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK) + +#define CMC_SSRS_RSTACK_MASK (0x400U) +#define CMC_SSRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK) + +#define CMC_SSRS_LPACK_MASK (0x800U) +#define CMC_SSRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK) + +#define CMC_SSRS_SCG_MASK (0x1000U) +#define CMC_SSRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK) + +#define CMC_SSRS_WWDT0_MASK (0x2000U) +#define CMC_SSRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK) + +#define CMC_SSRS_SW_MASK (0x4000U) +#define CMC_SSRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK) + +#define CMC_SSRS_LOCKUP_MASK (0x8000U) +#define CMC_SSRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK) + +#define CMC_SSRS_CPU1_MASK (0x10000U) +#define CMC_SSRS_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Reset not generated from CPU1 reset source. + * 0b1..Reset generated from CPU1 reset source. + */ +#define CMC_SSRS_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CPU1_SHIFT)) & CMC_SSRS_CPU1_MASK) + +#define CMC_SSRS_VBAT_MASK (0x1000000U) +#define CMC_SSRS_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VBAT_SHIFT)) & CMC_SSRS_VBAT_MASK) + +#define CMC_SSRS_WWDT1_MASK (0x2000000U) +#define CMC_SSRS_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT1_SHIFT)) & CMC_SSRS_WWDT1_MASK) + +#define CMC_SSRS_CDOG0_MASK (0x4000000U) +#define CMC_SSRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK) + +#define CMC_SSRS_CDOG1_MASK (0x8000000U) +#define CMC_SSRS_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG1_SHIFT)) & CMC_SSRS_CDOG1_MASK) + +#define CMC_SSRS_JTAG_MASK (0x10000000U) +#define CMC_SSRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK) + +#define CMC_SSRS_SECVIO_MASK (0x40000000U) +#define CMC_SSRS_SECVIO_SHIFT (30U) +/*! SECVIO - Security Violation Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SECVIO(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SECVIO_SHIFT)) & CMC_SSRS_SECVIO_MASK) + +#define CMC_SSRS_TAMPER_MASK (0x80000000U) +#define CMC_SSRS_TAMPER_SHIFT (31U) +/*! TAMPER - Tamper Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_TAMPER(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_TAMPER_SHIFT)) & CMC_SSRS_TAMPER_MASK) +/*! @} */ + +/*! @name SRIE - System Reset Interrupt Enable */ +/*! @{ */ + +#define CMC_SRIE_PIN_MASK (0x100U) +#define CMC_SRIE_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK) + +#define CMC_SRIE_DAP_MASK (0x200U) +#define CMC_SRIE_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK) + +#define CMC_SRIE_LPACK_MASK (0x800U) +#define CMC_SRIE_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK) + +#define CMC_SRIE_SCG_MASK (0x1000U) +#define CMC_SRIE_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK) + +#define CMC_SRIE_WWDT0_MASK (0x2000U) +#define CMC_SRIE_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK) + +#define CMC_SRIE_SW_MASK (0x4000U) +#define CMC_SRIE_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK) + +#define CMC_SRIE_LOCKUP_MASK (0x8000U) +#define CMC_SRIE_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK) + +#define CMC_SRIE_CPU1_MASK (0x10000U) +#define CMC_SRIE_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CPU1_SHIFT)) & CMC_SRIE_CPU1_MASK) + +#define CMC_SRIE_VBAT_MASK (0x1000000U) +#define CMC_SRIE_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_VBAT_SHIFT)) & CMC_SRIE_VBAT_MASK) + +#define CMC_SRIE_WWDT1_MASK (0x2000000U) +#define CMC_SRIE_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT1_SHIFT)) & CMC_SRIE_WWDT1_MASK) + +#define CMC_SRIE_CDOG0_MASK (0x4000000U) +#define CMC_SRIE_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK) + +#define CMC_SRIE_CDOG1_MASK (0x8000000U) +#define CMC_SRIE_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG1_SHIFT)) & CMC_SRIE_CDOG1_MASK) +/*! @} */ + +/*! @name SRIF - System Reset Interrupt Flag */ +/*! @{ */ + +#define CMC_SRIF_PIN_MASK (0x100U) +#define CMC_SRIF_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK) + +#define CMC_SRIF_DAP_MASK (0x200U) +#define CMC_SRIF_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK) + +#define CMC_SRIF_LPACK_MASK (0x800U) +#define CMC_SRIF_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK) + +#define CMC_SRIF_WWDT0_MASK (0x2000U) +#define CMC_SRIF_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK) + +#define CMC_SRIF_SW_MASK (0x4000U) +#define CMC_SRIF_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK) + +#define CMC_SRIF_LOCKUP_MASK (0x8000U) +#define CMC_SRIF_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK) + +#define CMC_SRIF_CPU1_MASK (0x10000U) +#define CMC_SRIF_CPU1_SHIFT (16U) +/*! CPU1 - CPU1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CPU1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CPU1_SHIFT)) & CMC_SRIF_CPU1_MASK) + +#define CMC_SRIF_VBAT_MASK (0x1000000U) +#define CMC_SRIF_VBAT_SHIFT (24U) +/*! VBAT - VBAT System Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_VBAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_VBAT_SHIFT)) & CMC_SRIF_VBAT_MASK) + +#define CMC_SRIF_WWDT1_MASK (0x2000000U) +#define CMC_SRIF_WWDT1_SHIFT (25U) +/*! WWDT1 - Windowed Watchdog 1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT1_SHIFT)) & CMC_SRIF_WWDT1_MASK) + +#define CMC_SRIF_CDOG0_MASK (0x4000000U) +#define CMC_SRIF_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK) + +#define CMC_SRIF_CDOG1_MASK (0x8000000U) +#define CMC_SRIF_CDOG1_SHIFT (27U) +/*! CDOG1 - Code Watchdog 1 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG1_SHIFT)) & CMC_SRIF_CDOG1_MASK) +/*! @} */ + +/*! @name RSTCNT - Reset Count Register */ +/*! @{ */ + +#define CMC_RSTCNT_COUNT_MASK (0xFFU) +#define CMC_RSTCNT_COUNT_SHIFT (0U) +/*! COUNT - Count */ +#define CMC_RSTCNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK) +/*! @} */ + +/*! @name MR - Mode */ +/*! @{ */ + +#define CMC_MR_ISPMODE_n_MASK (0x1U) +#define CMC_MR_ISPMODE_n_SHIFT (0U) +/*! ISPMODE_n - In System Programming Mode */ +#define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK) +/*! @} */ + +/* The count of CMC_MR */ +#define CMC_MR_COUNT (1U) + +/*! @name FM - Force Mode */ +/*! @{ */ + +#define CMC_FM_FORCECFG_MASK (0x1U) +#define CMC_FM_FORCECFG_SHIFT (0U) +/*! FORCECFG - Boot Configuration + * 0b0..No effect + * 0b1..Asserts + */ +#define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK) +/*! @} */ + +/* The count of CMC_FM */ +#define CMC_FM_COUNT (1U) + +/*! @name SRAMDIS - SRAM Disable */ +/*! @{ */ + +#define CMC_SRAMDIS_DIS0_MASK (0x1U) +#define CMC_SRAMDIS_DIS0_SHIFT (0U) +/*! DIS0 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS0_SHIFT)) & CMC_SRAMDIS_DIS0_MASK) + +#define CMC_SRAMDIS_DIS1_MASK (0x2U) +#define CMC_SRAMDIS_DIS1_SHIFT (1U) +/*! DIS1 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS1_SHIFT)) & CMC_SRAMDIS_DIS1_MASK) + +#define CMC_SRAMDIS_DIS2_MASK (0x4U) +#define CMC_SRAMDIS_DIS2_SHIFT (2U) +/*! DIS2 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS2_SHIFT)) & CMC_SRAMDIS_DIS2_MASK) + +#define CMC_SRAMDIS_DIS3_MASK (0x8U) +#define CMC_SRAMDIS_DIS3_SHIFT (3U) +/*! DIS3 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS3_SHIFT)) & CMC_SRAMDIS_DIS3_MASK) + +#define CMC_SRAMDIS_DIS4_MASK (0x10U) +#define CMC_SRAMDIS_DIS4_SHIFT (4U) +/*! DIS4 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS4_SHIFT)) & CMC_SRAMDIS_DIS4_MASK) + +#define CMC_SRAMDIS_DIS5_MASK (0x20U) +#define CMC_SRAMDIS_DIS5_SHIFT (5U) +/*! DIS5 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS5_SHIFT)) & CMC_SRAMDIS_DIS5_MASK) + +#define CMC_SRAMDIS_DIS6_MASK (0x40U) +#define CMC_SRAMDIS_DIS6_SHIFT (6U) +/*! DIS6 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS6_SHIFT)) & CMC_SRAMDIS_DIS6_MASK) + +#define CMC_SRAMDIS_DIS7_MASK (0x80U) +#define CMC_SRAMDIS_DIS7_SHIFT (7U) +/*! DIS7 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS7_SHIFT)) & CMC_SRAMDIS_DIS7_MASK) + +#define CMC_SRAMDIS_DIS8_MASK (0x100U) +#define CMC_SRAMDIS_DIS8_SHIFT (8U) +/*! DIS8 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS8_SHIFT)) & CMC_SRAMDIS_DIS8_MASK) + +#define CMC_SRAMDIS_DIS9_MASK (0x200U) +#define CMC_SRAMDIS_DIS9_SHIFT (9U) +/*! DIS9 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS9_SHIFT)) & CMC_SRAMDIS_DIS9_MASK) + +#define CMC_SRAMDIS_DIS10_MASK (0x400U) +#define CMC_SRAMDIS_DIS10_SHIFT (10U) +/*! DIS10 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS10_SHIFT)) & CMC_SRAMDIS_DIS10_MASK) + +#define CMC_SRAMDIS_DIS11_MASK (0x800U) +#define CMC_SRAMDIS_DIS11_SHIFT (11U) +/*! DIS11 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS11_SHIFT)) & CMC_SRAMDIS_DIS11_MASK) + +#define CMC_SRAMDIS_DIS12_MASK (0x1000U) +#define CMC_SRAMDIS_DIS12_SHIFT (12U) +/*! DIS12 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS12_SHIFT)) & CMC_SRAMDIS_DIS12_MASK) + +#define CMC_SRAMDIS_DIS13_MASK (0x2000U) +#define CMC_SRAMDIS_DIS13_SHIFT (13U) +/*! DIS13 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS13_SHIFT)) & CMC_SRAMDIS_DIS13_MASK) + +#define CMC_SRAMDIS_DIS14_MASK (0x4000U) +#define CMC_SRAMDIS_DIS14_SHIFT (14U) +/*! DIS14 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS14_SHIFT)) & CMC_SRAMDIS_DIS14_MASK) + +#define CMC_SRAMDIS_DIS15_MASK (0x8000U) +#define CMC_SRAMDIS_DIS15_SHIFT (15U) +/*! DIS15 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS15_SHIFT)) & CMC_SRAMDIS_DIS15_MASK) + +#define CMC_SRAMDIS_DIS16_MASK (0x10000U) +#define CMC_SRAMDIS_DIS16_SHIFT (16U) +/*! DIS16 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS16_SHIFT)) & CMC_SRAMDIS_DIS16_MASK) + +#define CMC_SRAMDIS_DIS17_MASK (0x20000U) +#define CMC_SRAMDIS_DIS17_SHIFT (17U) +/*! DIS17 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS17_SHIFT)) & CMC_SRAMDIS_DIS17_MASK) + +#define CMC_SRAMDIS_DIS18_MASK (0x40000U) +#define CMC_SRAMDIS_DIS18_SHIFT (18U) +/*! DIS18 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS18_SHIFT)) & CMC_SRAMDIS_DIS18_MASK) + +#define CMC_SRAMDIS_DIS19_MASK (0x80000U) +#define CMC_SRAMDIS_DIS19_SHIFT (19U) +/*! DIS19 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS19_SHIFT)) & CMC_SRAMDIS_DIS19_MASK) + +#define CMC_SRAMDIS_DIS20_MASK (0x100000U) +#define CMC_SRAMDIS_DIS20_SHIFT (20U) +/*! DIS20 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS20_SHIFT)) & CMC_SRAMDIS_DIS20_MASK) + +#define CMC_SRAMDIS_DIS21_MASK (0x200000U) +#define CMC_SRAMDIS_DIS21_SHIFT (21U) +/*! DIS21 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS21_SHIFT)) & CMC_SRAMDIS_DIS21_MASK) + +#define CMC_SRAMDIS_DIS22_MASK (0x400000U) +#define CMC_SRAMDIS_DIS22_SHIFT (22U) +/*! DIS22 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS22_SHIFT)) & CMC_SRAMDIS_DIS22_MASK) + +#define CMC_SRAMDIS_DIS23_MASK (0x800000U) +#define CMC_SRAMDIS_DIS23_SHIFT (23U) +/*! DIS23 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS23_SHIFT)) & CMC_SRAMDIS_DIS23_MASK) + +#define CMC_SRAMDIS_DIS24_MASK (0x1000000U) +#define CMC_SRAMDIS_DIS24_SHIFT (24U) +/*! DIS24 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS24_SHIFT)) & CMC_SRAMDIS_DIS24_MASK) + +#define CMC_SRAMDIS_DIS25_MASK (0x2000000U) +#define CMC_SRAMDIS_DIS25_SHIFT (25U) +/*! DIS25 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS25_SHIFT)) & CMC_SRAMDIS_DIS25_MASK) + +#define CMC_SRAMDIS_DIS26_MASK (0x4000000U) +#define CMC_SRAMDIS_DIS26_SHIFT (26U) +/*! DIS26 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS26_SHIFT)) & CMC_SRAMDIS_DIS26_MASK) + +#define CMC_SRAMDIS_DIS27_MASK (0x8000000U) +#define CMC_SRAMDIS_DIS27_SHIFT (27U) +/*! DIS27 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS27_SHIFT)) & CMC_SRAMDIS_DIS27_MASK) + +#define CMC_SRAMDIS_DIS28_MASK (0x10000000U) +#define CMC_SRAMDIS_DIS28_SHIFT (28U) +/*! DIS28 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS28_SHIFT)) & CMC_SRAMDIS_DIS28_MASK) + +#define CMC_SRAMDIS_DIS29_MASK (0x20000000U) +#define CMC_SRAMDIS_DIS29_SHIFT (29U) +/*! DIS29 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS29_SHIFT)) & CMC_SRAMDIS_DIS29_MASK) + +#define CMC_SRAMDIS_DIS30_MASK (0x40000000U) +#define CMC_SRAMDIS_DIS30_SHIFT (30U) +/*! DIS30 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS30_SHIFT)) & CMC_SRAMDIS_DIS30_MASK) + +#define CMC_SRAMDIS_DIS31_MASK (0x80000000U) +#define CMC_SRAMDIS_DIS31_SHIFT (31U) +/*! DIS31 - SRAM Disable + * 0b0..Enables + * 0b1..Disables + */ +#define CMC_SRAMDIS_DIS31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS31_SHIFT)) & CMC_SRAMDIS_DIS31_MASK) +/*! @} */ + +/* The count of CMC_SRAMDIS */ +#define CMC_SRAMDIS_COUNT (1U) + +/*! @name SRAMRET - SRAM Retention */ +/*! @{ */ + +#define CMC_SRAMRET_RET0_MASK (0x1U) +#define CMC_SRAMRET_RET0_SHIFT (0U) +/*! RET0 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET0_SHIFT)) & CMC_SRAMRET_RET0_MASK) + +#define CMC_SRAMRET_RET1_MASK (0x2U) +#define CMC_SRAMRET_RET1_SHIFT (1U) +/*! RET1 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET1(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET1_SHIFT)) & CMC_SRAMRET_RET1_MASK) + +#define CMC_SRAMRET_RET2_MASK (0x4U) +#define CMC_SRAMRET_RET2_SHIFT (2U) +/*! RET2 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET2(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET2_SHIFT)) & CMC_SRAMRET_RET2_MASK) + +#define CMC_SRAMRET_RET3_MASK (0x8U) +#define CMC_SRAMRET_RET3_SHIFT (3U) +/*! RET3 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET3(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET3_SHIFT)) & CMC_SRAMRET_RET3_MASK) + +#define CMC_SRAMRET_RET4_MASK (0x10U) +#define CMC_SRAMRET_RET4_SHIFT (4U) +/*! RET4 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET4(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET4_SHIFT)) & CMC_SRAMRET_RET4_MASK) + +#define CMC_SRAMRET_RET5_MASK (0x20U) +#define CMC_SRAMRET_RET5_SHIFT (5U) +/*! RET5 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET5(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET5_SHIFT)) & CMC_SRAMRET_RET5_MASK) + +#define CMC_SRAMRET_RET6_MASK (0x40U) +#define CMC_SRAMRET_RET6_SHIFT (6U) +/*! RET6 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET6(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET6_SHIFT)) & CMC_SRAMRET_RET6_MASK) + +#define CMC_SRAMRET_RET7_MASK (0x80U) +#define CMC_SRAMRET_RET7_SHIFT (7U) +/*! RET7 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET7(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET7_SHIFT)) & CMC_SRAMRET_RET7_MASK) + +#define CMC_SRAMRET_RET8_MASK (0x100U) +#define CMC_SRAMRET_RET8_SHIFT (8U) +/*! RET8 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET8(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET8_SHIFT)) & CMC_SRAMRET_RET8_MASK) + +#define CMC_SRAMRET_RET9_MASK (0x200U) +#define CMC_SRAMRET_RET9_SHIFT (9U) +/*! RET9 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET9(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET9_SHIFT)) & CMC_SRAMRET_RET9_MASK) + +#define CMC_SRAMRET_RET10_MASK (0x400U) +#define CMC_SRAMRET_RET10_SHIFT (10U) +/*! RET10 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET10(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET10_SHIFT)) & CMC_SRAMRET_RET10_MASK) + +#define CMC_SRAMRET_RET11_MASK (0x800U) +#define CMC_SRAMRET_RET11_SHIFT (11U) +/*! RET11 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET11(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET11_SHIFT)) & CMC_SRAMRET_RET11_MASK) + +#define CMC_SRAMRET_RET12_MASK (0x1000U) +#define CMC_SRAMRET_RET12_SHIFT (12U) +/*! RET12 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET12(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET12_SHIFT)) & CMC_SRAMRET_RET12_MASK) + +#define CMC_SRAMRET_RET13_MASK (0x2000U) +#define CMC_SRAMRET_RET13_SHIFT (13U) +/*! RET13 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET13(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET13_SHIFT)) & CMC_SRAMRET_RET13_MASK) + +#define CMC_SRAMRET_RET14_MASK (0x4000U) +#define CMC_SRAMRET_RET14_SHIFT (14U) +/*! RET14 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET14(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET14_SHIFT)) & CMC_SRAMRET_RET14_MASK) + +#define CMC_SRAMRET_RET15_MASK (0x8000U) +#define CMC_SRAMRET_RET15_SHIFT (15U) +/*! RET15 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET15(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET15_SHIFT)) & CMC_SRAMRET_RET15_MASK) + +#define CMC_SRAMRET_RET16_MASK (0x10000U) +#define CMC_SRAMRET_RET16_SHIFT (16U) +/*! RET16 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET16(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET16_SHIFT)) & CMC_SRAMRET_RET16_MASK) + +#define CMC_SRAMRET_RET17_MASK (0x20000U) +#define CMC_SRAMRET_RET17_SHIFT (17U) +/*! RET17 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET17(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET17_SHIFT)) & CMC_SRAMRET_RET17_MASK) + +#define CMC_SRAMRET_RET18_MASK (0x40000U) +#define CMC_SRAMRET_RET18_SHIFT (18U) +/*! RET18 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET18(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET18_SHIFT)) & CMC_SRAMRET_RET18_MASK) + +#define CMC_SRAMRET_RET19_MASK (0x80000U) +#define CMC_SRAMRET_RET19_SHIFT (19U) +/*! RET19 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET19(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET19_SHIFT)) & CMC_SRAMRET_RET19_MASK) + +#define CMC_SRAMRET_RET20_MASK (0x100000U) +#define CMC_SRAMRET_RET20_SHIFT (20U) +/*! RET20 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET20(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET20_SHIFT)) & CMC_SRAMRET_RET20_MASK) + +#define CMC_SRAMRET_RET21_MASK (0x200000U) +#define CMC_SRAMRET_RET21_SHIFT (21U) +/*! RET21 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET21(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET21_SHIFT)) & CMC_SRAMRET_RET21_MASK) + +#define CMC_SRAMRET_RET22_MASK (0x400000U) +#define CMC_SRAMRET_RET22_SHIFT (22U) +/*! RET22 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET22(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET22_SHIFT)) & CMC_SRAMRET_RET22_MASK) + +#define CMC_SRAMRET_RET23_MASK (0x800000U) +#define CMC_SRAMRET_RET23_SHIFT (23U) +/*! RET23 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET23(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET23_SHIFT)) & CMC_SRAMRET_RET23_MASK) + +#define CMC_SRAMRET_RET24_MASK (0x1000000U) +#define CMC_SRAMRET_RET24_SHIFT (24U) +/*! RET24 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET24(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET24_SHIFT)) & CMC_SRAMRET_RET24_MASK) + +#define CMC_SRAMRET_RET25_MASK (0x2000000U) +#define CMC_SRAMRET_RET25_SHIFT (25U) +/*! RET25 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET25(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET25_SHIFT)) & CMC_SRAMRET_RET25_MASK) + +#define CMC_SRAMRET_RET26_MASK (0x4000000U) +#define CMC_SRAMRET_RET26_SHIFT (26U) +/*! RET26 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET26(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET26_SHIFT)) & CMC_SRAMRET_RET26_MASK) + +#define CMC_SRAMRET_RET27_MASK (0x8000000U) +#define CMC_SRAMRET_RET27_SHIFT (27U) +/*! RET27 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET27(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET27_SHIFT)) & CMC_SRAMRET_RET27_MASK) + +#define CMC_SRAMRET_RET28_MASK (0x10000000U) +#define CMC_SRAMRET_RET28_SHIFT (28U) +/*! RET28 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET28(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET28_SHIFT)) & CMC_SRAMRET_RET28_MASK) + +#define CMC_SRAMRET_RET29_MASK (0x20000000U) +#define CMC_SRAMRET_RET29_SHIFT (29U) +/*! RET29 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET29(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET29_SHIFT)) & CMC_SRAMRET_RET29_MASK) + +#define CMC_SRAMRET_RET30_MASK (0x40000000U) +#define CMC_SRAMRET_RET30_SHIFT (30U) +/*! RET30 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET30(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET30_SHIFT)) & CMC_SRAMRET_RET30_MASK) + +#define CMC_SRAMRET_RET31_MASK (0x80000000U) +#define CMC_SRAMRET_RET31_SHIFT (31U) +/*! RET31 - SRAM Retention + * 0b0..Retains + * 0b1..Powers off + */ +#define CMC_SRAMRET_RET31(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET31_SHIFT)) & CMC_SRAMRET_RET31_MASK) +/*! @} */ + +/* The count of CMC_SRAMRET */ +#define CMC_SRAMRET_COUNT (1U) + +/*! @name FLASHCR - Flash Control */ +/*! @{ */ + +#define CMC_FLASHCR_FLASHDIS_MASK (0x1U) +#define CMC_FLASHCR_FLASHDIS_SHIFT (0U) +/*! FLASHDIS - Flash Disable + * 0b0..No effect + * 0b1..Flash memory is disabled + */ +#define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK) + +#define CMC_FLASHCR_FLASHDOZE_MASK (0x2U) +#define CMC_FLASHCR_FLASHDOZE_SHIFT (1U) +/*! FLASHDOZE - Flash Doze + * 0b0..No effect + * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) + */ +#define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) +/*! @} */ + +/*! @name BSR - BootROM Status Register */ +/*! @{ */ + +#define CMC_BSR_STAT_MASK (0xFFFFFFFFU) +#define CMC_BSR_STAT_SHIFT (0U) +/*! STAT - Provides status information written by the BootROM. */ +#define CMC_BSR_STAT(x) (((uint32_t)(((uint32_t)(x)) << CMC_BSR_STAT_SHIFT)) & CMC_BSR_STAT_MASK) +/*! @} */ + +/*! @name BLR - BootROM Lock Register */ +/*! @{ */ + +#define CMC_BLR_LOCK_MASK (0x7U) +#define CMC_BLR_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b010..BootROM Status and Lock Registers can be written + * 0b101..BootROM Status and Lock Registers cannot be written + */ +#define CMC_BLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_BLR_LOCK_SHIFT)) & CMC_BLR_LOCK_MASK) +/*! @} */ + +/*! @name CORECTL - Core Control */ +/*! @{ */ + +#define CMC_CORECTL_NPIE_MASK (0x1U) +#define CMC_CORECTL_NPIE_SHIFT (0U) +/*! NPIE - Non-maskable Pin Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK) +/*! @} */ + +/*! @name DBGCTL - Debug Control */ +/*! @{ */ + +#define CMC_DBGCTL_SOD_MASK (0x1U) +#define CMC_DBGCTL_SOD_SHIFT (0U) +/*! SOD - Sleep Or Debug + * 0b0..Remains enabled + * 0b1..Disabled + */ +#define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMC_Register_Masks */ + + +/* CMC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x50048000u) + /** Peripheral CMC0 base address */ + #define CMC0_BASE_NS (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Peripheral CMC0 base pointer */ + #define CMC0_NS ((CMC_Type *)CMC0_BASE_NS) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS_NS { CMC0_BASE_NS } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS_NS { CMC0_NS } +#else + /** Peripheral CMC0 base address */ + #define CMC0_BASE (0x40048000u) + /** Peripheral CMC0 base pointer */ + #define CMC0 ((CMC_Type *)CMC0_BASE) + /** Array initializer of CMC peripheral base addresses */ + #define CMC_BASE_ADDRS { CMC0_BASE } + /** Array initializer of CMC peripheral base pointers */ + #define CMC_BASE_PTRS { CMC0 } +#endif +/* Backward compatibility for CMC */ +#define CMC_SRAMDIS_DIS_MASK (0xFFFFFFFFU) +#define CMC_SRAMDIS_DIS_SHIFT (0U) +/*! DIS - SRAM Disable */ +#define CMC_SRAMDIS_DIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMDIS_DIS_SHIFT)) & CMC_SRAMDIS_DIS_MASK) + +#define CMC_SRAMRET_RET_MASK (0xFFFFFFFFU) +#define CMC_SRAMRET_RET_SHIFT (0U) +/*! RET - SRAM Retention */ +#define CMC_SRAMRET_RET(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRAMRET_RET_SHIFT)) & CMC_SRAMRET_RET_MASK) + + +/*! + * @} + */ /* end of group CMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ + } ACCESS8BIT; + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< Data, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ + } GPOLY_ACCESS8BIT; + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ + } CTRL_ACCESS8BIT; + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATALL - CRC_DATALL register */ +/*! @{ */ + +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ + +/*! @name DATALU - CRC_DATALU register */ +/*! @{ */ + +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ + +/*! @name DATAHL - CRC_DATAHL register */ +/*! @{ */ + +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ + +/*! @name DATAHU - CRC_DATAHU register */ +/*! @{ */ + +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ + +/*! @name DATAL - CRC_DATAL register */ +/*! @{ */ + +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ + +/*! @name DATAH - CRC_DATAH register */ +/*! @{ */ + +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +/*! LL - Lower Part of Low Byte */ +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) + +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +/*! LU - Upper Part of Low Byte */ +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) + +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +/*! HL - Lower Part of High Byte */ +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) + +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +/*! HU - Upper Part of High Byte */ +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ + +/*! @name GPOLYLL - CRC_GPOLYLL register */ +/*! @{ */ + +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ + +/*! @name GPOLYLU - CRC_GPOLYLU register */ +/*! @{ */ + +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ + +/*! @name GPOLYHL - CRC_GPOLYHL register */ +/*! @{ */ + +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ + +/*! @name GPOLYHU - CRC_GPOLYHU register */ +/*! @{ */ + +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ + +/*! @name GPOLYL - CRC_GPOLYL register */ +/*! @{ */ + +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ + +/*! @name GPOLYH - CRC_GPOLYH register */ +/*! @{ */ + +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ + +/*! @name GPOLY - Polynomial */ +/*! @{ */ + +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +/*! LOW - Low Half-Word */ +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) + +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +/*! HIGH - High Half-Word */ +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ + +/*! @name CTRLHU - CRC_CTRLHU register */ +/*! @{ */ + +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) + +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) + +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) + +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) + +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) + +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) + +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) + +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) + +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x500CB000u) + /** Peripheral CRC0 base address */ + #define CRC0_BASE_NS (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Peripheral CRC0 base pointer */ + #define CRC0_NS ((CRC_Type *)CRC0_BASE_NS) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS_NS { CRC0_BASE_NS } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS_NS { CRC0_NS } +#else + /** Peripheral CRC0 base address */ + #define CRC0_BASE (0x400CB000u) + /** Peripheral CRC0 base pointer */ + #define CRC0 ((CRC_Type *)CRC0_BASE) + /** Array initializer of CRC peripheral base addresses */ + #define CRC_BASE_ADDRS { CRC0_BASE } + /** Array initializer of CRC peripheral base pointers */ + #define CRC_BASE_PTRS { CRC0 } +#endif + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt, offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control, offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control, offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture, array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match, offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control, offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt Flag for Match Channel 0 Event */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt Flag for Match Channel 1 Event */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt Flag for Match Channel 2 Event */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt Flag for Match Channel 3 Event */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +#define CTIMER_TCR_AGCEN_MASK (0x10U) +#define CTIMER_TCR_AGCEN_SHIFT (4U) +/*! AGCEN - Allow Global Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) + +#define CTIMER_TCR_ATCEN_MASK (0x20U) +#define CTIMER_TCR_ATCEN_SHIFT (5U) +/*! ATCEN - Allow Trigger Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer Counter Value */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale Reload Value */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale Counter Value */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer Counter Match Value */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate Interrupt on Channel 0 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate Interrupt on Channel 1 Capture Event + * 0b0..Does not generates + * 0b1..Generates + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate Interrupt on Channel 2 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate Interrupt on Channel 3 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer Counter Capture Value */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter Timer Mode + * 0b00..Timer mode + * 0b01..Counter mode rising edge + * 0b10..Counter mode falling edge + * 0b11..Counter mode dual edge + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select + * 0b00..Channel 0, CAPn[0] for CTIMERn + * 0b01..Channel 1, CAPn[1] for CTIMERn + * 0b10..Channel 2, CAPn[2] for CTIMERn + * 0b11..Channel 3, CAPn[3] for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Capture Channel Enable */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge Select + * 0b000..Capture channel 0 rising edge + * 0b001..Capture channel 0 falling edge + * 0b010..Capture channel 1 rising edge + * 0b011..Capture channel 1 falling edge + * 0b100..Capture channel 2 rising edge + * 0b101..Capture channel 2 falling edge + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM Mode Enable for Channel 0 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM Mode Enable for Channel 1 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM Mode Enable for Channel 2 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM Mode Enable for Channel 3 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow */ +/*! @{ */ + +#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) +/*! MATCH_SHADOW - Timer Counter Match Shadow Value */ +#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x5000C000u) + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE_NS (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0_NS ((CTIMER_Type *)CTIMER0_BASE_NS) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x5000D000u) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE_NS (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1_NS ((CTIMER_Type *)CTIMER1_BASE_NS) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x5000E000u) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE_NS (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2_NS ((CTIMER_Type *)CTIMER2_BASE_NS) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x5000F000u) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE_NS (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3_NS ((CTIMER_Type *)CTIMER3_BASE_NS) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x50010000u) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE_NS (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4_NS ((CTIMER_Type *)CTIMER4_BASE_NS) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS_NS { CTIMER0_BASE_NS, CTIMER1_BASE_NS, CTIMER2_BASE_NS, CTIMER3_BASE_NS, CTIMER4_BASE_NS } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS_NS { CTIMER0_NS, CTIMER1_NS, CTIMER2_NS, CTIMER3_NS, CTIMER4_NS } +#else + /** Peripheral CTIMER0 base address */ + #define CTIMER0_BASE (0x4000C000u) + /** Peripheral CTIMER0 base pointer */ + #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) + /** Peripheral CTIMER1 base address */ + #define CTIMER1_BASE (0x4000D000u) + /** Peripheral CTIMER1 base pointer */ + #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) + /** Peripheral CTIMER2 base address */ + #define CTIMER2_BASE (0x4000E000u) + /** Peripheral CTIMER2 base pointer */ + #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) + /** Peripheral CTIMER3 base address */ + #define CTIMER3_BASE (0x4000F000u) + /** Peripheral CTIMER3 base pointer */ + #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) + /** Peripheral CTIMER4 base address */ + #define CTIMER4_BASE (0x40010000u) + /** Peripheral CTIMER4 base pointer */ + #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) + /** Array initializer of CTIMER peripheral base addresses */ + #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } + /** Array initializer of CTIMER peripheral base pointers */ + #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +#endif +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DIGTMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Peripheral_Access_Layer DIGTMP Peripheral Access Layer + * @{ + */ + +/** DIGTMP - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t LR; /**< Lock, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t TSR; /**< Tamper Seconds, offset: 0x20 */ + __IO uint32_t TER; /**< Tamper Enable, offset: 0x24 */ + __IO uint32_t PDR; /**< Pin Direction, offset: 0x28 */ + __IO uint32_t PPR; /**< Pin Polarity, offset: 0x2C */ + __IO uint32_t ATR[2]; /**< Active Tamper, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t PGFR[8]; /**< Pin Glitch Filter, array offset: 0x40, array step: 0x4 */ +} DIGTMP_Type; + +/* ---------------------------------------------------------------------------- + -- DIGTMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DIGTMP_Register_Masks DIGTMP Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define DIGTMP_CR_SWR_MASK (0x1U) +#define DIGTMP_CR_SWR_SHIFT (0U) +/*! SWR - Software Reset + * 0b0..No effect + * 0b1..Perform a software reset + */ +#define DIGTMP_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_SWR_SHIFT)) & DIGTMP_CR_SWR_MASK) + +#define DIGTMP_CR_DEN_MASK (0x2U) +#define DIGTMP_CR_DEN_SHIFT (1U) +/*! DEN - Digital Tamper Enable + * 0b0..Disables TDET clock and prescaler + * 0b1..Enables TDET clock and prescaler + */ +#define DIGTMP_CR_DEN(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DEN_SHIFT)) & DIGTMP_CR_DEN_MASK) + +#define DIGTMP_CR_TFSR_MASK (0x4U) +#define DIGTMP_CR_TFSR_SHIFT (2U) +/*! TFSR - Tamper Force System Reset + * 0b0..Do not force chip reset + * 0b1..Force chip reset + */ +#define DIGTMP_CR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_TFSR_SHIFT)) & DIGTMP_CR_TFSR_MASK) + +#define DIGTMP_CR_UM_MASK (0x8U) +#define DIGTMP_CR_UM_SHIFT (3U) +/*! UM - Update Mode + * 0b0..No effect + * 0b1..Allows the clearing of interrupts + */ +#define DIGTMP_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_UM_SHIFT)) & DIGTMP_CR_UM_MASK) + +#define DIGTMP_CR_ATCS0_MASK (0x10U) +#define DIGTMP_CR_ATCS0_SHIFT (4U) +/*! ATCS0 - Active Tamper Clock Source + * 0b0..1 Hz prescaler clock + * 0b1..64 Hz prescaler clock + */ +#define DIGTMP_CR_ATCS0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS0_SHIFT)) & DIGTMP_CR_ATCS0_MASK) + +#define DIGTMP_CR_ATCS1_MASK (0x20U) +#define DIGTMP_CR_ATCS1_SHIFT (5U) +/*! ATCS1 - Active Tamper Clock Source + * 0b0..1 Hz prescaler clock + * 0b1..64 Hz prescaler clock + */ +#define DIGTMP_CR_ATCS1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_ATCS1_SHIFT)) & DIGTMP_CR_ATCS1_MASK) + +#define DIGTMP_CR_DISTAM_MASK (0x100U) +#define DIGTMP_CR_DISTAM_SHIFT (8U) +/*! DISTAM - Disable Prescaler On Tamper + * 0b0..No effect + * 0b1..Automatically disables the prescaler after tamper detection + */ +#define DIGTMP_CR_DISTAM(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DISTAM_SHIFT)) & DIGTMP_CR_DISTAM_MASK) + +#define DIGTMP_CR_DPR_MASK (0xFFFE0000U) +#define DIGTMP_CR_DPR_SHIFT (17U) +/*! DPR - Digital Tamper Prescaler */ +#define DIGTMP_CR_DPR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_CR_DPR_SHIFT)) & DIGTMP_CR_DPR_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define DIGTMP_SR_DTF_MASK (0x1U) +#define DIGTMP_SR_DTF_SHIFT (0U) +/*! DTF - Digital Tamper Flag + * 0b0..TDET tampering not detected + * 0b1..TDET tampering detected + */ +#define DIGTMP_SR_DTF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_DTF_SHIFT)) & DIGTMP_SR_DTF_MASK) + +#define DIGTMP_SR_TAF_MASK (0x2U) +#define DIGTMP_SR_TAF_SHIFT (1U) +/*! TAF - Tamper Acknowledge Flag + * 0b0..Digital Tamper Flag (SR[DTF]) is clear or chip reset has not occurred after Digital Tamper Flag (SR[DTF]) was set. + * 0b1..Chip reset has occurred after Digital Tamper Flag (SR[DTF]) was set. + */ +#define DIGTMP_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TAF_SHIFT)) & DIGTMP_SR_TAF_MASK) + +#define DIGTMP_SR_TIF0_MASK (0x4U) +#define DIGTMP_SR_TIF0_SHIFT (2U) +/*! TIF0 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF0_SHIFT)) & DIGTMP_SR_TIF0_MASK) + +#define DIGTMP_SR_TIF1_MASK (0x8U) +#define DIGTMP_SR_TIF1_SHIFT (3U) +/*! TIF1 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF1_SHIFT)) & DIGTMP_SR_TIF1_MASK) + +#define DIGTMP_SR_TIF2_MASK (0x10U) +#define DIGTMP_SR_TIF2_SHIFT (4U) +/*! TIF2 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF2_SHIFT)) & DIGTMP_SR_TIF2_MASK) + +#define DIGTMP_SR_TIF3_MASK (0x20U) +#define DIGTMP_SR_TIF3_SHIFT (5U) +/*! TIF3 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF3_SHIFT)) & DIGTMP_SR_TIF3_MASK) + +#define DIGTMP_SR_TIF4_MASK (0x40U) +#define DIGTMP_SR_TIF4_SHIFT (6U) +/*! TIF4 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF4_SHIFT)) & DIGTMP_SR_TIF4_MASK) + +#define DIGTMP_SR_TIF5_MASK (0x80U) +#define DIGTMP_SR_TIF5_SHIFT (7U) +/*! TIF5 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF5_SHIFT)) & DIGTMP_SR_TIF5_MASK) + +#define DIGTMP_SR_TIF6_MASK (0x100U) +#define DIGTMP_SR_TIF6_SHIFT (8U) +/*! TIF6 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF6_SHIFT)) & DIGTMP_SR_TIF6_MASK) + +#define DIGTMP_SR_TIF7_MASK (0x200U) +#define DIGTMP_SR_TIF7_SHIFT (9U) +/*! TIF7 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF7_SHIFT)) & DIGTMP_SR_TIF7_MASK) + +#define DIGTMP_SR_TIF8_MASK (0x400U) +#define DIGTMP_SR_TIF8_SHIFT (10U) +/*! TIF8 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF8_SHIFT)) & DIGTMP_SR_TIF8_MASK) + +#define DIGTMP_SR_TIF9_MASK (0x800U) +#define DIGTMP_SR_TIF9_SHIFT (11U) +/*! TIF9 - Tamper Input n Flag + * 0b0..On-chip tamper not detected + * 0b1..On-chip tamper detected + */ +#define DIGTMP_SR_TIF9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TIF9_SHIFT)) & DIGTMP_SR_TIF9_MASK) + +#define DIGTMP_SR_TPF0_MASK (0x10000U) +#define DIGTMP_SR_TPF0_SHIFT (16U) +/*! TPF0 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF0_SHIFT)) & DIGTMP_SR_TPF0_MASK) + +#define DIGTMP_SR_TPF1_MASK (0x20000U) +#define DIGTMP_SR_TPF1_SHIFT (17U) +/*! TPF1 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF1_SHIFT)) & DIGTMP_SR_TPF1_MASK) + +#define DIGTMP_SR_TPF2_MASK (0x40000U) +#define DIGTMP_SR_TPF2_SHIFT (18U) +/*! TPF2 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF2_SHIFT)) & DIGTMP_SR_TPF2_MASK) + +#define DIGTMP_SR_TPF3_MASK (0x80000U) +#define DIGTMP_SR_TPF3_SHIFT (19U) +/*! TPF3 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF3_SHIFT)) & DIGTMP_SR_TPF3_MASK) + +#define DIGTMP_SR_TPF4_MASK (0x100000U) +#define DIGTMP_SR_TPF4_SHIFT (20U) +/*! TPF4 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF4_SHIFT)) & DIGTMP_SR_TPF4_MASK) + +#define DIGTMP_SR_TPF5_MASK (0x200000U) +#define DIGTMP_SR_TPF5_SHIFT (21U) +/*! TPF5 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF5_SHIFT)) & DIGTMP_SR_TPF5_MASK) + +#define DIGTMP_SR_TPF6_MASK (0x400000U) +#define DIGTMP_SR_TPF6_SHIFT (22U) +/*! TPF6 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF6_SHIFT)) & DIGTMP_SR_TPF6_MASK) + +#define DIGTMP_SR_TPF7_MASK (0x800000U) +#define DIGTMP_SR_TPF7_SHIFT (23U) +/*! TPF7 - Tamper Pin n Flag + * 0b0..Pin tamper not detected + * 0b1..Pin tamper detected + */ +#define DIGTMP_SR_TPF7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_SR_TPF7_SHIFT)) & DIGTMP_SR_TPF7_MASK) +/*! @} */ + +/*! @name LR - Lock */ +/*! @{ */ + +#define DIGTMP_LR_CRL_MASK (0x10U) +#define DIGTMP_LR_CRL_SHIFT (4U) +/*! CRL - Control Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_CRL_SHIFT)) & DIGTMP_LR_CRL_MASK) + +#define DIGTMP_LR_SRL_MASK (0x20U) +#define DIGTMP_LR_SRL_SHIFT (5U) +/*! SRL - Status Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_SRL_SHIFT)) & DIGTMP_LR_SRL_MASK) + +#define DIGTMP_LR_LRL_MASK (0x40U) +#define DIGTMP_LR_LRL_SHIFT (6U) +/*! LRL - Lock Register Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_LRL_SHIFT)) & DIGTMP_LR_LRL_MASK) + +#define DIGTMP_LR_IEL_MASK (0x80U) +#define DIGTMP_LR_IEL_SHIFT (7U) +/*! IEL - Interrupt Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_IEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_IEL_SHIFT)) & DIGTMP_LR_IEL_MASK) + +#define DIGTMP_LR_TSL_MASK (0x100U) +#define DIGTMP_LR_TSL_SHIFT (8U) +/*! TSL - Tamper Seconds Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TSL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TSL_SHIFT)) & DIGTMP_LR_TSL_MASK) + +#define DIGTMP_LR_TEL_MASK (0x200U) +#define DIGTMP_LR_TEL_SHIFT (9U) +/*! TEL - Tamper Enable Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_TEL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_TEL_SHIFT)) & DIGTMP_LR_TEL_MASK) + +#define DIGTMP_LR_PDL_MASK (0x400U) +#define DIGTMP_LR_PDL_SHIFT (10U) +/*! PDL - Pin Direction Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_PDL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PDL_SHIFT)) & DIGTMP_LR_PDL_MASK) + +#define DIGTMP_LR_PPL_MASK (0x800U) +#define DIGTMP_LR_PPL_SHIFT (11U) +/*! PPL - Pin Polarity Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_PPL(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_PPL_SHIFT)) & DIGTMP_LR_PPL_MASK) + +#define DIGTMP_LR_ATL0_MASK (0x1000U) +#define DIGTMP_LR_ATL0_SHIFT (12U) +/*! ATL0 - Active Tamper Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_ATL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL0_SHIFT)) & DIGTMP_LR_ATL0_MASK) + +#define DIGTMP_LR_ATL1_MASK (0x2000U) +#define DIGTMP_LR_ATL1_SHIFT (13U) +/*! ATL1 - Active Tamper Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_ATL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_ATL1_SHIFT)) & DIGTMP_LR_ATL1_MASK) + +#define DIGTMP_LR_GFL0_MASK (0x10000U) +#define DIGTMP_LR_GFL0_SHIFT (16U) +/*! GFL0 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL0_SHIFT)) & DIGTMP_LR_GFL0_MASK) + +#define DIGTMP_LR_GFL1_MASK (0x20000U) +#define DIGTMP_LR_GFL1_SHIFT (17U) +/*! GFL1 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL1_SHIFT)) & DIGTMP_LR_GFL1_MASK) + +#define DIGTMP_LR_GFL2_MASK (0x40000U) +#define DIGTMP_LR_GFL2_SHIFT (18U) +/*! GFL2 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL2_SHIFT)) & DIGTMP_LR_GFL2_MASK) + +#define DIGTMP_LR_GFL3_MASK (0x80000U) +#define DIGTMP_LR_GFL3_SHIFT (19U) +/*! GFL3 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL3_SHIFT)) & DIGTMP_LR_GFL3_MASK) + +#define DIGTMP_LR_GFL4_MASK (0x100000U) +#define DIGTMP_LR_GFL4_SHIFT (20U) +/*! GFL4 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL4_SHIFT)) & DIGTMP_LR_GFL4_MASK) + +#define DIGTMP_LR_GFL5_MASK (0x200000U) +#define DIGTMP_LR_GFL5_SHIFT (21U) +/*! GFL5 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL5_SHIFT)) & DIGTMP_LR_GFL5_MASK) + +#define DIGTMP_LR_GFL6_MASK (0x400000U) +#define DIGTMP_LR_GFL6_SHIFT (22U) +/*! GFL6 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL6_SHIFT)) & DIGTMP_LR_GFL6_MASK) + +#define DIGTMP_LR_GFL7_MASK (0x800000U) +#define DIGTMP_LR_GFL7_SHIFT (23U) +/*! GFL7 - Glitch Filter Lock + * 0b0..Locked and writes are ignored + * 0b1..Not locked and writes complete as normal + */ +#define DIGTMP_LR_GFL7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_LR_GFL7_SHIFT)) & DIGTMP_LR_GFL7_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define DIGTMP_IER_DTIE_MASK (0x1U) +#define DIGTMP_IER_DTIE_SHIFT (0U) +/*! DTIE - Digital Tamper Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_DTIE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_DTIE_SHIFT)) & DIGTMP_IER_DTIE_MASK) + +#define DIGTMP_IER_TIIE0_MASK (0x4U) +#define DIGTMP_IER_TIIE0_SHIFT (2U) +/*! TIIE0 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE0_SHIFT)) & DIGTMP_IER_TIIE0_MASK) + +#define DIGTMP_IER_TIIE1_MASK (0x8U) +#define DIGTMP_IER_TIIE1_SHIFT (3U) +/*! TIIE1 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE1_SHIFT)) & DIGTMP_IER_TIIE1_MASK) + +#define DIGTMP_IER_TIIE2_MASK (0x10U) +#define DIGTMP_IER_TIIE2_SHIFT (4U) +/*! TIIE2 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE2_SHIFT)) & DIGTMP_IER_TIIE2_MASK) + +#define DIGTMP_IER_TIIE3_MASK (0x20U) +#define DIGTMP_IER_TIIE3_SHIFT (5U) +/*! TIIE3 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE3_SHIFT)) & DIGTMP_IER_TIIE3_MASK) + +#define DIGTMP_IER_TIIE4_MASK (0x40U) +#define DIGTMP_IER_TIIE4_SHIFT (6U) +/*! TIIE4 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE4_SHIFT)) & DIGTMP_IER_TIIE4_MASK) + +#define DIGTMP_IER_TIIE5_MASK (0x80U) +#define DIGTMP_IER_TIIE5_SHIFT (7U) +/*! TIIE5 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE5_SHIFT)) & DIGTMP_IER_TIIE5_MASK) + +#define DIGTMP_IER_TIIE6_MASK (0x100U) +#define DIGTMP_IER_TIIE6_SHIFT (8U) +/*! TIIE6 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE6_SHIFT)) & DIGTMP_IER_TIIE6_MASK) + +#define DIGTMP_IER_TIIE7_MASK (0x200U) +#define DIGTMP_IER_TIIE7_SHIFT (9U) +/*! TIIE7 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE7_SHIFT)) & DIGTMP_IER_TIIE7_MASK) + +#define DIGTMP_IER_TIIE8_MASK (0x400U) +#define DIGTMP_IER_TIIE8_SHIFT (10U) +/*! TIIE8 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE8_SHIFT)) & DIGTMP_IER_TIIE8_MASK) + +#define DIGTMP_IER_TIIE9_MASK (0x800U) +#define DIGTMP_IER_TIIE9_SHIFT (11U) +/*! TIIE9 - Tamper Input n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TIIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TIIE9_SHIFT)) & DIGTMP_IER_TIIE9_MASK) + +#define DIGTMP_IER_TPIE0_MASK (0x10000U) +#define DIGTMP_IER_TPIE0_SHIFT (16U) +/*! TPIE0 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE0_SHIFT)) & DIGTMP_IER_TPIE0_MASK) + +#define DIGTMP_IER_TPIE1_MASK (0x20000U) +#define DIGTMP_IER_TPIE1_SHIFT (17U) +/*! TPIE1 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE1_SHIFT)) & DIGTMP_IER_TPIE1_MASK) + +#define DIGTMP_IER_TPIE2_MASK (0x40000U) +#define DIGTMP_IER_TPIE2_SHIFT (18U) +/*! TPIE2 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE2_SHIFT)) & DIGTMP_IER_TPIE2_MASK) + +#define DIGTMP_IER_TPIE3_MASK (0x80000U) +#define DIGTMP_IER_TPIE3_SHIFT (19U) +/*! TPIE3 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE3_SHIFT)) & DIGTMP_IER_TPIE3_MASK) + +#define DIGTMP_IER_TPIE4_MASK (0x100000U) +#define DIGTMP_IER_TPIE4_SHIFT (20U) +/*! TPIE4 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE4_SHIFT)) & DIGTMP_IER_TPIE4_MASK) + +#define DIGTMP_IER_TPIE5_MASK (0x200000U) +#define DIGTMP_IER_TPIE5_SHIFT (21U) +/*! TPIE5 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE5_SHIFT)) & DIGTMP_IER_TPIE5_MASK) + +#define DIGTMP_IER_TPIE6_MASK (0x400000U) +#define DIGTMP_IER_TPIE6_SHIFT (22U) +/*! TPIE6 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE6_SHIFT)) & DIGTMP_IER_TPIE6_MASK) + +#define DIGTMP_IER_TPIE7_MASK (0x800000U) +#define DIGTMP_IER_TPIE7_SHIFT (23U) +/*! TPIE7 - Tamper Pin n Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_IER_TPIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_IER_TPIE7_SHIFT)) & DIGTMP_IER_TPIE7_MASK) +/*! @} */ + +/*! @name TSR - Tamper Seconds */ +/*! @{ */ + +#define DIGTMP_TSR_TTS_MASK (0xFFFFFFFFU) +#define DIGTMP_TSR_TTS_SHIFT (0U) +/*! TTS - Tamper Time Seconds */ +#define DIGTMP_TSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TSR_TTS_SHIFT)) & DIGTMP_TSR_TTS_MASK) +/*! @} */ + +/*! @name TER - Tamper Enable */ +/*! @{ */ + +#define DIGTMP_TER_TIE0_MASK (0x4U) +#define DIGTMP_TER_TIE0_SHIFT (2U) +/*! TIE0 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE0_SHIFT)) & DIGTMP_TER_TIE0_MASK) + +#define DIGTMP_TER_TIE1_MASK (0x8U) +#define DIGTMP_TER_TIE1_SHIFT (3U) +/*! TIE1 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE1_SHIFT)) & DIGTMP_TER_TIE1_MASK) + +#define DIGTMP_TER_TIE2_MASK (0x10U) +#define DIGTMP_TER_TIE2_SHIFT (4U) +/*! TIE2 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE2_SHIFT)) & DIGTMP_TER_TIE2_MASK) + +#define DIGTMP_TER_TIE3_MASK (0x20U) +#define DIGTMP_TER_TIE3_SHIFT (5U) +/*! TIE3 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE3_SHIFT)) & DIGTMP_TER_TIE3_MASK) + +#define DIGTMP_TER_TIE4_MASK (0x40U) +#define DIGTMP_TER_TIE4_SHIFT (6U) +/*! TIE4 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE4_SHIFT)) & DIGTMP_TER_TIE4_MASK) + +#define DIGTMP_TER_TIE5_MASK (0x80U) +#define DIGTMP_TER_TIE5_SHIFT (7U) +/*! TIE5 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE5_SHIFT)) & DIGTMP_TER_TIE5_MASK) + +#define DIGTMP_TER_TIE6_MASK (0x100U) +#define DIGTMP_TER_TIE6_SHIFT (8U) +/*! TIE6 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE6_SHIFT)) & DIGTMP_TER_TIE6_MASK) + +#define DIGTMP_TER_TIE7_MASK (0x200U) +#define DIGTMP_TER_TIE7_SHIFT (9U) +/*! TIE7 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE7_SHIFT)) & DIGTMP_TER_TIE7_MASK) + +#define DIGTMP_TER_TIE8_MASK (0x400U) +#define DIGTMP_TER_TIE8_SHIFT (10U) +/*! TIE8 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE8(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE8_SHIFT)) & DIGTMP_TER_TIE8_MASK) + +#define DIGTMP_TER_TIE9_MASK (0x800U) +#define DIGTMP_TER_TIE9_SHIFT (11U) +/*! TIE9 - Tamper Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TIE9(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TIE9_SHIFT)) & DIGTMP_TER_TIE9_MASK) + +#define DIGTMP_TER_TPE0_MASK (0x10000U) +#define DIGTMP_TER_TPE0_SHIFT (16U) +/*! TPE0 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE0_SHIFT)) & DIGTMP_TER_TPE0_MASK) + +#define DIGTMP_TER_TPE1_MASK (0x20000U) +#define DIGTMP_TER_TPE1_SHIFT (17U) +/*! TPE1 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE1_SHIFT)) & DIGTMP_TER_TPE1_MASK) + +#define DIGTMP_TER_TPE2_MASK (0x40000U) +#define DIGTMP_TER_TPE2_SHIFT (18U) +/*! TPE2 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE2_SHIFT)) & DIGTMP_TER_TPE2_MASK) + +#define DIGTMP_TER_TPE3_MASK (0x80000U) +#define DIGTMP_TER_TPE3_SHIFT (19U) +/*! TPE3 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE3_SHIFT)) & DIGTMP_TER_TPE3_MASK) + +#define DIGTMP_TER_TPE4_MASK (0x100000U) +#define DIGTMP_TER_TPE4_SHIFT (20U) +/*! TPE4 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE4_SHIFT)) & DIGTMP_TER_TPE4_MASK) + +#define DIGTMP_TER_TPE5_MASK (0x200000U) +#define DIGTMP_TER_TPE5_SHIFT (21U) +/*! TPE5 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE5_SHIFT)) & DIGTMP_TER_TPE5_MASK) + +#define DIGTMP_TER_TPE6_MASK (0x400000U) +#define DIGTMP_TER_TPE6_SHIFT (22U) +/*! TPE6 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE6_SHIFT)) & DIGTMP_TER_TPE6_MASK) + +#define DIGTMP_TER_TPE7_MASK (0x800000U) +#define DIGTMP_TER_TPE7_SHIFT (23U) +/*! TPE7 - Tamper Pin Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_TER_TPE7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_TER_TPE7_SHIFT)) & DIGTMP_TER_TPE7_MASK) +/*! @} */ + +/*! @name PDR - Pin Direction */ +/*! @{ */ + +#define DIGTMP_PDR_TPD0_MASK (0x1U) +#define DIGTMP_PDR_TPD0_SHIFT (0U) +/*! TPD0 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD0_SHIFT)) & DIGTMP_PDR_TPD0_MASK) + +#define DIGTMP_PDR_TPD1_MASK (0x2U) +#define DIGTMP_PDR_TPD1_SHIFT (1U) +/*! TPD1 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD1_SHIFT)) & DIGTMP_PDR_TPD1_MASK) + +#define DIGTMP_PDR_TPD2_MASK (0x4U) +#define DIGTMP_PDR_TPD2_SHIFT (2U) +/*! TPD2 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD2_SHIFT)) & DIGTMP_PDR_TPD2_MASK) + +#define DIGTMP_PDR_TPD3_MASK (0x8U) +#define DIGTMP_PDR_TPD3_SHIFT (3U) +/*! TPD3 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD3_SHIFT)) & DIGTMP_PDR_TPD3_MASK) + +#define DIGTMP_PDR_TPD4_MASK (0x10U) +#define DIGTMP_PDR_TPD4_SHIFT (4U) +/*! TPD4 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD4_SHIFT)) & DIGTMP_PDR_TPD4_MASK) + +#define DIGTMP_PDR_TPD5_MASK (0x20U) +#define DIGTMP_PDR_TPD5_SHIFT (5U) +/*! TPD5 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD5_SHIFT)) & DIGTMP_PDR_TPD5_MASK) + +#define DIGTMP_PDR_TPD6_MASK (0x40U) +#define DIGTMP_PDR_TPD6_SHIFT (6U) +/*! TPD6 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD6_SHIFT)) & DIGTMP_PDR_TPD6_MASK) + +#define DIGTMP_PDR_TPD7_MASK (0x80U) +#define DIGTMP_PDR_TPD7_SHIFT (7U) +/*! TPD7 - Tamper Pin Direction + * 0b0..Input + * 0b1..Output and drives the inverse of the expected value (tamper pin is asserted) + */ +#define DIGTMP_PDR_TPD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPD7_SHIFT)) & DIGTMP_PDR_TPD7_MASK) + +#define DIGTMP_PDR_TPOD0_MASK (0x10000U) +#define DIGTMP_PDR_TPOD0_SHIFT (16U) +/*! TPOD0 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD0_SHIFT)) & DIGTMP_PDR_TPOD0_MASK) + +#define DIGTMP_PDR_TPOD1_MASK (0x20000U) +#define DIGTMP_PDR_TPOD1_SHIFT (17U) +/*! TPOD1 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD1_SHIFT)) & DIGTMP_PDR_TPOD1_MASK) + +#define DIGTMP_PDR_TPOD2_MASK (0x40000U) +#define DIGTMP_PDR_TPOD2_SHIFT (18U) +/*! TPOD2 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD2_SHIFT)) & DIGTMP_PDR_TPOD2_MASK) + +#define DIGTMP_PDR_TPOD3_MASK (0x80000U) +#define DIGTMP_PDR_TPOD3_SHIFT (19U) +/*! TPOD3 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD3_SHIFT)) & DIGTMP_PDR_TPOD3_MASK) + +#define DIGTMP_PDR_TPOD4_MASK (0x100000U) +#define DIGTMP_PDR_TPOD4_SHIFT (20U) +/*! TPOD4 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD4_SHIFT)) & DIGTMP_PDR_TPOD4_MASK) + +#define DIGTMP_PDR_TPOD5_MASK (0x200000U) +#define DIGTMP_PDR_TPOD5_SHIFT (21U) +/*! TPOD5 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD5_SHIFT)) & DIGTMP_PDR_TPOD5_MASK) + +#define DIGTMP_PDR_TPOD6_MASK (0x400000U) +#define DIGTMP_PDR_TPOD6_SHIFT (22U) +/*! TPOD6 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD6_SHIFT)) & DIGTMP_PDR_TPOD6_MASK) + +#define DIGTMP_PDR_TPOD7_MASK (0x800000U) +#define DIGTMP_PDR_TPOD7_SHIFT (23U) +/*! TPOD7 - Tamper Pin Output Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PDR_TPOD7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PDR_TPOD7_SHIFT)) & DIGTMP_PDR_TPOD7_MASK) +/*! @} */ + +/*! @name PPR - Pin Polarity */ +/*! @{ */ + +#define DIGTMP_PPR_TPP0_MASK (0x1U) +#define DIGTMP_PPR_TPP0_SHIFT (0U) +/*! TPP0 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP0_SHIFT)) & DIGTMP_PPR_TPP0_MASK) + +#define DIGTMP_PPR_TPP1_MASK (0x2U) +#define DIGTMP_PPR_TPP1_SHIFT (1U) +/*! TPP1 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP1_SHIFT)) & DIGTMP_PPR_TPP1_MASK) + +#define DIGTMP_PPR_TPP2_MASK (0x4U) +#define DIGTMP_PPR_TPP2_SHIFT (2U) +/*! TPP2 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP2_SHIFT)) & DIGTMP_PPR_TPP2_MASK) + +#define DIGTMP_PPR_TPP3_MASK (0x8U) +#define DIGTMP_PPR_TPP3_SHIFT (3U) +/*! TPP3 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP3_SHIFT)) & DIGTMP_PPR_TPP3_MASK) + +#define DIGTMP_PPR_TPP4_MASK (0x10U) +#define DIGTMP_PPR_TPP4_SHIFT (4U) +/*! TPP4 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP4_SHIFT)) & DIGTMP_PPR_TPP4_MASK) + +#define DIGTMP_PPR_TPP5_MASK (0x20U) +#define DIGTMP_PPR_TPP5_SHIFT (5U) +/*! TPP5 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP5_SHIFT)) & DIGTMP_PPR_TPP5_MASK) + +#define DIGTMP_PPR_TPP6_MASK (0x40U) +#define DIGTMP_PPR_TPP6_SHIFT (6U) +/*! TPP6 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP6_SHIFT)) & DIGTMP_PPR_TPP6_MASK) + +#define DIGTMP_PPR_TPP7_MASK (0x80U) +#define DIGTMP_PPR_TPP7_SHIFT (7U) +/*! TPP7 - Tamper Pin n Polarity + * 0b0..Not inverted + * 0b1..Inverted + */ +#define DIGTMP_PPR_TPP7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPP7_SHIFT)) & DIGTMP_PPR_TPP7_MASK) + +#define DIGTMP_PPR_TPID0_MASK (0x10000U) +#define DIGTMP_PPR_TPID0_SHIFT (16U) +/*! TPID0 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID0(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID0_SHIFT)) & DIGTMP_PPR_TPID0_MASK) + +#define DIGTMP_PPR_TPID1_MASK (0x20000U) +#define DIGTMP_PPR_TPID1_SHIFT (17U) +/*! TPID1 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID1(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID1_SHIFT)) & DIGTMP_PPR_TPID1_MASK) + +#define DIGTMP_PPR_TPID2_MASK (0x40000U) +#define DIGTMP_PPR_TPID2_SHIFT (18U) +/*! TPID2 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID2(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID2_SHIFT)) & DIGTMP_PPR_TPID2_MASK) + +#define DIGTMP_PPR_TPID3_MASK (0x80000U) +#define DIGTMP_PPR_TPID3_SHIFT (19U) +/*! TPID3 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID3(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID3_SHIFT)) & DIGTMP_PPR_TPID3_MASK) + +#define DIGTMP_PPR_TPID4_MASK (0x100000U) +#define DIGTMP_PPR_TPID4_SHIFT (20U) +/*! TPID4 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID4(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID4_SHIFT)) & DIGTMP_PPR_TPID4_MASK) + +#define DIGTMP_PPR_TPID5_MASK (0x200000U) +#define DIGTMP_PPR_TPID5_SHIFT (21U) +/*! TPID5 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID5(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID5_SHIFT)) & DIGTMP_PPR_TPID5_MASK) + +#define DIGTMP_PPR_TPID6_MASK (0x400000U) +#define DIGTMP_PPR_TPID6_SHIFT (22U) +/*! TPID6 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID6(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID6_SHIFT)) & DIGTMP_PPR_TPID6_MASK) + +#define DIGTMP_PPR_TPID7_MASK (0x800000U) +#define DIGTMP_PPR_TPID7_SHIFT (23U) +/*! TPID7 - Tamper Pin n Input Data + * 0b0..Zero + * 0b1..One + */ +#define DIGTMP_PPR_TPID7(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PPR_TPID7_SHIFT)) & DIGTMP_PPR_TPID7_MASK) +/*! @} */ + +/*! @name ATR - Active Tamper */ +/*! @{ */ + +#define DIGTMP_ATR_ATSR_MASK (0xFFFFU) +#define DIGTMP_ATR_ATSR_SHIFT (0U) +/*! ATSR - Active Tamper Shift Register */ +#define DIGTMP_ATR_ATSR(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATSR_SHIFT)) & DIGTMP_ATR_ATSR_MASK) + +#define DIGTMP_ATR_ATP_MASK (0xFFFF0000U) +#define DIGTMP_ATR_ATP_SHIFT (16U) +/*! ATP - Active Tamper Polynomial */ +#define DIGTMP_ATR_ATP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_ATR_ATP_SHIFT)) & DIGTMP_ATR_ATP_MASK) +/*! @} */ + +/* The count of DIGTMP_ATR */ +#define DIGTMP_ATR_COUNT (2U) + +/*! @name PGFR - Pin Glitch Filter */ +/*! @{ */ + +#define DIGTMP_PGFR_GFW_MASK (0x3FU) +#define DIGTMP_PGFR_GFW_SHIFT (0U) +/*! GFW - Glitch Filter Width */ +#define DIGTMP_PGFR_GFW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFW_SHIFT)) & DIGTMP_PGFR_GFW_MASK) + +#define DIGTMP_PGFR_GFP_MASK (0x40U) +#define DIGTMP_PGFR_GFP_SHIFT (6U) +/*! GFP - Glitch Filter Prescaler + * 0b0..512 Hz prescaler clock + * 0b1..32.768 kHz clock + */ +#define DIGTMP_PGFR_GFP(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFP_SHIFT)) & DIGTMP_PGFR_GFP_MASK) + +#define DIGTMP_PGFR_GFE_MASK (0x80U) +#define DIGTMP_PGFR_GFE_SHIFT (7U) +/*! GFE - Glitch Filter Enable + * 0b0..Bypasses + * 0b1..Enables + */ +#define DIGTMP_PGFR_GFE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_GFE_SHIFT)) & DIGTMP_PGFR_GFE_MASK) + +#define DIGTMP_PGFR_TPSW_MASK (0x300U) +#define DIGTMP_PGFR_TPSW_SHIFT (8U) +/*! TPSW - Tamper Pin Sample Width + * 0b00..Continuous monitoring, pin sampling disabled + * 0b01..2 cycles for pull enable and 1 cycle for input buffer enable + * 0b10..4 cycles for pull enable and 2 cycles for input buffer enable + * 0b11..8 cycles for pull enable and 4 cycles for input buffer enable + */ +#define DIGTMP_PGFR_TPSW(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSW_SHIFT)) & DIGTMP_PGFR_TPSW_MASK) + +#define DIGTMP_PGFR_TPSF_MASK (0xC00U) +#define DIGTMP_PGFR_TPSF_SHIFT (10U) +/*! TPSF - Tamper Pin Sample Frequency + * 0b00..Every 8 cycles + * 0b01..Every 32 cycles + * 0b10..Every 128 cycles + * 0b11..Every 512 cycles + */ +#define DIGTMP_PGFR_TPSF(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPSF_SHIFT)) & DIGTMP_PGFR_TPSF_MASK) + +#define DIGTMP_PGFR_TPEX_MASK (0x30000U) +#define DIGTMP_PGFR_TPEX_SHIFT (16U) +/*! TPEX - Tamper Pin Expected + * 0b00..Zero/passive tamper + * 0b01..Active Tamper 0 output + * 0b10..Active Tamper 1 output + * 0b11..Active Tamper 0 output XORed with Active Tamper 1 output + */ +#define DIGTMP_PGFR_TPEX(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPEX_SHIFT)) & DIGTMP_PGFR_TPEX_MASK) + +#define DIGTMP_PGFR_TPE_MASK (0x1000000U) +#define DIGTMP_PGFR_TPE_SHIFT (24U) +/*! TPE - Tamper Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define DIGTMP_PGFR_TPE(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPE_SHIFT)) & DIGTMP_PGFR_TPE_MASK) + +#define DIGTMP_PGFR_TPS_MASK (0x2000000U) +#define DIGTMP_PGFR_TPS_SHIFT (25U) +/*! TPS - Tamper Pull Select + * 0b0..Asserts + * 0b1..Negates + */ +#define DIGTMP_PGFR_TPS(x) (((uint32_t)(((uint32_t)(x)) << DIGTMP_PGFR_TPS_SHIFT)) & DIGTMP_PGFR_TPS_MASK) +/*! @} */ + +/* The count of DIGTMP_PGFR */ +#define DIGTMP_PGFR_COUNT (8U) + + +/*! + * @} + */ /* end of group DIGTMP_Register_Masks */ + + +/* DIGTMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x50058000u) + /** Peripheral TDET0 base address */ + #define TDET0_BASE_NS (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Peripheral TDET0 base pointer */ + #define TDET0_NS ((DIGTMP_Type *)TDET0_BASE_NS) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS_NS { TDET0_BASE_NS } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS_NS { TDET0_NS } +#else + /** Peripheral TDET0 base address */ + #define TDET0_BASE (0x40058000u) + /** Peripheral TDET0 base pointer */ + #define TDET0 ((DIGTMP_Type *)TDET0_BASE) + /** Array initializer of DIGTMP peripheral base addresses */ + #define DIGTMP_BASE_ADDRS { TDET0_BASE } + /** Array initializer of DIGTMP peripheral base pointers */ + #define DIGTMP_BASE_PTRS { TDET0 } +#endif + +/*! + * @} + */ /* end of group DIGTMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DM_Peripheral_Access_Layer DM Peripheral Access Layer + * @{ + */ + +/** DM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */ + __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification, offset: 0xFC */ +} DM_Type; + +/* ---------------------------------------------------------------------------- + -- DM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DM_Register_Masks DM Register Masks + * @{ + */ + +/*! @name CSW - Command and Status Word */ +/*! @{ */ + +#define DM_CSW_RESYNCH_REQ_MASK (0x1U) +#define DM_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Resynchronization Request + * 0b0..No request + * 0b1..Request for resynchronization + */ +#define DM_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_RESYNCH_REQ_SHIFT)) & DM_CSW_RESYNCH_REQ_MASK) + +#define DM_CSW_REQ_PENDING_MASK (0x2U) +#define DM_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request Pending + * 0b0..No request pending + * 0b1..Request for resynchronization pending + */ +#define DM_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_REQ_PENDING_SHIFT)) & DM_CSW_REQ_PENDING_MASK) + +#define DM_CSW_DBG_OR_ERR_MASK (0x4U) +#define DM_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - DBGMB Overrun Error + * 0b0..No DBGMB Overrun error + * 0b1..DBGMB overrun error. A DBGMB overrun occurred. + */ +#define DM_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_DBG_OR_ERR_SHIFT)) & DM_CSW_DBG_OR_ERR_MASK) + +#define DM_CSW_AHB_OR_ERR_MASK (0x8U) +#define DM_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB Overrun Error + * 0b0..No AHB Overrun Error + * 0b1..AHB Overrun Error. An AHB overrun occurred. + */ +#define DM_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_AHB_OR_ERR_SHIFT)) & DM_CSW_AHB_OR_ERR_MASK) + +#define DM_CSW_SOFT_RESET_MASK (0x10U) +#define DM_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset */ +#define DM_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_SOFT_RESET_SHIFT)) & DM_CSW_SOFT_RESET_MASK) + +#define DM_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DM_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Chip Reset Request */ +#define DM_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DM_CSW_CHIP_RESET_REQ_SHIFT)) & DM_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - Request Value */ +/*! @{ */ + +#define DM_REQUEST_REQUEST_MASK (0xFFFFFFFFU) +#define DM_REQUEST_REQUEST_SHIFT (0U) +/*! REQUEST - Request Value */ +#define DM_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DM_REQUEST_REQUEST_SHIFT)) & DM_REQUEST_REQUEST_MASK) +/*! @} */ + +/*! @name RETURN - Return Value */ +/*! @{ */ + +#define DM_RETURN_RET_MASK (0xFFFFFFFFU) +#define DM_RETURN_RET_SHIFT (0U) +/*! RET - Return Value */ +#define DM_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DM_RETURN_RET_SHIFT)) & DM_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define DM_ID_ID_MASK (0xFFFFFFFFU) +#define DM_ID_ID_SHIFT (0U) +/*! ID - Identification Value */ +#define DM_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DM_ID_ID_SHIFT)) & DM_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DM_Register_Masks */ + + +/* DM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DM0 base address */ + #define DM0_BASE (0x500BD000u) + /** Peripheral DM0 base address */ + #define DM0_BASE_NS (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Peripheral DM0 base pointer */ + #define DM0_NS ((DM_Type *)DM0_BASE_NS) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS_NS { DM0_BASE_NS } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS_NS { DM0_NS } +#else + /** Peripheral DM0 base address */ + #define DM0_BASE (0x400BD000u) + /** Peripheral DM0 base pointer */ + #define DM0 ((DM_Type *)DM0_BASE) + /** Array initializer of DM peripheral base addresses */ + #define DM_BASE_ADDRS { DM0_BASE } + /** Array initializer of DM peripheral base pointers */ + #define DM_BASE_PTRS { DM0 } +#endif + +/*! + * @} + */ /* end of group DM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[16]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4, irregular array, not all indices are valid */ + uint8_t RESERVED_1[3776]; + struct { /* offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000, irregular array, not all indices are valid */ + uint8_t RESERVED_0[8]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000, irregular array, not all indices are valid */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000, irregular array, not all indices are valid */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000, irregular array, not all indices are valid */ + union { /* offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000, irregular array, not all indices are valid */ + }; + uint8_t RESERVED_1[4032]; + } CH[16]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication disabled for all channels + * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0xF000000U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0xFFFFU) /* Merged from fields with different position or width, of widths (8, 16), largest definition used */ +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) /* Merged from fields with different position or width, of widths (8, 16), largest definition used */ +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (16U) + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define DMA_CH_CSR_ERQ_MASK (0x1U) +#define DMA_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) + +#define DMA_CH_CSR_EARQ_MASK (0x2U) +#define DMA_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) + +#define DMA_CH_CSR_EEI_MASK (0x4U) +#define DMA_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) + +#define DMA_CH_CSR_EBW_MASK (0x8U) +#define DMA_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) + +#define DMA_CH_CSR_DONE_MASK (0x40000000U) +#define DMA_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) + +#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA_CH_CSR */ +#define DMA_CH_CSR_COUNT (16U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define DMA_CH_ES_DBE_MASK (0x1U) +#define DMA_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) + +#define DMA_CH_ES_SBE_MASK (0x2U) +#define DMA_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) + +#define DMA_CH_ES_SGE_MASK (0x4U) +#define DMA_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) + +#define DMA_CH_ES_NCE_MASK (0x8U) +#define DMA_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) + +#define DMA_CH_ES_DOE_MASK (0x10U) +#define DMA_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) + +#define DMA_CH_ES_DAE_MASK (0x20U) +#define DMA_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) + +#define DMA_CH_ES_SOE_MASK (0x40U) +#define DMA_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) + +#define DMA_CH_ES_SAE_MASK (0x80U) +#define DMA_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) + +#define DMA_CH_ES_ERR_MASK (0x80000000U) +#define DMA_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA_CH_ES */ +#define DMA_CH_ES_COUNT (16U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define DMA_CH_INT_INT_MASK (0x1U) +#define DMA_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA_CH_INT */ +#define DMA_CH_INT_COUNT (16U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define DMA_CH_SBR_MID_MASK (0x1FU) +#define DMA_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) + +#define DMA_CH_SBR_SEC_MASK (0x4000U) +#define DMA_CH_SBR_SEC_SHIFT (14U) +/*! SEC - Security Level + * 0b0..Nonsecure protection level for DMA transfers + * 0b1..Secure protection level for DMA transfers + */ +#define DMA_CH_SBR_SEC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_SEC_SHIFT)) & DMA_CH_SBR_SEC_MASK) + +#define DMA_CH_SBR_PAL_MASK (0x8000U) +#define DMA_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) + +#define DMA_CH_SBR_EMI_MASK (0x10000U) +#define DMA_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID Replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) +/*! @} */ + +/* The count of DMA_CH_SBR */ +#define DMA_CH_SBR_COUNT (16U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define DMA_CH_PRI_APL_MASK (0x7U) +#define DMA_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) + +#define DMA_CH_PRI_DPA_MASK (0x40000000U) +#define DMA_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) + +#define DMA_CH_PRI_ECP_MASK (0x80000000U) +#define DMA_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA_CH_PRI */ +#define DMA_CH_PRI_COUNT (16U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA_CH_MUX_SRC_MASK (0x7FU) +#define DMA_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA_CH_MUX */ +#define DMA_CH_MUX_COUNT (16U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_SADDR */ +#define DMA_TCD_SADDR_COUNT (16U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_SOFF */ +#define DMA_TCD_SOFF_COUNT (16U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define DMA_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) + +#define DMA_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) + +#define DMA_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110.. + * 0b111.. + */ +#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) + +#define DMA_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] + */ +#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_TCD_ATTR */ +#define DMA_TCD_ATTR_COUNT (16U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFNO */ +#define DMA_TCD_NBYTES_MLOFFNO_COUNT (16U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFYES */ +#define DMA_TCD_NBYTES_MLOFFYES_COUNT (16U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA_TCD_SLAST_SDA */ +#define DMA_TCD_SLAST_SDA_COUNT (16U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_DADDR */ +#define DMA_TCD_DADDR_COUNT (16U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_DOFF */ +#define DMA_TCD_DOFF_COUNT (16U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKNO */ +#define DMA_TCD_CITER_ELINKNO_COUNT (16U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x1E00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKYES */ +#define DMA_TCD_CITER_ELINKYES_COUNT (16U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA_TCD_DLAST_SGA */ +#define DMA_TCD_DLAST_SGA_COUNT (16U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define DMA_TCD_CSR_START_MASK (0x1U) +#define DMA_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) + +#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) + +#define DMA_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) + +#define DMA_TCD_CSR_DREQ_MASK (0x8U) +#define DMA_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) + +#define DMA_TCD_CSR_ESG_MASK (0x10U) +#define DMA_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) + +#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) + +#define DMA_TCD_CSR_EEOP_MASK (0x40U) +#define DMA_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) + +#define DMA_TCD_CSR_ESDA_MASK (0x80U) +#define DMA_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) + +#define DMA_TCD_CSR_MAJORLINKCH_MASK (0xF00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_CSR_BWC_MASK (0xC000U) +#define DMA_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_TCD_CSR */ +#define DMA_TCD_CSR_COUNT (16U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKNO */ +#define DMA_TCD_BITER_ELINKNO_COUNT (16U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x1E00U) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ + +#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKYES */ +#define DMA_TCD_BITER_ELINKYES_COUNT (16U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x50080000u) + /** Peripheral DMA0 base address */ + #define DMA0_BASE_NS (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA0 base pointer */ + #define DMA0_NS ((DMA_Type *)DMA0_BASE_NS) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x500A0000u) + /** Peripheral DMA1 base address */ + #define DMA1_BASE_NS (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Peripheral DMA1 base pointer */ + #define DMA1_NS ((DMA_Type *)DMA1_BASE_NS) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS_NS { DMA0_BASE_NS, DMA1_BASE_NS } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS_NS { DMA0_NS, DMA1_NS } +#else + /** Peripheral DMA0 base address */ + #define DMA0_BASE (0x40080000u) + /** Peripheral DMA0 base pointer */ + #define DMA0 ((DMA_Type *)DMA0_BASE) + /** Peripheral DMA1 base address */ + #define DMA1_BASE (0x400A0000u) + /** Peripheral DMA1 base pointer */ + #define DMA1 ((DMA_Type *)DMA1_BASE) + /** Array initializer of DMA peripheral base addresses */ + #define DMA_BASE_ADDRS { DMA0_BASE, DMA1_BASE } + /** Array initializer of DMA peripheral base pointers */ + #define DMA_BASE_PTRS { DMA0, DMA1 } +#endif +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { { EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn }, \ + { EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA0_TEE_ALIAS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA0_TEE_ALIAS_Peripheral_Access_Layer DMA0_TEE_ALIAS Peripheral Access Layer + * @{ + */ + +/** DMA0_TEE_ALIAS - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4092]; + uint32_t RESERVED; /**< Reserved., offset: 0xFFC */ +} DMA0_TEE_ALIAS_Type; + +/* ---------------------------------------------------------------------------- + -- DMA0_TEE_ALIAS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA0_TEE_ALIAS_Register_Masks DMA0_TEE_ALIAS Register Masks + * @{ + */ + + +/*! + * @} + */ /* end of group DMA0_TEE_ALIAS_Register_Masks */ + + +/* DMA0_TEE_ALIAS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE (0x50080000u) + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE_NS (0x40080000u) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE (0x50081000u) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE_NS (0x40081000u) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE (0x50082000u) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE_NS (0x40082000u) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE (0x50083000u) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE_NS (0x40083000u) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE (0x50084000u) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE_NS (0x40084000u) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE (0x50085000u) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE_NS (0x40085000u) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE (0x50086000u) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE_NS (0x40086000u) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE (0x50087000u) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE_NS (0x40087000u) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE (0x50088000u) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE_NS (0x40088000u) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE (0x50089000u) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE_NS (0x40089000u) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE (0x5008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE_NS (0x4008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE (0x5008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE_NS (0x4008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE (0x5008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE_NS (0x4008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE (0x5008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE_NS (0x4008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE (0x5008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE_NS (0x4008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE (0x5008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE_NS (0x4008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE_NS) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE (0x50090000u) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE_NS (0x40090000u) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16_NS ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE_NS) + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS { DMA0_TEE_ALIAS0_BASE, DMA0_TEE_ALIAS1_BASE, DMA0_TEE_ALIAS2_BASE, DMA0_TEE_ALIAS3_BASE, DMA0_TEE_ALIAS4_BASE, DMA0_TEE_ALIAS5_BASE, DMA0_TEE_ALIAS6_BASE, DMA0_TEE_ALIAS7_BASE, DMA0_TEE_ALIAS8_BASE, DMA0_TEE_ALIAS9_BASE, DMA0_TEE_ALIAS10_BASE, DMA0_TEE_ALIAS11_BASE, DMA0_TEE_ALIAS12_BASE, DMA0_TEE_ALIAS13_BASE, DMA0_TEE_ALIAS14_BASE, DMA0_TEE_ALIAS15_BASE, DMA0_TEE_ALIAS16_BASE } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS { DMA0_TEE_ALIAS0, DMA0_TEE_ALIAS1, DMA0_TEE_ALIAS2, DMA0_TEE_ALIAS3, DMA0_TEE_ALIAS4, DMA0_TEE_ALIAS5, DMA0_TEE_ALIAS6, DMA0_TEE_ALIAS7, DMA0_TEE_ALIAS8, DMA0_TEE_ALIAS9, DMA0_TEE_ALIAS10, DMA0_TEE_ALIAS11, DMA0_TEE_ALIAS12, DMA0_TEE_ALIAS13, DMA0_TEE_ALIAS14, DMA0_TEE_ALIAS15, DMA0_TEE_ALIAS16 } + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS_NS { DMA0_TEE_ALIAS0_BASE_NS, DMA0_TEE_ALIAS1_BASE_NS, DMA0_TEE_ALIAS2_BASE_NS, DMA0_TEE_ALIAS3_BASE_NS, DMA0_TEE_ALIAS4_BASE_NS, DMA0_TEE_ALIAS5_BASE_NS, DMA0_TEE_ALIAS6_BASE_NS, DMA0_TEE_ALIAS7_BASE_NS, DMA0_TEE_ALIAS8_BASE_NS, DMA0_TEE_ALIAS9_BASE_NS, DMA0_TEE_ALIAS10_BASE_NS, DMA0_TEE_ALIAS11_BASE_NS, DMA0_TEE_ALIAS12_BASE_NS, DMA0_TEE_ALIAS13_BASE_NS, DMA0_TEE_ALIAS14_BASE_NS, DMA0_TEE_ALIAS15_BASE_NS, DMA0_TEE_ALIAS16_BASE_NS } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS_NS { DMA0_TEE_ALIAS0_NS, DMA0_TEE_ALIAS1_NS, DMA0_TEE_ALIAS2_NS, DMA0_TEE_ALIAS3_NS, DMA0_TEE_ALIAS4_NS, DMA0_TEE_ALIAS5_NS, DMA0_TEE_ALIAS6_NS, DMA0_TEE_ALIAS7_NS, DMA0_TEE_ALIAS8_NS, DMA0_TEE_ALIAS9_NS, DMA0_TEE_ALIAS10_NS, DMA0_TEE_ALIAS11_NS, DMA0_TEE_ALIAS12_NS, DMA0_TEE_ALIAS13_NS, DMA0_TEE_ALIAS14_NS, DMA0_TEE_ALIAS15_NS, DMA0_TEE_ALIAS16_NS } +#else + /** Peripheral DMA0_TEE_ALIAS0 base address */ + #define DMA0_TEE_ALIAS0_BASE (0x40080000u) + /** Peripheral DMA0_TEE_ALIAS0 base pointer */ + #define DMA0_TEE_ALIAS0 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS0_BASE) + /** Peripheral DMA0_TEE_ALIAS1 base address */ + #define DMA0_TEE_ALIAS1_BASE (0x40081000u) + /** Peripheral DMA0_TEE_ALIAS1 base pointer */ + #define DMA0_TEE_ALIAS1 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS1_BASE) + /** Peripheral DMA0_TEE_ALIAS2 base address */ + #define DMA0_TEE_ALIAS2_BASE (0x40082000u) + /** Peripheral DMA0_TEE_ALIAS2 base pointer */ + #define DMA0_TEE_ALIAS2 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS2_BASE) + /** Peripheral DMA0_TEE_ALIAS3 base address */ + #define DMA0_TEE_ALIAS3_BASE (0x40083000u) + /** Peripheral DMA0_TEE_ALIAS3 base pointer */ + #define DMA0_TEE_ALIAS3 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS3_BASE) + /** Peripheral DMA0_TEE_ALIAS4 base address */ + #define DMA0_TEE_ALIAS4_BASE (0x40084000u) + /** Peripheral DMA0_TEE_ALIAS4 base pointer */ + #define DMA0_TEE_ALIAS4 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS4_BASE) + /** Peripheral DMA0_TEE_ALIAS5 base address */ + #define DMA0_TEE_ALIAS5_BASE (0x40085000u) + /** Peripheral DMA0_TEE_ALIAS5 base pointer */ + #define DMA0_TEE_ALIAS5 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS5_BASE) + /** Peripheral DMA0_TEE_ALIAS6 base address */ + #define DMA0_TEE_ALIAS6_BASE (0x40086000u) + /** Peripheral DMA0_TEE_ALIAS6 base pointer */ + #define DMA0_TEE_ALIAS6 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS6_BASE) + /** Peripheral DMA0_TEE_ALIAS7 base address */ + #define DMA0_TEE_ALIAS7_BASE (0x40087000u) + /** Peripheral DMA0_TEE_ALIAS7 base pointer */ + #define DMA0_TEE_ALIAS7 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS7_BASE) + /** Peripheral DMA0_TEE_ALIAS8 base address */ + #define DMA0_TEE_ALIAS8_BASE (0x40088000u) + /** Peripheral DMA0_TEE_ALIAS8 base pointer */ + #define DMA0_TEE_ALIAS8 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS8_BASE) + /** Peripheral DMA0_TEE_ALIAS9 base address */ + #define DMA0_TEE_ALIAS9_BASE (0x40089000u) + /** Peripheral DMA0_TEE_ALIAS9 base pointer */ + #define DMA0_TEE_ALIAS9 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS9_BASE) + /** Peripheral DMA0_TEE_ALIAS10 base address */ + #define DMA0_TEE_ALIAS10_BASE (0x4008A000u) + /** Peripheral DMA0_TEE_ALIAS10 base pointer */ + #define DMA0_TEE_ALIAS10 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS10_BASE) + /** Peripheral DMA0_TEE_ALIAS11 base address */ + #define DMA0_TEE_ALIAS11_BASE (0x4008B000u) + /** Peripheral DMA0_TEE_ALIAS11 base pointer */ + #define DMA0_TEE_ALIAS11 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS11_BASE) + /** Peripheral DMA0_TEE_ALIAS12 base address */ + #define DMA0_TEE_ALIAS12_BASE (0x4008C000u) + /** Peripheral DMA0_TEE_ALIAS12 base pointer */ + #define DMA0_TEE_ALIAS12 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS12_BASE) + /** Peripheral DMA0_TEE_ALIAS13 base address */ + #define DMA0_TEE_ALIAS13_BASE (0x4008D000u) + /** Peripheral DMA0_TEE_ALIAS13 base pointer */ + #define DMA0_TEE_ALIAS13 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS13_BASE) + /** Peripheral DMA0_TEE_ALIAS14 base address */ + #define DMA0_TEE_ALIAS14_BASE (0x4008E000u) + /** Peripheral DMA0_TEE_ALIAS14 base pointer */ + #define DMA0_TEE_ALIAS14 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS14_BASE) + /** Peripheral DMA0_TEE_ALIAS15 base address */ + #define DMA0_TEE_ALIAS15_BASE (0x4008F000u) + /** Peripheral DMA0_TEE_ALIAS15 base pointer */ + #define DMA0_TEE_ALIAS15 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS15_BASE) + /** Peripheral DMA0_TEE_ALIAS16 base address */ + #define DMA0_TEE_ALIAS16_BASE (0x40090000u) + /** Peripheral DMA0_TEE_ALIAS16 base pointer */ + #define DMA0_TEE_ALIAS16 ((DMA0_TEE_ALIAS_Type *)DMA0_TEE_ALIAS16_BASE) + /** Array initializer of DMA0_TEE_ALIAS peripheral base addresses */ + #define DMA0_TEE_ALIAS_BASE_ADDRS { DMA0_TEE_ALIAS0_BASE, DMA0_TEE_ALIAS1_BASE, DMA0_TEE_ALIAS2_BASE, DMA0_TEE_ALIAS3_BASE, DMA0_TEE_ALIAS4_BASE, DMA0_TEE_ALIAS5_BASE, DMA0_TEE_ALIAS6_BASE, DMA0_TEE_ALIAS7_BASE, DMA0_TEE_ALIAS8_BASE, DMA0_TEE_ALIAS9_BASE, DMA0_TEE_ALIAS10_BASE, DMA0_TEE_ALIAS11_BASE, DMA0_TEE_ALIAS12_BASE, DMA0_TEE_ALIAS13_BASE, DMA0_TEE_ALIAS14_BASE, DMA0_TEE_ALIAS15_BASE, DMA0_TEE_ALIAS16_BASE } + /** Array initializer of DMA0_TEE_ALIAS peripheral base pointers */ + #define DMA0_TEE_ALIAS_BASE_PTRS { DMA0_TEE_ALIAS0, DMA0_TEE_ALIAS1, DMA0_TEE_ALIAS2, DMA0_TEE_ALIAS3, DMA0_TEE_ALIAS4, DMA0_TEE_ALIAS5, DMA0_TEE_ALIAS6, DMA0_TEE_ALIAS7, DMA0_TEE_ALIAS8, DMA0_TEE_ALIAS9, DMA0_TEE_ALIAS10, DMA0_TEE_ALIAS11, DMA0_TEE_ALIAS12, DMA0_TEE_ALIAS13, DMA0_TEE_ALIAS14, DMA0_TEE_ALIAS15, DMA0_TEE_ALIAS16 } +#endif + +/*! + * @} + */ /* end of group DMA0_TEE_ALIAS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA1_TEE_ALIAS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA1_TEE_ALIAS_Peripheral_Access_Layer DMA1_TEE_ALIAS Peripheral Access Layer + * @{ + */ + +/** DMA1_TEE_ALIAS - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4092]; + uint32_t RESERVED; /**< Reserved., offset: 0xFFC */ +} DMA1_TEE_ALIAS_Type; + +/* ---------------------------------------------------------------------------- + -- DMA1_TEE_ALIAS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA1_TEE_ALIAS_Register_Masks DMA1_TEE_ALIAS Register Masks + * @{ + */ + + +/*! + * @} + */ /* end of group DMA1_TEE_ALIAS_Register_Masks */ + + +/* DMA1_TEE_ALIAS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE (0x500A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE_NS (0x400A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE (0x500A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE_NS (0x400A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE (0x500A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE_NS (0x400A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE (0x500A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE_NS (0x400A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE (0x500A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE_NS (0x400A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE (0x500A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE_NS (0x400A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE (0x500A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE_NS (0x400A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE (0x500A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE_NS (0x400A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE_NS) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE (0x500A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE_NS (0x400A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8_NS ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE_NS) + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS { DMA1_TEE_ALIAS0_BASE, DMA1_TEE_ALIAS1_BASE, DMA1_TEE_ALIAS2_BASE, DMA1_TEE_ALIAS3_BASE, DMA1_TEE_ALIAS4_BASE, DMA1_TEE_ALIAS5_BASE, DMA1_TEE_ALIAS6_BASE, DMA1_TEE_ALIAS7_BASE, DMA1_TEE_ALIAS8_BASE } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS { DMA1_TEE_ALIAS0, DMA1_TEE_ALIAS1, DMA1_TEE_ALIAS2, DMA1_TEE_ALIAS3, DMA1_TEE_ALIAS4, DMA1_TEE_ALIAS5, DMA1_TEE_ALIAS6, DMA1_TEE_ALIAS7, DMA1_TEE_ALIAS8 } + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS_NS { DMA1_TEE_ALIAS0_BASE_NS, DMA1_TEE_ALIAS1_BASE_NS, DMA1_TEE_ALIAS2_BASE_NS, DMA1_TEE_ALIAS3_BASE_NS, DMA1_TEE_ALIAS4_BASE_NS, DMA1_TEE_ALIAS5_BASE_NS, DMA1_TEE_ALIAS6_BASE_NS, DMA1_TEE_ALIAS7_BASE_NS, DMA1_TEE_ALIAS8_BASE_NS } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS_NS { DMA1_TEE_ALIAS0_NS, DMA1_TEE_ALIAS1_NS, DMA1_TEE_ALIAS2_NS, DMA1_TEE_ALIAS3_NS, DMA1_TEE_ALIAS4_NS, DMA1_TEE_ALIAS5_NS, DMA1_TEE_ALIAS6_NS, DMA1_TEE_ALIAS7_NS, DMA1_TEE_ALIAS8_NS } +#else + /** Peripheral DMA1_TEE_ALIAS0 base address */ + #define DMA1_TEE_ALIAS0_BASE (0x400A0000u) + /** Peripheral DMA1_TEE_ALIAS0 base pointer */ + #define DMA1_TEE_ALIAS0 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS0_BASE) + /** Peripheral DMA1_TEE_ALIAS1 base address */ + #define DMA1_TEE_ALIAS1_BASE (0x400A1000u) + /** Peripheral DMA1_TEE_ALIAS1 base pointer */ + #define DMA1_TEE_ALIAS1 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS1_BASE) + /** Peripheral DMA1_TEE_ALIAS2 base address */ + #define DMA1_TEE_ALIAS2_BASE (0x400A2000u) + /** Peripheral DMA1_TEE_ALIAS2 base pointer */ + #define DMA1_TEE_ALIAS2 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS2_BASE) + /** Peripheral DMA1_TEE_ALIAS3 base address */ + #define DMA1_TEE_ALIAS3_BASE (0x400A3000u) + /** Peripheral DMA1_TEE_ALIAS3 base pointer */ + #define DMA1_TEE_ALIAS3 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS3_BASE) + /** Peripheral DMA1_TEE_ALIAS4 base address */ + #define DMA1_TEE_ALIAS4_BASE (0x400A4000u) + /** Peripheral DMA1_TEE_ALIAS4 base pointer */ + #define DMA1_TEE_ALIAS4 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS4_BASE) + /** Peripheral DMA1_TEE_ALIAS5 base address */ + #define DMA1_TEE_ALIAS5_BASE (0x400A5000u) + /** Peripheral DMA1_TEE_ALIAS5 base pointer */ + #define DMA1_TEE_ALIAS5 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS5_BASE) + /** Peripheral DMA1_TEE_ALIAS6 base address */ + #define DMA1_TEE_ALIAS6_BASE (0x400A6000u) + /** Peripheral DMA1_TEE_ALIAS6 base pointer */ + #define DMA1_TEE_ALIAS6 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS6_BASE) + /** Peripheral DMA1_TEE_ALIAS7 base address */ + #define DMA1_TEE_ALIAS7_BASE (0x400A7000u) + /** Peripheral DMA1_TEE_ALIAS7 base pointer */ + #define DMA1_TEE_ALIAS7 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS7_BASE) + /** Peripheral DMA1_TEE_ALIAS8 base address */ + #define DMA1_TEE_ALIAS8_BASE (0x400A8000u) + /** Peripheral DMA1_TEE_ALIAS8 base pointer */ + #define DMA1_TEE_ALIAS8 ((DMA1_TEE_ALIAS_Type *)DMA1_TEE_ALIAS8_BASE) + /** Array initializer of DMA1_TEE_ALIAS peripheral base addresses */ + #define DMA1_TEE_ALIAS_BASE_ADDRS { DMA1_TEE_ALIAS0_BASE, DMA1_TEE_ALIAS1_BASE, DMA1_TEE_ALIAS2_BASE, DMA1_TEE_ALIAS3_BASE, DMA1_TEE_ALIAS4_BASE, DMA1_TEE_ALIAS5_BASE, DMA1_TEE_ALIAS6_BASE, DMA1_TEE_ALIAS7_BASE, DMA1_TEE_ALIAS8_BASE } + /** Array initializer of DMA1_TEE_ALIAS peripheral base pointers */ + #define DMA1_TEE_ALIAS_BASE_PTRS { DMA1_TEE_ALIAS0, DMA1_TEE_ALIAS1, DMA1_TEE_ALIAS2, DMA1_TEE_ALIAS3, DMA1_TEE_ALIAS4, DMA1_TEE_ALIAS5, DMA1_TEE_ALIAS6, DMA1_TEE_ALIAS7, DMA1_TEE_ALIAS8 } +#endif + +/*! + * @} + */ /* end of group DMA1_TEE_ALIAS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ + __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ + __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ + uint8_t RESERVED_1[56]; + __IO uint32_t EICHD1_WORD0; /**< Error Injection Channel Descriptor 1, Word0, offset: 0x140 */ + __IO uint32_t EICHD1_WORD1; /**< Error Injection Channel Descriptor 1, Word1, offset: 0x144 */ + uint8_t RESERVED_2[56]; + __IO uint32_t EICHD2_WORD0; /**< Error Injection Channel Descriptor 2, Word0, offset: 0x180 */ + __IO uint32_t EICHD2_WORD1; /**< Error Injection Channel Descriptor 2, Word1, offset: 0x184 */ + uint8_t RESERVED_3[56]; + __IO uint32_t EICHD3_WORD0; /**< Error Injection Channel Descriptor 3, Word0, offset: 0x1C0 */ + __IO uint32_t EICHD3_WORD1; /**< Error Injection Channel Descriptor 3, Word1, offset: 0x1C4 */ + uint8_t RESERVED_4[56]; + __IO uint32_t EICHD4_WORD0; /**< Error Injection Channel Descriptor 4, Word0, offset: 0x200 */ + __IO uint32_t EICHD4_WORD1; /**< Error Injection Channel Descriptor 4, Word1, offset: 0x204 */ + uint8_t RESERVED_5[56]; + __IO uint32_t EICHD5_WORD0; /**< Error Injection Channel Descriptor 5, Word0, offset: 0x240 */ + __IO uint32_t EICHD5_WORD1; /**< Error Injection Channel Descriptor 5, Word1, offset: 0x244 */ + uint8_t RESERVED_6[56]; + __IO uint32_t EICHD6_WORD0; /**< Error Injection Channel Descriptor 6, Word0, offset: 0x280 */ + __IO uint32_t EICHD6_WORD1; /**< Error Injection Channel Descriptor 6, Word1, offset: 0x284 */ + uint8_t RESERVED_7[56]; + __IO uint32_t EICHD7_WORD0; /**< Error Injection Channel Descriptor 7, Word0, offset: 0x2C0 */ + __IO uint32_t EICHD7_WORD1; /**< Error Injection Channel Descriptor 7, Word1, offset: 0x2C4 */ + uint8_t RESERVED_8[56]; + __IO uint32_t EICHD8_WORD0; /**< Error Injection Channel Descriptor 8, Word0, offset: 0x300 */ + __IO uint32_t EICHD8_WORD1; /**< Error Injection Channel Descriptor 8, Word1, offset: 0x304 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name EIMCR - Error Injection Module Configuration Register */ +/*! @{ */ + +#define EIM_EIMCR_GEIEN_MASK (0x1U) +#define EIM_EIMCR_GEIEN_SHIFT (0U) +/*! GEIEN - Global Error Injection Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) +/*! @} */ + +/*! @name EICHEN - Error Injection Channel Enable register */ +/*! @{ */ + +#define EIM_EICHEN_EICH8EN_MASK (0x800000U) +#define EIM_EICHEN_EICH8EN_SHIFT (23U) +/*! EICH8EN - Error Injection Channel 8 Enable + * 0b0..Error injection is disabled on Error Injection Channel 8 + * 0b1..Error injection is enabled on Error Injection Channel 8 + */ +#define EIM_EICHEN_EICH8EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH8EN_SHIFT)) & EIM_EICHEN_EICH8EN_MASK) + +#define EIM_EICHEN_EICH7EN_MASK (0x1000000U) +#define EIM_EICHEN_EICH7EN_SHIFT (24U) +/*! EICH7EN - Error Injection Channel 7 Enable + * 0b0..Error injection is disabled on Error Injection Channel 7 + * 0b1..Error injection is enabled on Error Injection Channel 7 + */ +#define EIM_EICHEN_EICH7EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH7EN_SHIFT)) & EIM_EICHEN_EICH7EN_MASK) + +#define EIM_EICHEN_EICH6EN_MASK (0x2000000U) +#define EIM_EICHEN_EICH6EN_SHIFT (25U) +/*! EICH6EN - Error Injection Channel 6 Enable + * 0b0..Error injection is disabled on Error Injection Channel 6 + * 0b1..Error injection is enabled on Error Injection Channel 6 + */ +#define EIM_EICHEN_EICH6EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH6EN_SHIFT)) & EIM_EICHEN_EICH6EN_MASK) + +#define EIM_EICHEN_EICH5EN_MASK (0x4000000U) +#define EIM_EICHEN_EICH5EN_SHIFT (26U) +/*! EICH5EN - Error Injection Channel 5 Enable + * 0b0..Error injection is disabled on Error Injection Channel 5 + * 0b1..Error injection is enabled on Error Injection Channel 5 + */ +#define EIM_EICHEN_EICH5EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH5EN_SHIFT)) & EIM_EICHEN_EICH5EN_MASK) + +#define EIM_EICHEN_EICH4EN_MASK (0x8000000U) +#define EIM_EICHEN_EICH4EN_SHIFT (27U) +/*! EICH4EN - Error Injection Channel 4 Enable + * 0b0..Error injection is disabled on Error Injection Channel 4 + * 0b1..Error injection is enabled on Error Injection Channel 4 + */ +#define EIM_EICHEN_EICH4EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH4EN_SHIFT)) & EIM_EICHEN_EICH4EN_MASK) + +#define EIM_EICHEN_EICH3EN_MASK (0x10000000U) +#define EIM_EICHEN_EICH3EN_SHIFT (28U) +/*! EICH3EN - Error Injection Channel 3 Enable + * 0b0..Error injection is disabled on Error Injection Channel 3 + * 0b1..Error injection is enabled on Error Injection Channel 3 + */ +#define EIM_EICHEN_EICH3EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH3EN_SHIFT)) & EIM_EICHEN_EICH3EN_MASK) + +#define EIM_EICHEN_EICH2EN_MASK (0x20000000U) +#define EIM_EICHEN_EICH2EN_SHIFT (29U) +/*! EICH2EN - Error Injection Channel 2 Enable + * 0b0..Error injection is disabled on Error Injection Channel 2 + * 0b1..Error injection is enabled on Error Injection Channel 2 + */ +#define EIM_EICHEN_EICH2EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH2EN_SHIFT)) & EIM_EICHEN_EICH2EN_MASK) + +#define EIM_EICHEN_EICH1EN_MASK (0x40000000U) +#define EIM_EICHEN_EICH1EN_SHIFT (30U) +/*! EICH1EN - Error Injection Channel 1 Enable + * 0b0..Error injection is disabled on Error Injection Channel 1 + * 0b1..Error injection is enabled on Error Injection Channel 1 + */ +#define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH1EN_SHIFT)) & EIM_EICHEN_EICH1EN_MASK) + +#define EIM_EICHEN_EICH0EN_MASK (0x80000000U) +#define EIM_EICHEN_EICH0EN_SHIFT (31U) +/*! EICH0EN - Error Injection Channel 0 Enable + * 0b0..Error injection is disabled on Error Injection Channel 0 + * 0b1..Error injection is enabled on Error Injection Channel 0 + */ +#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) +/*! @} */ + +/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ +/*! @{ */ + +#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ +/*! @{ */ + +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD1_WORD0 - Error Injection Channel Descriptor 1, Word0 */ +/*! @{ */ + +#define EIM_EICHD1_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD1_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD1_WORD1 - Error Injection Channel Descriptor 1, Word1 */ +/*! @{ */ + +#define EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD1_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD2_WORD0 - Error Injection Channel Descriptor 2, Word0 */ +/*! @{ */ + +#define EIM_EICHD2_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD2_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD2_WORD1 - Error Injection Channel Descriptor 2, Word1 */ +/*! @{ */ + +#define EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD2_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD3_WORD0 - Error Injection Channel Descriptor 3, Word0 */ +/*! @{ */ + +#define EIM_EICHD3_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD3_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD3_WORD1 - Error Injection Channel Descriptor 3, Word1 */ +/*! @{ */ + +#define EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD3_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD4_WORD0 - Error Injection Channel Descriptor 4, Word0 */ +/*! @{ */ + +#define EIM_EICHD4_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD4_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD4_WORD1 - Error Injection Channel Descriptor 4, Word1 */ +/*! @{ */ + +#define EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD4_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD5_WORD0 - Error Injection Channel Descriptor 5, Word0 */ +/*! @{ */ + +#define EIM_EICHD5_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD5_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD5_WORD1 - Error Injection Channel Descriptor 5, Word1 */ +/*! @{ */ + +#define EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD5_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD6_WORD0 - Error Injection Channel Descriptor 6, Word0 */ +/*! @{ */ + +#define EIM_EICHD6_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD6_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD6_WORD1 - Error Injection Channel Descriptor 6, Word1 */ +/*! @{ */ + +#define EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD6_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD7_WORD0 - Error Injection Channel Descriptor 7, Word0 */ +/*! @{ */ + +#define EIM_EICHD7_WORD0_CHKBIT_MASK_MASK (0x80000000U) +#define EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT (31U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD7_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD7_WORD1 - Error Injection Channel Descriptor 7, Word1 */ +/*! @{ */ + +#define EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD7_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + +/*! @name EICHD8_WORD0 - Error Injection Channel Descriptor 8, Word0 */ +/*! @{ */ + +#define EIM_EICHD8_WORD0_CHKBIT_MASK_MASK (0xF0000000U) +#define EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT (28U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD8_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD8_WORD1 - Error Injection Channel Descriptor 8, Word1 */ +/*! @{ */ + +#define EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD8_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x5005B000u) + /** Peripheral EIM0 base address */ + #define EIM0_BASE_NS (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Peripheral EIM0 base pointer */ + #define EIM0_NS ((EIM_Type *)EIM0_BASE_NS) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS_NS { EIM0_BASE_NS } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS_NS { EIM0_NS } +#else + /** Peripheral EIM0 base address */ + #define EIM0_BASE (0x4005B000u) + /** Peripheral EIM0 base pointer */ + #define EIM0 ((EIM_Type *)EIM0_BASE) + /** Array initializer of EIM peripheral base addresses */ + #define EIM_BASE_ADDRS { EIM0_BASE } + /** Array initializer of EIM peripheral base pointers */ + #define EIM_BASE_PTRS { EIM0 } +#endif + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ERM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer + * @{ + */ + +/** ERM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ + __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ + __IO uint32_t SR1; /**< ERM Status Register 1, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ + __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ + __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ + uint8_t RESERVED_2[4]; + __I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset: 0x110 */ + __I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x114 */ + __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ + uint8_t RESERVED_3[4]; + __I uint32_t EAR2; /**< ERM Memory 2 Error Address Register, offset: 0x120 */ + __I uint32_t SYN2; /**< ERM Memory 2 Syndrome Register, offset: 0x124 */ + __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */ + uint8_t RESERVED_4[4]; + __I uint32_t EAR3; /**< ERM Memory 3 Error Address Register, offset: 0x130 */ + __I uint32_t SYN3; /**< ERM Memory 3 Syndrome Register, offset: 0x134 */ + __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */ + uint8_t RESERVED_5[4]; + __I uint32_t EAR4; /**< ERM Memory 4 Error Address Register, offset: 0x140 */ + __I uint32_t SYN4; /**< ERM Memory 4 Syndrome Register, offset: 0x144 */ + __IO uint32_t CORR_ERR_CNT4; /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */ + uint8_t RESERVED_8[12]; + __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */ + uint8_t RESERVED_9[8]; + __I uint32_t SYN8; /**< ERM Memory 8 Syndrome Register, offset: 0x184 */ + __IO uint32_t CORR_ERR_CNT8; /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CORR_ERR_CNT9; /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198 */ +} ERM_Type; + +/* ---------------------------------------------------------------------------- + -- ERM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Register_Masks ERM Register Masks + * @{ + */ + +/*! @name CR0 - ERM Configuration Register 0 */ +/*! @{ */ + +#define ERM_CR0_ENCIE7_MASK (0x4U) +#define ERM_CR0_ENCIE7_SHIFT (2U) +/*! ENCIE7 - ENCIE7 + * 0b0..Interrupt notification of Memory 7 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 7 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE7_SHIFT)) & ERM_CR0_ENCIE7_MASK) + +#define ERM_CR0_ESCIE7_MASK (0x8U) +#define ERM_CR0_ESCIE7_SHIFT (3U) +/*! ESCIE7 - ESCIE7 + * 0b0..Interrupt notification of Memory 7 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 7 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE7_SHIFT)) & ERM_CR0_ESCIE7_MASK) + +#define ERM_CR0_ENCIE6_MASK (0x40U) +#define ERM_CR0_ENCIE6_SHIFT (6U) +/*! ENCIE6 - ENCIE6 + * 0b0..Interrupt notification of Memory 6 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 6 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE6_SHIFT)) & ERM_CR0_ENCIE6_MASK) + +#define ERM_CR0_ESCIE6_MASK (0x80U) +#define ERM_CR0_ESCIE6_SHIFT (7U) +/*! ESCIE6 - ESCIE6 + * 0b0..Interrupt notification of Memory 6 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 6 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE6_SHIFT)) & ERM_CR0_ESCIE6_MASK) + +#define ERM_CR0_ENCIE5_MASK (0x400U) +#define ERM_CR0_ENCIE5_SHIFT (10U) +/*! ENCIE5 - ENCIE5 + * 0b0..Interrupt notification of Memory 5 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 5 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE5_SHIFT)) & ERM_CR0_ENCIE5_MASK) + +#define ERM_CR0_ESCIE5_MASK (0x800U) +#define ERM_CR0_ESCIE5_SHIFT (11U) +/*! ESCIE5 - ESCIE5 + * 0b0..Interrupt notification of Memory 5 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 5 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE5_SHIFT)) & ERM_CR0_ESCIE5_MASK) + +#define ERM_CR0_ENCIE4_MASK (0x4000U) +#define ERM_CR0_ENCIE4_SHIFT (14U) +/*! ENCIE4 - ENCIE4 + * 0b0..Interrupt notification of Memory 4 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 4 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE4_SHIFT)) & ERM_CR0_ENCIE4_MASK) + +#define ERM_CR0_ESCIE4_MASK (0x8000U) +#define ERM_CR0_ESCIE4_SHIFT (15U) +/*! ESCIE4 - ESCIE4 + * 0b0..Interrupt notification of Memory 4 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 4 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE4_SHIFT)) & ERM_CR0_ESCIE4_MASK) + +#define ERM_CR0_ENCIE3_MASK (0x40000U) +#define ERM_CR0_ENCIE3_SHIFT (18U) +/*! ENCIE3 - ENCIE3 + * 0b0..Interrupt notification of Memory 3 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 3 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK) + +#define ERM_CR0_ESCIE3_MASK (0x80000U) +#define ERM_CR0_ESCIE3_SHIFT (19U) +/*! ESCIE3 - ESCIE3 + * 0b0..Interrupt notification of Memory 3 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 3 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK) + +#define ERM_CR0_ENCIE2_MASK (0x400000U) +#define ERM_CR0_ENCIE2_SHIFT (22U) +/*! ENCIE2 - ENCIE2 + * 0b0..Interrupt notification of Memory 2 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 2 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK) + +#define ERM_CR0_ESCIE2_MASK (0x800000U) +#define ERM_CR0_ESCIE2_SHIFT (23U) +/*! ESCIE2 - ESCIE2 + * 0b0..Interrupt notification of Memory 2 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 2 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK) + +#define ERM_CR0_ENCIE1_MASK (0x4000000U) +#define ERM_CR0_ENCIE1_SHIFT (26U) +/*! ENCIE1 - ENCIE1 + * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) + +#define ERM_CR0_ESCIE1_MASK (0x8000000U) +#define ERM_CR0_ESCIE1_SHIFT (27U) +/*! ESCIE1 - ESCIE1 + * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) + +#define ERM_CR0_ENCIE0_MASK (0x40000000U) +#define ERM_CR0_ENCIE0_SHIFT (30U) +/*! ENCIE0 - ENCIE0 + * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) + +#define ERM_CR0_ESCIE0_MASK (0x80000000U) +#define ERM_CR0_ESCIE0_SHIFT (31U) +/*! ESCIE0 - ESCIE0 + * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) +/*! @} */ + +/*! @name CR1 - ERM Configuration Register 1 */ +/*! @{ */ + +#define ERM_CR1_ENCIE9_MASK (0x4000000U) +#define ERM_CR1_ENCIE9_SHIFT (26U) +/*! ENCIE9 - ENCIE9 + * 0b0..Interrupt notification of Memory 9 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 9 non-correctable error events is enabled. + */ +#define ERM_CR1_ENCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE9_SHIFT)) & ERM_CR1_ENCIE9_MASK) + +#define ERM_CR1_ESCIE9_MASK (0x8000000U) +#define ERM_CR1_ESCIE9_SHIFT (27U) +/*! ESCIE9 - ESCIE9 + * 0b0..Interrupt notification of Memory 9 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 9 single-bit correction events is enabled. + */ +#define ERM_CR1_ESCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE9_SHIFT)) & ERM_CR1_ESCIE9_MASK) + +#define ERM_CR1_ENCIE8_MASK (0x40000000U) +#define ERM_CR1_ENCIE8_SHIFT (30U) +/*! ENCIE8 - ENCIE8 + * 0b0..Interrupt notification of Memory 8 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 8 non-correctable error events is enabled. + */ +#define ERM_CR1_ENCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE8_SHIFT)) & ERM_CR1_ENCIE8_MASK) + +#define ERM_CR1_ESCIE8_MASK (0x80000000U) +#define ERM_CR1_ESCIE8_SHIFT (31U) +/*! ESCIE8 - ESCIE8 + * 0b0..Interrupt notification of Memory 8 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 8 single-bit correction events is enabled. + */ +#define ERM_CR1_ESCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE8_SHIFT)) & ERM_CR1_ESCIE8_MASK) +/*! @} */ + +/*! @name SR0 - ERM Status Register 0 */ +/*! @{ */ + +#define ERM_SR0_NCE7_MASK (0x4U) +#define ERM_SR0_NCE7_SHIFT (2U) +/*! NCE7 - NCE7 + * 0b0..No non-correctable error event on Memory 7 detected. + * 0b1..Non-correctable error event on Memory 7 detected. + */ +#define ERM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE7_SHIFT)) & ERM_SR0_NCE7_MASK) + +#define ERM_SR0_SBC7_MASK (0x8U) +#define ERM_SR0_SBC7_SHIFT (3U) +/*! SBC7 - SBC7 + * 0b0..No single-bit correction event on Memory 7 detected. + * 0b1..Single-bit correction event on Memory 7 detected. + */ +#define ERM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC7_SHIFT)) & ERM_SR0_SBC7_MASK) + +#define ERM_SR0_NCE6_MASK (0x40U) +#define ERM_SR0_NCE6_SHIFT (6U) +/*! NCE6 - NCE6 + * 0b0..No non-correctable error event on Memory 6 detected. + * 0b1..Non-correctable error event on Memory 6 detected. + */ +#define ERM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE6_SHIFT)) & ERM_SR0_NCE6_MASK) + +#define ERM_SR0_SBC6_MASK (0x80U) +#define ERM_SR0_SBC6_SHIFT (7U) +/*! SBC6 - SBC6 + * 0b0..No single-bit correction event on Memory 6 detected. + * 0b1..Single-bit correction event on Memory 6 detected. + */ +#define ERM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC6_SHIFT)) & ERM_SR0_SBC6_MASK) + +#define ERM_SR0_NCE5_MASK (0x400U) +#define ERM_SR0_NCE5_SHIFT (10U) +/*! NCE5 - NCE5 + * 0b0..No non-correctable error event on Memory 5 detected. + * 0b1..Non-correctable error event on Memory 5 detected. + */ +#define ERM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE5_SHIFT)) & ERM_SR0_NCE5_MASK) + +#define ERM_SR0_SBC5_MASK (0x800U) +#define ERM_SR0_SBC5_SHIFT (11U) +/*! SBC5 - SBC5 + * 0b0..No single-bit correction event on Memory 5 detected. + * 0b1..Single-bit correction event on Memory 5 detected. + */ +#define ERM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC5_SHIFT)) & ERM_SR0_SBC5_MASK) + +#define ERM_SR0_NCE4_MASK (0x4000U) +#define ERM_SR0_NCE4_SHIFT (14U) +/*! NCE4 - NCE4 + * 0b0..No non-correctable error event on Memory 4 detected. + * 0b1..Non-correctable error event on Memory 4 detected. + */ +#define ERM_SR0_NCE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE4_SHIFT)) & ERM_SR0_NCE4_MASK) + +#define ERM_SR0_SBC4_MASK (0x8000U) +#define ERM_SR0_SBC4_SHIFT (15U) +/*! SBC4 - SBC4 + * 0b0..No single-bit correction event on Memory 4 detected. + * 0b1..Single-bit correction event on Memory 4 detected. + */ +#define ERM_SR0_SBC4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC4_SHIFT)) & ERM_SR0_SBC4_MASK) + +#define ERM_SR0_NCE3_MASK (0x40000U) +#define ERM_SR0_NCE3_SHIFT (18U) +/*! NCE3 - NCE3 + * 0b0..No non-correctable error event on Memory 3 detected. + * 0b1..Non-correctable error event on Memory 3 detected. + */ +#define ERM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK) + +#define ERM_SR0_SBC3_MASK (0x80000U) +#define ERM_SR0_SBC3_SHIFT (19U) +/*! SBC3 - SBC3 + * 0b0..No single-bit correction event on Memory 3 detected. + * 0b1..Single-bit correction event on Memory 3 detected. + */ +#define ERM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK) + +#define ERM_SR0_NCE2_MASK (0x400000U) +#define ERM_SR0_NCE2_SHIFT (22U) +/*! NCE2 - NCE2 + * 0b0..No non-correctable error event on Memory 2 detected. + * 0b1..Non-correctable error event on Memory 2 detected. + */ +#define ERM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK) + +#define ERM_SR0_SBC2_MASK (0x800000U) +#define ERM_SR0_SBC2_SHIFT (23U) +/*! SBC2 - SBC2 + * 0b0..No single-bit correction event on Memory 2 detected. + * 0b1..Single-bit correction event on Memory 2 detected. + */ +#define ERM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK) + +#define ERM_SR0_NCE1_MASK (0x4000000U) +#define ERM_SR0_NCE1_SHIFT (26U) +/*! NCE1 - NCE1 + * 0b0..No non-correctable error event on Memory 1 detected. + * 0b1..Non-correctable error event on Memory 1 detected. + */ +#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) + +#define ERM_SR0_SBC1_MASK (0x8000000U) +#define ERM_SR0_SBC1_SHIFT (27U) +/*! SBC1 - SBC1 + * 0b0..No single-bit correction event on Memory 1 detected. + * 0b1..Single-bit correction event on Memory 1 detected. + */ +#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) + +#define ERM_SR0_NCE0_MASK (0x40000000U) +#define ERM_SR0_NCE0_SHIFT (30U) +/*! NCE0 - NCE0 + * 0b0..No non-correctable error event on Memory 0 detected. + * 0b1..Non-correctable error event on Memory 0 detected. + */ +#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) + +#define ERM_SR0_SBC0_MASK (0x80000000U) +#define ERM_SR0_SBC0_SHIFT (31U) +/*! SBC0 - SBC0 + * 0b0..No single-bit correction event on Memory 0 detected. + * 0b1..Single-bit correction event on Memory 0 detected. + */ +#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) +/*! @} */ + +/*! @name SR1 - ERM Status Register 1 */ +/*! @{ */ + +#define ERM_SR1_NCE9_MASK (0x4000000U) +#define ERM_SR1_NCE9_SHIFT (26U) +/*! NCE9 - NCE9 + * 0b0..No non-correctable error event on Memory 9 detected. + * 0b1..Non-correctable error event on Memory 9 detected. + */ +#define ERM_SR1_NCE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE9_SHIFT)) & ERM_SR1_NCE9_MASK) + +#define ERM_SR1_SBC9_MASK (0x8000000U) +#define ERM_SR1_SBC9_SHIFT (27U) +/*! SBC9 - SBC9 + * 0b0..No single-bit correction event on Memory 9 detected. + * 0b1..Single-bit correction event on Memory 9 detected. + */ +#define ERM_SR1_SBC9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC9_SHIFT)) & ERM_SR1_SBC9_MASK) + +#define ERM_SR1_NCE8_MASK (0x40000000U) +#define ERM_SR1_NCE8_SHIFT (30U) +/*! NCE8 - NCE8 + * 0b0..No non-correctable error event on Memory 8 detected. + * 0b1..Non-correctable error event on Memory 8 detected. + */ +#define ERM_SR1_NCE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE8_SHIFT)) & ERM_SR1_NCE8_MASK) + +#define ERM_SR1_SBC8_MASK (0x80000000U) +#define ERM_SR1_SBC8_SHIFT (31U) +/*! SBC8 - SBC8 + * 0b0..No single-bit correction event on Memory 8 detected. + * 0b1..Single-bit correction event on Memory 8 detected. + */ +#define ERM_SR1_SBC8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC8_SHIFT)) & ERM_SR1_SBC8_MASK) +/*! @} */ + +/*! @name EAR0 - ERM Memory 0 Error Address Register */ +/*! @{ */ + +#define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR0_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) +/*! @} */ + +/*! @name SYN0 - ERM Memory 0 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN0_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN0_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) +/*! @} */ + +/*! @name EAR1 - ERM Memory 1 Error Address Register */ +/*! @{ */ + +#define ERM_EAR1_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR1_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR1_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR1_EAR_SHIFT)) & ERM_EAR1_EAR_MASK) +/*! @} */ + +/*! @name SYN1 - ERM Memory 1 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN1_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN1_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN1_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN1_SYNDROME_SHIFT)) & ERM_SYN1_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) +/*! @} */ + +/*! @name EAR2 - ERM Memory 2 Error Address Register */ +/*! @{ */ + +#define ERM_EAR2_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR2_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR2_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR2_EAR_SHIFT)) & ERM_EAR2_EAR_MASK) +/*! @} */ + +/*! @name SYN2 - ERM Memory 2 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN2_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN2_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN2_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN2_SYNDROME_SHIFT)) & ERM_SYN2_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT2_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_CORR_ERR_CNT2_COUNT_MASK) +/*! @} */ + +/*! @name EAR3 - ERM Memory 3 Error Address Register */ +/*! @{ */ + +#define ERM_EAR3_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR3_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR3_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR3_EAR_SHIFT)) & ERM_EAR3_EAR_MASK) +/*! @} */ + +/*! @name SYN3 - ERM Memory 3 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN3_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN3_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN3_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN3_SYNDROME_SHIFT)) & ERM_SYN3_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT3_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_CORR_ERR_CNT3_COUNT_MASK) +/*! @} */ + +/*! @name EAR4 - ERM Memory 4 Error Address Register */ +/*! @{ */ + +#define ERM_EAR4_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR4_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR4_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR4_EAR_SHIFT)) & ERM_EAR4_EAR_MASK) +/*! @} */ + +/*! @name SYN4 - ERM Memory 4 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN4_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN4_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN4_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN4_SYNDROME_SHIFT)) & ERM_SYN4_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT4_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT4_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_CORR_ERR_CNT4_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT5_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_CORR_ERR_CNT5_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT6_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_CORR_ERR_CNT6_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT7_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_CORR_ERR_CNT7_COUNT_MASK) +/*! @} */ + +/*! @name SYN8 - ERM Memory 8 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN8_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN8_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN8_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN8_SYNDROME_SHIFT)) & ERM_SYN8_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT8_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT8_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT8_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_CORR_ERR_CNT8_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT9_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT9_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT9_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_CORR_ERR_CNT9_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ERM_Register_Masks */ + + +/* ERM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x5005C000u) + /** Peripheral ERM0 base address */ + #define ERM0_BASE_NS (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Peripheral ERM0 base pointer */ + #define ERM0_NS ((ERM_Type *)ERM0_BASE_NS) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS_NS { ERM0_BASE_NS } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS_NS { ERM0_NS } +#else + /** Peripheral ERM0 base address */ + #define ERM0_BASE (0x4005C000u) + /** Peripheral ERM0 base pointer */ + #define ERM0 ((ERM_Type *)ERM0_BASE) + /** Array initializer of ERM peripheral base addresses */ + #define ERM_BASE_ADDRS { ERM0_BASE } + /** Array initializer of ERM peripheral base pointers */ + #define ERM_BASE_PTRS { ERM0 } +#endif + +/*! + * @} + */ /* end of group ERM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EVTG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EVTG_Peripheral_Access_Layer EVTG Peripheral Access Layer + * @{ + */ + +/** EVTG - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_BFT01; /**< AOI0 Boolean Function Term 0 and 1 Configuration, array offset: 0x0, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_BFT23; /**< AOI0 Boolean Function Term 2 and 3 Configuration, array offset: 0x2, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_BFT01; /**< AOI1 Boolean Function Term 0 and 1 Configuration, array offset: 0x4, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_BFT23; /**< AOI1 Boolean Function Term 2 and 3 Configuration, array offset: 0x6, array step: 0x10 */ + uint8_t RESERVED_0[2]; + __IO uint16_t EVTG_CTRL; /**< Control and Status, array offset: 0xA, array step: 0x10 */ + __IO uint16_t EVTG_AOI0_FILT; /**< AOI0 Output Filter, array offset: 0xC, array step: 0x10 */ + __IO uint16_t EVTG_AOI1_FILT; /**< AOI1 Output Filter, array offset: 0xE, array step: 0x10 */ + } EVTG_INST[4]; +} EVTG_Type; + +/* ---------------------------------------------------------------------------- + -- EVTG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EVTG_Register_Masks EVTG Register Masks + * @{ + */ + +/*! @name EVTG_INST_EVTG_AOI0_BFT01 - AOI0 Boolean Function Term 0 and 1 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT01 */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT01_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI0_BFT23 - AOI0 Boolean Function Term 2 and 3 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_BFT23 */ +#define EVTG_EVTG_INST_EVTG_AOI0_BFT23_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_BFT01 - AOI1 Boolean Function Term 0 and 1 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT01 */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT01_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_BFT23 - AOI1 Boolean Function Term 2 and 3 Configuration */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK (0x3U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK (0xCU) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK (0x30U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK (0x300U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, D Input Configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK (0xC00U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, C Input Configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, B Input Configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK (0xC000U) +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, A Input Configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_BFT23 */ +#define EVTG_EVTG_INST_EVTG_AOI1_BFT23_COUNT (4U) + +/*! @name EVTG_INST_EVTG_CTRL - Control and Status */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK (0x1U) +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT (0U) +/*! FF_INIT - Flip flop Initial Value Configuration + * 0b0..0 + * 0b1..1 + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FF_INIT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK (0x2U) +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT (1U) +/*! INIT_EN - Flip-Flop Initial Output Enable Control + * 0b0..Write 0 does not generate enable pulse + * 0b1..Write 1 generates enable pulse + */ +#define EVTG_EVTG_INST_EVTG_CTRL_INIT_EN(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK (0x1CU) +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT (2U) +/*! MODE_SEL - Flip-Flop Mode Selection + * 0b000..Bypass mode + * 0b001..RS Trigger mode + * 0b010..T-FF mode + * 0b011..D-FF mode + * 0b100..JK-FF mode + * 0b101..Latch mode + * 0b110..Reserved + * 0b111..Reserved + */ +#define EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK (0xC0U) +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT (6U) +/*! FB_OVRD - EVTG Output Feedback Override Control + * 0b00..Replace An + * 0b01..Replace Bn + * 0b10..Replace Cn + * 0b11..Replace Dn + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK (0xF00U) +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT (8U) +/*! SYNC_CTRL - Synchronize Control + * 0bxxx1..EVTG input "An" will be synced by two bus clk cycles + * 0bxxx0..EVTG input "An" will not be synced + * 0bxx1x..EVTG input "Bn" will be synced by two bus clk cycles + * 0bxx0x..EVTG input "Bn" will not be synced + * 0bx1xx..EVTG input "Cn" will be synced by two bus clk cycles + * 0bx0xx..EVTG input "Cn" will not be synced + * 0b1xxx..EVTG input "Dn" will be synced by two bus clk cycles + * 0b0xxx..EVTG input "Dn" will not be synced + */ +#define EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL_MASK) + +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK (0x3000U) +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT (12U) +/*! FORCE_BYPASS - Force Bypass Control + * 0bx1..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_0(Filter_0) value directly to EVTG_OUTA + * 0bx0..Will not force the bypass + * 0b1x..Whatever MODE_SEL is, will force bypass flip-flop and route the AOI_1(Filter_1) value directly to EVTG_OUTB + * 0b0x..Will not force the bypass + */ +#define EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_SHIFT)) & EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_CTRL */ +#define EVTG_EVTG_INST_EVTG_CTRL_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI0_FILT - AOI0 Output Filter */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK (0xFFU) +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Output Filter Sample Period */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK (0x700U) +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Output Filter Sample Count */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI0_FILT */ +#define EVTG_EVTG_INST_EVTG_AOI0_FILT_COUNT (4U) + +/*! @name EVTG_INST_EVTG_AOI1_FILT - AOI1 Output Filter */ +/*! @{ */ + +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK (0xFFU) +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Output Filter Sample Period */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER_MASK) + +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK (0x700U) +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Output Filter Sample Count */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_SHIFT)) & EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of EVTG_EVTG_INST_EVTG_AOI1_FILT */ +#define EVTG_EVTG_INST_EVTG_AOI1_FILT_COUNT (4U) + + +/*! + * @} + */ /* end of group EVTG_Register_Masks */ + + +/* EVTG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x500D2000u) + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE_NS (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Peripheral EVTG0 base pointer */ + #define EVTG0_NS ((EVTG_Type *)EVTG0_BASE_NS) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS_NS { EVTG0_BASE_NS } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS_NS { EVTG0_NS } +#else + /** Peripheral EVTG0 base address */ + #define EVTG0_BASE (0x400D2000u) + /** Peripheral EVTG0 base pointer */ + #define EVTG0 ((EVTG_Type *)EVTG0_BASE) + /** Array initializer of EVTG peripheral base addresses */ + #define EVTG_BASE_ADDRS { EVTG0_BASE } + /** Array initializer of EVTG peripheral base pointers */ + #define EVTG_BASE_PTRS { EVTG0 } +#endif + +/*! + * @} + */ /* end of group EVTG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control, offset: 0x0 */ + __O uint8_t SERV; /**< Service, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +/*! EWMEN - EWM Enable + * 0b0..Disables + * 0b1..Enables + */ +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) + +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +/*! ASSIN - Assertion State Select + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) + +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +/*! INEN - Input Enable + * 0b0..Disables + * 0b1..Enables + */ +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) + +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +/*! INTEN - Interrupt Enable + * 0b1..Generates interrupt requests + * 0b0..Deasserts interrupt requests + */ +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service */ +/*! @{ */ + +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +/*! SERVICE - Service */ +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low */ +/*! @{ */ + +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +/*! COMPAREL - Compare Low */ +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High */ +/*! @{ */ + +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +/*! COMPAREH - Compare High */ +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control */ +/*! @{ */ + +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +/*! CLKSEL - Clock Select */ +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler */ +/*! @{ */ + +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +/*! CLK_DIV - Clock Divider */ +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x500C0000u) + /** Peripheral EWM0 base address */ + #define EWM0_BASE_NS (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Peripheral EWM0 base pointer */ + #define EWM0_NS ((EWM_Type *)EWM0_BASE_NS) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS_NS { EWM0_BASE_NS } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS_NS { EWM0_NS } +#else + /** Peripheral EWM0 base address */ + #define EWM0_BASE (0x400C0000u) + /** Peripheral EWM0 base pointer */ + #define EWM0 ((EWM_Type *)EWM0_BASE) + /** Array initializer of EWM peripheral base addresses */ + #define EWM_BASE_ADDRS { EWM0_BASE } + /** Array initializer of EWM peripheral base pointers */ + #define EWM_BASE_PTRS { EWM0 } +#endif + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ + uint8_t RESERVED_4[4]; + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SHIFTCTL[8]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_6[96]; + __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_7[224]; + __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[96]; + __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[96]; + __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_10[96]; + __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_11[96]; + __IO uint32_t TIMCTL[8]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[96]; + __IO uint32_t TIMCFG[8]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_13[96]; + __IO uint32_t TIMCMP[8]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_14[352]; + __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_15[96]; + __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_16[96]; + __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ + uint8_t RESERVED_17[96]; + __IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_18[96]; + __IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_19[96]; + __IO uint32_t SHIFTBUFHBS[8]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FLEXIO Control */ +/*! @{ */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FLEXIO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Normal + * 0b1..Fast + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State */ +/*! @{ */ + +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status */ +/*! @{ */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error */ +/*! @{ */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Flag */ +/*! @{ */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name TIMERSDEN - Timer Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) +/*! TSDE - Timer Status DMA Enable */ +#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State */ +/*! @{ */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name TRGSTAT - Trigger Status */ +/*! @{ */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xFFU) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) +/*! ETSF - External Trigger Status Flag + * 0b00000000..Clear + * 0b00000001..Set + * 0b00000000..No effect + * 0b00000001..Clear the flag + */ +#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) +/*! @} */ + +/*! @name TRIGIEN - External Trigger Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xFFU) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) +/*! TRIE - External Trigger Interrupt Enable */ +#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) +/*! @} */ + +/*! @name PINSTAT - Pin Status */ +/*! @{ */ + +#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) +#define FLEXIO_PINSTAT_PSF_SHIFT (0U) +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Clear the flag + */ +#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) +/*! @} */ + +/*! @name PINIEN - Pin Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINIEN_PSIE_SHIFT (0U) +/*! PSIE - Pin Status Interrupt Enable */ +#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) +/*! @} */ + +/*! @name PINREN - Pin Rising Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINREN_PRE_SHIFT (0U) +/*! PRE - Pin Rising Edge */ +#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) +/*! @} */ + +/*! @name PINFEN - Pin Falling Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINFEN_PFE_SHIFT (0U) +/*! PFE - Pin Falling Edge */ +#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) +/*! @} */ + +/*! @name PINOUTD - Pin Output Data */ +/*! @{ */ + +#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTD_OUTD_SHIFT (0U) +/*! OUTD - Output Data */ +#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) +/*! @} */ + +/*! @name PINOUTE - Pin Output Enable */ +/*! @{ */ + +#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTE_OUTE_SHIFT (0U) +/*! OUTE - Output Enable */ +#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) +/*! @} */ + +/*! @name PINOUTDIS - Pin Output Disable */ +/*! @{ */ + +#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) +/*! OUTDIS - Output Disable */ +#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) +/*! @} */ + +/*! @name PINOUTCLR - Pin Output Clear */ +/*! @{ */ + +#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) +/*! OUTCLR - Output Clear */ +#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) +/*! @} */ + +/*! @name PINOUTSET - Pin Output Set */ +/*! @{ */ + +#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) +/*! OUTSET - Output Set */ +#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) +/*! @} */ + +/*! @name PINOUTTOG - Pin Output Toggle */ +/*! @{ */ + +#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) +/*! OUTTOG - Output Toggle */ +#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control */ +/*! @{ */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open-drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Positive edge + * 0b1..Negative edge + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (8U) + +/*! @name SHIFTCFG - Shifter Configuration */ +/*! @{ */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter n+1 output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) +/*! LATST - Late Store + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state + */ +#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) +/*! SSIZE - Shifter Size + * 0b0..32-bit + * 0b1..24-bit + */ +#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (8U) + +/*! @name SHIFTBUF - Shifter Buffer */ +/*! @{ */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (8U) + +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (8U) + +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (8U) + +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (8U) + +/*! @name TIMCTL - Timer Control */ +/*! @{ */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) +#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) +/*! ONETIM - Timer One Time Operation + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear + */ +#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + +#define FLEXIO_TIMCTL_PININS_MASK (0x40U) +#define FLEXIO_TIMCTL_PININS_SHIFT (6U) +/*! PININS - Timer Pin Input Select + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL + */ +#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open-drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (8U) + +/*! @name TIMCFG - Timer Configuration */ +/*! @{ */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low + * 0b100..Timer disabled on pin rising or falling edge + * 0b101..Timer disabled on pin rising or falling edge provided trigger is high + * 0b110..Timer disabled on trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Never reset timer + * 0b001..Timer reset on timer output high. + * 0b010..Timer reset on timer pin equal to timer output + * 0b011..Timer reset on timer trigger equal to timer output + * 0b100..Timer reset on timer pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on trigger rising edge + * 0b111..Timer reset on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (8U) + +/*! @name TIMCMP - Timer Compare */ +/*! @{ */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (8U) + +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (8U) + +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (8U) + +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (8U) + +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) +/*! SHIFTBUFOES - Shift Buffer */ +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFOES */ +#define FLEXIO_SHIFTBUFOES_COUNT (8U) + +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) +/*! SHIFTBUFEOS - Shift Buffer */ +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFEOS */ +#define FLEXIO_SHIFTBUFEOS_COUNT (8U) + +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) +/*! SHIFTBUFHBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHBS */ +#define FLEXIO_SHIFTBUFHBS_COUNT (8U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x50105000u) + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE_NS (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0_NS ((FLEXIO_Type *)FLEXIO0_BASE_NS) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS_NS { FLEXIO0_BASE_NS } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS_NS { FLEXIO0_NS } +#else + /** Peripheral FLEXIO0 base address */ + #define FLEXIO0_BASE (0x40105000u) + /** Peripheral FLEXIO0 base pointer */ + #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) + /** Array initializer of FLEXIO peripheral base addresses */ + #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } + /** Array initializer of FLEXIO peripheral base pointers */ + #define FLEXIO_BASE_PTRS { FLEXIO0 } +#endif +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer + * @{ + */ + +/** FMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FCCOB[8]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */ +} FMU_Type; + +/* ---------------------------------------------------------------------------- + -- FMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Register_Masks FMU Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMU_FSTAT_FAIL_MASK (0x1U) +#define FMU_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK) + +#define FMU_FSTAT_CMDABT_MASK (0x4U) +#define FMU_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK) + +#define FMU_FSTAT_PVIOL_MASK (0x10U) +#define FMU_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK) + +#define FMU_FSTAT_ACCERR_MASK (0x20U) +#define FMU_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK) + +#define FMU_FSTAT_CWSABT_MASK (0x40U) +#define FMU_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK) + +#define FMU_FSTAT_CCIF_MASK (0x80U) +#define FMU_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command, initialization, or power mode recovery in progress + * 0b1..Flash command, initialization, or power mode recovery has completed + */ +#define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK) + +#define FMU_FSTAT_CMDPRT_MASK (0x300U) +#define FMU_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command protection level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK) + +#define FMU_FSTAT_CMDP_MASK (0x800U) +#define FMU_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command protection status flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK) + +#define FMU_FSTAT_CMDDID_MASK (0xF000U) +#define FMU_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command domain ID */ +#define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK) + +#define FMU_FSTAT_DFDIF_MASK (0x10000U) +#define FMU_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + */ +#define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK) + +#define FMU_FSTAT_SALV_USED_MASK (0x20000U) +#define FMU_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK) + +#define FMU_FSTAT_PEWEN_MASK (0x3000000U) +#define FMU_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK) + +#define FMU_FSTAT_PERDY_MASK (0x80000000U) +#define FMU_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program-Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation not stalled + * 0b1..Program or sector erase command operation ready to execute + */ +#define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMU_FCNFG_CCIE_MASK (0x80U) +#define FMU_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled + */ +#define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK) + +#define FMU_FCNFG_ERSREQ_MASK (0x100U) +#define FMU_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK) + +#define FMU_FCNFG_DFDIE_MASK (0x10000U) +#define FMU_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled + */ +#define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK) + +#define FMU_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMU_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK) + +#define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMU_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMU_FCTRL_RWSC_MASK (0xFU) +#define FMU_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control */ +#define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK) + +#define FMU_FCTRL_FDFD_MASK (0x10000U) +#define FMU_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt + * request is generated if the DFDIE bit is set. + */ +#define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK) + +#define FMU_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMU_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FCCOB - Flash Common Command Object Registers */ +/*! @{ */ + +#define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU) +#define FMU_FCCOB_CCOBn_SHIFT (0U) +/*! CCOBn - CCOBn */ +#define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK) +/*! @} */ + +/* The count of FMU_FCCOB */ +#define FMU_FCCOB_COUNT (8U) + + +/*! + * @} + */ /* end of group FMU_Register_Masks */ + + +/* FMU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x50043000u) + /** Peripheral FMU0 base address */ + #define FMU0_BASE_NS (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Peripheral FMU0 base pointer */ + #define FMU0_NS ((FMU_Type *)FMU0_BASE_NS) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS_NS { FMU0_BASE_NS } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS_NS { FMU0_NS } +#else + /** Peripheral FMU0 base address */ + #define FMU0_BASE (0x40043000u) + /** Peripheral FMU0 base pointer */ + #define FMU0 ((FMU_Type *)FMU0_BASE) + /** Array initializer of FMU peripheral base addresses */ + #define FMU_BASE_ADDRS { FMU0_BASE } + /** Array initializer of FMU peripheral base pointers */ + #define FMU_BASE_PTRS { FMU0 } +#endif + +/*! + * @} + */ /* end of group FMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMUTEST Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Peripheral_Access_Layer FMUTEST Peripheral Access Layer + * @{ + */ + +/** FMUTEST - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + __I uint32_t FTEST; /**< Flash Test Register, offset: 0xC */ + __IO uint32_t FCCOB0; /**< Flash Command Control 0 Register, offset: 0x10 */ + __IO uint32_t FCCOB1; /**< Flash Command Control 1 Register, offset: 0x14 */ + __IO uint32_t FCCOB2; /**< Flash Command Control 2 Register, offset: 0x18 */ + __IO uint32_t FCCOB3; /**< Flash Command Control 3 Register, offset: 0x1C */ + __IO uint32_t FCCOB4; /**< Flash Command Control 4 Register, offset: 0x20 */ + __IO uint32_t FCCOB5; /**< Flash Command Control 5 Register, offset: 0x24 */ + __IO uint32_t FCCOB6; /**< Flash Command Control 6 Register, offset: 0x28 */ + __IO uint32_t FCCOB7; /**< Flash Command Control 7 Register, offset: 0x2C */ + uint8_t RESERVED_0[208]; + __IO uint32_t RESET_STATUS; /**< FMU Initialization Tracking Register, offset: 0x100 */ + __IO uint32_t MCTL; /**< FMU Control Register, offset: 0x104 */ + __I uint32_t BSEL_GEN; /**< FMU Block Select Generation Register, offset: 0x108 */ + __IO uint32_t PWR_OPT; /**< Power Mode Options Register, offset: 0x10C */ + __I uint32_t CMD_CHECK; /**< FMU Command Check Register, offset: 0x110 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BSEL; /**< FMU Block Select Register, offset: 0x120 */ + __IO uint32_t MSIZE; /**< FMU Memory Size Register, offset: 0x124 */ + __IO uint32_t FLASH_RD_ADD; /**< Flash Read Address Register, offset: 0x128 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FLASH_STOP_ADD; /**< Flash Stop Address Register, offset: 0x130 */ + __IO uint32_t FLASH_RD_CTRL; /**< Flash Read Control Register, offset: 0x134 */ + __IO uint32_t MM_ADDR; /**< Memory Map Address Register, offset: 0x138 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MM_WDATA; /**< Memory Map Write Data Register, offset: 0x140 */ + __IO uint32_t MM_CTL; /**< Memory Map Control Register, offset: 0x144 */ + __IO uint32_t UINT_CTL; /**< User Interface Control Register, offset: 0x148 */ + __IO uint32_t RD_DATA0; /**< Read Data 0 Register, offset: 0x14C */ + __IO uint32_t RD_DATA1; /**< Read Data 1 Register, offset: 0x150 */ + __IO uint32_t RD_DATA2; /**< Read Data 2 Register, offset: 0x154 */ + __IO uint32_t RD_DATA3; /**< Read Data 3 Register, offset: 0x158 */ + __IO uint32_t PARITY; /**< Parity Register, offset: 0x15C */ + __IO uint32_t RD_PATH_CTRL_STATUS; /**< Read Path Control and Status Register, offset: 0x160 */ + __IO uint32_t SMW_DIN0; /**< SMW DIN 0 Register, offset: 0x164 */ + __IO uint32_t SMW_DIN1; /**< SMW DIN 1 Register, offset: 0x168 */ + __IO uint32_t SMW_DIN2; /**< SMW DIN 2 Register, offset: 0x16C */ + __IO uint32_t SMW_DIN3; /**< SMW DIN 3 Register, offset: 0x170 */ + __IO uint32_t SMW_ADDR; /**< SMW Address Register, offset: 0x174 */ + __IO uint32_t SMW_CMD_WAIT; /**< SMW Command and Wait Register, offset: 0x178 */ + __I uint32_t SMW_STATUS; /**< SMW Status Register, offset: 0x17C */ + __IO uint32_t SOCTRIM0_0; /**< SoC Trim Phrase 0 Word 0 Register, offset: 0x180 */ + __IO uint32_t SOCTRIM0_1; /**< SoC Trim Phrase 0 Word 1 Register, offset: 0x184 */ + __IO uint32_t SOCTRIM0_2; /**< SoC Trim Phrase 0 Word 2 Register, offset: 0x188 */ + __IO uint32_t SOCTRIM0_3; /**< SoC Trim Phrase 0 Word 3 Register, offset: 0x18C */ + __IO uint32_t SOCTRIM1_0; /**< SoC Trim Phrase 1 Word 0 Register, offset: 0x190 */ + __IO uint32_t SOCTRIM1_1; /**< SoC Trim Phrase 1 Word 1 Register, offset: 0x194 */ + __IO uint32_t SOCTRIM1_2; /**< SoC Trim Phrase 1 Word 2 Register, offset: 0x198 */ + __IO uint32_t SOCTRIM1_3; /**< SoC Trim Phrase 1 Word 3 Register, offset: 0x19C */ + __IO uint32_t SOCTRIM2_0; /**< SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0 */ + __IO uint32_t SOCTRIM2_1; /**< SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4 */ + __IO uint32_t SOCTRIM2_2; /**< SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8 */ + __IO uint32_t SOCTRIM2_3; /**< SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC */ + __IO uint32_t SOCTRIM3_0; /**< SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0 */ + __IO uint32_t SOCTRIM3_1; /**< SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4 */ + __IO uint32_t SOCTRIM3_2; /**< SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8 */ + __IO uint32_t SOCTRIM3_3; /**< SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC */ + __IO uint32_t SOCTRIM4_0; /**< SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0 */ + __IO uint32_t SOCTRIM4_1; /**< SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4 */ + __IO uint32_t SOCTRIM4_2; /**< SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8 */ + __IO uint32_t SOCTRIM4_3; /**< SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC */ + __IO uint32_t SOCTRIM5_0; /**< SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0 */ + __IO uint32_t SOCTRIM5_1; /**< SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4 */ + __IO uint32_t SOCTRIM5_2; /**< SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8 */ + __IO uint32_t SOCTRIM5_3; /**< SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC */ + __IO uint32_t SOCTRIM6_0; /**< SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0 */ + __IO uint32_t SOCTRIM6_1; /**< SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4 */ + __IO uint32_t SOCTRIM6_2; /**< SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8 */ + __IO uint32_t SOCTRIM6_3; /**< SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC */ + __IO uint32_t SOCTRIM7_0; /**< SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0 */ + __IO uint32_t SOCTRIM7_1; /**< SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4 */ + __IO uint32_t SOCTRIM7_2; /**< SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8 */ + __IO uint32_t SOCTRIM7_3; /**< SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC */ + uint8_t RESERVED_4[4]; + __IO uint32_t R_IP_CONFIG; /**< BIST Configuration Register, offset: 0x204 */ + __IO uint32_t R_TESTCODE; /**< BIST Test Code Register, offset: 0x208 */ + __IO uint32_t R_DFT_CTRL; /**< BIST DFT Control Register, offset: 0x20C */ + __IO uint32_t R_ADR_CTRL; /**< BIST Address Control Register, offset: 0x210 */ + __IO uint32_t R_DATA_CTRL0; /**< BIST Data Control 0 Register, offset: 0x214 */ + __IO uint32_t R_PIN_CTRL; /**< BIST Pin Control Register, offset: 0x218 */ + __IO uint32_t R_CNT_LOOP_CTRL; /**< BIST Loop Count Control Register, offset: 0x21C */ + __IO uint32_t R_TIMER_CTRL; /**< BIST Timer Control Register, offset: 0x220 */ + __IO uint32_t R_TEST_CTRL; /**< BIST Test Control Register, offset: 0x224 */ + __O uint32_t R_ABORT_LOOP; /**< BIST Abort Loop Register, offset: 0x228 */ + __I uint32_t R_ADR_QUERY; /**< BIST Address Query Register, offset: 0x22C */ + __I uint32_t R_DOUT_QUERY0; /**< BIST DOUT Query 0 Register, offset: 0x230 */ + uint8_t RESERVED_5[8]; + __I uint32_t R_SMW_QUERY; /**< BIST SMW Query Register, offset: 0x23C */ + __IO uint32_t R_SMW_SETTING0; /**< BIST SMW Setting 0 Register, offset: 0x240 */ + __IO uint32_t R_SMW_SETTING1; /**< BIST SMW Setting 1 Register, offset: 0x244 */ + __IO uint32_t R_SMP_WHV0; /**< BIST SMP WHV Setting 0 Register, offset: 0x248 */ + __IO uint32_t R_SMP_WHV1; /**< BIST SMP WHV Setting 1 Register, offset: 0x24C */ + __IO uint32_t R_SME_WHV0; /**< BIST SME WHV Setting 0 Register, offset: 0x250 */ + __IO uint32_t R_SME_WHV1; /**< BIST SME WHV Setting 1 Register, offset: 0x254 */ + __IO uint32_t R_SMW_SETTING2; /**< BIST SMW Setting 2 Register, offset: 0x258 */ + __I uint32_t R_D_MISR0; /**< BIST DIN MISR 0 Register, offset: 0x25C */ + __I uint32_t R_A_MISR0; /**< BIST Address MISR 0 Register, offset: 0x260 */ + __I uint32_t R_C_MISR0; /**< BIST Control MISR 0 Register, offset: 0x264 */ + __IO uint32_t R_SMW_SETTING3; /**< BIST SMW Setting 3 Register, offset: 0x268 */ + __IO uint32_t R_DATA_CTRL1; /**< BIST Data Control 1 Register, offset: 0x26C */ + __IO uint32_t R_DATA_CTRL2; /**< BIST Data Control 2 Register, offset: 0x270 */ + __IO uint32_t R_DATA_CTRL3; /**< BIST Data Control 3 Register, offset: 0x274 */ + uint8_t RESERVED_6[8]; + __I uint32_t R_REPAIR0_0; /**< BIST Repair 0 for Block 0 Register, offset: 0x280 */ + __I uint32_t R_REPAIR0_1; /**< BIST Repair 1 Block 0 Register, offset: 0x284 */ + __I uint32_t R_REPAIR1_0; /**< BIST Repair 0 Block 1 Register, offset: 0x288 */ + __I uint32_t R_REPAIR1_1; /**< BIST Repair 1 Block 1 Register, offset: 0x28C */ + uint8_t RESERVED_7[132]; + __IO uint32_t R_DATA_CTRL0_EX; /**< BIST Data Control 0 Extension Register, offset: 0x314 */ + uint8_t RESERVED_8[8]; + __IO uint32_t R_TIMER_CTRL_EX; /**< BIST Timer Control Extension Register, offset: 0x320 */ + uint8_t RESERVED_9[12]; + __I uint32_t R_DOUT_QUERY1; /**< BIST DOUT Query 1 Register, offset: 0x330 */ + uint8_t RESERVED_10[40]; + __I uint32_t R_D_MISR1; /**< BIST DIN MISR 1 Register, offset: 0x35C */ + __I uint32_t R_A_MISR1; /**< BIST Address MISR 1 Register, offset: 0x360 */ + __I uint32_t R_C_MISR1; /**< BIST Control MISR 1 Register, offset: 0x364 */ + uint8_t RESERVED_11[4]; + __IO uint32_t R_DATA_CTRL1_EX; /**< BIST Data Control 1 Extension Register, offset: 0x36C */ + __IO uint32_t R_DATA_CTRL2_EX; /**< BIST Data Control 2 Extension Register, offset: 0x370 */ + __IO uint32_t R_DATA_CTRL3_EX; /**< BIST Data Control 3 Extension Register, offset: 0x374 */ + uint8_t RESERVED_12[136]; + __IO uint32_t SMW_TIMER_OPTION; /**< SMW Timer Option Register, offset: 0x400 */ + __IO uint32_t SMW_SETTING_OPTION0; /**< SMW Setting Option 0 Register, offset: 0x404 */ + __IO uint32_t SMW_SETTING_OPTION2; /**< SMW Setting Option 2 Register, offset: 0x408 */ + __IO uint32_t SMW_SETTING_OPTION3; /**< SMW Setting Option 3 Register, offset: 0x40C */ + __IO uint32_t SMW_SMP_WHV_OPTION0; /**< SMW SMP WHV Option 0 Register, offset: 0x410 */ + __IO uint32_t SMW_SME_WHV_OPTION0; /**< SMW SME WHV Option 0 Register, offset: 0x414 */ + __IO uint32_t SMW_SETTING_OPTION1; /**< SMW Setting Option 1 Register, offset: 0x418 */ + __IO uint32_t SMW_SMP_WHV_OPTION1; /**< SMW SMP WHV Option 1 Register, offset: 0x41C */ + __IO uint32_t SMW_SME_WHV_OPTION1; /**< SMW SME WHV Option 1 Register, offset: 0x420 */ + uint8_t RESERVED_13[220]; + __IO uint32_t REPAIR0_0; /**< FMU Repair 0 Block 0 Register, offset: 0x500 */ + __IO uint32_t REPAIR0_1; /**< FMU Repair 1 Block 0 Register, offset: 0x504 */ + __IO uint32_t REPAIR1_0; /**< FMU Repair 0 Block 1 Register, offset: 0x508 */ + __IO uint32_t REPAIR1_1; /**< FMU Repair 1 Block 1 Register, offset: 0x50C */ + uint8_t RESERVED_14[240]; + __IO uint32_t SMW_HB_SIGNALS; /**< SMW HB Signals Register, offset: 0x600 */ + __IO uint32_t BIST_DUMP_CTRL; /**< BIST Datadump Control Register, offset: 0x604 */ + uint8_t RESERVED_15[4]; + __IO uint32_t ATX_PIN_CTRL; /**< ATX Pin Control Register, offset: 0x60C */ + __IO uint32_t FAILCNT; /**< Fail Count Register, offset: 0x610 */ + __IO uint32_t PGM_PULSE_CNT0; /**< Block 0 Program Pulse Count Register, offset: 0x614 */ + __IO uint32_t PGM_PULSE_CNT1; /**< Block 1 Program Pulse Count Register, offset: 0x618 */ + __IO uint32_t ERS_PULSE_CNT; /**< Erase Pulse Count Register, offset: 0x61C */ + __IO uint32_t MAX_PULSE_CNT; /**< Maximum Pulse Count Register, offset: 0x620 */ + __IO uint32_t PORT_CTRL; /**< Port Control Register, offset: 0x624 */ +} FMUTEST_Type; + +/* ---------------------------------------------------------------------------- + -- FMUTEST Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Register_Masks FMUTEST Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMUTEST_FSTAT_FAIL_MASK (0x1U) +#define FMUTEST_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_FAIL_SHIFT)) & FMUTEST_FSTAT_FAIL_MASK) + +#define FMUTEST_FSTAT_CMDABT_MASK (0x4U) +#define FMUTEST_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMUTEST_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDABT_SHIFT)) & FMUTEST_FSTAT_CMDABT_MASK) + +#define FMUTEST_FSTAT_PVIOL_MASK (0x10U) +#define FMUTEST_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMUTEST_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PVIOL_SHIFT)) & FMUTEST_FSTAT_PVIOL_MASK) + +#define FMUTEST_FSTAT_ACCERR_MASK (0x20U) +#define FMUTEST_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMUTEST_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_ACCERR_SHIFT)) & FMUTEST_FSTAT_ACCERR_MASK) + +#define FMUTEST_FSTAT_CWSABT_MASK (0x40U) +#define FMUTEST_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMUTEST_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CWSABT_SHIFT)) & FMUTEST_FSTAT_CWSABT_MASK) + +#define FMUTEST_FSTAT_CCIF_MASK (0x80U) +#define FMUTEST_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command or initialization in progress + * 0b1..Flash command or initialization has completed + */ +#define FMUTEST_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CCIF_SHIFT)) & FMUTEST_FSTAT_CCIF_MASK) + +#define FMUTEST_FSTAT_CMDPRT_MASK (0x300U) +#define FMUTEST_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command Protection Level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMUTEST_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDPRT_SHIFT)) & FMUTEST_FSTAT_CMDPRT_MASK) + +#define FMUTEST_FSTAT_CMDP_MASK (0x800U) +#define FMUTEST_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command Protection Status Flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMUTEST_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDP_SHIFT)) & FMUTEST_FSTAT_CMDP_MASK) + +#define FMUTEST_FSTAT_CMDDID_MASK (0xF000U) +#define FMUTEST_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command Domain ID */ +#define FMUTEST_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDDID_SHIFT)) & FMUTEST_FSTAT_CMDDID_MASK) + +#define FMUTEST_FSTAT_DFDIF_MASK (0x10000U) +#define FMUTEST_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access from the FMC + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC + */ +#define FMUTEST_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_DFDIF_SHIFT)) & FMUTEST_FSTAT_DFDIF_MASK) + +#define FMUTEST_FSTAT_SALV_USED_MASK (0x20000U) +#define FMUTEST_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during the last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMUTEST_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_SALV_USED_SHIFT)) & FMUTEST_FSTAT_SALV_USED_MASK) + +#define FMUTEST_FSTAT_PEWEN_MASK (0x3000000U) +#define FMUTEST_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMUTEST_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PEWEN_SHIFT)) & FMUTEST_FSTAT_PEWEN_MASK) + +#define FMUTEST_FSTAT_PERDY_MASK (0x80000000U) +#define FMUTEST_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program/Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation is not stalled + * 0b1..Program or sector erase command operation is stalled + */ +#define FMUTEST_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PERDY_SHIFT)) & FMUTEST_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMUTEST_FCNFG_CCIE_MASK (0x80U) +#define FMUTEST_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. + */ +#define FMUTEST_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_CCIE_SHIFT)) & FMUTEST_FCNFG_CCIE_MASK) + +#define FMUTEST_FCNFG_ERSREQ_MASK (0x100U) +#define FMUTEST_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase (Erase All) Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMUTEST_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSREQ_SHIFT)) & FMUTEST_FCNFG_ERSREQ_MASK) + +#define FMUTEST_FCNFG_DFDIE_MASK (0x10000U) +#define FMUTEST_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set + */ +#define FMUTEST_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_DFDIE_SHIFT)) & FMUTEST_FCNFG_DFDIE_MASK) + +#define FMUTEST_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMUTEST_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN0_SHIFT)) & FMUTEST_FCNFG_ERSIEN0_MASK) + +#define FMUTEST_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMUTEST_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN1_SHIFT)) & FMUTEST_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMUTEST_FCTRL_RWSC_MASK (0xFU) +#define FMUTEST_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control + * 0b0000..no additional wait-states are added (single cycle access) + * 0b0001..1 additional wait-state is added + * 0b0010..2 additional wait-states are added + * 0b0011..3 additional wait-states are added + * 0b0100..4 additional wait-states are added + * 0b0101..5 additional wait-states are added + * 0b0110..6 additional wait-states are added + * 0b0111..7 additional wait-states are added + * 0b1000..8 additional wait-states are added + * 0b1001..9 additional wait-states are added + * 0b1010..10 additional wait-states are added + * 0b1011..11 additional wait-states are added + * 0b1100..12 additional wait-states are added + * 0b1101..13 additional wait-states are added + * 0b1110..14 additional wait-states are added + * 0b1111..15 additional wait-states are added + */ +#define FMUTEST_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_RWSC_SHIFT)) & FMUTEST_FCTRL_RWSC_MASK) + +#define FMUTEST_FCTRL_LSACTIVE_MASK (0x100U) +#define FMUTEST_FCTRL_LSACTIVE_SHIFT (8U) +/*! LSACTIVE - Low Speed Active Mode + * 0b0..Full speed active mode requested + * 0b1..Low speed active mode requested + */ +#define FMUTEST_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_LSACTIVE_SHIFT)) & FMUTEST_FCTRL_LSACTIVE_MASK) + +#define FMUTEST_FCTRL_FDFD_MASK (0x10000U) +#define FMUTEST_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set + */ +#define FMUTEST_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_FDFD_SHIFT)) & FMUTEST_FCTRL_FDFD_MASK) + +#define FMUTEST_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMUTEST_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMUTEST_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_ABTREQ_SHIFT)) & FMUTEST_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FTEST - Flash Test Register */ +/*! @{ */ + +#define FMUTEST_FTEST_TMECTL_MASK (0x1U) +#define FMUTEST_FTEST_TMECTL_SHIFT (0U) +/*! TMECTL - Test Mode Entry Control + * 0b0..FTEST register always reads 0 and writes to FTEST are ignored + * 0b1..FTEST register is readable and can be written to enable writability of TME + */ +#define FMUTEST_FTEST_TMECTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMECTL_SHIFT)) & FMUTEST_FTEST_TMECTL_MASK) + +#define FMUTEST_FTEST_TMEWR_MASK (0x2U) +#define FMUTEST_FTEST_TMEWR_SHIFT (1U) +/*! TMEWR - Test Mode Entry Writable + * 0b0..TME bit is not writable + * 0b1..TME bit is writable + */ +#define FMUTEST_FTEST_TMEWR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMEWR_SHIFT)) & FMUTEST_FTEST_TMEWR_MASK) + +#define FMUTEST_FTEST_TME_MASK (0x4U) +#define FMUTEST_FTEST_TME_SHIFT (2U) +/*! TME - Test Mode Entry + * 0b0..Test mode entry not requested + * 0b1..Test mode entry requested + */ +#define FMUTEST_FTEST_TME(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TME_SHIFT)) & FMUTEST_FTEST_TME_MASK) + +#define FMUTEST_FTEST_TMODE_MASK (0x8U) +#define FMUTEST_FTEST_TMODE_SHIFT (3U) +/*! TMODE - Test Mode Status + * 0b0..Test mode not active + * 0b1..Test mode active + */ +#define FMUTEST_FTEST_TMODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMODE_SHIFT)) & FMUTEST_FTEST_TMODE_MASK) + +#define FMUTEST_FTEST_TMELOCK_MASK (0x10U) +#define FMUTEST_FTEST_TMELOCK_SHIFT (4U) +/*! TMELOCK - Test Mode Entry Lock + * 0b0..FTEST register not locked from accepting writes + * 0b1..FTEST register locked from accepting writes + */ +#define FMUTEST_FTEST_TMELOCK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMELOCK_SHIFT)) & FMUTEST_FTEST_TMELOCK_MASK) +/*! @} */ + +/*! @name FCCOB0 - Flash Command Control 0 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB0_CMDCODE_MASK (0xFFU) +#define FMUTEST_FCCOB0_CMDCODE_SHIFT (0U) +/*! CMDCODE - Command code */ +#define FMUTEST_FCCOB0_CMDCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB0_CMDCODE_SHIFT)) & FMUTEST_FCCOB0_CMDCODE_MASK) +/*! @} */ + +/*! @name FCCOB1 - Flash Command Control 1 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB1_CMDOPT_MASK (0xFFU) +#define FMUTEST_FCCOB1_CMDOPT_SHIFT (0U) +/*! CMDOPT - Command options */ +#define FMUTEST_FCCOB1_CMDOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB1_CMDOPT_SHIFT)) & FMUTEST_FCCOB1_CMDOPT_MASK) +/*! @} */ + +/*! @name FCCOB2 - Flash Command Control 2 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB2_CMDADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB2_CMDADDR_SHIFT (0U) +/*! CMDADDR - Command starting address */ +#define FMUTEST_FCCOB2_CMDADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB2_CMDADDR_SHIFT)) & FMUTEST_FCCOB2_CMDADDR_MASK) +/*! @} */ + +/*! @name FCCOB3 - Flash Command Control 3 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB3_CMDADDRE_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB3_CMDADDRE_SHIFT (0U) +/*! CMDADDRE - Command ending address */ +#define FMUTEST_FCCOB3_CMDADDRE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB3_CMDADDRE_SHIFT)) & FMUTEST_FCCOB3_CMDADDRE_MASK) +/*! @} */ + +/*! @name FCCOB4 - Flash Command Control 4 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB4_CMDDATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB4_CMDDATA0_SHIFT (0U) +/*! CMDDATA0 - Command data word 0 */ +#define FMUTEST_FCCOB4_CMDDATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB4_CMDDATA0_SHIFT)) & FMUTEST_FCCOB4_CMDDATA0_MASK) +/*! @} */ + +/*! @name FCCOB5 - Flash Command Control 5 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB5_CMDDATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB5_CMDDATA1_SHIFT (0U) +/*! CMDDATA1 - Command data word 1 */ +#define FMUTEST_FCCOB5_CMDDATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB5_CMDDATA1_SHIFT)) & FMUTEST_FCCOB5_CMDDATA1_MASK) +/*! @} */ + +/*! @name FCCOB6 - Flash Command Control 6 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB6_CMDDATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB6_CMDDATA2_SHIFT (0U) +/*! CMDDATA2 - Command data word 2 */ +#define FMUTEST_FCCOB6_CMDDATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB6_CMDDATA2_SHIFT)) & FMUTEST_FCCOB6_CMDDATA2_MASK) +/*! @} */ + +/*! @name FCCOB7 - Flash Command Control 7 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB7_CMDDATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB7_CMDDATA3_SHIFT (0U) +/*! CMDDATA3 - Command data word 3 */ +#define FMUTEST_FCCOB7_CMDDATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB7_CMDDATA3_SHIFT)) & FMUTEST_FCCOB7_CMDDATA3_MASK) +/*! @} */ + +/*! @name RESET_STATUS - FMU Initialization Tracking Register */ +/*! @{ */ + +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK (0x1U) +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT (0U) +/*! ARY_TRIM_DONE - Array Trim Complete + * 0b0..Recall register load operation has not been completed + * 0b1..Recall register load operation has completed + */ +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK (0x2U) +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT (1U) +/*! FMU_PARM_EN - Status of the C0DE_C0DEh check to enable loading of the FMU parameters + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK (0x4U) +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT (2U) +/*! FMU_PARM_DONE - FMU Register Load Complete + * 0b0..FMU registers have not been loaded + * 0b1..FMU registers have been loaded + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK (0x8U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT (3U) +/*! SOC_TRIM_EN - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK (0x10U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT (4U) +/*! SOC_TRIM_ECC - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings + * 0b0..C0DE_C0DEh check failed + * 0b1..C0DE_C0DEh check passed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK (0x20U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT (5U) +/*! SOC_TRIM_DONE - SoC Trim Complete + * 0b0..SoC Trim registers have not been updated + * 0b1..All SoC Trim registers have been updated + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RPR_DONE_MASK (0x40U) +#define FMUTEST_RESET_STATUS_RPR_DONE_SHIFT (6U) +/*! RPR_DONE - Array Repair Complete + * 0b0..Repair registers have not been loaded + * 0b1..Repair registers have been loaded + */ +#define FMUTEST_RESET_STATUS_RPR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RPR_DONE_SHIFT)) & FMUTEST_RESET_STATUS_RPR_DONE_MASK) + +#define FMUTEST_RESET_STATUS_INIT_DONE_MASK (0x80U) +#define FMUTEST_RESET_STATUS_INIT_DONE_SHIFT (7U) +/*! INIT_DONE - Initialization Done + * 0b0..All initialization steps did not complete + * 0b1..All initialization steps completed + */ +#define FMUTEST_RESET_STATUS_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_INIT_DONE_SHIFT)) & FMUTEST_RESET_STATUS_INIT_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RST_SF_ERR_MASK (0x100U) +#define FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT (8U) +/*! RST_SF_ERR - ECC Single Fault during Reset Recovery + * 0b0..No single-bit faults detected during initialization + * 0b1..At least one single ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_SF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_SF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_DF_ERR_MASK (0x200U) +#define FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT (9U) +/*! RST_DF_ERR - ECC Double Fault during Reset Recovery + * 0b0..No double-bit faults detected during initialization + * 0b1..Double-bit ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK (0x3FC00U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT (10U) +/*! SOC_TRIM_DF_ERR - ECC Double Fault during load of SoC Trim phrases */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK (0x40000U) +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT (18U) +/*! RST_PATCH_LD - Reset Patch Required + * 0b0..No patch required to be loaded during reset + * 0b1..Patch loaded during reset + */ +#define FMUTEST_RESET_STATUS_RST_PATCH_LD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT)) & FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK) + +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK (0x80000U) +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT (19U) +/*! RECALL_DATA_MISMATCH - Recall Data Mismatch + * 0b0..Data read towards end of reset matched data read for Recall + * 0b1..Data read towards end of reset did not match data read for recall + */ +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT)) & FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK) +/*! @} */ + +/*! @name MCTL - FMU Control Register */ +/*! @{ */ + +#define FMUTEST_MCTL_COREHLD_MASK (0x1U) +#define FMUTEST_MCTL_COREHLD_SHIFT (0U) +/*! COREHLD - Core Hold + * 0b0..CPU access is allowed + * 0b1..CPU access must be blocked + */ +#define FMUTEST_MCTL_COREHLD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_COREHLD_SHIFT)) & FMUTEST_MCTL_COREHLD_MASK) + +#define FMUTEST_MCTL_LSACT_EN_MASK (0x4U) +#define FMUTEST_MCTL_LSACT_EN_SHIFT (2U) +/*! LSACT_EN - LSACTIVE Feature Enable + * 0b0..LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface. + * 0b1..LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM. + */ +#define FMUTEST_MCTL_LSACT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACT_EN_SHIFT)) & FMUTEST_MCTL_LSACT_EN_MASK) + +#define FMUTEST_MCTL_LSACTWREN_MASK (0x8U) +#define FMUTEST_MCTL_LSACTWREN_SHIFT (3U) +/*! LSACTWREN - LSACTIVE Write Enable + * 0b0..Unrestricted write access allowed + * 0b1..Write access while CMP set must match CMDDID and CMDPRT + */ +#define FMUTEST_MCTL_LSACTWREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACTWREN_SHIFT)) & FMUTEST_MCTL_LSACTWREN_MASK) + +#define FMUTEST_MCTL_MASTER_REPAIR_EN_MASK (0x10U) +#define FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT (4U) +/*! MASTER_REPAIR_EN - Master Repair Enable + * 0b0..Repair disabled + * 0b1..Repair enable determined by bit 0 of each REPAIR register + */ +#define FMUTEST_MCTL_MASTER_REPAIR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT)) & FMUTEST_MCTL_MASTER_REPAIR_EN_MASK) + +#define FMUTEST_MCTL_RFCMDEN_MASK (0x20U) +#define FMUTEST_MCTL_RFCMDEN_SHIFT (5U) +/*! RFCMDEN - RF Active Command Enable Control + * 0b0..Flash commands blocked (CCIF not writable) + * 0b1..Flash commands allowed + */ +#define FMUTEST_MCTL_RFCMDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_RFCMDEN_SHIFT)) & FMUTEST_MCTL_RFCMDEN_MASK) + +#define FMUTEST_MCTL_CWSABTEN_MASK (0x40U) +#define FMUTEST_MCTL_CWSABTEN_SHIFT (6U) +/*! CWSABTEN - Command Write Sequence Abort Enable + * 0b0..CWS abort feature is disabled + * 0b1..CWS abort feature is enabled + */ +#define FMUTEST_MCTL_CWSABTEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_CWSABTEN_SHIFT)) & FMUTEST_MCTL_CWSABTEN_MASK) + +#define FMUTEST_MCTL_MRGRDDIS_MASK (0x80U) +#define FMUTEST_MCTL_MRGRDDIS_SHIFT (7U) +/*! MRGRDDIS - Margin Read Disable + * 0b0..Margin Read Settings are enabled + * 0b1..Margin Read Settings are disabled + */ +#define FMUTEST_MCTL_MRGRDDIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRDDIS_SHIFT)) & FMUTEST_MCTL_MRGRDDIS_MASK) + +#define FMUTEST_MCTL_MRGRD0_MASK (0xF00U) +#define FMUTEST_MCTL_MRGRD0_SHIFT (8U) +/*! MRGRD0 - Margin Read Setting for Program */ +#define FMUTEST_MCTL_MRGRD0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD0_SHIFT)) & FMUTEST_MCTL_MRGRD0_MASK) + +#define FMUTEST_MCTL_MRGRD1_MASK (0xF000U) +#define FMUTEST_MCTL_MRGRD1_SHIFT (12U) +/*! MRGRD1 - Margin Read Setting for Erase */ +#define FMUTEST_MCTL_MRGRD1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD1_SHIFT)) & FMUTEST_MCTL_MRGRD1_MASK) + +#define FMUTEST_MCTL_ERSAACK_MASK (0x10000U) +#define FMUTEST_MCTL_ERSAACK_SHIFT (16U) +/*! ERSAACK - Mass Erase (Erase All) Acknowledge + * 0b0..Mass Erase operation is not active (operation has completed or has not started) + * 0b1..Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation) + */ +#define FMUTEST_MCTL_ERSAACK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_ERSAACK_SHIFT)) & FMUTEST_MCTL_ERSAACK_MASK) + +#define FMUTEST_MCTL_SCAN_OBS_MASK (0x80000U) +#define FMUTEST_MCTL_SCAN_OBS_SHIFT (19U) +/*! SCAN_OBS - Scan Observability Control + * 0b0..Normal functional behavior + * 0b1..Enables observation of signals that may otherwise be ATPG untestable + */ +#define FMUTEST_MCTL_SCAN_OBS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SCAN_OBS_SHIFT)) & FMUTEST_MCTL_SCAN_OBS_MASK) + +#define FMUTEST_MCTL_BIST_CTL_MASK (0x100000U) +#define FMUTEST_MCTL_BIST_CTL_SHIFT (20U) +/*! BIST_CTL - BIST IP Control + * 0b0..BIST IP disabled + * 0b1..BIST IP enabled + */ +#define FMUTEST_MCTL_BIST_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_CTL_SHIFT)) & FMUTEST_MCTL_BIST_CTL_MASK) + +#define FMUTEST_MCTL_SMWR_CTL_MASK (0x200000U) +#define FMUTEST_MCTL_SMWR_CTL_SHIFT (21U) +/*! SMWR_CTL - SMWR IP Control + * 0b0..SMWR IP disabled + * 0b1..SMWR IP enabled + */ +#define FMUTEST_MCTL_SMWR_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SMWR_CTL_SHIFT)) & FMUTEST_MCTL_SMWR_CTL_MASK) + +#define FMUTEST_MCTL_SALV_DIS_MASK (0x1000000U) +#define FMUTEST_MCTL_SALV_DIS_SHIFT (24U) +/*! SALV_DIS - Salvage Disable + * 0b0..Salvage enabled (ECC used during erase verify) + * 0b1..Salvage disabled (ECC not used during erase verify) + */ +#define FMUTEST_MCTL_SALV_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SALV_DIS_SHIFT)) & FMUTEST_MCTL_SALV_DIS_MASK) + +#define FMUTEST_MCTL_SOC_ECC_CTL_MASK (0x2000000U) +#define FMUTEST_MCTL_SOC_ECC_CTL_SHIFT (25U) +/*! SOC_ECC_CTL - SOC ECC Control + * 0b0..ECC is enabled for SOC read access + * 0b1..ECC is disabled for SOC read access + */ +#define FMUTEST_MCTL_SOC_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SOC_ECC_CTL_SHIFT)) & FMUTEST_MCTL_SOC_ECC_CTL_MASK) + +#define FMUTEST_MCTL_FMU_ECC_CTL_MASK (0x4000000U) +#define FMUTEST_MCTL_FMU_ECC_CTL_SHIFT (26U) +/*! FMU_ECC_CTL - FMU ECC Control + * 0b0..ECC is enabled for FMU program operations + * 0b1..ECC is disabled for FMU program operations + */ +#define FMUTEST_MCTL_FMU_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_FMU_ECC_CTL_SHIFT)) & FMUTEST_MCTL_FMU_ECC_CTL_MASK) + +#define FMUTEST_MCTL_BIST_PWR_DIS_MASK (0x20000000U) +#define FMUTEST_MCTL_BIST_PWR_DIS_SHIFT (29U) +/*! BIST_PWR_DIS - BIST Power Mode Disable + * 0b0..BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands) + * 0b1..BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values + */ +#define FMUTEST_MCTL_BIST_PWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_PWR_DIS_SHIFT)) & FMUTEST_MCTL_BIST_PWR_DIS_MASK) + +#define FMUTEST_MCTL_OSC_H_MASK (0x80000000U) +#define FMUTEST_MCTL_OSC_H_SHIFT (31U) +/*! OSC_H - Oscillator control + * 0b0..Use APB clock + * 0b1..Use a known fixed-frequency clock, e.g. 12 MHz + */ +#define FMUTEST_MCTL_OSC_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_OSC_H_SHIFT)) & FMUTEST_MCTL_OSC_H_MASK) +/*! @} */ + +/*! @name BSEL_GEN - FMU Block Select Generation Register */ +/*! @{ */ + +#define FMUTEST_BSEL_GEN_SBSEL_GEN_MASK (0x3U) +#define FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT (0U) +/*! SBSEL_GEN - Generated SBSEL */ +#define FMUTEST_BSEL_GEN_SBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_SBSEL_GEN_MASK) + +#define FMUTEST_BSEL_GEN_MBSEL_GEN_MASK (0x300U) +#define FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT (8U) +/*! MBSEL_GEN - Generated MBSEL */ +#define FMUTEST_BSEL_GEN_MBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_MBSEL_GEN_MASK) +/*! @} */ + +/*! @name PWR_OPT - Power Mode Options Register */ +/*! @{ */ + +#define FMUTEST_PWR_OPT_PD_CDIV_MASK (0xFFU) +#define FMUTEST_PWR_OPT_PD_CDIV_SHIFT (0U) +/*! PD_CDIV - Power Down Clock Divider Setting */ +#define FMUTEST_PWR_OPT_PD_CDIV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_CDIV_SHIFT)) & FMUTEST_PWR_OPT_PD_CDIV_MASK) + +#define FMUTEST_PWR_OPT_SLM_COUNT_MASK (0x3FF0000U) +#define FMUTEST_PWR_OPT_SLM_COUNT_SHIFT (16U) +/*! SLM_COUNT - Sleep Recovery Timer Count */ +#define FMUTEST_PWR_OPT_SLM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_SLM_COUNT_SHIFT)) & FMUTEST_PWR_OPT_SLM_COUNT_MASK) + +#define FMUTEST_PWR_OPT_PD_TIMER_EN_MASK (0x80000000U) +#define FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT (31U) +/*! PD_TIMER_EN - Power Down BIST Timer Enable + * 0b0..BIST timer is not triggered during Power Down recovery + * 0b1..BIST timer is triggered during Power Down recovery (default behavior) + */ +#define FMUTEST_PWR_OPT_PD_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT)) & FMUTEST_PWR_OPT_PD_TIMER_EN_MASK) +/*! @} */ + +/*! @name CMD_CHECK - FMU Command Check Register */ +/*! @{ */ + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK (0x1U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT (0U) +/*! ALIGNFAIL_PHR - Phrase Alignment Fail + * 0b0..The address is phrase-aligned + * 0b1..The address is not phrase-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK (0x2U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT (1U) +/*! ALIGNFAIL_PG - Page Alignment Fail + * 0b0..The address is page-aligned + * 0b1..The address is not page-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK (0x4U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT (2U) +/*! ALIGNFAIL_SCR - Sector Alignment Fail + * 0b0..The address is sector-aligned + * 0b1..The address is not sector-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK (0x8U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT (3U) +/*! ALIGNFAIL_BLK - Block Alignment Fail + * 0b0..The address is block-aligned + * 0b1..The address is not block-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK) + +#define FMUTEST_CMD_CHECK_ADDR_FAIL_MASK (0x10U) +#define FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT (4U) +/*! ADDR_FAIL - Address Fail + * 0b0..The address is within the flash or IFR address space + * 0b1..The address is outside the flash or IFR address space + */ +#define FMUTEST_CMD_CHECK_ADDR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_ADDR_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_IFR_CMD_MASK (0x20U) +#define FMUTEST_CMD_CHECK_IFR_CMD_SHIFT (5U) +/*! IFR_CMD - IFR Command + * 0b0..The command operates on a main flash address + * 0b1..The command operates on an IFR address + */ +#define FMUTEST_CMD_CHECK_IFR_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_IFR_CMD_SHIFT)) & FMUTEST_CMD_CHECK_IFR_CMD_MASK) + +#define FMUTEST_CMD_CHECK_ALL_CMD_MASK (0x40U) +#define FMUTEST_CMD_CHECK_ALL_CMD_SHIFT (6U) +/*! ALL_CMD - All Blocks Command + * 0b0..The command operates on a single flash block + * 0b1..The command operates on all flash blocks + */ +#define FMUTEST_CMD_CHECK_ALL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ALL_CMD_MASK) + +#define FMUTEST_CMD_CHECK_RANGE_FAIL_MASK (0x80U) +#define FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT (7U) +/*! RANGE_FAIL - Address Range Fail + * 0b0..The address range is valid + * 0b1..The address range is invalid + */ +#define FMUTEST_CMD_CHECK_RANGE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_RANGE_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK (0x100U) +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT (8U) +/*! SCR_ALIGN_CHK - Sector Alignment Check + * 0b0..No sector alignment check + * 0b1..Sector alignment check + */ +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT)) & FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK) + +#define FMUTEST_CMD_CHECK_OPTION_FAIL_MASK (0x200U) +#define FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT (9U) +/*! OPTION_FAIL - Option Check Fail + * 0b0..Option check passes for read command or command is not a read command + * 0b1..Option check fails for read command + */ +#define FMUTEST_CMD_CHECK_OPTION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_OPTION_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK (0x400U) +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT (10U) +/*! ILLEGAL_CMD - Illegal Command + * 0b0..Command is legal + * 0b1..Command is illegal + */ +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK) +/*! @} */ + +/*! @name BSEL - FMU Block Select Register */ +/*! @{ */ + +#define FMUTEST_BSEL_SBSEL_MASK (0x3U) +#define FMUTEST_BSEL_SBSEL_SHIFT (0U) +/*! SBSEL - Slave Block Select */ +#define FMUTEST_BSEL_SBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_SBSEL_SHIFT)) & FMUTEST_BSEL_SBSEL_MASK) + +#define FMUTEST_BSEL_MBSEL_MASK (0x300U) +#define FMUTEST_BSEL_MBSEL_SHIFT (8U) +/*! MBSEL - Master Block Select */ +#define FMUTEST_BSEL_MBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_MBSEL_SHIFT)) & FMUTEST_BSEL_MBSEL_MASK) +/*! @} */ + +/*! @name MSIZE - FMU Memory Size Register */ +/*! @{ */ + +#define FMUTEST_MSIZE_MAXADDR0_MASK (0xFFU) +#define FMUTEST_MSIZE_MAXADDR0_SHIFT (0U) +/*! MAXADDR0 - Size of Flash Block 0 */ +#define FMUTEST_MSIZE_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR0_SHIFT)) & FMUTEST_MSIZE_MAXADDR0_MASK) + +#define FMUTEST_MSIZE_MAXADDR1_MASK (0xFF00U) +#define FMUTEST_MSIZE_MAXADDR1_SHIFT (8U) +/*! MAXADDR1 - Size of Flash Block 1 */ +#define FMUTEST_MSIZE_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR1_SHIFT)) & FMUTEST_MSIZE_MAXADDR1_MASK) +/*! @} */ + +/*! @name FLASH_RD_ADD - Flash Read Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT (0U) +/*! FLASH_RD_ADD - Flash Read Address */ +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT)) & FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK) +/*! @} */ + +/*! @name FLASH_STOP_ADD - Flash Stop Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT (0U) +/*! FLASH_STOP_ADD - Flash Stop Address */ +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT)) & FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK) +/*! @} */ + +/*! @name FLASH_RD_CTRL - Flash Read Control Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK (0x1U) +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT (0U) +/*! FLASH_RD - Flash Read Enable + * 0b0..Manual flash read not enabled.(default) + * 0b1..Manual flash read enabled + */ +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK (0x2U) +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT (1U) +/*! WIDE_LOAD - Wide Load Enable + * 0b0..Wide load mode disabled (default) + * 0b1..Wide load mode enabled + */ +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK (0x4U) +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT (2U) +/*! SINGLE_RD - Single Flash Read + * 0b0..Normal UINT operation + * 0b1..UINT configured for single cycle reads + */ +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK) +/*! @} */ + +/*! @name MM_ADDR - Memory Map Address Register */ +/*! @{ */ + +#define FMUTEST_MM_ADDR_MM_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_ADDR_MM_ADDR_SHIFT (0U) +/*! MM_ADDR - Memory Map Address */ +#define FMUTEST_MM_ADDR_MM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_ADDR_MM_ADDR_SHIFT)) & FMUTEST_MM_ADDR_MM_ADDR_MASK) +/*! @} */ + +/*! @name MM_WDATA - Memory Map Write Data Register */ +/*! @{ */ + +#define FMUTEST_MM_WDATA_MM_WDATA_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_WDATA_MM_WDATA_SHIFT (0U) +/*! MM_WDATA - Memory Map Write Data */ +#define FMUTEST_MM_WDATA_MM_WDATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_WDATA_MM_WDATA_SHIFT)) & FMUTEST_MM_WDATA_MM_WDATA_MASK) +/*! @} */ + +/*! @name MM_CTL - Memory Map Control Register */ +/*! @{ */ + +#define FMUTEST_MM_CTL_MM_SEL_MASK (0x1U) +#define FMUTEST_MM_CTL_MM_SEL_SHIFT (0U) +/*! MM_SEL - Register Access Enable */ +#define FMUTEST_MM_CTL_MM_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_SEL_SHIFT)) & FMUTEST_MM_CTL_MM_SEL_MASK) + +#define FMUTEST_MM_CTL_MM_RD_MASK (0x2U) +#define FMUTEST_MM_CTL_MM_RD_SHIFT (1U) +/*! MM_RD - Register R/W Control + * 0b0..Write to register + * 0b1..Read register + */ +#define FMUTEST_MM_CTL_MM_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_RD_SHIFT)) & FMUTEST_MM_CTL_MM_RD_MASK) + +#define FMUTEST_MM_CTL_BIST_ON_MASK (0x4U) +#define FMUTEST_MM_CTL_BIST_ON_SHIFT (2U) +/*! BIST_ON - BIST on + * 0b0..BIST enable not forced by user interface + * 0b1..BIST enable control by user interface + */ +#define FMUTEST_MM_CTL_BIST_ON(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_BIST_ON_SHIFT)) & FMUTEST_MM_CTL_BIST_ON_MASK) + +#define FMUTEST_MM_CTL_FORCE_SW_CLK_MASK (0x8U) +#define FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT (3U) +/*! FORCE_SW_CLK - Force Switch Clock + * 0b0..Switch clock not forced on (gated normally) + * 0b1..Switch clock forced on + */ +#define FMUTEST_MM_CTL_FORCE_SW_CLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT)) & FMUTEST_MM_CTL_FORCE_SW_CLK_MASK) +/*! @} */ + +/*! @name UINT_CTL - User Interface Control Register */ +/*! @{ */ + +#define FMUTEST_UINT_CTL_SET_FAIL_MASK (0x1U) +#define FMUTEST_UINT_CTL_SET_FAIL_SHIFT (0U) +/*! SET_FAIL - Set Fail On Exit + * 0b0..FAIL flag should not be set on command exit (no failure detected) + * 0b1..FAIL flag should be set on command exit + */ +#define FMUTEST_UINT_CTL_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_SET_FAIL_SHIFT)) & FMUTEST_UINT_CTL_SET_FAIL_MASK) + +#define FMUTEST_UINT_CTL_DBERR_MASK (0x2U) +#define FMUTEST_UINT_CTL_DBERR_SHIFT (1U) +/*! DBERR - Double-Bit ECC Fault Detect + * 0b0..No double-bit fault detected during UINT-driven read sequence + * 0b1..Double-bit fault detected during UINT-driven read sequence + */ +#define FMUTEST_UINT_CTL_DBERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_DBERR_SHIFT)) & FMUTEST_UINT_CTL_DBERR_MASK) +/*! @} */ + +/*! @name RD_DATA0 - Read Data 0 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA0_RD_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA0_RD_DATA0_SHIFT (0U) +/*! RD_DATA0 - Read Data 0 */ +#define FMUTEST_RD_DATA0_RD_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA0_RD_DATA0_SHIFT)) & FMUTEST_RD_DATA0_RD_DATA0_MASK) +/*! @} */ + +/*! @name RD_DATA1 - Read Data 1 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA1_RD_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA1_RD_DATA1_SHIFT (0U) +/*! RD_DATA1 - Read Data 1 */ +#define FMUTEST_RD_DATA1_RD_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA1_RD_DATA1_SHIFT)) & FMUTEST_RD_DATA1_RD_DATA1_MASK) +/*! @} */ + +/*! @name RD_DATA2 - Read Data 2 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA2_RD_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA2_RD_DATA2_SHIFT (0U) +/*! RD_DATA2 - Read Data 2 */ +#define FMUTEST_RD_DATA2_RD_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA2_RD_DATA2_SHIFT)) & FMUTEST_RD_DATA2_RD_DATA2_MASK) +/*! @} */ + +/*! @name RD_DATA3 - Read Data 3 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA3_RD_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA3_RD_DATA3_SHIFT (0U) +/*! RD_DATA3 - Read Data 3 */ +#define FMUTEST_RD_DATA3_RD_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA3_RD_DATA3_SHIFT)) & FMUTEST_RD_DATA3_RD_DATA3_MASK) +/*! @} */ + +/*! @name PARITY - Parity Register */ +/*! @{ */ + +#define FMUTEST_PARITY_PARITY_MASK (0x1FFU) +#define FMUTEST_PARITY_PARITY_SHIFT (0U) +/*! PARITY - Read data [136:128] */ +#define FMUTEST_PARITY_PARITY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PARITY_PARITY_SHIFT)) & FMUTEST_PARITY_PARITY_MASK) +/*! @} */ + +/*! @name RD_PATH_CTRL_STATUS - Read Path Control and Status Register */ +/*! @{ */ + +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK (0xFFU) +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT (0U) +/*! RD_CAPT - Read Capture Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK (0xFF00U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT (8U) +/*! SE_SIZE - SE Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK (0x10000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT (16U) +/*! ECC_ENABLEB - ECC Decoder Control + * 0b0..ECC decoder enabled (default) + * 0b1..ECC decoder disabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK (0x20000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT (17U) +/*! MISR_EN - MISR Enable + * 0b0..MISR option disabled (default) + * 0b1..MISR option enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK (0x40000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT (18U) +/*! CPY_PAR_EN - Copy Parity Enable + * 0b0..Copy parity disabled + * 0b1..Copy parity enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK (0x80000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT (19U) +/*! BIST_MUX_TO_SMW - BIST Mux to SMW + * 0b0..BIST drives fields + * 0b1..SMW registers drive fields + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK (0xF00000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT (20U) +/*! AD_SET - Multi-Cycle Address Setup Time */ +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK (0x1000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT (24U) +/*! WR_PATH_EN - Write Path Enable + * 0b0..Writes to BIST setting registers driven by MM_WDATA + * 0b1..Writes to BIST setting registers driven by SMW_DIN + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK (0x2000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT (25U) +/*! WR_PATH_ECC_EN - Write Path ECC Enable + * 0b0..ECC encoding disabled + * 0b1..ECC encoding enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK (0x4000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT (26U) +/*! DBERR_REG - Double-Bit Error + * 0b0..Double-bit fault not detected + * 0b1..Double-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK (0x8000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT (27U) +/*! SBERR_REG - Single-Bit Error + * 0b0..Single-bit fault not detected + * 0b1..Single-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK (0x10000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT (28U) +/*! CPY_PHRASE_EN - Copy Phrase Enable + * 0b0..Copy Flash read data disabled + * 0b1..Copy Flash read data enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK (0x20000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT (29U) +/*! SMW_ARRAY1_SMW0_SEL - SMW_ARRAY1_SMW0_SEL + * 0b0..Select block 0 + * 0b1..Select block 1 + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK (0x40000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT (30U) +/*! BIST_ECC_EN - BIST ECC Enable + * 0b0..ECC correction disabled + * 0b1..ECC correction enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK (0x80000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT (31U) +/*! LAST_READ - Last Read + * 0b0..Latest read not last in multi-address operation + * 0b1..Latest read last in multi-address operation + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK) +/*! @} */ + +/*! @name SMW_DIN0 - SMW DIN 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN0_SMW_DIN0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT (0U) +/*! SMW_DIN0 - SMW DIN 0 */ +#define FMUTEST_SMW_DIN0_SMW_DIN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT)) & FMUTEST_SMW_DIN0_SMW_DIN0_MASK) +/*! @} */ + +/*! @name SMW_DIN1 - SMW DIN 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN1_SMW_DIN1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT (0U) +/*! SMW_DIN1 - SMW DIN 1 */ +#define FMUTEST_SMW_DIN1_SMW_DIN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT)) & FMUTEST_SMW_DIN1_SMW_DIN1_MASK) +/*! @} */ + +/*! @name SMW_DIN2 - SMW DIN 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN2_SMW_DIN2_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT (0U) +/*! SMW_DIN2 - SMW DIN 2 */ +#define FMUTEST_SMW_DIN2_SMW_DIN2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT)) & FMUTEST_SMW_DIN2_SMW_DIN2_MASK) +/*! @} */ + +/*! @name SMW_DIN3 - SMW DIN 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN3_SMW_DIN3_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT (0U) +/*! SMW_DIN3 - SMW DIN 3 */ +#define FMUTEST_SMW_DIN3_SMW_DIN3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT)) & FMUTEST_SMW_DIN3_SMW_DIN3_MASK) +/*! @} */ + +/*! @name SMW_ADDR - SMW Address Register */ +/*! @{ */ + +#define FMUTEST_SMW_ADDR_SMW_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT (0U) +/*! SMW_ADDR - SMW Address */ +#define FMUTEST_SMW_ADDR_SMW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT)) & FMUTEST_SMW_ADDR_SMW_ADDR_MASK) +/*! @} */ + +/*! @name SMW_CMD_WAIT - SMW Command and Wait Register */ +/*! @{ */ + +#define FMUTEST_SMW_CMD_WAIT_CMD_MASK (0x7U) +#define FMUTEST_SMW_CMD_WAIT_CMD_SHIFT (0U) +/*! CMD - SMW Command + * 0b000..IDLE + * 0b001..ABORT + * 0b010..SME2 to one-shot mass erase + * 0b011..SME3 to sector erase on selected array + * 0b100..SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit + * 0b101..Reserved for SME4 (multi-sector erase) + * 0b110..SMP2 to program phrase or page on selected array to repair cells of weak program after power loss + * 0b111..Reserved + */ +#define FMUTEST_SMW_CMD_WAIT_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_CMD_SHIFT)) & FMUTEST_SMW_CMD_WAIT_CMD_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK (0x8U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT (3U) +/*! WAIT_EN - SMW Wait Enable + * 0b0..Wait feature disabled + * 0b1..Wait feature enabled + */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK (0x10U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT (4U) +/*! WAIT_AUTO_SET - SMW Wait Auto Set */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK) +/*! @} */ + +/*! @name SMW_STATUS - SMW Status Register */ +/*! @{ */ + +#define FMUTEST_SMW_STATUS_SMW_ERR_MASK (0x1U) +#define FMUTEST_SMW_STATUS_SMW_ERR_SHIFT (0U) +/*! SMW_ERR - SMW Error + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_SMW_STATUS_SMW_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_ERR_SHIFT)) & FMUTEST_SMW_STATUS_SMW_ERR_MASK) + +#define FMUTEST_SMW_STATUS_SMW_BUSY_MASK (0x2U) +#define FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT (1U) +/*! SMW_BUSY - SMW Busy + * 0b0..SMW command not active + * 0b1..SMW command is active + */ +#define FMUTEST_SMW_STATUS_SMW_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_SMW_BUSY_MASK) + +#define FMUTEST_SMW_STATUS_BIST_BUSY_MASK (0x4U) +#define FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT (2U) +/*! BIST_BUSY - BIST Busy + * 0b0..BIST Command not active + * 0b1..BIST Command is active + */ +#define FMUTEST_SMW_STATUS_BIST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_BIST_BUSY_MASK) +/*! @} */ + +/*! @name SOCTRIM0_0 - SoC Trim Phrase 0 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_0_TRIM0_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT (0U) +/*! TRIM0_0 - TRIM0_0 */ +#define FMUTEST_SOCTRIM0_0_TRIM0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT)) & FMUTEST_SOCTRIM0_0_TRIM0_0_MASK) +/*! @} */ + +/*! @name SOCTRIM0_1 - SoC Trim Phrase 0 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_1_TRIM0_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT (0U) +/*! TRIM0_1 - TRIM0_1 */ +#define FMUTEST_SOCTRIM0_1_TRIM0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT)) & FMUTEST_SOCTRIM0_1_TRIM0_1_MASK) +/*! @} */ + +/*! @name SOCTRIM0_2 - SoC Trim Phrase 0 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_2_TRIM0_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT (0U) +/*! TRIM0_2 - TRIM0_2 */ +#define FMUTEST_SOCTRIM0_2_TRIM0_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT)) & FMUTEST_SOCTRIM0_2_TRIM0_2_MASK) +/*! @} */ + +/*! @name SOCTRIM0_3 - SoC Trim Phrase 0 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_3_TRIM0_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT (0U) +/*! TRIM0_3 - TRIM0_3 */ +#define FMUTEST_SOCTRIM0_3_TRIM0_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT)) & FMUTEST_SOCTRIM0_3_TRIM0_3_MASK) +/*! @} */ + +/*! @name SOCTRIM1_0 - SoC Trim Phrase 1 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_0_TRIM1_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT (0U) +/*! TRIM1_0 - TRIM1_0 */ +#define FMUTEST_SOCTRIM1_0_TRIM1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT)) & FMUTEST_SOCTRIM1_0_TRIM1_0_MASK) +/*! @} */ + +/*! @name SOCTRIM1_1 - SoC Trim Phrase 1 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_1_TRIM1_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT (0U) +/*! TRIM1_1 - TRIM1_1 */ +#define FMUTEST_SOCTRIM1_1_TRIM1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT)) & FMUTEST_SOCTRIM1_1_TRIM1_1_MASK) +/*! @} */ + +/*! @name SOCTRIM1_2 - SoC Trim Phrase 1 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_2_TRIM1_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT (0U) +/*! TRIM1_2 - TRIM1_2 */ +#define FMUTEST_SOCTRIM1_2_TRIM1_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT)) & FMUTEST_SOCTRIM1_2_TRIM1_2_MASK) +/*! @} */ + +/*! @name SOCTRIM1_3 - SoC Trim Phrase 1 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_3_TRIM1_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT (0U) +/*! TRIM1_3 - TRIM1_3 */ +#define FMUTEST_SOCTRIM1_3_TRIM1_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT)) & FMUTEST_SOCTRIM1_3_TRIM1_3_MASK) +/*! @} */ + +/*! @name SOCTRIM2_0 - SoC Trim Phrase 2 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_0_TRIM2_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT (0U) +/*! TRIM2_0 - TRIM2_0 */ +#define FMUTEST_SOCTRIM2_0_TRIM2_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT)) & FMUTEST_SOCTRIM2_0_TRIM2_0_MASK) +/*! @} */ + +/*! @name SOCTRIM2_1 - SoC Trim Phrase 2 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_1_TRIM2_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT (0U) +/*! TRIM2_1 - TRIM2_1 */ +#define FMUTEST_SOCTRIM2_1_TRIM2_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT)) & FMUTEST_SOCTRIM2_1_TRIM2_1_MASK) +/*! @} */ + +/*! @name SOCTRIM2_2 - SoC Trim Phrase 2 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_2_TRIM2_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT (0U) +/*! TRIM2_2 - TRIM2_2 */ +#define FMUTEST_SOCTRIM2_2_TRIM2_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT)) & FMUTEST_SOCTRIM2_2_TRIM2_2_MASK) +/*! @} */ + +/*! @name SOCTRIM2_3 - SoC Trim Phrase 2 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_3_TRIM2_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT (0U) +/*! TRIM2_3 - TRIM2_3 */ +#define FMUTEST_SOCTRIM2_3_TRIM2_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT)) & FMUTEST_SOCTRIM2_3_TRIM2_3_MASK) +/*! @} */ + +/*! @name SOCTRIM3_0 - SoC Trim Phrase 3 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_0_TRIM3_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT (0U) +/*! TRIM3_0 - TRIM3_0 */ +#define FMUTEST_SOCTRIM3_0_TRIM3_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT)) & FMUTEST_SOCTRIM3_0_TRIM3_0_MASK) +/*! @} */ + +/*! @name SOCTRIM3_1 - SoC Trim Phrase 3 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_1_TRIM3_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT (0U) +/*! TRIM3_1 - TRIM3_1 */ +#define FMUTEST_SOCTRIM3_1_TRIM3_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT)) & FMUTEST_SOCTRIM3_1_TRIM3_1_MASK) +/*! @} */ + +/*! @name SOCTRIM3_2 - SoC Trim Phrase 3 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_2_TRIM3_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT (0U) +/*! TRIM3_2 - TRIM3_2 */ +#define FMUTEST_SOCTRIM3_2_TRIM3_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT)) & FMUTEST_SOCTRIM3_2_TRIM3_2_MASK) +/*! @} */ + +/*! @name SOCTRIM3_3 - SoC Trim Phrase 3 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_3_TRIM3_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT (0U) +/*! TRIM3_3 - TRIM3_3 */ +#define FMUTEST_SOCTRIM3_3_TRIM3_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT)) & FMUTEST_SOCTRIM3_3_TRIM3_3_MASK) +/*! @} */ + +/*! @name SOCTRIM4_0 - SoC Trim Phrase 4 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_0_TRIM4_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT (0U) +/*! TRIM4_0 - TRIM4_0 */ +#define FMUTEST_SOCTRIM4_0_TRIM4_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT)) & FMUTEST_SOCTRIM4_0_TRIM4_0_MASK) +/*! @} */ + +/*! @name SOCTRIM4_1 - SoC Trim Phrase 4 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_1_TRIM4_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT (0U) +/*! TRIM4_1 - TRIM4_1 */ +#define FMUTEST_SOCTRIM4_1_TRIM4_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT)) & FMUTEST_SOCTRIM4_1_TRIM4_1_MASK) +/*! @} */ + +/*! @name SOCTRIM4_2 - SoC Trim Phrase 4 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_2_TRIM4_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT (0U) +/*! TRIM4_2 - TRIM4_2 */ +#define FMUTEST_SOCTRIM4_2_TRIM4_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT)) & FMUTEST_SOCTRIM4_2_TRIM4_2_MASK) +/*! @} */ + +/*! @name SOCTRIM4_3 - SoC Trim Phrase 4 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_3_TRIM4_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT (0U) +/*! TRIM4_3 - TRIM4_3 */ +#define FMUTEST_SOCTRIM4_3_TRIM4_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT)) & FMUTEST_SOCTRIM4_3_TRIM4_3_MASK) +/*! @} */ + +/*! @name SOCTRIM5_0 - SoC Trim Phrase 5 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_0_TRIM5_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT (0U) +/*! TRIM5_0 - TRIM5_0 */ +#define FMUTEST_SOCTRIM5_0_TRIM5_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT)) & FMUTEST_SOCTRIM5_0_TRIM5_0_MASK) +/*! @} */ + +/*! @name SOCTRIM5_1 - SoC Trim Phrase 5 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_1_TRIM5_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT (0U) +/*! TRIM5_1 - TRIM5_1 */ +#define FMUTEST_SOCTRIM5_1_TRIM5_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT)) & FMUTEST_SOCTRIM5_1_TRIM5_1_MASK) +/*! @} */ + +/*! @name SOCTRIM5_2 - SoC Trim Phrase 5 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_2_TRIM5_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT (0U) +/*! TRIM5_2 - TRIM5_2 */ +#define FMUTEST_SOCTRIM5_2_TRIM5_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT)) & FMUTEST_SOCTRIM5_2_TRIM5_2_MASK) +/*! @} */ + +/*! @name SOCTRIM5_3 - SoC Trim Phrase 5 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_3_TRIM5_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT (0U) +/*! TRIM5_3 - TRIM5_3 */ +#define FMUTEST_SOCTRIM5_3_TRIM5_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT)) & FMUTEST_SOCTRIM5_3_TRIM5_3_MASK) +/*! @} */ + +/*! @name SOCTRIM6_0 - SoC Trim Phrase 6 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_0_TRIM6_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT (0U) +/*! TRIM6_0 - TRIM6_0 */ +#define FMUTEST_SOCTRIM6_0_TRIM6_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT)) & FMUTEST_SOCTRIM6_0_TRIM6_0_MASK) +/*! @} */ + +/*! @name SOCTRIM6_1 - SoC Trim Phrase 6 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_1_TRIM6_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT (0U) +/*! TRIM6_1 - TRIM6_1 */ +#define FMUTEST_SOCTRIM6_1_TRIM6_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT)) & FMUTEST_SOCTRIM6_1_TRIM6_1_MASK) +/*! @} */ + +/*! @name SOCTRIM6_2 - SoC Trim Phrase 6 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_2_TRIM6_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT (0U) +/*! TRIM6_2 - TRIM6_2 */ +#define FMUTEST_SOCTRIM6_2_TRIM6_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT)) & FMUTEST_SOCTRIM6_2_TRIM6_2_MASK) +/*! @} */ + +/*! @name SOCTRIM6_3 - SoC Trim Phrase 6 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_3_TRIM6_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT (0U) +/*! TRIM6_3 - TRIM6_3 */ +#define FMUTEST_SOCTRIM6_3_TRIM6_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT)) & FMUTEST_SOCTRIM6_3_TRIM6_3_MASK) +/*! @} */ + +/*! @name SOCTRIM7_0 - SoC Trim Phrase 7 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_0_TRIM7_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT (0U) +/*! TRIM7_0 - TRIM7_0 */ +#define FMUTEST_SOCTRIM7_0_TRIM7_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT)) & FMUTEST_SOCTRIM7_0_TRIM7_0_MASK) +/*! @} */ + +/*! @name SOCTRIM7_1 - SoC Trim Phrase 7 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_1_TRIM7_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT (0U) +/*! TRIM7_1 - TRIM7_1 */ +#define FMUTEST_SOCTRIM7_1_TRIM7_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT)) & FMUTEST_SOCTRIM7_1_TRIM7_1_MASK) +/*! @} */ + +/*! @name SOCTRIM7_2 - SoC Trim Phrase 7 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_2_TRIM7_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT (0U) +/*! TRIM7_2 - TRIM7_2 */ +#define FMUTEST_SOCTRIM7_2_TRIM7_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT)) & FMUTEST_SOCTRIM7_2_TRIM7_2_MASK) +/*! @} */ + +/*! @name SOCTRIM7_3 - SoC Trim Phrase 7 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_3_TRIM7_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT (0U) +/*! TRIM7_3 - TRIM7_3 */ +#define FMUTEST_SOCTRIM7_3_TRIM7_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT)) & FMUTEST_SOCTRIM7_3_TRIM7_3_MASK) +/*! @} */ + +/*! @name R_IP_CONFIG - BIST Configuration Register */ +/*! @{ */ + +#define FMUTEST_R_IP_CONFIG_IPSEL0_MASK (0x3U) +#define FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT (0U) +/*! IPSEL0 - Block 0 Select Control + * 0b00..Unselect block 0 + * 0b01..not used, reserved + * 0b10..Enable block 0 test, repair off (default) + * 0b11..Enable block 0 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL0_MASK) + +#define FMUTEST_R_IP_CONFIG_IPSEL1_MASK (0xCU) +#define FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT (2U) +/*! IPSEL1 - Block 1 Select Control + * 0b00..Unselect block 1 + * 0b01..not used, reserved + * 0b10..Enable block 1 test, repair off (default) + * 0b11..Enable block 1 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL1_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK (0xFF0U) +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT (4U) +/*! BIST_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK) + +#define FMUTEST_R_IP_CONFIG_CDIVS_MASK (0x7000U) +#define FMUTEST_R_IP_CONFIG_CDIVS_SHIFT (12U) +/*! CDIVS - Number of clock cycles to generate short pulse */ +#define FMUTEST_R_IP_CONFIG_CDIVS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_CDIVS_SHIFT)) & FMUTEST_R_IP_CONFIG_CDIVS_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK (0xF8000U) +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT (15U) +/*! BIST_TVFY - Timer adjust for verify */ +#define FMUTEST_R_IP_CONFIG_BIST_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK) + +#define FMUTEST_R_IP_CONFIG_TSTCTL_MASK (0x300000U) +#define FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT (20U) +/*! TSTCTL - BIST self-test control + * 0b00..Default, disable both BIST self-test and MISR + * 0b01..Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR. + * 0b10..Enable MISR + * 0b11..Enable both BIST self-test mode and MISR + */ +#define FMUTEST_R_IP_CONFIG_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_TSTCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_DBGCTL_MASK (0x400000U) +#define FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT (22U) +/*! DBGCTL - Debug feature control + * 0b0..Default + * 0b1..Enable debug feature to collect failure address and data. + */ +#define FMUTEST_R_IP_CONFIG_DBGCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_DBGCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK (0x800000U) +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT (23U) +/*! BIST_CLK_SEL - BIST Clock Select */ +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK) + +#define FMUTEST_R_IP_CONFIG_SMWTST_MASK (0x3000000U) +#define FMUTEST_R_IP_CONFIG_SMWTST_SHIFT (24U) +/*! SMWTST - SMWR DOUT Function Control + * 0b00..Default + * 0b01..Enable SMWR self-test mode, DOUT from macro will be forced to all 0 + * 0b10..Enable SMWR self-test mode, DOUT from macro will be forced to all 1 + * 0b11..Reserved (unused) + */ +#define FMUTEST_R_IP_CONFIG_SMWTST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_SMWTST_SHIFT)) & FMUTEST_R_IP_CONFIG_SMWTST_MASK) + +#define FMUTEST_R_IP_CONFIG_ECCEN_MASK (0x4000000U) +#define FMUTEST_R_IP_CONFIG_ECCEN_SHIFT (26U) +/*! ECCEN - BIST ECC Control + * 0b0..Default mode (no ECC encode or decode) + * 0b1..Enable ECC encode/decode + */ +#define FMUTEST_R_IP_CONFIG_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_ECCEN_SHIFT)) & FMUTEST_R_IP_CONFIG_ECCEN_MASK) +/*! @} */ + +/*! @name R_TESTCODE - BIST Test Code Register */ +/*! @{ */ + +#define FMUTEST_R_TESTCODE_TESTCODE_MASK (0x3FU) +#define FMUTEST_R_TESTCODE_TESTCODE_SHIFT (0U) +/*! TESTCODE - Used to store test code information before running TMR-RST/TMRSET BIST command */ +#define FMUTEST_R_TESTCODE_TESTCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TESTCODE_TESTCODE_SHIFT)) & FMUTEST_R_TESTCODE_TESTCODE_MASK) +/*! @} */ + +/*! @name R_DFT_CTRL - BIST DFT Control Register */ +/*! @{ */ + +#define FMUTEST_R_DFT_CTRL_DFT_XADR_MASK (0xFU) +#define FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT (0U) +/*! DFT_XADR - DFT XADR Pattern + * 0b0000..XADR fixed, no change at all + * 0b0001..XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of + * row. For PROG operation, XADR increases by 1 after NVSTR falls. + * 0b0010..XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern. + * 0b0011..XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls. + * 0b0100..XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0101..XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word + * of a row. For PROG operation, XADR is increased by 2 when NVSTR falls. + * 0b0110..XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0111..XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle. + * 0b1000..XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0. + * 0b1001..XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle. + */ +#define FMUTEST_R_DFT_CTRL_DFT_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_XADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_YADR_MASK (0xF0U) +#define FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT (4U) +/*! DFT_YADR - DFT YADR Pattern + * 0b0000..YADR fixed, no change at all + * 0b0001..YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern. + * 0b0010..YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern. + * 0b0011..YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG + * operations, YADR increased by 1 after YE falls. + * 0b0100..YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern. + * 0b0101..YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls. + * 0b0110..YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls. + * 0b0111..YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row. + * 0b1000..YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle. + * 0b1001..YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0. + */ +#define FMUTEST_R_DFT_CTRL_DFT_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_YADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_MASK (0xF00U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT (8U) +/*! DFT_DATA - DFT Data Pattern + * 0b0000..CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle. + * 0b0001..ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle. + * 0b0010..Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern. + * 0b0011..Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to + * R_ADR_CTRL[GRPSEL] for modules with multiple groups. + * 0b0100..Random data pattern which will be generated based on the initial seed set in R_DATA; for READ + * operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected + * groups. + * 0b0101..DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If + * more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched. + * 0b0110..R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA + * when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals + * R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. + * 0b0111..SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data + * pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern. + * 0b1000..REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 + * and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared + * against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only + * one flash block can be selected. + * 0b1001..REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1. + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_MASK) + +#define FMUTEST_R_DFT_CTRL_CMP_MASK_MASK (0x3000U) +#define FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT (12U) +/*! CMP_MASK - Data Compare Mask + * 0b00..Expected data is compared to DOUT + * 0b01..Expected data (only 0s are considered) are compared to DOUT + * 0b10..Expected data (only 1s are considered) are compared to DOUT + */ +#define FMUTEST_R_DFT_CTRL_CMP_MASK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT)) & FMUTEST_R_DFT_CTRL_CMP_MASK_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK (0x4000U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT (14U) +/*! DFT_DATA_SRC - DFT Data Source + * 0b0..{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + * 0b1..{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK) +/*! @} */ + +/*! @name R_ADR_CTRL - BIST Address Control Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_CTRL_GRPSEL_MASK (0xFU) +#define FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT (0U) +/*! GRPSEL - Data Group Select + * 0b0000..Select no data + * 0b0001..Select data slice [34:0] + * 0b0010..Select data slice [69:35] + * 0b0100..Select data slice [104:70] + * 0b1000..Select data slice [136:105] + * 0b1111..Select data [136:0] + */ +#define FMUTEST_R_ADR_CTRL_GRPSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT)) & FMUTEST_R_ADR_CTRL_GRPSEL_MASK) + +#define FMUTEST_R_ADR_CTRL_XADR_MASK (0xFFF0U) +#define FMUTEST_R_ADR_CTRL_XADR_SHIFT (4U) +/*! XADR - BIST XADR */ +#define FMUTEST_R_ADR_CTRL_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_XADR_SHIFT)) & FMUTEST_R_ADR_CTRL_XADR_MASK) + +#define FMUTEST_R_ADR_CTRL_YADR_MASK (0x1F0000U) +#define FMUTEST_R_ADR_CTRL_YADR_SHIFT (16U) +/*! YADR - BIST YADR */ +#define FMUTEST_R_ADR_CTRL_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_YADR_SHIFT)) & FMUTEST_R_ADR_CTRL_YADR_MASK) + +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK (0xE00000U) +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT (21U) +/*! PROG_ATTR - Program Attribute + * 0b000..One YE pulse will program one data slice group + * 0b001..One YE pulse will program two data slice groups + * 0b010..One YE pulse will program three data slice groups (reserved) + * 0b011..One YE pulse will program four data slice groups + * 0b100..One YE pulse will program five data slice groups (reserved) + * 0b101..One YE pulse will program six data slice groups (reserved) + * 0b110..One YE pulse will program seven data slice groups (reserved) + * 0b111..One YE pulse will program eight data slice groups (reserved) + */ +#define FMUTEST_R_ADR_CTRL_PROG_ATTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT)) & FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0 - BIST Data Control 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL0_DATA0_SHIFT (0U) +/*! DATA0 - BIST Data 0 Low */ +#define FMUTEST_R_DATA_CTRL0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_DATA0_SHIFT)) & FMUTEST_R_DATA_CTRL0_DATA0_MASK) +/*! @} */ + +/*! @name R_PIN_CTRL - BIST Pin Control Register */ +/*! @{ */ + +#define FMUTEST_R_PIN_CTRL_MAS1_MASK (0x1U) +#define FMUTEST_R_PIN_CTRL_MAS1_SHIFT (0U) +/*! MAS1 - Mass Erase */ +#define FMUTEST_R_PIN_CTRL_MAS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_MAS1_SHIFT)) & FMUTEST_R_PIN_CTRL_MAS1_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN_MASK (0x2U) +#define FMUTEST_R_PIN_CTRL_IFREN_SHIFT (1U) +/*! IFREN - IFR Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN1_MASK (0x4U) +#define FMUTEST_R_PIN_CTRL_IFREN1_SHIFT (2U) +/*! IFREN1 - IFR1 Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN1_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN1_MASK) + +#define FMUTEST_R_PIN_CTRL_REDEN_MASK (0x8U) +#define FMUTEST_R_PIN_CTRL_REDEN_SHIFT (3U) +/*! REDEN - Redundancy Block Enable */ +#define FMUTEST_R_PIN_CTRL_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_REDEN_SHIFT)) & FMUTEST_R_PIN_CTRL_REDEN_MASK) + +#define FMUTEST_R_PIN_CTRL_LVE_MASK (0x10U) +#define FMUTEST_R_PIN_CTRL_LVE_SHIFT (4U) +/*! LVE - Low Voltage Enable */ +#define FMUTEST_R_PIN_CTRL_LVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_LVE_SHIFT)) & FMUTEST_R_PIN_CTRL_LVE_MASK) + +#define FMUTEST_R_PIN_CTRL_PV_MASK (0x20U) +#define FMUTEST_R_PIN_CTRL_PV_SHIFT (5U) +/*! PV - Program Verify Enable */ +#define FMUTEST_R_PIN_CTRL_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PV_SHIFT)) & FMUTEST_R_PIN_CTRL_PV_MASK) + +#define FMUTEST_R_PIN_CTRL_EV_MASK (0x40U) +#define FMUTEST_R_PIN_CTRL_EV_SHIFT (6U) +/*! EV - Erase Verify Enable */ +#define FMUTEST_R_PIN_CTRL_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_EV_SHIFT)) & FMUTEST_R_PIN_CTRL_EV_MASK) + +#define FMUTEST_R_PIN_CTRL_WIPGM_MASK (0x180U) +#define FMUTEST_R_PIN_CTRL_WIPGM_SHIFT (7U) +/*! WIPGM - Program Current */ +#define FMUTEST_R_PIN_CTRL_WIPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WIPGM_SHIFT)) & FMUTEST_R_PIN_CTRL_WIPGM_MASK) + +#define FMUTEST_R_PIN_CTRL_WHV_MASK (0x1E00U) +#define FMUTEST_R_PIN_CTRL_WHV_SHIFT (9U) +/*! WHV - High Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WHV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WHV_SHIFT)) & FMUTEST_R_PIN_CTRL_WHV_MASK) + +#define FMUTEST_R_PIN_CTRL_WMV_MASK (0xE000U) +#define FMUTEST_R_PIN_CTRL_WMV_SHIFT (13U) +/*! WMV - Medium Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WMV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WMV_SHIFT)) & FMUTEST_R_PIN_CTRL_WMV_MASK) + +#define FMUTEST_R_PIN_CTRL_XE_MASK (0x10000U) +#define FMUTEST_R_PIN_CTRL_XE_SHIFT (16U) +/*! XE - X Address Enable */ +#define FMUTEST_R_PIN_CTRL_XE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_XE_SHIFT)) & FMUTEST_R_PIN_CTRL_XE_MASK) + +#define FMUTEST_R_PIN_CTRL_YE_MASK (0x20000U) +#define FMUTEST_R_PIN_CTRL_YE_SHIFT (17U) +/*! YE - Y Address Enable */ +#define FMUTEST_R_PIN_CTRL_YE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_YE_SHIFT)) & FMUTEST_R_PIN_CTRL_YE_MASK) + +#define FMUTEST_R_PIN_CTRL_SE_MASK (0x40000U) +#define FMUTEST_R_PIN_CTRL_SE_SHIFT (18U) +/*! SE - Sense Amp Enable */ +#define FMUTEST_R_PIN_CTRL_SE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SE_SHIFT)) & FMUTEST_R_PIN_CTRL_SE_MASK) + +#define FMUTEST_R_PIN_CTRL_ERASE_MASK (0x80000U) +#define FMUTEST_R_PIN_CTRL_ERASE_SHIFT (19U) +/*! ERASE - Erase Mode */ +#define FMUTEST_R_PIN_CTRL_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_ERASE_SHIFT)) & FMUTEST_R_PIN_CTRL_ERASE_MASK) + +#define FMUTEST_R_PIN_CTRL_PROG_MASK (0x100000U) +#define FMUTEST_R_PIN_CTRL_PROG_SHIFT (20U) +/*! PROG - Program Mode */ +#define FMUTEST_R_PIN_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PROG_SHIFT)) & FMUTEST_R_PIN_CTRL_PROG_MASK) + +#define FMUTEST_R_PIN_CTRL_NVSTR_MASK (0x200000U) +#define FMUTEST_R_PIN_CTRL_NVSTR_SHIFT (21U) +/*! NVSTR - NVM Store */ +#define FMUTEST_R_PIN_CTRL_NVSTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_NVSTR_SHIFT)) & FMUTEST_R_PIN_CTRL_NVSTR_MASK) + +#define FMUTEST_R_PIN_CTRL_SLM_MASK (0x400000U) +#define FMUTEST_R_PIN_CTRL_SLM_SHIFT (22U) +/*! SLM - Sleep Mode Enable */ +#define FMUTEST_R_PIN_CTRL_SLM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SLM_SHIFT)) & FMUTEST_R_PIN_CTRL_SLM_MASK) + +#define FMUTEST_R_PIN_CTRL_RECALL_MASK (0x800000U) +#define FMUTEST_R_PIN_CTRL_RECALL_SHIFT (23U) +/*! RECALL - Recall Trim Code */ +#define FMUTEST_R_PIN_CTRL_RECALL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_RECALL_SHIFT)) & FMUTEST_R_PIN_CTRL_RECALL_MASK) + +#define FMUTEST_R_PIN_CTRL_HEM_MASK (0x1000000U) +#define FMUTEST_R_PIN_CTRL_HEM_SHIFT (24U) +/*! HEM - HEM Control */ +#define FMUTEST_R_PIN_CTRL_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_HEM_SHIFT)) & FMUTEST_R_PIN_CTRL_HEM_MASK) +/*! @} */ + +/*! @name R_CNT_LOOP_CTRL - BIST Loop Count Control Register */ +/*! @{ */ + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK (0xFFFU) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT (0U) +/*! LOOPCNT - Loop Count Control */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK (0x7000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT (12U) +/*! LOOPOPT - Loop Option + * 0b000..Loop is disabled; selected BIST operation is run once + * 0b001..Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b010..Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b011..Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b100..Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1. + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK (0x38000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT (15U) +/*! LOOPUNIT - Loop Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK (0x1FC0000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT (18U) +/*! LOOPDLY - Loop Time Delay Scalar */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL - BIST Timer Control Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT (0U) +/*! TNVSUNIT - Tnvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK (0x78U) +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT (3U) +/*! TNVSDLY - Tnvs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK (0x380U) +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT (7U) +/*! TNVHUNIT - Tnvh Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK (0x3C00U) +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT (10U) +/*! TNVHDLY - Tnvh Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVHDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK (0x1C000U) +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT (14U) +/*! TPGSUNIT - Tpgs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK (0x1E0000U) +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT (17U) +/*! TPGSDLY - Tpgs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TPGSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK (0xE00000U) +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT (21U) +/*! TRCVUNIT - Trcv Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK (0xF000000U) +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT (24U) +/*! TRCVDLY - Trcv Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TRCVDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK (0x70000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT (28U) +/*! TLVSUNIT - Tlvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK (0x80000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT (31U) +/*! TLVSDLY_L - Tlvs Time Delay Scalar Low */ +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK) +/*! @} */ + +/*! @name R_TEST_CTRL - BIST Test Control Register */ +/*! @{ */ + +#define FMUTEST_R_TEST_CTRL_BUSY_MASK (0x1U) +#define FMUTEST_R_TEST_CTRL_BUSY_SHIFT (0U) +/*! BUSY - BIST Busy Status + * 0b0..BIST is idle + * 0b1..BIST is busy + */ +#define FMUTEST_R_TEST_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_BUSY_SHIFT)) & FMUTEST_R_TEST_CTRL_BUSY_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUG_MASK (0x2U) +#define FMUTEST_R_TEST_CTRL_DEBUG_SHIFT (1U) +/*! DEBUG - BIST Debug Status */ +#define FMUTEST_R_TEST_CTRL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUG_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUG_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS0_MASK (0x4U) +#define FMUTEST_R_TEST_CTRL_STATUS0_SHIFT (2U) +/*! STATUS0 - BIST Status 0 + * 0b0..BIST test passed on flash block 0 + * 0b1..BIST test failed on flash block 0 + */ +#define FMUTEST_R_TEST_CTRL_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS0_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS0_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS1_MASK (0x8U) +#define FMUTEST_R_TEST_CTRL_STATUS1_SHIFT (3U) +/*! STATUS1 - BIST status 1 + * 0b0..BIST test passed on flash block 1 + * 0b1..BIST test failed on flash block 1 + */ +#define FMUTEST_R_TEST_CTRL_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS1_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS1_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK (0x10U) +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT (4U) +/*! DEBUGRUN - BIST Continue Debug Run */ +#define FMUTEST_R_TEST_CTRL_DEBUGRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_STARTRUN_MASK (0x20U) +#define FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT (5U) +/*! STARTRUN - Run New BIST Operation */ +#define FMUTEST_R_TEST_CTRL_STARTRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_STARTRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_CMDINDEX_MASK (0xFFC0U) +#define FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT (6U) +/*! CMDINDEX - BIST Command Index (code) */ +#define FMUTEST_R_TEST_CTRL_CMDINDEX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT)) & FMUTEST_R_TEST_CTRL_CMDINDEX_MASK) + +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT (16U) +/*! DISABLE_IP1 - BIST Disable IP1 */ +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK) +/*! @} */ + +/*! @name R_ABORT_LOOP - BIST Abort Loop Register */ +/*! @{ */ + +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK (0x1U) +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT (0U) +/*! ABORT_LOOP - Abort Loop + * 0b0..No effect + * 0b1..Abort BIST loop commands and force the loop counter to return to 0x0 + */ +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT)) & FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK) +/*! @} */ + +/*! @name R_ADR_QUERY - BIST Address Query Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_QUERY_YADRFAIL_MASK (0x1FU) +#define FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT (0U) +/*! YADRFAIL - Failing YADR */ +#define FMUTEST_R_ADR_QUERY_YADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_YADRFAIL_MASK) + +#define FMUTEST_R_ADR_QUERY_XADRFAIL_MASK (0x1FFE0U) +#define FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT (5U) +/*! XADRFAIL - Failing XADR */ +#define FMUTEST_R_ADR_QUERY_XADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_XADRFAIL_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY0 - BIST DOUT Query 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT (0U) +/*! DOUTFAIL - Failing DOUT Low */ +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT)) & FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK) +/*! @} */ + +/*! @name R_SMW_QUERY - BIST SMW Query Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_QUERY_SMWLOOP_MASK (0x3FFU) +#define FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT (0U) +/*! SMWLOOP - SMW Total Loop Count */ +#define FMUTEST_R_SMW_QUERY_SMWLOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLOOP_MASK) + +#define FMUTEST_R_SMW_QUERY_SMWLAST_MASK (0x7FC00U) +#define FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT (10U) +/*! SMWLAST - SMW Last Voltage Setting */ +#define FMUTEST_R_SMW_QUERY_SMWLAST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLAST_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING0 - BIST SMW Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK (0x7FFFFFFFU) +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT (0U) +/*! SMWPARM0 - SMW Parameter Set 0 */ +#define FMUTEST_R_SMW_SETTING0_SMWPARM0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT)) & FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING1 - BIST SMW Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT (0U) +/*! SMWPARM1 - SMW Parameter Set 1 */ +#define FMUTEST_R_SMW_SETTING1_SMWPARM1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK) +/*! @} */ + +/*! @name R_SMP_WHV0 - BIST SMP WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV0_SMPWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT (0U) +/*! SMPWHV0 - SMP WHV Parameter Set 0 */ +#define FMUTEST_R_SMP_WHV0_SMPWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT)) & FMUTEST_R_SMP_WHV0_SMPWHV0_MASK) +/*! @} */ + +/*! @name R_SMP_WHV1 - BIST SMP WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV1_SMPWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT (0U) +/*! SMPWHV1 - SMP WHV Parameter Set 1 */ +#define FMUTEST_R_SMP_WHV1_SMPWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT)) & FMUTEST_R_SMP_WHV1_SMPWHV1_MASK) +/*! @} */ + +/*! @name R_SME_WHV0 - BIST SME WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT (0U) +/*! SMEWHV0 - SME WHV Parameter Set 0 */ +#define FMUTEST_R_SME_WHV0_SMEWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK) +/*! @} */ + +/*! @name R_SME_WHV1 - BIST SME WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV1_SMEWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT (0U) +/*! SMEWHV1 - SME WHV Parameter Set 1 */ +#define FMUTEST_R_SME_WHV1_SMEWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT)) & FMUTEST_R_SME_WHV1_SMEWHV1_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING2 - BIST SMW Setting 2 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK (0x1FFFFFFFU) +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT (0U) +/*! SMWPARM2 - SMW Parameter Set 2 */ +#define FMUTEST_R_SMW_SETTING2_SMWPARM2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT)) & FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK) +/*! @} */ + +/*! @name R_D_MISR0 - BIST DIN MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR0_DATASIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_D_MISR0_DATASIG0_SHIFT (0U) +/*! DATASIG0 - Data Signature */ +#define FMUTEST_R_D_MISR0_DATASIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR0_DATASIG0_SHIFT)) & FMUTEST_R_D_MISR0_DATASIG0_MASK) +/*! @} */ + +/*! @name R_A_MISR0 - BIST Address MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR0_ADRSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_A_MISR0_ADRSIG0_SHIFT (0U) +/*! ADRSIG0 - Address Signature */ +#define FMUTEST_R_A_MISR0_ADRSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR0_ADRSIG0_SHIFT)) & FMUTEST_R_A_MISR0_ADRSIG0_MASK) +/*! @} */ + +/*! @name R_C_MISR0 - BIST Control MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT (0U) +/*! CTRLSIG0 - Control Signature */ +#define FMUTEST_R_C_MISR0_CTRLSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING3 - BIST SMW Setting 3 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK (0x1FFFFU) +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT (0U) +/*! SMWPARM3 - SMW Parameter Set 3 */ +#define FMUTEST_R_SMW_SETTING3_SMWPARM3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT)) & FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1 - BIST Data Control 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL1_DATA1_SHIFT (0U) +/*! DATA1 - BIST Data 1 Low */ +#define FMUTEST_R_DATA_CTRL1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_DATA1_SHIFT)) & FMUTEST_R_DATA_CTRL1_DATA1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2 - BIST Data Control 2 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL2_DATA2_SHIFT (0U) +/*! DATA2 - BIST Data 2 Low */ +#define FMUTEST_R_DATA_CTRL2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_DATA2_SHIFT)) & FMUTEST_R_DATA_CTRL2_DATA2_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3 - BIST Data Control 3 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL3_DATA3_SHIFT (0U) +/*! DATA3 - BIST Data 3 Low */ +#define FMUTEST_R_DATA_CTRL3_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_DATA3_SHIFT)) & FMUTEST_R_DATA_CTRL3_DATA3_MASK) +/*! @} */ + +/*! @name R_REPAIR0_0 - BIST Repair 0 for Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - Control Repair 0 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_R_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - XADR for Repair 0 in Block 0 */ +#define FMUTEST_R_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name R_REPAIR0_1 - BIST Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - Control Repair 1 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_R_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - XADR for Repair 1 in Block 0. */ +#define FMUTEST_R_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name R_REPAIR1_0 - BIST Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - Control Repair 0 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_R_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - XADR for Repair 0 in Block 1. */ +#define FMUTEST_R_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name R_REPAIR1_1 - BIST Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - Control Repair 1 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_R_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - XADR for Repair 1 in Block 1. */ +#define FMUTEST_R_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0_EX - BIST Data Control 0 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT (0U) +/*! DATA0X - BIST Data 0 High */ +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT)) & FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL_EX - BIST Timer Control Extension Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT (0U) +/*! TLVSDLY_H - Tlvs Time Delay Scalar High */ +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT)) & FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY1 - BIST DOUT Query 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY1_DOUT_MASK (0x7U) +#define FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT (0U) +/*! DOUT - Failing DOUT High */ +#define FMUTEST_R_DOUT_QUERY1_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT)) & FMUTEST_R_DOUT_QUERY1_DOUT_MASK) +/*! @} */ + +/*! @name R_D_MISR1 - BIST DIN MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR1_DATASIG1_MASK (0xFFU) +#define FMUTEST_R_D_MISR1_DATASIG1_SHIFT (0U) +/*! DATASIG1 - MISR Data Signature High */ +#define FMUTEST_R_D_MISR1_DATASIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR1_DATASIG1_SHIFT)) & FMUTEST_R_D_MISR1_DATASIG1_MASK) +/*! @} */ + +/*! @name R_A_MISR1 - BIST Address MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR1_ADRSIG1_MASK (0xFFU) +#define FMUTEST_R_A_MISR1_ADRSIG1_SHIFT (0U) +/*! ADRSIG1 - MISR Address Signature High */ +#define FMUTEST_R_A_MISR1_ADRSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR1_ADRSIG1_SHIFT)) & FMUTEST_R_A_MISR1_ADRSIG1_MASK) +/*! @} */ + +/*! @name R_C_MISR1 - BIST Control MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR1_CTRLSIG1_MASK (0xFFU) +#define FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT (0U) +/*! CTRLSIG1 - MISR Control Signature High */ +#define FMUTEST_R_C_MISR1_CTRLSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT)) & FMUTEST_R_C_MISR1_CTRLSIG1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1_EX - BIST Data Control 1 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT (0U) +/*! DATA1X - BIST Data 1 High */ +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT)) & FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2_EX - BIST Data Control 2 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT (0U) +/*! DATA2X - BIST Data 2 High */ +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT)) & FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3_EX - BIST Data Control 3 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT (0U) +/*! DATA3X - BIST Data 3 High */ +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT)) & FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK) +/*! @} */ + +/*! @name SMW_TIMER_OPTION - SMW Timer Option Register */ +/*! @{ */ + +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK (0xFFU) +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT (0U) +/*! SMW_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK) + +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK (0x1F00U) +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT (8U) +/*! SMW_TVFY - Timer Adjust for Verify */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION0 - SMW Setting Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK (0x1C000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT (14U) +/*! MV_INIT - Medium Voltage Level Select Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK (0xE0000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT (17U) +/*! MV_END - Medium Voltage Level Select Final */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK (0xF00000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT (20U) +/*! MV_MISC - Medium Voltage Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK (0x3000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT (24U) +/*! IPGM_INIT - Program Current Control Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK (0xC000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT (26U) +/*! IPGM_END - Program Current Control Final */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK (0x70000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT (28U) +/*! IPGM_MISC - Program Current Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION2 - SMW Setting Option 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT (0U) +/*! THVS_CTRL - Thvs control */ +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK (0x38U) +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT (3U) +/*! TRCV_CTRL - Trcv Control */ +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK (0xC0U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT (6U) +/*! XTRA_ERS - Number of Post Shots for SME */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK (0x300U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT (8U) +/*! XTRA_PGM - Number of Post Shots for SMP */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK (0x3FC00U) +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT (10U) +/*! WHV_CNTR - WHV Counter */ +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK (0x1C0000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT (18U) +/*! POST_TERS - Post Ters Time + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK (0x600000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT (21U) +/*! POST_TPGM - Post Tpgm Time + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK (0x1800000U) +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT (23U) +/*! VFY_OPT - Verify Option + * 0b00..Skip verify for post shot only, verify for all other shots + * 0b01..Skip verify for the 1st and post shots + * 0b10..Skip the 1st, 2nd, and post shots + * 0b11..Skip verify for all shots + */ +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK (0x6000000U) +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT (25U) +/*! TPGM_OPT - Tpgm Option + * 0b00..Fixed Tpgm for all shots, except post shot + * 0b01..Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec + * 0b10..Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec + * 0b11..Unused + */ +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT (27U) +/*! MASK0_OPT - MASK0_OPT + * 0b0..Mask programmed bits passing PV until extra shot + * 0b1..Always program bits even if they pass PV + */ +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK (0x10000000U) +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT (28U) +/*! DIS_PRER - Disable pre-PV Read before First Program Shot + * 0b0..Enable pre-PV read before first program shot + * 0b1..Disable pre-PV read before first program shot + */ +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION3 - SMW Setting Option 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK (0xFFU) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT (0U) +/*! HEM_WHV_CNTR - WHV_COUNTER for HEM-erase Cycle */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK (0x1FF00U) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT (8U) +/*! HEM_MAX_ERS - HEM Max Erase Shot Count */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION0 - SMW SMP WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT (0U) +/*! SMP_WHV_OPT0 - Smart Program WHV Option Low */ +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION0 - SMW SME WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT (0U) +/*! SME_WHV_OPT0 - Smart Erase WHV Option Low */ +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION1 - SMW Setting Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT (0U) +/*! TERS_CTRL0 - Ters Control + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK (0x18U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT (3U) +/*! TPGM_CTRL - Tpgm Control + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK (0xE0U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT (5U) +/*! TNVS_CTRL - Tnvs Control + * 0b000..5 usec + * 0b001..8 usec + * 0b010..11 usec + * 0b011..14 usec + * 0b100..17 usec + * 0b101..20 usec + * 0b110..23 usec + * 0b111..26 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK (0x700U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT (8U) +/*! TNVH_CTRL - Tnvh Control + * 0b000..2 usec + * 0b001..2.5 usec + * 0b010..3 usec + * 0b011..3.5 usec + * 0b100..4 usec + * 0b101..4.5 usec + * 0b110..5 usec + * 0b111..5.5 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK (0x3800U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT (11U) +/*! TPGS_CTRL - Tpgs Control + * 0b000..1 usec + * 0b001..2 usec + * 0b010..3 usec + * 0b011..4 usec + * 0b100..5 usec + * 0b101..6 usec + * 0b110..7 usec + * 0b111..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK (0x7FC000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT (14U) +/*! MAX_ERASE - Number of Erase Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK (0xF800000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT (23U) +/*! MAX_PROG - Number of Program Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION1 - SMW SMP WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT (0U) +/*! SMP_WHV_OPT1 - Smart Program WHV Option High */ +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION1 - SMW SME WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT (0U) +/*! SME_WHV_OPT1 - Smart Erase WHV Option High */ +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK) +/*! @} */ + +/*! @name REPAIR0_0 - FMU Repair 0 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - RDIS0_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - RADR0_0 */ +#define FMUTEST_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name REPAIR0_1 - FMU Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - RDIS0_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - RADR0_1 */ +#define FMUTEST_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name REPAIR1_0 - FMU Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - RDIS1_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - RADR1_0 */ +#define FMUTEST_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name REPAIR1_1 - FMU Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - RDIS1_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - RADR1_1 */ +#define FMUTEST_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name SMW_HB_SIGNALS - SMW HB Signals Register */ +/*! @{ */ + +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK (0x7U) +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT (0U) +/*! SMW_ARRAY - SMW Region Select + * 0b000..Main array + * 0b001..IFR space only or main (and REDEN space) with IFR space for mass erase + * 0b010..IFR1 space + * 0b100..REDEN space + */ +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK (0x8U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT (3U) +/*! USER_IFREN1 - IFR1 Enable + * 0b0..IFREN1 input to the flash array is driven LOW + * 0b1..IFREN1 input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK (0x10U) +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT (4U) +/*! USER_PV - Program Verify + * 0b0..PV input to the flash array is driven LOW + * 0b1..PV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK (0x20U) +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT (5U) +/*! USER_EV - Erase Verify + * 0b0..EV input to the flash array is driven LOW + * 0b1..EV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK (0x40U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT (6U) +/*! USER_IFREN - IFR Enable + * 0b0..IFREN input to the flash array is driven LOW + * 0b1..IFREN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK (0x80U) +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT (7U) +/*! USER_REDEN - Repair Read Enable + * 0b0..REDEN input to the flash array is driven LOW + * 0b1..REDEN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK (0x100U) +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT (8U) +/*! USER_HEM - High Endurance Enable + * 0b0..HEM input to SMW / BIST PIN_CTRL[24] is driven LOW + * 0b1..HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK) +/*! @} */ + +/*! @name BIST_DUMP_CTRL - BIST Datadump Control Register */ +/*! @{ */ + +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK (0x10000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT (16U) +/*! BIST_DONE - BIST Done + * 0b0..The BIST (or data dump) is running + * 0b1..The BIST (or data dump) has completed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK (0x20000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT (17U) +/*! BIST_FAIL - BIST Fail + * 0b0..The last BIST operation completed successfully (or could not fail) + * 0b1..The last BIST operation failed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK (0x40000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT (18U) +/*! DATADUMP - Data Dump Enable */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK (0x80000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT (19U) +/*! DATADUMP_TRIG - Data Dump Trigger */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK (0x300000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT (20U) +/*! DATADUMP_PATT - Data Dump Pattern Select + * 0b00..All ones + * 0b01..All zeroes + * 0b10..Checkerboard + * 0b11..Inverse checkerboard + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK (0x400000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT (22U) +/*! DATADUMP_MRGEN - Data Dump Margin Enable + * 0b0..Normal read pulse shape + * 0b1..Margin read pulse shape + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK (0x800000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT (23U) +/*! DATADUMP_MRGTYPE - Data Dump Margin Type + * 0b0..DIN method used + * 0b1..TM method used + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK) +/*! @} */ + +/*! @name ATX_PIN_CTRL - ATX Pin Control Register */ +/*! @{ */ + +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK (0xFFU) +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT (0U) +/*! TM_TO_ATX - TM to ATX + * 0b00000001..TM[0] to ATX0 + * 0b00000010..TM[1] to ATX0 + * 0b00000100..TM[2] to ATX0 + * 0b00001000..TM[3] to ATX0 + * 0b00010000..TM[0] to ATX1 + * 0b00100000..TM[1] to ATX1 + * 0b01000000..TM[2] to ATX1 + * 0b10000000..TM[3] to ATX1 + */ +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT)) & FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK) +/*! @} */ + +/*! @name FAILCNT - Fail Count Register */ +/*! @{ */ + +#define FMUTEST_FAILCNT_FAILCNT_MASK (0xFFFFFFFFU) +#define FMUTEST_FAILCNT_FAILCNT_SHIFT (0U) +/*! FAILCNT - Fail Count */ +#define FMUTEST_FAILCNT_FAILCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FAILCNT_FAILCNT_SHIFT)) & FMUTEST_FAILCNT_FAILCNT_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT0 - Block 0 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT (0U) +/*! PGM_CNT0 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT)) & FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT1 - Block 1 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT (0U) +/*! PGM_CNT1 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT)) & FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK) +/*! @} */ + +/*! @name ERS_PULSE_CNT - Erase Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK (0xFFFFU) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT (0U) +/*! ERS_CNT0 - Block 0 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK) + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK (0xFFFF0000U) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT (16U) +/*! ERS_CNT1 - Block 1 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK) +/*! @} */ + +/*! @name MAX_PULSE_CNT - Maximum Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK (0x1FFU) +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT (0U) +/*! LAST_PCNT - Last SMW Operation's Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK (0x1FF0000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT (16U) +/*! MAX_ERS_CNT - Maximum Erase Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK (0xF8000000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT (27U) +/*! MAX_PGM_CNT - Maximum Program Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK) +/*! @} */ + +/*! @name PORT_CTRL - Port Control Register */ +/*! @{ */ + +#define FMUTEST_PORT_CTRL_BDONE_SEL_MASK (0x3U) +#define FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT (0U) +/*! BDONE_SEL - BIST Done Select + * 0b00..Select internal bist_done signal from current module instantiation + * 0b01..Select ipt_bist_fail signal from current module instantiation + * 0b10..Select ipt_bist_done signal from other module instantiation + * 0b11..Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BDONE_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BDONE_SEL_MASK) + +#define FMUTEST_PORT_CTRL_BSDO_SEL_MASK (0xCU) +#define FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT (2U) +/*! BSDO_SEL - BIST Serial Data Output Select + * 0b00..Select internal bist_sdo signal from current module instantiation + * 0b01..Select ipt_bist_done signal from current module instantiation + * 0b10..Select ipt_bist_sdo signal from other module instantiation + * 0b11..Select ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BSDO_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BSDO_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMUTEST_Register_Masks */ + + +/* FMUTEST - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x50043000u) + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE_NS (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST_NS ((FMUTEST_Type *)FMU0TEST_BASE_NS) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS_NS { FMU0TEST_BASE_NS } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS_NS { FMU0TEST_NS } +#else + /** Peripheral FMU0TEST base address */ + #define FMU0TEST_BASE (0x40043000u) + /** Peripheral FMU0TEST base pointer */ + #define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) + /** Array initializer of FMUTEST peripheral base addresses */ + #define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } + /** Array initializer of FMUTEST peripheral base pointers */ + #define FMUTEST_BASE_PTRS { FMU0TEST } +#endif + +/*! + * @} + */ /* end of group FMUTEST_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FREQME Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer + * @{ + */ + +/** FREQME - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */ + __O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */ + }; + __IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */ + __IO uint32_t MIN; /**< Minimum, offset: 0x8 */ + __IO uint32_t MAX; /**< Maximum, offset: 0xC */ +} FREQME_Type; + +/* ---------------------------------------------------------------------------- + -- FREQME Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Register_Masks FREQME Register Masks + * @{ + */ + +/*! @name CTRL_R - Control (in Read mode) */ +/*! @{ */ + +#define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU) +#define FREQME_CTRL_R_RESULT_SHIFT (0U) +#define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK) + +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Complete + * 0b1..In progress + */ +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRL_W - Control (in Write mode) */ +/*! @{ */ + +#define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRL_W_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Clock Scaling Factor */ +#define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK) + +#define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Width Measurement Mode Select + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK) + +#define FREQME_CTRL_W_PULSE_POL_MASK (0x200U) +#define FREQME_CTRL_W_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK) + +#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Terminates measurement + * 0b1..Initiates measurement + */ +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRLSTAT - Control Status */ +/*! @{ */ + +#define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Scale */ +#define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK) + +#define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Mode + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK) + +#define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U) +#define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) +#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U) +/*! LT_MIN_STAT - Less Than Minimum Results Status + * 0b0..Greater than MIN[MIN_VALUE] + * 0b1..Less than MIN[MIN_VALUE] + */ +#define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) +#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U) +/*! GT_MAX_STAT - Greater Than Maximum Result Status + * 0b0..Less than MAX[MAX_VALUE] + * 0b1..Greater than MAX[MAX_VALUE] + */ +#define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) +#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U) +/*! RESULT_READY_STAT - Result Ready Status + * 0b0..Not complete + * 0b1..Complete + */ +#define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK) + +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement in Progress Status + * 0b0..Not in progress + * 0b1..In progress + */ +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name MIN - Minimum */ +/*! @{ */ + +#define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MIN_MIN_VALUE_SHIFT (0U) +/*! MIN_VALUE - Minimum Value */ +#define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK) +/*! @} */ + +/*! @name MAX - Maximum */ +/*! @{ */ + +#define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MAX_MAX_VALUE_SHIFT (0U) +/*! MAX_VALUE - Maximum Value */ +#define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FREQME_Register_Masks */ + + +/* FREQME - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x50011000u) + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE_NS (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Peripheral FREQME0 base pointer */ + #define FREQME0_NS ((FREQME_Type *)FREQME0_BASE_NS) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS_NS { FREQME0_BASE_NS } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS_NS { FREQME0_NS } +#else + /** Peripheral FREQME0 base address */ + #define FREQME0_BASE (0x40011000u) + /** Peripheral FREQME0 base pointer */ + #define FREQME0 ((FREQME_Type *)FREQME0_BASE) + /** Array initializer of FREQME peripheral base addresses */ + #define FREQME_BASE_ADDRS { FREQME0_BASE } + /** Array initializer of FREQME peripheral base pointers */ + #define FREQME_BASE_PTRS { FREQME0 } +#endif +/** Interrupt vectors for the FREQME peripheral type */ +#define FREQME_IRQS { Freqme_IRQn } + +/*! + * @} + */ /* end of group FREQME_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GDET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GDET_Peripheral_Access_Layer GDET Peripheral Access Layer + * @{ + */ + +/** GDET - Register Layout Typedef */ +typedef struct { + __IO uint32_t GDET_CONF_0; /**< GDET Configuration 0 Register, offset: 0x0 */ + __IO uint32_t GDET_CONF_1; /**< GDET Configuration 1 Register, offset: 0x4 */ + __IO uint32_t GDET_ENABLE1; /**< GDET Enable Register, offset: 0x8 */ + __IO uint32_t GDET_CONF_2; /**< GDET Configuration 2 Register, offset: 0xC */ + __IO uint32_t GDET_CONF_3; /**< GDET Configuration 3 Register, offset: 0x10 */ + __IO uint32_t GDET_CONF_4; /**< GDET Configuration 4 Register, offset: 0x14 */ + __IO uint32_t GDET_CONF_5; /**< GDET Configuration 5 Register, offset: 0x18 */ + uint8_t RESERVED_0[4004]; + __IO uint32_t GDET_RESET; /**< GDET Reset Register, offset: 0xFC0 */ + __IO uint32_t GDET_TEST; /**< GDET Test Register, offset: 0xFC4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t GDET_DLY_CTRL; /**< GDET Delay Control Register, offset: 0xFCC */ +} GDET_Type; + +/* ---------------------------------------------------------------------------- + -- GDET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GDET_Register_Masks GDET Register Masks + * @{ + */ + +/*! @name GDET_CONF_0 - GDET Configuration 0 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_0_FIELD_3_0_MASK (0xFU) +#define GDET_GDET_CONF_0_FIELD_3_0_SHIFT (0U) +/*! FIELD_3_0 - GDET Configuration 0 Field 3_0 */ +#define GDET_GDET_CONF_0_FIELD_3_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_FIELD_3_0_SHIFT)) & GDET_GDET_CONF_0_FIELD_3_0_MASK) + +#define GDET_GDET_CONF_0_SBZ_MASK (0x10U) +#define GDET_GDET_CONF_0_SBZ_SHIFT (4U) +/*! SBZ - Should Be Left to Zero */ +#define GDET_GDET_CONF_0_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_SBZ_SHIFT)) & GDET_GDET_CONF_0_SBZ_MASK) + +#define GDET_GDET_CONF_0_RFU_MASK (0xFFFFFFE0U) +#define GDET_GDET_CONF_0_RFU_SHIFT (5U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_CONF_0_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_0_RFU_SHIFT)) & GDET_GDET_CONF_0_RFU_MASK) +/*! @} */ + +/*! @name GDET_CONF_1 - GDET Configuration 1 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_1_FIELD_1_0_MASK (0x3U) +#define GDET_GDET_CONF_1_FIELD_1_0_SHIFT (0U) +/*! FIELD_1_0 - GDET Configuration 1 Field 1_0 */ +#define GDET_GDET_CONF_1_FIELD_1_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_1_0_SHIFT)) & GDET_GDET_CONF_1_FIELD_1_0_MASK) + +#define GDET_GDET_CONF_1_FIELD_3_2_MASK (0xCU) +#define GDET_GDET_CONF_1_FIELD_3_2_SHIFT (2U) +/*! FIELD_3_2 - GDET Configuration 1 Field 3_2 */ +#define GDET_GDET_CONF_1_FIELD_3_2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_3_2_SHIFT)) & GDET_GDET_CONF_1_FIELD_3_2_MASK) + +#define GDET_GDET_CONF_1_SBZ1_MASK (0x10U) +#define GDET_GDET_CONF_1_SBZ1_SHIFT (4U) +/*! SBZ1 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ1_SHIFT)) & GDET_GDET_CONF_1_SBZ1_MASK) + +#define GDET_GDET_CONF_1_SBZ2_MASK (0x20U) +#define GDET_GDET_CONF_1_SBZ2_SHIFT (5U) +/*! SBZ2 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ2_SHIFT)) & GDET_GDET_CONF_1_SBZ2_MASK) + +#define GDET_GDET_CONF_1_SBZ3_MASK (0x40U) +#define GDET_GDET_CONF_1_SBZ3_SHIFT (6U) +/*! SBZ3 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ3_SHIFT)) & GDET_GDET_CONF_1_SBZ3_MASK) + +#define GDET_GDET_CONF_1_FIELD_7_MASK (0x80U) +#define GDET_GDET_CONF_1_FIELD_7_SHIFT (7U) +/*! FIELD_7 - GDET Configuration 1 Field 7 */ +#define GDET_GDET_CONF_1_FIELD_7(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_7_SHIFT)) & GDET_GDET_CONF_1_FIELD_7_MASK) + +#define GDET_GDET_CONF_1_FIELD_8_MASK (0x100U) +#define GDET_GDET_CONF_1_FIELD_8_SHIFT (8U) +/*! FIELD_8 - GDET Configuration 1 Field 8 */ +#define GDET_GDET_CONF_1_FIELD_8(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_FIELD_8_SHIFT)) & GDET_GDET_CONF_1_FIELD_8_MASK) + +#define GDET_GDET_CONF_1_SBZ4_MASK (0x200U) +#define GDET_GDET_CONF_1_SBZ4_SHIFT (9U) +/*! SBZ4 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ4(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ4_SHIFT)) & GDET_GDET_CONF_1_SBZ4_MASK) + +#define GDET_GDET_CONF_1_SBZ5_MASK (0x400U) +#define GDET_GDET_CONF_1_SBZ5_SHIFT (10U) +/*! SBZ5 - Should Be Left to Zero */ +#define GDET_GDET_CONF_1_SBZ5(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_SBZ5_SHIFT)) & GDET_GDET_CONF_1_SBZ5_MASK) + +#define GDET_GDET_CONF_1_RFU_MASK (0xFFFFF800U) +#define GDET_GDET_CONF_1_RFU_SHIFT (11U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_CONF_1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_1_RFU_SHIFT)) & GDET_GDET_CONF_1_RFU_MASK) +/*! @} */ + +/*! @name GDET_ENABLE1 - GDET Enable Register */ +/*! @{ */ + +#define GDET_GDET_ENABLE1_EN1_MASK (0x1U) +#define GDET_GDET_ENABLE1_EN1_SHIFT (0U) +/*! EN1 - If set, the detector will be clock gated */ +#define GDET_GDET_ENABLE1_EN1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_EN1_SHIFT)) & GDET_GDET_ENABLE1_EN1_MASK) + +#define GDET_GDET_ENABLE1_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_ENABLE1_RFU_SHIFT (1U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_ENABLE1_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_ENABLE1_RFU_SHIFT)) & GDET_GDET_ENABLE1_RFU_MASK) +/*! @} */ + +/*! @name GDET_CONF_2 - GDET Configuration 2 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_2_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_2_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 2 Field 6_0 */ +#define GDET_GDET_CONF_2_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_2_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_2_RFU1_MASK (0xFF80U) +#define GDET_GDET_CONF_2_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU1_SHIFT)) & GDET_GDET_CONF_2_RFU1_MASK) + +#define GDET_GDET_CONF_2_FIELD_21_16_MASK (0x3F0000U) +#define GDET_GDET_CONF_2_FIELD_21_16_SHIFT (16U) +/*! FIELD_21_16 - GDET Configuration 2 Field 21_16 */ +#define GDET_GDET_CONF_2_FIELD_21_16(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_21_16_SHIFT)) & GDET_GDET_CONF_2_FIELD_21_16_MASK) + +#define GDET_GDET_CONF_2_RFU2_MASK (0xC00000U) +#define GDET_GDET_CONF_2_RFU2_SHIFT (22U) +/*! RFU2 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU2_SHIFT)) & GDET_GDET_CONF_2_RFU2_MASK) + +#define GDET_GDET_CONF_2_FIELD_29_24_MASK (0x3F000000U) +#define GDET_GDET_CONF_2_FIELD_29_24_SHIFT (24U) +/*! FIELD_29_24 - GDET Configuration 2 Field 29_24 */ +#define GDET_GDET_CONF_2_FIELD_29_24(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_FIELD_29_24_SHIFT)) & GDET_GDET_CONF_2_FIELD_29_24_MASK) + +#define GDET_GDET_CONF_2_RFU3_MASK (0xC0000000U) +#define GDET_GDET_CONF_2_RFU3_SHIFT (30U) +/*! RFU3 - Reserved for Future Use */ +#define GDET_GDET_CONF_2_RFU3(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_2_RFU3_SHIFT)) & GDET_GDET_CONF_2_RFU3_MASK) +/*! @} */ + +/*! @name GDET_CONF_3 - GDET Configuration 3 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_3_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_3_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 3 Field 6_0 */ +#define GDET_GDET_CONF_3_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_3_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_3_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_3_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_3_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_3_RFU1_SHIFT)) & GDET_GDET_CONF_3_RFU1_MASK) +/*! @} */ + +/*! @name GDET_CONF_4 - GDET Configuration 4 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_4_FIELD_6_0_MASK (0x7FU) +#define GDET_GDET_CONF_4_FIELD_6_0_SHIFT (0U) +/*! FIELD_6_0 - GDET Configuration 4 Field 6_0 */ +#define GDET_GDET_CONF_4_FIELD_6_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_FIELD_6_0_SHIFT)) & GDET_GDET_CONF_4_FIELD_6_0_MASK) + +#define GDET_GDET_CONF_4_RFU1_MASK (0xFFFFFF80U) +#define GDET_GDET_CONF_4_RFU1_SHIFT (7U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_4_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_4_RFU1_SHIFT)) & GDET_GDET_CONF_4_RFU1_MASK) +/*! @} */ + +/*! @name GDET_CONF_5 - GDET Configuration 5 Register */ +/*! @{ */ + +#define GDET_GDET_CONF_5_FIELD_5_0_MASK (0x3FU) +#define GDET_GDET_CONF_5_FIELD_5_0_SHIFT (0U) +/*! FIELD_5_0 - GDET Configuration 5 Field 5_0 */ +#define GDET_GDET_CONF_5_FIELD_5_0(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_5_0_SHIFT)) & GDET_GDET_CONF_5_FIELD_5_0_MASK) + +#define GDET_GDET_CONF_5_FIELD_11_6_MASK (0xFC0U) +#define GDET_GDET_CONF_5_FIELD_11_6_SHIFT (6U) +/*! FIELD_11_6 - GDET Configuration 5 Field 11_6 */ +#define GDET_GDET_CONF_5_FIELD_11_6(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_FIELD_11_6_SHIFT)) & GDET_GDET_CONF_5_FIELD_11_6_MASK) + +#define GDET_GDET_CONF_5_RFU1_MASK (0xFFFFF000U) +#define GDET_GDET_CONF_5_RFU1_SHIFT (12U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_CONF_5_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_CONF_5_RFU1_SHIFT)) & GDET_GDET_CONF_5_RFU1_MASK) +/*! @} */ + +/*! @name GDET_RESET - GDET Reset Register */ +/*! @{ */ + +#define GDET_GDET_RESET_RFU1_MASK (0x7U) +#define GDET_GDET_RESET_RFU1_SHIFT (0U) +/*! RFU1 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU1(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU1_SHIFT)) & GDET_GDET_RESET_RFU1_MASK) + +#define GDET_GDET_RESET_SFT_RST_MASK (0x8U) +#define GDET_GDET_RESET_SFT_RST_SHIFT (3U) +/*! SFT_RST - Soft Reset for the Core Reset */ +#define GDET_GDET_RESET_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_SFT_RST_SHIFT)) & GDET_GDET_RESET_SFT_RST_MASK) + +#define GDET_GDET_RESET_RFU2_MASK (0xFFFFFFF0U) +#define GDET_GDET_RESET_RFU2_SHIFT (4U) +/*! RFU2 - Reserved for Future Use */ +#define GDET_GDET_RESET_RFU2(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_RESET_RFU2_SHIFT)) & GDET_GDET_RESET_RFU2_MASK) +/*! @} */ + +/*! @name GDET_TEST - GDET Test Register */ +/*! @{ */ + +#define GDET_GDET_TEST_SBZ_MASK (0x1U) +#define GDET_GDET_TEST_SBZ_SHIFT (0U) +/*! SBZ - Should Be Left to Zero */ +#define GDET_GDET_TEST_SBZ(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_SBZ_SHIFT)) & GDET_GDET_TEST_SBZ_MASK) + +#define GDET_GDET_TEST_RFU_MASK (0xFFFFFFFEU) +#define GDET_GDET_TEST_RFU_SHIFT (1U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_TEST_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_TEST_RFU_SHIFT)) & GDET_GDET_TEST_RFU_MASK) +/*! @} */ + +/*! @name GDET_DLY_CTRL - GDET Delay Control Register */ +/*! @{ */ + +#define GDET_GDET_DLY_CTRL_VOL_SEL_MASK (0x3U) +#define GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT (0U) +/*! VOL_SEL - GDET Delay Control of the Voltage Mode */ +#define GDET_GDET_DLY_CTRL_VOL_SEL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_VOL_SEL_SHIFT)) & GDET_GDET_DLY_CTRL_VOL_SEL_MASK) + +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK (0x4U) +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT (2U) +/*! SW_VOL_CTRL - Select the Control of the Trim Code to the Delay Line */ +#define GDET_GDET_DLY_CTRL_SW_VOL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_SW_VOL_CTRL_SHIFT)) & GDET_GDET_DLY_CTRL_SW_VOL_CTRL_MASK) + +#define GDET_GDET_DLY_CTRL_RFU_MASK (0xFFFFFFF8U) +#define GDET_GDET_DLY_CTRL_RFU_SHIFT (3U) +/*! RFU - Reserved for Future Use */ +#define GDET_GDET_DLY_CTRL_RFU(x) (((uint32_t)(((uint32_t)(x)) << GDET_GDET_DLY_CTRL_RFU_SHIFT)) & GDET_GDET_DLY_CTRL_RFU_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GDET_Register_Masks */ + + +/* GDET - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x50024000u) + /** Peripheral GDET0 base address */ + #define GDET0_BASE_NS (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET0 base pointer */ + #define GDET0_NS ((GDET_Type *)GDET0_BASE_NS) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x50025000u) + /** Peripheral GDET1 base address */ + #define GDET1_BASE_NS (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Peripheral GDET1 base pointer */ + #define GDET1_NS ((GDET_Type *)GDET1_BASE_NS) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS_NS { GDET0_BASE_NS, GDET1_BASE_NS } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS_NS { GDET0_NS, GDET1_NS } +#else + /** Peripheral GDET0 base address */ + #define GDET0_BASE (0x40024000u) + /** Peripheral GDET0 base pointer */ + #define GDET0 ((GDET_Type *)GDET0_BASE) + /** Peripheral GDET1 base address */ + #define GDET1_BASE (0x40025000u) + /** Peripheral GDET1 base pointer */ + #define GDET1 ((GDET_Type *)GDET1_BASE) + /** Array initializer of GDET peripheral base addresses */ + #define GDET_BASE_ADDRS { GDET0_BASE, GDET1_BASE } + /** Array initializer of GDET peripheral base pointers */ + #define GDET_BASE_PTRS { GDET0, GDET1 } +#endif + +/*! + * @} + */ /* end of group GDET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LOCK; /**< Lock, offset: 0xC */ + __IO uint32_t PCNS; /**< Pin Control Nonsecure, offset: 0x10 */ + __IO uint32_t ICNS; /**< Interrupt Control Nonsecure, offset: 0x14 */ + __IO uint32_t PCNP; /**< Pin Control Nonprivilege, offset: 0x18 */ + __IO uint32_t ICNP; /**< Interrupt Control Nonprivilege, offset: 0x1C */ + uint8_t RESERVED_1[32]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_2[4]; + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_3[24]; + __IO uint32_t ISFR[2]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define GPIO_VERID_FEATURE_MASK (0xFFFFU) +#define GPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) + +#define GPIO_VERID_MINOR_MASK (0xFF0000U) +#define GPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK) + +#define GPIO_VERID_MAJOR_MASK (0xFF000000U) +#define GPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define GPIO_PARAM_IRQNUM_MASK (0xFU) +#define GPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define GPIO_LOCK_PCNS_MASK (0x1U) +#define GPIO_LOCK_PCNS_SHIFT (0U) +/*! PCNS - Lock PCNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_PCNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNS_SHIFT)) & GPIO_LOCK_PCNS_MASK) + +#define GPIO_LOCK_ICNS_MASK (0x2U) +#define GPIO_LOCK_ICNS_SHIFT (1U) +/*! ICNS - Lock ICNS + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_ICNS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNS_SHIFT)) & GPIO_LOCK_ICNS_MASK) + +#define GPIO_LOCK_PCNP_MASK (0x4U) +#define GPIO_LOCK_PCNP_SHIFT (2U) +/*! PCNP - Lock PCNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_PCNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_PCNP_SHIFT)) & GPIO_LOCK_PCNP_MASK) + +#define GPIO_LOCK_ICNP_MASK (0x8U) +#define GPIO_LOCK_ICNP_SHIFT (3U) +/*! ICNP - Lock ICNP + * 0b0..Writable in Secure-Privilege state + * 0b1..Not writable until the next reset + */ +#define GPIO_LOCK_ICNP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_LOCK_ICNP_SHIFT)) & GPIO_LOCK_ICNP_MASK) +/*! @} */ + +/*! @name PCNS - Pin Control Nonsecure */ +/*! @{ */ + +#define GPIO_PCNS_NSE0_MASK (0x1U) +#define GPIO_PCNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE0_SHIFT)) & GPIO_PCNS_NSE0_MASK) + +#define GPIO_PCNS_NSE1_MASK (0x2U) +#define GPIO_PCNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE1_SHIFT)) & GPIO_PCNS_NSE1_MASK) + +#define GPIO_PCNS_NSE2_MASK (0x4U) +#define GPIO_PCNS_NSE2_SHIFT (2U) +/*! NSE2 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE2_SHIFT)) & GPIO_PCNS_NSE2_MASK) + +#define GPIO_PCNS_NSE3_MASK (0x8U) +#define GPIO_PCNS_NSE3_SHIFT (3U) +/*! NSE3 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE3_SHIFT)) & GPIO_PCNS_NSE3_MASK) + +#define GPIO_PCNS_NSE4_MASK (0x10U) +#define GPIO_PCNS_NSE4_SHIFT (4U) +/*! NSE4 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE4_SHIFT)) & GPIO_PCNS_NSE4_MASK) + +#define GPIO_PCNS_NSE5_MASK (0x20U) +#define GPIO_PCNS_NSE5_SHIFT (5U) +/*! NSE5 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE5_SHIFT)) & GPIO_PCNS_NSE5_MASK) + +#define GPIO_PCNS_NSE6_MASK (0x40U) +#define GPIO_PCNS_NSE6_SHIFT (6U) +/*! NSE6 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE6_SHIFT)) & GPIO_PCNS_NSE6_MASK) + +#define GPIO_PCNS_NSE7_MASK (0x80U) +#define GPIO_PCNS_NSE7_SHIFT (7U) +/*! NSE7 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE7_SHIFT)) & GPIO_PCNS_NSE7_MASK) + +#define GPIO_PCNS_NSE8_MASK (0x100U) +#define GPIO_PCNS_NSE8_SHIFT (8U) +/*! NSE8 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE8_SHIFT)) & GPIO_PCNS_NSE8_MASK) + +#define GPIO_PCNS_NSE9_MASK (0x200U) +#define GPIO_PCNS_NSE9_SHIFT (9U) +/*! NSE9 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE9_SHIFT)) & GPIO_PCNS_NSE9_MASK) + +#define GPIO_PCNS_NSE10_MASK (0x400U) +#define GPIO_PCNS_NSE10_SHIFT (10U) +/*! NSE10 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE10_SHIFT)) & GPIO_PCNS_NSE10_MASK) + +#define GPIO_PCNS_NSE11_MASK (0x800U) +#define GPIO_PCNS_NSE11_SHIFT (11U) +/*! NSE11 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE11_SHIFT)) & GPIO_PCNS_NSE11_MASK) + +#define GPIO_PCNS_NSE12_MASK (0x1000U) +#define GPIO_PCNS_NSE12_SHIFT (12U) +/*! NSE12 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE12_SHIFT)) & GPIO_PCNS_NSE12_MASK) + +#define GPIO_PCNS_NSE13_MASK (0x2000U) +#define GPIO_PCNS_NSE13_SHIFT (13U) +/*! NSE13 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE13_SHIFT)) & GPIO_PCNS_NSE13_MASK) + +#define GPIO_PCNS_NSE14_MASK (0x4000U) +#define GPIO_PCNS_NSE14_SHIFT (14U) +/*! NSE14 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE14_SHIFT)) & GPIO_PCNS_NSE14_MASK) + +#define GPIO_PCNS_NSE15_MASK (0x8000U) +#define GPIO_PCNS_NSE15_SHIFT (15U) +/*! NSE15 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE15_SHIFT)) & GPIO_PCNS_NSE15_MASK) + +#define GPIO_PCNS_NSE16_MASK (0x10000U) +#define GPIO_PCNS_NSE16_SHIFT (16U) +/*! NSE16 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE16_SHIFT)) & GPIO_PCNS_NSE16_MASK) + +#define GPIO_PCNS_NSE17_MASK (0x20000U) +#define GPIO_PCNS_NSE17_SHIFT (17U) +/*! NSE17 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE17_SHIFT)) & GPIO_PCNS_NSE17_MASK) + +#define GPIO_PCNS_NSE18_MASK (0x40000U) +#define GPIO_PCNS_NSE18_SHIFT (18U) +/*! NSE18 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE18_SHIFT)) & GPIO_PCNS_NSE18_MASK) + +#define GPIO_PCNS_NSE19_MASK (0x80000U) +#define GPIO_PCNS_NSE19_SHIFT (19U) +/*! NSE19 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE19_SHIFT)) & GPIO_PCNS_NSE19_MASK) + +#define GPIO_PCNS_NSE20_MASK (0x100000U) +#define GPIO_PCNS_NSE20_SHIFT (20U) +/*! NSE20 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE20_SHIFT)) & GPIO_PCNS_NSE20_MASK) + +#define GPIO_PCNS_NSE21_MASK (0x200000U) +#define GPIO_PCNS_NSE21_SHIFT (21U) +/*! NSE21 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE21_SHIFT)) & GPIO_PCNS_NSE21_MASK) + +#define GPIO_PCNS_NSE22_MASK (0x400000U) +#define GPIO_PCNS_NSE22_SHIFT (22U) +/*! NSE22 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE22_SHIFT)) & GPIO_PCNS_NSE22_MASK) + +#define GPIO_PCNS_NSE23_MASK (0x800000U) +#define GPIO_PCNS_NSE23_SHIFT (23U) +/*! NSE23 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE23_SHIFT)) & GPIO_PCNS_NSE23_MASK) + +#define GPIO_PCNS_NSE24_MASK (0x1000000U) +#define GPIO_PCNS_NSE24_SHIFT (24U) +/*! NSE24 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE24_SHIFT)) & GPIO_PCNS_NSE24_MASK) + +#define GPIO_PCNS_NSE25_MASK (0x2000000U) +#define GPIO_PCNS_NSE25_SHIFT (25U) +/*! NSE25 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE25_SHIFT)) & GPIO_PCNS_NSE25_MASK) + +#define GPIO_PCNS_NSE26_MASK (0x4000000U) +#define GPIO_PCNS_NSE26_SHIFT (26U) +/*! NSE26 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE26_SHIFT)) & GPIO_PCNS_NSE26_MASK) + +#define GPIO_PCNS_NSE27_MASK (0x8000000U) +#define GPIO_PCNS_NSE27_SHIFT (27U) +/*! NSE27 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE27_SHIFT)) & GPIO_PCNS_NSE27_MASK) + +#define GPIO_PCNS_NSE28_MASK (0x10000000U) +#define GPIO_PCNS_NSE28_SHIFT (28U) +/*! NSE28 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE28_SHIFT)) & GPIO_PCNS_NSE28_MASK) + +#define GPIO_PCNS_NSE29_MASK (0x20000000U) +#define GPIO_PCNS_NSE29_SHIFT (29U) +/*! NSE29 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE29_SHIFT)) & GPIO_PCNS_NSE29_MASK) + +#define GPIO_PCNS_NSE30_MASK (0x40000000U) +#define GPIO_PCNS_NSE30_SHIFT (30U) +/*! NSE30 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE30_SHIFT)) & GPIO_PCNS_NSE30_MASK) + +#define GPIO_PCNS_NSE31_MASK (0x80000000U) +#define GPIO_PCNS_NSE31_SHIFT (31U) +/*! NSE31 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_PCNS_NSE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNS_NSE31_SHIFT)) & GPIO_PCNS_NSE31_MASK) +/*! @} */ + +/*! @name ICNS - Interrupt Control Nonsecure */ +/*! @{ */ + +#define GPIO_ICNS_NSE0_MASK (0x1U) +#define GPIO_ICNS_NSE0_SHIFT (0U) +/*! NSE0 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_ICNS_NSE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE0_SHIFT)) & GPIO_ICNS_NSE0_MASK) + +#define GPIO_ICNS_NSE1_MASK (0x2U) +#define GPIO_ICNS_NSE1_SHIFT (1U) +/*! NSE1 - Nonsecure Enable + * 0b0..Secure access + * 0b1..Nonsecure access + */ +#define GPIO_ICNS_NSE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNS_NSE1_SHIFT)) & GPIO_ICNS_NSE1_MASK) +/*! @} */ + +/*! @name PCNP - Pin Control Nonprivilege */ +/*! @{ */ + +#define GPIO_PCNP_NPE0_MASK (0x1U) +#define GPIO_PCNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE0_SHIFT)) & GPIO_PCNP_NPE0_MASK) + +#define GPIO_PCNP_NPE1_MASK (0x2U) +#define GPIO_PCNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE1_SHIFT)) & GPIO_PCNP_NPE1_MASK) + +#define GPIO_PCNP_NPE2_MASK (0x4U) +#define GPIO_PCNP_NPE2_SHIFT (2U) +/*! NPE2 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE2_SHIFT)) & GPIO_PCNP_NPE2_MASK) + +#define GPIO_PCNP_NPE3_MASK (0x8U) +#define GPIO_PCNP_NPE3_SHIFT (3U) +/*! NPE3 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE3_SHIFT)) & GPIO_PCNP_NPE3_MASK) + +#define GPIO_PCNP_NPE4_MASK (0x10U) +#define GPIO_PCNP_NPE4_SHIFT (4U) +/*! NPE4 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE4_SHIFT)) & GPIO_PCNP_NPE4_MASK) + +#define GPIO_PCNP_NPE5_MASK (0x20U) +#define GPIO_PCNP_NPE5_SHIFT (5U) +/*! NPE5 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE5_SHIFT)) & GPIO_PCNP_NPE5_MASK) + +#define GPIO_PCNP_NPE6_MASK (0x40U) +#define GPIO_PCNP_NPE6_SHIFT (6U) +/*! NPE6 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE6_SHIFT)) & GPIO_PCNP_NPE6_MASK) + +#define GPIO_PCNP_NPE7_MASK (0x80U) +#define GPIO_PCNP_NPE7_SHIFT (7U) +/*! NPE7 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE7_SHIFT)) & GPIO_PCNP_NPE7_MASK) + +#define GPIO_PCNP_NPE8_MASK (0x100U) +#define GPIO_PCNP_NPE8_SHIFT (8U) +/*! NPE8 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE8_SHIFT)) & GPIO_PCNP_NPE8_MASK) + +#define GPIO_PCNP_NPE9_MASK (0x200U) +#define GPIO_PCNP_NPE9_SHIFT (9U) +/*! NPE9 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE9_SHIFT)) & GPIO_PCNP_NPE9_MASK) + +#define GPIO_PCNP_NPE10_MASK (0x400U) +#define GPIO_PCNP_NPE10_SHIFT (10U) +/*! NPE10 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE10_SHIFT)) & GPIO_PCNP_NPE10_MASK) + +#define GPIO_PCNP_NPE11_MASK (0x800U) +#define GPIO_PCNP_NPE11_SHIFT (11U) +/*! NPE11 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE11_SHIFT)) & GPIO_PCNP_NPE11_MASK) + +#define GPIO_PCNP_NPE12_MASK (0x1000U) +#define GPIO_PCNP_NPE12_SHIFT (12U) +/*! NPE12 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE12_SHIFT)) & GPIO_PCNP_NPE12_MASK) + +#define GPIO_PCNP_NPE13_MASK (0x2000U) +#define GPIO_PCNP_NPE13_SHIFT (13U) +/*! NPE13 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE13_SHIFT)) & GPIO_PCNP_NPE13_MASK) + +#define GPIO_PCNP_NPE14_MASK (0x4000U) +#define GPIO_PCNP_NPE14_SHIFT (14U) +/*! NPE14 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE14_SHIFT)) & GPIO_PCNP_NPE14_MASK) + +#define GPIO_PCNP_NPE15_MASK (0x8000U) +#define GPIO_PCNP_NPE15_SHIFT (15U) +/*! NPE15 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE15_SHIFT)) & GPIO_PCNP_NPE15_MASK) + +#define GPIO_PCNP_NPE16_MASK (0x10000U) +#define GPIO_PCNP_NPE16_SHIFT (16U) +/*! NPE16 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE16_SHIFT)) & GPIO_PCNP_NPE16_MASK) + +#define GPIO_PCNP_NPE17_MASK (0x20000U) +#define GPIO_PCNP_NPE17_SHIFT (17U) +/*! NPE17 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE17_SHIFT)) & GPIO_PCNP_NPE17_MASK) + +#define GPIO_PCNP_NPE18_MASK (0x40000U) +#define GPIO_PCNP_NPE18_SHIFT (18U) +/*! NPE18 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE18_SHIFT)) & GPIO_PCNP_NPE18_MASK) + +#define GPIO_PCNP_NPE19_MASK (0x80000U) +#define GPIO_PCNP_NPE19_SHIFT (19U) +/*! NPE19 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE19_SHIFT)) & GPIO_PCNP_NPE19_MASK) + +#define GPIO_PCNP_NPE20_MASK (0x100000U) +#define GPIO_PCNP_NPE20_SHIFT (20U) +/*! NPE20 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE20_SHIFT)) & GPIO_PCNP_NPE20_MASK) + +#define GPIO_PCNP_NPE21_MASK (0x200000U) +#define GPIO_PCNP_NPE21_SHIFT (21U) +/*! NPE21 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE21_SHIFT)) & GPIO_PCNP_NPE21_MASK) + +#define GPIO_PCNP_NPE22_MASK (0x400000U) +#define GPIO_PCNP_NPE22_SHIFT (22U) +/*! NPE22 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE22_SHIFT)) & GPIO_PCNP_NPE22_MASK) + +#define GPIO_PCNP_NPE23_MASK (0x800000U) +#define GPIO_PCNP_NPE23_SHIFT (23U) +/*! NPE23 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE23_SHIFT)) & GPIO_PCNP_NPE23_MASK) + +#define GPIO_PCNP_NPE24_MASK (0x1000000U) +#define GPIO_PCNP_NPE24_SHIFT (24U) +/*! NPE24 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE24_SHIFT)) & GPIO_PCNP_NPE24_MASK) + +#define GPIO_PCNP_NPE25_MASK (0x2000000U) +#define GPIO_PCNP_NPE25_SHIFT (25U) +/*! NPE25 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE25_SHIFT)) & GPIO_PCNP_NPE25_MASK) + +#define GPIO_PCNP_NPE26_MASK (0x4000000U) +#define GPIO_PCNP_NPE26_SHIFT (26U) +/*! NPE26 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE26_SHIFT)) & GPIO_PCNP_NPE26_MASK) + +#define GPIO_PCNP_NPE27_MASK (0x8000000U) +#define GPIO_PCNP_NPE27_SHIFT (27U) +/*! NPE27 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE27_SHIFT)) & GPIO_PCNP_NPE27_MASK) + +#define GPIO_PCNP_NPE28_MASK (0x10000000U) +#define GPIO_PCNP_NPE28_SHIFT (28U) +/*! NPE28 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE28_SHIFT)) & GPIO_PCNP_NPE28_MASK) + +#define GPIO_PCNP_NPE29_MASK (0x20000000U) +#define GPIO_PCNP_NPE29_SHIFT (29U) +/*! NPE29 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE29_SHIFT)) & GPIO_PCNP_NPE29_MASK) + +#define GPIO_PCNP_NPE30_MASK (0x40000000U) +#define GPIO_PCNP_NPE30_SHIFT (30U) +/*! NPE30 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE30_SHIFT)) & GPIO_PCNP_NPE30_MASK) + +#define GPIO_PCNP_NPE31_MASK (0x80000000U) +#define GPIO_PCNP_NPE31_SHIFT (31U) +/*! NPE31 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_PCNP_NPE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCNP_NPE31_SHIFT)) & GPIO_PCNP_NPE31_MASK) +/*! @} */ + +/*! @name ICNP - Interrupt Control Nonprivilege */ +/*! @{ */ + +#define GPIO_ICNP_NPE0_MASK (0x1U) +#define GPIO_ICNP_NPE0_SHIFT (0U) +/*! NPE0 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_ICNP_NPE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE0_SHIFT)) & GPIO_ICNP_NPE0_MASK) + +#define GPIO_ICNP_NPE1_MASK (0x2U) +#define GPIO_ICNP_NPE1_SHIFT (1U) +/*! NPE1 - Nonprivilege Enable + * 0b0..Privilege access + * 0b1..Nonprivilege access + */ +#define GPIO_ICNP_NPE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICNP_NPE1_SHIFT)) & GPIO_ICNP_NPE1_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define GPIO_PDOR_PDO0_MASK (0x1U) +#define GPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) + +#define GPIO_PDOR_PDO1_MASK (0x2U) +#define GPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) + +#define GPIO_PDOR_PDO2_MASK (0x4U) +#define GPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) + +#define GPIO_PDOR_PDO3_MASK (0x8U) +#define GPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) + +#define GPIO_PDOR_PDO4_MASK (0x10U) +#define GPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) + +#define GPIO_PDOR_PDO5_MASK (0x20U) +#define GPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) + +#define GPIO_PDOR_PDO6_MASK (0x40U) +#define GPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) + +#define GPIO_PDOR_PDO7_MASK (0x80U) +#define GPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) + +#define GPIO_PDOR_PDO8_MASK (0x100U) +#define GPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) + +#define GPIO_PDOR_PDO9_MASK (0x200U) +#define GPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) + +#define GPIO_PDOR_PDO10_MASK (0x400U) +#define GPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) + +#define GPIO_PDOR_PDO11_MASK (0x800U) +#define GPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) + +#define GPIO_PDOR_PDO12_MASK (0x1000U) +#define GPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) + +#define GPIO_PDOR_PDO13_MASK (0x2000U) +#define GPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) + +#define GPIO_PDOR_PDO14_MASK (0x4000U) +#define GPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) + +#define GPIO_PDOR_PDO15_MASK (0x8000U) +#define GPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) + +#define GPIO_PDOR_PDO16_MASK (0x10000U) +#define GPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) + +#define GPIO_PDOR_PDO17_MASK (0x20000U) +#define GPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) + +#define GPIO_PDOR_PDO18_MASK (0x40000U) +#define GPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) + +#define GPIO_PDOR_PDO19_MASK (0x80000U) +#define GPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) + +#define GPIO_PDOR_PDO20_MASK (0x100000U) +#define GPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) + +#define GPIO_PDOR_PDO21_MASK (0x200000U) +#define GPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) + +#define GPIO_PDOR_PDO22_MASK (0x400000U) +#define GPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) + +#define GPIO_PDOR_PDO23_MASK (0x800000U) +#define GPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) + +#define GPIO_PDOR_PDO24_MASK (0x1000000U) +#define GPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) + +#define GPIO_PDOR_PDO25_MASK (0x2000000U) +#define GPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) + +#define GPIO_PDOR_PDO26_MASK (0x4000000U) +#define GPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) + +#define GPIO_PDOR_PDO27_MASK (0x8000000U) +#define GPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) + +#define GPIO_PDOR_PDO28_MASK (0x10000000U) +#define GPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) + +#define GPIO_PDOR_PDO29_MASK (0x20000000U) +#define GPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) + +#define GPIO_PDOR_PDO30_MASK (0x40000000U) +#define GPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) + +#define GPIO_PDOR_PDO31_MASK (0x80000000U) +#define GPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define GPIO_PSOR_PTSO0_MASK (0x1U) +#define GPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) + +#define GPIO_PSOR_PTSO1_MASK (0x2U) +#define GPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) + +#define GPIO_PSOR_PTSO2_MASK (0x4U) +#define GPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) + +#define GPIO_PSOR_PTSO3_MASK (0x8U) +#define GPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) + +#define GPIO_PSOR_PTSO4_MASK (0x10U) +#define GPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) + +#define GPIO_PSOR_PTSO5_MASK (0x20U) +#define GPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) + +#define GPIO_PSOR_PTSO6_MASK (0x40U) +#define GPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) + +#define GPIO_PSOR_PTSO7_MASK (0x80U) +#define GPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) + +#define GPIO_PSOR_PTSO8_MASK (0x100U) +#define GPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) + +#define GPIO_PSOR_PTSO9_MASK (0x200U) +#define GPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) + +#define GPIO_PSOR_PTSO10_MASK (0x400U) +#define GPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) + +#define GPIO_PSOR_PTSO11_MASK (0x800U) +#define GPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) + +#define GPIO_PSOR_PTSO12_MASK (0x1000U) +#define GPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) + +#define GPIO_PSOR_PTSO13_MASK (0x2000U) +#define GPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) + +#define GPIO_PSOR_PTSO14_MASK (0x4000U) +#define GPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) + +#define GPIO_PSOR_PTSO15_MASK (0x8000U) +#define GPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) + +#define GPIO_PSOR_PTSO16_MASK (0x10000U) +#define GPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) + +#define GPIO_PSOR_PTSO17_MASK (0x20000U) +#define GPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) + +#define GPIO_PSOR_PTSO18_MASK (0x40000U) +#define GPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) + +#define GPIO_PSOR_PTSO19_MASK (0x80000U) +#define GPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) + +#define GPIO_PSOR_PTSO20_MASK (0x100000U) +#define GPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) + +#define GPIO_PSOR_PTSO21_MASK (0x200000U) +#define GPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) + +#define GPIO_PSOR_PTSO22_MASK (0x400000U) +#define GPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) + +#define GPIO_PSOR_PTSO23_MASK (0x800000U) +#define GPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) + +#define GPIO_PSOR_PTSO24_MASK (0x1000000U) +#define GPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) + +#define GPIO_PSOR_PTSO25_MASK (0x2000000U) +#define GPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) + +#define GPIO_PSOR_PTSO26_MASK (0x4000000U) +#define GPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) + +#define GPIO_PSOR_PTSO27_MASK (0x8000000U) +#define GPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) + +#define GPIO_PSOR_PTSO28_MASK (0x10000000U) +#define GPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) + +#define GPIO_PSOR_PTSO29_MASK (0x20000000U) +#define GPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) + +#define GPIO_PSOR_PTSO30_MASK (0x40000000U) +#define GPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) + +#define GPIO_PSOR_PTSO31_MASK (0x80000000U) +#define GPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define GPIO_PCOR_PTCO0_MASK (0x1U) +#define GPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) + +#define GPIO_PCOR_PTCO1_MASK (0x2U) +#define GPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) + +#define GPIO_PCOR_PTCO2_MASK (0x4U) +#define GPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) + +#define GPIO_PCOR_PTCO3_MASK (0x8U) +#define GPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) + +#define GPIO_PCOR_PTCO4_MASK (0x10U) +#define GPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) + +#define GPIO_PCOR_PTCO5_MASK (0x20U) +#define GPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) + +#define GPIO_PCOR_PTCO6_MASK (0x40U) +#define GPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) + +#define GPIO_PCOR_PTCO7_MASK (0x80U) +#define GPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) + +#define GPIO_PCOR_PTCO8_MASK (0x100U) +#define GPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) + +#define GPIO_PCOR_PTCO9_MASK (0x200U) +#define GPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) + +#define GPIO_PCOR_PTCO10_MASK (0x400U) +#define GPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) + +#define GPIO_PCOR_PTCO11_MASK (0x800U) +#define GPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) + +#define GPIO_PCOR_PTCO12_MASK (0x1000U) +#define GPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) + +#define GPIO_PCOR_PTCO13_MASK (0x2000U) +#define GPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) + +#define GPIO_PCOR_PTCO14_MASK (0x4000U) +#define GPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) + +#define GPIO_PCOR_PTCO15_MASK (0x8000U) +#define GPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) + +#define GPIO_PCOR_PTCO16_MASK (0x10000U) +#define GPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) + +#define GPIO_PCOR_PTCO17_MASK (0x20000U) +#define GPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) + +#define GPIO_PCOR_PTCO18_MASK (0x40000U) +#define GPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) + +#define GPIO_PCOR_PTCO19_MASK (0x80000U) +#define GPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) + +#define GPIO_PCOR_PTCO20_MASK (0x100000U) +#define GPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) + +#define GPIO_PCOR_PTCO21_MASK (0x200000U) +#define GPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) + +#define GPIO_PCOR_PTCO22_MASK (0x400000U) +#define GPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) + +#define GPIO_PCOR_PTCO23_MASK (0x800000U) +#define GPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) + +#define GPIO_PCOR_PTCO24_MASK (0x1000000U) +#define GPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) + +#define GPIO_PCOR_PTCO25_MASK (0x2000000U) +#define GPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) + +#define GPIO_PCOR_PTCO26_MASK (0x4000000U) +#define GPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) + +#define GPIO_PCOR_PTCO27_MASK (0x8000000U) +#define GPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) + +#define GPIO_PCOR_PTCO28_MASK (0x10000000U) +#define GPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) + +#define GPIO_PCOR_PTCO29_MASK (0x20000000U) +#define GPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) + +#define GPIO_PCOR_PTCO30_MASK (0x40000000U) +#define GPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) + +#define GPIO_PCOR_PTCO31_MASK (0x80000000U) +#define GPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define GPIO_PTOR_PTTO0_MASK (0x1U) +#define GPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) + +#define GPIO_PTOR_PTTO1_MASK (0x2U) +#define GPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) + +#define GPIO_PTOR_PTTO2_MASK (0x4U) +#define GPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) + +#define GPIO_PTOR_PTTO3_MASK (0x8U) +#define GPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) + +#define GPIO_PTOR_PTTO4_MASK (0x10U) +#define GPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) + +#define GPIO_PTOR_PTTO5_MASK (0x20U) +#define GPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) + +#define GPIO_PTOR_PTTO6_MASK (0x40U) +#define GPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) + +#define GPIO_PTOR_PTTO7_MASK (0x80U) +#define GPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) + +#define GPIO_PTOR_PTTO8_MASK (0x100U) +#define GPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) + +#define GPIO_PTOR_PTTO9_MASK (0x200U) +#define GPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) + +#define GPIO_PTOR_PTTO10_MASK (0x400U) +#define GPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) + +#define GPIO_PTOR_PTTO11_MASK (0x800U) +#define GPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) + +#define GPIO_PTOR_PTTO12_MASK (0x1000U) +#define GPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) + +#define GPIO_PTOR_PTTO13_MASK (0x2000U) +#define GPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) + +#define GPIO_PTOR_PTTO14_MASK (0x4000U) +#define GPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) + +#define GPIO_PTOR_PTTO15_MASK (0x8000U) +#define GPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) + +#define GPIO_PTOR_PTTO16_MASK (0x10000U) +#define GPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) + +#define GPIO_PTOR_PTTO17_MASK (0x20000U) +#define GPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) + +#define GPIO_PTOR_PTTO18_MASK (0x40000U) +#define GPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) + +#define GPIO_PTOR_PTTO19_MASK (0x80000U) +#define GPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) + +#define GPIO_PTOR_PTTO20_MASK (0x100000U) +#define GPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) + +#define GPIO_PTOR_PTTO21_MASK (0x200000U) +#define GPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) + +#define GPIO_PTOR_PTTO22_MASK (0x400000U) +#define GPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) + +#define GPIO_PTOR_PTTO23_MASK (0x800000U) +#define GPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) + +#define GPIO_PTOR_PTTO24_MASK (0x1000000U) +#define GPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) + +#define GPIO_PTOR_PTTO25_MASK (0x2000000U) +#define GPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) + +#define GPIO_PTOR_PTTO26_MASK (0x4000000U) +#define GPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) + +#define GPIO_PTOR_PTTO27_MASK (0x8000000U) +#define GPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) + +#define GPIO_PTOR_PTTO28_MASK (0x10000000U) +#define GPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) + +#define GPIO_PTOR_PTTO29_MASK (0x20000000U) +#define GPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) + +#define GPIO_PTOR_PTTO30_MASK (0x40000000U) +#define GPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) + +#define GPIO_PTOR_PTTO31_MASK (0x80000000U) +#define GPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define GPIO_PDIR_PDI0_MASK (0x1U) +#define GPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) + +#define GPIO_PDIR_PDI1_MASK (0x2U) +#define GPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) + +#define GPIO_PDIR_PDI2_MASK (0x4U) +#define GPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) + +#define GPIO_PDIR_PDI3_MASK (0x8U) +#define GPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) + +#define GPIO_PDIR_PDI4_MASK (0x10U) +#define GPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) + +#define GPIO_PDIR_PDI5_MASK (0x20U) +#define GPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) + +#define GPIO_PDIR_PDI6_MASK (0x40U) +#define GPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) + +#define GPIO_PDIR_PDI7_MASK (0x80U) +#define GPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) + +#define GPIO_PDIR_PDI8_MASK (0x100U) +#define GPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) + +#define GPIO_PDIR_PDI9_MASK (0x200U) +#define GPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) + +#define GPIO_PDIR_PDI10_MASK (0x400U) +#define GPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) + +#define GPIO_PDIR_PDI11_MASK (0x800U) +#define GPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) + +#define GPIO_PDIR_PDI12_MASK (0x1000U) +#define GPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) + +#define GPIO_PDIR_PDI13_MASK (0x2000U) +#define GPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) + +#define GPIO_PDIR_PDI14_MASK (0x4000U) +#define GPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) + +#define GPIO_PDIR_PDI15_MASK (0x8000U) +#define GPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) + +#define GPIO_PDIR_PDI16_MASK (0x10000U) +#define GPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) + +#define GPIO_PDIR_PDI17_MASK (0x20000U) +#define GPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) + +#define GPIO_PDIR_PDI18_MASK (0x40000U) +#define GPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) + +#define GPIO_PDIR_PDI19_MASK (0x80000U) +#define GPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) + +#define GPIO_PDIR_PDI20_MASK (0x100000U) +#define GPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) + +#define GPIO_PDIR_PDI21_MASK (0x200000U) +#define GPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) + +#define GPIO_PDIR_PDI22_MASK (0x400000U) +#define GPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) + +#define GPIO_PDIR_PDI23_MASK (0x800000U) +#define GPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) + +#define GPIO_PDIR_PDI24_MASK (0x1000000U) +#define GPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) + +#define GPIO_PDIR_PDI25_MASK (0x2000000U) +#define GPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) + +#define GPIO_PDIR_PDI26_MASK (0x4000000U) +#define GPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) + +#define GPIO_PDIR_PDI27_MASK (0x8000000U) +#define GPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) + +#define GPIO_PDIR_PDI28_MASK (0x10000000U) +#define GPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) + +#define GPIO_PDIR_PDI29_MASK (0x20000000U) +#define GPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) + +#define GPIO_PDIR_PDI30_MASK (0x40000000U) +#define GPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) + +#define GPIO_PDIR_PDI31_MASK (0x80000000U) +#define GPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define GPIO_PDDR_PDD0_MASK (0x1U) +#define GPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) + +#define GPIO_PDDR_PDD1_MASK (0x2U) +#define GPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) + +#define GPIO_PDDR_PDD2_MASK (0x4U) +#define GPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) + +#define GPIO_PDDR_PDD3_MASK (0x8U) +#define GPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) + +#define GPIO_PDDR_PDD4_MASK (0x10U) +#define GPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) + +#define GPIO_PDDR_PDD5_MASK (0x20U) +#define GPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) + +#define GPIO_PDDR_PDD6_MASK (0x40U) +#define GPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) + +#define GPIO_PDDR_PDD7_MASK (0x80U) +#define GPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) + +#define GPIO_PDDR_PDD8_MASK (0x100U) +#define GPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) + +#define GPIO_PDDR_PDD9_MASK (0x200U) +#define GPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) + +#define GPIO_PDDR_PDD10_MASK (0x400U) +#define GPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) + +#define GPIO_PDDR_PDD11_MASK (0x800U) +#define GPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) + +#define GPIO_PDDR_PDD12_MASK (0x1000U) +#define GPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) + +#define GPIO_PDDR_PDD13_MASK (0x2000U) +#define GPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) + +#define GPIO_PDDR_PDD14_MASK (0x4000U) +#define GPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) + +#define GPIO_PDDR_PDD15_MASK (0x8000U) +#define GPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) + +#define GPIO_PDDR_PDD16_MASK (0x10000U) +#define GPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) + +#define GPIO_PDDR_PDD17_MASK (0x20000U) +#define GPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) + +#define GPIO_PDDR_PDD18_MASK (0x40000U) +#define GPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) + +#define GPIO_PDDR_PDD19_MASK (0x80000U) +#define GPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) + +#define GPIO_PDDR_PDD20_MASK (0x100000U) +#define GPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) + +#define GPIO_PDDR_PDD21_MASK (0x200000U) +#define GPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) + +#define GPIO_PDDR_PDD22_MASK (0x400000U) +#define GPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) + +#define GPIO_PDDR_PDD23_MASK (0x800000U) +#define GPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) + +#define GPIO_PDDR_PDD24_MASK (0x1000000U) +#define GPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) + +#define GPIO_PDDR_PDD25_MASK (0x2000000U) +#define GPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) + +#define GPIO_PDDR_PDD26_MASK (0x4000000U) +#define GPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) + +#define GPIO_PDDR_PDD27_MASK (0x8000000U) +#define GPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) + +#define GPIO_PDDR_PDD28_MASK (0x10000000U) +#define GPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) + +#define GPIO_PDDR_PDD29_MASK (0x20000000U) +#define GPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) + +#define GPIO_PDDR_PDD30_MASK (0x40000000U) +#define GPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) + +#define GPIO_PDDR_PDD31_MASK (0x80000000U) +#define GPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define GPIO_PIDR_PID0_MASK (0x1U) +#define GPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) + +#define GPIO_PIDR_PID1_MASK (0x2U) +#define GPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) + +#define GPIO_PIDR_PID2_MASK (0x4U) +#define GPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) + +#define GPIO_PIDR_PID3_MASK (0x8U) +#define GPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) + +#define GPIO_PIDR_PID4_MASK (0x10U) +#define GPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) + +#define GPIO_PIDR_PID5_MASK (0x20U) +#define GPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) + +#define GPIO_PIDR_PID6_MASK (0x40U) +#define GPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) + +#define GPIO_PIDR_PID7_MASK (0x80U) +#define GPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) + +#define GPIO_PIDR_PID8_MASK (0x100U) +#define GPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) + +#define GPIO_PIDR_PID9_MASK (0x200U) +#define GPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) + +#define GPIO_PIDR_PID10_MASK (0x400U) +#define GPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) + +#define GPIO_PIDR_PID11_MASK (0x800U) +#define GPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) + +#define GPIO_PIDR_PID12_MASK (0x1000U) +#define GPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) + +#define GPIO_PIDR_PID13_MASK (0x2000U) +#define GPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) + +#define GPIO_PIDR_PID14_MASK (0x4000U) +#define GPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) + +#define GPIO_PIDR_PID15_MASK (0x8000U) +#define GPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) + +#define GPIO_PIDR_PID16_MASK (0x10000U) +#define GPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) + +#define GPIO_PIDR_PID17_MASK (0x20000U) +#define GPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) + +#define GPIO_PIDR_PID18_MASK (0x40000U) +#define GPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) + +#define GPIO_PIDR_PID19_MASK (0x80000U) +#define GPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) + +#define GPIO_PIDR_PID20_MASK (0x100000U) +#define GPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) + +#define GPIO_PIDR_PID21_MASK (0x200000U) +#define GPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) + +#define GPIO_PIDR_PID22_MASK (0x400000U) +#define GPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) + +#define GPIO_PIDR_PID23_MASK (0x800000U) +#define GPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) + +#define GPIO_PIDR_PID24_MASK (0x1000000U) +#define GPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) + +#define GPIO_PIDR_PID25_MASK (0x2000000U) +#define GPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) + +#define GPIO_PIDR_PID26_MASK (0x4000000U) +#define GPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) + +#define GPIO_PIDR_PID27_MASK (0x8000000U) +#define GPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) + +#define GPIO_PIDR_PID28_MASK (0x10000000U) +#define GPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) + +#define GPIO_PIDR_PID29_MASK (0x20000000U) +#define GPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) + +#define GPIO_PIDR_PID30_MASK (0x40000000U) +#define GPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) + +#define GPIO_PIDR_PID31_MASK (0x80000000U) +#define GPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define GPIO_PDR_PD_MASK (0x1U) +#define GPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) +/*! @} */ + +/* The count of GPIO_PDR */ +#define GPIO_PDR_COUNT (32U) + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define GPIO_ICR_IRQC_MASK (0xF0000U) +#define GPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved + */ +#define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) + +#define GPIO_ICR_IRQS_MASK (0x100000U) +#define GPIO_ICR_IRQS_SHIFT (20U) +/*! IRQS - Interrupt Select + * 0b0..Interrupt, trigger output, or DMA request 0 + * 0b1..Interrupt, trigger output, or DMA request 1 + */ +#define GPIO_ICR_IRQS(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQS_SHIFT)) & GPIO_ICR_IRQS_MASK) + +#define GPIO_ICR_LK_MASK (0x800000U) +#define GPIO_ICR_LK_SHIFT (23U) +/*! LK - Lock + * 0b0..Lock + * 0b1..Do not lock + */ +#define GPIO_ICR_LK(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_LK_SHIFT)) & GPIO_ICR_LK_MASK) + +#define GPIO_ICR_ISF_MASK (0x1000000U) +#define GPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) +/*! @} */ + +/* The count of GPIO_ICR */ +#define GPIO_ICR_COUNT (32U) + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define GPIO_GICLR_GIWE0_MASK (0x1U) +#define GPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) + +#define GPIO_GICLR_GIWE1_MASK (0x2U) +#define GPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) + +#define GPIO_GICLR_GIWE2_MASK (0x4U) +#define GPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) + +#define GPIO_GICLR_GIWE3_MASK (0x8U) +#define GPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) + +#define GPIO_GICLR_GIWE4_MASK (0x10U) +#define GPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) + +#define GPIO_GICLR_GIWE5_MASK (0x20U) +#define GPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) + +#define GPIO_GICLR_GIWE6_MASK (0x40U) +#define GPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) + +#define GPIO_GICLR_GIWE7_MASK (0x80U) +#define GPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) + +#define GPIO_GICLR_GIWE8_MASK (0x100U) +#define GPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) + +#define GPIO_GICLR_GIWE9_MASK (0x200U) +#define GPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) + +#define GPIO_GICLR_GIWE10_MASK (0x400U) +#define GPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) + +#define GPIO_GICLR_GIWE11_MASK (0x800U) +#define GPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) + +#define GPIO_GICLR_GIWE12_MASK (0x1000U) +#define GPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) + +#define GPIO_GICLR_GIWE13_MASK (0x2000U) +#define GPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) + +#define GPIO_GICLR_GIWE14_MASK (0x4000U) +#define GPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) + +#define GPIO_GICLR_GIWE15_MASK (0x8000U) +#define GPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) + +#define GPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define GPIO_GICHR_GIWE16_MASK (0x1U) +#define GPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) + +#define GPIO_GICHR_GIWE17_MASK (0x2U) +#define GPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) + +#define GPIO_GICHR_GIWE18_MASK (0x4U) +#define GPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) + +#define GPIO_GICHR_GIWE19_MASK (0x8U) +#define GPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) + +#define GPIO_GICHR_GIWE20_MASK (0x10U) +#define GPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) + +#define GPIO_GICHR_GIWE21_MASK (0x20U) +#define GPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) + +#define GPIO_GICHR_GIWE22_MASK (0x40U) +#define GPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) + +#define GPIO_GICHR_GIWE23_MASK (0x80U) +#define GPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) + +#define GPIO_GICHR_GIWE24_MASK (0x100U) +#define GPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) + +#define GPIO_GICHR_GIWE25_MASK (0x200U) +#define GPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) + +#define GPIO_GICHR_GIWE26_MASK (0x400U) +#define GPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) + +#define GPIO_GICHR_GIWE27_MASK (0x800U) +#define GPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) + +#define GPIO_GICHR_GIWE28_MASK (0x1000U) +#define GPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) + +#define GPIO_GICHR_GIWE29_MASK (0x2000U) +#define GPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) + +#define GPIO_GICHR_GIWE30_MASK (0x4000U) +#define GPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) + +#define GPIO_GICHR_GIWE31_MASK (0x8000U) +#define GPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) + +#define GPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define GPIO_ISFR_ISF0_MASK (0x1U) +#define GPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) + +#define GPIO_ISFR_ISF1_MASK (0x2U) +#define GPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) + +#define GPIO_ISFR_ISF2_MASK (0x4U) +#define GPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) + +#define GPIO_ISFR_ISF3_MASK (0x8U) +#define GPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) + +#define GPIO_ISFR_ISF4_MASK (0x10U) +#define GPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) + +#define GPIO_ISFR_ISF5_MASK (0x20U) +#define GPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) + +#define GPIO_ISFR_ISF6_MASK (0x40U) +#define GPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) + +#define GPIO_ISFR_ISF7_MASK (0x80U) +#define GPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) + +#define GPIO_ISFR_ISF8_MASK (0x100U) +#define GPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) + +#define GPIO_ISFR_ISF9_MASK (0x200U) +#define GPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) + +#define GPIO_ISFR_ISF10_MASK (0x400U) +#define GPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) + +#define GPIO_ISFR_ISF11_MASK (0x800U) +#define GPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) + +#define GPIO_ISFR_ISF12_MASK (0x1000U) +#define GPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) + +#define GPIO_ISFR_ISF13_MASK (0x2000U) +#define GPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) + +#define GPIO_ISFR_ISF14_MASK (0x4000U) +#define GPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) + +#define GPIO_ISFR_ISF15_MASK (0x8000U) +#define GPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) + +#define GPIO_ISFR_ISF16_MASK (0x10000U) +#define GPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) + +#define GPIO_ISFR_ISF17_MASK (0x20000U) +#define GPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) + +#define GPIO_ISFR_ISF18_MASK (0x40000U) +#define GPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) + +#define GPIO_ISFR_ISF19_MASK (0x80000U) +#define GPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) + +#define GPIO_ISFR_ISF20_MASK (0x100000U) +#define GPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) + +#define GPIO_ISFR_ISF21_MASK (0x200000U) +#define GPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) + +#define GPIO_ISFR_ISF22_MASK (0x400000U) +#define GPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) + +#define GPIO_ISFR_ISF23_MASK (0x800000U) +#define GPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) + +#define GPIO_ISFR_ISF24_MASK (0x1000000U) +#define GPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) + +#define GPIO_ISFR_ISF25_MASK (0x2000000U) +#define GPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) + +#define GPIO_ISFR_ISF26_MASK (0x4000000U) +#define GPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) + +#define GPIO_ISFR_ISF27_MASK (0x8000000U) +#define GPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) + +#define GPIO_ISFR_ISF28_MASK (0x10000000U) +#define GPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) + +#define GPIO_ISFR_ISF29_MASK (0x20000000U) +#define GPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) + +#define GPIO_ISFR_ISF30_MASK (0x40000000U) +#define GPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) + +#define GPIO_ISFR_ISF31_MASK (0x80000000U) +#define GPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) +/*! @} */ + +/* The count of GPIO_ISFR */ +#define GPIO_ISFR_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x50096000u) + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE_NS (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0 base pointer */ + #define GPIO0_NS ((GPIO_Type *)GPIO0_BASE_NS) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x50097000u) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE_NS (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1_NS ((GPIO_Type *)GPIO0_ALIAS1_BASE_NS) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x50098000u) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE_NS (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1 base pointer */ + #define GPIO1_NS ((GPIO_Type *)GPIO1_BASE_NS) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x50099000u) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE_NS (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1_NS ((GPIO_Type *)GPIO1_ALIAS1_BASE_NS) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x5009A000u) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE_NS (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2 base pointer */ + #define GPIO2_NS ((GPIO_Type *)GPIO2_BASE_NS) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x5009B000u) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE_NS (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1_NS ((GPIO_Type *)GPIO2_ALIAS1_BASE_NS) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x5009C000u) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE_NS (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3 base pointer */ + #define GPIO3_NS ((GPIO_Type *)GPIO3_BASE_NS) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x5009D000u) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE_NS (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1_NS ((GPIO_Type *)GPIO3_ALIAS1_BASE_NS) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x5009E000u) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE_NS (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4 base pointer */ + #define GPIO4_NS ((GPIO_Type *)GPIO4_BASE_NS) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x5009F000u) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE_NS (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1_NS ((GPIO_Type *)GPIO4_ALIAS1_BASE_NS) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x50040000u) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE_NS (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5 base pointer */ + #define GPIO5_NS ((GPIO_Type *)GPIO5_BASE_NS) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x50041000u) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE_NS (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1_NS ((GPIO_Type *)GPIO5_ALIAS1_BASE_NS) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS_NS { GPIO0_BASE_NS, GPIO1_BASE_NS, GPIO2_BASE_NS, GPIO3_BASE_NS, GPIO4_BASE_NS, GPIO5_BASE_NS } + #define GPIO_ALIAS1_BASE_ADDRS_NS { GPIO0_ALIAS1_BASE_NS, GPIO1_ALIAS1_BASE_NS, GPIO2_ALIAS1_BASE_NS, GPIO3_ALIAS1_BASE_NS, GPIO4_ALIAS1_BASE_NS, GPIO5_ALIAS1_BASE_NS } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS_NS { GPIO0_NS, GPIO1_NS, GPIO2_NS, GPIO3_NS, GPIO4_NS, GPIO5_NS } + #define GPIO_ALIAS1_BASE_PTRS_NS { GPIO0_ALIAS1_NS, GPIO1_ALIAS1_NS, GPIO2_ALIAS1_NS, GPIO3_ALIAS1_NS, GPIO4_ALIAS1_NS, GPIO5_ALIAS1_NS } +#else + /** Peripheral GPIO0 base address */ + #define GPIO0_BASE (0x40096000u) + /** Peripheral GPIO0 base pointer */ + #define GPIO0 ((GPIO_Type *)GPIO0_BASE) + /** Peripheral GPIO0_ALIAS1 base address */ + #define GPIO0_ALIAS1_BASE (0x40097000u) + /** Peripheral GPIO0_ALIAS1 base pointer */ + #define GPIO0_ALIAS1 ((GPIO_Type *)GPIO0_ALIAS1_BASE) + /** Peripheral GPIO1 base address */ + #define GPIO1_BASE (0x40098000u) + /** Peripheral GPIO1 base pointer */ + #define GPIO1 ((GPIO_Type *)GPIO1_BASE) + /** Peripheral GPIO1_ALIAS1 base address */ + #define GPIO1_ALIAS1_BASE (0x40099000u) + /** Peripheral GPIO1_ALIAS1 base pointer */ + #define GPIO1_ALIAS1 ((GPIO_Type *)GPIO1_ALIAS1_BASE) + /** Peripheral GPIO2 base address */ + #define GPIO2_BASE (0x4009A000u) + /** Peripheral GPIO2 base pointer */ + #define GPIO2 ((GPIO_Type *)GPIO2_BASE) + /** Peripheral GPIO2_ALIAS1 base address */ + #define GPIO2_ALIAS1_BASE (0x4009B000u) + /** Peripheral GPIO2_ALIAS1 base pointer */ + #define GPIO2_ALIAS1 ((GPIO_Type *)GPIO2_ALIAS1_BASE) + /** Peripheral GPIO3 base address */ + #define GPIO3_BASE (0x4009C000u) + /** Peripheral GPIO3 base pointer */ + #define GPIO3 ((GPIO_Type *)GPIO3_BASE) + /** Peripheral GPIO3_ALIAS1 base address */ + #define GPIO3_ALIAS1_BASE (0x4009D000u) + /** Peripheral GPIO3_ALIAS1 base pointer */ + #define GPIO3_ALIAS1 ((GPIO_Type *)GPIO3_ALIAS1_BASE) + /** Peripheral GPIO4 base address */ + #define GPIO4_BASE (0x4009E000u) + /** Peripheral GPIO4 base pointer */ + #define GPIO4 ((GPIO_Type *)GPIO4_BASE) + /** Peripheral GPIO4_ALIAS1 base address */ + #define GPIO4_ALIAS1_BASE (0x4009F000u) + /** Peripheral GPIO4_ALIAS1 base pointer */ + #define GPIO4_ALIAS1 ((GPIO_Type *)GPIO4_ALIAS1_BASE) + /** Peripheral GPIO5 base address */ + #define GPIO5_BASE (0x40040000u) + /** Peripheral GPIO5 base pointer */ + #define GPIO5 ((GPIO_Type *)GPIO5_BASE) + /** Peripheral GPIO5_ALIAS1 base address */ + #define GPIO5_ALIAS1_BASE (0x40041000u) + /** Peripheral GPIO5_ALIAS1 base pointer */ + #define GPIO5_ALIAS1 ((GPIO_Type *)GPIO5_ALIAS1_BASE) + /** Array initializer of GPIO peripheral base addresses */ + #define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } + #define GPIO_ALIAS1_BASE_ADDRS { GPIO0_ALIAS1_BASE, GPIO1_ALIAS1_BASE, GPIO2_ALIAS1_BASE, GPIO3_ALIAS1_BASE, GPIO4_ALIAS1_BASE, GPIO5_ALIAS1_BASE } + /** Array initializer of GPIO peripheral base pointers */ + #define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } + #define GPIO_ALIAS1_BASE_PTRS { GPIO0_ALIAS1, GPIO1_ALIAS1, GPIO2_ALIAS1, GPIO3_ALIAS1, GPIO4_ALIAS1, GPIO5_ALIAS1 } +#endif +/* Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS {GPIO00_IRQn, GPIO10_IRQn, GPIO20_IRQn, GPIO30_IRQn,GPIO40_IRQn,GPIO50_IRQn} +#define GPIO_IRQS_1 {GPIO01_IRQn, GPIO11_IRQn, GPIO21_IRQn, GPIO31_IRQn,GPIO41_IRQn,GPIO51_IRQn} + + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ + __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ + __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ + __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ + __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ + __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ + __O uint32_t TDR[2]; /**< Transmit Data, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[24]; + __I uint32_t TFR[2]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ + __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ + __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ + __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ + __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ + __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ + __I uint32_t RDR[2]; /**< Receive Data, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[24]; + __I uint32_t RFR[2]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[24]; + __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ + uint8_t RESERVED_5[28]; + __IO uint32_t MCR; /**< MCLK Control, offset: 0x100 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) + +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) + +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +/*! DATALINE - Number of Data Lines */ +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) + +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +/*! FIFO - FIFO Size */ +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) + +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +/*! FRAME - Frame Size */ +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - Transmit Control */ +/*! @{ */ + +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) + +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) + +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) + +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) + +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) + +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) + +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) + +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) + +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) + +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) + +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) + +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) + +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) + +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) + +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) + +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) + +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) + +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable (or transmitter has been disabled and has not yet reached the end of the frame) + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - Transmit Configuration 1 */ +/*! @{ */ + +#define I2S_TCR1_TFW_MASK (0x7U) +#define I2S_TCR1_TFW_SHIFT (0U) +/*! TFW - Transmit FIFO Watermark + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(TFW +1) + * 0b111..8 + */ +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - Transmit Configuration 2 */ +/*! @{ */ + +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) + +#define I2S_TCR2_BYP_MASK (0x800000U) +#define I2S_TCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) + +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generate externally in Target mode + * 0b1..Generate internally in Controller mode + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) + +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) + +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) + +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) + +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) + +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode + * 0b01..Synchronous with receiver + * 0b10..Synchronous with another SAI transmitter + * 0b11..Synchronous with another SAI receiver + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - Transmit Configuration 3 */ +/*! @{ */ + +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration */ +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) + +#define I2S_TCR3_TCE_MASK (0x30000U) +#define I2S_TCR3_TCE_SHIFT (16U) +/*! TCE - Transmit Channel Enable */ +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +#define I2S_TCR3_CFR_MASK (0x3000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - Transmit Configuration 4 */ +/*! @{ */ + +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) + +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) + +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated after the FIFO warning flag is cleared + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) + +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) + +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) + +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode + * 0b1..Output mode + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) + +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width */ +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) + +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size */ +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable FIFO packing + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) + +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO reads (from transmit shift registers) + * 0b10..Enable on FIFO writes (by software) + * 0b11..Enable on FIFO reads (from transmit shift registers) and writes (by software) + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) + +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..Continue from the start of the next frame + * 0b1..Continue from the same word that caused the FIFO error + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - Transmit Configuration 5 */ +/*! @{ */ + +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT + * 0b11111..31 + */ +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) + +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) + +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +/*! TDR - Transmit Data */ +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (2U) + +/*! @name TFR - Transmit FIFO */ +/*! @{ */ + +#define I2S_TFR_RFP_MASK (0xFU) +#define I2S_TFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) + +#define I2S_TFR_WFP_MASK (0xF0000U) +#define I2S_TFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be written + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (2U) + +/*! @name TMR - Transmit Mask */ +/*! @{ */ + +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - Receive Control */ +/*! @{ */ + +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) + +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) + +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) + +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) + +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) + +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) + +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) + +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Watermark not reached + * 0b1..Watermark reached + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) + +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..Not full + * 0b1..Full + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) + +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Receive overflow detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) + +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) + +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) + +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) + +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect + * 0b1..Reset + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) + +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) + +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Disable after completing the current frame + * 0b1..Enable + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) + +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) + +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable (or receiver disabled and not yet reached end of frame) + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - Receive Configuration 1 */ +/*! @{ */ + +#define I2S_RCR1_RFW_MASK (0x7U) +#define I2S_RCR1_RFW_SHIFT (0U) +/*! RFW - Receive FIFO Watermark + * 0b000..1 + * 0b001..2 + * 0b010-0b110..(RFW value + 1) + * 0b111..8 + */ +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - Receive Configuration 2 */ +/*! @{ */ + +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +/*! DIV - Bit Clock Divide */ +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) + +#define I2S_RCR2_BYP_MASK (0x800000U) +#define I2S_RCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) + +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) + +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) + +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus clock + * 0b01..Controller clock (MCLK) option 1 + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) + +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) + +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source + * 0b1..Swap the bit clock source + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) + +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode + * 0b01..Synchronous with transmitter + * 0b10..Synchronous with another SAI receiver + * 0b11..Synchronous with another SAI transmitter + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - Receive Configuration 3 */ +/*! @{ */ + +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +/*! WDFL - Word Flag Configuration + * 0b00000..Word 1 + * 0b00001..Word 2 + * 0b00010-0b11110..Word (WDFL value + 1) + * 0b11111..Word 32 + */ +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) + +#define I2S_RCR3_RCE_MASK (0x30000U) +#define I2S_RCR3_RCE_SHIFT (16U) +/*! RCE - Receive Channel Enable */ +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +#define I2S_RCR3_CFR_MASK (0x3000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +/*! CFR - Channel FIFO Reset */ +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - Receive Configuration 4 */ +/*! @{ */ + +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Generated externally in Target mode + * 0b1..Generated internally in Controller mode + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) + +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) + +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On-Demand Mode + * 0b0..Generated continuously + * 0b1..Generated when the FIFO warning flag is 0 + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) + +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..First bit of the frame + * 0b1..One bit before the first bit of the frame + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) + +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) + +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +/*! SYWD - Sync Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(SYWD value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) + +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +/*! FRSZ - Frame Size + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(FRSZ value + 1) + * 0b11111..32 + */ +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..Disable + * 0b01..Reserved + * 0b10..Enable 8-bit FIFO packing + * 0b11..Enable 16-bit FIFO packing + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) + +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..Disable + * 0b01..Enable on FIFO writes (from receive shift registers) + * 0b10..Enable on FIFO reads (by software) + * 0b11..Enable on FIFO writes (from receive shift registers) and reads (by software) + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) + +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..From the start of the next frame after the FIFO error flag is cleared + * 0b1..From the same word that caused the FIFO error to become 1 after the FIFO warning flag is cleared + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - Receive Configuration 5 */ +/*! @{ */ + +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +/*! FBT - First Bit Shifted + * 0b00000..0 + * 0b00001-0b11110..FBT value + * 0b11111..31 + */ +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) + +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +/*! W0W - Word 0 Width + * 0b00000..1 + * 0b00001..2 + * 0b00010-0b11110..(W0W value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) + +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +/*! WNW - Word N Width + * 0b00111..8 + * 0b01000..9 + * 0b01001-0b11110..(WNW value + 1) + * 0b11111..32 + */ +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +/*! RDR - Receive Data */ +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (2U) + +/*! @name RFR - Receive FIFO */ +/*! @{ */ + +#define I2S_RFR_RFP_MASK (0xFU) +#define I2S_RFR_RFP_SHIFT (0U) +/*! RFP - Read FIFO Pointer */ +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) + +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Read Channel Pointer + * 0b0..No effect + * 0b1..Next FIFO to be read + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) + +#define I2S_RFR_WFP_MASK (0xF0000U) +#define I2S_RFR_WFP_SHIFT (16U) +/*! WFP - Write FIFO Pointer */ +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (2U) + +/*! @name RMR - Receive Mask */ +/*! @{ */ + +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Enable + * 0b00000000000000000000000000000001..Mask + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + +/*! @name MCR - MCLK Control */ +/*! @{ */ + +#define I2S_MCR_DIV_MASK (0xFFU) +#define I2S_MCR_DIV_SHIFT (0U) +/*! DIV - MCLK Post Divide */ +#define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK) + +#define I2S_MCR_DIVEN_MASK (0x800000U) +#define I2S_MCR_DIVEN_SHIFT (23U) +/*! DIVEN - MCLK Post Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK) + +#define I2S_MCR_MSEL_MASK (0x3000000U) +#define I2S_MCR_MSEL_SHIFT (24U) +/*! MSEL - MCLK Select + * 0b00..Controller clock (MCLK) option 1 + * 0b01..Reserved + * 0b10..Controller clock (MCLK) option 2 + * 0b11..Controller clock (MCLK) option 3 + */ +#define I2S_MCR_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MSEL_SHIFT)) & I2S_MCR_MSEL_MASK) + +#define I2S_MCR_MOE_MASK (0x40000000U) +#define I2S_MCR_MOE_SHIFT (30U) +/*! MOE - MCLK Output Enable + * 0b0..Input + * 0b1..Output + */ +#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x50106000u) + /** Peripheral SAI0 base address */ + #define SAI0_BASE_NS (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI0 base pointer */ + #define SAI0_NS ((I2S_Type *)SAI0_BASE_NS) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x50107000u) + /** Peripheral SAI1 base address */ + #define SAI1_BASE_NS (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Peripheral SAI1 base pointer */ + #define SAI1_NS ((I2S_Type *)SAI1_BASE_NS) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS_NS { SAI0_BASE_NS, SAI1_BASE_NS } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS_NS { SAI0_NS, SAI1_NS } +#else + /** Peripheral SAI0 base address */ + #define SAI0_BASE (0x40106000u) + /** Peripheral SAI0 base pointer */ + #define SAI0 ((I2S_Type *)SAI0_BASE) + /** Peripheral SAI1 base address */ + #define SAI1_BASE (0x40107000u) + /** Peripheral SAI1 base pointer */ + #define SAI1 ((I2S_Type *)SAI1_BASE) + /** Array initializer of I2S peripheral base addresses */ + #define I2S_BASE_ADDRS { SAI0_BASE, SAI1_BASE } + /** Array initializer of I2S peripheral base pointers */ + #define I2S_BASE_PTRS { SAI0, SAI1 } +#endif +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { SAI0_IRQn, SAI1_IRQn } +#define I2S_TX_IRQS { SAI0_IRQn, SAI1_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ + uint8_t RESERVED_2[8]; + union { /* offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ + }; + uint8_t RESERVED_3[4]; + __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ + __IO uint32_t SDYNADDR; /**< Target Dynamic Address, offset: 0x64 */ + __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ + __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ + __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_5[4]; + __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ + union { /* offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ + __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ + }; + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_6[4]; + __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_7[52]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + uint8_t RESERVED_8[32]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_9[3764]; + __I uint32_t SID; /**< Target Module ID, offset: 0xFFC */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Controller Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Controller Enable + * 0b00..CONTROLLER_OFF + * 0b01..CONTROLLER_ON + * 0b10..CONTROLLER_CAPABLE + * 0b11..I2C_CONTROLLER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + * 0b1..Disabled, if configured + * 0b0..Enabled + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..None + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open Drain Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-Pull Baud Rate */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull Low */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open Drain Baud Rate */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open Drain High Push-Pull + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C Baud Rate */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Target Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Target Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not Acknowledge + * 0b1..Always enable NACK mode (works normally) + * 0b0..Always disable NACK mode + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match Start or Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b1..Ignore TE0 or TE1 errors + * 0b0..Do not ignore TE0 or TE1 errors + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_HDROK_MASK (0x10U) +#define I3C_SCONFIG_HDROK_SHIFT (4U) +/*! HDROK - HDR OK + * 0b1..Enable HDR OK + * 0b0..Disable HDR OK + */ +#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus Available Match */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static Address */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Target Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not Stop + * 0b1..Busy + * 0b0..In STOP condition + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status Message + * 0b1..Busy + * 0b0..Idle + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + * 0b1..Handled automatically + * 0b0..No CCC message handled + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status Request Read + * 0b1..SDR read from this target or an IBI is being pushed out + * 0b0..Not an SDR read + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status Request Write + * 0b1..SDR write data from the controller, but not in ENTDAA mode + * 0b0..Not an SDR write + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + * 0b1..In ENTDAA mode + * 0b0..Not in ENTDAA mode + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + * 0b1..I3C bus in HDR-DDR mode + * 0b0..I3C bus not in HDR-DDR mode + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start + * 0b1..Detected + * 0b0..Not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched + * 0b1..Header matched + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop + * 0b1..Stopped state detected + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received Message Pending + * 0b1..Received message pending + * 0b0..No received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer Not Full + * 0b1..Transmit buffer not full + * 0b0..Transmit buffer full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change + * 0b1..DA change detected + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code + * 0b1..CCC received + * 0b0..CCC not received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error Warning */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate Command Match + * 0b1..Matched the I3C dynamic address + * 0b0..Did not match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code Handled + * 0b1..CCC handling in progress + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event + * 0b1..IBI, CR, or HJ occurred + * 0b0..No event occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event Details + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Controller Requests Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join Disabled + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity State from Common Command Codes (CCC) + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time Control + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Target Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - Event + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..CONTROLLER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt Data */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending Interrupt */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity State of Target */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor Information */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Target Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) +/*! @} */ + +/*! @name SINTCLR - Target Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START Interrupt Enable Clear */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Interrupt Enable Clear */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Enable Clear */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Enable Clear */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Enable Clear */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Enable Clear */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Enable Clear */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Enable Clear */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) +/*! @} */ + +/*! @name SINTMASKED - Target Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START Interrupt Mask */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED Interrupt Mask */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Mask */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Mask */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Mask */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Mask */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Mask */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Mask */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Mask */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) +/*! @} */ + +/*! @name SERRWARN - Target Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun Error + * 0b1..Overrun error + * 0b0..No overrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Underrun error + * 0b0..No underrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error + * 0b1..Underrun; not acknowledged error + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated Error + * 0b1..Terminated error + * 0b0..No terminated error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid Start Error + * 0b1..Invalid start error + * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR Parity Error + * 0b1..SDR parity error + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR Parity Error + * 0b1..HDR parity error + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC Error + * 0b1..HDR-DDR CRC error occurred + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - TE0 or TE1 Error + * 0b1..TE0 or TE1 error occurred + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-Read Error + * 0b1..Over-read error + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-Write Error + * 0b1..Overwrite error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Target DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA Operations + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name SDATACTRL - Target Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Cannot be changed + * 0b1..Can be changed + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Default (trigger when 1 less than full or less) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 or more full + * 0b10..Trigger when 1/2 or more full + * 0b11..Trigger when 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of Bytes in Transmit */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of Bytes in Receive */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b1..Full + * 0b0..Not full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b1..Empty + * 0b0..Not empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End Also + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Target Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Target Write Data Halfword End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Target Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Target Read Data Halfword */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SWDATAB1 - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB1_DATA_MASK (0xFFU) +#define I3C_SWDATAB1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH1 - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH1_DATA_MASK (0xFFFFU) +#define I3C_SWDATAH1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Target Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) +#define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) +/*! I2CRST - I2C Software Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Target Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - Group + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - SETAASA + * 0b1..SETAASA supported + * 0b0..SETAASA not supported + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable + * 0b1..Subscriber capable + * 0b0..Not subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Target-Target(s)-Tunnel Write Capable + * 0b1..Write capable + * 0b0..Not write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Target Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b Handler + * 0b00..Application + * 0b01..Hardware + * 0b10..Hardware, but the I3C module instance handles ID 48b + * 0b11..A part number register (PARTNO) + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID Register + * 0b0000..All ID register features disabled + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + * 0bxx1x..An ID Random field is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0b1xxx..A Bus Characteristics Register (BCR) is available + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - High Data Rate Support + * 0b00..No HDR modes supported + * 0b01..DDR mode supported + * *.. + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Controller + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static Address + * 0b00..No static address + * 0b01..Static address is fixed in hardware + * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) + * 0b11..SCONFIG register supplies the static address + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes Handling + * 0b0000..All handling features disabled + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0bxxxx1..Application can generate an IBI + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bx1xxx..Application can generate a Hot-Join event + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time Control + * 0b0..No time control supported + * 0b1..At least one time-control type supported + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..No external FIFO available + * 0b001..Standard available or free external FIFO + * 0b010..Request track external FIFO + * *.. + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO Transmit + * 0b00..Two + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO Receive + * 0b00..Two or three + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - Interrupts + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - Direct Memory Access + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SDYNADDR - Target Dynamic Address */ +/*! @{ */ + +#define I3C_SDYNADDR_DAVALID_MASK (0x1U) +#define I3C_SDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..DANOTASSIGNED: a dynamic address is not assigned + * 0b1..DAASSIGNED: a dynamic address is assigned + */ +#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) + +#define I3C_SDYNADDR_DADDR_MASK (0xFEU) +#define I3C_SDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) + +#define I3C_SDYNADDR_MAPSA_MASK (0x1000U) +#define I3C_SDYNADDR_MAPSA_SHIFT (12U) +/*! MAPSA - Map a Static Address */ +#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) + +#define I3C_SDYNADDR_SA10B_MASK (0xE000U) +#define I3C_SDYNADDR_SA10B_SHIFT (13U) +/*! SA10B - 10-Bit Static Address */ +#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) + +#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) +#define I3C_SDYNADDR_KEY_SHIFT (16U) +/*! KEY - Key */ +#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Target Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum Read Length */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum Write Length */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Target ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part Number */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Target ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Target Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Target Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock Accuracy */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock Frequency */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Target Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + * 0b1..I2C static address + * 0b0..I3C dynamic address + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCONFIG_EXT - Controller Extended Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) +/*! I3C_CAS_DEL - I3C CAS Delay After START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 3/2 + */ +#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) + +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) +/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 1 1/2 + */ +#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) +/*! @} */ + +/*! @name MCTRL - Controller Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..Force Exit and Target Reset + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus Type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt Response + * 0b00..ACK (acknowledge) + * 0b01..NACK (reject) + * 0b10..Acknowledge with mandatory byte + * 0b11..Manual + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read Terminate Counter */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Controller Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive (for other cases) + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not Acknowledged + * 0b1..NACKed (not acknowledged) + * 0b0..Not NACKed + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) Type + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start + * 0b1..Target requesting START + * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done + * 0b1..Done + * 0b0..Not done + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - Complete + * 0b1..Complete + * 0b0..Not complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + * 0b1..Receive message pending + * 0b0..No receive message pending + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX Buffer or FIFO Not Full + * 0b1..Receive buffer or FIFO not full + * 0b0..Receive buffer or FIFO full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) Won + * 0b1..IBI arbitration won + * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning + * 0b1..Error or warning + * 0b0..No error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Module is now Controller + * 0b1..Controller + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI Address */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Most Significant Address Bit is 0 + * 0b1..MSB is 0 + * 0b0..MSB is not 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + * 0b1..Without mandatory IBI byte + * 0b0..With mandatory IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Controller Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed Message Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Pending Interrupt Enable */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - IBI Won Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now Controller Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Controller Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Controller Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Controller Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_URUN_MASK (0x2U) +#define I3C_MERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not Acknowledge Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - Write Abort Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_TERM_MASK (0x10U) +#define I3C_MERRWARN_TERM_SHIFT (4U) +/*! TERM - Terminate Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High Data Rate Parity + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High Data Rate CRC Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Overread Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Overwrite Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid Request Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - Timeout Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Controller DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA Width + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name MDATACTRL - Controller Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Locked + * 0b1..Unlocked + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Trigger when 1 less than full or less (default) + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 full or more + * 0b10..Trigger when 1/2 full or more + * 0b11..Trigger when 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Transmit Byte Count */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Byte Count */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Controller Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data Byte */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Controller Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Controller Write Data Halfword */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Controller Write Data Halfword End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Controller Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Controller Read Data Halfword */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) +#define I3C_MWDATAH1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Controller Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) +/*! ADDRCMD - Address Command */ +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) +/*! LEN - Length of Message */ +#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Controller Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Controller Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b1..Valid DA assigned + * 0b0..No valid DA assigned + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable Primary Dynamic Address + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + * 0b000..No information (this value occurs when not configured to write DA) + * 0b001..Set using ENTDAA + * 0b010..Set using SETDASA, SETAASA, or SETNEWDA + * 0b011..Cleared using RSTDAA + * 0b100..Auto MAP change happened last + * *.. + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra Byte 1 */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra Byte 2 */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra Byte 3 */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra Byte 4 */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra Byte 5 */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra Byte 6 */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra Byte 7 */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SID - Target Module ID */ +/*! @{ */ + +#define I3C_SID_ID_MASK (0xFFFFFFFFU) +#define I3C_SID_ID_SHIFT (0U) +/*! ID - ID */ +#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/* I3C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x50021000u) + /** Peripheral I3C0 base address */ + #define I3C0_BASE_NS (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C0 base pointer */ + #define I3C0_NS ((I3C_Type *)I3C0_BASE_NS) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x50022000u) + /** Peripheral I3C1 base address */ + #define I3C1_BASE_NS (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Peripheral I3C1 base pointer */ + #define I3C1_NS ((I3C_Type *)I3C1_BASE_NS) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS_NS { I3C0_BASE_NS, I3C1_BASE_NS } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS_NS { I3C0_NS, I3C1_NS } +#else + /** Peripheral I3C0 base address */ + #define I3C0_BASE (0x40021000u) + /** Peripheral I3C0 base pointer */ + #define I3C0 ((I3C_Type *)I3C0_BASE) + /** Peripheral I3C1 base address */ + #define I3C1_BASE (0x40022000u) + /** Peripheral I3C1 base pointer */ + #define I3C1 ((I3C_Type *)I3C1_BASE) + /** Array initializer of I3C peripheral base addresses */ + #define I3C_BASE_ADDRS { I3C0_BASE, I3C1_BASE } + /** Array initializer of I3C peripheral base pointers */ + #define I3C_BASE_PTRS { I3C0, I3C1 } +#endif +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn, I3C1_IRQn } + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CTIMER0CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x20 */ + __IO uint32_t CTIMER0CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x24 */ + __IO uint32_t CTIMER0CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x28 */ + __IO uint32_t CTIMER0CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x2C */ + __IO uint32_t TIMER0TRIG; /**< Trigger Register for CTIMER, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CTIMER1CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x40 */ + __IO uint32_t CTIMER1CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x44 */ + __IO uint32_t CTIMER1CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x48 */ + __IO uint32_t CTIMER1CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x4C */ + __IO uint32_t TIMER1TRIG; /**< Trigger Register for CTIMER, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CTIMER2CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x60 */ + __IO uint32_t CTIMER2CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x64 */ + __IO uint32_t CTIMER2CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x68 */ + __IO uint32_t CTIMER2CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x6C */ + __IO uint32_t TIMER2TRIG; /**< Trigger Register for CTIMER, offset: 0x70 */ + uint8_t RESERVED_3[44]; + __IO uint32_t SMARTDMAARCHB_INMUX[8]; /**< Inputmux Register for SMARTDMA Arch B Inputs, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t PINTSEL[8]; /**< Pin Interrupt Select, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[160]; + __IO uint32_t FREQMEAS_REF; /**< Selection for Frequency Measurement Reference Clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for Frequency Measurement Target Clock, offset: 0x184 */ + uint8_t RESERVED_5[24]; + __IO uint32_t CTIMER3CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A0 */ + __IO uint32_t CTIMER3CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A4 */ + __IO uint32_t CTIMER3CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1A8 */ + __IO uint32_t CTIMER3CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1AC */ + __IO uint32_t TIMER3TRIG; /**< Trigger Register for CTIMER, offset: 0x1B0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CTIMER4CAP0; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C0 */ + __IO uint32_t CTIMER4CAP1; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C4 */ + __IO uint32_t CTIMER4CAP2; /**< Capture Select Register for CTIMER Inputs, offset: 0x1C8 */ + __IO uint32_t CTIMER4CAP3; /**< Capture Select Register for CTIMER Inputs, offset: 0x1CC */ + __IO uint32_t TIMER4TRIG; /**< Trigger Register for CTIMER, offset: 0x1D0 */ + uint8_t RESERVED_7[140]; + __IO uint32_t CMP0_TRIG; /**< CMP0 Input Connections, offset: 0x260 */ + uint8_t RESERVED_8[28]; + __IO uint32_t ADC0_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[48]; + __IO uint32_t ADC1_TRIG[4]; /**< ADC Trigger Input Connections, array offset: 0x2C0, array step: 0x4 */ + uint8_t RESERVED_10[144]; + struct { /* offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_TRIG; /**< QDC0 Trigger Input Connections..QDC1 Trigger Input Connections, array offset: 0x360, array step: 0x20 */ + __IO uint32_t QDC_HOME; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x364, array step: 0x20 */ + __IO uint32_t QDC_INDEX; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x368, array step: 0x20 */ + __IO uint32_t QDC_PHASEB; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x36C, array step: 0x20 */ + __IO uint32_t QDC_PHASEA; /**< QDC0 Input Connections..QDC1 Input Connections, array offset: 0x370, array step: 0x20 */ + uint8_t RESERVED_0[12]; + } QDCN[2]; + __IO uint32_t FLEXPWM0_SM_EXTSYNC[4]; /**< PWM0 External Synchronization, array offset: 0x3A0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_SM_EXTA[4]; /**< PWM0 Input Trigger Connections, array offset: 0x3B0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_EXTFORCE; /**< PWM0 External Force Trigger Connections, offset: 0x3C0 */ + __IO uint32_t FLEXPWM0_FAULT[4]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C4, array step: 0x4 */ + uint8_t RESERVED_11[12]; + __IO uint32_t FLEXPWM1_SM_EXTSYNC[4]; /**< PWM1 External Synchronization, array offset: 0x3E0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_SM_EXTA[4]; /**< PWM1 Input EXTA Connections, array offset: 0x3F0, array step: 0x4 */ + __IO uint32_t FLEXPWM1_EXTFORCE; /**< PWM1 External Force Trigger Connections, offset: 0x400 */ + __IO uint32_t FLEXPWM1_FAULT[4]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x404, array step: 0x4 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PWM0_EXT_CLK; /**< PWM0 External Clock Trigger, offset: 0x420 */ + __IO uint32_t PWM1_EXT_CLK; /**< PWM1 External Clock Trigger, offset: 0x424 */ + uint8_t RESERVED_13[24]; + __IO uint32_t EVTG_TRIG[16]; /**< EVTG Trigger Input Connections, array offset: 0x440, array step: 0x4 */ + uint8_t RESERVED_14[64]; + __IO uint32_t EXT_TRIG[8]; /**< EXT Trigger Connections, array offset: 0x4C0, array step: 0x4 */ + __IO uint32_t CMP1_TRIG; /**< CMP1 Input Connections, offset: 0x4E0 */ + uint8_t RESERVED_15[188]; + __IO uint32_t FLEXCOMM0_TRIG; /**< LP_FLEXCOMM0 Trigger Input Connections, offset: 0x5A0 */ + uint8_t RESERVED_16[28]; + __IO uint32_t FLEXCOMM1_TRIG; /**< LP_FLEXCOMM1 Trigger Input Connections, offset: 0x5C0 */ + uint8_t RESERVED_17[28]; + __IO uint32_t FLEXCOMM2_TRIG; /**< LP_FLEXCOMM2 Trigger Input Connections, offset: 0x5E0 */ + uint8_t RESERVED_18[28]; + __IO uint32_t FLEXCOMM3_TRIG; /**< LP_FLEXCOMM3 Trigger Input Connections, offset: 0x600 */ + uint8_t RESERVED_19[28]; + __IO uint32_t FLEXCOMM4_TRIG; /**< LP_FLEXCOMM4 Trigger Input Connections, offset: 0x620 */ + uint8_t RESERVED_20[28]; + __IO uint32_t FLEXCOMM5_TRIG; /**< LP_FLEXCOMM5 Trigger Input Connections, offset: 0x640 */ + uint8_t RESERVED_21[28]; + __IO uint32_t FLEXCOMM6_TRIG; /**< LP_FLEXCOMM6 Trigger Input Connections, offset: 0x660 */ + uint8_t RESERVED_22[28]; + __IO uint32_t FLEXCOMM7_TRIG; /**< LP_FLEXCOMM7 Trigger Input Connections, offset: 0x680 */ + uint8_t RESERVED_23[92]; + __IO uint32_t FLEXIO_TRIG[8]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ + __IO uint32_t DMA0_REQ_ENABLE0; /**< DMA0 Request Enable0, offset: 0x700 */ + __O uint32_t DMA0_REQ_ENABLE0_SET; /**< DMA0 Request Enable0, offset: 0x704 */ + __O uint32_t DMA0_REQ_ENABLE0_CLR; /**< DMA0 Request Enable0, offset: 0x708 */ + __O uint32_t DMA0_REQ_ENABLE0_TOG; /**< DMA0 Request Enable0, offset: 0x70C */ + __IO uint32_t DMA0_REQ_ENABLE1; /**< DMA0 Request Enable1, offset: 0x710 */ + __O uint32_t DMA0_REQ_ENABLE1_SET; /**< DMA0 Request Enable1, offset: 0x714 */ + __O uint32_t DMA0_REQ_ENABLE1_CLR; /**< DMA0 Request Enable1, offset: 0x718 */ + __O uint32_t DMA0_REQ_ENABLE1_TOG; /**< DMA0 Request Enable1, offset: 0x71C */ + __IO uint32_t DMA0_REQ_ENABLE2; /**< DMA0 Request Enable2, offset: 0x720 */ + __O uint32_t DMA0_REQ_ENABLE2_SET; /**< DMA0 Request Enable2, offset: 0x724 */ + __O uint32_t DMA0_REQ_ENABLE2_CLR; /**< DMA0 Request Enable2, offset: 0x728 */ + __O uint32_t DMA0_REQ_ENABLE2_TOG; /**< DMA0 Request Enable2, offset: 0x72C */ + __IO uint32_t DMA0_REQ_ENABLE3; /**< DMA0 Request Enable3, offset: 0x730 */ + __O uint32_t DMA0_REQ_ENABLE3_SET; /**< DMA0 Request Enable3, offset: 0x734 */ + __O uint32_t DMA0_REQ_ENABLE3_CLR; /**< DMA0 Request Enable3, offset: 0x738 */ + uint8_t RESERVED_24[68]; + __IO uint32_t DMA1_REQ_ENABLE0; /**< DMA1 Request Enable0, offset: 0x780 */ + __O uint32_t DMA1_REQ_ENABLE0_SET; /**< DMA1 Request Enable0, offset: 0x784 */ + __O uint32_t DMA1_REQ_ENABLE0_CLR; /**< DMA1 Request Enable0, offset: 0x788 */ + __O uint32_t DMA1_REQ_ENABLE0_TOG; /**< DMA1 Request Enable0, offset: 0x78C */ + __IO uint32_t DMA1_REQ_ENABLE1; /**< DMA1 Request Enable1, offset: 0x790 */ + __O uint32_t DMA1_REQ_ENABLE1_SET; /**< DMA1 Request Enable1, offset: 0x794 */ + __O uint32_t DMA1_REQ_ENABLE1_CLR; /**< DMA1 Request Enable1, offset: 0x798 */ + __O uint32_t DMA1_REQ_ENABLE1_TOG; /**< DMA1 Request Enable1, offset: 0x79C */ + __IO uint32_t DMA1_REQ_ENABLE2; /**< DMA1 Request Enable2, offset: 0x7A0 */ + __O uint32_t DMA1_REQ_ENABLE2_SET; /**< DMA1 Request Enable2, offset: 0x7A4 */ + __O uint32_t DMA1_REQ_ENABLE2_CLR; /**< DMA1 Request Enable2, offset: 0x7A8 */ + __O uint32_t DMA1_REQ_ENABLE2_TOG; /**< DMA1 Request Enable2, offset: 0x7AC */ + __IO uint32_t DMA1_REQ_ENABLE3; /**< DMA1 Request Enable3, offset: 0x7B0 */ + __O uint32_t DMA1_REQ_ENABLE3_SET; /**< DMA1 Request Enable3, offset: 0x7B4 */ + __O uint32_t DMA1_REQ_ENABLE3_CLR; /**< DMA1 Request Enable3, offset: 0x7B8 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name CTIMER0CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP0_INP_SHIFT)) & INPUTMUX_CTIMER0CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP1_INP_SHIFT)) & INPUTMUX_CTIMER0CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP2_INP_SHIFT)) & INPUTMUX_CTIMER0CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER0CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER0CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER0CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER0CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER0CAP3_INP_SHIFT)) & INPUTMUX_CTIMER0CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER0TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP0_INP_SHIFT)) & INPUTMUX_CTIMER1CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP1_INP_SHIFT)) & INPUTMUX_CTIMER1CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP2_INP_SHIFT)) & INPUTMUX_CTIMER1CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER1CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER1CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER1CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER1CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER1CAP3_INP_SHIFT)) & INPUTMUX_CTIMER1CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER1TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP0_INP_SHIFT)) & INPUTMUX_CTIMER2CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP1_INP_SHIFT)) & INPUTMUX_CTIMER2CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP2_INP_SHIFT)) & INPUTMUX_CTIMER2CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER2CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER2CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER2CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER2CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER2CAP3_INP_SHIFT)) & INPUTMUX_CTIMER2CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER2TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0_IRQ input is selected + * 0b0011010..ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) +/*! @} */ + +/*! @name INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX - Inputmux Register for SMARTDMA Arch B Inputs */ +/*! @{ */ + +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK (0x7FU) +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT (0U) +/*! INP - Input number select to SmartDMA ARCHB input + * 0b0000000..FlexIO interrupt is selected as input + * 0b0000001..GPIO P0_1 input is selected + * 0b0000010..GPIO P0_2 input is selected + * 0b0000011..GPIO P0_3 input is selected + * 0b0000100..GPIO P0_4 input is selected + * 0b0000101..GPIO P0_5 input is selected + * 0b0000110..GPIO P0_6 input is selected + * 0b0000111..GPIO P0_7 input is selected + * 0b0001000..Reserved + * 0b0001001..Reserved + * 0b0001010..Reserved + * 0b0001011..Reserved + * 0b0001100..GPIO P0_12 input is selected + * 0b0001101..GPIO P0_13 input is selected + * 0b0001110..GPIO P0_14 input is selected + * 0b0001111..GPIO P0_15 input is selected + * 0b0010000..Reserved + * 0b0010001..Reserved + * 0b0010010..Reserved + * 0b0010011..Reserved + * 0b0010100..MRT0 MRT_CH0_IRQ input is selected + * 0b0010101..MRT0 MRT_CH1_IRQ input is selected + * 0b0010110..CTIMER4_MAT3 input is selected + * 0b0010111..CTIMER4_MAT2 input is selected + * 0b0011000..CTIMER3_MAT3 input is selected + * 0b0011001..CTIMER3_MAT2 input is selected + * 0b0011010..CTIMER1_MAT3 input is selected + * 0b0011011..CTIMER1_MAT2 input is selected + * 0b0011100..UTICK0 UTICK_IRQ input is selected + * 0b0011101..WWDT0 WDT0_IRQ input is selected + * 0b0011110..ADC0 ADC0_IRQ input is selected + * 0b0011111..CMP0_IRQ input is selected + * 0b0100000..Reserved + * 0b0100001..LP_FLEXCOMM7_IRQ input is selected + * 0b0100010..LP_FLEXCOMM6_IRQ input is selected + * 0b0100011..LP_FLEXCOMM5_IRQ input is selected + * 0b0100100..LP_FLEXCOMM4_IRQ input is selected + * 0b0100101..LP_FLEXCOMM3_IRQ input is selected + * 0b0100110..LP_FLEXCOMM2_IRQ input is selected + * 0b0100111..LP_FLEXCOMM1_IRQ input is selected + * 0b0101000..LP_FLEXCOMM0_IRQ input is selected + * 0b0101001..DMA0_IRQ input is selected + * 0b0101010..DMA1_IRQ input is selected + * 0b0101011..SYS_IRQSYS_IRQ combines the CDOG IRQ, WWDT IRQ, MBC secure violation IRQ, Secure AHB Matrix secure + * violation IRQ, GDET IRQ, ELS S50 error IRQ, PKC error IRQ, and VBAT IRQ using the logical OR + * operation. input is selected + * 0b0101100..RTC_COMBO_IRQ input is selected + * 0b0101101..ARM_TXEV input is selected + * 0b0101110..PINT0 GPIO_INT_BMATCH input is selected + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CMP0_OUT input is selected + * 0b0110010..usb0 start of frame input is selected + * 0b0110011..usb1 start of frame input is selected + * 0b0110100..OSTIMER0 OS_EVENT_TIMER_IRQ input is selected + * 0b0110101..ADC1_IRQ input is selected + * 0b0110110..CMP0_IRQ/CMP1_IRQ input is selected + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..PWM0_IRQ input is selected + * 0b0111010..PWM1_IRQ input is selected + * 0b0111011..QDC0_IRQ input is selected + * 0b0111100..QDC1_IRQ input is selected + * 0b0111101..EVTG_OUT0A input is selected + * 0b0111110..EVTG_OUT1A input is selected + * 0b0111111..Reserved + * 0b1000000..Reserved + * 0b1000001..GPIO1_alias0 GPIO1 Pin Event Trig 0 input is selected + * 0b1000010..GPIO1_alias1 GPIO1 Pin Event Trig 1 input is selected + * 0b1000011..GPIO2_alias0 GPIO2 Pin Event Trig 0 input is selected + * 0b1000100..GPIO2_alias1 GPIO2 Pin Event Trig 1 input is selected + * 0b1000101..GPIO3_alias0 GPIO3 Pin Event Trig 0 input is selected + * 0b1000110..GPIO3_alias1 GPIO3 Pin Event Trig 1 input is selected + * 0b1000111..FlexIO Shifter DMA Request 0 is selected + * 0b1001000..FlexIO Shifter DMA Request 1 is selected + * 0b1001001..FlexIO Shifter DMA Request 2 is selected + * 0b1001010..FlexIO Shifter DMA Request 3 is selected + * 0b1001011..FlexIO Shifter DMA Request 4 is selected + * 0b1001100..FlexIO Shifter DMA Request 5 is selected + * 0b1001101..FlexIO Shifter DMA Request 6 is selected + * 0b1001110..FlexIO Shifter DMA Request 7 is selected + * *.. + */ +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_SHIFT)) & INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX */ +#define INPUTMUX_INPUTMUX_SMARTDMA_SMARTDMAARCHB_INMUX_COUNT (8U) + +/*! @name INPUTMUX_GPIO_INT_PINTSEL - Pin Interrupt Select */ +/*! @{ */ + +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK (0x7FU) +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT (0U) +/*! INP - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INP = (x * + * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + * 0b0000000..GPIO P0_0 input is selected + * 0b0000001..GPIO P0_1 input is selected + * 0b0000010..GPIO P0_2 input is selected + * 0b0000011..GPIO P0_3 input is selected + * 0b0000100..GPIO P0_4 input is selected + * 0b0000101..GPIO P0_5 input is selected + * 0b0000110..GPIO P0_6 input is selected + * 0b0000111..GPIO P0_7 input is selected + * 0b0001000..Reserved + * 0b0001001..Reserved + * 0b0001010..Reserved + * 0b0001011..Reserved + * 0b0001100..GPIO P0_12 input is selected + * 0b0001101..GPIO P0_13 input is selected + * 0b0001110..GPIO P0_14 input is selected + * 0b0001111..GPIO P0_15 input is selected + * 0b0010000..GPIO P0_16 input is selected + * 0b0010001..GPIO P0_17 input is selected + * 0b0010010..GPIO P0_18 input is selected + * 0b0010011..GPIO P0_19 input is selected + * 0b0010100..GPIO P0_20 input is selected + * 0b0010101..GPIO P0_21 input is selected + * 0b0010110..GPIO P0_22 input is selected + * 0b0010111..GPIO P0_23 input is selected + * 0b0011000..GPIO P0_24 input is selected + * 0b0011001..GPIO P0_25 input is selected + * 0b0011010..GPIO P0_26 input is selected + * 0b0011011..GPIO P0_27 input is selected + * 0b0011100..GPIO P0_28 input is selected + * 0b0011101..GPIO P0_29 input is selected + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..GPIO P1_0 input is selected + * 0b0100001..GPIO P1_1 input is selected + * 0b0100010..GPIO P1_2 input is selected + * 0b0100011..GPIO P1_3 input is selected + * 0b0100100..GPIO P1_4 input is selected + * 0b0100101..GPIO P1_5 input is selected + * 0b0100110..GPIO P1_6 input is selected + * 0b0100111..GPIO P1_7 input is selected + * 0b0101000..GPIO P1_8 input is selected + * 0b0101001..GPIO P1_9 input is selected + * 0b0101010..GPIO P1_10 input is selected + * 0b0101011..GPIO P1_11 input is selected + * 0b0101100..GPIO P1_12 input is selected + * 0b0101101..GPIO P1_13 input is selected + * 0b0101110..GPIO P1_14 input is selected + * 0b0101111..GPIO P1_15 input is selected + * 0b0110000..GPIO P1_16 input is selected + * 0b0110001..GPIO P1_17 input is selected + * 0b0110010..GPIO P1_18 input is selected + * 0b0110011..GPIO P1_19 input is selected + * 0b0110100..Reserved + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..GPIO P1_30 input is selected + * 0b0111111..GPIO P1_31 input is selected + * *.. + */ +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_SHIFT)) & INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL */ +#define INPUTMUX_INPUTMUX_GPIO_INT_PINTSEL_COUNT (8U) + +/*! @name FREQMEAS_REF - Selection for Frequency Measurement Reference Clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_INP_MASK (0x3FU) +#define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function reference clock. + * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected + * 0b000001..FRO_12M input is selected + * 0b000010..FRO_144M input is selected + * 0b000011..Reserved + * 0b000100..OSC_32K input is selected + * 0b000101..CPU/system_clk input is selected + * 0b000110..FREQME_CLK_IN0 input is selected + * 0b000111..FREQME_CLK_IN1 input is selected + * 0b001000..EVTG_OUT0A input is selected + * 0b001001..EVTG_OUT1A input is selected + * *.. + */ +#define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for Frequency Measurement Target Clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x3FU) +#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b000000..clk_in (output of clk_in or XTAL mux in Clockgen) input is selected + * 0b000001..FRO_12M input is selected + * 0b000010..FRO_144M input is selected + * 0b000011..Reserved + * 0b000100..OSC_32K input is selected + * 0b000101..CPU/system_clk input is selected + * 0b000110..FREQME_CLK_IN0 input is selected + * 0b000111..FREQME_CLK_IN1 input is selected + * 0b001000..EVTG_OUT0A input is selected + * 0b001001..EVTG_OUT1A input is selected + * *.. + */ +#define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP0_INP_SHIFT)) & INPUTMUX_CTIMER3CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP1_INP_SHIFT)) & INPUTMUX_CTIMER3CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP2_INP_SHIFT)) & INPUTMUX_CTIMER3CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER3CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER3CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER3CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER3CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER3CAP3_INP_SHIFT)) & INPUTMUX_CTIMER3CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER3TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP0 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP0_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP0_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP0_INP_SHIFT)) & INPUTMUX_CTIMER4CAP0_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP1 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP1_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP1_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP1_INP_SHIFT)) & INPUTMUX_CTIMER4CAP1_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP2 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP2_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP2_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP2_INP_SHIFT)) & INPUTMUX_CTIMER4CAP2_INP_MASK) +/*! @} */ + +/*! @name CTIMER4CAP3 - Capture Select Register for CTIMER Inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMER4CAP3_INP_MASK (0x7FU) +#define INPUTMUX_CTIMER4CAP3_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_CTIMER4CAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMER4CAP3_INP_SHIFT)) & INPUTMUX_CTIMER4CAP3_INP_MASK) +/*! @} */ + +/*! @name TIMER4TRIG - Trigger Register for CTIMER */ +/*! @{ */ + +#define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER + * 0b0000000..CT_INP0 input is selected + * 0b0000001..CT_INP1 input is selected + * 0b0000010..CT_INP2 input is selected + * 0b0000011..CT_INP3 input is selected + * 0b0000100..CT_INP4 input is selected + * 0b0000101..CT_INP5 input is selected + * 0b0000110..CT_INP6 input is selected + * 0b0000111..CT_INP7 input is selected + * 0b0001000..CT_INP8 input is selected + * 0b0001001..CT_INP9 input is selected + * 0b0001010..CT_INP10 input is selected + * 0b0001011..CT_INP11 input is selected + * 0b0001100..CT_INP12 input is selected + * 0b0001101..CT_INP13 input is selected + * 0b0001110..CT_INP14 input is selected + * 0b0001111..CT_INP15 input is selected + * 0b0010000..CT_INP16 input is selected + * 0b0010001..CT_INP17 input is selected + * 0b0010010..CT_INP18 input is selected + * 0b0010011..CT_INP19 input is selected + * 0b0010100..usb0 start of frame input is selected + * 0b0010101..usb1 start of frame input is selected + * 0b0010110..DCDC_BURST_ACTIVE input is selected + * 0b0010111..sai0_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011000..sai0_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * 0b0011001..ADC0 ADC0_IRQ input is selected + * 0b0011010..ADC0 ADC1_IRQ input is selected + * 0b0011011..CMP0_OUT input is selected + * 0b0011100..CMP1_OUT input is selected + * 0b0011101..Reserved + * 0b0011110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b0100110..QDC0_CMP/POS_MATCH input is selected + * 0b0100111..QDC1_CMP/POS_MATCH input is selected + * 0b0101000..EVTG_OUT0A input is selected + * 0b0101001..EVTG_OUT0B input is selected + * 0b0101010..EVTG_OUT1A input is selected + * 0b0101011..EVTG_OUT1B input is selected + * 0b0101100..EVTG_OUT2A input is selected + * 0b0101101..EVTG_OUT2B input is selected + * 0b0101110..EVTG_OUT3A input is selected + * 0b0101111..EVTG_OUT3B input is selected + * 0b0110000..Reserved + * 0b0110001..Reserved + * 0b0110010..LP_FLEXCOMM0 trig 0 input is selected + * 0b0110011..LP_FLEXCOMM0 trig 1 input is selected + * 0b0110100..LP_FLEXCOMM0 trig 2 input is selected + * 0b0110101..LP_FLEXCOMM1 trig 0 input is selected + * 0b0110110..LP_FLEXCOMM1 trig 1 input is selected + * 0b0110111..LP_FLEXCOMM1 trig 2 input is selected + * 0b0111000..LP_FLEXCOMM2 trig 0 input is selected + * 0b0111001..LP_FLEXCOMM2 trig 1 input is selected + * 0b0111010..LP_FLEXCOMM2 trig 2 input is selected + * 0b0111011..LP_FLEXCOMM3 trig 0 input is selected + * 0b0111100..LP_FLEXCOMM3 trig 1 input is selected + * 0b0111101..LP_FLEXCOMM3 trig 2 input is selected + * 0b0111110..LP_FLEXCOMM3 trig 3 input is selected + * 0b0111111..sai1_tx_sync_outsai_tx_sync_out is Transmit Frame Sync for multi-SAI synchronous operation. input is selected + * 0b1000000..sai1_rx_sync_outsai_rx_sync_out is Receive Frame Sync for multi-SAI synchronous operation. input is selected + * *.. + */ +#define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) +/*! @} */ + +/*! @name CMP0_TRIG - CMP0 Input Connections */ +/*! @{ */ + +#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT6 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER0_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..Reserved + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC1_tcomp[0] input is selected + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected + * 0b011011..EVTG_OUT0A input is selected + * 0b011100..EVTG_OUT0B input is selected + * 0b011101..EVTG_OUT1A input is selected + * 0b011110..EVTG_OUT1B input is selected + * 0b011111..EVTG_OUT2A input is selected + * 0b100000..EVTG_OUT2B input is selected + * 0b100001..EVTG_OUT3A input is selected + * 0b100010..EVTG_OUT3B input is selected + * 0b100011..LPTMR0 input is selected + * 0b100100..LPTMR1 input is selected + * 0b100101..GPIO2 Pin Event Trig 0 input is selected + * 0b100110..GPIO2 Pin Event Trig 1 input is selected + * 0b100111..GPIO3 Pin Event Trig 0 input is selected + * 0b101000..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0xFFU) +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b00000000..PINT PIN_INT0 input is selected + * 0b00000001..PINT PIN_INT1 input is selected + * 0b00000010..Reserved + * 0b00000011..Reserved + * 0b00000100..Reserved + * 0b00000101..CTIMER0_MAT3 input is selected + * 0b00000110..CTIMER1_MAT3 input is selected + * 0b00000111..CTIMER2_MAT3 input is selected + * 0b00001000..CTIMER3_MAT3 input is selected + * 0b00001001..CTIMER4_MAT3 input is selected + * 0b00001010..DCDC_Burst_Done_Trig input is selected + * 0b00001011..Reserved + * 0b00001100..PINT GPIO_INT_BMAT input is selected + * 0b00001101..ADC0_tcomp[0] input is selected + * 0b00001110..ADC0_tcomp[1] input is selected + * 0b00001111..ADC0_tcomp[2] input is selected + * 0b00010000..ADC0_tcomp[3] input is selected + * 0b00010001..ADC1_tcomp[0] input is selected + * 0b00010010..ADC1_tcomp[1] input is selected + * 0b00010011..ADC1_tcomp[2] input is selected + * 0b00010100..ADC1_tcomp[3] input is selected + * 0b00010101..CMP0_OUT input is selected + * 0b00010110..CMP1_OUT input is selected + * 0b00010111..Reserved + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected + * 0b00101010..EVTG_OUT0A input is selected + * 0b00101011..EVTG_OUT0B input is selected + * 0b00101100..EVTG_OUT1A input is selected + * 0b00101101..EVTG_OUT1B input is selected + * 0b00101110..EVTG_OUT2A input is selected + * 0b00101111..EVTG_OUT2B input is selected + * 0b00110000..EVTG_OUT3A input is selected + * 0b00110001..EVTG_OUT3B input is selected + * 0b00110010..LPTMR0 input is selected + * 0b00110011..LPTMR1 input is selected + * 0b00110100..FlexIO CH0 input is selected + * 0b00110101..FlexIO CH1 input is selected + * 0b00110110..FlexIO CH2 input is selected + * 0b00110111..FlexIO CH3 input is selected + * 0b00111000..Reserved + * 0b00111001..Reserved + * 0b00111010..Reserved + * 0b00111011..Reserved + * 0b00111100..Reserved + * 0b00111101..GPIO2 Pin Event Trig 0 input is selected + * 0b00111110..GPIO2 Pin Event Trig 1 input is selected + * 0b00111111..GPIO3 Pin Event Trig 0 input is selected + * 0b01000000..GPIO3 Pin Event Trig 1 input is selected + * 0b01000001..WUU input is selected + * *.. + */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U) + +/*! @name ADC1_TRIGN_ADC1_TRIG - ADC Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK (0xFFU) +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC1 trigger inputs + * 0b00000000..PINT PIN_INT0 input is selected + * 0b00000001..PINT PIN_INT2 input is selected + * 0b00000010..Reserved + * 0b00000011..Reserved + * 0b00000100..Reserved + * 0b00000101..CTIMER0_MAT3 input is selected + * 0b00000110..CTIMER1_MAT3 input is selected + * 0b00000111..CTIMER2_MAT3 input is selected + * 0b00001000..CTIMER3_MAT2 input is selected + * 0b00001001..CTIMER4_MAT1 input is selected + * 0b00001010..DCDC_Burst_Done_Trig input is selected + * 0b00001011..Reserved + * 0b00001100..PINT GPIO_INT_BMAT input is selected + * 0b00001101..ADC0_tcomp[0] input is selected + * 0b00001110..ADC0_tcomp[1] input is selected + * 0b00001111..ADC0_tcomp[2] input is selected + * 0b00010000..ADC0_tcomp[3] input is selected + * 0b00010001..ADC1_tcomp[0] input is selected + * 0b00010010..ADC1_tcomp[1] input is selected + * 0b00010011..ADC1_tcomp[2] input is selected + * 0b00010100..ADC1_tcomp[3] input is selected + * 0b00010101..CMP0_OUT input is selected + * 0b00010110..CMP1_OUT input is selected + * 0b00010111..Reserved + * 0b00011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b00011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b00011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b00011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b00011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b00011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b00011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b00011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b00100000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b00100001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b00100010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b00100011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b00100100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b00100101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b00100110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b00100111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b00101000..QDC0_CMP/POS_MATCH input is selected + * 0b00101001..QDC1_CMP/POS_MATCH input is selected + * 0b00101010..EVTG_OUT0A input is selected + * 0b00101011..EVTG_OUT0B input is selected + * 0b00101100..EVTG_OUT1A input is selected + * 0b00101101..EVTG_OUT1B input is selected + * 0b00101110..EVTG_OUT2A input is selected + * 0b00101111..EVTG_OUT2B input is selected + * 0b00110000..EVTG_OUT3A input is selected + * 0b00110001..EVTG_OUT3B input is selected + * 0b00110010..LPTMR0 input is selected + * 0b00110011..LPTMR1 input is selected + * 0b00110100..FlexIO CH0 input is selected + * 0b00110101..FlexIO CH1 input is selected + * 0b00110110..FlexIO CH2 input is selected + * 0b00110111..FlexIO CH3 input is selected + * 0b00111000..Reserved + * 0b00111001..Reserved + * 0b00111010..Reserved + * 0b00111011..Reserved + * 0b00111100..Reserved + * 0b00111101..GPIO2 Pin Event Trig 0 input is selected + * 0b00111110..GPIO2 Pin Event Trig 1 input is selected + * 0b00111111..GPIO3 Pin Event Trig 0 input is selected + * 0b01000000..GPIO3 Pin Event Trig 1 input is selected + * 0b01000001..WUU input is selected + * *.. + */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGN_ADC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC1_TRIGN_ADC1_TRIG */ +#define INPUTMUX_ADC1_TRIGN_ADC1_TRIG_COUNT (4U) + +/*! @name QDCN_QDC_TRIG - QDC0 Trigger Input Connections..QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_TRIG_INP_SHIFT)) & INPUTMUX_QDCN_QDC_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_TRIG */ +#define INPUTMUX_QDCN_QDC_TRIG_COUNT (2U) + +/*! @name QDCN_QDC_HOME - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_HOME_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_HOME_INP_SHIFT (0U) +/*! INP - QDC1 HOME input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_HOME_INP_SHIFT)) & INPUTMUX_QDCN_QDC_HOME_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_HOME */ +#define INPUTMUX_QDCN_QDC_HOME_COUNT (2U) + +/*! @name QDCN_QDC_INDEX - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_INDEX_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 INDEX input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_INDEX_INP_SHIFT)) & INPUTMUX_QDCN_QDC_INDEX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_INDEX */ +#define INPUTMUX_QDCN_QDC_INDEX_COUNT (2U) + +/*! @name QDCN_QDC_PHASEB - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_PHASEB_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 PHASEB input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEB_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEB_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_PHASEB */ +#define INPUTMUX_QDCN_QDC_PHASEB_COUNT (2U) + +/*! @name QDCN_QDC_PHASEA - QDC0 Input Connections..QDC1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDCN_QDC_PHASEA_INP_MASK (0x3FU) +#define INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT (0U) +/*! INP - QDC1 PHASEA input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT4 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER1_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * *.. + */ +#define INPUTMUX_QDCN_QDC_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDCN_QDC_PHASEA_INP_SHIFT)) & INPUTMUX_QDCN_QDC_PHASEA_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_QDCN_QDC_PHASEA */ +#define INPUTMUX_QDCN_QDC_PHASEA_COUNT (2U) + +/*! @name FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC - PWM0 External Synchronization */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC */ +#define INPUTMUX_FLEXPWM_SM_EXTSYNC_FLEXPWM0_SM_EXTSYNC_COUNT (4U) + +/*! @name FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA - PWM0 Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA */ +#define INPUTMUX_FLEXPWM_SM_EXT_FLEXPWM0_SM_EXTA_COUNT (4U) + +/*! @name FLEXPWM0_EXTFORCE - PWM0 External Force Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTFORCE input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM_FAULT_FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM0 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER4_MAT0 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM1_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM1_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT */ +#define INPUTMUX_FLEXPWM_FAULT_FLEXPWM0_FAULT_COUNT (4U) + +/*! @name FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC - PWM1 External Synchronization */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC */ +#define INPUTMUX_FLEXPWM1_SM_EXTSYNC_ARRAY_FLEXPWM1_SM_EXTSYNC_COUNT (4U) + +/*! @name FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA - PWM1 Input EXTA Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA */ +#define INPUTMUX_FLEXPWM_SM1_EXTA_ARRAY_FLEXPWM1_SM_EXTA_COUNT (4U) + +/*! @name FLEXPWM1_EXTFORCE - PWM1 External Force Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTFORCE input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_EXTFORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM1 + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT2 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..ARM_TXEV input is selected + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[0] input is selected + * 0b001110..ADC0_tcomp[1] input is selected + * 0b001111..ADC0_tcomp[2] input is selected + * 0b010000..ADC0_tcomp[3] input is selected + * 0b010001..ADC1_tcomp[0] input is selected + * 0b010010..ADC1_tcomp[1] input is selected + * 0b010011..ADC1_tcomp[2] input is selected + * 0b010100..ADC1_tcomp[3] input is selected + * 0b010101..CMP0_OUT input is selected + * 0b010110..CMP1_OUT input is selected + * 0b010111..Reserved + * 0b011000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b011101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011110..PWM0_SM3_MUX_TRIG0 input is selected + * 0b011111..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100000..QDC0_CMP/POS_MATCH input is selected + * 0b100001..QDC1_CMP/POS_MATCH input is selected + * 0b100010..EVTG_OUT0A input is selected + * 0b100011..EVTG_OUT0B input is selected + * 0b100100..EVTG_OUT1A input is selected + * 0b100101..EVTG_OUT1B input is selected + * 0b100110..EVTG_OUT2A input is selected + * 0b100111..EVTG_OUT2B input is selected + * 0b101000..EVTG_OUT3A input is selected + * 0b101001..EVTG_OUT3B input is selected + * 0b101010..TRIG_IN0 input is selected + * 0b101011..TRIG_IN1 input is selected + * 0b101100..TRIG_IN2 input is selected + * 0b101101..TRIG_IN3 input is selected + * 0b101110..TRIG_IN4 input is selected + * 0b101111..TRIG_IN5 input is selected + * 0b110000..TRIG_IN6 input is selected + * 0b110001..TRIG_IN7 input is selected + * 0b110010..TRIG_IN8 input is selected + * 0b110011..TRIG_IN9 input is selected + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..GPIO2 Pin Event Trig 0 input is selected + * 0b111010..GPIO2 Pin Event Trig 1 input is selected + * 0b111011..GPIO3 Pin Event Trig 0 input is selected + * 0b111100..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM1_FAULT */ +#define INPUTMUX_FLEXPWM1_FAULT_COUNT (4U) + +/*! @name PWM0_EXT_CLK - PWM0 External Clock Trigger */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0x7U) +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXT_CLK input connections for PWM0 + * 0b000..FRO16K input is selected + * 0b001..OSC_32k input is selected + * 0b010..EVTG_OUT0A input is selected + * 0b011..EVTG_OUT1A input is selected + * 0b100..TRIG_IN0 input is selected + * 0b101..TRIG_IN7 input is selected + * *.. + */ +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_EXT_CLK - PWM1 External Clock Trigger */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXT_CLK input connections for PWM1 + * 0b0000..FRO16K input is selected + * 0b0001..OSC_32k input is selected + * 0b0010..EVTG_OUT0A input is selected + * 0b0011..EVTG_OUT1A input is selected + * 0b0100..TRIG_IN0 input is selected + * 0b0101..TRIG_IN7 input is selected + * *.. + */ +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name EVTG_TRIGN_EVTG_TRIG - EVTG Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT (0U) +/*! INP - EVTG trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT1 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT3 input is selected + * 0b000111..CTIMER1_MAT3 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER2_MAT2 input is selected + * 0b001010..CTIMER3_MAT2 input is selected + * 0b001011..CTIMER4_MAT2 input is selected + * 0b001100..Reserved + * 0b001101..PINT GPIO_INT_BMAT input is selected + * 0b001110..ADC0_IRQ input is selected + * 0b001111..ADC1_IRQ input is selected + * 0b010000..ADC0_tcomp[0] input is selected + * 0b010001..ADC0_tcomp[1] input is selected + * 0b010010..ADC0_tcomp[2] input is selected + * 0b010011..ADC0_tcomp[3] input is selected + * 0b010100..ADC1_tcomp[0] input is selected + * 0b010101..ADC1_tcomp[1] input is selected + * 0b010110..ADC1_tcomp[2] input is selected + * 0b010111..ADC1_tcomp[3] input is selected + * 0b011000..CMP0_OUT input is selected + * 0b011001..CMP1_OUT input is selected + * 0b011010..Reserved + * 0b011011..PWM0_SM0_MUX_TRIG0 input is selected + * 0b011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b100001..PWM0_SM3_MUX_TRIG0 input is selected + * 0b100010..PWM0_SM3_MUX_TRIG1 input is selected + * 0b100011..PWM1_SM0_MUX_TRIG0 input is selected + * 0b100100..PWM1_SM0_MUX_TRIG1 input is selected + * 0b100101..PWM1_SM1_MUX_TRIG0 input is selected + * 0b100110..PWM1_SM1_MUX_TRIG1 input is selected + * 0b100111..PWM1_SM2_MUX_TRIG0 input is selected + * 0b101000..PWM1_SM2_MUX_TRIG1 input is selected + * 0b101001..PWM1_SM3_MUX_TRIG0 input is selected + * 0b101010..PWM1_SM3_MUX_TRIG1 input is selected + * 0b101011..QDC0_CMP/POS_MATCH input is selected + * 0b101100..QDC1_CMP/POS_MATCH input is selected + * 0b101101..TRIG_IN0 input is selected + * 0b101110..TRIG_IN1 input is selected + * 0b101111..TRIG_IN2 input is selected + * 0b110000..TRIG_IN3 input is selected + * 0b110001..LPTMR0 input is selected + * 0b110010..LPTMR1 input is selected + * 0b110011..Reserved + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..Reserved + * *.. + */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_SHIFT)) & INPUTMUX_EVTG_TRIGN_EVTG_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EVTG_TRIGN_EVTG_TRIG */ +#define INPUTMUX_EVTG_TRIGN_EVTG_TRIG_COUNT (16U) + +/*! @name EXT_TRIGN_EXT_TRIG - EXT Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT (0U) +/*! INP - EXT trigger input connections + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT1 input is selected + * 0b000010..ADC0_IRQ input is selected + * 0b000011..ADC1_IRQ input is selected + * 0b000100..ADC0_tcomp[0] input is selected + * 0b000101..ADC1_tcomp[0] input is selected + * 0b000110..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b000111..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b001000..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b001001..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b001010..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b001011..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b001100..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b001101..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b001110..QDC0_CMP/POS_MATCH input is selected + * 0b001111..QDC1_CMP/POS_MATCH input is selected + * 0b010000..EVTG_OUT0A input is selected + * 0b010001..EVTG_OUT0B input is selected + * 0b010010..EVTG_OUT1A input is selected + * 0b010011..EVTG_OUT1B input is selected + * 0b010100..EVTG_OUT2A input is selected + * 0b010101..EVTG_OUT2B input is selected + * 0b010110..EVTG_OUT3A input is selected + * 0b010111..EVTG_OUT3B input is selected + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..LPTMR0 input is selected + * 0b011011..LPTMR1 input is selected + * 0b011100..Reserved + * 0b011101..Reserved + * 0b011110..Reserved + * 0b011111..Reserved + * 0b100000..Reserved + * 0b100001..Reserved + * 0b100010..LP_FLEXCOMM0 trigger output 3 input is selected + * 0b100011..LP_FLEXCOMM1 trigger output 3 input is selected + * 0b100100..LP_FLEXCOMM2 trigger output 3 input is selected + * 0b100101..LP_FLEXCOMM3 trigger output 3 input is selected + * 0b100110..LP_FLEXCOMM4 trigger output 3 input is selected + * 0b100111..LP_FLEXCOMM5 trigger output 3 input is selected + * 0b101000..LP_FLEXCOMM6 trigger output 3 input is selected + * 0b101001..LP_FLEXCOMM7 trigger output 3 input is selected + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..CMP0_OUT input is selected + * 0b101101..CMP1_OUT input is selected + * 0b101110..Reserved + * 0b101111..Reserved + * *.. + */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_SHIFT)) & INPUTMUX_EXT_TRIGN_EXT_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_EXT_TRIGN_EXT_TRIG */ +#define INPUTMUX_EXT_TRIGN_EXT_TRIG_COUNT (8U) + +/*! @name CMP1_TRIG - CMP1 Input Connections */ +/*! @{ */ + +#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP1 input trigger + * 0b000000..PINT PIN_INT0 input is selected + * 0b000001..PINT PIN_INT7 input is selected + * 0b000010..Reserved + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..CTIMER0_MAT3 input is selected + * 0b000110..CTIMER1_MAT3 input is selected + * 0b000111..CTIMER2_MAT3 input is selected + * 0b001000..CTIMER3_MAT1 input is selected + * 0b001001..CTIMER4_MAT1 input is selected + * 0b001010..Reserved + * 0b001011..Reserved + * 0b001100..PINT GPIO_INT_BMAT input is selected + * 0b001101..ADC0_tcomp[1] input is selected + * 0b001110..ADC1_tcomp[1] input is selected + * 0b001111..Reserved + * 0b010000..Reserved + * 0b010001..PWM0_SM0_MUX_TRIG0/PWM0_SM0_MUX_TRIG1 input is selected + * 0b010010..PWM0_SM1_MUX_TRIG0/PWM0_SM1_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM2_MUX_TRIG0/PWM0_SM2_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM3_MUX_TRIG0/PWM0_SM3_MUX_TRIG1 input is selected + * 0b010101..PWM1_SM0_MUX_TRIG0/PWM1_SM0_MUX_TRIG1 input is selected + * 0b010110..PWM1_SM1_MUX_TRIG0/PWM1_SM1_MUX_TRIG1 input is selected + * 0b010111..PWM1_SM2_MUX_TRIG0/PWM1_SM2_MUX_TRIG1 input is selected + * 0b011000..PWM1_SM3_MUX_TRIG0/PWM1_SM3_MUX_TRIG1 input is selected + * 0b011001..QDC0_CMP/POS_MATCH input is selected + * 0b011010..QDC1_CMP/POS_MATCH input is selected + * 0b011011..EVTG_OUT0A input is selected + * 0b011100..EVTG_OUT0B input is selected + * 0b011101..EVTG_OUT1A input is selected + * 0b011110..EVTG_OUT1B input is selected + * 0b011111..EVTG_OUT2A input is selected + * 0b100000..EVTG_OUT2B input is selected + * 0b100001..EVTG_OUT3A input is selected + * 0b100010..EVTG_OUT3B input is selected + * 0b100011..LPTMR0 input is selected + * 0b100100..LPTMR1 input is selected + * 0b100101..GPIO2 Pin Event Trig 0 input is selected + * 0b100110..GPIO2 Pin Event Trig 1 input is selected + * 0b100111..GPIO3 Pin Event Trig 0 input is selected + * 0b101000..GPIO3 Pin Event Trig 1 input is selected + * *.. + */ +#define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXCOMM0_TRIG - LP_FLEXCOMM0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM0 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT6 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..CTIMER4_MAT0 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM0_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM0_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM1_TRIG - LP_FLEXCOMM1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM1 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT6 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT0 input is selected + * 0b001001..CTIMER3_MAT0 input is selected + * 0b001010..CTIMER4_MAT0 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM1_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM1_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM2_TRIG - LP_FLEXCOMM2 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM2_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM2 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT6 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER3_MAT1 input is selected + * 0b001010..CTIMER4_MAT1 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM2_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM2_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM3_TRIG - LP_FLEXCOMM3 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM3_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM3 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT1 input is selected + * 0b001001..CTIMER3_MAT1 input is selected + * 0b001010..CTIMER4_MAT1 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM3_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM3_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM3_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM4_TRIG - LP_FLEXCOMM4 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM4_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM4 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT2 input is selected + * 0b001001..CTIMER3_MAT2 input is selected + * 0b001010..CTIMER4_MAT2 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM4_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM4_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM4_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM5_TRIG - LP_FLEXCOMM5 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM5_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM5 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT2 input is selected + * 0b001001..CTIMER3_MAT2 input is selected + * 0b001010..CTIMER4_MAT2 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM5_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM5_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM5_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM6_TRIG - LP_FLEXCOMM6 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM6_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM6 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER3_MAT3 input is selected + * 0b001010..CTIMER4_MAT3 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM6_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM6_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM6_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXCOMM7_TRIG - LP_FLEXCOMM7 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXCOMM7_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT (0U) +/*! INP - LP_FLEXCOMM7 trigger input connections + * 0b000000..PINT PIN_INT4 input is selected + * 0b000001..PINT PIN_INT5 input is selected + * 0b000010..PINT PIN_INT7 input is selected + * 0b000011..Reserved + * 0b000100..Reserved + * 0b000101..Reserved + * 0b000110..CTIMER0_MAT1 input is selected + * 0b000111..CTIMER1_MAT1 input is selected + * 0b001000..CTIMER2_MAT3 input is selected + * 0b001001..CTIMER3_MAT3 input is selected + * 0b001010..CTIMER4_MAT3 input is selected + * 0b001011..LPTMR0 input is selected + * 0b001100..LPTMR1 input is selected + * 0b001101..Reserved + * 0b001110..PINT GPIO_INT_BMAT input is selected + * 0b001111..CMP0_OUT input is selected + * 0b010000..CMP1_OUT input is selected + * 0b010001..Reserved + * 0b010010..EVTG_OUT0A input is selected + * 0b010011..EVTG_OUT0B input is selected + * 0b010100..EVTG_OUT1A input is selected + * 0b010101..EVTG_OUT1B input is selected + * 0b010110..EVTG_OUT2A input is selected + * 0b010111..EVTG_OUT2B input is selected + * 0b011000..EVTG_OUT3A input is selected + * 0b011001..EVTG_OUT3B input is selected + * 0b011010..TRIG_IN0 input is selected + * 0b011011..TRIG_IN1 input is selected + * 0b011100..TRIG_IN2 input is selected + * 0b011101..TRIG_IN3 input is selected + * 0b011110..TRIG_IN4 input is selected + * 0b011111..TRIG_IN10 input is selected + * 0b100000..TRIG_IN11 input is selected + * 0b100001..FlexIO CH4 input is selected + * 0b100010..FlexIO CH5 input is selected + * 0b100011..FlexIO CH6 input is selected + * 0b100100..FlexIO CH7 input is selected + * 0b100101..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100110..GPIO2 Pin Event Trig 0 input is selected + * 0b100111..GPIO2 Pin Event Trig 1 input is selected + * 0b101000..GPIO3 Pin Event Trig 0 input is selected + * 0b101001..GPIO3 Pin Event Trig 1 input is selected + * 0b101010..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXCOMM7_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXCOMM7_TRIG_INP_SHIFT)) & INPUTMUX_FLEXCOMM7_TRIG_INP_MASK) +/*! @} */ + +/*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) +/*! INP - Input number for FlexIO0. + * 0b0000000..PINT PIN_INT4 input is selected + * 0b0000001..PINT PIN_INT5 input is selected + * 0b0000010..PINT PIN_INT6 input is selected + * 0b0000011..PINT PIN_INT7 input is selected + * 0b0000100..Reserved + * 0b0000101..Reserved + * 0b0000110..Reserved + * 0b0000111..Reserved + * 0b0001000..Reserved + * 0b0001001..T0_MAT1 input is selected + * 0b0001010..T1_MAT1 input is selected + * 0b0001011..T2_MAT1 input is selected + * 0b0001100..T3_MAT1 input is selected + * 0b0001101..T4_MAT1 input is selected + * 0b0001110..LPTMR0 input is selected + * 0b0001111..LPTMR1 input is selected + * 0b0010000..Reserved + * 0b0010001..PINT GPIO_INT_BMAT input is selected + * 0b0010010..ADC0_tcomp[0] input is selected + * 0b0010011..ADC0_tcomp[1] input is selected + * 0b0010100..ADC0_tcomp[2] input is selected + * 0b0010101..ADC0_tcomp[3] input is selected + * 0b0010110..ADC1_tcomp[0] input is selected + * 0b0010111..ADC1_tcomp[1] input is selected + * 0b0011000..ADC1_tcomp[2] input is selected + * 0b0011001..ADC1_tcomp[3] input is selected + * 0b0011010..CMP0_OUT input is selected + * 0b0011011..CMP1_OUT input is selected + * 0b0011100..Reserved + * 0b0011101..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0100001..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100010..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100011..PWM0_SM3_MUX_TRIG0 input is selected + * 0b0100100..PWM0_SM3_MUX_TRIG1 input is selected + * 0b0100101..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100110..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100111..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0101000..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0101001..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0101010..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101011..PWM1_SM3_MUX_TRIG0 input is selected + * 0b0101100..PWM1_SM3_MUX_TRIG1 input is selected + * 0b0101101..EVTG_OUT0A input is selected + * 0b0101110..EVTG_OUT0B input is selected + * 0b0101111..EVTG_OUT1A input is selected + * 0b0110000..EVTG_OUT1B input is selected + * 0b0110001..EVTG_OUT2A input is selected + * 0b0110010..EVTG_OUT2B input is selected + * 0b0110011..EVTG_OUT3A input is selected + * 0b0110100..EVTG_OUT3B input is selected + * 0b0110101..TRIG_IN0 input is selected + * 0b0110110..TRIG_IN1 input is selected + * 0b0110111..TRIG_IN2 input is selected + * 0b0111000..TRIG_IN3 input is selected + * 0b0111001..TRIG_IN4 input is selected + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..Reserved + * 0b0111111..LP_FLEXCOMM0 trig 0 (lpuart_trg_txword) input is selected + * 0b1000000..LP_FLEXCOMM0 trig 1 (lpuart_trg_rxword) input is selected + * 0b1000001..LP_FLEXCOMM0 trig 2 (lpuart_trg_rxidle) input is selected + * 0b1000010..LP_FLEXCOMM1 trig 0 input is selected + * 0b1000011..LP_FLEXCOMM1 trig 1 input is selected + * 0b1000100..LP_FLEXCOMM1 trig 2 input is selected + * 0b1000101..LP_FLEXCOMM2 trig 0 input is selected + * 0b1000110..LP_FLEXCOMM2 trig 1 input is selected + * 0b1000111..LP_FLEXCOMM2 trig 2 input is selected + * 0b1001000..LP_FLEXCOMM3 trig 0 input is selected + * 0b1001001..LP_FLEXCOMM3 trig 1 input is selected + * 0b1001010..LP_FLEXCOMM3 trig 2 input is selected + * 0b1001011..LP_FLEXCOMM3 trig 3 input is selected + * 0b1001100..WUU input is selected + * *.. + */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (8U) + +/*! @name DMA0_REQ_ENABLE0 - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - This register is used to enable and disable PINT0 INT0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - This register is used to enable and disable PINT0 INT1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - This register is used to enable and disable PINT0 INT2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - This register is used to enable and disable PINT0 INT3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - This register is used to enable and disable WUU0 wake up event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - This register is used to enable and disable MICFIL0 FIFO_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - This register is used to enable and disable ADC0 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - This register is used to enable and disable ADC0 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - This register is used to enable and disable ADC1 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - This register is used to enable and disable ADC1 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - This register is used to enable and disable CMP0 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - This register is used to enable and disable CMP1 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - This register is used to enable and disable EVTG0 OUT0A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_SET - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_SET_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_CLR - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to REQ9_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_CLR_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE0_TOG - DMA0 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT (3U) +/*! REQ3_EN0 - Writing a 1 to REQ3_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ3_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT (4U) +/*! REQ4_EN0 - Writing a 1 to REQ4_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ4_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT (5U) +/*! REQ5_EN0 - Writing a 1 to REQ5_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ5_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT (6U) +/*! REQ6_EN0 - Writing a 1 to REQ6_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ6_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT (7U) +/*! REQ7_EN0 - Writing a 1 to REQ7_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ7_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT (8U) +/*! REQ8_EN0 - Writing a 1 to REQ8_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ8_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT (9U) +/*! REQ9_EN0 - Writing a 1 to RE9_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ9_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT (10U) +/*! REQ10_EN0 - Writing a 1 to REQ10_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ10_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT (11U) +/*! REQ11_EN0 - Writing a 1 to REQ11_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ11_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT (12U) +/*! REQ12_EN0 - Writing a 1 to REQ12_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ12_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT (13U) +/*! REQ13_EN0 - Writing a 1 to REQ13_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ13_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT (14U) +/*! REQ14_EN0 - Writing a 1 to REQ14_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ14_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT (15U) +/*! REQ15_EN0 - Writing a 1 to REQ15_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ15_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT (16U) +/*! REQ16_EN0 - Writing a 1 to REQ16_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ16_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT (17U) +/*! REQ17_EN0 - Writing a 1 to REQ17_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ17_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT (18U) +/*! REQ18_EN0 - Writing a 1 to REQ18_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ18_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT (21U) +/*! REQ21_EN0 - Writing a 1 to REQ21_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ21_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT (22U) +/*! REQ22_EN0 - Writing a 1 to REQ22_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ22_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT (23U) +/*! REQ23_EN0 - Writing a 1 to REQ23_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ23_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK (0x1000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT (24U) +/*! REQ24_EN0 - Writing a 1 to REQ24_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ24_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT (28U) +/*! REQ28_EN0 - Writing a 1 to REQ28_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ28_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT (29U) +/*! REQ29_EN0 - Writing a 1 to REQ29_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ29_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT (31U) +/*! REQ31_EN0 - Writing a 1 to REQ31_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE0. */ +#define INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE0_TOG_REQ31_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1 - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - This register is used to enable and disable EVTG0 OUT0B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - This register is used to enable and disable EVTG0 OUT1A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - This register is used to enable and disable EVTG0 OUT1B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - This register is used to enable and disable EVTG0 OUT2A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - This register is used to enable and disable EVTG0 OUT2B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - This register is used to enable and disable EVTG0 OUT3A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - This register is used to enable and disable EVTG0 OUT3B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - This register is used to enable and disable PWM0 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - This register is used to enable and disable PWM0 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - This register is used to enable and disable PWM0 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - This register is used to enable and disable PWM0 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - This register is used to enable and disable PWM0 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - This register is used to enable and disable PWM0 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - This register is used to enable and disable PWM0 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - This register is used to enable and disable PWM0 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - This register is used to enable and disable PWM1 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - This register is used to enable and disable PWM1 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - This register is used to enable and disable PWM1 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - This register is used to enable and disable PWM1 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - This register is used to enable and disable PWM1 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - This register is used to enable and disable PWM1 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - This register is used to enable and disable PWM1 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - This register is used to enable and disable PWM1 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - This register is used to enable and disable LPTMR0 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - This register is used to enable and disable LPTMR1 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - This register is used to enable and disable CAN0 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - This register is used to enable and disable CAN1 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_SET - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_SET_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_CLR - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ45_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_CLR_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE1_TOG - DMA0 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT (0U) +/*! REQ32_EN0 - Writing a 1 to REQ32_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ32_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT (1U) +/*! REQ33_EN0 - Writing a 1 to REQ33_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ33_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT (2U) +/*! REQ34_EN0 - Writing a 1 to REQ34_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ34_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT (3U) +/*! REQ35_EN0 - Writing a 1 to REQ35_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ35_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT (4U) +/*! REQ36_EN0 - Writing a 1 to REQ36_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ36_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT (5U) +/*! REQ37_EN0 - Writing a 1 to REQ37_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ37_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT (6U) +/*! REQ38_EN0 - Writing a 1 to REQ38_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ38_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT (7U) +/*! REQ39_EN0 - Writing a 1 to REQ39_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ39_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT (8U) +/*! REQ40_EN0 - Writing a 1 to REQ40_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ40_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT (9U) +/*! REQ41_EN0 - Writing a 1 to REQ41_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ41_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT (10U) +/*! REQ42_EN0 - Writing a 1 to REQ42_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ42_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT (11U) +/*! REQ43_EN0 - Writing a 1 to REQ43_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ43_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT (12U) +/*! REQ44_EN0 - Writing a 1 to REQ44_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ44_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT (13U) +/*! REQ45_EN0 - Writing a 1 to REQ55_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ45_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT (14U) +/*! REQ46_EN0 - Writing a 1 to REQ46_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ46_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT (15U) +/*! REQ47_EN0 - Writing a 1 to REQ47_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ47_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT (16U) +/*! REQ48_EN0 - Writing a 1 to REQ48_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ48_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT (17U) +/*! REQ49_EN0 - Writing a 1 to REQ49_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ49_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT (18U) +/*! REQ50_EN0 - Writing a 1 to REQ50_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ50_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT (19U) +/*! REQ51_EN0 - Writing a 1 to REQ51_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ51_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT (20U) +/*! REQ52_EN0 - Writing a 1 to REQ52_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ52_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT (21U) +/*! REQ53_EN0 - Writing a 1 to REQ53_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ53_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT (22U) +/*! REQ54_EN0 - Writing a 1 to REQ54_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ54_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK (0x2000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT (25U) +/*! REQ57_EN0 - Writing a 1 to REQ57_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ57_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK (0x4000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT (26U) +/*! REQ58_EN0 - Writing a 1 to REQ58_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ58_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK (0x8000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT (27U) +/*! REQ59_EN0 - Writing a 1 to REQ59_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ59_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK (0x10000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT (28U) +/*! REQ60_EN0 - Writing a 1 to REQ60_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ60_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK (0x20000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT (29U) +/*! REQ61_EN0 - Writing a 1 to REQ61_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ61_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK (0x40000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT (30U) +/*! REQ62_EN0 - Writing a 1 to REQ62_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ62_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT (31U) +/*! REQ63_EN0 - Writing a 1 to REQ63_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE1. */ +#define INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE1_TOG_REQ63_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2 - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - This register is used to enable and disable FlexIO0 shift register 3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - This register is used to enable and disable FlexIO0 shift register 4 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - This register is used to enable and disable FlexIO0 shift register 5 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - This register is used to enable and disable FlexIO0 shift register 6 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - This register is used to enable and disable FlexIO0 shift register 7 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - This register is used to enable and disable LP_FLEXCOMM0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - This register is used to enable and disable LP_FLEXCOMM1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - This register is used to enable and disable LP_FLEXCOMM2 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - This register is used to enable and disable LP_FLEXCOMM3 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - This register is used to enable and disable LP_FLEXCOMM4 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - This register is used to enable and disable LP_FLEXCOMM5 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - This register is used to enable and disable LP_FLEXCOMM6 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - This register is used to enable and disable LP_FLEXCOMM7 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - This register is used to enable and disable I3C0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_SET - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ876_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_SET_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_CLR - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_CLR_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE2_TOG - DMA0 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT (0U) +/*! REQ64_EN0 - Writing a 1 to REQ64_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ64_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT (1U) +/*! REQ65_EN0 - Writing a 1 to REQ65_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ65_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT (2U) +/*! REQ66_EN0 - Writing a 1 to REQ66_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ66_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT (3U) +/*! REQ67_EN0 - Writing a 1 to REQ67_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ67_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT (4U) +/*! REQ68_EN0 - Writing a 1 to REQ68_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ68_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT (5U) +/*! REQ69_EN0 - Writing a 1 to REQ69_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ69_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT (6U) +/*! REQ70_EN0 - Writing a 1 to REQ70_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ70_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK (0x80U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT (7U) +/*! REQ71_EN0 - Writing a 1 to REQ71_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ71_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK (0x100U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT (8U) +/*! REQ72_EN0 - Writing a 1 to REQ72_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ72_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK (0x200U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT (9U) +/*! REQ73_EN0 - Writing a 1 to REQ73_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ73_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK (0x400U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT (10U) +/*! REQ74_EN0 - Writing a 1 to REQ74_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ74_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK (0x800U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT (11U) +/*! REQ75_EN0 - Writing a 1 to REQ75_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ75_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT (12U) +/*! REQ76_EN0 - Writing a 1 to REQ76_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ76_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT (13U) +/*! REQ77_EN0 - Writing a 1 to REQ77_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ77_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT (14U) +/*! REQ78_EN0 - Writing a 1 to REQ78_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ78_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT (15U) +/*! REQ79_EN0 - Writing a 1 to REQ79_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ79_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT (16U) +/*! REQ80_EN0 - Writing a 1 to REQ80_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ80_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT (17U) +/*! REQ81_EN0 - Writing a 1 to REQ81_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ81_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT (18U) +/*! REQ82_EN0 - Writing a 1 to REQ82_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ82_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT (19U) +/*! REQ83_EN0 - Writing a 1 to REQ83_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ83_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT (20U) +/*! REQ84_EN0 - Writing a 1 to REQ84_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ84_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK (0x80000000U) +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT (31U) +/*! REQ95_EN0 - Writing a 1 to REQ95_EN0 in this register toggles the corresponding bit in DMA0_REQ_ENABLE2. */ +#define INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE2_TOG_REQ95_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3 - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - This register is used to enable and disable I3C0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - This register is used to enable and disable I3C1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - This register is used to enable and disable I3C1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - This register is used to enable and disable SAI0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - This register is used to enable and disable SAI0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - This register is used to enable and disable SAI1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - This register is used to enable and disable SAI1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - This register is used to enable and disable GPIO0 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - This register is used to enable and disable GPIO0 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - This register is used to enable and disable GPIO1 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - This register is used to enable and disable GPIO1 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - This register is used to enable and disable GPIO2 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - This register is used to enable and disable GPIO2 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - This register is used to enable and disable GPIO3 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - This register is used to enable and disable GPIO3 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - This register is used to enable and disable GPIO4 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - This register is used to enable and disable GPIO4 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - This register is used to enable and disable GPIO5 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - This register is used to enable and disable GPIO5 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3_SET - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_SET_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA0_REQ_ENABLE3_CLR - DMA0 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK (0x1U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT (0U) +/*! REQ96_EN0 - Writing a 1 to REQ96_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ96_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK (0x2U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT (1U) +/*! REQ97_EN0 - Writing a 1 to REQ97_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ97_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK (0x4U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT (2U) +/*! REQ98_EN0 - Writing a 1 to REQ98_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ98_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK (0x8U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT (3U) +/*! REQ99_EN0 - Writing a 1 to REQ99_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ99_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK (0x10U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT (4U) +/*! REQ100_EN0 - Writing a 1 to REQ100_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ100_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK (0x20U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT (5U) +/*! REQ101_EN0 - Writing a 1 to REQ101_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ101_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK (0x40U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT (6U) +/*! REQ102_EN0 - Writing a 1 to REQ102_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ102_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK (0x1000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT (12U) +/*! REQ108_EN0 - Writing a 1 to REQ108_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ108_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK (0x2000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT (13U) +/*! REQ109_EN0 - Writing a 1 to REQ109_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ109_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK (0x4000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT (14U) +/*! REQ110_EN0 - Writing a 1 to REQ110_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ110_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK (0x8000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT (15U) +/*! REQ111_EN0 - Writing a 1 to REQ111_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ111_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK (0x10000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT (16U) +/*! REQ112_EN0 - Writing a 1 to REQ112_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ112_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK (0x20000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT (17U) +/*! REQ113_EN0 - Writing a 1 to REQ113_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ113_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK (0x40000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT (18U) +/*! REQ114_EN0 - Writing a 1 to REQ114_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ114_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK (0x80000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT (19U) +/*! REQ115_EN0 - Writing a 1 to REQ115_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ115_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK (0x100000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT (20U) +/*! REQ116_EN0 - Writing a 1 to REQ116_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ116_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK (0x200000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT (21U) +/*! REQ117_EN0 - Writing a 1 to REQ117_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ117_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK (0x400000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT (22U) +/*! REQ118_EN0 - Writing a 1 to REQ118_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ118_EN0_MASK) + +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK (0x800000U) +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT (23U) +/*! REQ119_EN0 - Writing a 1 to REQ119_EN0 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_SHIFT)) & INPUTMUX_DMA0_REQ_ENABLE3_CLR_REQ119_EN0_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0 - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - This register is used to enable and disable PINT0 INT0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - This register is used to enable and disable PINT0 INT1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - This register is used to enable and disable PINT0 INT2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - This register is used to enable and disable PINT0 INT3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - This register is used to enable and disable CTIMER0 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - This register is used to enable and disable CTIMER1 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - This register is used to enable and disable CTIMER2 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - This register is used to enable and disable CTIMER3 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - This register is used to enable and disable CTIMER4 DMAREQ_M1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - This register is used to enable and disable WUU0 wake up event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - This register is used to enable and disable MICFIL0 FIFO_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - This register is used to enable and disable ADC0 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - This register is used to enable and disable ADC0 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - This register is used to enable and disable ADC1 FIFO A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - This register is used to enable and disable ADC1 FIFO B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - This register is used to enable and disable CMP0 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - This register is used to enable and disable CMP1 DMA_request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - This register is used to enable and disable EVTG0 OUT0A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_SET - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_SET_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_CLR - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to REQ9_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_CLR_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE0_TOG - DMA1 Request Enable0 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT (3U) +/*! REQ3_EN1 - Writing a 1 to REQ3_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ3_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT (4U) +/*! REQ4_EN1 - Writing a 1 to REQ4_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ4_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT (5U) +/*! REQ5_EN1 - Writing a 1 to REQ5_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ5_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT (6U) +/*! REQ6_EN1 - Writing a 1 to REQ6_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ6_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT (7U) +/*! REQ7_EN1 - Writing a 1 to REQ7_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ7_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT (8U) +/*! REQ8_EN1 - Writing a 1 to REQ8_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ8_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT (9U) +/*! REQ9_EN1 - Writing a 1 to RE9_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ9_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT (10U) +/*! REQ10_EN1 - Writing a 1 to REQ10_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ10_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT (11U) +/*! REQ11_EN1 - Writing a 1 to REQ11_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ11_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT (12U) +/*! REQ12_EN1 - Writing a 1 to REQ12_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ12_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT (13U) +/*! REQ13_EN1 - Writing a 1 to REQ13_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ13_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT (14U) +/*! REQ14_EN1 - Writing a 1 to REQ14_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ14_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT (15U) +/*! REQ15_EN1 - Writing a 1 to REQ15_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ15_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT (16U) +/*! REQ16_EN1 - Writing a 1 to REQ16_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ16_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT (17U) +/*! REQ17_EN1 - Writing a 1 to REQ17_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ17_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT (18U) +/*! REQ18_EN1 - Writing a 1 to REQ18_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ18_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT (21U) +/*! REQ21_EN1 - Writing a 1 to REQ21_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ21_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT (22U) +/*! REQ22_EN1 - Writing a 1 to REQ22_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ22_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT (23U) +/*! REQ23_EN1 - Writing a 1 to REQ23_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ23_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT (24U) +/*! REQ24_EN1 - Writing a 1 to REQ24_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ24_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT (28U) +/*! REQ28_EN1 - Writing a 1 to REQ28_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ28_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT (29U) +/*! REQ29_EN1 - Writing a 1 to REQ29_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ29_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT (31U) +/*! REQ31_EN1 - Writing a 1 to REQ31_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE0. */ +#define INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE0_TOG_REQ31_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1 - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - This register is used to enable and disable EVTG0 OUT0B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - This register is used to enable and disable EVTG0 OUT1A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - This register is used to enable and disable EVTG0 OUT1B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - This register is used to enable and disable EVTG0 OUT2A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - This register is used to enable and disable EVTG0 OUT2B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - This register is used to enable and disable EVTG0 OUT3A request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - This register is used to enable and disable EVTG0 OUT3B request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - This register is used to enable and disable PWM0 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - This register is used to enable and disable PWM0 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - This register is used to enable and disable PWM0 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - This register is used to enable and disable PWM0 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - This register is used to enable and disable PWM0 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - This register is used to enable and disable PWM0 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - This register is used to enable and disable PWM0 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - This register is used to enable and disable PWM0 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - This register is used to enable and disable PWM1 Req_capt0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - This register is used to enable and disable PWM1 Req_capt1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - This register is used to enable and disable PWM1 Req_capt2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - This register is used to enable and disable PWM1 Req_capt3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - This register is used to enable and disable PWM1 Req_val0 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - This register is used to enable and disable PWM1 Req_val1 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - This register is used to enable and disable PWM1 Req_val2 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - This register is used to enable and disable PWM1 Req_val3 request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - This register is used to enable and disable LPTMR0 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - This register is used to enable and disable LPTMR1 counter match event request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - This register is used to enable and disable CAN0 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - This register is used to enable and disable CAN1 DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - This register is used to enable and disable FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - This register is used to enable and disable FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - This register is used to enable and disable FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_SET - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_SET_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_CLR - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ45_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_CLR_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE1_TOG - DMA1 Request Enable1 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT (0U) +/*! REQ32_EN1 - Writing a 1 to REQ32_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ32_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT (1U) +/*! REQ33_EN1 - Writing a 1 to REQ33_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ33_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT (2U) +/*! REQ34_EN1 - Writing a 1 to REQ34_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ34_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT (3U) +/*! REQ35_EN1 - Writing a 1 to REQ35_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ35_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT (4U) +/*! REQ36_EN1 - Writing a 1 to REQ36_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ36_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT (5U) +/*! REQ37_EN1 - Writing a 1 to REQ37_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ37_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT (6U) +/*! REQ38_EN1 - Writing a 1 to REQ38_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ38_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT (7U) +/*! REQ39_EN1 - Writing a 1 to REQ39_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ39_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT (8U) +/*! REQ40_EN1 - Writing a 1 to REQ40_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ40_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT (9U) +/*! REQ41_EN1 - Writing a 1 to REQ41_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ41_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT (10U) +/*! REQ42_EN1 - Writing a 1 to REQ42_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ42_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT (11U) +/*! REQ43_EN1 - Writing a 1 to REQ43_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ43_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT (12U) +/*! REQ44_EN1 - Writing a 1 to REQ44_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ44_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT (13U) +/*! REQ45_EN1 - Writing a 1 to REQ55_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ45_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT (14U) +/*! REQ46_EN1 - Writing a 1 to REQ46_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ46_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT (15U) +/*! REQ47_EN1 - Writing a 1 to REQ47_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ47_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT (16U) +/*! REQ48_EN1 - Writing a 1 to REQ48_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ48_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT (17U) +/*! REQ49_EN1 - Writing a 1 to REQ49_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ49_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT (18U) +/*! REQ50_EN1 - Writing a 1 to REQ50_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ50_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT (19U) +/*! REQ51_EN1 - Writing a 1 to REQ51_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ51_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT (20U) +/*! REQ52_EN1 - Writing a 1 to REQ52_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ52_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT (21U) +/*! REQ53_EN1 - Writing a 1 to REQ53_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ53_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT (22U) +/*! REQ54_EN1 - Writing a 1 to REQ54_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ54_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT (25U) +/*! REQ57_EN1 - Writing a 1 to REQ57_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ57_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT (26U) +/*! REQ58_EN1 - Writing a 1 to REQ58_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ58_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT (27U) +/*! REQ59_EN1 - Writing a 1 to REQ59_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ59_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT (28U) +/*! REQ60_EN1 - Writing a 1 to REQ60_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ60_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT (29U) +/*! REQ61_EN1 - Writing a 1 to REQ61_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ61_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT (30U) +/*! REQ62_EN1 - Writing a 1 to REQ62_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ62_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT (31U) +/*! REQ63_EN1 - Writing a 1 to REQ63_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE1. */ +#define INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE1_TOG_REQ63_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2 - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - This register is used to enable and disable FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - This register is used to enable and disable FlexIO0 Shifter4 Status DMA request OR Timer4 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - This register is used to enable and disable FlexIO0 Shifter5 Status DMA request OR Timer5 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - This register is used to enable and disable FlexIO0 Shifter6 Status DMA request OR Timer6 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - This register is used to enable and disable FlexIO0 Shifter7 Status DMA request OR Timer7 Status DMA request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - This register is used to enable and disable LP_FLEXCOMM0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - This register is used to enable and disable LP_FLEXCOMM0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - This register is used to enable and disable LP_FLEXCOMM1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - This register is used to enable and disable LP_FLEXCOMM1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - This register is used to enable and disable LP_FLEXCOMM2 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - This register is used to enable and disable LP_FLEXCOMM2 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - This register is used to enable and disable LP_FLEXCOMM3 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - This register is used to enable and disable LP_FLEXCOMM3 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - This register is used to enable and disable LP_FLEXCOMM4 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - This register is used to enable and disable LP_FLEXCOMM4 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - This register is used to enable and disable LP_FLEXCOMM5 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - This register is used to enable and disable LP_FLEXCOMM5 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - This register is used to enable and disable LP_FLEXCOMM6 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - This register is used to enable and disable LP_FLEXCOMM6 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - This register is used to enable and disable LP_FLEXCOMM7 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - This register is used to enable and disable LP_FLEXCOMM7 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - This register is used to enable and disable I3C0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_SET - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ876_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register sets the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_SET_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_CLR - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register clears the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_CLR_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE2_TOG - DMA1 Request Enable2 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT (0U) +/*! REQ64_EN1 - Writing a 1 to REQ64_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ64_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT (1U) +/*! REQ65_EN1 - Writing a 1 to REQ65_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ65_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT (2U) +/*! REQ66_EN1 - Writing a 1 to REQ66_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ66_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT (3U) +/*! REQ67_EN1 - Writing a 1 to REQ67_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ67_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT (4U) +/*! REQ68_EN1 - Writing a 1 to REQ68_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ68_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT (5U) +/*! REQ69_EN1 - Writing a 1 to REQ69_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ69_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT (6U) +/*! REQ70_EN1 - Writing a 1 to REQ70_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ70_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT (7U) +/*! REQ71_EN1 - Writing a 1 to REQ71_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ71_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT (8U) +/*! REQ72_EN1 - Writing a 1 to REQ72_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ72_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT (9U) +/*! REQ73_EN1 - Writing a 1 to REQ73_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ73_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT (10U) +/*! REQ74_EN1 - Writing a 1 to REQ74_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ74_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT (11U) +/*! REQ75_EN1 - Writing a 1 to REQ75_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ75_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT (12U) +/*! REQ76_EN1 - Writing a 1 to REQ76_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ76_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT (13U) +/*! REQ77_EN1 - Writing a 1 to REQ77_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ77_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT (14U) +/*! REQ78_EN1 - Writing a 1 to REQ78_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ78_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT (15U) +/*! REQ79_EN1 - Writing a 1 to REQ79_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ79_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT (16U) +/*! REQ80_EN1 - Writing a 1 to REQ80_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ80_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT (17U) +/*! REQ81_EN1 - Writing a 1 to REQ81_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ81_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT (18U) +/*! REQ82_EN1 - Writing a 1 to REQ82_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ82_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT (19U) +/*! REQ83_EN1 - Writing a 1 to REQ83_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ83_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT (20U) +/*! REQ84_EN1 - Writing a 1 to REQ84_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ84_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT (21U) +/*! REQ85_EN1 - Writing a 1 to REQ85_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ85_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT (22U) +/*! REQ86_EN1 - Writing a 1 to REQ86_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ86_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT (23U) +/*! REQ87_EN1 - Writing a 1 to REQ87_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ87_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT (24U) +/*! REQ88_EN1 - Writing a 1 to REQ88_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ88_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT (25U) +/*! REQ89_EN1 - Writing a 1 to REQ89_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ89_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK (0x4000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT (26U) +/*! REQ90_EN1 - Writing a 1 to REQ90_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ90_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK (0x8000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT (27U) +/*! REQ91_EN1 - Writing a 1 to REQ91_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ91_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK (0x10000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT (28U) +/*! REQ92_EN1 - Writing a 1 to REQ92_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ92_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK (0x20000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT (29U) +/*! REQ93_EN1 - Writing a 1 to REQ93_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ93_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK (0x40000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT (30U) +/*! REQ94_EN1 - Writing a 1 to REQ94_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ94_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK (0x80000000U) +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT (31U) +/*! REQ95_EN1 - Writing a 1 to REQ95_EN1 in this register toggles the corresponding bit in DMA1_REQ_ENABLE2. */ +#define INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE2_TOG_REQ95_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3 - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - This register is used to enable and disable I3C0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - This register is used to enable and disable I3C1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - This register is used to enable and disable I3C1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - This register is used to enable and disable SAI0 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - This register is used to enable and disable SAI0 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - This register is used to enable and disable SAI1 receive request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - This register is used to enable and disable SAI1 transmit request. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - This register is used to enable and disable GPIO0 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - This register is used to enable and disable GPIO0 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - This register is used to enable and disable GPIO1 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - This register is used to enable and disable GPIO1 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - This register is used to enable and disable GPIO2 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - This register is used to enable and disable GPIO2 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - This register is used to enable and disable GPIO3 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - This register is used to enable and disable GPIO3 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - This register is used to enable and disable GPIO4 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - This register is used to enable and disable GPIO4 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - This register is used to enable and disable GPIO5 pin event request 0. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - This register is used to enable and disable GPIO5 pin event request 1. + * 0b0..Disable + * 0b1..Enable + */ +#define INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_REQ119_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3_SET - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT (7U) +/*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ103_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT (8U) +/*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ104_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT (9U) +/*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ105_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT (10U) +/*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ106_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT (11U) +/*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ107_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ119_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT (24U) +/*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ120_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT (25U) +/*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register sets the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_SET_REQ121_EN1_MASK) +/*! @} */ + +/*! @name DMA1_REQ_ENABLE3_CLR - DMA1 Request Enable3 */ +/*! @{ */ + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK (0x1U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT (0U) +/*! REQ96_EN1 - Writing a 1 to REQ96_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ96_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK (0x2U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT (1U) +/*! REQ97_EN1 - Writing a 1 to REQ97_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ97_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK (0x4U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT (2U) +/*! REQ98_EN1 - Writing a 1 to REQ98_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ98_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK (0x8U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT (3U) +/*! REQ99_EN1 - Writing a 1 to REQ99_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ99_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK (0x10U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT (4U) +/*! REQ100_EN1 - Writing a 1 to REQ100_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ100_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK (0x20U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT (5U) +/*! REQ101_EN1 - Writing a 1 to REQ101_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ101_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK (0x40U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT (6U) +/*! REQ102_EN1 - Writing a 1 to REQ102_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ102_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK (0x80U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT (7U) +/*! REQ103_EN1 - Writing a 1 to REQ103_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ103_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK (0x100U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT (8U) +/*! REQ104_EN1 - Writing a 1 to REQ104_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ104_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK (0x200U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT (9U) +/*! REQ105_EN1 - Writing a 1 to REQ105_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ105_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK (0x400U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT (10U) +/*! REQ106_EN1 - Writing a 1 to REQ106_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ106_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK (0x800U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT (11U) +/*! REQ107_EN1 - Writing a 1 to REQ107_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ107_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK (0x1000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT (12U) +/*! REQ108_EN1 - Writing a 1 to REQ108_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ108_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK (0x2000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT (13U) +/*! REQ109_EN1 - Writing a 1 to REQ109_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ109_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK (0x4000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT (14U) +/*! REQ110_EN1 - Writing a 1 to REQ110_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ110_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK (0x8000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT (15U) +/*! REQ111_EN1 - Writing a 1 to REQ111_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ111_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK (0x10000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT (16U) +/*! REQ112_EN1 - Writing a 1 to REQ112_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ112_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK (0x20000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT (17U) +/*! REQ113_EN1 - Writing a 1 to REQ113_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ113_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK (0x40000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT (18U) +/*! REQ114_EN1 - Writing a 1 to REQ114_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ114_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK (0x80000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT (19U) +/*! REQ115_EN1 - Writing a 1 to REQ115_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ115_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK (0x100000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT (20U) +/*! REQ116_EN1 - Writing a 1 to REQ116_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ116_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK (0x200000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT (21U) +/*! REQ117_EN1 - Writing a 1 to REQ117_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ117_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK (0x400000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT (22U) +/*! REQ118_EN1 - Writing a 1 to REQ118_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ118_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK (0x800000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT (23U) +/*! REQ119_EN1 - Writing a 1 to REQ119_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ119_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK (0x1000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT (24U) +/*! REQ120_EN1 - Writing a 1 to REQ120_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3 */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ120_EN1_MASK) + +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK (0x2000000U) +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT (25U) +/*! REQ121_EN1 - Writing a 1 to REQ121_EN1 in this register clears the corresponding bit in DMA0_REQ_ENABLE3. */ +#define INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_SHIFT)) & INPUTMUX_DMA1_REQ_ENABLE3_CLR_REQ121_EN1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x50006000u) + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE_NS (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0_NS ((INPUTMUX_Type *)INPUTMUX0_BASE_NS) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS_NS { INPUTMUX0_BASE_NS } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS_NS { INPUTMUX0_NS } +#else + /** Peripheral INPUTMUX0 base address */ + #define INPUTMUX0_BASE (0x40006000u) + /** Peripheral INPUTMUX0 base pointer */ + #define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) + /** Array initializer of INPUTMUX peripheral base addresses */ + #define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } + /** Array initializer of INPUTMUX peripheral base pointers */ + #define INPUTMUX_BASE_PTRS { INPUTMUX0 } +#endif +/* Backward compatibility for INPUTMUX */ +#define INPUTMUX INPUTMUX0 + + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INTM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INTM_Peripheral_Access_Layer INTM Peripheral Access Layer + * @{ + */ + +/** INTM - Register Layout Typedef */ +typedef struct { + __IO uint32_t INTM_MM; /**< Monitor Mode, offset: 0x0 */ + __O uint32_t INTM_IACK; /**< Interrupt Acknowledge, offset: 0x4 */ + struct { /* offset: 0x8, array step: 0x10 */ + __IO uint32_t INTM_IRQSEL; /**< Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3, array offset: 0x8, array step: 0x10 */ + __IO uint32_t INTM_LATENCY; /**< Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3, array offset: 0xC, array step: 0x10 */ + __IO uint32_t INTM_TIMER; /**< Timer for Monitor 0..Timer for Monitor 3, array offset: 0x10, array step: 0x10 */ + __I uint32_t INTM_STATUS; /**< Status for Monitor 0..Status for Monitor 3, array offset: 0x14, array step: 0x10 */ + } MON[4]; +} INTM_Type; + +/* ---------------------------------------------------------------------------- + -- INTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INTM_Register_Masks INTM Register Masks + * @{ + */ + +/*! @name INTM_MM - Monitor Mode */ +/*! @{ */ + +#define INTM_INTM_MM_MM_MASK (0x1U) +#define INTM_INTM_MM_MM_SHIFT (0U) +/*! MM - Monitor Mode + * 0b1..Enable + * 0b0..Disable + */ +#define INTM_INTM_MM_MM(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_MM_MM_SHIFT)) & INTM_INTM_MM_MM_MASK) +/*! @} */ + +/*! @name INTM_IACK - Interrupt Acknowledge */ +/*! @{ */ + +#define INTM_INTM_IACK_IRQ_MASK (0x3FFU) +#define INTM_INTM_IACK_IRQ_SHIFT (0U) +/*! IRQ - Interrupt Request */ +#define INTM_INTM_IACK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_INTM_IACK_IRQ_SHIFT)) & INTM_INTM_IACK_IRQ_MASK) +/*! @} */ + +/*! @name MON_INTM_IRQSEL - Interrupt Request Select for Monitor 0..Interrupt Request Select for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_IRQSEL_IRQ_MASK (0x3FFU) +#define INTM_MON_INTM_IRQSEL_IRQ_SHIFT (0U) +/*! IRQ - Interrupt Request */ +#define INTM_MON_INTM_IRQSEL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_IRQSEL_IRQ_SHIFT)) & INTM_MON_INTM_IRQSEL_IRQ_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_IRQSEL */ +#define INTM_MON_INTM_IRQSEL_COUNT (4U) + +/*! @name MON_INTM_LATENCY - Interrupt Latency for Monitor 0..Interrupt Latency for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_LATENCY_LAT_MASK (0xFFFFFFU) +#define INTM_MON_INTM_LATENCY_LAT_SHIFT (0U) +/*! LAT - Latency */ +#define INTM_MON_INTM_LATENCY_LAT(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_LATENCY_LAT_SHIFT)) & INTM_MON_INTM_LATENCY_LAT_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_LATENCY */ +#define INTM_MON_INTM_LATENCY_COUNT (4U) + +/*! @name MON_INTM_TIMER - Timer for Monitor 0..Timer for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_TIMER_TIMER_MASK (0xFFFFFFU) +#define INTM_MON_INTM_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer */ +#define INTM_MON_INTM_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_TIMER_TIMER_SHIFT)) & INTM_MON_INTM_TIMER_TIMER_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_TIMER */ +#define INTM_MON_INTM_TIMER_COUNT (4U) + +/*! @name MON_INTM_STATUS - Status for Monitor 0..Status for Monitor 3 */ +/*! @{ */ + +#define INTM_MON_INTM_STATUS_STATUS_MASK (0x1U) +#define INTM_MON_INTM_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Monitor status + * 0b1..Exceeded + * 0b0..Did not exceed + */ +#define INTM_MON_INTM_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << INTM_MON_INTM_STATUS_STATUS_SHIFT)) & INTM_MON_INTM_STATUS_STATUS_MASK) +/*! @} */ + +/* The count of INTM_MON_INTM_STATUS */ +#define INTM_MON_INTM_STATUS_COUNT (4U) + + +/*! + * @} + */ /* end of group INTM_Register_Masks */ + + +/* INTM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x5005D000u) + /** Peripheral INTM0 base address */ + #define INTM0_BASE_NS (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Peripheral INTM0 base pointer */ + #define INTM0_NS ((INTM_Type *)INTM0_BASE_NS) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS_NS { INTM0_BASE_NS } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS_NS { INTM0_NS } +#else + /** Peripheral INTM0 base address */ + #define INTM0_BASE (0x4005D000u) + /** Peripheral INTM0 base pointer */ + #define INTM0 ((INTM_Type *)INTM0_BASE) + /** Array initializer of INTM peripheral base addresses */ + #define INTM_BASE_ADDRS { INTM0_BASE } + /** Array initializer of INTM peripheral base pointers */ + #define INTM_BASE_PTRS { INTM0 } +#endif + +/*! + * @} + */ /* end of group INTM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ITRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Peripheral_Access_Layer ITRC Peripheral Access Layer + * @{ + */ + +/** ITRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t STATUS; /**< ITRC outputs and IN0 to IN15 Status, offset: 0x0 */ + __IO uint32_t STATUS1; /**< ITRC IN16 to IN47 Status, offset: 0x4 */ + __IO uint32_t OUT_SEL[7][2]; /**< Trigger Source IN0 to IN15 selector, array offset: 0x8, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t OUT_SEL_1[7][2]; /**< Trigger Source IN16 to IN31 selector, array offset: 0x48, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_1[8]; + __IO uint32_t OUT_SEL_2[7][2]; /**< Trigger source IN32 to IN47 selector, array offset: 0x88, array step: index*0x8, index2*0x4 */ + uint8_t RESERVED_2[48]; + __O uint32_t SW_EVENT0; /**< Software event 0, offset: 0xF0 */ + __O uint32_t SW_EVENT1; /**< Software event 1, offset: 0xF4 */ +} ITRC_Type; + +/* ---------------------------------------------------------------------------- + -- ITRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ITRC_Register_Masks ITRC Register Masks + * @{ + */ + +/*! @name STATUS - ITRC outputs and IN0 to IN15 Status */ +/*! @{ */ + +#define ITRC_STATUS_IN0_STATUS_MASK (0x1U) +#define ITRC_STATUS_IN0_STATUS_SHIFT (0U) +/*! IN0_STATUS - GDET0 & 1 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN0_STATUS_SHIFT)) & ITRC_STATUS_IN0_STATUS_MASK) + +#define ITRC_STATUS_IN1_STATUS_MASK (0x2U) +#define ITRC_STATUS_IN1_STATUS_SHIFT (1U) +/*! IN1_STATUS - TDET tamper output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN1_STATUS_SHIFT)) & ITRC_STATUS_IN1_STATUS_MASK) + +#define ITRC_STATUS_IN2_STATUS_MASK (0x4U) +#define ITRC_STATUS_IN2_STATUS_SHIFT (2U) +/*! IN2_STATUS - Code Watchdog 0 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN2_STATUS_SHIFT)) & ITRC_STATUS_IN2_STATUS_MASK) + +#define ITRC_STATUS_IN3_STATUS_MASK (0x8U) +#define ITRC_STATUS_IN3_STATUS_SHIFT (3U) +/*! IN3_STATUS - VDD_MAIN volt tamper output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN3_STATUS_SHIFT)) & ITRC_STATUS_IN3_STATUS_MASK) + +#define ITRC_STATUS_IN4_STATUS_MASK (0x10U) +#define ITRC_STATUS_IN4_STATUS_SHIFT (4U) +/*! IN4_STATUS - SPC VDD_CORE_LVD detect. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN4_STATUS_SHIFT)) & ITRC_STATUS_IN4_STATUS_MASK) + +#define ITRC_STATUS_IN5_STATUS_MASK (0x20U) +#define ITRC_STATUS_IN5_STATUS_SHIFT (5U) +/*! IN5_STATUS - Watch Dog timer event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN5_STATUS_SHIFT)) & ITRC_STATUS_IN5_STATUS_MASK) + +#define ITRC_STATUS_IN6_STATUS_MASK (0x40U) +#define ITRC_STATUS_IN6_STATUS_SHIFT (6U) +/*! IN6_STATUS - Flash ECC mismatch event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN6_STATUS_SHIFT)) & ITRC_STATUS_IN6_STATUS_MASK) + +#define ITRC_STATUS_IN7_STATUS_MASK (0x80U) +#define ITRC_STATUS_IN7_STATUS_SHIFT (7U) +/*! IN7_STATUS - AHB secure bus checkers detected illegal access. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN7_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN7_STATUS_SHIFT)) & ITRC_STATUS_IN7_STATUS_MASK) + +#define ITRC_STATUS_IN8_STATUS_MASK (0x100U) +#define ITRC_STATUS_IN8_STATUS_SHIFT (8U) +/*! IN8_STATUS - ELS error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN8_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN8_STATUS_SHIFT)) & ITRC_STATUS_IN8_STATUS_MASK) + +#define ITRC_STATUS_IN9_STATUS_MASK (0x200U) +#define ITRC_STATUS_IN9_STATUS_SHIFT (9U) +/*! IN9_STATUS - SPC VDD_CORE glitch detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN9_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN9_STATUS_SHIFT)) & ITRC_STATUS_IN9_STATUS_MASK) + +#define ITRC_STATUS_IN10_STATUS_MASK (0x400U) +#define ITRC_STATUS_IN10_STATUS_SHIFT (10U) +/*! IN10_STATUS - PKC module detected an error event. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN10_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN10_STATUS_SHIFT)) & ITRC_STATUS_IN10_STATUS_MASK) + +#define ITRC_STATUS_IN11_STATUS_MASK (0x800U) +#define ITRC_STATUS_IN11_STATUS_SHIFT (11U) +/*! IN11_STATUS - Code Watchdog 1 interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN11_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN11_STATUS_SHIFT)) & ITRC_STATUS_IN11_STATUS_MASK) + +#define ITRC_STATUS_IN112_STATUS_MASK (0x1000U) +#define ITRC_STATUS_IN112_STATUS_SHIFT (12U) +/*! IN112_STATUS - Watchdog 1 timer event interrupt. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN112_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN112_STATUS_SHIFT)) & ITRC_STATUS_IN112_STATUS_MASK) + +#define ITRC_STATUS_IN113_STATUS_MASK (0x2000U) +#define ITRC_STATUS_IN113_STATUS_SHIFT (13U) +/*! IN113_STATUS - FREQME out of range status output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN113_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN113_STATUS_SHIFT)) & ITRC_STATUS_IN113_STATUS_MASK) + +#define ITRC_STATUS_IN14_STATUS_MASK (0x4000U) +#define ITRC_STATUS_IN14_STATUS_SHIFT (14U) +/*! IN14_STATUS - Software event 0 occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN14_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN14_STATUS_SHIFT)) & ITRC_STATUS_IN14_STATUS_MASK) + +#define ITRC_STATUS_IN15_STATUS_MASK (0x8000U) +#define ITRC_STATUS_IN15_STATUS_SHIFT (15U) +/*! IN15_STATUS - Software event 1 occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_IN15_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_IN15_STATUS_SHIFT)) & ITRC_STATUS_IN15_STATUS_MASK) + +#define ITRC_STATUS_OUT0_STATUS_MASK (0x10000U) +#define ITRC_STATUS_OUT0_STATUS_SHIFT (16U) +/*! OUT0_STATUS - ITRC triggered ITRC_IRQ output. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT0_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT0_STATUS_SHIFT)) & ITRC_STATUS_OUT0_STATUS_MASK) + +#define ITRC_STATUS_OUT1_STATUS_MASK (0x20000U) +#define ITRC_STATUS_OUT1_STATUS_SHIFT (17U) +/*! OUT1_STATUS - ITRC triggered ELS_RESET to clear ELS key store. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT1_STATUS_SHIFT)) & ITRC_STATUS_OUT1_STATUS_MASK) + +#define ITRC_STATUS_OUT2_STATUS_MASK (0x40000U) +#define ITRC_STATUS_OUT2_STATUS_SHIFT (18U) +/*! OUT2_STATUS - ITRC triggered PUF_ZEROIZE to clear PUF key store and RAM. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT2_STATUS_SHIFT)) & ITRC_STATUS_OUT2_STATUS_MASK) + +#define ITRC_STATUS_OUT3_STATUS_MASK (0x80000U) +#define ITRC_STATUS_OUT3_STATUS_SHIFT (19U) +/*! OUT3_STATUS - ITRC triggered RAM_ZEROIZE. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT3_STATUS_SHIFT)) & ITRC_STATUS_OUT3_STATUS_MASK) + +#define ITRC_STATUS_OUT4_STATUS_MASK (0x100000U) +#define ITRC_STATUS_OUT4_STATUS_SHIFT (20U) +/*! OUT4_STATUS - ITRC triggered CHIP_RESET to reset the chip after all other response process finished. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT4_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT4_STATUS_SHIFT)) & ITRC_STATUS_OUT4_STATUS_MASK) + +#define ITRC_STATUS_OUT5_STATUS_MASK (0x200000U) +#define ITRC_STATUS_OUT5_STATUS_SHIFT (21U) +/*! OUT5_STATUS - ITRC triggered TMPR_OUT0 internal signal connected to various on-chip multiplexers. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT5_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT5_STATUS_SHIFT)) & ITRC_STATUS_OUT5_STATUS_MASK) + +#define ITRC_STATUS_OUT6_STATUS_MASK (0x400000U) +#define ITRC_STATUS_OUT6_STATUS_SHIFT (22U) +/*! OUT6_STATUS - ITRC triggered TMPR_OUT1 internal signal connected to various on-chip multiplexers. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS_OUT6_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS_OUT6_STATUS_SHIFT)) & ITRC_STATUS_OUT6_STATUS_MASK) +/*! @} */ + +/*! @name STATUS1 - ITRC IN16 to IN47 Status */ +/*! @{ */ + +#define ITRC_STATUS1_IN16_STATUS_MASK (0x1U) +#define ITRC_STATUS1_IN16_STATUS_SHIFT (0U) +/*! IN16_STATUS - SSPC VDD_SYS_LVD detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN16_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN16_STATUS_SHIFT)) & ITRC_STATUS1_IN16_STATUS_MASK) + +#define ITRC_STATUS1_IN17_STATUS_MASK (0x2U) +#define ITRC_STATUS1_IN17_STATUS_SHIFT (1U) +/*! IN17_STATUS - SPC VDD_IO_LVD detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN17_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN17_STATUS_SHIFT)) & ITRC_STATUS1_IN17_STATUS_MASK) + +#define ITRC_STATUS1_IN18_STATUS_MASK (0x4U) +#define ITRC_STATUS1_IN18_STATUS_SHIFT (2U) +/*! IN18_STATUS - Reserved + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN18_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN18_STATUS_SHIFT)) & ITRC_STATUS1_IN18_STATUS_MASK) + +#define ITRC_STATUS1_IN19_STATUS_MASK (0x8U) +#define ITRC_STATUS1_IN19_STATUS_SHIFT (3U) +/*! IN19_STATUS - Reserved + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN19_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN19_STATUS_SHIFT)) & ITRC_STATUS1_IN19_STATUS_MASK) + +#define ITRC_STATUS1_IN20_STATUS_MASK (0x10U) +#define ITRC_STATUS1_IN20_STATUS_SHIFT (4U) +/*! IN20_STATUS - VDD_MAIN clock tamper output event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN20_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN20_STATUS_SHIFT)) & ITRC_STATUS1_IN20_STATUS_MASK) + +#define ITRC_STATUS1_IN24_21_STATUS_MASK (0x1E0U) +#define ITRC_STATUS1_IN24_21_STATUS_SHIFT (5U) +/*! IN24_21_STATUS - INTM interrupt monitor error 3~0 event occurred. + * 0b0000..Output not triggered. + * 0b0001..Output has been triggered. + */ +#define ITRC_STATUS1_IN24_21_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN24_21_STATUS_SHIFT)) & ITRC_STATUS1_IN24_21_STATUS_MASK) + +#define ITRC_STATUS1_IN32_25_STATUS_MASK (0x1FE00U) +#define ITRC_STATUS1_IN32_25_STATUS_SHIFT (9U) +/*! IN32_25_STATUS - MSF SOCTRIM 7~0 ECC error event occurred. + * 0b00000000..Output not triggered. + * 0b00000001..Output has been triggered. + */ +#define ITRC_STATUS1_IN32_25_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN32_25_STATUS_SHIFT)) & ITRC_STATUS1_IN32_25_STATUS_MASK) + +#define ITRC_STATUS1_IN33_STATUS_MASK (0x20000U) +#define ITRC_STATUS1_IN33_STATUS_SHIFT (17U) +/*! IN33_STATUS - GDET0/1 SFR error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN33_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN33_STATUS_SHIFT)) & ITRC_STATUS1_IN33_STATUS_MASK) + +#define ITRC_STATUS1_IN34_STATUS_MASK (0x40000U) +#define ITRC_STATUS1_IN34_STATUS_SHIFT (18U) +/*! IN34_STATUS - SPC VDD_CORE high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN34_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN34_STATUS_SHIFT)) & ITRC_STATUS1_IN34_STATUS_MASK) + +#define ITRC_STATUS1_IN35_STATUS_MASK (0x80000U) +#define ITRC_STATUS1_IN35_STATUS_SHIFT (19U) +/*! IN35_STATUS - SPC VDD_SYS_HVD high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN35_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN35_STATUS_SHIFT)) & ITRC_STATUS1_IN35_STATUS_MASK) + +#define ITRC_STATUS1_IN36_STATUS_MASK (0x100000U) +#define ITRC_STATUS1_IN36_STATUS_SHIFT (20U) +/*! IN36_STATUS - SPC VDD_IO high voltage detect event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN36_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN36_STATUS_SHIFT)) & ITRC_STATUS1_IN36_STATUS_MASK) + +#define ITRC_STATUS1_IN37_STATUS_MASK (0x200000U) +#define ITRC_STATUS1_IN37_STATUS_SHIFT (21U) +/*! IN37_STATUS - FLEXSPI GCM error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN37_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN37_STATUS_SHIFT)) & ITRC_STATUS1_IN37_STATUS_MASK) + +#define ITRC_STATUS1_IN46_STATUS_MASK (0x40000000U) +#define ITRC_STATUS1_IN46_STATUS_SHIFT (30U) +/*! IN46_STATUS - SM3 SGI error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN46_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN46_STATUS_SHIFT)) & ITRC_STATUS1_IN46_STATUS_MASK) + +#define ITRC_STATUS1_IN47_STATUS_MASK (0x80000000U) +#define ITRC_STATUS1_IN47_STATUS_SHIFT (31U) +/*! IN47_STATUS - TRNG HW error event occurred. + * 0b0..Output not triggered. + * 0b1..Output has been triggered. + */ +#define ITRC_STATUS1_IN47_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ITRC_STATUS1_IN47_STATUS_SHIFT)) & ITRC_STATUS1_IN47_STATUS_MASK) +/*! @} */ + +/*! @name OUTX_SEL_OUTX_SELY_OUT_SEL - Trigger Source IN0 to IN15 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT (0U) +/*! IN0_SELn - Selects digital glitch detector as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT (2U) +/*! IN1_SELn - Selects TDET event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN1_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT (4U) +/*! IN2_SELn - Selects Code Watchdog 0 event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN2_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT (6U) +/*! IN3_SELn - Selects VDD_MAIN voltage tamper event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN3_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT (8U) +/*! IN4_SELn - Selects low-voltage event on VDD_CORE rail as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN4_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT (10U) +/*! IN5_SELn - Selects Watchdog 0 timer event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN5_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK (0x3000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT (12U) +/*! IN6_SELn - Selects Flash ECC mismatch event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN6_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK (0xC000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT (14U) +/*! IN7_SELn - Selects AHB secure bus or MBC bus illegal access event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN7_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK (0x30000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT (16U) +/*! IN8_SELn - Selects ELS error event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN8_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK (0xC0000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT (18U) +/*! IN9_SELn - Selects SPC VDD_CORE glitch detector as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK (0x300000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT (20U) +/*! IN10_SELn - Selects PKC error event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN10_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK (0xC00000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT (22U) +/*! IN11_SELn - Selects Code Watchdog 1 event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK (0x3000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT (24U) +/*! IN12_SELn - Selects Watchdog 1 timer event as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK (0xC000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT (26U) +/*! IN13_SELn - Selects FREQME out of range status output as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT (28U) +/*! IN14_SELn - Selects software event 0 as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN14_SELn_MASK) + +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT (30U) +/*! IN15_SELn - Selects software event 1 as a trigger source. */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_SHIFT)) & ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN15_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL */ +#define ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_COUNT2 (2U) + +/*! @name OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 - Trigger Source IN16 to IN31 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT (0U) +/*! IN16_SELn - Selects SPC VDD_SYS_LVD detect as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT (2U) +/*! IN17_SELn - Selects SPC VDD_IO_LVD detect as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT (4U) +/*! IN18_SELn - Reserved. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN18_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT (6U) +/*! IN19_SELn - Selects VDD_MAIN temperature tamper output event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT (8U) +/*! IN20_SELn - Selects VDD_MAIN clock tamper output event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT (10U) +/*! IN21_SELn - Selects INTM interrupt monitor error 0 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK (0x3000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT (12U) +/*! IN22_SELn - Selects INTM interrupt monitor error 1 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK (0xC000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT (14U) +/*! IN23_SELn - Selects INTM interrupt monitor error 2 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK (0x30000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT (16U) +/*! IN24_SELn - Selects INTM interrupt monitor error 3 event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK (0xC0000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT (18U) +/*! IN25_SELn - Selects MSF SOCTRIM 0 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK (0x300000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT (20U) +/*! IN26_SELn - Selects MSF SOCTRIM 1 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN26_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK (0xC00000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT (22U) +/*! IN27_SELn - Selects MSF SOCTRIM 2 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN27_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK (0x3000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT (24U) +/*! IN28_SELn - Selects MSF SOCTRIM 3 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN28_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK (0xC000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT (26U) +/*! IN29_SELn - Selects MSF SOCTRIM 4 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN29_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT (28U) +/*! IN30_SELn - Selects MSF SOCTRIM 5 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN30_SELn_MASK) + +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT (30U) +/*! IN31_SELn - Selects MSF SOCTRIM 6 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_SHIFT)) & ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN31_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1 */ +#define ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT2 (2U) + +/*! @name OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 - Trigger source IN32 to IN47 selector */ +/*! @{ */ + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK (0x3U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT (0U) +/*! IN32_SELn - Selects MSF SOCTRIM 7 ECC error event as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK (0xCU) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT (2U) +/*! IN33_SELn - Selects GDET0 & 1 SFR error detect as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK (0x30U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT (4U) +/*! IN34_SELn - Selects SPC VDD_CORE_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK (0xC0U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT (6U) +/*! IN35_SELn - Selects VDD_SYS_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK (0x300U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT (8U) +/*! IN36_SELn - Selects VDD_IO_HVD as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK (0xC00U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT (10U) +/*! IN37_SELn - Selects FLEXSPI GCM error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK (0x30000000U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT (28U) +/*! IN46_SELn - Selects SM3 SGI error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK) + +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK (0xC0000000U) +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT (30U) +/*! IN47_SELn - Selects TRNG HW Error as a trigger source. */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn(x) (((uint32_t)(((uint32_t)(x)) << ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_SHIFT)) & ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK) +/*! @} */ + +/* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT (7U) + +/* The count of ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2 */ +#define ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT2 (2U) + +/*! @name SW_EVENT0 - Software event 0 */ +/*! @{ */ + +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT (0U) +/*! TRIGGER_SW_EVENT_0 - Trigger software event 0. */ +#define ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_SHIFT)) & ITRC_SW_EVENT0_TRIGGER_SW_EVENT_0_MASK) +/*! @} */ + +/*! @name SW_EVENT1 - Software event 1 */ +/*! @{ */ + +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK (0xFFFFFFFFU) +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT (0U) +/*! TRIGGER_SW_EVENT_1 - Trigger software event 1. */ +#define ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1(x) (((uint32_t)(((uint32_t)(x)) << ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_SHIFT)) & ITRC_SW_EVENT1_TRIGGER_SW_EVENT_1_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ITRC_Register_Masks */ + + +/* ITRC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x50026000u) + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE_NS (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Peripheral ITRC0 base pointer */ + #define ITRC0_NS ((ITRC_Type *)ITRC0_BASE_NS) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS_NS { ITRC0_BASE_NS } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS_NS { ITRC0_NS } +#else + /** Peripheral ITRC0 base address */ + #define ITRC0_BASE (0x40026000u) + /** Peripheral ITRC0 base pointer */ + #define ITRC0 ((ITRC_Type *)ITRC0_BASE) + /** Array initializer of ITRC peripheral base addresses */ + #define ITRC_BASE_ADDRS { ITRC0_BASE } + /** Array initializer of ITRC peripheral base pointers */ + #define ITRC_BASE_PTRS { ITRC0 } +#endif + +/*! + * @} + */ /* end of group ITRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPCMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer + * @{ + */ + +/** LPCMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ + __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ + __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< DAC Control, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */ + __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ + __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ + __IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */ + __IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ +} LPCMP_Type; + +/* ---------------------------------------------------------------------------- + -- LPCMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Register_Masks LPCMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) +#define LPCMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000001..Round robin feature + */ +#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) + +#define LPCMP_VERID_MINOR_MASK (0xFF0000U) +#define LPCMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) + +#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) +#define LPCMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPCMP_PARAM_DAC_RES_MASK (0xFU) +#define LPCMP_PARAM_DAC_RES_SHIFT (0U) +/*! DAC_RES - DAC Resolution + * 0b0000..4-bit DAC + * 0b0001..6-bit DAC + * 0b0010..8-bit DAC + * 0b0011..10-bit DAC + * 0b0100..12-bit DAC + * 0b0101..14-bit DAC + * 0b0110..16-bit DAC + */ +#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) +/*! @} */ + +/*! @name CCR0 - Comparator Control Register 0 */ +/*! @{ */ + +#define LPCMP_CCR0_CMP_EN_MASK (0x1U) +#define LPCMP_CCR0_CMP_EN_SHIFT (0U) +/*! CMP_EN - Comparator Enable + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable + */ +#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) +/*! @} */ + +/*! @name CCR1 - Comparator Control Register 1 */ +/*! @{ */ + +#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) +#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) +/*! WINDOW_EN - Windowing Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) + +#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) +#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) +/*! SAMPLE_EN - Sampling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) + +#define LPCMP_CCR1_DMA_EN_MASK (0x4U) +#define LPCMP_CCR1_DMA_EN_SHIFT (2U) +/*! DMA_EN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) + +#define LPCMP_CCR1_COUT_INV_MASK (0x8U) +#define LPCMP_CCR1_COUT_INV_SHIFT (3U) +/*! COUT_INV - Comparator Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) + +#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) +#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) +/*! COUT_SEL - Comparator Output Select + * 0b0..Use COUT (filtered) + * 0b1..Use COUTA (unfiltered) + */ +#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) + +#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) +#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) +/*! COUT_PEN - Comparator Output Pin Enable + * 0b0..Not available + * 0b1..Available + */ +#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) + +#define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) +#define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) +/*! COUTA_OWEN - COUTA_OW Enable + * 0b0..COUTA holds the last sampled value. + * 0b1..Enables the COUTA signal value to be defined by COUTA_OW. + */ +#define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) + +#define LPCMP_CCR1_COUTA_OW_MASK (0x80U) +#define LPCMP_CCR1_COUTA_OW_SHIFT (7U) +/*! COUTA_OW - COUTA Output Level for Closed Window + * 0b0..COUTA is 0 + * 0b1..COUTA is 1 + */ +#define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) + +#define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) +#define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) +/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) + +#define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) +#define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) +/*! WINDOW_CLS - COUT Event Window Close + * 0b0..COUT event cannot close the window + * 0b1..COUT event can close the window + */ +#define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) + +#define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) +#define LPCMP_CCR1_EVT_SEL_SHIFT (10U) +/*! EVT_SEL - COUT Event Select + * 0b00..Rising edge + * 0b01..Falling edge + * 0b1x..Both edges + */ +#define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) + +#define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U) +#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U) +/*! FUNC_CLK_SEL - Functional Clock Source Select + * 0b00..Select functional clock source 0 + * 0b01..Select functional clock source 1 + * 0b10..Select functional clock source 2 + * 0b11..Select functional clock source 3 + */ +#define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK) + +#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) +#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) +/*! FILT_CNT - Filter Sample Count + * 0b000..Filter is bypassed: COUT = COUTA + * 0b001..1 consecutive sample (Comparator output is simply sampled.) + * 0b010..2 consecutive samples + * 0b011..3 consecutive samples + * 0b100..4 consecutive samples + * 0b101..5 consecutive samples + * 0b110..6 consecutive samples + * 0b111..7 consecutive samples + */ +#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) + +#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) +#define LPCMP_CCR1_FILT_PER_SHIFT (24U) +/*! FILT_PER - Filter Sample Period */ +#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) +/*! @} */ + +/*! @name CCR2 - Comparator Control Register 2 */ +/*! @{ */ + +#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) +#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) +/*! CMP_HPMD - CMP High Power Mode Select + * 0b0..Low power (speed) comparison mode + * 0b1..High power (speed) comparison mode + */ +#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) + +#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) +#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) +/*! CMP_NPMD - CMP Nano Power Mode Select + * 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator. + * 0b1..Enables CMP Nano power mode. + */ +#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) + +#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) +#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) +/*! HYSTCTR - Comparator Hysteresis Control + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. + */ +#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) + +#define LPCMP_CCR2_PSEL_MASK (0x70000U) +#define LPCMP_CCR2_PSEL_SHIFT (16U) +/*! PSEL - Plus Input MUX Select + * 0b000..Input 0p + * 0b001..Input 1p + * 0b010..Input 2p + * 0b011..Input 3p + * 0b100..Input 4p + * 0b101..Input 5p + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) + +#define LPCMP_CCR2_MSEL_MASK (0x700000U) +#define LPCMP_CCR2_MSEL_SHIFT (20U) +/*! MSEL - Minus Input MUX Select + * 0b000..Input 0m + * 0b001..Input 1m + * 0b010..Input 2m + * 0b011..Input 3m + * 0b100..Input 4m + * 0b101..Input 5m + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) +/*! @} */ + +/*! @name DCR - DAC Control */ +/*! @{ */ + +#define LPCMP_DCR_DAC_EN_MASK (0x1U) +#define LPCMP_DCR_DAC_EN_SHIFT (0U) +/*! DAC_EN - DAC Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) + +#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) +#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) + +#define LPCMP_DCR_VRSEL_MASK (0x100U) +#define LPCMP_DCR_VRSEL_SHIFT (8U) +/*! VRSEL - DAC Reference High Voltage Source Select + * 0b0..VREFH0 + * 0b1..VREFH1 + */ +#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) + +#define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) +#define LPCMP_DCR_DAC_DATA_SHIFT (16U) +/*! DAC_DATA - DAC Output Voltage Select */ +#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPCMP_IER_CFR_IE_MASK (0x1U) +#define LPCMP_IER_CFR_IE_SHIFT (0U) +/*! CFR_IE - Comparator Flag Rising Interrupt Enable + * 0b0..Disables the comparator flag rising interrupt. + * 0b1..Enables the comparator flag rising interrupt when CFR is set. + */ +#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) + +#define LPCMP_IER_CFF_IE_MASK (0x2U) +#define LPCMP_IER_CFF_IE_SHIFT (1U) +/*! CFF_IE - Comparator Flag Falling Interrupt Enable + * 0b0..Disables the comparator flag falling interrupt. + * 0b1..Enables the comparator flag falling interrupt when CFF is set. + */ +#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) + +#define LPCMP_IER_RRF_IE_MASK (0x4U) +#define LPCMP_IER_RRF_IE_SHIFT (2U) +/*! RRF_IE - Round-Robin Flag Interrupt Enable + * 0b0..Disables the round-robin flag interrupt. + * 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel. + */ +#define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) +/*! @} */ + +/*! @name CSR - Comparator Status */ +/*! @{ */ + +#define LPCMP_CSR_CFR_MASK (0x1U) +#define LPCMP_CSR_CFR_SHIFT (0U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) + +#define LPCMP_CSR_CFF_MASK (0x2U) +#define LPCMP_CSR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) + +#define LPCMP_CSR_RRF_MASK (0x4U) +#define LPCMP_CSR_RRF_SHIFT (2U) +/*! RRF - Round-Robin Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) + +#define LPCMP_CSR_COUT_MASK (0x100U) +#define LPCMP_CSR_COUT_SHIFT (8U) +/*! COUT - Analog Comparator Output */ +#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) +/*! @} */ + +/*! @name RRCR0 - Round Robin Control Register 0 */ +/*! @{ */ + +#define LPCMP_RRCR0_RR_EN_MASK (0x1U) +#define LPCMP_RRCR0_RR_EN_SHIFT (0U) +/*! RR_EN - Round-Robin Enable + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) + +#define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U) +#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U) +/*! RR_TRG_SEL - Round-Robin Trigger Select + * 0b0..External trigger + * 0b1..Internal trigger + */ +#define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) +#define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) +/*! RR_NSAM - Number of Sample Clocks + * 0b00..0 clock + * 0b01..1 clock + * 0b10..2 clocks + * 0b11..3 clocks + */ +#define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) + +#define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U) +#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U) +/*! RR_CLK_SEL - Round Robin Clock Source Select + * 0b00..Select Round Robin clock Source 0 + * 0b01..Select Round Robin clock Source 1 + * 0b10..Select Round Robin clock Source 2 + * 0b11..Select Round Robin clock Source 3 + */ +#define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK) + +#define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) +#define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) +/*! RR_INITMOD - Initialization Delay Modulus + * 0b000000..63 cycles (same as 111111b) + * 0b000001-0b111111..1 to 63 cycles + */ +#define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U) +#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U) +/*! RR_SAMPLE_CNT - Number of Sample for One Channel + * 0b0000..1 samples + * 0b0001..2 samples + * 0b0010..3 samples + * 0b0011..4 samples + * 0b0100..5 samples + * 0b0101..6 samples + * 0b0110..7 samples + * 0b0111..8 samples + * 0b1000..9 samples + * 0b1001..10 samples + * 0b1010..11 samples + * 0b1011..12 samples + * 0b1100..13 samples + * 0b1101..14 samples + * 0b1110..15 samples + * 0b1111..16 samples + */ +#define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U) +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U) +/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold + * 0b0000..At least 1 sampled "1", the final result is "1" + * 0b0001..At least 2 sampled "1", the final result is "1" + * 0b0010..At least 3 sampled "1", the final result is "1" + * 0b0011..At least 4 sampled "1", the final result is "1" + * 0b0100..At least 5 sampled "1", the final result is "1" + * 0b0101..At least 6 sampled "1", the final result is "1" + * 0b0110..At least 7 sampled "1", the final result is "1" + * 0b0111..At least 8 sampled "1", the final result is "1" + * 0b1000..At least 9 sampled "1", the final result is "1" + * 0b1001..At least 10 sampled "1", the final result is "1" + * 0b1010..At least 11 sampled "1", the final result is "1" + * 0b1011..At least 12 sampled "1", the final result is "1" + * 0b1100..At least 13 sampled "1", the final result is "1" + * 0b1101..At least 14 sampled "1", the final result is "1" + * 0b1110..At least 15 sampled "1", the final result is "1" + * 0b1111..At least 16 sampled "1", the final result is "1" + */ +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK) +/*! @} */ + +/*! @name RRCR1 - Round Robin Control Register 1 */ +/*! @{ */ + +#define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) +#define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) +/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) + +#define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) +#define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) +/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) + +#define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) +#define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) +/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) + +#define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) +#define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) +/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) + +#define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) +#define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) +/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) + +#define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) +#define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) +/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) + +#define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) +#define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) +/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) + +#define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) +#define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) +/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) + +#define LPCMP_RRCR1_FIXP_MASK (0x10000U) +#define LPCMP_RRCR1_FIXP_SHIFT (16U) +/*! FIXP - Fixed Port + * 0b0..Fix the plus port. Sweep only the inputs to the minus port. + * 0b1..Fix the minus port. Sweep only the inputs to the plus port. + */ +#define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) + +#define LPCMP_RRCR1_FIXCH_MASK (0x700000U) +#define LPCMP_RRCR1_FIXCH_SHIFT (20U) +/*! FIXCH - Fixed Channel Select + * 0b000..Channel 0 + * 0b001..Channel 1 + * 0b010..Channel 2 + * 0b011..Channel 3 + * 0b100..Channel 4 + * 0b101..Channel 5 + * 0b110..Channel 6 + * 0b111..Channel 7 + */ +#define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) +/*! @} */ + +/*! @name RRCSR - Round Robin Control and Status */ +/*! @{ */ + +#define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) +#define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) +/*! RR_CH0OUT - Comparison Result for Channel 0 */ +#define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) + +#define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) +#define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) +/*! RR_CH1OUT - Comparison Result for Channel 1 */ +#define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) + +#define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) +#define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) +/*! RR_CH2OUT - Comparison Result for Channel 2 */ +#define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) + +#define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) +#define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) +/*! RR_CH3OUT - Comparison Result for Channel 3 */ +#define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) + +#define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) +#define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) +/*! RR_CH4OUT - Comparison Result for Channel 4 */ +#define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) + +#define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) +#define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) +/*! RR_CH5OUT - Comparison Result for Channel 5 */ +#define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) + +#define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) +#define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) +/*! RR_CH6OUT - Comparison Result for Channel 6 */ +#define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) + +#define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) +#define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) +/*! RR_CH7OUT - Comparison Result for Channel 7 */ +#define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) +/*! @} */ + +/*! @name RRSR - Round Robin Status */ +/*! @{ */ + +#define LPCMP_RRSR_RR_CH0F_MASK (0x1U) +#define LPCMP_RRSR_RR_CH0F_SHIFT (0U) +/*! RR_CH0F - Channel 0 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) + +#define LPCMP_RRSR_RR_CH1F_MASK (0x2U) +#define LPCMP_RRSR_RR_CH1F_SHIFT (1U) +/*! RR_CH1F - Channel 1 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) + +#define LPCMP_RRSR_RR_CH2F_MASK (0x4U) +#define LPCMP_RRSR_RR_CH2F_SHIFT (2U) +/*! RR_CH2F - Channel 2 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) + +#define LPCMP_RRSR_RR_CH3F_MASK (0x8U) +#define LPCMP_RRSR_RR_CH3F_SHIFT (3U) +/*! RR_CH3F - Channel 3 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) + +#define LPCMP_RRSR_RR_CH4F_MASK (0x10U) +#define LPCMP_RRSR_RR_CH4F_SHIFT (4U) +/*! RR_CH4F - Channel 4 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) + +#define LPCMP_RRSR_RR_CH5F_MASK (0x20U) +#define LPCMP_RRSR_RR_CH5F_SHIFT (5U) +/*! RR_CH5F - Channel 5 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) + +#define LPCMP_RRSR_RR_CH6F_MASK (0x40U) +#define LPCMP_RRSR_RR_CH6F_SHIFT (6U) +/*! RR_CH6F - Channel 6 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) + +#define LPCMP_RRSR_RR_CH7F_MASK (0x80U) +#define LPCMP_RRSR_RR_CH7F_SHIFT (7U) +/*! RR_CH7F - Channel 7 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) +/*! @} */ + +/*! @name RRCR2 - Round Robin Control Register 2 */ +/*! @{ */ + +#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) +#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) +/*! RR_TIMER_RELOAD - Number of Sample Clocks */ +#define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK) + +#define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) +#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) +/*! RR_TIMER_EN - Round-Robin Internal Timer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPCMP_Register_Masks */ + + +/* LPCMP - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x50051000u) + /** Peripheral CMP0 base address */ + #define CMP0_BASE_NS (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP0 base pointer */ + #define CMP0_NS ((LPCMP_Type *)CMP0_BASE_NS) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x50052000u) + /** Peripheral CMP1 base address */ + #define CMP1_BASE_NS (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Peripheral CMP1 base pointer */ + #define CMP1_NS ((LPCMP_Type *)CMP1_BASE_NS) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS_NS { CMP0_BASE_NS, CMP1_BASE_NS } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS_NS { CMP0_NS, CMP1_NS } +#else + /** Peripheral CMP0 base address */ + #define CMP0_BASE (0x40051000u) + /** Peripheral CMP0 base pointer */ + #define CMP0 ((LPCMP_Type *)CMP0_BASE) + /** Peripheral CMP1 base address */ + #define CMP1_BASE (0x40052000u) + /** Peripheral CMP1 base pointer */ + #define CMP1 ((LPCMP_Type *)CMP1_BASE) + /** Array initializer of LPCMP peripheral base addresses */ + #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } + /** Array initializer of LPCMP peripheral base pointers */ + #define LPCMP_BASE_PTRS { CMP0, CMP1 } +#endif +/** Interrupt vectors for the LPCMP peripheral type */ +#define LPCMP_IRQS { HSCMP0_IRQn, HSCMP1_IRQn } + +/*! + * @} + */ /* end of group LPCMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ + uint8_t RESERVED_13[132]; + __O uint32_t MTCBR[128]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t MTDBR[253]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b1..Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b1..Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No unexpected NACK detected + * 0b1..Unexpected NACK detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b1..Controller lost arbitration + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout did not occur + * 0b1..Pin low timeout occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b1..Matching data received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b1..Start condition detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_HRDIR_MASK (0x8U) +#define LPI2C_MCFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..HREQ pin is input (for LPI2C controller) + * 0b1..HREQ pin is output (for LPI2C target) + */ +#define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x7U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x70000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0xFU) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b1..Repeated Start detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b1..Stop detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b1..Bit error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + +/*! @name MTCBR - Controller Transmit Command Burst */ +/*! @{ */ + +#define LPI2C_MTCBR_DATA_MASK (0xFFU) +#define LPI2C_MTCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) + +#define LPI2C_MTCBR_CMD_MASK (0x700U) +#define LPI2C_MTCBR_CMD_SHIFT (8U) +/*! CMD - Command */ +#define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) +/*! @} */ + +/* The count of LPI2C_MTCBR */ +#define LPI2C_MTCBR_COUNT (128U) + +/*! @name MTDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPI2C_MTDBR_DATA0_MASK (0xFFU) +#define LPI2C_MTDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data */ +#define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) + +#define LPI2C_MTDBR_DATA1_MASK (0xFF00U) +#define LPI2C_MTDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data */ +#define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) + +#define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) +#define LPI2C_MTDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data */ +#define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) + +#define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) +#define LPI2C_MTDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data */ +#define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPI2C_MTDBR */ +#define LPI2C_MTDBR_COUNT (253U) + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x50092800u) + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE_NS (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0_NS ((LPI2C_Type *)LPI2C0_BASE_NS) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x50093800u) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE_NS (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1_NS ((LPI2C_Type *)LPI2C1_BASE_NS) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x50094800u) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE_NS (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2_NS ((LPI2C_Type *)LPI2C2_BASE_NS) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x50095800u) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE_NS (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3_NS ((LPI2C_Type *)LPI2C3_BASE_NS) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x500B4800u) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE_NS (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4_NS ((LPI2C_Type *)LPI2C4_BASE_NS) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x500B5800u) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE_NS (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5_NS ((LPI2C_Type *)LPI2C5_BASE_NS) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x500B6800u) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE_NS (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6_NS ((LPI2C_Type *)LPI2C6_BASE_NS) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x500B7800u) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE_NS (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7_NS ((LPI2C_Type *)LPI2C7_BASE_NS) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS_NS { LPI2C0_BASE_NS, LPI2C1_BASE_NS, LPI2C2_BASE_NS, LPI2C3_BASE_NS, LPI2C4_BASE_NS, LPI2C5_BASE_NS, LPI2C6_BASE_NS, LPI2C7_BASE_NS } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS_NS { LPI2C0_NS, LPI2C1_NS, LPI2C2_NS, LPI2C3_NS, LPI2C4_NS, LPI2C5_NS, LPI2C6_NS, LPI2C7_NS } +#else + /** Peripheral LPI2C0 base address */ + #define LPI2C0_BASE (0x40092800u) + /** Peripheral LPI2C0 base pointer */ + #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) + /** Peripheral LPI2C1 base address */ + #define LPI2C1_BASE (0x40093800u) + /** Peripheral LPI2C1 base pointer */ + #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) + /** Peripheral LPI2C2 base address */ + #define LPI2C2_BASE (0x40094800u) + /** Peripheral LPI2C2 base pointer */ + #define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) + /** Peripheral LPI2C3 base address */ + #define LPI2C3_BASE (0x40095800u) + /** Peripheral LPI2C3 base pointer */ + #define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) + /** Peripheral LPI2C4 base address */ + #define LPI2C4_BASE (0x400B4800u) + /** Peripheral LPI2C4 base pointer */ + #define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) + /** Peripheral LPI2C5 base address */ + #define LPI2C5_BASE (0x400B5800u) + /** Peripheral LPI2C5 base pointer */ + #define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE) + /** Peripheral LPI2C6 base address */ + #define LPI2C6_BASE (0x400B6800u) + /** Peripheral LPI2C6 base pointer */ + #define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE) + /** Peripheral LPI2C7 base address */ + #define LPI2C7_BASE (0x400B7800u) + /** Peripheral LPI2C7 base pointer */ + #define LPI2C7 ((LPI2C_Type *)LPI2C7_BASE) + /** Array initializer of LPI2C peripheral base addresses */ + #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE, LPI2C7_BASE } + /** Array initializer of LPI2C peripheral base pointers */ + #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7 } +#endif +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + * *.. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No underrun + * 0b1..Underrun + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No match + * 0b1..Match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) + +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) + +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..HREQ pin + * 0b1..Input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) + +#define LPSPI_CFGR0_HRDIR_MASK (0x8U) +#define LPSPI_CFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..Input + * 0b1..Output + */ +#define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) + +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x7U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x70000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0xFU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0xF0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1-bit transfer + * 0b01..2-bit transfer + * 0b10..4-bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + * 0b11..Transfer using PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_TDBR */ +#define LPSPI_TDBR_COUNT (128U) + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_RDBR */ +#define LPSPI_RDBR_COUNT (128U) + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x50092000u) + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE_NS (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0_NS ((LPSPI_Type *)LPSPI0_BASE_NS) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x50093000u) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE_NS (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1_NS ((LPSPI_Type *)LPSPI1_BASE_NS) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x50094000u) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE_NS (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2_NS ((LPSPI_Type *)LPSPI2_BASE_NS) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x50095000u) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE_NS (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3_NS ((LPSPI_Type *)LPSPI3_BASE_NS) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x500B4000u) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE_NS (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4_NS ((LPSPI_Type *)LPSPI4_BASE_NS) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x500B5000u) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE_NS (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5_NS ((LPSPI_Type *)LPSPI5_BASE_NS) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x500B6000u) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE_NS (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6_NS ((LPSPI_Type *)LPSPI6_BASE_NS) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x500B7000u) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE_NS (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7_NS ((LPSPI_Type *)LPSPI7_BASE_NS) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS_NS { LPSPI0_BASE_NS, LPSPI1_BASE_NS, LPSPI2_BASE_NS, LPSPI3_BASE_NS, LPSPI4_BASE_NS, LPSPI5_BASE_NS, LPSPI6_BASE_NS, LPSPI7_BASE_NS } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS_NS { LPSPI0_NS, LPSPI1_NS, LPSPI2_NS, LPSPI3_NS, LPSPI4_NS, LPSPI5_NS, LPSPI6_NS, LPSPI7_NS } +#else + /** Peripheral LPSPI0 base address */ + #define LPSPI0_BASE (0x40092000u) + /** Peripheral LPSPI0 base pointer */ + #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) + /** Peripheral LPSPI1 base address */ + #define LPSPI1_BASE (0x40093000u) + /** Peripheral LPSPI1 base pointer */ + #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) + /** Peripheral LPSPI2 base address */ + #define LPSPI2_BASE (0x40094000u) + /** Peripheral LPSPI2 base pointer */ + #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) + /** Peripheral LPSPI3 base address */ + #define LPSPI3_BASE (0x40095000u) + /** Peripheral LPSPI3 base pointer */ + #define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) + /** Peripheral LPSPI4 base address */ + #define LPSPI4_BASE (0x400B4000u) + /** Peripheral LPSPI4 base pointer */ + #define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) + /** Peripheral LPSPI5 base address */ + #define LPSPI5_BASE (0x400B5000u) + /** Peripheral LPSPI5 base pointer */ + #define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE) + /** Peripheral LPSPI6 base address */ + #define LPSPI6_BASE (0x400B6000u) + /** Peripheral LPSPI6 base pointer */ + #define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE) + /** Peripheral LPSPI7 base address */ + #define LPSPI7_BASE (0x400B7000u) + /** Peripheral LPSPI7 base pointer */ + #define LPSPI7 ((LPSPI_Type *)LPSPI7_BASE) + /** Array initializer of LPSPI peripheral base addresses */ + #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE, LPSPI7_BASE } + /** Array initializer of LPSPI peripheral base pointers */ + #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7 } +#endif +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b1..CNR = (CMR + 1) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x5004A000u) + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE_NS (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0_NS ((LPTMR_Type *)LPTMR0_BASE_NS) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x5004B000u) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE_NS (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1_NS ((LPTMR_Type *)LPTMR1_BASE_NS) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS_NS { LPTMR0_BASE_NS, LPTMR1_BASE_NS } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS_NS { LPTMR0_NS, LPTMR1_NS } +#else + /** Peripheral LPTMR0 base address */ + #define LPTMR0_BASE (0x4004A000u) + /** Peripheral LPTMR0 base pointer */ + #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) + /** Peripheral LPTMR1 base address */ + #define LPTMR1_BASE (0x4004B000u) + /** Peripheral LPTMR1 base pointer */ + #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) + /** Array initializer of LPTMR peripheral base addresses */ + #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } + /** Array initializer of LPTMR peripheral base pointers */ + #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } +#endif +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t MCR; /**< MODEM Control, offset: 0x40 */ + __IO uint32_t MSR; /**< MODEM Status, offset: 0x44 */ + __IO uint32_t REIR; /**< Receiver Extended Idle, offset: 0x48 */ + __IO uint32_t TEIR; /**< Transmitter Extended Idle, offset: 0x4C */ + __IO uint32_t HDCR; /**< Half Duplex Control, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t TOCR; /**< Timeout Control, offset: 0x58 */ + __IO uint32_t TOSR; /**< Timeout Status, offset: 0x5C */ + __IO uint32_t TIMEOUT[4]; /**< Timeout N, array offset: 0x60, array step: 0x4 */ + uint8_t RESERVED_2[400]; + __O uint32_t TCBR[128]; /**< Transmit Command Burst, array offset: 0x200, array step: 0x4 */ + __O uint32_t TDBR[256]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + * 0b0000000000000111..Enhanced feature set with full MODEM, IrDA, and enhanced idle detection + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MSF_MASK (0x100U) +#define LPUART_STAT_MSF_SHIFT (8U) +/*! MSF - MODEM Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_MSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSF_SHIFT)) & LPUART_STAT_MSF_MASK) + +#define LPUART_STAT_TSF_MASK (0x200U) +#define LPUART_STAT_TSF_SHIFT (9U) +/*! TSF - Timeout Status Flag + * 0b0..Field is 0 + * 0b1..Field is 1 + */ +#define LPUART_STAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TSF_SHIFT)) & LPUART_STAT_TSF_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Not equal to MA2 + * 0b1..Equal to MA2 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Not equal to MA1 + * 0b1..Equal to MA1 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error detected + * 0b1..Parity error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b1..Framing error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected + * 0b1..Noise detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun + * 0b1..Receive overrun (new LPUART data is lost) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b1..Idle line not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..Not occurred + * 0b1..Occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0x700U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No underflow + * 0b1..Underflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0x7U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0xF00U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0x70000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0xF000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + +/*! @name MCR - MODEM Control */ +/*! @{ */ + +#define LPUART_MCR_CTS_MASK (0x1U) +#define LPUART_MCR_CTS_SHIFT (0U) +/*! CTS - Clear To Send + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_CTS_SHIFT)) & LPUART_MCR_CTS_MASK) + +#define LPUART_MCR_DSR_MASK (0x2U) +#define LPUART_MCR_DSR_SHIFT (1U) +/*! DSR - Data Set Ready + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DSR_SHIFT)) & LPUART_MCR_DSR_MASK) + +#define LPUART_MCR_RIN_MASK (0x4U) +#define LPUART_MCR_RIN_SHIFT (2U) +/*! RIN - Ring Indicator + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RIN_SHIFT)) & LPUART_MCR_RIN_MASK) + +#define LPUART_MCR_DCD_MASK (0x8U) +#define LPUART_MCR_DCD_SHIFT (3U) +/*! DCD - Data Carrier Detect + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define LPUART_MCR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DCD_SHIFT)) & LPUART_MCR_DCD_MASK) + +#define LPUART_MCR_DTR_MASK (0x100U) +#define LPUART_MCR_DTR_SHIFT (8U) +/*! DTR - Data Terminal Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_DTR_SHIFT)) & LPUART_MCR_DTR_MASK) + +#define LPUART_MCR_RTS_MASK (0x200U) +#define LPUART_MCR_RTS_SHIFT (9U) +/*! RTS - Request To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MCR_RTS_SHIFT)) & LPUART_MCR_RTS_MASK) +/*! @} */ + +/*! @name MSR - MODEM Status */ +/*! @{ */ + +#define LPUART_MSR_DCTS_MASK (0x1U) +#define LPUART_MSR_DCTS_SHIFT (0U) +/*! DCTS - Delta Clear To Send + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCTS_SHIFT)) & LPUART_MSR_DCTS_MASK) + +#define LPUART_MSR_DDSR_MASK (0x2U) +#define LPUART_MSR_DDSR_SHIFT (1U) +/*! DDSR - Delta Data Set Ready + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDSR_SHIFT)) & LPUART_MSR_DDSR_MASK) + +#define LPUART_MSR_DRI_MASK (0x4U) +#define LPUART_MSR_DRI_SHIFT (2U) +/*! DRI - Delta Ring Indicator + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DRI(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DRI_SHIFT)) & LPUART_MSR_DRI_MASK) + +#define LPUART_MSR_DDCD_MASK (0x8U) +#define LPUART_MSR_DDCD_SHIFT (3U) +/*! DDCD - Delta Data Carrier Detect + * 0b0..Did not change state + * 0b1..Changed state + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DDCD_SHIFT)) & LPUART_MSR_DDCD_MASK) + +#define LPUART_MSR_CTS_MASK (0x10U) +#define LPUART_MSR_CTS_SHIFT (4U) +/*! CTS - Clear To Send + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_CTS_SHIFT)) & LPUART_MSR_CTS_MASK) + +#define LPUART_MSR_DSR_MASK (0x20U) +#define LPUART_MSR_DSR_SHIFT (5U) +/*! DSR - Data Set Ready + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DSR_SHIFT)) & LPUART_MSR_DSR_MASK) + +#define LPUART_MSR_RIN_MASK (0x40U) +#define LPUART_MSR_RIN_SHIFT (6U) +/*! RIN - Ring Indicator + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_RIN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_RIN_SHIFT)) & LPUART_MSR_RIN_MASK) + +#define LPUART_MSR_DCD_MASK (0x80U) +#define LPUART_MSR_DCD_SHIFT (7U) +/*! DCD - Data Carrier Detect + * 0b0..Logic one + * 0b1..Logic zero + */ +#define LPUART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MSR_DCD_SHIFT)) & LPUART_MSR_DCD_MASK) +/*! @} */ + +/*! @name REIR - Receiver Extended Idle */ +/*! @{ */ + +#define LPUART_REIR_IDTIME_MASK (0x3FFFU) +#define LPUART_REIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_REIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_REIR_IDTIME_SHIFT)) & LPUART_REIR_IDTIME_MASK) +/*! @} */ + +/*! @name TEIR - Transmitter Extended Idle */ +/*! @{ */ + +#define LPUART_TEIR_IDTIME_MASK (0x3FFFU) +#define LPUART_TEIR_IDTIME_SHIFT (0U) +/*! IDTIME - Idle Time */ +#define LPUART_TEIR_IDTIME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TEIR_IDTIME_SHIFT)) & LPUART_TEIR_IDTIME_MASK) +/*! @} */ + +/*! @name HDCR - Half Duplex Control */ +/*! @{ */ + +#define LPUART_HDCR_TXSTALL_MASK (0x1U) +#define LPUART_HDCR_TXSTALL_SHIFT (0U) +/*! TXSTALL - Transmit Stall + * 0b0..No effect + * 0b1..Does not become busy + */ +#define LPUART_HDCR_TXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_TXSTALL_SHIFT)) & LPUART_HDCR_TXSTALL_MASK) + +#define LPUART_HDCR_RXSEL_MASK (0x2U) +#define LPUART_HDCR_RXSEL_SHIFT (1U) +/*! RXSEL - Receive Select + * 0b0..RXD + * 0b1..TXD + */ +#define LPUART_HDCR_RXSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXSEL_SHIFT)) & LPUART_HDCR_RXSEL_MASK) + +#define LPUART_HDCR_RXWRMSK_MASK (0x4U) +#define LPUART_HDCR_RXWRMSK_SHIFT (2U) +/*! RXWRMSK - Receive FIFO Write Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXWRMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXWRMSK_SHIFT)) & LPUART_HDCR_RXWRMSK_MASK) + +#define LPUART_HDCR_RXMSK_MASK (0x8U) +#define LPUART_HDCR_RXMSK_SHIFT (3U) +/*! RXMSK - Receive Mask + * 0b0..Do not mask + * 0b1..Mask + */ +#define LPUART_HDCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RXMSK_SHIFT)) & LPUART_HDCR_RXMSK_MASK) + +#define LPUART_HDCR_RTSEXT_MASK (0xFF00U) +#define LPUART_HDCR_RTSEXT_SHIFT (8U) +/*! RTSEXT - RTS Extended */ +#define LPUART_HDCR_RTSEXT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_HDCR_RTSEXT_SHIFT)) & LPUART_HDCR_RTSEXT_MASK) +/*! @} */ + +/*! @name TOCR - Timeout Control */ +/*! @{ */ + +#define LPUART_TOCR_TOEN_MASK (0xFU) +#define LPUART_TOCR_TOEN_SHIFT (0U) +/*! TOEN - Timeout Enable */ +#define LPUART_TOCR_TOEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOEN_SHIFT)) & LPUART_TOCR_TOEN_MASK) + +#define LPUART_TOCR_TOIE_MASK (0xF00U) +#define LPUART_TOCR_TOIE_SHIFT (8U) +/*! TOIE - Timeout Interrupt Enable */ +#define LPUART_TOCR_TOIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOCR_TOIE_SHIFT)) & LPUART_TOCR_TOIE_MASK) +/*! @} */ + +/*! @name TOSR - Timeout Status */ +/*! @{ */ + +#define LPUART_TOSR_TOZ_MASK (0xFU) +#define LPUART_TOSR_TOZ_SHIFT (0U) +/*! TOZ - Timeout Zero */ +#define LPUART_TOSR_TOZ(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOZ_SHIFT)) & LPUART_TOSR_TOZ_MASK) + +#define LPUART_TOSR_TOF_MASK (0xF00U) +#define LPUART_TOSR_TOF_SHIFT (8U) +/*! TOF - Timeout Flag + * 0b0000..Not occurred + * 0b0001..Occurred + * 0b0000..No effect + * 0b0001..Clear the flag + */ +#define LPUART_TOSR_TOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TOSR_TOF_SHIFT)) & LPUART_TOSR_TOF_MASK) +/*! @} */ + +/*! @name TIMEOUT - Timeout N */ +/*! @{ */ + +#define LPUART_TIMEOUT_TIMEOUT_MASK (0x3FFFU) +#define LPUART_TIMEOUT_TIMEOUT_SHIFT (0U) +/*! TIMEOUT - Timeout Value */ +#define LPUART_TIMEOUT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_TIMEOUT_SHIFT)) & LPUART_TIMEOUT_TIMEOUT_MASK) + +#define LPUART_TIMEOUT_CFG_MASK (0xC0000000U) +#define LPUART_TIMEOUT_CFG_SHIFT (30U) +/*! CFG - Idle Configuration + * 0b00..Becomes 1 after timeout characters are received + * 0b01..Becomes 1 when idle for timeout bit clocks + * 0b10..Becomes 1 when idle for timeout bit clocks following the next character + * 0b11..Becomes 1 when idle for at least timeout bit clocks, but a new character is detected before the extended idle timeout is reached + */ +#define LPUART_TIMEOUT_CFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TIMEOUT_CFG_SHIFT)) & LPUART_TIMEOUT_CFG_MASK) +/*! @} */ + +/* The count of LPUART_TIMEOUT */ +#define LPUART_TIMEOUT_COUNT (4U) + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPUART_TCBR_DATA_MASK (0xFFFFU) +#define LPUART_TCBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPUART_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TCBR_DATA_SHIFT)) & LPUART_TCBR_DATA_MASK) +/*! @} */ + +/* The count of LPUART_TCBR */ +#define LPUART_TCBR_COUNT (128U) + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPUART_TDBR_DATA0_MASK (0xFFU) +#define LPUART_TDBR_DATA0_SHIFT (0U) +/*! DATA0 - Data0 */ +#define LPUART_TDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA0_SHIFT)) & LPUART_TDBR_DATA0_MASK) + +#define LPUART_TDBR_DATA1_MASK (0xFF00U) +#define LPUART_TDBR_DATA1_SHIFT (8U) +/*! DATA1 - Data1 */ +#define LPUART_TDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA1_SHIFT)) & LPUART_TDBR_DATA1_MASK) + +#define LPUART_TDBR_DATA2_MASK (0xFF0000U) +#define LPUART_TDBR_DATA2_SHIFT (16U) +/*! DATA2 - Data2 */ +#define LPUART_TDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA2_SHIFT)) & LPUART_TDBR_DATA2_MASK) + +#define LPUART_TDBR_DATA3_MASK (0xFF000000U) +#define LPUART_TDBR_DATA3_SHIFT (24U) +/*! DATA3 - Data3 */ +#define LPUART_TDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_TDBR_DATA3_SHIFT)) & LPUART_TDBR_DATA3_MASK) +/*! @} */ + +/* The count of LPUART_TDBR */ +#define LPUART_TDBR_COUNT (256U) + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x50092000u) + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE_NS (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART0 base pointer */ + #define LPUART0_NS ((LPUART_Type *)LPUART0_BASE_NS) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x50093000u) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE_NS (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART1 base pointer */ + #define LPUART1_NS ((LPUART_Type *)LPUART1_BASE_NS) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x50094000u) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE_NS (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART2 base pointer */ + #define LPUART2_NS ((LPUART_Type *)LPUART2_BASE_NS) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x50095000u) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE_NS (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART3 base pointer */ + #define LPUART3_NS ((LPUART_Type *)LPUART3_BASE_NS) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x500B4000u) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE_NS (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART4 base pointer */ + #define LPUART4_NS ((LPUART_Type *)LPUART4_BASE_NS) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x500B5000u) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE_NS (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART5 base pointer */ + #define LPUART5_NS ((LPUART_Type *)LPUART5_BASE_NS) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x500B6000u) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE_NS (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART6 base pointer */ + #define LPUART6_NS ((LPUART_Type *)LPUART6_BASE_NS) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x500B7000u) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE_NS (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Peripheral LPUART7 base pointer */ + #define LPUART7_NS ((LPUART_Type *)LPUART7_BASE_NS) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS_NS { LPUART0_BASE_NS, LPUART1_BASE_NS, LPUART2_BASE_NS, LPUART3_BASE_NS, LPUART4_BASE_NS, LPUART5_BASE_NS, LPUART6_BASE_NS, LPUART7_BASE_NS } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS_NS { LPUART0_NS, LPUART1_NS, LPUART2_NS, LPUART3_NS, LPUART4_NS, LPUART5_NS, LPUART6_NS, LPUART7_NS } +#else + /** Peripheral LPUART0 base address */ + #define LPUART0_BASE (0x40092000u) + /** Peripheral LPUART0 base pointer */ + #define LPUART0 ((LPUART_Type *)LPUART0_BASE) + /** Peripheral LPUART1 base address */ + #define LPUART1_BASE (0x40093000u) + /** Peripheral LPUART1 base pointer */ + #define LPUART1 ((LPUART_Type *)LPUART1_BASE) + /** Peripheral LPUART2 base address */ + #define LPUART2_BASE (0x40094000u) + /** Peripheral LPUART2 base pointer */ + #define LPUART2 ((LPUART_Type *)LPUART2_BASE) + /** Peripheral LPUART3 base address */ + #define LPUART3_BASE (0x40095000u) + /** Peripheral LPUART3 base pointer */ + #define LPUART3 ((LPUART_Type *)LPUART3_BASE) + /** Peripheral LPUART4 base address */ + #define LPUART4_BASE (0x400B4000u) + /** Peripheral LPUART4 base pointer */ + #define LPUART4 ((LPUART_Type *)LPUART4_BASE) + /** Peripheral LPUART5 base address */ + #define LPUART5_BASE (0x400B5000u) + /** Peripheral LPUART5 base pointer */ + #define LPUART5 ((LPUART_Type *)LPUART5_BASE) + /** Peripheral LPUART6 base address */ + #define LPUART6_BASE (0x400B6000u) + /** Peripheral LPUART6 base pointer */ + #define LPUART6 ((LPUART_Type *)LPUART6_BASE) + /** Peripheral LPUART7 base address */ + #define LPUART7_BASE (0x400B7000u) + /** Peripheral LPUART7 base pointer */ + #define LPUART7 ((LPUART_Type *)LPUART7_BASE) + /** Array initializer of LPUART peripheral base addresses */ + #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE } + /** Array initializer of LPUART peripheral base pointers */ + #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7 } +#endif +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } +#define LPUART_ERR_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LP_FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LP_FLEXCOMM_Peripheral_Access_Layer LP_FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** LP_FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4084]; + __I uint32_t ISTAT; /**< Interrupt Status, offset: 0xFF4 */ + __IO uint32_t PSELID; /**< Peripheral Select and ID, offset: 0xFF8 */ +} LP_FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- LP_FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LP_FLEXCOMM_Register_Masks LP_FLEXCOMM Register Masks + * @{ + */ + +/*! @name ISTAT - Interrupt Status */ +/*! @{ */ + +#define LP_FLEXCOMM_ISTAT_UARTTX_MASK (0x1U) +#define LP_FLEXCOMM_ISTAT_UARTTX_SHIFT (0U) +/*! UARTTX - UART TX Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_UARTTX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTTX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTTX_MASK) + +#define LP_FLEXCOMM_ISTAT_UARTRX_MASK (0x2U) +#define LP_FLEXCOMM_ISTAT_UARTRX_SHIFT (1U) +/*! UARTRX - UART RX Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_UARTRX(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_UARTRX_SHIFT)) & LP_FLEXCOMM_ISTAT_UARTRX_MASK) + +#define LP_FLEXCOMM_ISTAT_SPI_MASK (0x4U) +#define LP_FLEXCOMM_ISTAT_SPI_SHIFT (2U) +/*! SPI - SPI Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_SPI(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_SPI_SHIFT)) & LP_FLEXCOMM_ISTAT_SPI_MASK) + +#define LP_FLEXCOMM_ISTAT_I2CM_MASK (0x10U) +#define LP_FLEXCOMM_ISTAT_I2CM_SHIFT (4U) +/*! I2CM - I2C Controller Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_I2CM(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CM_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CM_MASK) + +#define LP_FLEXCOMM_ISTAT_I2CS_MASK (0x20U) +#define LP_FLEXCOMM_ISTAT_I2CS_SHIFT (5U) +/*! I2CS - I2C Subordinate Interrupt + * 0b0..Clear + * 0b1..Set + */ +#define LP_FLEXCOMM_ISTAT_I2CS(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_ISTAT_I2CS_SHIFT)) & LP_FLEXCOMM_ISTAT_I2CS_MASK) +/*! @} */ + +/*! @name PSELID - Peripheral Select and ID */ +/*! @{ */ + +#define LP_FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define LP_FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select + * 0b000..No peripheral selected + * 0b001..UART + * 0b011..I2C + * 0b111..UART and I2C + * 0b010..SPI + */ +#define LP_FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_PERSEL_SHIFT)) & LP_FLEXCOMM_PSELID_PERSEL_MASK) + +#define LP_FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define LP_FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock + * 0b0..PERSEL is writable + * 0b1..PERSEL is not writable + */ +#define LP_FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_LOCK_SHIFT)) & LP_FLEXCOMM_PSELID_LOCK_MASK) + +#define LP_FLEXCOMM_PSELID_UARTPRESENT_MASK (0x10U) +#define LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT (4U) +/*! UARTPRESENT - UART Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_UARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_UARTPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_UARTPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_SPIPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C Present + * 0b0..Not supported + * 0b1..Supported + */ +#define LP_FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & LP_FLEXCOMM_PSELID_I2CPRESENT_MASK) + +#define LP_FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define LP_FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - LP_FLEXCOMM interface ID */ +#define LP_FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << LP_FLEXCOMM_PSELID_ID_SHIFT)) & LP_FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LP_FLEXCOMM_Register_Masks */ + + +/* LP_FLEXCOMM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x50092000u) + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE_NS (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE_NS) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x50093000u) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE_NS (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE_NS) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x50094000u) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE_NS (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE_NS) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x50095000u) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE_NS (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE_NS) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x500B4000u) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE_NS (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE_NS) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x500B5000u) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE_NS (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE_NS) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x500B6000u) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE_NS (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE_NS) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x500B7000u) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE_NS (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7_NS ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE_NS) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS_NS { LP_FLEXCOMM0_BASE_NS, LP_FLEXCOMM1_BASE_NS, LP_FLEXCOMM2_BASE_NS, LP_FLEXCOMM3_BASE_NS, LP_FLEXCOMM4_BASE_NS, LP_FLEXCOMM5_BASE_NS, LP_FLEXCOMM6_BASE_NS, LP_FLEXCOMM7_BASE_NS } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS_NS { LP_FLEXCOMM0_NS, LP_FLEXCOMM1_NS, LP_FLEXCOMM2_NS, LP_FLEXCOMM3_NS, LP_FLEXCOMM4_NS, LP_FLEXCOMM5_NS, LP_FLEXCOMM6_NS, LP_FLEXCOMM7_NS } +#else + /** Peripheral LP_FLEXCOMM0 base address */ + #define LP_FLEXCOMM0_BASE (0x40092000u) + /** Peripheral LP_FLEXCOMM0 base pointer */ + #define LP_FLEXCOMM0 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM0_BASE) + /** Peripheral LP_FLEXCOMM1 base address */ + #define LP_FLEXCOMM1_BASE (0x40093000u) + /** Peripheral LP_FLEXCOMM1 base pointer */ + #define LP_FLEXCOMM1 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM1_BASE) + /** Peripheral LP_FLEXCOMM2 base address */ + #define LP_FLEXCOMM2_BASE (0x40094000u) + /** Peripheral LP_FLEXCOMM2 base pointer */ + #define LP_FLEXCOMM2 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM2_BASE) + /** Peripheral LP_FLEXCOMM3 base address */ + #define LP_FLEXCOMM3_BASE (0x40095000u) + /** Peripheral LP_FLEXCOMM3 base pointer */ + #define LP_FLEXCOMM3 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM3_BASE) + /** Peripheral LP_FLEXCOMM4 base address */ + #define LP_FLEXCOMM4_BASE (0x400B4000u) + /** Peripheral LP_FLEXCOMM4 base pointer */ + #define LP_FLEXCOMM4 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM4_BASE) + /** Peripheral LP_FLEXCOMM5 base address */ + #define LP_FLEXCOMM5_BASE (0x400B5000u) + /** Peripheral LP_FLEXCOMM5 base pointer */ + #define LP_FLEXCOMM5 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM5_BASE) + /** Peripheral LP_FLEXCOMM6 base address */ + #define LP_FLEXCOMM6_BASE (0x400B6000u) + /** Peripheral LP_FLEXCOMM6 base pointer */ + #define LP_FLEXCOMM6 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM6_BASE) + /** Peripheral LP_FLEXCOMM7 base address */ + #define LP_FLEXCOMM7_BASE (0x400B7000u) + /** Peripheral LP_FLEXCOMM7 base pointer */ + #define LP_FLEXCOMM7 ((LP_FLEXCOMM_Type *)LP_FLEXCOMM7_BASE) + /** Array initializer of LP_FLEXCOMM peripheral base addresses */ + #define LP_FLEXCOMM_BASE_ADDRS { LP_FLEXCOMM0_BASE, LP_FLEXCOMM1_BASE, LP_FLEXCOMM2_BASE, LP_FLEXCOMM3_BASE, LP_FLEXCOMM4_BASE, LP_FLEXCOMM5_BASE, LP_FLEXCOMM6_BASE, LP_FLEXCOMM7_BASE } + /** Array initializer of LP_FLEXCOMM peripheral base pointers */ + #define LP_FLEXCOMM_BASE_PTRS { LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7 } +#endif +/** Interrupt vectors for the LP_FLEXCOMM peripheral type */ +#define LP_FLEXCOMM_IRQS { LP_FLEXCOMM0_IRQn, LP_FLEXCOMM1_IRQn, LP_FLEXCOMM2_IRQn, LP_FLEXCOMM3_IRQn, LP_FLEXCOMM4_IRQn, LP_FLEXCOMM5_IRQn, LP_FLEXCOMM6_IRQn, LP_FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group LP_FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< Time Interval Value, array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< Timer, array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< Control, array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< Status, array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration, offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle Channel, offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global Interrupt Flag, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - Time Interval Value */ +/*! @{ */ + +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time Interval Load Value. */ +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Force Load Enable + * 0b0..No force load + * 0b1..Force load + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - Timer */ +/*! @{ */ + +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Current Timer Value */ +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - Control */ +/*! @{ */ + +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Interrupt request + * 0b0..Disabled + * 0b1..Enabled + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - MRT Operating mode + * 0b00..Repeat Interrupt mode + * 0b01..One-Shot Interrupt mode + * 0b10..One-Shot Stall mode + * 0b11..Reserved + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - Status */ +/*! @{ */ + +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Interrupt Flag + * 0b0..No pending interrupt. + * 0b1..Pending interrupt. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Timer n State + * 0b0..Idle state. + * 0b1..Running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel-In-Use flag + * 0b0..This timer channel is not in use. + * 0b1..This timer channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration */ +/*! @{ */ + +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Number of Channels */ +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Number of Bits */ +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - MULTITASK + * 0b0..Hardware status mode. + * 0b1..Multitask mode + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle Channel */ +/*! @{ */ + +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle Channel */ +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global Interrupt Flag */ +/*! @{ */ + +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Interrupt Flag + * 0b0..No pending interrupt. + * 0b1..Pending interrupt + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Interrupt Flag */ +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x50013000u) + /** Peripheral MRT0 base address */ + #define MRT0_BASE_NS (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Peripheral MRT0 base pointer */ + #define MRT0_NS ((MRT_Type *)MRT0_BASE_NS) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS_NS { MRT0_BASE_NS } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS_NS { MRT0_NS } +#else + /** Peripheral MRT0 base address */ + #define MRT0_BASE (0x40013000u) + /** Peripheral MRT0 base pointer */ + #define MRT0 ((MRT_Type *)MRT0_BASE) + /** Array initializer of MRT peripheral base addresses */ + #define MRT_BASE_ADDRS { MRT0_BASE } + /** Array initializer of MRT peripheral base pointers */ + #define MRT_BASE_PTRS { MRT0 } +#endif +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- NPX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NPX_Peripheral_Access_Layer NPX Peripheral Access Layer + * @{ + */ + +/** NPX - Register Layout Typedef */ +typedef struct { + __IO uint32_t NPXCR; /**< NPX Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t NPXSR; /**< NPX Status Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __O uint32_t CACMSK; /**< Flash Cache Obfuscation Mask, offset: 0x10 */ + uint8_t RESERVED_2[12]; + __IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */ + uint8_t RESERVED_3[28]; + struct { /* offset: 0x40, array step: 0x10 */ + __IO uint32_t VMAPCTX_WD[2]; /**< Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3, array offset: 0x40, array step: index*0x10, index2*0x4 */ + __O uint32_t BIVCTX_WD[2]; /**< Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3, array offset: 0x48, array step: index*0x10, index2*0x4 */ + } CTX_VALID_IV_ARRAY[4]; +} NPX_Type; + +/* ---------------------------------------------------------------------------- + -- NPX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup NPX_Register_Masks NPX Register Masks + * @{ + */ + +/*! @name NPXCR - NPX Control Register */ +/*! @{ */ + +#define NPX_NPXCR_GEE_MASK (0x1U) +#define NPX_NPXCR_GEE_SHIFT (0U) +/*! GEE - Global Encryption Enable + * 0b1..Global encryption enabled. NPX on-the-fly encryption is enabled if the flash access hits in a valid + * memory context. Subsequent reads return 1. + * 0b0..Global encryption disabled. NPX on-the-fly encryption is disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GEE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GEE_SHIFT)) & NPX_NPXCR_GEE_MASK) + +#define NPX_NPXCR_GDE_MASK (0x4U) +#define NPX_NPXCR_GDE_SHIFT (2U) +/*! GDE - Global Decryption Enable + * 0b1..Global decryption enabled. NPX on-the-fly decryption is globally enabled. Subsequent reads return 1. + * 0b0..Global decryption disabled. NPX on-the-fly decryption is globally disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GDE(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GDE_SHIFT)) & NPX_NPXCR_GDE_MASK) + +#define NPX_NPXCR_GLK_MASK (0x10U) +#define NPX_NPXCR_GLK_SHIFT (4U) +/*! GLK - Global Lock Enable + * 0b1..Lock enabled: cannot write to VMAPCTXn, NPXCR, or CACMSK. Subsequent reads return 1. + * 0b0..Lock disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_GLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_GLK_SHIFT)) & NPX_NPXCR_GLK_MASK) + +#define NPX_NPXCR_MLK_MASK (0x40U) +#define NPX_NPXCR_MLK_SHIFT (6U) +/*! MLK - Mask Lock Enable + * 0b1..Lock enabled: cannot write to mask. Subsequent reads return 1. + * 0b0..Lock disabled. Subsequent reads return 0. + */ +#define NPX_NPXCR_MLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_MLK_SHIFT)) & NPX_NPXCR_MLK_MASK) + +#define NPX_NPXCR_CTX0LK_MASK (0x100U) +#define NPX_NPXCR_CTX0LK_SHIFT (8U) +/*! CTX0LK - Lock Enable for Context 0 + * 0b1..Lock enabled: cannot write to VMAPCTX0 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX0 remains read-write + */ +#define NPX_NPXCR_CTX0LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX0LK_SHIFT)) & NPX_NPXCR_CTX0LK_MASK) + +#define NPX_NPXCR_CTX1LK_MASK (0x400U) +#define NPX_NPXCR_CTX1LK_SHIFT (10U) +/*! CTX1LK - Lock Enable for Context 1 + * 0b1..Lock enabled: cannot write to VMAPCTX1 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX1 remains read-write + */ +#define NPX_NPXCR_CTX1LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX1LK_SHIFT)) & NPX_NPXCR_CTX1LK_MASK) + +#define NPX_NPXCR_CTX2LK_MASK (0x1000U) +#define NPX_NPXCR_CTX2LK_SHIFT (12U) +/*! CTX2LK - Lock Enable for Context 2 + * 0b1..Lock enabled: cannot write to VMAPCTX2 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX2 remains read-write + */ +#define NPX_NPXCR_CTX2LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX2LK_SHIFT)) & NPX_NPXCR_CTX2LK_MASK) + +#define NPX_NPXCR_CTX3LK_MASK (0x4000U) +#define NPX_NPXCR_CTX3LK_SHIFT (14U) +/*! CTX3LK - Lock Enable for Context 3 + * 0b1..Lock enabled: cannot write to VMAPCTX3 (becomes read-only) + * 0b0..Lock disabled: VMAPCTX3 remains read-write + */ +#define NPX_NPXCR_CTX3LK(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXCR_CTX3LK_SHIFT)) & NPX_NPXCR_CTX3LK_MASK) +/*! @} */ + +/*! @name NPXSR - NPX Status Register */ +/*! @{ */ + +#define NPX_NPXSR_NUMCTX_MASK (0xFU) +#define NPX_NPXSR_NUMCTX_SHIFT (0U) +/*! NUMCTX - Number of implemented memory contexts + * 0b0000..No (zero) implemented memory contexts + * 0b0001..1 implemented memory contexts + * 0b0010..2 implemented memory contexts + * 0b0011..3 implemented memory contexts + * 0b0100..4 implemented memory contexts + */ +#define NPX_NPXSR_NUMCTX(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_NUMCTX_SHIFT)) & NPX_NPXSR_NUMCTX_MASK) + +#define NPX_NPXSR_V0_MASK (0x100U) +#define NPX_NPXSR_V0_SHIFT (8U) +/*! V0 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V0(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V0_SHIFT)) & NPX_NPXSR_V0_MASK) + +#define NPX_NPXSR_V1_MASK (0x200U) +#define NPX_NPXSR_V1_SHIFT (9U) +/*! V1 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V1(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V1_SHIFT)) & NPX_NPXSR_V1_MASK) + +#define NPX_NPXSR_V2_MASK (0x400U) +#define NPX_NPXSR_V2_SHIFT (10U) +/*! V2 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V2(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V2_SHIFT)) & NPX_NPXSR_V2_MASK) + +#define NPX_NPXSR_V3_MASK (0x800U) +#define NPX_NPXSR_V3_SHIFT (11U) +/*! V3 - Key n Valid + * 0b0..Not valid + * 0b1..Valid + */ +#define NPX_NPXSR_V3(x) (((uint32_t)(((uint32_t)(x)) << NPX_NPXSR_V3_SHIFT)) & NPX_NPXSR_V3_MASK) +/*! @} */ + +/*! @name CACMSK - Flash Cache Obfuscation Mask */ +/*! @{ */ + +#define NPX_CACMSK_OBMASK_MASK (0xFFFFFFFFU) +#define NPX_CACMSK_OBMASK_SHIFT (0U) +/*! OBMASK - Obfuscation Mask */ +#define NPX_CACMSK_OBMASK(x) (((uint32_t)(((uint32_t)(x)) << NPX_CACMSK_OBMASK_SHIFT)) & NPX_CACMSK_OBMASK_MASK) +/*! @} */ + +/*! @name REMAP - Data Remap */ +/*! @{ */ + +#define NPX_REMAP_REMAPLK_MASK (0x1U) +#define NPX_REMAP_REMAPLK_SHIFT (0U) +/*! REMAPLK - Remap Lock Enable + * 0b1..Lock enabled: cannot write to REMAP + * 0b0..Lock disabled: can write to REMAP + */ +#define NPX_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_REMAPLK_SHIFT)) & NPX_REMAP_REMAPLK_MASK) + +#define NPX_REMAP_LIM_MASK (0x1F0000U) +#define NPX_REMAP_LIM_SHIFT (16U) +/*! LIM - LIM Remapping Address */ +#define NPX_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIM_SHIFT)) & NPX_REMAP_LIM_MASK) + +#define NPX_REMAP_LIMDP_MASK (0x1F000000U) +#define NPX_REMAP_LIMDP_SHIFT (24U) +/*! LIMDP - LIMDP Remapping Address */ +#define NPX_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << NPX_REMAP_LIMDP_SHIFT)) & NPX_REMAP_LIMDP_MASK) +/*! @} */ + +/*! @name CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD - Bitmap of Valid Control for Memory Context 0..Bitmap of Valid Control for Memory Context 3 */ +/*! @{ */ + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK (0x1U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT (0U) +/*! VAL0 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL0_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK (0x1U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT (0U) +/*! VAL32 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL32_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK (0x2U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT (1U) +/*! VAL1 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL1_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK (0x2U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT (1U) +/*! VAL33 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL33_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK (0x4U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT (2U) +/*! VAL2 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL2_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK (0x4U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT (2U) +/*! VAL34 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL34_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK (0x8U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT (3U) +/*! VAL3 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL3_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK (0x8U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT (3U) +/*! VAL35 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL35_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK (0x10U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT (4U) +/*! VAL4 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL4_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK (0x10U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT (4U) +/*! VAL36 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL36_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK (0x20U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT (5U) +/*! VAL5 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL5_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK (0x20U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT (5U) +/*! VAL37 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL37_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK (0x40U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT (6U) +/*! VAL6 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL6_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK (0x40U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT (6U) +/*! VAL38 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL38_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK (0x80U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT (7U) +/*! VAL7 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL7_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK (0x80U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT (7U) +/*! VAL39 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL39_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK (0x100U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT (8U) +/*! VAL8 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL8_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK (0x100U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT (8U) +/*! VAL40 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL40_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK (0x200U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT (9U) +/*! VAL9 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL9_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK (0x200U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT (9U) +/*! VAL41 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL41_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK (0x400U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT (10U) +/*! VAL10 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL10_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK (0x400U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT (10U) +/*! VAL42 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL42_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK (0x800U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT (11U) +/*! VAL11 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL11_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK (0x800U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT (11U) +/*! VAL43 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL43_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK (0x1000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT (12U) +/*! VAL12 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL12_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK (0x1000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT (12U) +/*! VAL44 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL44_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK (0x2000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT (13U) +/*! VAL13 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL13_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK (0x2000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT (13U) +/*! VAL45 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL45_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK (0x4000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT (14U) +/*! VAL14 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL14_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK (0x4000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT (14U) +/*! VAL46 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL46_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK (0x8000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT (15U) +/*! VAL15 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL15_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK (0x8000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT (15U) +/*! VAL47 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL47_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK (0x10000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT (16U) +/*! VAL16 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL16_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK (0x10000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT (16U) +/*! VAL48 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL48_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK (0x20000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT (17U) +/*! VAL17 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL17_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK (0x20000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT (17U) +/*! VAL49 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL49_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK (0x40000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT (18U) +/*! VAL18 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL18_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK (0x40000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT (18U) +/*! VAL50 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL50_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK (0x80000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT (19U) +/*! VAL19 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL19_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK (0x80000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT (19U) +/*! VAL51 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL51_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK (0x100000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT (20U) +/*! VAL20 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL20_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK (0x100000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT (20U) +/*! VAL52 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL52_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK (0x200000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT (21U) +/*! VAL21 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL21_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK (0x200000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT (21U) +/*! VAL53 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL53_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK (0x400000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT (22U) +/*! VAL22 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL22_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK (0x400000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT (22U) +/*! VAL54 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL54_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK (0x800000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT (23U) +/*! VAL23 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL23_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK (0x800000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT (23U) +/*! VAL55 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL55_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK (0x1000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT (24U) +/*! VAL24 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL24_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK (0x1000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT (24U) +/*! VAL56 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL56_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK (0x2000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT (25U) +/*! VAL25 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL25_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK (0x2000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT (25U) +/*! VAL57 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL57_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK (0x4000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT (26U) +/*! VAL26 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL26_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK (0x4000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT (26U) +/*! VAL58 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL58_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK (0x8000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT (27U) +/*! VAL27 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL27_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK (0x8000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT (27U) +/*! VAL59 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL59_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK (0x10000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT (28U) +/*! VAL28 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL28_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK (0x10000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT (28U) +/*! VAL60 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL60_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK (0x20000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT (29U) +/*! VAL29 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL29_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK (0x20000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT (29U) +/*! VAL61 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL61_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK (0x40000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT (30U) +/*! VAL30 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL30_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK (0x40000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT (30U) +/*! VAL62 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL62_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK (0x80000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT (31U) +/*! VAL31 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL31_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK (0x80000000U) +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT (31U) +/*! VAL63 - Block valid enable for encryption/decryption + * 0b0..Disable + * 0b1..Enable + */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_VAL63_MASK) +/*! @} */ + +/* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT (4U) + +/* The count of NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_VMAPCTX_ARRAY_VMAPCTX_WD_COUNT2 (2U) + +/*! @name CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD - Block Initial Vector for Memory Context 0..Block Initial Vector for Memory Context 3 */ +/*! @{ */ + +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK (0xFFFFFFFFU) +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT (0U) +/*! BIV_WD0 - Block Initial Vector Word0 */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD0_MASK) + +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK (0xFFFFFFFFU) +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT (0U) +/*! BIV_WD1 - Block Initial Vector Word1 */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1(x) (((uint32_t)(((uint32_t)(x)) << NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_SHIFT)) & NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_BIV_WD1_MASK) +/*! @} */ + +/* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT (4U) + +/* The count of NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD */ +#define NPX_CTX_VALID_IV_ARRAY_BIVCTX_ARRAY_BIVCTX_WD_COUNT2 (2U) + + +/*! + * @} + */ /* end of group NPX_Register_Masks */ + + +/* NPX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x500CC000u) + /** Peripheral NPX0 base address */ + #define NPX0_BASE_NS (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Peripheral NPX0 base pointer */ + #define NPX0_NS ((NPX_Type *)NPX0_BASE_NS) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS_NS { NPX0_BASE_NS } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS_NS { NPX0_NS } +#else + /** Peripheral NPX0 base address */ + #define NPX0_BASE (0x400CC000u) + /** Peripheral NPX0 base pointer */ + #define NPX0 ((NPX_Type *)NPX0_BASE) + /** Array initializer of NPX peripheral base addresses */ + #define NPX_BASE_ADDRS { NPX0_BASE } + /** Array initializer of NPX peripheral base pointers */ + #define NPX_BASE_PTRS { NPX0 } +#endif + +/*! + * @} + */ /* end of group NPX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Local Capture Low for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Local Capture High for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Local Match Low for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Local Match High for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - Interrupt Flag */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - Interrupt or Wake-Up Request + * 0b0..Interrupts blocked + * 0b1..Interrupts enabled + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - EVTimer Match Write Ready */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x50049000u) + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE_NS (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0_NS ((OSTIMER_Type *)OSTIMER0_BASE_NS) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS_NS { OSTIMER0_BASE_NS } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS_NS { OSTIMER0_NS } +#else + /** Peripheral OSTIMER0 base address */ + #define OSTIMER0_BASE (0x40049000u) + /** Peripheral OSTIMER0 base pointer */ + #define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) + /** Array initializer of OSTIMER peripheral base addresses */ + #define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } + /** Array initializer of OSTIMER peripheral base pointers */ + #define OSTIMER_BASE_PTRS { OSTIMER0 } +#endif +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OTPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer + * @{ + */ + +/** OTPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameters, offset: 0x4 */ + __IO uint32_t SR; /**< Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RWC; /**< Read and Write Control, offset: 0x10 */ + __IO uint32_t RLC; /**< Reload Control, offset: 0x14 */ + __IO uint32_t PCR; /**< Power Control, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t WDATA; /**< Write Data, offset: 0x20 */ + __I uint32_t RDATA; /**< Read Data, offset: 0x24 */ + uint8_t RESERVED_2[8]; + __IO uint32_t TIMING1; /**< Timing1, offset: 0x30 */ + __IO uint32_t TIMING2; /**< Timing2, offset: 0x34 */ + uint8_t RESERVED_3[456]; + __I uint32_t LOCK; /**< Lock, offset: 0x200 */ + __I uint32_t SECURE; /**< Secure, offset: 0x204 */ + __I uint32_t SECURE_INV; /**< Inverted Secure, offset: 0x208 */ + __I uint32_t DBG_KEY; /**< Debug and Key, offset: 0x20C */ + __IO uint32_t MISC_CFG; /**< MISC Config, offset: 0x210 */ + __IO uint32_t PHANTOM_CFG; /**< PHANTOM Config, offset: 0x214 */ + __IO uint32_t FLEX_CFG0; /**< Flexible Config 0, offset: 0x218 */ + __IO uint32_t FLEX_CFG1; /**< Flexible Config 1, offset: 0x21C */ +} OTPC_Type; + +/* ---------------------------------------------------------------------------- + -- OTPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OTPC_Register_Masks OTPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define OTPC_VERID_FEATURE_MASK (0xFFFFU) +#define OTPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set + */ +#define OTPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_FEATURE_SHIFT)) & OTPC_VERID_FEATURE_MASK) + +#define OTPC_VERID_MINOR_MASK (0xFF0000U) +#define OTPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define OTPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MINOR_SHIFT)) & OTPC_VERID_MINOR_MASK) + +#define OTPC_VERID_MAJOR_MASK (0xFF000000U) +#define OTPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define OTPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_VERID_MAJOR_SHIFT)) & OTPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameters */ +/*! @{ */ + +#define OTPC_PARAM_NUM_FUSE_MASK (0xFFFFU) +#define OTPC_PARAM_NUM_FUSE_SHIFT (0U) +/*! NUM_FUSE - Number of fuse bytes */ +#define OTPC_PARAM_NUM_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PARAM_NUM_FUSE_SHIFT)) & OTPC_PARAM_NUM_FUSE_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define OTPC_SR_BUSY_MASK (0x1U) +#define OTPC_SR_BUSY_SHIFT (0U) +/*! BUSY - Busy status + * 0b0..Not busy (transaction complete) + * 0b1..Busy + */ +#define OTPC_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_BUSY_SHIFT)) & OTPC_SR_BUSY_MASK) + +#define OTPC_SR_ERROR_MASK (0x2U) +#define OTPC_SR_ERROR_SHIFT (1U) +/*! ERROR - Error flag + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ERROR_SHIFT)) & OTPC_SR_ERROR_MASK) + +#define OTPC_SR_ECC_SF_MASK (0x4U) +#define OTPC_SR_ECC_SF_SHIFT (2U) +/*! ECC_SF - ECC single fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_ECC_SF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_SF_SHIFT)) & OTPC_SR_ECC_SF_MASK) + +#define OTPC_SR_ECC_DF_MASK (0x8U) +#define OTPC_SR_ECC_DF_SHIFT (3U) +/*! ECC_DF - ECC double fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_ECC_DF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ECC_DF_SHIFT)) & OTPC_SR_ECC_DF_MASK) + +#define OTPC_SR_TRI_F_MASK (0x10U) +#define OTPC_SR_TRI_F_SHIFT (4U) +/*! TRI_F - Triple voting fault + * 0b0..No fault + * 0b1..Fault + */ +#define OTPC_SR_TRI_F(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_TRI_F_SHIFT)) & OTPC_SR_TRI_F_MASK) + +#define OTPC_SR_RD_FUSE_LOCK_MASK (0x100U) +#define OTPC_SR_RD_FUSE_LOCK_SHIFT (8U) +/*! RD_FUSE_LOCK - Read fuse lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_RD_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_FUSE_LOCK_SHIFT)) & OTPC_SR_RD_FUSE_LOCK_MASK) + +#define OTPC_SR_WR_FUSE_LOCK_MASK (0x200U) +#define OTPC_SR_WR_FUSE_LOCK_SHIFT (9U) +/*! WR_FUSE_LOCK - Write fuse lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_FUSE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_FUSE_LOCK_SHIFT)) & OTPC_SR_WR_FUSE_LOCK_MASK) + +#define OTPC_SR_RD_REG_LOCK_MASK (0x400U) +#define OTPC_SR_RD_REG_LOCK_SHIFT (10U) +/*! RD_REG_LOCK - Read register lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_RD_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_RD_REG_LOCK_SHIFT)) & OTPC_SR_RD_REG_LOCK_MASK) + +#define OTPC_SR_WR_REG_LOCK_MASK (0x800U) +#define OTPC_SR_WR_REG_LOCK_SHIFT (11U) +/*! WR_REG_LOCK - Write register lock error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_LOCK_SHIFT)) & OTPC_SR_WR_REG_LOCK_MASK) + +#define OTPC_SR_WR_REG_BUSY_MASK (0x1000U) +#define OTPC_SR_WR_REG_BUSY_SHIFT (12U) +/*! WR_REG_BUSY - Write register when busy error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_REG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_REG_BUSY_SHIFT)) & OTPC_SR_WR_REG_BUSY_MASK) + +#define OTPC_SR_WR_POWER_OFF_MASK (0x2000U) +#define OTPC_SR_WR_POWER_OFF_SHIFT (13U) +/*! WR_POWER_OFF - Write when power off error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_WR_POWER_OFF(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_WR_POWER_OFF_SHIFT)) & OTPC_SR_WR_POWER_OFF_MASK) + +#define OTPC_SR_FSM_MASK (0x10000U) +#define OTPC_SR_FSM_SHIFT (16U) +/*! FSM - Finite-state machine error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FSM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSM_SHIFT)) & OTPC_SR_FSM_MASK) + +#define OTPC_SR_FLC_MASK (0x20000U) +#define OTPC_SR_FLC_SHIFT (17U) +/*! FLC - Fuse load counter error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FLC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FLC_SHIFT)) & OTPC_SR_FLC_MASK) + +#define OTPC_SR_ADC_MASK (0x40000U) +#define OTPC_SR_ADC_SHIFT (18U) +/*! ADC - Address and data compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_ADC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_ADC_SHIFT)) & OTPC_SR_ADC_MASK) + +#define OTPC_SR_IRC_MASK (0x80000U) +#define OTPC_SR_IRC_SHIFT (19U) +/*! IRC - Inverted register compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_IRC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_IRC_SHIFT)) & OTPC_SR_IRC_MASK) + +#define OTPC_SR_FSC_MASK (0x100000U) +#define OTPC_SR_FSC_SHIFT (20U) +/*! FSC - Fuse and shadow register compare error + * 0b0..No error + * 0b1..Error + */ +#define OTPC_SR_FSC(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SR_FSC_SHIFT)) & OTPC_SR_FSC_MASK) +/*! @} */ + +/*! @name RWC - Read and Write Control */ +/*! @{ */ + +#define OTPC_RWC_ADDR_MASK (0x7FU) +#define OTPC_RWC_ADDR_SHIFT (0U) +/*! ADDR - EFUSE address */ +#define OTPC_RWC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_ADDR_SHIFT)) & OTPC_RWC_ADDR_MASK) + +#define OTPC_RWC_WR_ALL1S_MASK (0x1000U) +#define OTPC_RWC_WR_ALL1S_SHIFT (12U) +/*! WR_ALL1S - Write all 1s + * 0b0..Uses the WDATA value + * 0b1..Writes all 1s + */ +#define OTPC_RWC_WR_ALL1S(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_ALL1S_SHIFT)) & OTPC_RWC_WR_ALL1S_MASK) + +#define OTPC_RWC_READ_EFUSE_MASK (0x2000U) +#define OTPC_RWC_READ_EFUSE_SHIFT (13U) +/*! READ_EFUSE - Read EFUSE + * 0b0..Starts program operation when the WR_UNLOCK value is 0x9527; otherwise, takes no action. + * 0b1..Starts read operation + */ +#define OTPC_RWC_READ_EFUSE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_EFUSE_SHIFT)) & OTPC_RWC_READ_EFUSE_MASK) + +#define OTPC_RWC_READ_UPDATE_MASK (0x4000U) +#define OTPC_RWC_READ_UPDATE_SHIFT (14U) +/*! READ_UPDATE - Read update + * 0b0..Shadow register does not update + * 0b1..Shadow register updates + */ +#define OTPC_RWC_READ_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_READ_UPDATE_SHIFT)) & OTPC_RWC_READ_UPDATE_MASK) + +#define OTPC_RWC_WR_UNLOCK_MASK (0xFFFF0000U) +#define OTPC_RWC_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - Write Unlock */ +#define OTPC_RWC_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RWC_WR_UNLOCK_SHIFT)) & OTPC_RWC_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name RLC - Reload Control */ +/*! @{ */ + +#define OTPC_RLC_RELOAD_SHADOWS_MASK (0x1U) +#define OTPC_RLC_RELOAD_SHADOWS_SHIFT (0U) +/*! RELOAD_SHADOWS - Reload shadow registers + * 0b0..No action (when writing) or reload complete (when reading) + * 0b1..Reload + */ +#define OTPC_RLC_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RLC_RELOAD_SHADOWS_SHIFT)) & OTPC_RLC_RELOAD_SHADOWS_MASK) +/*! @} */ + +/*! @name PCR - Power Control */ +/*! @{ */ + +#define OTPC_PCR_HVREQ_MASK (0x1U) +#define OTPC_PCR_HVREQ_SHIFT (0U) +/*! HVREQ - Strong switch request + * 0b0..Turn off + * 0b1..Turn on + */ +#define OTPC_PCR_HVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_HVREQ_SHIFT)) & OTPC_PCR_HVREQ_MASK) + +#define OTPC_PCR_LVREQ_MASK (0x2U) +#define OTPC_PCR_LVREQ_SHIFT (1U) +/*! LVREQ - Weak switch request + * 0b0..Turn off + * 0b1..Turn on + */ +#define OTPC_PCR_LVREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_LVREQ_SHIFT)) & OTPC_PCR_LVREQ_MASK) + +#define OTPC_PCR_PDREQ_MASK (0x4U) +#define OTPC_PCR_PDREQ_SHIFT (2U) +/*! PDREQ - Power down request + * 0b0..PD pin is set to low when OTPC is in idle state. It means EFUSE hardmacro is in standby mode. Idle state + * means OTPC is not in read and program modes. + * 0b1..PD pin is set to high when OTPC is in idle state. It means EFUSE hardmacro is in power down mode. + */ +#define OTPC_PCR_PDREQ(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PCR_PDREQ_SHIFT)) & OTPC_PCR_PDREQ_MASK) +/*! @} */ + +/*! @name WDATA - Write Data */ +/*! @{ */ + +#define OTPC_WDATA_DAT_MASK (0xFFFFFFFFU) +#define OTPC_WDATA_DAT_SHIFT (0U) +/*! DAT - Write data */ +#define OTPC_WDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_WDATA_DAT_SHIFT)) & OTPC_WDATA_DAT_MASK) +/*! @} */ + +/*! @name RDATA - Read Data */ +/*! @{ */ + +#define OTPC_RDATA_DAT_MASK (0xFFFFFFFFU) +#define OTPC_RDATA_DAT_SHIFT (0U) +/*! DAT - Read data */ +#define OTPC_RDATA_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_RDATA_DAT_SHIFT)) & OTPC_RDATA_DAT_MASK) +/*! @} */ + +/*! @name TIMING1 - Timing1 */ +/*! @{ */ + +#define OTPC_TIMING1_TADDR_MASK (0xFU) +#define OTPC_TIMING1_TADDR_SHIFT (0U) +/*! TADDR - Address to STROBE setup and hold time */ +#define OTPC_TIMING1_TADDR(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TADDR_SHIFT)) & OTPC_TIMING1_TADDR_MASK) + +#define OTPC_TIMING1_TRELAX_MASK (0xF0U) +#define OTPC_TIMING1_TRELAX_SHIFT (4U) +/*! TRELAX - CSB, PGENB and LOAD to STROBE setup and hold time */ +#define OTPC_TIMING1_TRELAX(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRELAX_SHIFT)) & OTPC_TIMING1_TRELAX_MASK) + +#define OTPC_TIMING1_TRD_MASK (0x3F00U) +#define OTPC_TIMING1_TRD_SHIFT (8U) +/*! TRD - Read strobe pulse width time */ +#define OTPC_TIMING1_TRD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TRD_SHIFT)) & OTPC_TIMING1_TRD_MASK) + +#define OTPC_TIMING1_TPS_MASK (0x3F0000U) +#define OTPC_TIMING1_TPS_SHIFT (16U) +/*! TPS - PS to CSB setup and hold time between power switch and chip select assertion */ +#define OTPC_TIMING1_TPS(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPS_SHIFT)) & OTPC_TIMING1_TPS_MASK) + +#define OTPC_TIMING1_TPD_MASK (0xFF000000U) +#define OTPC_TIMING1_TPD_SHIFT (24U) +/*! TPD - PD to CSB setup time between power down signal deassertion and chip select signal assertion */ +#define OTPC_TIMING1_TPD(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING1_TPD_SHIFT)) & OTPC_TIMING1_TPD_MASK) +/*! @} */ + +/*! @name TIMING2 - Timing2 */ +/*! @{ */ + +#define OTPC_TIMING2_TPGM_MASK (0xFFFU) +#define OTPC_TIMING2_TPGM_SHIFT (0U) +/*! TPGM - Typical program strobe pulse width time */ +#define OTPC_TIMING2_TPGM(x) (((uint32_t)(((uint32_t)(x)) << OTPC_TIMING2_TPGM_SHIFT)) & OTPC_TIMING2_TPGM_MASK) +/*! @} */ + +/*! @name LOCK - Lock */ +/*! @{ */ + +#define OTPC_LOCK_NXP_PART_CFG_LOCK_MASK (0x7U) +#define OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT (0U) +/*! NXP_PART_CFG_LOCK - NXP Part Config Lock */ +#define OTPC_LOCK_NXP_PART_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_PART_CFG_LOCK_SHIFT)) & OTPC_LOCK_NXP_PART_CFG_LOCK_MASK) + +#define OTPC_LOCK_NXP_EXT_LOCK_MASK (0x38U) +#define OTPC_LOCK_NXP_EXT_LOCK_SHIFT (3U) +/*! NXP_EXT_LOCK - NXP EXT Lock */ +#define OTPC_LOCK_NXP_EXT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_NXP_EXT_LOCK_SHIFT)) & OTPC_LOCK_NXP_EXT_LOCK_MASK) + +#define OTPC_LOCK_BOOT_CFG_LOCK_MASK (0xE00U) +#define OTPC_LOCK_BOOT_CFG_LOCK_SHIFT (9U) +/*! BOOT_CFG_LOCK - Boot config Lock */ +#define OTPC_LOCK_BOOT_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_BOOT_CFG_LOCK_SHIFT)) & OTPC_LOCK_BOOT_CFG_LOCK_MASK) + +#define OTPC_LOCK_PRINCE_CFG_LOCK_MASK (0x7000U) +#define OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT (12U) +/*! PRINCE_CFG_LOCK - Prince Config Lock */ +#define OTPC_LOCK_PRINCE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_PRINCE_CFG_LOCK_SHIFT)) & OTPC_LOCK_PRINCE_CFG_LOCK_MASK) + +#define OTPC_LOCK_OSCAA_KEY_LOCK_MASK (0x38000U) +#define OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT (15U) +/*! OSCAA_KEY_LOCK - OSCAA Key Lock */ +#define OTPC_LOCK_OSCAA_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_OSCAA_KEY_LOCK_SHIFT)) & OTPC_LOCK_OSCAA_KEY_LOCK_MASK) + +#define OTPC_LOCK_CUST_LOCK0_MASK (0x1C0000U) +#define OTPC_LOCK_CUST_LOCK0_SHIFT (18U) +/*! CUST_LOCK0 - CUST Lock 0 */ +#define OTPC_LOCK_CUST_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK0_SHIFT)) & OTPC_LOCK_CUST_LOCK0_MASK) + +#define OTPC_LOCK_CUST_LOCK1_MASK (0xE00000U) +#define OTPC_LOCK_CUST_LOCK1_SHIFT (21U) +/*! CUST_LOCK1 - CUST Lock 1 */ +#define OTPC_LOCK_CUST_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK1_SHIFT)) & OTPC_LOCK_CUST_LOCK1_MASK) + +#define OTPC_LOCK_CUST_LOCK2_MASK (0x7000000U) +#define OTPC_LOCK_CUST_LOCK2_SHIFT (24U) +/*! CUST_LOCK2 - CUST Lock 2 */ +#define OTPC_LOCK_CUST_LOCK2(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK2_SHIFT)) & OTPC_LOCK_CUST_LOCK2_MASK) + +#define OTPC_LOCK_CUST_LOCK3_MASK (0x38000000U) +#define OTPC_LOCK_CUST_LOCK3_SHIFT (27U) +/*! CUST_LOCK3 - CUST Lock 3 */ +#define OTPC_LOCK_CUST_LOCK3(x) (((uint32_t)(((uint32_t)(x)) << OTPC_LOCK_CUST_LOCK3_SHIFT)) & OTPC_LOCK_CUST_LOCK3_MASK) +/*! @} */ + +/*! @name SECURE - Secure */ +/*! @{ */ + +#define OTPC_SECURE_DAT_MASK (0xFFFFFFFFU) +#define OTPC_SECURE_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_SECURE_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_DAT_SHIFT)) & OTPC_SECURE_DAT_MASK) +/*! @} */ + +/*! @name SECURE_INV - Inverted Secure */ +/*! @{ */ + +#define OTPC_SECURE_INV_DAT_MASK (0xFFFFFFFFU) +#define OTPC_SECURE_INV_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_SECURE_INV_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_SECURE_INV_DAT_SHIFT)) & OTPC_SECURE_INV_DAT_MASK) +/*! @} */ + +/*! @name DBG_KEY - Debug and Key */ +/*! @{ */ + +#define OTPC_DBG_KEY_DAT_MASK (0xFFFFFFFFU) +#define OTPC_DBG_KEY_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_DBG_KEY_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_DBG_KEY_DAT_SHIFT)) & OTPC_DBG_KEY_DAT_MASK) +/*! @} */ + +/*! @name MISC_CFG - MISC Config */ +/*! @{ */ + +#define OTPC_MISC_CFG_DAT_MASK (0xFFFFFFFFU) +#define OTPC_MISC_CFG_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_MISC_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_MISC_CFG_DAT_SHIFT)) & OTPC_MISC_CFG_DAT_MASK) +/*! @} */ + +/*! @name PHANTOM_CFG - PHANTOM Config */ +/*! @{ */ + +#define OTPC_PHANTOM_CFG_DAT_MASK (0xFFFFFFFFU) +#define OTPC_PHANTOM_CFG_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_PHANTOM_CFG_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_PHANTOM_CFG_DAT_SHIFT)) & OTPC_PHANTOM_CFG_DAT_MASK) +/*! @} */ + +/*! @name FLEX_CFG0 - Flexible Config 0 */ +/*! @{ */ + +#define OTPC_FLEX_CFG0_DAT_MASK (0xFFFFFFFFU) +#define OTPC_FLEX_CFG0_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_FLEX_CFG0_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG0_DAT_SHIFT)) & OTPC_FLEX_CFG0_DAT_MASK) +/*! @} */ + +/*! @name FLEX_CFG1 - Flexible Config 1 */ +/*! @{ */ + +#define OTPC_FLEX_CFG1_DAT_MASK (0xFFFFFFFFU) +#define OTPC_FLEX_CFG1_DAT_SHIFT (0U) +/*! DAT - Data */ +#define OTPC_FLEX_CFG1_DAT(x) (((uint32_t)(((uint32_t)(x)) << OTPC_FLEX_CFG1_DAT_SHIFT)) & OTPC_FLEX_CFG1_DAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OTPC_Register_Masks */ + + +/* OTPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x500C9000u) + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE_NS (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Peripheral OTPC0 base pointer */ + #define OTPC0_NS ((OTPC_Type *)OTPC0_BASE_NS) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS_NS { OTPC0_BASE_NS } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS_NS { OTPC0_NS } +#else + /** Peripheral OTPC0 base address */ + #define OTPC0_BASE (0x400C9000u) + /** Peripheral OTPC0 base pointer */ + #define OTPC0 ((OTPC_Type *)OTPC0_BASE) + /** Array initializer of OTPC peripheral base addresses */ + #define OTPC_BASE_ADDRS { OTPC0_BASE } + /** Array initializer of OTPC peripheral base pointers */ + #define OTPC_BASE_PTRS { OTPC0 } +#endif + +/*! + * @} + */ /* end of group OTPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PDM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer + * @{ + */ + +/** PDM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_1; /**< MICFIL Control 1, offset: 0x0 */ + __IO uint32_t CTRL_2; /**< MICFIL Control 2, offset: 0x4 */ + __IO uint32_t STAT; /**< MICFIL Status, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control, offset: 0x10 */ + __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status, offset: 0x14 */ + uint8_t RESERVED_1[12]; + __I uint32_t DATACH[4]; /**< MICFIL Output Result, array offset: 0x24, array step: 0x4 */ + uint8_t RESERVED_2[48]; + __I uint32_t DC_CTRL; /**< MICFIL DC Remover Control, offset: 0x64 */ + __IO uint32_t DC_OUT_CTRL; /**< MICFIL Output DC Remover Control, offset: 0x68 */ + uint8_t RESERVED_3[8]; + __IO uint32_t RANGE_CTRL; /**< MICFIL Range Control, offset: 0x74 */ + uint8_t RESERVED_4[4]; + __IO uint32_t RANGE_STAT; /**< MICFIL Range Status, offset: 0x7C */ + __IO uint32_t FSYNC_CTRL; /**< Frame Synchronization Control, offset: 0x80 */ + __I uint32_t VERID; /**< Version ID, offset: 0x84 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x88 */ +} PDM_Type; + +/* ---------------------------------------------------------------------------- + -- PDM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PDM_Register_Masks PDM Register Masks + * @{ + */ + +/*! @name CTRL_1 - MICFIL Control 1 */ +/*! @{ */ + +#define PDM_CTRL_1_CH0EN_MASK (0x1U) +#define PDM_CTRL_1_CH0EN_SHIFT (0U) +/*! CH0EN - Channel 0 Enable */ +#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) + +#define PDM_CTRL_1_CH1EN_MASK (0x2U) +#define PDM_CTRL_1_CH1EN_SHIFT (1U) +/*! CH1EN - Channel 1 Enable */ +#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) + +#define PDM_CTRL_1_CH2EN_MASK (0x4U) +#define PDM_CTRL_1_CH2EN_SHIFT (2U) +/*! CH2EN - Channel 2 Enable */ +#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) + +#define PDM_CTRL_1_CH3EN_MASK (0x8U) +#define PDM_CTRL_1_CH3EN_SHIFT (3U) +/*! CH3EN - Channel 3 Enable */ +#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) + +#define PDM_CTRL_1_FSYNCEN_MASK (0x10000U) +#define PDM_CTRL_1_FSYNCEN_SHIFT (16U) +/*! FSYNCEN - Frame Synchronization Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_FSYNCEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_FSYNCEN_SHIFT)) & PDM_CTRL_1_FSYNCEN_MASK) + +#define PDM_CTRL_1_DECFILS_MASK (0x100000U) +#define PDM_CTRL_1_DECFILS_SHIFT (20U) +/*! DECFILS - Decimation Filter Enable in Stop + * 0b0..Stops decimation filter + * 0b1..Keeps decimation filter running + */ +#define PDM_CTRL_1_DECFILS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DECFILS_SHIFT)) & PDM_CTRL_1_DECFILS_MASK) + +#define PDM_CTRL_1_ERREN_MASK (0x800000U) +#define PDM_CTRL_1_ERREN_SHIFT (23U) +/*! ERREN - Error Interruption Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) + +#define PDM_CTRL_1_DISEL_MASK (0x3000000U) +#define PDM_CTRL_1_DISEL_SHIFT (24U) +/*! DISEL - DMA Interrupt Selection + * 0b00..Disables DMA and interrupt requests + * 0b01..Enables DMA requests + * 0b10..Enables interrupt requests + * 0b11..Reserved + */ +#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) + +#define PDM_CTRL_1_DBGE_MASK (0x4000000U) +#define PDM_CTRL_1_DBGE_SHIFT (26U) +/*! DBGE - Module Enable in Debug + * 0b0..Disables after completing the current frame + * 0b1..Enables operation + */ +#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) + +#define PDM_CTRL_1_SRES_MASK (0x8000000U) +#define PDM_CTRL_1_SRES_SHIFT (27U) +/*! SRES - Software Reset + * 0b0..No action + * 0b1..Software reset + */ +#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) + +#define PDM_CTRL_1_DBG_MASK (0x10000000U) +#define PDM_CTRL_1_DBG_SHIFT (28U) +/*! DBG - Debug Mode + * 0b0..Normal + * 0b1..Debug + */ +#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) + +#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) +#define PDM_CTRL_1_PDMIEN_SHIFT (29U) +/*! PDMIEN - MICFIL Enable + * 0b0..Stops MICFIL operation + * 0b1..Starts MICFIL operation + */ +#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) + +#define PDM_CTRL_1_DOZEN_MASK (0x40000000U) +#define PDM_CTRL_1_DOZEN_SHIFT (30U) +/*! DOZEN - Stop Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) + +#define PDM_CTRL_1_MDIS_MASK (0x80000000U) +#define PDM_CTRL_1_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Normal mode + * 0b1..DLL mode + */ +#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK) +/*! @} */ + +/*! @name CTRL_2 - MICFIL Control 2 */ +/*! @{ */ + +#define PDM_CTRL_2_CLKDIV_MASK (0xFFU) +#define PDM_CTRL_2_CLKDIV_SHIFT (0U) +/*! CLKDIV - Clock Divider + * 0b00000000..Internal clock divider value = 0 + * 0b00000001..Internal clock divider value = 1 + * 0b00000010-0b11111110..... + * 0b11111111..Internal clock divider value = 255 + */ +#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) + +#define PDM_CTRL_2_CLKDIVDIS_MASK (0x8000U) +#define PDM_CTRL_2_CLKDIVDIS_SHIFT (15U) +/*! CLKDIVDIS - Clock Divider Disable + * 0b0..Enables + * 0b1..Disables + */ +#define PDM_CTRL_2_CLKDIVDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIVDIS_SHIFT)) & PDM_CTRL_2_CLKDIVDIS_MASK) + +#define PDM_CTRL_2_CICOSR_MASK (0xF0000U) +#define PDM_CTRL_2_CICOSR_SHIFT (16U) +/*! CICOSR - CIC Decimation Rate + * 0b0000..CIC oversampling rate = 0 + * 0b0001..CIC oversampling rate = 1 + * 0b0010-0b1110..... + * 0b1111..CIC oversampling rate = 15 + */ +#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) + +#define PDM_CTRL_2_QSEL_MASK (0xE000000U) +#define PDM_CTRL_2_QSEL_SHIFT (25U) +/*! QSEL - Quality Mode + * 0b001..High-Quality mode + * 0b000..Medium-Quality mode + * 0b111..Low-Quality mode + * 0b110..Very-Low-Quality 0 mode + * 0b101..Very-Low-Quality 1 mode + * 0b100..Very-Low-Quality 2 mode + */ +#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) +/*! @} */ + +/*! @name STAT - MICFIL Status */ +/*! @{ */ + +#define PDM_STAT_CH0F_MASK (0x1U) +#define PDM_STAT_CH0F_SHIFT (0U) +/*! CH0F - Channel 0 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) + +#define PDM_STAT_CH1F_MASK (0x2U) +#define PDM_STAT_CH1F_SHIFT (1U) +/*! CH1F - Channel 1 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) + +#define PDM_STAT_CH2F_MASK (0x4U) +#define PDM_STAT_CH2F_SHIFT (2U) +/*! CH2F - Channel 2 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) + +#define PDM_STAT_CH3F_MASK (0x8U) +#define PDM_STAT_CH3F_SHIFT (3U) +/*! CH3F - Channel 3 Output Data Flag + * 0b0..Not surpassed + * 0b1..Surpassed + */ +#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) + +#define PDM_STAT_BSY_FIL_MASK (0x80000000U) +#define PDM_STAT_BSY_FIL_SHIFT (31U) +/*! BSY_FIL - Busy Flag + * 0b1..MICFIL is running + * 0b0..MICFIL is stopped + */ +#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) +/*! @} */ + +/*! @name FIFO_CTRL - MICFIL FIFO Control */ +/*! @{ */ + +#define PDM_FIFO_CTRL_FIFOWMK_MASK (0xFU) +#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) +/*! FIFOWMK - FIFO Watermark Control */ +#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK) +/*! @} */ + +/*! @name FIFO_STAT - MICFIL FIFO Status */ +/*! @{ */ + +#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) +#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) +/*! FIFOOVF0 - FIFO Overflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) + +#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) +#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) +/*! FIFOOVF1 - FIFO Overflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) + +#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) +#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) +/*! FIFOOVF2 - FIFO Overflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) + +#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) +#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) +/*! FIFOOVF3 - FIFO Overflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO overflow + * 0b1..Exception by FIFO overflow + */ +#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) + +#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) +#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) +/*! FIFOUND0 - FIFO Underflow Exception Flag for Channel 0 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) + +#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) +#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) +/*! FIFOUND1 - FIFO Underflow Exception Flag for Channel 1 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) + +#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) +#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) +/*! FIFOUND2 - FIFO Underflow Exception Flag for Channel 2 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) + +#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) +#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) +/*! FIFOUND3 - FIFO Underflow Exception Flag for Channel 3 + * 0b0..No exception by FIFO underflow + * 0b1..Exception by FIFO underflow + */ +#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) +/*! @} */ + +/*! @name DATACHN_DATACH - MICFIL Output Result */ +/*! @{ */ + +#define PDM_DATACHN_DATACH_DATA_MASK (0xFFFFFFFFU) +#define PDM_DATACHN_DATACH_DATA_SHIFT (0U) +/*! DATA - Channel n Data */ +#define PDM_DATACHN_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACHN_DATACH_DATA_SHIFT)) & PDM_DATACHN_DATACH_DATA_MASK) +/*! @} */ + +/* The count of PDM_DATACHN_DATACH */ +#define PDM_DATACHN_DATACH_COUNT (4U) + +/*! @name DC_CTRL - MICFIL DC Remover Control */ +/*! @{ */ + +#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (PDM_CLK = 3.072 MHz) + * 0b01..13.3 Hz (PDM_CLK = 3.072 MHz) + * 0b10..40 Hz (PDM_CLK = 3.072 MHz) + */ +#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) +/*! @} */ + +/*! @name DC_OUT_CTRL - MICFIL Output DC Remover Control */ +/*! @{ */ + +#define PDM_DC_OUT_CTRL_DCCONFIG0_MASK (0x3U) +#define PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT (0U) +/*! DCCONFIG0 - Channel 0 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG0_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG1_MASK (0xCU) +#define PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT (2U) +/*! DCCONFIG1 - Channel 1 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG1_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG2_MASK (0x30U) +#define PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT (4U) +/*! DCCONFIG2 - Channel 2 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG2_MASK) + +#define PDM_DC_OUT_CTRL_DCCONFIG3_MASK (0xC0U) +#define PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT (6U) +/*! DCCONFIG3 - Channel 3 DC Remover Configuration + * 0b11..DC remover is bypassed + * 0b00..20 Hz (FS = 48 kHz) + * 0b01..13.3 Hz (FS = 48 kHz) + * 0b10..40 Hz (FS = 48 kHz) + */ +#define PDM_DC_OUT_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_OUT_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_OUT_CTRL_DCCONFIG3_MASK) +/*! @} */ + +/*! @name RANGE_CTRL - MICFIL Range Control */ +/*! @{ */ + +#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) +#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) +/*! RANGEADJ0 - Channel 0 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) +#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) +/*! RANGEADJ1 - Channel 1 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) +#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) +/*! RANGEADJ2 - Channel 2 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) + +#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) +#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) +/*! RANGEADJ3 - Channel 3 Range Adjustment */ +#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) +/*! @} */ + +/*! @name RANGE_STAT - MICFIL Range Status */ +/*! @{ */ + +#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) +#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) +/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) + +#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) +#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) +/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) + +#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) +#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) +/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) + +#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) +#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) +/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow + */ +#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) + +#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) +#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) +/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) + +#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) +#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) +/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) + +#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) +#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) +/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) + +#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) +#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) +/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow + */ +#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) +/*! @} */ + +/*! @name FSYNC_CTRL - Frame Synchronization Control */ +/*! @{ */ + +#define PDM_FSYNC_CTRL_FSYNCLEN_MASK (0xFFFFFFFFU) +#define PDM_FSYNC_CTRL_FSYNCLEN_SHIFT (0U) +/*! FSYNCLEN - Frame Synchronization Window Length */ +#define PDM_FSYNC_CTRL_FSYNCLEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_FSYNC_CTRL_FSYNCLEN_SHIFT)) & PDM_FSYNC_CTRL_FSYNCLEN_MASK) +/*! @} */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PDM_VERID_FEATURE_MASK (0xFFFFU) +#define PDM_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define PDM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_FEATURE_SHIFT)) & PDM_VERID_FEATURE_MASK) + +#define PDM_VERID_MINOR_MASK (0xFF0000U) +#define PDM_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PDM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MINOR_SHIFT)) & PDM_VERID_MINOR_MASK) + +#define PDM_VERID_MAJOR_MASK (0xFF000000U) +#define PDM_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PDM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VERID_MAJOR_SHIFT)) & PDM_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define PDM_PARAM_NPAIR_MASK (0xFU) +#define PDM_PARAM_NPAIR_SHIFT (0U) +/*! NPAIR - Number of Microphone Pairs + * 0b0000..None + * 0b0001..1 pair + * 0b0010..2 pairs + * 0b0011-0b1110..... + * 0b1111..15 pairs + */ +#define PDM_PARAM_NPAIR(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_NPAIR_SHIFT)) & PDM_PARAM_NPAIR_MASK) + +#define PDM_PARAM_FIFO_PTRWID_MASK (0xF0U) +#define PDM_PARAM_FIFO_PTRWID_SHIFT (4U) +/*! FIFO_PTRWID - FIFO Pointer Width + * 0b0000..0 bits + * 0b0001..1 bit + * 0b0010..2 bits + * 0b0011-0b1110..... + * 0b1111..15 bits + */ +#define PDM_PARAM_FIFO_PTRWID(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIFO_PTRWID_SHIFT)) & PDM_PARAM_FIFO_PTRWID_MASK) + +#define PDM_PARAM_FIL_OUT_WIDTH_24B_MASK (0x100U) +#define PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT (8U) +/*! FIL_OUT_WIDTH_24B - Filter Output Width + * 0b0..16 bits + * 0b1..24 bits + */ +#define PDM_PARAM_FIL_OUT_WIDTH_24B(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_FIL_OUT_WIDTH_24B_SHIFT)) & PDM_PARAM_FIL_OUT_WIDTH_24B_MASK) + +#define PDM_PARAM_LOW_POWER_MASK (0x200U) +#define PDM_PARAM_LOW_POWER_SHIFT (9U) +/*! LOW_POWER - Low-Power Decimation Filter + * 0b0..Disables + * 0b1..Enables + */ +#define PDM_PARAM_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_LOW_POWER_SHIFT)) & PDM_PARAM_LOW_POWER_MASK) + +#define PDM_PARAM_DC_BYPASS_MASK (0x400U) +#define PDM_PARAM_DC_BYPASS_SHIFT (10U) +/*! DC_BYPASS - Input DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_BYPASS_SHIFT)) & PDM_PARAM_DC_BYPASS_MASK) + +#define PDM_PARAM_DC_OUT_BYPASS_MASK (0x800U) +#define PDM_PARAM_DC_OUT_BYPASS_SHIFT (11U) +/*! DC_OUT_BYPASS - Output DC Remover Bypass + * 0b0..Active + * 0b1..Disabled + */ +#define PDM_PARAM_DC_OUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PDM_PARAM_DC_OUT_BYPASS_SHIFT)) & PDM_PARAM_DC_OUT_BYPASS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PDM_Register_Masks */ + + +/* PDM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PDM base address */ + #define PDM_BASE (0x5010C000u) + /** Peripheral PDM base address */ + #define PDM_BASE_NS (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Peripheral PDM base pointer */ + #define PDM_NS ((PDM_Type *)PDM_BASE_NS) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS_NS { PDM_BASE_NS } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS_NS { PDM_NS } +#else + /** Peripheral PDM base address */ + #define PDM_BASE (0x4010C000u) + /** Peripheral PDM base pointer */ + #define PDM ((PDM_Type *)PDM_BASE) + /** Array initializer of PDM peripheral base addresses */ + #define PDM_BASE_ADDRS { PDM_BASE } + /** Array initializer of PDM peripheral base pointers */ + #define PDM_BASE_PTRS { PDM } +#endif +/** Interrupt vectors for the PDM peripheral type */ +#define PDM_IRQS { PDM_EVENT_IRQn } + +/*! + * @} + */ /* end of group PDM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Enable, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin Interrupt Level or Rising-Edge Interrupt Set, offset: 0x8 */ + __IO uint32_t CIENR; /**< Pin Interrupt Level (Rising-Edge Interrupt) Clear, offset: 0xC */ + __IO uint32_t IENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Enable, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Set, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin Interrupt Active Level or Falling-Edge Interrupt Clear, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin Interrupt Rising Edge, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin Interrupt Falling Edge, offset: 0x20 */ + __IO uint32_t IST; /**< Pin Interrupt Status, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern-Match Interrupt Control, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern-Match Interrupt Bit-Slice Source, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern-Match Interrupt Bit Slice Configuration, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode */ +/*! @{ */ + +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Interrupt mode + * 0b00000000..In bit n configures the interrupt to be edge-sensitive + * 0b00000001..In bit n configures the interrupt to be level-sensitive + */ +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin Interrupt Level or Rising-Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables Interrupt + * 0b00000000..In bit n disables the corresponding interrupt + * 0b00000001..In bit n enables the corresponding interrupt + */ +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin Interrupt Level or Rising-Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Configures IENR + * 0b00000000..No operation for interrupt n + * 0b00000001..Enable rising edge or level interrupt for interrupt n + */ +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin Interrupt Level (Rising-Edge Interrupt) Clear */ +/*! @{ */ + +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Clear bits in IENR + * 0b00000000..No operation + * 0b00000001..Disable rising edge or level interrupt + */ +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin Interrupt Active Level or Falling-Edge Interrupt Enable */ +/*! @{ */ + +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables Interrupt + * 0b00000000..Disable (set active interrupt level LOW) + * 0b00000001..Enable (set active interrupt level HIGH) + */ +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Set */ +/*! @{ */ + +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF + * 0b00000000..Writes 0 to IENF. + * 0b00000001..Select HIGH-active interrupt or enable falling-edge interrupt + */ +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin Interrupt Active Level or Falling-Edge Interrupt Clear */ +/*! @{ */ + +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Writes 0 to IENF + * 0b00000000..No operation + * 0b00000001..LOW-active interrupt selected or falling-edge interrupt disabled + */ +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin Interrupt Rising Edge */ +/*! @{ */ + +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising-Edge Detect + * 0b00000000..Read 0- No rising edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation + * 0b00000001..Read 1- Rising edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear rising-edge detection for this pin + */ +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin Interrupt Falling Edge */ +/*! @{ */ + +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling-Edge Detect + * 0b00000000..Read 0- No falling edge (since Reset or you wrote a 1 to this field last time), Write 0- No operation + * 0b00000001..Read 1- Falling edge (since Reset or you wrote a 1 to this field last time), Write 1- Clear falling-edge detection for this bit + */ +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin Interrupt Status */ +/*! @{ */ + +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin Interrupt Status + * 0b00000000..Read 0- Interrupt is not requested, Write 0- No operation + * 0b00000001..Read 1- Interrupt is requested, Write 1 (edge-sensitive)- clear rising- and falling-edge detection + * for this pin, Write 1 (level-sensitive)- switch the active level for this pin in + */ +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern-Match Interrupt Control */ +/*! @{ */ + +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the pin interrupts are controlled by the pin interrupt function + * or by the pattern-match function. If this value is 0b, interrupts are driven in response to the + * standard pin interrupt function. If this value is 1b, interrupts are driven in response to + * pattern matches. + * 0b0..Pin interrupt + * 0b1..Pattern match + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output, when the specified + * Boolean expression evaluates to true. If this value is 0b, RXEV output to the CPU is disabled. If + * this value is 1b, RXEV output to the CPU is enabled. + * 0b0..Disabled + * 0b1..Enabled + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - Pattern Matches + * 0b00000001..The corresponding product term is matched by the current state of the appropriate inputs + */ +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern-Match Interrupt Bit-Slice Source */ +/*! @{ */ + +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0 (selects the pin identified in PINTSEL0) + * 0b001..Input 1 (selects the pin identified in PINTSEL1) + * 0b010..Input 2 (selects the pin identified in PINTSEL2) + * 0b011..Input 3 (selects the pin identified in PINTSEL3) + * 0b100..Input 4 (selects the pin identified in PINTSEL4) + * 0b101..Input 5 (selects the pin identified in PINTSEL5) + * 0b110..Input 6 (selects the pin identified in PINTSEL6) + * 0b111..Input 7 (selects the pin identified in PINTSEL7) + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern-Match Interrupt Bit Slice Configuration */ +/*! @{ */ + +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. Slice 0 is not an endpoint. Slice 0 is + * the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. Slice 1 is not an endpoint. Slice 1 is + * the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. Slice 2 is not an endpoint. Slice 2 is + * the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. Slice 3 is not an endpoint. Slice 3 is + * the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. Slice 4 is not an endpoint. Slice 4 is + * the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. Slice 5 is not an endpoint. Slice 5 is + * the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. Slice 6 is not an endpoint. Slice 6 is + * the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the + * minterm evaluates as true. + * 0b0..No effect + * 0b1..Endpoint + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Match Configuration + * 0b000..Constant HIGH + * 0b001..Sticky rising edge + * 0b010..Sticky falling edge + * 0b011..Sticky rising or falling edge + * 0b100..High level + * 0b101..Low level + * 0b110..Constant 0 + * 0b111..Event (Nonsticky rising or falling edge) + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x50004000u) + /** Peripheral PINT0 base address */ + #define PINT0_BASE_NS (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Peripheral PINT0 base pointer */ + #define PINT0_NS ((PINT_Type *)PINT0_BASE_NS) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS_NS { PINT0_BASE_NS } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS_NS { PINT0_NS } +#else + /** Peripheral PINT0 base address */ + #define PINT0_BASE (0x40004000u) + /** Peripheral PINT0 base pointer */ + #define PINT0 ((PINT_Type *)PINT0_BASE) + /** Array initializer of PINT peripheral base addresses */ + #define PINT_BASE_ADDRS { PINT0_BASE } + /** Array initializer of PINT peripheral base pointers */ + #define PINT_BASE_PTRS { PINT0 } +#endif +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PINT0_IRQn } +/* Backward compatibility */ +#define PINT PINT0 + + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PKC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Peripheral_Access_Layer PKC Peripheral Access Layer + * @{ + */ + +/** PKC - Register Layout Typedef */ +typedef struct { + __I uint32_t PKC_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t PKC_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t PKC_CFG; /**< Configuration register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t PKC_MODE1; /**< Mode register, parameter set 1, offset: 0x10 */ + __IO uint32_t PKC_XYPTR1; /**< X+Y pointer register, parameter set 1, offset: 0x14 */ + __IO uint32_t PKC_ZRPTR1; /**< Z+R pointer register, parameter set 1, offset: 0x18 */ + __IO uint32_t PKC_LEN1; /**< Length register, parameter set 1, offset: 0x1C */ + __IO uint32_t PKC_MODE2; /**< Mode register, parameter set 2, offset: 0x20 */ + __IO uint32_t PKC_XYPTR2; /**< X+Y pointer register, parameter set 2, offset: 0x24 */ + __IO uint32_t PKC_ZRPTR2; /**< Z+R pointer register, parameter set 2, offset: 0x28 */ + __IO uint32_t PKC_LEN2; /**< Length register, parameter set 2, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t PKC_UPTR; /**< Universal pointer FUP program, offset: 0x40 */ + __IO uint32_t PKC_UPTRT; /**< Universal pointer FUP table, offset: 0x44 */ + __IO uint32_t PKC_ULEN; /**< Universal pointer length, offset: 0x48 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PKC_MCDATA; /**< MC pattern data interface, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __I uint32_t PKC_VERSION; /**< PKC version register, offset: 0x60 */ + uint8_t RESERVED_4[3916]; + __O uint32_t PKC_SOFT_RST; /**< Software reset, offset: 0xFB0 */ + uint8_t RESERVED_5[12]; + __I uint32_t PKC_ACCESS_ERR; /**< Access Error, offset: 0xFC0 */ + __O uint32_t PKC_ACCESS_ERR_CLR; /**< Clear Access Error, offset: 0xFC4 */ + uint8_t RESERVED_6[16]; + __O uint32_t PKC_INT_CLR_ENABLE; /**< Interrupt enable clear, offset: 0xFD8 */ + __O uint32_t PKC_INT_SET_ENABLE; /**< Interrupt enable set, offset: 0xFDC */ + __I uint32_t PKC_INT_STATUS; /**< Interrupt status, offset: 0xFE0 */ + __I uint32_t PKC_INT_ENABLE; /**< Interrupt enable, offset: 0xFE4 */ + __O uint32_t PKC_INT_CLR_STATUS; /**< Interrupt status clear, offset: 0xFE8 */ + __O uint32_t PKC_INT_SET_STATUS; /**< Interrupt status set, offset: 0xFEC */ + uint8_t RESERVED_7[12]; + __I uint32_t PKC_MODULE_ID; /**< Module ID, offset: 0xFFC */ +} PKC_Type; + +/* ---------------------------------------------------------------------------- + -- PKC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PKC_Register_Masks PKC Register Masks + * @{ + */ + +/*! @name PKC_STATUS - Status Register */ +/*! @{ */ + +#define PKC_PKC_STATUS_ACTIV_MASK (0x1U) +#define PKC_PKC_STATUS_ACTIV_SHIFT (0U) +/*! ACTIV - PKC ACTIV */ +#define PKC_PKC_STATUS_ACTIV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ACTIV_SHIFT)) & PKC_PKC_STATUS_ACTIV_MASK) + +#define PKC_PKC_STATUS_CARRY_MASK (0x2U) +#define PKC_PKC_STATUS_CARRY_SHIFT (1U) +/*! CARRY - Carry overflow flag */ +#define PKC_PKC_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_CARRY_SHIFT)) & PKC_PKC_STATUS_CARRY_MASK) + +#define PKC_PKC_STATUS_ZERO_MASK (0x4U) +#define PKC_PKC_STATUS_ZERO_SHIFT (2U) +/*! ZERO - Zero result flag */ +#define PKC_PKC_STATUS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_ZERO_SHIFT)) & PKC_PKC_STATUS_ZERO_MASK) + +#define PKC_PKC_STATUS_GOANY_MASK (0x8U) +#define PKC_PKC_STATUS_GOANY_SHIFT (3U) +/*! GOANY - Combined GO status flag */ +#define PKC_PKC_STATUS_GOANY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_GOANY_SHIFT)) & PKC_PKC_STATUS_GOANY_MASK) + +#define PKC_PKC_STATUS_LOCKED_MASK (0x60U) +#define PKC_PKC_STATUS_LOCKED_SHIFT (5U) +/*! LOCKED - Parameter set locked */ +#define PKC_PKC_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_STATUS_LOCKED_SHIFT)) & PKC_PKC_STATUS_LOCKED_MASK) +/*! @} */ + +/*! @name PKC_CTRL - Control Register */ +/*! @{ */ + +#define PKC_PKC_CTRL_RESET_MASK (0x1U) +#define PKC_PKC_CTRL_RESET_SHIFT (0U) +/*! RESET - PKC reset control bit */ +#define PKC_PKC_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_RESET_SHIFT)) & PKC_PKC_CTRL_RESET_MASK) + +#define PKC_PKC_CTRL_STOP_MASK (0x2U) +#define PKC_PKC_CTRL_STOP_SHIFT (1U) +/*! STOP - Freeze PKC calculation */ +#define PKC_PKC_CTRL_STOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_STOP_SHIFT)) & PKC_PKC_CTRL_STOP_MASK) + +#define PKC_PKC_CTRL_GOD1_MASK (0x4U) +#define PKC_PKC_CTRL_GOD1_SHIFT (2U) +/*! GOD1 - Control bit to start direct operation using parameter set 1 */ +#define PKC_PKC_CTRL_GOD1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD1_SHIFT)) & PKC_PKC_CTRL_GOD1_MASK) + +#define PKC_PKC_CTRL_GOD2_MASK (0x8U) +#define PKC_PKC_CTRL_GOD2_SHIFT (3U) +/*! GOD2 - Control bit to start direct operation using parameter set 2 */ +#define PKC_PKC_CTRL_GOD2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOD2_SHIFT)) & PKC_PKC_CTRL_GOD2_MASK) + +#define PKC_PKC_CTRL_GOM1_MASK (0x10U) +#define PKC_PKC_CTRL_GOM1_SHIFT (4U) +/*! GOM1 - Control bit to start MC pattern using parameter set 1 */ +#define PKC_PKC_CTRL_GOM1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM1_SHIFT)) & PKC_PKC_CTRL_GOM1_MASK) + +#define PKC_PKC_CTRL_GOM2_MASK (0x20U) +#define PKC_PKC_CTRL_GOM2_SHIFT (5U) +/*! GOM2 - Control bit to start MC pattern using parameter set 2 */ +#define PKC_PKC_CTRL_GOM2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOM2_SHIFT)) & PKC_PKC_CTRL_GOM2_MASK) + +#define PKC_PKC_CTRL_GOU_MASK (0x40U) +#define PKC_PKC_CTRL_GOU_SHIFT (6U) +/*! GOU - Control bit to start pipe operation */ +#define PKC_PKC_CTRL_GOU(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GOU_SHIFT)) & PKC_PKC_CTRL_GOU_MASK) + +#define PKC_PKC_CTRL_GF2CONV_MASK (0x80U) +#define PKC_PKC_CTRL_GF2CONV_SHIFT (7U) +/*! GF2CONV - Convert to GF2 calculation modes */ +#define PKC_PKC_CTRL_GF2CONV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_GF2CONV_SHIFT)) & PKC_PKC_CTRL_GF2CONV_MASK) + +#define PKC_PKC_CTRL_CLRCACHE_MASK (0x100U) +#define PKC_PKC_CTRL_CLRCACHE_SHIFT (8U) +/*! CLRCACHE - Clear universal pointer cache */ +#define PKC_PKC_CTRL_CLRCACHE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CLRCACHE_SHIFT)) & PKC_PKC_CTRL_CLRCACHE_MASK) + +#define PKC_PKC_CTRL_CACHE_EN_MASK (0x200U) +#define PKC_PKC_CTRL_CACHE_EN_SHIFT (9U) +/*! CACHE_EN - Enable universal pointer cache */ +#define PKC_PKC_CTRL_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_CACHE_EN_SHIFT)) & PKC_PKC_CTRL_CACHE_EN_MASK) + +#define PKC_PKC_CTRL_REDMUL_MASK (0xC00U) +#define PKC_PKC_CTRL_REDMUL_SHIFT (10U) +/*! REDMUL - Reduced multiplier mode + * 0b00..full size mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b01..Reserved - Error Generated if selected + * 0b10..64-bit mode, 3 least significant bits of pointer and length are ignored, minimum supported length 0x0008 + * 0b11..Reserved - Error Generated if selected + */ +#define PKC_PKC_CTRL_REDMUL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CTRL_REDMUL_SHIFT)) & PKC_PKC_CTRL_REDMUL_MASK) +/*! @} */ + +/*! @name PKC_CFG - Configuration register */ +/*! @{ */ + +#define PKC_PKC_CFG_IDLEOP_MASK (0x1U) +#define PKC_PKC_CFG_IDLEOP_SHIFT (0U) +#define PKC_PKC_CFG_IDLEOP(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_IDLEOP_SHIFT)) & PKC_PKC_CFG_IDLEOP_MASK) + +#define PKC_PKC_CFG_RFU1_MASK (0x2U) +#define PKC_PKC_CFG_RFU1_SHIFT (1U) +#define PKC_PKC_CFG_RFU1(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU1_SHIFT)) & PKC_PKC_CFG_RFU1_MASK) + +#define PKC_PKC_CFG_RFU2_MASK (0x4U) +#define PKC_PKC_CFG_RFU2_SHIFT (2U) +#define PKC_PKC_CFG_RFU2(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RFU2_SHIFT)) & PKC_PKC_CFG_RFU2_MASK) + +#define PKC_PKC_CFG_CLKRND_MASK (0x8U) +#define PKC_PKC_CFG_CLKRND_SHIFT (3U) +#define PKC_PKC_CFG_CLKRND(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_CLKRND_SHIFT)) & PKC_PKC_CFG_CLKRND_MASK) + +#define PKC_PKC_CFG_REDMULNOISE_MASK (0x10U) +#define PKC_PKC_CFG_REDMULNOISE_SHIFT (4U) +#define PKC_PKC_CFG_REDMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_REDMULNOISE_SHIFT)) & PKC_PKC_CFG_REDMULNOISE_MASK) + +#define PKC_PKC_CFG_RNDDLY_MASK (0xE0U) +#define PKC_PKC_CFG_RNDDLY_SHIFT (5U) +#define PKC_PKC_CFG_RNDDLY(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_RNDDLY_SHIFT)) & PKC_PKC_CFG_RNDDLY_MASK) + +#define PKC_PKC_CFG_SBXNOISE_MASK (0x100U) +#define PKC_PKC_CFG_SBXNOISE_SHIFT (8U) +#define PKC_PKC_CFG_SBXNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_SBXNOISE_SHIFT)) & PKC_PKC_CFG_SBXNOISE_MASK) + +#define PKC_PKC_CFG_ALPNOISE_MASK (0x200U) +#define PKC_PKC_CFG_ALPNOISE_SHIFT (9U) +#define PKC_PKC_CFG_ALPNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_ALPNOISE_SHIFT)) & PKC_PKC_CFG_ALPNOISE_MASK) + +#define PKC_PKC_CFG_FMULNOISE_MASK (0x400U) +#define PKC_PKC_CFG_FMULNOISE_SHIFT (10U) +#define PKC_PKC_CFG_FMULNOISE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_CFG_FMULNOISE_SHIFT)) & PKC_PKC_CFG_FMULNOISE_MASK) +/*! @} */ + +/*! @name PKC_MODE1 - Mode register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_MODE1_MODE_MASK (0xFFU) +#define PKC_PKC_MODE1_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE1_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE1_MODE_SHIFT)) & PKC_PKC_MODE1_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR1 - X+Y pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_XYPTR1_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR1_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_XPTR_SHIFT)) & PKC_PKC_XYPTR1_XPTR_MASK) + +#define PKC_PKC_XYPTR1_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR1_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR1_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR1_YPTR_SHIFT)) & PKC_PKC_XYPTR1_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR1 - Z+R pointer register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR1_ZPTR_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR1_ZPTR_SHIFT (0U) +/*! ZPTR - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR1_ZPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_ZPTR_SHIFT)) & PKC_PKC_ZRPTR1_ZPTR_MASK) + +#define PKC_PKC_ZRPTR1_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR1_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR1_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR1_RPTR_SHIFT)) & PKC_PKC_ZRPTR1_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN1 - Length register, parameter set 1 */ +/*! @{ */ + +#define PKC_PKC_LEN1_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN1_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN1_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_LEN_SHIFT)) & PKC_PKC_LEN1_LEN_MASK) + +#define PKC_PKC_LEN1_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN1_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN1_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN1_MCLEN_SHIFT)) & PKC_PKC_LEN1_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_MODE2 - Mode register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_MODE2_MODE_MASK (0xFFU) +#define PKC_PKC_MODE2_MODE_SHIFT (0U) +/*! MODE - Calculation Mode / MC Start address */ +#define PKC_PKC_MODE2_MODE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODE2_MODE_SHIFT)) & PKC_PKC_MODE2_MODE_MASK) +/*! @} */ + +/*! @name PKC_XYPTR2 - X+Y pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_XYPTR2_XPTR_MASK (0xFFFFU) +#define PKC_PKC_XYPTR2_XPTR_SHIFT (0U) +/*! XPTR - Start address of X operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_XPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_XPTR_SHIFT)) & PKC_PKC_XYPTR2_XPTR_MASK) + +#define PKC_PKC_XYPTR2_YPTR_MASK (0xFFFF0000U) +#define PKC_PKC_XYPTR2_YPTR_SHIFT (16U) +/*! YPTR - Start address of Y operand in PKCRAM with byte granularity */ +#define PKC_PKC_XYPTR2_YPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_XYPTR2_YPTR_SHIFT)) & PKC_PKC_XYPTR2_YPTR_MASK) +/*! @} */ + +/*! @name PKC_ZRPTR2 - Z+R pointer register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_ZRPTR2_ZPT_MASK (0xFFFFU) +#define PKC_PKC_ZRPTR2_ZPT_SHIFT (0U) +/*! ZPT - Start address of Z operand in PKCRAM with byte granularity or constant for calculation modes using CONST */ +#define PKC_PKC_ZRPTR2_ZPT(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_ZPT_SHIFT)) & PKC_PKC_ZRPTR2_ZPT_MASK) + +#define PKC_PKC_ZRPTR2_RPTR_MASK (0xFFFF0000U) +#define PKC_PKC_ZRPTR2_RPTR_SHIFT (16U) +/*! RPTR - Start address of R result in PKCRAM with byte granularity */ +#define PKC_PKC_ZRPTR2_RPTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ZRPTR2_RPTR_SHIFT)) & PKC_PKC_ZRPTR2_RPTR_MASK) +/*! @} */ + +/*! @name PKC_LEN2 - Length register, parameter set 2 */ +/*! @{ */ + +#define PKC_PKC_LEN2_LEN_MASK (0xFFFFU) +#define PKC_PKC_LEN2_LEN_SHIFT (0U) +/*! LEN - Operand length */ +#define PKC_PKC_LEN2_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_LEN_SHIFT)) & PKC_PKC_LEN2_LEN_MASK) + +#define PKC_PKC_LEN2_MCLEN_MASK (0xFFFF0000U) +#define PKC_PKC_LEN2_MCLEN_SHIFT (16U) +/*! MCLEN - Loop counter for microcode pattern */ +#define PKC_PKC_LEN2_MCLEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_LEN2_MCLEN_SHIFT)) & PKC_PKC_LEN2_MCLEN_MASK) +/*! @} */ + +/*! @name PKC_UPTR - Universal pointer FUP program */ +/*! @{ */ + +#define PKC_PKC_UPTR_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTR_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP program */ +#define PKC_PKC_UPTR_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTR_PTR_SHIFT)) & PKC_PKC_UPTR_PTR_MASK) +/*! @} */ + +/*! @name PKC_UPTRT - Universal pointer FUP table */ +/*! @{ */ + +#define PKC_PKC_UPTRT_PTR_MASK (0xFFFFFFFFU) +#define PKC_PKC_UPTRT_PTR_SHIFT (0U) +/*! PTR - Pointer to start address of PKC FUP table */ +#define PKC_PKC_UPTRT_PTR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_UPTRT_PTR_SHIFT)) & PKC_PKC_UPTRT_PTR_MASK) +/*! @} */ + +/*! @name PKC_ULEN - Universal pointer length */ +/*! @{ */ + +#define PKC_PKC_ULEN_LEN_MASK (0xFFU) +#define PKC_PKC_ULEN_LEN_SHIFT (0U) +/*! LEN - Length of universal pointer calculation */ +#define PKC_PKC_ULEN_LEN(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ULEN_LEN_SHIFT)) & PKC_PKC_ULEN_LEN_MASK) +/*! @} */ + +/*! @name PKC_MCDATA - MC pattern data interface */ +/*! @{ */ + +#define PKC_PKC_MCDATA_MCDATA_MASK (0xFFFFFFFFU) +#define PKC_PKC_MCDATA_MCDATA_SHIFT (0U) +/*! MCDATA - Microcode read/write data */ +#define PKC_PKC_MCDATA_MCDATA(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MCDATA_MCDATA_SHIFT)) & PKC_PKC_MCDATA_MCDATA_MASK) +/*! @} */ + +/*! @name PKC_VERSION - PKC version register */ +/*! @{ */ + +#define PKC_PKC_VERSION_MULSIZE_MASK (0x3U) +#define PKC_PKC_VERSION_MULSIZE_SHIFT (0U) +/*! MULSIZE + * 0b01..32-bit multiplier + * 0b10..64-bit multiplier + * 0b11..128-bit multiplier + * 0b10..128-bit multiplier + * 0b01..64-bit multiplier + */ +#define PKC_PKC_VERSION_MULSIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MULSIZE_SHIFT)) & PKC_PKC_VERSION_MULSIZE_MASK) + +#define PKC_PKC_VERSION_MCAVAIL_MASK (0x4U) +#define PKC_PKC_VERSION_MCAVAIL_SHIFT (2U) +#define PKC_PKC_VERSION_MCAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCAVAIL_SHIFT)) & PKC_PKC_VERSION_MCAVAIL_MASK) + +#define PKC_PKC_VERSION_UPAVAIL_MASK (0x8U) +#define PKC_PKC_VERSION_UPAVAIL_SHIFT (3U) +#define PKC_PKC_VERSION_UPAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPAVAIL_SHIFT)) & PKC_PKC_VERSION_UPAVAIL_MASK) + +#define PKC_PKC_VERSION_UPCACHEAVAIL_MASK (0x10U) +#define PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT (4U) +#define PKC_PKC_VERSION_UPCACHEAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_UPCACHEAVAIL_SHIFT)) & PKC_PKC_VERSION_UPCACHEAVAIL_MASK) + +#define PKC_PKC_VERSION_GF2AVAIL_MASK (0x20U) +#define PKC_PKC_VERSION_GF2AVAIL_SHIFT (5U) +#define PKC_PKC_VERSION_GF2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_GF2AVAIL_SHIFT)) & PKC_PKC_VERSION_GF2AVAIL_MASK) + +#define PKC_PKC_VERSION_PARAMNUM_MASK (0xC0U) +#define PKC_PKC_VERSION_PARAMNUM_SHIFT (6U) +#define PKC_PKC_VERSION_PARAMNUM(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_PARAMNUM_SHIFT)) & PKC_PKC_VERSION_PARAMNUM_MASK) + +#define PKC_PKC_VERSION_SBX0AVAIL_MASK (0x100U) +#define PKC_PKC_VERSION_SBX0AVAIL_SHIFT (8U) +#define PKC_PKC_VERSION_SBX0AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX0AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX0AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX1AVAIL_MASK (0x200U) +#define PKC_PKC_VERSION_SBX1AVAIL_SHIFT (9U) +#define PKC_PKC_VERSION_SBX1AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX1AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX1AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX2AVAIL_MASK (0x400U) +#define PKC_PKC_VERSION_SBX2AVAIL_SHIFT (10U) +#define PKC_PKC_VERSION_SBX2AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX2AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX2AVAIL_MASK) + +#define PKC_PKC_VERSION_SBX3AVAIL_MASK (0x800U) +#define PKC_PKC_VERSION_SBX3AVAIL_SHIFT (11U) +#define PKC_PKC_VERSION_SBX3AVAIL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_SBX3AVAIL_SHIFT)) & PKC_PKC_VERSION_SBX3AVAIL_MASK) + +#define PKC_PKC_VERSION_MCRECONF_SIZE_MASK (0xFF000U) +#define PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT (12U) +#define PKC_PKC_VERSION_MCRECONF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_VERSION_MCRECONF_SIZE_SHIFT)) & PKC_PKC_VERSION_MCRECONF_SIZE_MASK) +/*! @} */ + +/*! @name PKC_SOFT_RST - Software reset */ +/*! @{ */ + +#define PKC_PKC_SOFT_RST_SOFT_RST_MASK (0x1U) +#define PKC_PKC_SOFT_RST_SOFT_RST_SHIFT (0U) +#define PKC_PKC_SOFT_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_SOFT_RST_SOFT_RST_SHIFT)) & PKC_PKC_SOFT_RST_SOFT_RST_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR - Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT (0U) +/*! APB_NOTAV - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_NOTAV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_NOTAV_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_NOTAV_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK (0x2U) +#define PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT (1U) +/*! APB_WRGMD - APB Error */ +#define PKC_PKC_ACCESS_ERR_APB_WRGMD(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_WRGMD_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_WRGMD_MASK) + +#define PKC_PKC_ACCESS_ERR_APB_MASTER_MASK (0xF0U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT (4U) +#define PKC_PKC_ACCESS_ERR_APB_MASTER(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_APB_MASTER_SHIFT)) & PKC_PKC_ACCESS_ERR_APB_MASTER_MASK) + +#define PKC_PKC_ACCESS_ERR_AHB_MASK (0x400U) +#define PKC_PKC_ACCESS_ERR_AHB_SHIFT (10U) +/*! AHB - AHB Error */ +#define PKC_PKC_ACCESS_ERR_AHB(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_AHB_SHIFT)) & PKC_PKC_ACCESS_ERR_AHB_MASK) + +#define PKC_PKC_ACCESS_ERR_PKCC_MASK (0x10000U) +#define PKC_PKC_ACCESS_ERR_PKCC_SHIFT (16U) +#define PKC_PKC_ACCESS_ERR_PKCC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_PKCC_SHIFT)) & PKC_PKC_ACCESS_ERR_PKCC_MASK) + +#define PKC_PKC_ACCESS_ERR_FDET_MASK (0x20000U) +#define PKC_PKC_ACCESS_ERR_FDET_SHIFT (17U) +#define PKC_PKC_ACCESS_ERR_FDET(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_FDET_SHIFT)) & PKC_PKC_ACCESS_ERR_FDET_MASK) + +#define PKC_PKC_ACCESS_ERR_CTRL_MASK (0x40000U) +#define PKC_PKC_ACCESS_ERR_CTRL_SHIFT (18U) +#define PKC_PKC_ACCESS_ERR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CTRL_SHIFT)) & PKC_PKC_ACCESS_ERR_CTRL_MASK) + +#define PKC_PKC_ACCESS_ERR_UCRC_MASK (0x80000U) +#define PKC_PKC_ACCESS_ERR_UCRC_SHIFT (19U) +#define PKC_PKC_ACCESS_ERR_UCRC(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_UCRC_SHIFT)) & PKC_PKC_ACCESS_ERR_UCRC_MASK) +/*! @} */ + +/*! @name PKC_ACCESS_ERR_CLR - Clear Access Error */ +/*! @{ */ + +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK (0x1U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT (0U) +#define PKC_PKC_ACCESS_ERR_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_SHIFT)) & PKC_PKC_ACCESS_ERR_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_ENABLE - Interrupt enable clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_CLR_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_ENABLE - Interrupt enable set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_SET_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_STATUS - Interrupt status */ +/*! @{ */ + +#define PKC_PKC_INT_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_STATUS_INT_PDONE_SHIFT (0U) +/*! INT_PDONE - End-of-computation status flag */ +#define PKC_PKC_INT_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_ENABLE - Interrupt enable */ +/*! @{ */ + +#define PKC_PKC_INT_ENABLE_EN_PDONE_MASK (0x1U) +#define PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT (0U) +/*! EN_PDONE - PDONE interrupt enable flag */ +#define PKC_PKC_INT_ENABLE_EN_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_ENABLE_EN_PDONE_SHIFT)) & PKC_PKC_INT_ENABLE_EN_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_CLR_STATUS - Interrupt status clear */ +/*! @{ */ + +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_CLR_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_CLR_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_CLR_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_INT_SET_STATUS - Interrupt status set */ +/*! @{ */ + +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK (0x1U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT (0U) +#define PKC_PKC_INT_SET_STATUS_INT_PDONE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_INT_SET_STATUS_INT_PDONE_SHIFT)) & PKC_PKC_INT_SET_STATUS_INT_PDONE_MASK) +/*! @} */ + +/*! @name PKC_MODULE_ID - Module ID */ +/*! @{ */ + +#define PKC_PKC_MODULE_ID_SIZE_MASK (0xFFU) +#define PKC_PKC_MODULE_ID_SIZE_SHIFT (0U) +#define PKC_PKC_MODULE_ID_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_SIZE_SHIFT)) & PKC_PKC_MODULE_ID_SIZE_MASK) + +#define PKC_PKC_MODULE_ID_MINOR_REV_MASK (0xF00U) +#define PKC_PKC_MODULE_ID_MINOR_REV_SHIFT (8U) +#define PKC_PKC_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MINOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MINOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_MAJOR_REV_MASK (0xF000U) +#define PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT (12U) +#define PKC_PKC_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_MAJOR_REV_SHIFT)) & PKC_PKC_MODULE_ID_MAJOR_REV_MASK) + +#define PKC_PKC_MODULE_ID_ID_MASK (0xFFFF0000U) +#define PKC_PKC_MODULE_ID_ID_SHIFT (16U) +#define PKC_PKC_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << PKC_PKC_MODULE_ID_ID_SHIFT)) & PKC_PKC_MODULE_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PKC_Register_Masks */ + + +/* PKC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x5002B000u) + /** Peripheral PKC0 base address */ + #define PKC0_BASE_NS (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Peripheral PKC0 base pointer */ + #define PKC0_NS ((PKC_Type *)PKC0_BASE_NS) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS_NS { PKC0_BASE_NS } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS_NS { PKC0_NS } +#else + /** Peripheral PKC0 base address */ + #define PKC0_BASE (0x4002B000u) + /** Peripheral PKC0 base pointer */ + #define PKC0 ((PKC_Type *)PKC0_BASE) + /** Array initializer of PKC peripheral base addresses */ + #define PKC_BASE_ADDRS { PKC0_BASE } + /** Array initializer of PKC peripheral base pointers */ + #define PKC_BASE_PTRS { PKC0 } +#endif + +/*! + * @} + */ /* end of group PKC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __O uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */ + __O uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */ + uint8_t RESERVED_2[28]; + __I uint32_t EDFR; /**< EFT Detect Flag, offset: 0x40 */ + __IO uint32_t EDIER; /**< EFT Detect Interrupt Enable, offset: 0x44 */ + __IO uint32_t EDCR; /**< EFT Detect Clear, offset: 0x48 */ + uint8_t RESERVED_3[20]; + __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ + __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT2, PORT3 (missing on PORT4, PORT5) */ + uint8_t RESERVED_4[24]; + __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4, irregular array, not all indices are valid */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PORT_VERID_FEATURE_MASK (0xFFFFU) +#define PORT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + */ +#define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK) + +#define PORT_VERID_MINOR_MASK (0xFF0000U) +#define PORT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK) + +#define PORT_VERID_MAJOR_MASK (0xFF000000U) +#define PORT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name GPCLR - Global Pin Control Low */ +/*! @{ */ + +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) + +#define PORT_GPCLR_GPWE0_MASK (0x10000U) +#define PORT_GPCLR_GPWE0_SHIFT (16U) +/*! GPWE0 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK) + +#define PORT_GPCLR_GPWE1_MASK (0x20000U) +#define PORT_GPCLR_GPWE1_SHIFT (17U) +/*! GPWE1 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK) + +#define PORT_GPCLR_GPWE2_MASK (0x40000U) +#define PORT_GPCLR_GPWE2_SHIFT (18U) +/*! GPWE2 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK) + +#define PORT_GPCLR_GPWE3_MASK (0x80000U) +#define PORT_GPCLR_GPWE3_SHIFT (19U) +/*! GPWE3 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK) + +#define PORT_GPCLR_GPWE4_MASK (0x100000U) +#define PORT_GPCLR_GPWE4_SHIFT (20U) +/*! GPWE4 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK) + +#define PORT_GPCLR_GPWE5_MASK (0x200000U) +#define PORT_GPCLR_GPWE5_SHIFT (21U) +/*! GPWE5 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK) + +#define PORT_GPCLR_GPWE6_MASK (0x400000U) +#define PORT_GPCLR_GPWE6_SHIFT (22U) +/*! GPWE6 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK) + +#define PORT_GPCLR_GPWE7_MASK (0x800000U) +#define PORT_GPCLR_GPWE7_SHIFT (23U) +/*! GPWE7 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK) + +#define PORT_GPCLR_GPWE8_MASK (0x1000000U) +#define PORT_GPCLR_GPWE8_SHIFT (24U) +/*! GPWE8 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK) + +#define PORT_GPCLR_GPWE9_MASK (0x2000000U) +#define PORT_GPCLR_GPWE9_SHIFT (25U) +/*! GPWE9 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK) + +#define PORT_GPCLR_GPWE10_MASK (0x4000000U) +#define PORT_GPCLR_GPWE10_SHIFT (26U) +/*! GPWE10 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK) + +#define PORT_GPCLR_GPWE11_MASK (0x8000000U) +#define PORT_GPCLR_GPWE11_SHIFT (27U) +/*! GPWE11 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK) + +#define PORT_GPCLR_GPWE12_MASK (0x10000000U) +#define PORT_GPCLR_GPWE12_SHIFT (28U) +/*! GPWE12 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK) + +#define PORT_GPCLR_GPWE13_MASK (0x20000000U) +#define PORT_GPCLR_GPWE13_SHIFT (29U) +/*! GPWE13 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK) + +#define PORT_GPCLR_GPWE14_MASK (0x40000000U) +#define PORT_GPCLR_GPWE14_SHIFT (30U) +/*! GPWE14 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK) + +#define PORT_GPCLR_GPWE15_MASK (0x80000000U) +#define PORT_GPCLR_GPWE15_SHIFT (31U) +/*! GPWE15 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK) +/*! @} */ + +/*! @name GPCHR - Global Pin Control High */ +/*! @{ */ + +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) + +#define PORT_GPCHR_GPWE16_MASK (0x10000U) +#define PORT_GPCHR_GPWE16_SHIFT (16U) +/*! GPWE16 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK) + +#define PORT_GPCHR_GPWE17_MASK (0x20000U) +#define PORT_GPCHR_GPWE17_SHIFT (17U) +/*! GPWE17 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK) + +#define PORT_GPCHR_GPWE18_MASK (0x40000U) +#define PORT_GPCHR_GPWE18_SHIFT (18U) +/*! GPWE18 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK) + +#define PORT_GPCHR_GPWE19_MASK (0x80000U) +#define PORT_GPCHR_GPWE19_SHIFT (19U) +/*! GPWE19 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK) + +#define PORT_GPCHR_GPWE20_MASK (0x100000U) +#define PORT_GPCHR_GPWE20_SHIFT (20U) +/*! GPWE20 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK) + +#define PORT_GPCHR_GPWE21_MASK (0x200000U) +#define PORT_GPCHR_GPWE21_SHIFT (21U) +/*! GPWE21 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK) + +#define PORT_GPCHR_GPWE22_MASK (0x400000U) +#define PORT_GPCHR_GPWE22_SHIFT (22U) +/*! GPWE22 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK) + +#define PORT_GPCHR_GPWE23_MASK (0x800000U) +#define PORT_GPCHR_GPWE23_SHIFT (23U) +/*! GPWE23 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK) + +#define PORT_GPCHR_GPWE24_MASK (0x1000000U) +#define PORT_GPCHR_GPWE24_SHIFT (24U) +/*! GPWE24 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK) + +#define PORT_GPCHR_GPWE25_MASK (0x2000000U) +#define PORT_GPCHR_GPWE25_SHIFT (25U) +/*! GPWE25 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK) + +#define PORT_GPCHR_GPWE26_MASK (0x4000000U) +#define PORT_GPCHR_GPWE26_SHIFT (26U) +/*! GPWE26 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK) + +#define PORT_GPCHR_GPWE27_MASK (0x8000000U) +#define PORT_GPCHR_GPWE27_SHIFT (27U) +/*! GPWE27 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK) + +#define PORT_GPCHR_GPWE28_MASK (0x10000000U) +#define PORT_GPCHR_GPWE28_SHIFT (28U) +/*! GPWE28 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK) + +#define PORT_GPCHR_GPWE29_MASK (0x20000000U) +#define PORT_GPCHR_GPWE29_SHIFT (29U) +/*! GPWE29 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK) + +#define PORT_GPCHR_GPWE30_MASK (0x40000000U) +#define PORT_GPCHR_GPWE30_SHIFT (30U) +/*! GPWE30 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK) + +#define PORT_GPCHR_GPWE31_MASK (0x80000000U) +#define PORT_GPCHR_GPWE31_SHIFT (31U) +/*! GPWE31 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK) +/*! @} */ + +/*! @name CONFIG - Configuration */ +/*! @{ */ + +#define PORT_CONFIG_RANGE_MASK (0x1U) +#define PORT_CONFIG_RANGE_SHIFT (0U) +/*! RANGE - Port Voltage Range + * 0b0..1.71 V-3.6 V + * 0b1..2.70 V-3.6 V + */ +#define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK) +/*! @} */ + +/*! @name EDFR - EFT Detect Flag */ +/*! @{ */ + +#define PORT_EDFR_EDF0_MASK (0x1U) +#define PORT_EDFR_EDF0_SHIFT (0U) +/*! EDF0 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF0_SHIFT)) & PORT_EDFR_EDF0_MASK) + +#define PORT_EDFR_EDF1_MASK (0x2U) +#define PORT_EDFR_EDF1_SHIFT (1U) +/*! EDF1 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF1_SHIFT)) & PORT_EDFR_EDF1_MASK) + +#define PORT_EDFR_EDF2_MASK (0x4U) +#define PORT_EDFR_EDF2_SHIFT (2U) +/*! EDF2 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF2_SHIFT)) & PORT_EDFR_EDF2_MASK) + +#define PORT_EDFR_EDF3_MASK (0x8U) +#define PORT_EDFR_EDF3_SHIFT (3U) +/*! EDF3 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF3_SHIFT)) & PORT_EDFR_EDF3_MASK) + +#define PORT_EDFR_EDF4_MASK (0x10U) +#define PORT_EDFR_EDF4_SHIFT (4U) +/*! EDF4 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF4_SHIFT)) & PORT_EDFR_EDF4_MASK) + +#define PORT_EDFR_EDF5_MASK (0x20U) +#define PORT_EDFR_EDF5_SHIFT (5U) +/*! EDF5 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF5_SHIFT)) & PORT_EDFR_EDF5_MASK) + +#define PORT_EDFR_EDF6_MASK (0x40U) +#define PORT_EDFR_EDF6_SHIFT (6U) +/*! EDF6 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF6_SHIFT)) & PORT_EDFR_EDF6_MASK) + +#define PORT_EDFR_EDF7_MASK (0x80U) +#define PORT_EDFR_EDF7_SHIFT (7U) +/*! EDF7 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF7_SHIFT)) & PORT_EDFR_EDF7_MASK) + +#define PORT_EDFR_EDF8_MASK (0x100U) +#define PORT_EDFR_EDF8_SHIFT (8U) +/*! EDF8 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF8_SHIFT)) & PORT_EDFR_EDF8_MASK) + +#define PORT_EDFR_EDF9_MASK (0x200U) +#define PORT_EDFR_EDF9_SHIFT (9U) +/*! EDF9 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF9_SHIFT)) & PORT_EDFR_EDF9_MASK) + +#define PORT_EDFR_EDF10_MASK (0x400U) +#define PORT_EDFR_EDF10_SHIFT (10U) +/*! EDF10 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF10_SHIFT)) & PORT_EDFR_EDF10_MASK) + +#define PORT_EDFR_EDF11_MASK (0x800U) +#define PORT_EDFR_EDF11_SHIFT (11U) +/*! EDF11 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF11_SHIFT)) & PORT_EDFR_EDF11_MASK) + +#define PORT_EDFR_EDF12_MASK (0x1000U) +#define PORT_EDFR_EDF12_SHIFT (12U) +/*! EDF12 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF12_SHIFT)) & PORT_EDFR_EDF12_MASK) + +#define PORT_EDFR_EDF13_MASK (0x2000U) +#define PORT_EDFR_EDF13_SHIFT (13U) +/*! EDF13 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF13_SHIFT)) & PORT_EDFR_EDF13_MASK) + +#define PORT_EDFR_EDF14_MASK (0x4000U) +#define PORT_EDFR_EDF14_SHIFT (14U) +/*! EDF14 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF14_SHIFT)) & PORT_EDFR_EDF14_MASK) + +#define PORT_EDFR_EDF15_MASK (0x8000U) +#define PORT_EDFR_EDF15_SHIFT (15U) +/*! EDF15 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF15_SHIFT)) & PORT_EDFR_EDF15_MASK) + +#define PORT_EDFR_EDF16_MASK (0x10000U) +#define PORT_EDFR_EDF16_SHIFT (16U) +/*! EDF16 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF16_SHIFT)) & PORT_EDFR_EDF16_MASK) + +#define PORT_EDFR_EDF17_MASK (0x20000U) +#define PORT_EDFR_EDF17_SHIFT (17U) +/*! EDF17 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF17_SHIFT)) & PORT_EDFR_EDF17_MASK) + +#define PORT_EDFR_EDF18_MASK (0x40000U) +#define PORT_EDFR_EDF18_SHIFT (18U) +/*! EDF18 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF18_SHIFT)) & PORT_EDFR_EDF18_MASK) + +#define PORT_EDFR_EDF19_MASK (0x80000U) +#define PORT_EDFR_EDF19_SHIFT (19U) +/*! EDF19 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF19_SHIFT)) & PORT_EDFR_EDF19_MASK) + +#define PORT_EDFR_EDF20_MASK (0x100000U) +#define PORT_EDFR_EDF20_SHIFT (20U) +/*! EDF20 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF20_SHIFT)) & PORT_EDFR_EDF20_MASK) + +#define PORT_EDFR_EDF21_MASK (0x200000U) +#define PORT_EDFR_EDF21_SHIFT (21U) +/*! EDF21 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF21_SHIFT)) & PORT_EDFR_EDF21_MASK) + +#define PORT_EDFR_EDF22_MASK (0x400000U) +#define PORT_EDFR_EDF22_SHIFT (22U) +/*! EDF22 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF22_SHIFT)) & PORT_EDFR_EDF22_MASK) + +#define PORT_EDFR_EDF23_MASK (0x800000U) +#define PORT_EDFR_EDF23_SHIFT (23U) +/*! EDF23 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF23_SHIFT)) & PORT_EDFR_EDF23_MASK) + +#define PORT_EDFR_EDF24_MASK (0x1000000U) +#define PORT_EDFR_EDF24_SHIFT (24U) +/*! EDF24 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF24_SHIFT)) & PORT_EDFR_EDF24_MASK) + +#define PORT_EDFR_EDF25_MASK (0x2000000U) +#define PORT_EDFR_EDF25_SHIFT (25U) +/*! EDF25 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF25_SHIFT)) & PORT_EDFR_EDF25_MASK) + +#define PORT_EDFR_EDF26_MASK (0x4000000U) +#define PORT_EDFR_EDF26_SHIFT (26U) +/*! EDF26 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF26_SHIFT)) & PORT_EDFR_EDF26_MASK) + +#define PORT_EDFR_EDF27_MASK (0x8000000U) +#define PORT_EDFR_EDF27_SHIFT (27U) +/*! EDF27 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF27_SHIFT)) & PORT_EDFR_EDF27_MASK) + +#define PORT_EDFR_EDF28_MASK (0x10000000U) +#define PORT_EDFR_EDF28_SHIFT (28U) +/*! EDF28 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF28_SHIFT)) & PORT_EDFR_EDF28_MASK) + +#define PORT_EDFR_EDF29_MASK (0x20000000U) +#define PORT_EDFR_EDF29_SHIFT (29U) +/*! EDF29 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF29_SHIFT)) & PORT_EDFR_EDF29_MASK) + +#define PORT_EDFR_EDF30_MASK (0x40000000U) +#define PORT_EDFR_EDF30_SHIFT (30U) +/*! EDF30 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF30_SHIFT)) & PORT_EDFR_EDF30_MASK) + +#define PORT_EDFR_EDF31_MASK (0x80000000U) +#define PORT_EDFR_EDF31_SHIFT (31U) +/*! EDF31 - EFT Detect Flag + * 0b0..No EFT event detected + * 0b1..High or/and low EFT event detected + */ +#define PORT_EDFR_EDF31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDFR_EDF31_SHIFT)) & PORT_EDFR_EDF31_MASK) +/*! @} */ + +/*! @name EDIER - EFT Detect Interrupt Enable */ +/*! @{ */ + +#define PORT_EDIER_EDIE0_MASK (0x1U) +#define PORT_EDIER_EDIE0_SHIFT (0U) +/*! EDIE0 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE0_SHIFT)) & PORT_EDIER_EDIE0_MASK) + +#define PORT_EDIER_EDIE1_MASK (0x2U) +#define PORT_EDIER_EDIE1_SHIFT (1U) +/*! EDIE1 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE1_SHIFT)) & PORT_EDIER_EDIE1_MASK) + +#define PORT_EDIER_EDIE2_MASK (0x4U) +#define PORT_EDIER_EDIE2_SHIFT (2U) +/*! EDIE2 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE2_SHIFT)) & PORT_EDIER_EDIE2_MASK) + +#define PORT_EDIER_EDIE3_MASK (0x8U) +#define PORT_EDIER_EDIE3_SHIFT (3U) +/*! EDIE3 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE3_SHIFT)) & PORT_EDIER_EDIE3_MASK) + +#define PORT_EDIER_EDIE4_MASK (0x10U) +#define PORT_EDIER_EDIE4_SHIFT (4U) +/*! EDIE4 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE4_SHIFT)) & PORT_EDIER_EDIE4_MASK) + +#define PORT_EDIER_EDIE5_MASK (0x20U) +#define PORT_EDIER_EDIE5_SHIFT (5U) +/*! EDIE5 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE5_SHIFT)) & PORT_EDIER_EDIE5_MASK) + +#define PORT_EDIER_EDIE6_MASK (0x40U) +#define PORT_EDIER_EDIE6_SHIFT (6U) +/*! EDIE6 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE6_SHIFT)) & PORT_EDIER_EDIE6_MASK) + +#define PORT_EDIER_EDIE7_MASK (0x80U) +#define PORT_EDIER_EDIE7_SHIFT (7U) +/*! EDIE7 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE7_SHIFT)) & PORT_EDIER_EDIE7_MASK) + +#define PORT_EDIER_EDIE8_MASK (0x100U) +#define PORT_EDIER_EDIE8_SHIFT (8U) +/*! EDIE8 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE8_SHIFT)) & PORT_EDIER_EDIE8_MASK) + +#define PORT_EDIER_EDIE9_MASK (0x200U) +#define PORT_EDIER_EDIE9_SHIFT (9U) +/*! EDIE9 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE9_SHIFT)) & PORT_EDIER_EDIE9_MASK) + +#define PORT_EDIER_EDIE10_MASK (0x400U) +#define PORT_EDIER_EDIE10_SHIFT (10U) +/*! EDIE10 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE10_SHIFT)) & PORT_EDIER_EDIE10_MASK) + +#define PORT_EDIER_EDIE11_MASK (0x800U) +#define PORT_EDIER_EDIE11_SHIFT (11U) +/*! EDIE11 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE11_SHIFT)) & PORT_EDIER_EDIE11_MASK) + +#define PORT_EDIER_EDIE12_MASK (0x1000U) +#define PORT_EDIER_EDIE12_SHIFT (12U) +/*! EDIE12 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE12_SHIFT)) & PORT_EDIER_EDIE12_MASK) + +#define PORT_EDIER_EDIE13_MASK (0x2000U) +#define PORT_EDIER_EDIE13_SHIFT (13U) +/*! EDIE13 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE13_SHIFT)) & PORT_EDIER_EDIE13_MASK) + +#define PORT_EDIER_EDIE14_MASK (0x4000U) +#define PORT_EDIER_EDIE14_SHIFT (14U) +/*! EDIE14 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE14_SHIFT)) & PORT_EDIER_EDIE14_MASK) + +#define PORT_EDIER_EDIE15_MASK (0x8000U) +#define PORT_EDIER_EDIE15_SHIFT (15U) +/*! EDIE15 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE15_SHIFT)) & PORT_EDIER_EDIE15_MASK) + +#define PORT_EDIER_EDIE16_MASK (0x10000U) +#define PORT_EDIER_EDIE16_SHIFT (16U) +/*! EDIE16 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE16_SHIFT)) & PORT_EDIER_EDIE16_MASK) + +#define PORT_EDIER_EDIE17_MASK (0x20000U) +#define PORT_EDIER_EDIE17_SHIFT (17U) +/*! EDIE17 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE17_SHIFT)) & PORT_EDIER_EDIE17_MASK) + +#define PORT_EDIER_EDIE18_MASK (0x40000U) +#define PORT_EDIER_EDIE18_SHIFT (18U) +/*! EDIE18 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE18_SHIFT)) & PORT_EDIER_EDIE18_MASK) + +#define PORT_EDIER_EDIE19_MASK (0x80000U) +#define PORT_EDIER_EDIE19_SHIFT (19U) +/*! EDIE19 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE19_SHIFT)) & PORT_EDIER_EDIE19_MASK) + +#define PORT_EDIER_EDIE20_MASK (0x100000U) +#define PORT_EDIER_EDIE20_SHIFT (20U) +/*! EDIE20 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE20_SHIFT)) & PORT_EDIER_EDIE20_MASK) + +#define PORT_EDIER_EDIE21_MASK (0x200000U) +#define PORT_EDIER_EDIE21_SHIFT (21U) +/*! EDIE21 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE21_SHIFT)) & PORT_EDIER_EDIE21_MASK) + +#define PORT_EDIER_EDIE22_MASK (0x400000U) +#define PORT_EDIER_EDIE22_SHIFT (22U) +/*! EDIE22 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE22_SHIFT)) & PORT_EDIER_EDIE22_MASK) + +#define PORT_EDIER_EDIE23_MASK (0x800000U) +#define PORT_EDIER_EDIE23_SHIFT (23U) +/*! EDIE23 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE23_SHIFT)) & PORT_EDIER_EDIE23_MASK) + +#define PORT_EDIER_EDIE24_MASK (0x1000000U) +#define PORT_EDIER_EDIE24_SHIFT (24U) +/*! EDIE24 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE24_SHIFT)) & PORT_EDIER_EDIE24_MASK) + +#define PORT_EDIER_EDIE25_MASK (0x2000000U) +#define PORT_EDIER_EDIE25_SHIFT (25U) +/*! EDIE25 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE25_SHIFT)) & PORT_EDIER_EDIE25_MASK) + +#define PORT_EDIER_EDIE26_MASK (0x4000000U) +#define PORT_EDIER_EDIE26_SHIFT (26U) +/*! EDIE26 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE26_SHIFT)) & PORT_EDIER_EDIE26_MASK) + +#define PORT_EDIER_EDIE27_MASK (0x8000000U) +#define PORT_EDIER_EDIE27_SHIFT (27U) +/*! EDIE27 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE27_SHIFT)) & PORT_EDIER_EDIE27_MASK) + +#define PORT_EDIER_EDIE28_MASK (0x10000000U) +#define PORT_EDIER_EDIE28_SHIFT (28U) +/*! EDIE28 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE28_SHIFT)) & PORT_EDIER_EDIE28_MASK) + +#define PORT_EDIER_EDIE29_MASK (0x20000000U) +#define PORT_EDIER_EDIE29_SHIFT (29U) +/*! EDIE29 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE29_SHIFT)) & PORT_EDIER_EDIE29_MASK) + +#define PORT_EDIER_EDIE30_MASK (0x40000000U) +#define PORT_EDIER_EDIE30_SHIFT (30U) +/*! EDIE30 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE30_SHIFT)) & PORT_EDIER_EDIE30_MASK) + +#define PORT_EDIER_EDIE31_MASK (0x80000000U) +#define PORT_EDIER_EDIE31_SHIFT (31U) +/*! EDIE31 - EFT Detect Interrupt Enable + * 0b0..Interrupt not generated upon detection of the EFT event + * 0b1..Interrupt generated upon detection of the EFT event + */ +#define PORT_EDIER_EDIE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDIER_EDIE31_SHIFT)) & PORT_EDIER_EDIE31_MASK) +/*! @} */ + +/*! @name EDCR - EFT Detect Clear */ +/*! @{ */ + +#define PORT_EDCR_EDHC_MASK (0x1U) +#define PORT_EDCR_EDHC_SHIFT (0U) +/*! EDHC - EFT Detect High Clear + * 0b0..Does not clear + * 0b1..Clears + */ +#define PORT_EDCR_EDHC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDHC_SHIFT)) & PORT_EDCR_EDHC_MASK) + +#define PORT_EDCR_EDLC_MASK (0x2U) +#define PORT_EDCR_EDLC_SHIFT (1U) +/*! EDLC - EFT Detect Low Clear + * 0b0..Does not clear + * 0b1..Clears + */ +#define PORT_EDCR_EDLC(x) (((uint32_t)(((uint32_t)(x)) << PORT_EDCR_EDLC_SHIFT)) & PORT_EDCR_EDLC_MASK) +/*! @} */ + +/*! @name CALIB0 - Calibration 0 */ +/*! @{ */ + +#define PORT_CALIB0_NCAL_MASK (0x3FU) +#define PORT_CALIB0_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK) + +#define PORT_CALIB0_PCAL_MASK (0x3F0000U) +#define PORT_CALIB0_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK) +/*! @} */ + +/*! @name CALIB1 - Calibration 1 */ +/*! @{ */ + +#define PORT_CALIB1_NCAL_MASK (0x3FU) +#define PORT_CALIB1_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK) + +#define PORT_CALIB1_PCAL_MASK (0x3F0000U) +#define PORT_CALIB1_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) +/*! @} */ + +/*! @name PCR - Pin Control 0..Pin Control 31 */ +/*! @{ */ + +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +/*! PS - Pull Select + * 0b0..Enables internal pulldown resistor + * 0b1..Enables internal pullup resistor + */ +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) + +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +/*! PE - Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) + +#define PORT_PCR_PV_MASK (0x4U) +#define PORT_PCR_PV_SHIFT (2U) +/*! PV - Pull Value + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK) + +#define PORT_PCR_SRE_MASK (0x8U) +#define PORT_PCR_SRE_SHIFT (3U) +/*! SRE - Slew Rate Enable + * 0b0..Fast + * 0b1..Slow + */ +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) + +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +/*! PFE - Passive Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) + +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) + +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +/*! DSE - Drive Strength Enable + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) + +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ +#define PORT_PCR_MUX_SHIFT (8U) +/*! MUX - Pin Multiplex Control + * 0b0000..Alternative 0 (GPIO) + * 0b0001..Alternative 1 (chip-specific) + * 0b0010..Alternative 2 (chip-specific) + * 0b0011..Alternative 3 (chip-specific) + * 0b0100..Alternative 4 (chip-specific) + * 0b0101..Alternative 5 (chip-specific) + * 0b0110..Alternative 6 (chip-specific) + * 0b0111..Alternative 7 (chip-specific) + * 0b1000..Alternative 8 (chip-specific) + * 0b1001..Alternative 9 (chip-specific) + * 0b1010..Alternative 10 (chip-specific) + * 0b1011..Alternative 11 (chip-specific) + * 0b1100..Alternative 12 (chip-specific) + * 0b1101..Alternative 13 (chip-specific) + */ +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 4), largest definition used */ + +#define PORT_PCR_IBE_MASK (0x1000U) +#define PORT_PCR_IBE_SHIFT (12U) +/*! IBE - Input Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK) + +#define PORT_PCR_INV_MASK (0x2000U) +#define PORT_PCR_INV_SHIFT (13U) +/*! INV - Invert Input + * 0b0..Does not invert + * 0b1..Inverts + */ +#define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK) + +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +/*! LK - Lock Register + * 0b0..Does not lock + * 0b1..Locks + */ +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +/*! @} */ + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x50116000u) + /** Peripheral PORT0 base address */ + #define PORT0_BASE_NS (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT0 base pointer */ + #define PORT0_NS ((PORT_Type *)PORT0_BASE_NS) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x50117000u) + /** Peripheral PORT1 base address */ + #define PORT1_BASE_NS (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT1 base pointer */ + #define PORT1_NS ((PORT_Type *)PORT1_BASE_NS) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x50118000u) + /** Peripheral PORT2 base address */ + #define PORT2_BASE_NS (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT2 base pointer */ + #define PORT2_NS ((PORT_Type *)PORT2_BASE_NS) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x50119000u) + /** Peripheral PORT3 base address */ + #define PORT3_BASE_NS (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT3 base pointer */ + #define PORT3_NS ((PORT_Type *)PORT3_BASE_NS) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x5011A000u) + /** Peripheral PORT4 base address */ + #define PORT4_BASE_NS (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT4 base pointer */ + #define PORT4_NS ((PORT_Type *)PORT4_BASE_NS) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x50042000u) + /** Peripheral PORT5 base address */ + #define PORT5_BASE_NS (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Peripheral PORT5 base pointer */ + #define PORT5_NS ((PORT_Type *)PORT5_BASE_NS) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS_NS { PORT0_BASE_NS, PORT1_BASE_NS, PORT2_BASE_NS, PORT3_BASE_NS, PORT4_BASE_NS, PORT5_BASE_NS } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS_NS { PORT0_NS, PORT1_NS, PORT2_NS, PORT3_NS, PORT4_NS, PORT5_NS } +#else + /** Peripheral PORT0 base address */ + #define PORT0_BASE (0x40116000u) + /** Peripheral PORT0 base pointer */ + #define PORT0 ((PORT_Type *)PORT0_BASE) + /** Peripheral PORT1 base address */ + #define PORT1_BASE (0x40117000u) + /** Peripheral PORT1 base pointer */ + #define PORT1 ((PORT_Type *)PORT1_BASE) + /** Peripheral PORT2 base address */ + #define PORT2_BASE (0x40118000u) + /** Peripheral PORT2 base pointer */ + #define PORT2 ((PORT_Type *)PORT2_BASE) + /** Peripheral PORT3 base address */ + #define PORT3_BASE (0x40119000u) + /** Peripheral PORT3 base pointer */ + #define PORT3 ((PORT_Type *)PORT3_BASE) + /** Peripheral PORT4 base address */ + #define PORT4_BASE (0x4011A000u) + /** Peripheral PORT4 base pointer */ + #define PORT4 ((PORT_Type *)PORT4_BASE) + /** Peripheral PORT5 base address */ + #define PORT5_BASE (0x40042000u) + /** Peripheral PORT5 base pointer */ + #define PORT5 ((PORT_Type *)PORT5_BASE) + /** Array initializer of PORT peripheral base addresses */ + #define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE, PORT5_BASE } + /** Array initializer of PORT peripheral base pointers */ + #define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4, PORT5 } +#endif + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PUF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer + * @{ + */ + +/** PUF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control, offset: 0x0 */ + __I uint32_t ORR; /**< Operation Result, offset: 0x4 */ + __IO uint32_t SR; /**< Status, offset: 0x8 */ + __I uint32_t AR; /**< Allow, offset: 0xC */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x10 */ + __IO uint32_t IMR; /**< Interrupt Mask, offset: 0x14 */ + __IO uint32_t ISR; /**< Interrupt Status, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DATA_DEST; /**< Data Destination, offset: 0x20 */ + __IO uint32_t DATA_SRC; /**< Data Source, offset: 0x24 */ + uint8_t RESERVED_1[120]; + __O uint32_t DIR; /**< Data Input, offset: 0xA0 */ + uint8_t RESERVED_2[4]; + __I uint32_t DOR; /**< Data Output, offset: 0xA8 */ + uint8_t RESERVED_3[20]; + __IO uint32_t MISC; /**< Miscellaneous, offset: 0xC0 */ + uint8_t RESERVED_4[12]; + __IO uint32_t IF_SR; /**< Interface Status, offset: 0xD0 */ + uint8_t RESERVED_5[8]; + __I uint32_t PSR; /**< PUF Score, offset: 0xDC */ + __I uint32_t HW_RUC0; /**< Hardware Restrict User Context 0, offset: 0xE0 */ + __I uint32_t HW_RUC1; /**< Hardware Restrict User Context 1, offset: 0xE4 */ + uint8_t RESERVED_6[12]; + __I uint32_t HW_INFO; /**< Hardware Information, offset: 0xF4 */ + __I uint32_t HW_ID; /**< Hardware Identifier, offset: 0xF8 */ + __I uint32_t HW_VER; /**< Hardware Version, offset: 0xFC */ + __IO uint32_t CONFIG; /**< PUF command blocking configuration, offset: 0x100 */ + __IO uint32_t SEC_LOCK; /**< Security level lock, offset: 0x104 */ + __IO uint32_t APP_CTX_MASK; /**< Application defined context mask, offset: 0x108 */ + uint8_t RESERVED_7[500]; + __IO uint32_t SRAM_CFG; /**< SRAM Configuration, offset: 0x300 */ + __I uint32_t SRAM_STATUS; /**< Status, offset: 0x304 */ + uint8_t RESERVED_8[208]; + __O uint32_t SRAM_INT_CLR_ENABLE; /**< Interrupt Enable Clear, offset: 0x3D8 */ + __O uint32_t SRAM_INT_SET_ENABLE; /**< Interrupt Enable Set, offset: 0x3DC */ + __I uint32_t SRAM_INT_STATUS; /**< Interrupt Status, offset: 0x3E0 */ + __I uint32_t SRAM_INT_ENABLE; /**< Interrupt Enable, offset: 0x3E4 */ + __O uint32_t SRAM_INT_CLR_STATUS; /**< Interrupt Status Clear, offset: 0x3E8 */ + __O uint32_t SRAM_INT_SET_STATUS; /**< Interrupt Status set, offset: 0x3EC */ +} PUF_Type; + +/* ---------------------------------------------------------------------------- + -- PUF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PUF_Register_Masks PUF Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define PUF_CR_ZEROIZE_MASK (0x1U) +#define PUF_CR_ZEROIZE_SHIFT (0U) +/*! ZEROIZE - Zeroize operation */ +#define PUF_CR_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ZEROIZE_SHIFT)) & PUF_CR_ZEROIZE_MASK) + +#define PUF_CR_ENROLL_MASK (0x2U) +#define PUF_CR_ENROLL_SHIFT (1U) +/*! ENROLL - Enroll operation */ +#define PUF_CR_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_ENROLL_SHIFT)) & PUF_CR_ENROLL_MASK) + +#define PUF_CR_START_MASK (0x4U) +#define PUF_CR_START_SHIFT (2U) +/*! START - Start operation */ +#define PUF_CR_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_START_SHIFT)) & PUF_CR_START_MASK) + +#define PUF_CR_RECONSTRUCT_MASK (0x8U) +#define PUF_CR_RECONSTRUCT_SHIFT (3U) +/*! RECONSTRUCT - Reconstruct operation */ +#define PUF_CR_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_RECONSTRUCT_SHIFT)) & PUF_CR_RECONSTRUCT_MASK) + +#define PUF_CR_STOP_MASK (0x20U) +#define PUF_CR_STOP_SHIFT (5U) +/*! STOP - Stop operation */ +#define PUF_CR_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_STOP_SHIFT)) & PUF_CR_STOP_MASK) + +#define PUF_CR_GET_KEY_MASK (0x40U) +#define PUF_CR_GET_KEY_SHIFT (6U) +/*! GET_KEY - Get Key operation */ +#define PUF_CR_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GET_KEY_SHIFT)) & PUF_CR_GET_KEY_MASK) + +#define PUF_CR_UNWRAP_MASK (0x80U) +#define PUF_CR_UNWRAP_SHIFT (7U) +/*! UNWRAP - Unwrap operation */ +#define PUF_CR_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_UNWRAP_SHIFT)) & PUF_CR_UNWRAP_MASK) + +#define PUF_CR_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_CR_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! WRAP_GENERATED_RANDOM - Wrap Generated Random operation */ +#define PUF_CR_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_CR_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_CR_WRAP_MASK (0x200U) +#define PUF_CR_WRAP_SHIFT (9U) +/*! WRAP - Wrap operation */ +#define PUF_CR_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_WRAP_SHIFT)) & PUF_CR_WRAP_MASK) + +#define PUF_CR_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_CR_GENERATE_RANDOM_SHIFT (15U) +/*! GENERATE_RANDOM - Generate Random operation */ +#define PUF_CR_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_GENERATE_RANDOM_SHIFT)) & PUF_CR_GENERATE_RANDOM_MASK) + +#define PUF_CR_TEST_MEMORY_MASK (0x40000000U) +#define PUF_CR_TEST_MEMORY_SHIFT (30U) +/*! TEST_MEMORY - Test memory operation */ +#define PUF_CR_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_MEMORY_SHIFT)) & PUF_CR_TEST_MEMORY_MASK) + +#define PUF_CR_TEST_PUF_MASK (0x80000000U) +#define PUF_CR_TEST_PUF_SHIFT (31U) +/*! TEST_PUF - Test PUF operation */ +#define PUF_CR_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_CR_TEST_PUF_SHIFT)) & PUF_CR_TEST_PUF_MASK) +/*! @} */ + +/*! @name ORR - Operation Result */ +/*! @{ */ + +#define PUF_ORR_RESULT_CODE_MASK (0xFFU) +#define PUF_ORR_RESULT_CODE_SHIFT (0U) +/*! RESULT_CODE - Result code of last operation + * 0b00000000..Indicates that the last operation was successful or operation is in progress. + * 0b11110000..Indicates that the AC is not for the current product/version. + * 0b11110001..Indicates that the AC in the second phase is not for the current product/version. + * 0b11110010..Indicates that the AC is corrupted. + * 0b11110011..Indicates that the AC in the second phase is corrupted. + * 0b11110100..Indicates that the authentication of the provided AC failed. + * 0b11110101..Indicates that the authentication of the provided AC failed in the second phase. + * 0b11110110..Indicates that the SRAM PUF quality verification fails. + * 0b11110111..Indicates that the incorrect or unsupported context is provided. + * 0b11111000..Indicates that a data destination was set that is not allowed according to other settings and the current PUF state. + * 0b11111111..Indicates that the PUF SRAM access has failed. + */ +#define PUF_ORR_RESULT_CODE(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_RESULT_CODE_SHIFT)) & PUF_ORR_RESULT_CODE_MASK) + +#define PUF_ORR_LAST_OPERATION_MASK (0xFF000000U) +#define PUF_ORR_LAST_OPERATION_SHIFT (24U) +/*! LAST_OPERATION - Last operation type + * 0b00000000..Indicates that the operation is in progress. + * 0b00000001..Indicates that the last operation was Enroll. + * 0b00000010..Indicates that the last operation was Start. + * 0b00000011..Indicates that the last operation was Reconstruct + * 0b00000101..Indicates that the last operation was Stop. + * 0b00000110..Indicates that the last operation was Get Key. + * 0b00000111..Indicates that the last operation was Unwrap. + * 0b00001000..Indicates that the last operation was Wrap Generated Random. + * 0b00001001..Indicates that the last operation was Wrap. + * 0b00001111..Indicates that the last operation was Generate Random. + * 0b00011110..Indicates that the last operation was Test Memory. + * 0b00011111..Indicates that the last operation was Test PUF. + * 0b00100000..Indicates that the last operation was Initialization. + * 0b00101111..Indicates that the last operation was Zeroize. + */ +#define PUF_ORR_LAST_OPERATION(x) (((uint32_t)(((uint32_t)(x)) << PUF_ORR_LAST_OPERATION_SHIFT)) & PUF_ORR_LAST_OPERATION_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define PUF_SR_BUSY_MASK (0x1U) +#define PUF_SR_BUSY_SHIFT (0U) +/*! BUSY - Operation in progress */ +#define PUF_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_BUSY_SHIFT)) & PUF_SR_BUSY_MASK) + +#define PUF_SR_OK_MASK (0x2U) +#define PUF_SR_OK_SHIFT (1U) +/*! OK - Last operation successful */ +#define PUF_SR_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_OK_SHIFT)) & PUF_SR_OK_MASK) + +#define PUF_SR_ERROR_MASK (0x4U) +#define PUF_SR_ERROR_SHIFT (2U) +/*! ERROR - Last operation failed */ +#define PUF_SR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ERROR_SHIFT)) & PUF_SR_ERROR_MASK) + +#define PUF_SR_ZEROIZED_MASK (0x8U) +#define PUF_SR_ZEROIZED_SHIFT (3U) +/*! ZEROIZED - Zeroized or Locked state */ +#define PUF_SR_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_ZEROIZED_SHIFT)) & PUF_SR_ZEROIZED_MASK) + +#define PUF_SR_REJECTED_MASK (0x10U) +#define PUF_SR_REJECTED_SHIFT (4U) +/*! REJECTED - Operation rejected */ +#define PUF_SR_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_REJECTED_SHIFT)) & PUF_SR_REJECTED_MASK) + +#define PUF_SR_DI_REQUEST_MASK (0x20U) +#define PUF_SR_DI_REQUEST_SHIFT (5U) +/*! DI_REQUEST - Indicates the request for data in transfer via the DIR register */ +#define PUF_SR_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DI_REQUEST_SHIFT)) & PUF_SR_DI_REQUEST_MASK) + +#define PUF_SR_DO_REQUEST_MASK (0x40U) +#define PUF_SR_DO_REQUEST_SHIFT (6U) +/*! DO_REQUEST - Indicates the request for data out transfer via the DOR register */ +#define PUF_SR_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_SR_DO_REQUEST_SHIFT)) & PUF_SR_DO_REQUEST_MASK) +/*! @} */ + +/*! @name AR - Allow */ +/*! @{ */ + +#define PUF_AR_ALLOW_ENROLL_MASK (0x2U) +#define PUF_AR_ALLOW_ENROLL_SHIFT (1U) +/*! ALLOW_ENROLL - Enroll operation + * 0b0..Indicates that the Enroll operation is not allowed + * 0b1..Indicates that the Enroll operation is allowed + */ +#define PUF_AR_ALLOW_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_ENROLL_SHIFT)) & PUF_AR_ALLOW_ENROLL_MASK) + +#define PUF_AR_ALLOW_START_MASK (0x4U) +#define PUF_AR_ALLOW_START_SHIFT (2U) +/*! ALLOW_START - Start operation + * 0b0..Indicates that the Start operation is not allowed + * 0b1..Indicates that the Start operation is allowed + */ +#define PUF_AR_ALLOW_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_START_SHIFT)) & PUF_AR_ALLOW_START_MASK) + +#define PUF_AR_ALLOW_RECONSTRUCT_MASK (0x8U) +#define PUF_AR_ALLOW_RECONSTRUCT_SHIFT (3U) +/*! ALLOW_RECONSTRUCT - Reconstruct operation + * 0b0..Indicates that the Reconstruct operation is not allowed + * 0b1..Indicates that the Reconstruct operation is allowed + */ +#define PUF_AR_ALLOW_RECONSTRUCT(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_RECONSTRUCT_SHIFT)) & PUF_AR_ALLOW_RECONSTRUCT_MASK) + +#define PUF_AR_ALLOW_STOP_MASK (0x20U) +#define PUF_AR_ALLOW_STOP_SHIFT (5U) +/*! ALLOW_STOP - Stop operation + * 0b0..Indicates that the Stop operation is not allowed + * 0b1..Indicates that the Stop operation is allowed + */ +#define PUF_AR_ALLOW_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_STOP_SHIFT)) & PUF_AR_ALLOW_STOP_MASK) + +#define PUF_AR_ALLOW_GET_KEY_MASK (0x40U) +#define PUF_AR_ALLOW_GET_KEY_SHIFT (6U) +/*! ALLOW_GET_KEY - Get Key operation + * 0b0..Indicates that the Get Key operation is not allowed + * 0b1..Indicates that the Get Key operation is allowed + */ +#define PUF_AR_ALLOW_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GET_KEY_SHIFT)) & PUF_AR_ALLOW_GET_KEY_MASK) + +#define PUF_AR_ALLOW_UNWRAP_MASK (0x80U) +#define PUF_AR_ALLOW_UNWRAP_SHIFT (7U) +/*! ALLOW_UNWRAP - Unwrap operation + * 0b0..Indicates that the Unwrap operation is not allowed + * 0b1..Indicates that the Unwrap operation is allowed + */ +#define PUF_AR_ALLOW_UNWRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_UNWRAP_SHIFT)) & PUF_AR_ALLOW_UNWRAP_MASK) + +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK (0x100U) +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT (8U) +/*! ALLOW_WRAP_GENERATED_RANDOM - Wrap Generated Random operation + * 0b0..Indicates that the Wrap Generated Random operation is not allowed + * 0b1..Indicates that the Wrap Generated Random operation is allowed + */ +#define PUF_AR_ALLOW_WRAP_GENERATED_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_SHIFT)) & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK) + +#define PUF_AR_ALLOW_WRAP_MASK (0x200U) +#define PUF_AR_ALLOW_WRAP_SHIFT (9U) +/*! ALLOW_WRAP - Wrap operation + * 0b0..Indicates that the Wrap operation is not allowed + * 0b1..Indicates that the Wrap operation is allowed + */ +#define PUF_AR_ALLOW_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_WRAP_SHIFT)) & PUF_AR_ALLOW_WRAP_MASK) + +#define PUF_AR_ALLOW_GENERATE_RANDOM_MASK (0x8000U) +#define PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT (15U) +/*! ALLOW_GENERATE_RANDOM - Generate Random operation + * 0b0..Indicates that the Generate Random operation is not allowed + * 0b1..Indicates that the Generate Random operation is allowed + */ +#define PUF_AR_ALLOW_GENERATE_RANDOM(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_GENERATE_RANDOM_SHIFT)) & PUF_AR_ALLOW_GENERATE_RANDOM_MASK) + +#define PUF_AR_ALLOW_TEST_MEMORY_MASK (0x40000000U) +#define PUF_AR_ALLOW_TEST_MEMORY_SHIFT (30U) +/*! ALLOW_TEST_MEMORY + * 0b0..Indicates that the Test Memory operation is not allowed + * 0b1..Indicates that the Test Memory operation is allowed + */ +#define PUF_AR_ALLOW_TEST_MEMORY(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_MEMORY_SHIFT)) & PUF_AR_ALLOW_TEST_MEMORY_MASK) + +#define PUF_AR_ALLOW_TEST_PUF_MASK (0x80000000U) +#define PUF_AR_ALLOW_TEST_PUF_SHIFT (31U) +/*! ALLOW_TEST_PUF - Test PUF operation + * 0b0..Test PUF operation is not allowed + * 0b1..Test PUF operation is allowed + */ +#define PUF_AR_ALLOW_TEST_PUF(x) (((uint32_t)(((uint32_t)(x)) << PUF_AR_ALLOW_TEST_PUF_SHIFT)) & PUF_AR_ALLOW_TEST_PUF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define PUF_IER_INT_EN_MASK (0x1U) +#define PUF_IER_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt enable + * 0b0..Disables all PUF interrupts + * 0b1..Enables all PUF interrupts that are enabled in the Interrupt Mask register + */ +#define PUF_IER_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << PUF_IER_INT_EN_SHIFT)) & PUF_IER_INT_EN_MASK) +/*! @} */ + +/*! @name IMR - Interrupt Mask */ +/*! @{ */ + +#define PUF_IMR_INT_EN_BUSY_MASK (0x1U) +#define PUF_IMR_INT_EN_BUSY_SHIFT (0U) +/*! INT_EN_BUSY - Busy interrupt */ +#define PUF_IMR_INT_EN_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_BUSY_SHIFT)) & PUF_IMR_INT_EN_BUSY_MASK) + +#define PUF_IMR_INT_EN_OK_MASK (0x2U) +#define PUF_IMR_INT_EN_OK_SHIFT (1U) +/*! INT_EN_OK - Ok interrupt */ +#define PUF_IMR_INT_EN_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_OK_SHIFT)) & PUF_IMR_INT_EN_OK_MASK) + +#define PUF_IMR_INT_EN_ERROR_MASK (0x4U) +#define PUF_IMR_INT_EN_ERROR_SHIFT (2U) +/*! INT_EN_ERROR - Error interrupt */ +#define PUF_IMR_INT_EN_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ERROR_SHIFT)) & PUF_IMR_INT_EN_ERROR_MASK) + +#define PUF_IMR_INT_EN_ZEROIZED_MASK (0x8U) +#define PUF_IMR_INT_EN_ZEROIZED_SHIFT (3U) +/*! INT_EN_ZEROIZED - Zeroized interrupt */ +#define PUF_IMR_INT_EN_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_ZEROIZED_SHIFT)) & PUF_IMR_INT_EN_ZEROIZED_MASK) + +#define PUF_IMR_INT_EN_REJECTED_MASK (0x10U) +#define PUF_IMR_INT_EN_REJECTED_SHIFT (4U) +/*! INT_EN_REJECTED - Rejected interrupt */ +#define PUF_IMR_INT_EN_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_REJECTED_SHIFT)) & PUF_IMR_INT_EN_REJECTED_MASK) + +#define PUF_IMR_INT_EN_DI_REQUEST_MASK (0x20U) +#define PUF_IMR_INT_EN_DI_REQUEST_SHIFT (5U) +/*! INT_EN_DI_REQUEST - Data in request interrupt */ +#define PUF_IMR_INT_EN_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DI_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DI_REQUEST_MASK) + +#define PUF_IMR_INT_EN_DO_REQUEST_MASK (0x40U) +#define PUF_IMR_INT_EN_DO_REQUEST_SHIFT (6U) +/*! INT_EN_DO_REQUEST - Data out request interrupt */ +#define PUF_IMR_INT_EN_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_IMR_INT_EN_DO_REQUEST_SHIFT)) & PUF_IMR_INT_EN_DO_REQUEST_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define PUF_ISR_INT_BUSY_MASK (0x1U) +#define PUF_ISR_INT_BUSY_SHIFT (0U) +/*! INT_BUSY - Negative edge occurred on Busy */ +#define PUF_ISR_INT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_BUSY_SHIFT)) & PUF_ISR_INT_BUSY_MASK) + +#define PUF_ISR_INT_OK_MASK (0x2U) +#define PUF_ISR_INT_OK_SHIFT (1U) +/*! INT_OK - Positive edge occurred on Ok */ +#define PUF_ISR_INT_OK(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_OK_SHIFT)) & PUF_ISR_INT_OK_MASK) + +#define PUF_ISR_INT_ERROR_MASK (0x4U) +#define PUF_ISR_INT_ERROR_SHIFT (2U) +/*! INT_ERROR - Positive edge occurred on Error */ +#define PUF_ISR_INT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ERROR_SHIFT)) & PUF_ISR_INT_ERROR_MASK) + +#define PUF_ISR_INT_ZEROIZED_MASK (0x8U) +#define PUF_ISR_INT_ZEROIZED_SHIFT (3U) +/*! INT_ZEROIZED - Positive edge occurred on Zeroized */ +#define PUF_ISR_INT_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_ZEROIZED_SHIFT)) & PUF_ISR_INT_ZEROIZED_MASK) + +#define PUF_ISR_INT_REJECTED_MASK (0x10U) +#define PUF_ISR_INT_REJECTED_SHIFT (4U) +/*! INT_REJECTED - Positive edge occurred on Rejected */ +#define PUF_ISR_INT_REJECTED(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_REJECTED_SHIFT)) & PUF_ISR_INT_REJECTED_MASK) + +#define PUF_ISR_INT_DI_REQUEST_MASK (0x20U) +#define PUF_ISR_INT_DI_REQUEST_SHIFT (5U) +/*! INT_DI_REQUEST - Positive edge occurred on di_request */ +#define PUF_ISR_INT_DI_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DI_REQUEST_SHIFT)) & PUF_ISR_INT_DI_REQUEST_MASK) + +#define PUF_ISR_INT_DO_REQUEST_MASK (0x40U) +#define PUF_ISR_INT_DO_REQUEST_SHIFT (6U) +/*! INT_DO_REQUEST - Positive edge occurred on do_request */ +#define PUF_ISR_INT_DO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ISR_INT_DO_REQUEST_SHIFT)) & PUF_ISR_INT_DO_REQUEST_MASK) +/*! @} */ + +/*! @name DATA_DEST - Data Destination */ +/*! @{ */ + +#define PUF_DATA_DEST_DEST_DOR_MASK (0x1U) +#define PUF_DATA_DEST_DEST_DOR_SHIFT (0U) +/*! DEST_DOR - Key available via the DOR register */ +#define PUF_DATA_DEST_DEST_DOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_DOR_SHIFT)) & PUF_DATA_DEST_DEST_DOR_MASK) + +#define PUF_DATA_DEST_DEST_SO_MASK (0x2U) +#define PUF_DATA_DEST_DEST_SO_SHIFT (1U) +/*! DEST_SO - Key available to ELS */ +#define PUF_DATA_DEST_DEST_SO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_DEST_DEST_SO_SHIFT)) & PUF_DATA_DEST_DEST_SO_MASK) +/*! @} */ + +/*! @name DATA_SRC - Data Source */ +/*! @{ */ + +#define PUF_DATA_SRC_SRC_DIR_MASK (0x1U) +#define PUF_DATA_SRC_SRC_DIR_SHIFT (0U) +/*! SRC_DIR - Data provided via the DIR register */ +#define PUF_DATA_SRC_SRC_DIR(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_DIR_SHIFT)) & PUF_DATA_SRC_SRC_DIR_MASK) + +#define PUF_DATA_SRC_SRC_SI_MASK (0x2U) +#define PUF_DATA_SRC_SRC_SI_SHIFT (1U) +/*! SRC_SI - Data provided via the SI interface */ +#define PUF_DATA_SRC_SRC_SI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DATA_SRC_SRC_SI_SHIFT)) & PUF_DATA_SRC_SRC_SI_MASK) +/*! @} */ + +/*! @name DIR - Data Input */ +/*! @{ */ + +#define PUF_DIR_DI_MASK (0xFFFFFFFFU) +#define PUF_DIR_DI_SHIFT (0U) +/*! DI - Input data */ +#define PUF_DIR_DI(x) (((uint32_t)(((uint32_t)(x)) << PUF_DIR_DI_SHIFT)) & PUF_DIR_DI_MASK) +/*! @} */ + +/*! @name DOR - Data Output */ +/*! @{ */ + +#define PUF_DOR_DO_MASK (0xFFFFFFFFU) +#define PUF_DOR_DO_SHIFT (0U) +/*! DO - Output data */ +#define PUF_DOR_DO(x) (((uint32_t)(((uint32_t)(x)) << PUF_DOR_DO_SHIFT)) & PUF_DOR_DO_MASK) +/*! @} */ + +/*! @name MISC - Miscellaneous */ +/*! @{ */ + +#define PUF_MISC_DATA_ENDIANNESS_MASK (0x1U) +#define PUF_MISC_DATA_ENDIANNESS_SHIFT (0U) +/*! DATA_ENDIANNESS - Defines the endianness of data in DIR and DOR: + * 0b0..Little endian + * 0b1..Big endian (default) + */ +#define PUF_MISC_DATA_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_MISC_DATA_ENDIANNESS_SHIFT)) & PUF_MISC_DATA_ENDIANNESS_MASK) +/*! @} */ + +/*! @name IF_SR - Interface Status */ +/*! @{ */ + +#define PUF_IF_SR_APB_ERROR_MASK (0x1U) +#define PUF_IF_SR_APB_ERROR_SHIFT (0U) +/*! APB_ERROR - APB error */ +#define PUF_IF_SR_APB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IF_SR_APB_ERROR_SHIFT)) & PUF_IF_SR_APB_ERROR_MASK) +/*! @} */ + +/*! @name PSR - PUF Score */ +/*! @{ */ + +#define PUF_PSR_PUF_SCORE_MASK (0xFU) +#define PUF_PSR_PUF_SCORE_SHIFT (0U) +/*! PUF_SCORE - Provides the PUF score obtained during the last Test PUF, Enroll or Start operation. */ +#define PUF_PSR_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << PUF_PSR_PUF_SCORE_SHIFT)) & PUF_PSR_PUF_SCORE_MASK) +/*! @} */ + +/*! @name HW_RUC0 - Hardware Restrict User Context 0 */ +/*! @{ */ + +#define PUF_HW_RUC0_LC_STATE_MASK (0xFFU) +#define PUF_HW_RUC0_LC_STATE_SHIFT (0U) +/*! LC_STATE - Life cycle state based restrictions + * 0b00000011..OEM Develop + * 0b00000111..OEM Develop 2 + * 0b00001111..OEM In-field + * 0b00011111..OEM Field return + * 0b00111111..NXP Field Return/Failure Analysis + * 0b11001111..In-field Locked + * 0b11111111..Bricked + */ +#define PUF_HW_RUC0_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_LC_STATE_SHIFT)) & PUF_HW_RUC0_LC_STATE_MASK) + +#define PUF_HW_RUC0_BOOT_STATE_MASK (0xFFFF00U) +#define PUF_HW_RUC0_BOOT_STATE_SHIFT (8U) +/*! BOOT_STATE - Temporal boot state */ +#define PUF_HW_RUC0_BOOT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_BOOT_STATE_SHIFT)) & PUF_HW_RUC0_BOOT_STATE_MASK) + +#define PUF_HW_RUC0_CPU0_DEBUG_MASK (0x1000000U) +#define PUF_HW_RUC0_CPU0_DEBUG_SHIFT (24U) +/*! CPU0_DEBUG - Disable key access when debugger is attached to CPU0 after power-up */ +#define PUF_HW_RUC0_CPU0_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_CPU0_DEBUG_SHIFT)) & PUF_HW_RUC0_CPU0_DEBUG_MASK) + +#define PUF_HW_RUC0_COOLFLUX_DEBUG_MASK (0x2000000U) +#define PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT (25U) +/*! COOLFLUX_DEBUG - Disable key access when debugger is attached to COOLFLUX after power-up */ +#define PUF_HW_RUC0_COOLFLUX_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_COOLFLUX_DEBUG_SHIFT)) & PUF_HW_RUC0_COOLFLUX_DEBUG_MASK) + +#define PUF_HW_RUC0_dsp_debug_MASK (0x4000000U) +#define PUF_HW_RUC0_dsp_debug_SHIFT (26U) +/*! dsp_debug - DSP debug status. */ +#define PUF_HW_RUC0_dsp_debug(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_dsp_debug_SHIFT)) & PUF_HW_RUC0_dsp_debug_MASK) + +#define PUF_HW_RUC0_ACCESS_LEVEL_MASK (0xF0000000U) +#define PUF_HW_RUC0_ACCESS_LEVEL_SHIFT (28U) +/*! ACCESS_LEVEL - Restrict the key access based on TrustZone security level */ +#define PUF_HW_RUC0_ACCESS_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC0_ACCESS_LEVEL_SHIFT)) & PUF_HW_RUC0_ACCESS_LEVEL_MASK) +/*! @} */ + +/*! @name HW_RUC1 - Hardware Restrict User Context 1 */ +/*! @{ */ + +#define PUF_HW_RUC1_APP_CTX_MASK (0xFFFFFFFFU) +#define PUF_HW_RUC1_APP_CTX_SHIFT (0U) +/*! APP_CTX - Application customizable context */ +#define PUF_HW_RUC1_APP_CTX(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_RUC1_APP_CTX_SHIFT)) & PUF_HW_RUC1_APP_CTX_MASK) +/*! @} */ + +/*! @name HW_INFO - Hardware Information */ +/*! @{ */ + +#define PUF_HW_INFO_CONFIG_WRAP_MASK (0x1000000U) +#define PUF_HW_INFO_CONFIG_WRAP_SHIFT (24U) +/*! CONFIG_WRAP - Wrap configuration + * 0b0..Indicates that Wrap is not included + * 0b1..Indicates that Wrap is included + */ +#define PUF_HW_INFO_CONFIG_WRAP(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_WRAP_SHIFT)) & PUF_HW_INFO_CONFIG_WRAP_MASK) + +#define PUF_HW_INFO_CONFIG_TYPE_MASK (0xF0000000U) +#define PUF_HW_INFO_CONFIG_TYPE_SHIFT (28U) +/*! CONFIG_TYPE - PUF configuration + * 0b0001..Indicates that PUF configuration is Safe. + * 0b0010..Indicates that PUF configuration is Plus. + */ +#define PUF_HW_INFO_CONFIG_TYPE(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_INFO_CONFIG_TYPE_SHIFT)) & PUF_HW_INFO_CONFIG_TYPE_MASK) +/*! @} */ + +/*! @name HW_ID - Hardware Identifier */ +/*! @{ */ + +#define PUF_HW_ID_HW_ID_MASK (0xFFFFFFFFU) +#define PUF_HW_ID_HW_ID_SHIFT (0U) +/*! HW_ID - Provides the hardware identifier */ +#define PUF_HW_ID_HW_ID(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_ID_HW_ID_SHIFT)) & PUF_HW_ID_HW_ID_MASK) +/*! @} */ + +/*! @name HW_VER - Hardware Version */ +/*! @{ */ + +#define PUF_HW_VER_HW_REV_MASK (0xFFU) +#define PUF_HW_VER_HW_REV_SHIFT (0U) +/*! HW_REV - Provides the hardware version, patch part */ +#define PUF_HW_VER_HW_REV(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_REV_SHIFT)) & PUF_HW_VER_HW_REV_MASK) + +#define PUF_HW_VER_HW_VERSION_MINOR_MASK (0xFF00U) +#define PUF_HW_VER_HW_VERSION_MINOR_SHIFT (8U) +/*! HW_VERSION_MINOR - Provides the hardware version, minor part */ +#define PUF_HW_VER_HW_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MINOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MINOR_MASK) + +#define PUF_HW_VER_HW_VERSION_MAJOR_MASK (0xFF0000U) +#define PUF_HW_VER_HW_VERSION_MAJOR_SHIFT (16U) +/*! HW_VERSION_MAJOR - Provides the hardware version, major part */ +#define PUF_HW_VER_HW_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PUF_HW_VER_HW_VERSION_MAJOR_SHIFT)) & PUF_HW_VER_HW_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name CONFIG - PUF command blocking configuration */ +/*! @{ */ + +#define PUF_CONFIG_DIS_PUF_ENROLL_MASK (0x2U) +#define PUF_CONFIG_DIS_PUF_ENROLL_SHIFT (1U) +/*! DIS_PUF_ENROLL - Disable PUF enroll command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_ENROLL_SHIFT)) & PUF_CONFIG_DIS_PUF_ENROLL_MASK) + +#define PUF_CONFIG_DIS_PUF_START_MASK (0x4U) +#define PUF_CONFIG_DIS_PUF_START_SHIFT (2U) +/*! DIS_PUF_START - Disable PUF start command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_START_SHIFT)) & PUF_CONFIG_DIS_PUF_START_MASK) + +#define PUF_CONFIG_DIS_PUF_STOP_MASK (0x20U) +#define PUF_CONFIG_DIS_PUF_STOP_SHIFT (5U) +/*! DIS_PUF_STOP - Disable PUF stop command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_STOP(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_STOP_SHIFT)) & PUF_CONFIG_DIS_PUF_STOP_MASK) + +#define PUF_CONFIG_DIS_PUF_GET_KEY_MASK (0x40U) +#define PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT (6U) +/*! DIS_PUF_GET_KEY - Disable PUF get key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GET_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GET_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK (0x80U) +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT (7U) +/*! DIS_PUF_UNWRAP_KEY - Disable PUF unwrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_UNWRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_UNWRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_UNWRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK (0x100U) +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT (8U) +/*! DIS_PUF_GEN_WRAP_KEY - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK (0x200U) +#define PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT (9U) +/*! DIS_PUF_WRAP_KEY - Disable PUF wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_WRAP_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_WRAP_KEY_SHIFT)) & PUF_CONFIG_DIS_PUF_WRAP_KEY_MASK) + +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK (0x8000U) +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT (15U) +/*! DIS_PUF_GEN_RANDOM_NUMBER - Disable PUF generate and wrap key command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_SHIFT)) & PUF_CONFIG_DIS_PUF_GEN_RANDOM_NUMBER_MASK) + +#define PUF_CONFIG_DIS_PUF_TEST_MASK (0x80000000U) +#define PUF_CONFIG_DIS_PUF_TEST_SHIFT (31U) +/*! DIS_PUF_TEST - Disable PUF test command + * 0b0..Command enabled + * 0b1..Command disabled + */ +#define PUF_CONFIG_DIS_PUF_TEST(x) (((uint32_t)(((uint32_t)(x)) << PUF_CONFIG_DIS_PUF_TEST_SHIFT)) & PUF_CONFIG_DIS_PUF_TEST_MASK) +/*! @} */ + +/*! @name SEC_LOCK - Security level lock */ +/*! @{ */ + +#define PUF_SEC_LOCK_SEC_LEVEL_MASK (0x3U) +#define PUF_SEC_LOCK_SEC_LEVEL_SHIFT (0U) +/*! SEC_LEVEL - Security Level + * 0b00..Non-secure and non-privileged Master + * 0b01..Non-secure and privileged Master + * 0b10..Secure and non-privileged Master + * 0b11..Secure and privileged Master + */ +#define PUF_SEC_LOCK_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK (0xCU) +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT (2U) +/*! ANTI_POLE_SEC_LEVEL - Anti-pole of security level + * 0b00..Secure and privileged Master + * 0b01..Secure and non-privileged Master + * 0b10..Non-secure and privileged Master + * 0b11..Non-secure and non-privileged Master + */ +#define PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_SHIFT)) & PUF_SEC_LOCK_ANTI_POLE_SEC_LEVEL_MASK) + +#define PUF_SEC_LOCK_PATTERN_MASK (0xFFF0U) +#define PUF_SEC_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Pattern */ +#define PUF_SEC_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PUF_SEC_LOCK_PATTERN_SHIFT)) & PUF_SEC_LOCK_PATTERN_MASK) +/*! @} */ + +/*! @name APP_CTX_MASK - Application defined context mask */ +/*! @{ */ + +#define PUF_APP_CTX_MASK_APP_CTX_MASK_MASK (0xFFFFFFFFU) +#define PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT (0U) +/*! APP_CTX_MASK - Application defined context */ +#define PUF_APP_CTX_MASK_APP_CTX_MASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_APP_CTX_MASK_APP_CTX_MASK_SHIFT)) & PUF_APP_CTX_MASK_APP_CTX_MASK_MASK) +/*! @} */ + +/*! @name SRAM_CFG - SRAM Configuration */ +/*! @{ */ + +#define PUF_SRAM_CFG_ENABLE_MASK (0x1U) +#define PUF_SRAM_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - PUF SRAM Controller activation + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_ENABLE_SHIFT)) & PUF_SRAM_CFG_ENABLE_MASK) + +#define PUF_SRAM_CFG_CKGATING_MASK (0x4U) +#define PUF_SRAM_CFG_CKGATING_SHIFT (2U) +/*! CKGATING - PUF SRAM Clock Gating control + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_CFG_CKGATING(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_CFG_CKGATING_SHIFT)) & PUF_SRAM_CFG_CKGATING_MASK) +/*! @} */ + +/*! @name SRAM_STATUS - Status */ +/*! @{ */ + +#define PUF_SRAM_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_STATUS_READY_SHIFT (0U) +/*! READY - PUF SRAM Controller State */ +#define PUF_SRAM_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_STATUS_READY_SHIFT)) & PUF_SRAM_STATUS_READY_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_ENABLE - Interrupt Enable Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable clear */ +#define PUF_SRAM_INT_CLR_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable clear */ +#define PUF_SRAM_INT_CLR_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_ENABLE - Interrupt Enable Set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable set */ +#define PUF_SRAM_INT_SET_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Enable set */ +#define PUF_SRAM_INT_SET_ENABLE_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_ENABLE_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_ENABLE_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_STATUS - Interrupt Status */ +/*! @{ */ + +#define PUF_SRAM_INT_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status */ +#define PUF_SRAM_INT_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_READY_SHIFT)) & PUF_SRAM_INT_STATUS_READY_MASK) + +#define PUF_SRAM_INT_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status */ +#define PUF_SRAM_INT_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define PUF_SRAM_INT_ENABLE_READY_MASK (0x1U) +#define PUF_SRAM_INT_ENABLE_READY_SHIFT (0U) +/*! READY - READY Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_INT_ENABLE_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_READY_SHIFT)) & PUF_SRAM_INT_ENABLE_READY_MASK) + +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT (1U) +/*! SRAM_APB_ERR - APB_ERR Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define PUF_SRAM_INT_ENABLE_SRAM_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_SHIFT)) & PUF_SRAM_INT_ENABLE_SRAM_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_CLR_STATUS - Interrupt Status Clear */ +/*! @{ */ + +#define PUF_SRAM_INT_CLR_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_CLR_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status clear */ +#define PUF_SRAM_INT_CLR_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_READY_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_READY_MASK) + +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Clear + * 0b0..No effect + * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware + */ +#define PUF_SRAM_INT_CLR_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_CLR_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_CLR_STATUS_APB_ERR_MASK) +/*! @} */ + +/*! @name SRAM_INT_SET_STATUS - Interrupt Status set */ +/*! @{ */ + +#define PUF_SRAM_INT_SET_STATUS_READY_MASK (0x1U) +#define PUF_SRAM_INT_SET_STATUS_READY_SHIFT (0U) +/*! READY - READY Interrupt Status set */ +#define PUF_SRAM_INT_SET_STATUS_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_READY_SHIFT)) & PUF_SRAM_INT_SET_STATUS_READY_MASK) + +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK (0x2U) +#define PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT (1U) +/*! APB_ERR - APB_ERR Interrupt Status Set + * 0b0..No effect + * 0b1..Clears the APB_ERR bit field in register INT_STATUS. Automatically reset by the Hardware + */ +#define PUF_SRAM_INT_SET_STATUS_APB_ERR(x) (((uint32_t)(((uint32_t)(x)) << PUF_SRAM_INT_SET_STATUS_APB_ERR_SHIFT)) & PUF_SRAM_INT_SET_STATUS_APB_ERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PUF_Register_Masks */ + + +/* PUF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PUF base address */ + #define PUF_BASE (0x5002C000u) + /** Peripheral PUF base address */ + #define PUF_BASE_NS (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF base pointer */ + #define PUF_NS ((PUF_Type *)PUF_BASE_NS) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x5002D000u) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE_NS (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1_NS ((PUF_Type *)PUF_ALIAS1_BASE_NS) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x5002E000u) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE_NS (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2_NS ((PUF_Type *)PUF_ALIAS2_BASE_NS) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x5002F000u) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE_NS (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3_NS ((PUF_Type *)PUF_ALIAS3_BASE_NS) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS_NS { PUF_BASE_NS, PUF_ALIAS1_BASE_NS, PUF_ALIAS2_BASE_NS, PUF_ALIAS3_BASE_NS } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS_NS { PUF_NS, PUF_ALIAS1_NS, PUF_ALIAS2_NS, PUF_ALIAS3_NS } +#else + /** Peripheral PUF base address */ + #define PUF_BASE (0x4002C000u) + /** Peripheral PUF base pointer */ + #define PUF ((PUF_Type *)PUF_BASE) + /** Peripheral PUF_ALIAS1 base address */ + #define PUF_ALIAS1_BASE (0x4002D000u) + /** Peripheral PUF_ALIAS1 base pointer */ + #define PUF_ALIAS1 ((PUF_Type *)PUF_ALIAS1_BASE) + /** Peripheral PUF_ALIAS2 base address */ + #define PUF_ALIAS2_BASE (0x4002E000u) + /** Peripheral PUF_ALIAS2 base pointer */ + #define PUF_ALIAS2 ((PUF_Type *)PUF_ALIAS2_BASE) + /** Peripheral PUF_ALIAS3 base address */ + #define PUF_ALIAS3_BASE (0x4002F000u) + /** Peripheral PUF_ALIAS3 base pointer */ + #define PUF_ALIAS3 ((PUF_Type *)PUF_ALIAS3_BASE) + /** Array initializer of PUF peripheral base addresses */ + #define PUF_BASE_ADDRS { PUF_BASE, PUF_ALIAS1_BASE, PUF_ALIAS2_BASE, PUF_ALIAS3_BASE } + /** Array initializer of PUF peripheral base pointers */ + #define PUF_BASE_PTRS { PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group PUF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_1[2]; + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-3] */ + __IO uint16_t CAPTFILTA; /**< Capture PWM_A Input Filter Register, array offset: 0x5A, array step: 0x60 */ + __IO uint16_t CAPTFILTB; /**< Capture PWM_B Input Filter Register, array offset: 0x5C, array step: 0x60 */ + __IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */ + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ + +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ + +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it forces the clock to logic 0. + * 0b11..Reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it forces the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - Force Select + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - Force Enable + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload + * occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWM_X Double Switching Enable + * 0b0..PWM_X double pulse disabled. + * 0b1..PWM_X double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B + * 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses. + * 0b1..DBLPWM is split to PWM_A and PWM_B. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..Prescaler 1 + * 0b001..Prescaler 2 + * 0b010..Prescaler 4 + * 0b011..Prescaler 8 + * 0b100..Prescaler 16 + * 0b101..Prescaler 32 + * 0b110..Prescaler 64 + * 0b111..Prescaler 128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A + * output that is high at the end of a period maintains this state until a match with VAL3 clears the output + * in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ + +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value 0 */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ + +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +/*! FRACVAL1 - Fractional Value 1 */ +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ + +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value 1 */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ + +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +/*! FRACVAL2 - Fractional Value 2 */ +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ + +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value 2 */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ + +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +/*! FRACVAL3 - Fractional Value 3 */ +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ + +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value 3 */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ + +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +/*! FRACVAL4 - Fractional Value 4 */ +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ + +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value 4 */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ + +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +/*! FRACVAL5 - Fractional Value 5 */ +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ + +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value 5 */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ + +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) + +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) + +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) + +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +/*! TEST - Test Status Bit */ +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ + +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ + +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +/*! CFB0 - Capture Flag B0 */ +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) + +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +/*! CFB1 - Capture Flag B1 */ +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) + +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +/*! CFA0 - Capture Flag A0 */ +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) + +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +/*! CFA1 - Capture Flag A1 */ +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) + +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) + +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) + +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) + +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1] + * 0b1..Interrupt request enabled for STS[CFA1] + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) + +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ + +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +/*! CB0DE - Capture B0 FIFO DMA Enable */ +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) + +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +/*! CB1DE - Capture B1 FIFO DMA Enable */ +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) + +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +/*! CA0DE - Capture A0 FIFO DMA Enable */ +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) + +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +/*! CA1DE - Capture A1 FIFO DMA Enable */ +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) + +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which + * watermark(s) the DMA request is sensitive. + * 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..Enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ + +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. + * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. + * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. + * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. + * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. + * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger Frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Mux Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. + * 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Mux Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. + * 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0 */ +/*! @{ */ + +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) + +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) + +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (1U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ + +#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - Deadtime Count Register 0 */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ + +#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - Deadtime Count Register 1 */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ + +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) + +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) + +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) + +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) + +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) + +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) + +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +/*! CFAWM - Capture A FIFOs Water Mark */ +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) + +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +/*! CA0CNT - Capture A0 FIFO Word Count */ +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) + +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +/*! CA1CNT - Capture A1 FIFO Word Count */ +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ + +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +/*! EDGCMPA - Edge Compare A */ +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) + +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +/*! EDGCNTA - Edge Counter A */ +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ + +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) + +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) + +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) + +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) + +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) + +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) + +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +/*! CFBWM - Capture B FIFOs Water Mark */ +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) + +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +/*! CB0CNT - Capture B0 FIFO Word Count */ +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) + +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +/*! CB1CNT - Capture B1 FIFO Word Count */ +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ + +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +/*! EDGCMPB - Edge Compare B */ +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) + +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +/*! EDGCNTB - Edge Counter B */ +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ + +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ + +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ + +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - Capture Value 0 */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - Capture Value 0 Cycle */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ + +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - Capture Value 1 */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - Capture Value 1 Cycle */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ + +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +/*! CAPTVAL2 - Capture Value 2 */ +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +/*! CVAL2CYC - Capture Value 2 Cycle */ +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ + +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +/*! CAPTVAL3 - Capture Value 3 */ +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +/*! CVAL3CYC - Capture Value 3 Cycle */ +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ + +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +/*! CAPTVAL4 - Capture Value 4 */ +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +/*! CVAL4CYC - Capture Value 4 Cycle */ +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ + +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +/*! CAPTVAL5 - Capture Value 5 */ +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +/*! CVAL5CYC - Capture Value 5 Cycle */ +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name PHASEDLY - Phase Delay Register */ +/*! @{ */ + +#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) +#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) +/*! PHASEDLY - Initial Count Register Bits */ +#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) +/*! @} */ + +/* The count of PWM_PHASEDLY */ +#define PWM_PHASEDLY_COUNT (4U) + +/*! @name CAPTFILTA - Capture PWM_A Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTA_CAPTA_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT (0U) +/*! CAPTA_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTA_CAPTA_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_PER_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_PER_MASK) + +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT (8U) +/*! CAPTA_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTA_CAPTA_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTA_CAPTA_FILT_CNT_SHIFT)) & PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTA */ +#define PWM_CAPTFILTA_COUNT (4U) + +/*! @name CAPTFILTB - Capture PWM_B Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTB_CAPTB_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT (0U) +/*! CAPTB_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTB_CAPTB_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_PER_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_PER_MASK) + +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT (8U) +/*! CAPTB_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTB_CAPTB_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTB_CAPTB_FILT_CNT_SHIFT)) & PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTB */ +#define PWM_CAPTFILTB_COUNT (4U) + +/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) +/*! CAPTX_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) + +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTX */ +#define PWM_CAPTFILTX_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ + +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ + +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) + +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ + +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) + +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) + +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ + +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] used by the deadtime logic. + * 0b11..PWM0_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] used by the deadtime logic. + * 0b11..PWM1_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] used by the deadtime logic. + * 0b11..PWM2_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) + +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) + +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] used by the deadtime logic. + * 0b11..PWM3_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ + +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM counter is stopped, but PWM outputs hold the current state. + * 0b0001..PWM counter is started in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ + +#define PWM_MCTRL2_WRPROT_MASK (0xCU) +#define PWM_MCTRL2_WRPROT_SHIFT (2U) +/*! WRPROT - Write protect + * 0b00..Write protection off (default). + * 0b01..Write protection on. + * 0b10..Write protection off and locked until chip reset. + * 0b11..Write protection on and locked until chip reset. + */ +#define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK) + +#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U) +#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U) +/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig + * 0b00..Stretch count is zero, no stretch. + * 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. + * 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. + * 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. + */ +#define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ + +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard + * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be + * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input + * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in + * DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and + * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If + * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled + * by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without + * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition + * cannot be cleared. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ + +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ + +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ + +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ + +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x500CE000u) + /** Peripheral PWM0 base address */ + #define PWM0_BASE_NS (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM0 base pointer */ + #define PWM0_NS ((PWM_Type *)PWM0_BASE_NS) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x500D0000u) + /** Peripheral PWM1 base address */ + #define PWM1_BASE_NS (0x400D0000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Peripheral PWM1 base pointer */ + #define PWM1_NS ((PWM_Type *)PWM1_BASE_NS) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS_NS { PWM0_BASE_NS, PWM1_BASE_NS } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS_NS { PWM0_NS, PWM1_NS } +#else + /** Peripheral PWM0 base address */ + #define PWM0_BASE (0x400CE000u) + /** Peripheral PWM0 base pointer */ + #define PWM0 ((PWM_Type *)PWM0_BASE) + /** Peripheral PWM1 base address */ + #define PWM1_BASE (0x400D0000u) + /** Peripheral PWM1 base pointer */ + #define PWM1 ((PWM_Type *)PWM1_BASE) + /** Array initializer of PWM peripheral base addresses */ + #define PWM_BASE_ADDRS { PWM0_BASE, PWM1_BASE } + /** Array initializer of PWM peripheral base pointers */ + #define PWM_BASE_PTRS { PWM0, PWM1 } +#endif +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn, FLEXPWM0_SUBMODULE3_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn, FLEXPWM1_SUBMODULE3_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Peripheral_Access_Layer QDC Peripheral Access Layer + * @{ + */ + +/** QDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor, offset: 0x1A */ + __IO uint16_t TST; /**< Test, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare, offset: 0x26 */ + __I uint16_t LASTEDGE; /**< Last Edge Time, offset: 0x28 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold, offset: 0x2A */ + __I uint16_t POSDPER; /**< Position Difference Period Counter, offset: 0x2C */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer, offset: 0x2E */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold, offset: 0x30 */ + __IO uint16_t CTRL3; /**< Control 3, offset: 0x32 */ +} QDC_Type; + +/* ---------------------------------------------------------------------------- + -- QDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QDC_Register_Masks QDC Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define QDC_CTRL_CMPIE_MASK (0x1U) +#define QDC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIE_SHIFT)) & QDC_CTRL_CMPIE_MASK) + +#define QDC_CTRL_CMPIRQ_MASK (0x2U) +#define QDC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define QDC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_CMPIRQ_SHIFT)) & QDC_CTRL_CMPIRQ_MASK) + +#define QDC_CTRL_WDE_MASK (0x4U) +#define QDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_WDE_SHIFT)) & QDC_CTRL_WDE_MASK) + +#define QDC_CTRL_DIE_MASK (0x8U) +#define QDC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIE_SHIFT)) & QDC_CTRL_DIE_MASK) + +#define QDC_CTRL_DIRQ_MASK (0x10U) +#define QDC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_DIRQ_SHIFT)) & QDC_CTRL_DIRQ_MASK) + +#define QDC_CTRL_XNE_MASK (0x20U) +#define QDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive and Negative Edge of INDEX Pulse + * 0b0..Use positive edge + * 0b1..Use negative edge + */ +#define QDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XNE_SHIFT)) & QDC_CTRL_XNE_MASK) + +#define QDC_CTRL_XIP_MASK (0x40U) +#define QDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..Does not initialize + * 0b1..Initializes + */ +#define QDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIP_SHIFT)) & QDC_CTRL_XIP_MASK) + +#define QDC_CTRL_XIE_MASK (0x80U) +#define QDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIE_SHIFT)) & QDC_CTRL_XIE_MASK) + +#define QDC_CTRL_XIRQ_MASK (0x100U) +#define QDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_XIRQ_SHIFT)) & QDC_CTRL_XIRQ_MASK) + +#define QDC_CTRL_PH1_MASK (0x200U) +#define QDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Uses the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Bypasses the quadrature decoder. A positive transition of the PHASEA input generates a count signal. + * PHASEB input and CTRL[REV] controls the counter direction. If the value of CTRL[REV] and PHASEB are identical; + * then count is up. If the value of CTRL[REV] and PHASEB is different, then count is down. + */ +#define QDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_PH1_SHIFT)) & QDC_CTRL_PH1_MASK) + +#define QDC_CTRL_REV_MASK (0x400U) +#define QDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Counts normally + * 0b1..Counts in the reverse direction + */ +#define QDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_REV_SHIFT)) & QDC_CTRL_REV_MASK) + +#define QDC_CTRL_SWIP_MASK (0x800U) +#define QDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define QDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_SWIP_SHIFT)) & QDC_CTRL_SWIP_MASK) + +#define QDC_CTRL_HNE_MASK (0x1000U) +#define QDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define QDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HNE_SHIFT)) & QDC_CTRL_HNE_MASK) + +#define QDC_CTRL_HIP_MASK (0x2000U) +#define QDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define QDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIP_SHIFT)) & QDC_CTRL_HIP_MASK) + +#define QDC_CTRL_HIE_MASK (0x4000U) +#define QDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIE_SHIFT)) & QDC_CTRL_HIE_MASK) + +#define QDC_CTRL_HIRQ_MASK (0x8000U) +#define QDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..Not occurred + * 0b1..Occurred + */ +#define QDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL_HIRQ_SHIFT)) & QDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter */ +/*! @{ */ + +#define QDC_FILT_FILT_PER_MASK (0xFFU) +#define QDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define QDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PER_SHIFT)) & QDC_FILT_FILT_PER_MASK) + +#define QDC_FILT_FILT_CNT_MASK (0x700U) +#define QDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define QDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_CNT_SHIFT)) & QDC_FILT_FILT_CNT_MASK) + +#define QDC_FILT_FILT_PRSC_MASK (0xE000U) +#define QDC_FILT_FILT_PRSC_SHIFT (13U) +/*! FILT_PRSC - Prescaler Divide IPBus Clock to FILT Clock */ +#define QDC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_FILT_FILT_PRSC_SHIFT)) & QDC_FILT_FILT_PRSC_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout */ +/*! @{ */ + +#define QDC_WTR_WDOG_MASK (0xFFFFU) +#define QDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define QDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << QDC_WTR_WDOG_SHIFT)) & QDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter */ +/*! @{ */ + +#define QDC_POSD_POSD_MASK (0xFFFFU) +#define QDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define QDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSD_POSD_SHIFT)) & QDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold */ +/*! @{ */ + +#define QDC_POSDH_POSDH_MASK (0xFFFFU) +#define QDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define QDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDH_POSDH_SHIFT)) & QDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter */ +/*! @{ */ + +#define QDC_REV_REV_MASK (0xFFFFU) +#define QDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define QDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << QDC_REV_REV_SHIFT)) & QDC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold */ +/*! @{ */ + +#define QDC_REVH_REVH_MASK (0xFFFFU) +#define QDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define QDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << QDC_REVH_REVH_SHIFT)) & QDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter */ +/*! @{ */ + +#define QDC_UPOS_POS_MASK (0xFFFFU) +#define QDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOS_POS_SHIFT)) & QDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter */ +/*! @{ */ + +#define QDC_LPOS_POS_MASK (0xFFFFU) +#define QDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define QDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOS_POS_SHIFT)) & QDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold */ +/*! @{ */ + +#define QDC_UPOSH_POSH_MASK (0xFFFFU) +#define QDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_UPOSH_POSH_SHIFT)) & QDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold */ +/*! @{ */ + +#define QDC_LPOSH_POSH_MASK (0xFFFFU) +#define QDC_LPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define QDC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LPOSH_POSH_SHIFT)) & QDC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization */ +/*! @{ */ + +#define QDC_UINIT_INIT_MASK (0xFFFFU) +#define QDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_UINIT_INIT_SHIFT)) & QDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization */ +/*! @{ */ + +#define QDC_LINIT_INIT_MASK (0xFFFFU) +#define QDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define QDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << QDC_LINIT_INIT_SHIFT)) & QDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor */ +/*! @{ */ + +#define QDC_IMR_HOME_MASK (0x1U) +#define QDC_IMR_HOME_SHIFT (0U) +/*! HOME - HOME */ +#define QDC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_HOME_SHIFT)) & QDC_IMR_HOME_MASK) + +#define QDC_IMR_INDEX_MASK (0x2U) +#define QDC_IMR_INDEX_SHIFT (1U) +/*! INDEX - INDEX */ +#define QDC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_INDEX_SHIFT)) & QDC_IMR_INDEX_MASK) + +#define QDC_IMR_PHB_MASK (0x4U) +#define QDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define QDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHB_SHIFT)) & QDC_IMR_PHB_MASK) + +#define QDC_IMR_PHA_MASK (0x8U) +#define QDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define QDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_PHA_SHIFT)) & QDC_IMR_PHA_MASK) + +#define QDC_IMR_FHOM_MASK (0x10U) +#define QDC_IMR_FHOM_SHIFT (4U) +/*! FHOM - FHOM */ +#define QDC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FHOM_SHIFT)) & QDC_IMR_FHOM_MASK) + +#define QDC_IMR_FIND_MASK (0x20U) +#define QDC_IMR_FIND_SHIFT (5U) +/*! FIND - FIND */ +#define QDC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FIND_SHIFT)) & QDC_IMR_FIND_MASK) + +#define QDC_IMR_FPHB_MASK (0x40U) +#define QDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - FPHB */ +#define QDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHB_SHIFT)) & QDC_IMR_FPHB_MASK) + +#define QDC_IMR_FPHA_MASK (0x80U) +#define QDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - FPHA */ +#define QDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << QDC_IMR_FPHA_SHIFT)) & QDC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test */ +/*! @{ */ + +#define QDC_TST_TEST_COUNT_MASK (0xFFU) +#define QDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define QDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_COUNT_SHIFT)) & QDC_TST_TEST_COUNT_MASK) + +#define QDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define QDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define QDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEST_PERIOD_SHIFT)) & QDC_TST_TEST_PERIOD_MASK) + +#define QDC_TST_QDN_MASK (0x2000U) +#define QDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Positive quadrature decoder signal + * 0b1..Negative quadrature decoder signal + */ +#define QDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_QDN_SHIFT)) & QDC_TST_QDN_MASK) + +#define QDC_TST_TCE_MASK (0x4000U) +#define QDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TCE_SHIFT)) & QDC_TST_TCE_MASK) + +#define QDC_TST_TEN_MASK (0x8000U) +#define QDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_TST_TEN_SHIFT)) & QDC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define QDC_CTRL2_UPDHLD_MASK (0x1U) +#define QDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDHLD_SHIFT)) & QDC_CTRL2_UPDHLD_MASK) + +#define QDC_CTRL2_UPDPOS_MASK (0x2U) +#define QDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action + * 0b1..Clear + */ +#define QDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_UPDPOS_SHIFT)) & QDC_CTRL2_UPDPOS_MASK) + +#define QDC_CTRL2_MOD_MASK (0x4U) +#define QDC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_MOD_SHIFT)) & QDC_CTRL2_MOD_MASK) + +#define QDC_CTRL2_DIR_MASK (0x8U) +#define QDC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Down direction + * 0b1..Up direction + */ +#define QDC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_DIR_SHIFT)) & QDC_CTRL2_DIR_MASK) + +#define QDC_CTRL2_RUIE_MASK (0x10U) +#define QDC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIE_SHIFT)) & QDC_CTRL2_RUIE_MASK) + +#define QDC_CTRL2_RUIRQ_MASK (0x20U) +#define QDC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define QDC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_RUIRQ_SHIFT)) & QDC_CTRL2_RUIRQ_MASK) + +#define QDC_CTRL2_ROIE_MASK (0x40U) +#define QDC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIE_SHIFT)) & QDC_CTRL2_ROIE_MASK) + +#define QDC_CTRL2_ROIRQ_MASK (0x80U) +#define QDC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..Did not occur + * 0b1..Occurred + */ +#define QDC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_ROIRQ_SHIFT)) & QDC_CTRL2_ROIRQ_MASK) + +#define QDC_CTRL2_REVMOD_MASK (0x100U) +#define QDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse + * 0b1..Use modulus counting roll-over or roll-under + */ +#define QDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_REVMOD_SHIFT)) & QDC_CTRL2_REVMOD_MASK) + +#define QDC_CTRL2_OUTCTL_MASK (0x200U) +#define QDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP ) + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read + */ +#define QDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_OUTCTL_SHIFT)) & QDC_CTRL2_OUTCTL_MASK) + +#define QDC_CTRL2_SABIE_MASK (0x400U) +#define QDC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIE_SHIFT)) & QDC_CTRL2_SABIE_MASK) + +#define QDC_CTRL2_SABIRQ_MASK (0x800U) +#define QDC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change has occurred + * 0b1..A simultaneous change has occurred + */ +#define QDC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_SABIRQ_SHIFT)) & QDC_CTRL2_SABIRQ_MASK) + +#define QDC_CTRL2_INITPOS_MASK (0x1000U) +#define QDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initialize Position Registers + * 0b0..Don't initialize position counter + * 0b1..Initialize position counter + */ +#define QDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_INITPOS_SHIFT)) & QDC_CTRL2_INITPOS_MASK) + +#define QDC_CTRL2_EMIP_MASK (0x2000U) +#define QDC_CTRL2_EMIP_SHIFT (13U) +/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark + * 0b0..Disable + * 0b1..Enable + */ +#define QDC_CTRL2_EMIP(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL2_EMIP_SHIFT)) & QDC_CTRL2_EMIP_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus */ +/*! @{ */ + +#define QDC_UMOD_MOD_MASK (0xFFFFU) +#define QDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_UMOD_MOD_SHIFT)) & QDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus */ +/*! @{ */ + +#define QDC_LMOD_MOD_MASK (0xFFFFU) +#define QDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define QDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << QDC_LMOD_MOD_SHIFT)) & QDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare */ +/*! @{ */ + +#define QDC_UCOMP_COMP_MASK (0xFFFFU) +#define QDC_UCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_UCOMP_COMP_SHIFT)) & QDC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare */ +/*! @{ */ + +#define QDC_LCOMP_COMP_MASK (0xFFFFU) +#define QDC_LCOMP_COMP_SHIFT (0U) +/*! COMP - COMP */ +#define QDC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << QDC_LCOMP_COMP_SHIFT)) & QDC_LCOMP_COMP_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time */ +/*! @{ */ + +#define QDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define QDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define QDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGE_LASTEDGE_SHIFT)) & QDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold */ +/*! @{ */ + +#define QDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define QDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define QDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << QDC_LASTEDGEH_LASTEDGEH_SHIFT)) & QDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter */ +/*! @{ */ + +#define QDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define QDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define QDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPER_POSDPER_SHIFT)) & QDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer */ +/*! @{ */ + +#define QDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define QDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define QDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERBFR_POSDPERBFR_SHIFT)) & QDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold */ +/*! @{ */ + +#define QDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define QDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define QDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << QDC_POSDPERH_POSDPERH_SHIFT)) & QDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name CTRL3 - Control 3 */ +/*! @{ */ + +#define QDC_CTRL3_PMEN_MASK (0x1U) +#define QDC_CTRL3_PMEN_SHIFT (0U) +/*! PMEN - Period Measurement Function Enable + * 0b0..Not used + * 0b1..Used + */ +#define QDC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PMEN_SHIFT)) & QDC_CTRL3_PMEN_MASK) + +#define QDC_CTRL3_PRSC_MASK (0xF0U) +#define QDC_CTRL3_PRSC_SHIFT (4U) +/*! PRSC - Prescaler */ +#define QDC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << QDC_CTRL3_PRSC_SHIFT)) & QDC_CTRL3_PRSC_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group QDC_Register_Masks */ + + +/* QDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x500CF000u) + /** Peripheral QDC0 base address */ + #define QDC0_BASE_NS (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC0 base pointer */ + #define QDC0_NS ((QDC_Type *)QDC0_BASE_NS) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x500D1000u) + /** Peripheral QDC1 base address */ + #define QDC1_BASE_NS (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Peripheral QDC1 base pointer */ + #define QDC1_NS ((QDC_Type *)QDC1_BASE_NS) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS_NS { QDC0_BASE_NS, QDC1_BASE_NS } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS_NS { QDC0_NS, QDC1_NS } +#else + /** Peripheral QDC0 base address */ + #define QDC0_BASE (0x400CF000u) + /** Peripheral QDC0 base pointer */ + #define QDC0 ((QDC_Type *)QDC0_BASE) + /** Peripheral QDC1 base address */ + #define QDC1_BASE (0x400D1000u) + /** Peripheral QDC1 base pointer */ + #define QDC1 ((QDC_Type *)QDC1_BASE) + /** Array initializer of QDC peripheral base addresses */ + #define QDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } + /** Array initializer of QDC peripheral base pointers */ + #define QDC_BASE_PTRS { QDC0, QDC1 } +#endif +/** Interrupt vectors for the QDC peripheral type */ +#define QDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } +#define QDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } +#define QDC_WDOG_IRQS { QDC0_WDG_SAB_IRQn, QDC1_WDG_SAB_IRQn } +#define QDC_INDEX_IRQS { QDC0_IDX_IRQn, QDC1_IDX_IRQn } + +/*! + * @} + */ /* end of group QDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint16_t YEARMON; /**< Year and Month Counters, offset: 0x0 */ + __IO uint16_t DAYS; /**< Days and Day-of-Week Counters, offset: 0x2 */ + __IO uint16_t HOURMIN; /**< Hours and Minutes Counters, offset: 0x4 */ + __IO uint16_t SECONDS; /**< Seconds Counters, offset: 0x6 */ + __IO uint16_t ALM_YEARMON; /**< Year and Months Alarm, offset: 0x8 */ + __IO uint16_t ALM_DAYS; /**< Days Alarm, offset: 0xA */ + __IO uint16_t ALM_HOURMIN; /**< Hours and Minutes Alarm, offset: 0xC */ + __IO uint16_t ALM_SECONDS; /**< Seconds Alarm, offset: 0xE */ + __IO uint16_t CTRL; /**< Control, offset: 0x10 */ + __IO uint16_t STATUS; /**< Status, offset: 0x12 */ + __IO uint16_t ISR; /**< Interrupt Status, offset: 0x14 */ + __IO uint16_t IER; /**< Interrupt Enable, offset: 0x16 */ + uint8_t RESERVED_0[4]; + __I uint16_t RTC_TEST2; /**< Sub Second Counter, offset: 0x1C */ + uint8_t RESERVED_1[4]; + __IO uint16_t DST_HOUR; /**< Daylight Saving Hour, offset: 0x22 */ + __IO uint16_t DST_MONTH; /**< Daylight Saving Month, offset: 0x24 */ + __IO uint16_t DST_DAY; /**< Daylight Saving Day, offset: 0x26 */ + __IO uint16_t COMPEN; /**< Compensation, offset: 0x28 */ + uint8_t RESERVED_2[2006]; + __IO uint32_t SUBSECOND_CTRL; /**< Subsecond Control, offset: 0x800 */ + __I uint32_t SUBSECOND_CNT; /**< Subsecond Counter, offset: 0x804 */ + uint8_t RESERVED_3[1016]; + __IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0xC00 */ + uint8_t RESERVED_4[8]; + __IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC0C */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name YEARMON - Year and Month Counters */ +/*! @{ */ + +#define RTC_YEARMON_MON_CNT_MASK (0xFU) +#define RTC_YEARMON_MON_CNT_SHIFT (0U) +/*! MON_CNT - Month Counter + * 0b0000, 0b1101, 0b1110, 0b1111..Illegal Value + * 0b0001..January + * 0b0010..February + * 0b0011..March + * 0b0100..April + * 0b0101..May + * 0b0110..June + * 0b0111..July + * 0b1000..August + * 0b1001..September + * 0b1010..October + * 0b1011..November + * 0b1100..December + */ +#define RTC_YEARMON_MON_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK) + +#define RTC_YEARMON_YROFST_MASK (0xFF00U) +#define RTC_YEARMON_YROFST_SHIFT (8U) +/*! YROFST - Year Offset Count Value */ +#define RTC_YEARMON_YROFST(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK) +/*! @} */ + +/*! @name DAYS - Days and Day-of-Week Counters */ +/*! @{ */ + +#define RTC_DAYS_DAY_CNT_MASK (0x1FU) +#define RTC_DAYS_DAY_CNT_SHIFT (0U) +/*! DAY_CNT - Days Counter Value */ +#define RTC_DAYS_DAY_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK) + +#define RTC_DAYS_DOW_MASK (0x700U) +#define RTC_DAYS_DOW_SHIFT (8U) +/*! DOW - Day of Week Counter Value + * 0b000..Sunday + * 0b001..Monday + * 0b010..Tuesday + * 0b011..Wednesday + * 0b100..Thursday + * 0b101..Friday + * 0b110..Saturday + * 0b111.. + */ +#define RTC_DAYS_DOW(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK) +/*! @} */ + +/*! @name HOURMIN - Hours and Minutes Counters */ +/*! @{ */ + +#define RTC_HOURMIN_MIN_CNT_MASK (0x3FU) +#define RTC_HOURMIN_MIN_CNT_SHIFT (0U) +/*! MIN_CNT - Minutes Counter Value */ +#define RTC_HOURMIN_MIN_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK) + +#define RTC_HOURMIN_HOUR_CNT_MASK (0x1F00U) +#define RTC_HOURMIN_HOUR_CNT_SHIFT (8U) +/*! HOUR_CNT - Hours Counter Value */ +#define RTC_HOURMIN_HOUR_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK) +/*! @} */ + +/*! @name SECONDS - Seconds Counters */ +/*! @{ */ + +#define RTC_SECONDS_SEC_CNT_MASK (0x3FU) +#define RTC_SECONDS_SEC_CNT_SHIFT (0U) +/*! SEC_CNT - Seconds Counter Value */ +#define RTC_SECONDS_SEC_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK) +/*! @} */ + +/*! @name ALM_YEARMON - Year and Months Alarm */ +/*! @{ */ + +#define RTC_ALM_YEARMON_ALM_MON_MASK (0xFU) +#define RTC_ALM_YEARMON_ALM_MON_SHIFT (0U) +/*! ALM_MON - Months Value for Alarm */ +#define RTC_ALM_YEARMON_ALM_MON(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK) + +#define RTC_ALM_YEARMON_ALM_YEAR_MASK (0xFF00U) +#define RTC_ALM_YEARMON_ALM_YEAR_SHIFT (8U) +/*! ALM_YEAR - Year Value for Alarm */ +#define RTC_ALM_YEARMON_ALM_YEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK) +/*! @} */ + +/*! @name ALM_DAYS - Days Alarm */ +/*! @{ */ + +#define RTC_ALM_DAYS_ALM_DAY_MASK (0x1FU) +#define RTC_ALM_DAYS_ALM_DAY_SHIFT (0U) +/*! ALM_DAY - Days Value for Alarm */ +#define RTC_ALM_DAYS_ALM_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK) +/*! @} */ + +/*! @name ALM_HOURMIN - Hours and Minutes Alarm */ +/*! @{ */ + +#define RTC_ALM_HOURMIN_ALM_MIN_MASK (0x3FU) +#define RTC_ALM_HOURMIN_ALM_MIN_SHIFT (0U) +/*! ALM_MIN - Minutes Value for Alarm */ +#define RTC_ALM_HOURMIN_ALM_MIN(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK) + +#define RTC_ALM_HOURMIN_ALM_HOUR_MASK (0x1F00U) +#define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT (8U) +/*! ALM_HOUR - Hours Value for Alarm */ +#define RTC_ALM_HOURMIN_ALM_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK) +/*! @} */ + +/*! @name ALM_SECONDS - Seconds Alarm */ +/*! @{ */ + +#define RTC_ALM_SECONDS_ALM_SEC_MASK (0x3FU) +#define RTC_ALM_SECONDS_ALM_SEC_SHIFT (0U) +/*! ALM_SEC - Seconds Alarm Value */ +#define RTC_ALM_SECONDS_ALM_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK) + +#define RTC_ALM_SECONDS_DEC_SEC_MASK (0x100U) +#define RTC_ALM_SECONDS_DEC_SEC_SHIFT (8U) +/*! DEC_SEC - Decrement Seconds Counter by 1. */ +#define RTC_ALM_SECONDS_DEC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK) + +#define RTC_ALM_SECONDS_INC_SEC_MASK (0x200U) +#define RTC_ALM_SECONDS_INC_SEC_SHIFT (9U) +/*! INC_SEC - Increment Seconds Counter by 1. */ +#define RTC_ALM_SECONDS_INC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define RTC_CTRL_FINEEN_MASK (0x1U) +#define RTC_CTRL_FINEEN_SHIFT (0U) +/*! FINEEN - Fine Compensation Enable + * 0b1..Fine compensation is enabled. + * 0b0..Fine compensation is disabled + */ +#define RTC_CTRL_FINEEN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK) + +#define RTC_CTRL_COMP_EN_MASK (0x2U) +#define RTC_CTRL_COMP_EN_SHIFT (1U) +/*! COMP_EN - Compensation Enable + * 0b0..Coarse compensation is disabled. + * 0b1..Coarse compensation is enabled. + */ +#define RTC_CTRL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK) + +#define RTC_CTRL_ALM_MATCH_MASK (0xCU) +#define RTC_CTRL_ALM_MATCH_SHIFT (2U) +/*! ALM_MATCH - Alarm Match + * 0b00..Only seconds, minutes, and hours matched. + * 0b01..Only seconds, minutes, hours, and days matched. + * 0b10..Only seconds, minutes, hours, days, and months matched. + * 0b11..Only seconds, minutes, hours, days, months, and year (offset) matched. + */ +#define RTC_CTRL_ALM_MATCH(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK) + +#define RTC_CTRL_DST_EN_MASK (0x40U) +#define RTC_CTRL_DST_EN_SHIFT (6U) +/*! DST_EN - Daylight Saving Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define RTC_CTRL_DST_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK) + +#define RTC_CTRL_SWR_MASK (0x100U) +#define RTC_CTRL_SWR_SHIFT (8U) +/*! SWR - Software Reset + * 0b0..Software Reset cleared + * 0b1..Software Reset asserted + */ +#define RTC_CTRL_SWR(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK) + +#define RTC_CTRL_CLK_SEL_MASK (0x200U) +#define RTC_CTRL_CLK_SEL_SHIFT (9U) +/*! CLK_SEL - RTC Clock Select + * 0b0..16.384 kHz clock is selected + * 0b1..32.768 kHz clock is selected + */ +#define RTC_CTRL_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLK_SEL_SHIFT)) & RTC_CTRL_CLK_SEL_MASK) + +#define RTC_CTRL_CLKO_DIS_MASK (0x400U) +#define RTC_CTRL_CLKO_DIS_SHIFT (10U) +/*! CLKO_DIS - Clock Output Disable + * 0b0..The selected clock is output to other peripherals. + * 0b1..The selected clock is not output to other peripherals. + */ +#define RTC_CTRL_CLKO_DIS(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKO_DIS_SHIFT)) & RTC_CTRL_CLKO_DIS_MASK) + +#define RTC_CTRL_CLKOUT_MASK (0x6000U) +#define RTC_CTRL_CLKOUT_SHIFT (13U) +/*! CLKOUT - RTC Clock Output Selection + * 0b00..No output clock + * 0b01..Fine 1 Hz clock with both precise edges + * 0b10..32.768 or 16.384 kHz clock + * 0b11..Coarse 1 Hz clock with both precise edges + */ +#define RTC_CTRL_CLKOUT(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define RTC_STATUS_INVAL_BIT_MASK (0x1U) +#define RTC_STATUS_INVAL_BIT_SHIFT (0U) +/*! INVAL_BIT - Invalidate CPU Read/Write Access + * 0b0..Time and date counters can be read or written. Time and date is valid. + * 0b1..Time and date counter values are changing or time and date is invalid and cannot be read or written. + */ +#define RTC_STATUS_INVAL_BIT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK) + +#define RTC_STATUS_WRITE_PROT_EN_MASK (0x2U) +#define RTC_STATUS_WRITE_PROT_EN_SHIFT (1U) +/*! WRITE_PROT_EN - Write Protect Enable Status + * 0b0..Registers are unlocked and can be accessed. + * 0b1..Registers are locked and in read-only mode. + */ +#define RTC_STATUS_WRITE_PROT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK) + +#define RTC_STATUS_CMP_INT_MASK (0x20U) +#define RTC_STATUS_CMP_INT_SHIFT (5U) +/*! CMP_INT - Compensation Interval */ +#define RTC_STATUS_CMP_INT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK) + +#define RTC_STATUS_WE_MASK (0xC0U) +#define RTC_STATUS_WE_SHIFT (6U) +/*! WE - Write Enable + * 0b10..Enable Write Protection - Registers are locked. + */ +#define RTC_STATUS_WE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK) + +#define RTC_STATUS_BUS_ERR_MASK (0x100U) +#define RTC_STATUS_BUS_ERR_SHIFT (8U) +/*! BUS_ERR - Bus Error + * 0b0..Read and write accesses are normal. + * 0b1..Read or write accesses occurred when STATUS[INVAL_BIT] was asserted. + */ +#define RTC_STATUS_BUS_ERR(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK) + +#define RTC_STATUS_CMP_DONE_MASK (0x800U) +#define RTC_STATUS_CMP_DONE_SHIFT (11U) +/*! CMP_DONE - Compensation Done + * 0b0..Compensation busy or not enabled + * 0b1..Compensation completed + */ +#define RTC_STATUS_CMP_DONE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK) +/*! @} */ + +/*! @name ISR - Interrupt Status */ +/*! @{ */ + +#define RTC_ISR_ALM_IS_MASK (0x4U) +#define RTC_ISR_ALM_IS_SHIFT (2U) +/*! ALM_IS - Alarm Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_ALM_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK) + +#define RTC_ISR_DAY_IS_MASK (0x8U) +#define RTC_ISR_DAY_IS_SHIFT (3U) +/*! DAY_IS - Days Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_DAY_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK) + +#define RTC_ISR_HOUR_IS_MASK (0x10U) +#define RTC_ISR_HOUR_IS_SHIFT (4U) +/*! HOUR_IS - Hours Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_HOUR_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK) + +#define RTC_ISR_MIN_IS_MASK (0x20U) +#define RTC_ISR_MIN_IS_SHIFT (5U) +/*! MIN_IS - Minutes Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_MIN_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK) + +#define RTC_ISR_IS_1HZ_MASK (0x40U) +#define RTC_ISR_IS_1HZ_SHIFT (6U) +/*! IS_1HZ - 1 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK) + +#define RTC_ISR_IS_2HZ_MASK (0x80U) +#define RTC_ISR_IS_2HZ_SHIFT (7U) +/*! IS_2HZ - 2 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK) + +#define RTC_ISR_IS_4HZ_MASK (0x100U) +#define RTC_ISR_IS_4HZ_SHIFT (8U) +/*! IS_4HZ - 4 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK) + +#define RTC_ISR_IS_8HZ_MASK (0x200U) +#define RTC_ISR_IS_8HZ_SHIFT (9U) +/*! IS_8HZ - 8 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK) + +#define RTC_ISR_IS_16HZ_MASK (0x400U) +#define RTC_ISR_IS_16HZ_SHIFT (10U) +/*! IS_16HZ - 16 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK) + +#define RTC_ISR_IS_32HZ_MASK (0x800U) +#define RTC_ISR_IS_32HZ_SHIFT (11U) +/*! IS_32HZ - 32 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK) + +#define RTC_ISR_IS_64HZ_MASK (0x1000U) +#define RTC_ISR_IS_64HZ_SHIFT (12U) +/*! IS_64HZ - 64 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK) + +#define RTC_ISR_IS_128HZ_MASK (0x2000U) +#define RTC_ISR_IS_128HZ_SHIFT (13U) +/*! IS_128HZ - 128 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK) + +#define RTC_ISR_IS_256HZ_MASK (0x4000U) +#define RTC_ISR_IS_256HZ_SHIFT (14U) +/*! IS_256HZ - 256 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK) + +#define RTC_ISR_IS_512HZ_MASK (0x8000U) +#define RTC_ISR_IS_512HZ_SHIFT (15U) +/*! IS_512HZ - 512 Hz Interval Interrupt Status + * 0b0..Interrupt is de-asserted. + * 0b1..Interrupt is asserted. + */ +#define RTC_ISR_IS_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define RTC_IER_ALM_IE_MASK (0x4U) +#define RTC_IER_ALM_IE_SHIFT (2U) +/*! ALM_IE - Alarm Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_ALM_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK) + +#define RTC_IER_DAY_IE_MASK (0x8U) +#define RTC_IER_DAY_IE_SHIFT (3U) +/*! DAY_IE - Days Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_DAY_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK) + +#define RTC_IER_HOUR_IE_MASK (0x10U) +#define RTC_IER_HOUR_IE_SHIFT (4U) +/*! HOUR_IE - Hours Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_HOUR_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK) + +#define RTC_IER_MIN_IE_MASK (0x20U) +#define RTC_IER_MIN_IE_SHIFT (5U) +/*! MIN_IE - Minutes Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_MIN_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK) + +#define RTC_IER_IE_1HZ_MASK (0x40U) +#define RTC_IER_IE_1HZ_SHIFT (6U) +/*! IE_1HZ - 1 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK) + +#define RTC_IER_IE_2HZ_MASK (0x80U) +#define RTC_IER_IE_2HZ_SHIFT (7U) +/*! IE_2HZ - 2 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK) + +#define RTC_IER_IE_4HZ_MASK (0x100U) +#define RTC_IER_IE_4HZ_SHIFT (8U) +/*! IE_4HZ - 4 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK) + +#define RTC_IER_IE_8HZ_MASK (0x200U) +#define RTC_IER_IE_8HZ_SHIFT (9U) +/*! IE_8HZ - 8 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK) + +#define RTC_IER_IE_16HZ_MASK (0x400U) +#define RTC_IER_IE_16HZ_SHIFT (10U) +/*! IE_16HZ - 16 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK) + +#define RTC_IER_IE_32HZ_MASK (0x800U) +#define RTC_IER_IE_32HZ_SHIFT (11U) +/*! IE_32HZ - 32 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK) + +#define RTC_IER_IE_64HZ_MASK (0x1000U) +#define RTC_IER_IE_64HZ_SHIFT (12U) +/*! IE_64HZ - 64 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK) + +#define RTC_IER_IE_128HZ_MASK (0x2000U) +#define RTC_IER_IE_128HZ_SHIFT (13U) +/*! IE_128HZ - 128 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK) + +#define RTC_IER_IE_256HZ_MASK (0x4000U) +#define RTC_IER_IE_256HZ_SHIFT (14U) +/*! IE_256HZ - 256 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK) + +#define RTC_IER_IE_512HZ_MASK (0x8000U) +#define RTC_IER_IE_512HZ_SHIFT (15U) +/*! IE_512HZ - 512 Hz Interval Interrupt Enable + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define RTC_IER_IE_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK) +/*! @} */ + +/*! @name RTC_TEST2 - Sub Second Counter */ +/*! @{ */ + +#define RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK (0xFFFFU) +#define RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT (0U) +/*! SUB_SECOND_COUNT - Sub Second Counter Value */ +#define RTC_RTC_TEST2_SUB_SECOND_COUNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_RTC_TEST2_SUB_SECOND_COUNT_SHIFT)) & RTC_RTC_TEST2_SUB_SECOND_COUNT_MASK) +/*! @} */ + +/*! @name DST_HOUR - Daylight Saving Hour */ +/*! @{ */ + +#define RTC_DST_HOUR_DST_END_HOUR_MASK (0x1FU) +#define RTC_DST_HOUR_DST_END_HOUR_SHIFT (0U) +/*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value */ +#define RTC_DST_HOUR_DST_END_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK) + +#define RTC_DST_HOUR_DST_START_HOUR_MASK (0x1F00U) +#define RTC_DST_HOUR_DST_START_HOUR_SHIFT (8U) +/*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value */ +#define RTC_DST_HOUR_DST_START_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK) +/*! @} */ + +/*! @name DST_MONTH - Daylight Saving Month */ +/*! @{ */ + +#define RTC_DST_MONTH_DST_END_MONTH_MASK (0xFU) +#define RTC_DST_MONTH_DST_END_MONTH_SHIFT (0U) +/*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value */ +#define RTC_DST_MONTH_DST_END_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK) + +#define RTC_DST_MONTH_DST_START_MONTH_MASK (0xF00U) +#define RTC_DST_MONTH_DST_START_MONTH_SHIFT (8U) +/*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value */ +#define RTC_DST_MONTH_DST_START_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK) +/*! @} */ + +/*! @name DST_DAY - Daylight Saving Day */ +/*! @{ */ + +#define RTC_DST_DAY_DST_END_DAY_MASK (0x1FU) +#define RTC_DST_DAY_DST_END_DAY_SHIFT (0U) +/*! DST_END_DAY - Daylight Saving Time (DST) Day End Value */ +#define RTC_DST_DAY_DST_END_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK) + +#define RTC_DST_DAY_DST_START_DAY_MASK (0x1F00U) +#define RTC_DST_DAY_DST_START_DAY_SHIFT (8U) +/*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value */ +#define RTC_DST_DAY_DST_START_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK) +/*! @} */ + +/*! @name COMPEN - Compensation */ +/*! @{ */ + +#define RTC_COMPEN_COMPEN_VAL_MASK (0xFFFFU) +#define RTC_COMPEN_COMPEN_VAL_SHIFT (0U) +/*! COMPEN_VAL - Compensation Value */ +#define RTC_COMPEN_COMPEN_VAL(x) (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK) +/*! @} */ + +/*! @name SUBSECOND_CTRL - Subsecond Control */ +/*! @{ */ + +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK (0x1U) +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT (0U) +/*! SUB_SECOND_CNT_EN - Subsecond Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_SHIFT)) & RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK) +/*! @} */ + +/*! @name SUBSECOND_CNT - Subsecond Counter */ +/*! @{ */ + +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK (0xFFFFU) +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT (0U) +/*! SUBSECOND_CNT - Current Subsecond Counter Value */ +#define RTC_SUBSECOND_CNT_SUBSECOND_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSECOND_CNT_SUBSECOND_CNT_SHIFT)) & RTC_SUBSECOND_CNT_SUBSECOND_CNT_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CTRL - Wake Timer Control */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) +/*! WAKE_FLAG - Wake Timer Status Flag + * 0b0..Not timed out + * 0b1..Timed out + */ +#define RTC_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) + +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) +/*! CLR_WAKE_TIMER - Clear Wake Timer + * 0b0..No effect + * 0b1..Clear the wake timer counter + */ +#define RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) + +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) +/*! OSC_DIV_ENA - OSC Divide Enable + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) + +#define RTC_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) +#define RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) +/*! INTR_EN - Enable Interrupt + * 0b0..Disable + * 0b1..Enable + */ +#define RTC_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CNT - Wake Timer Counter */ +/*! @{ */ + +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) +#define RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) +/*! WAKE_CNT - Wake Counter */ +#define RTC_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & RTC_WAKE_TIMER_CNT_WAKE_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x5004C000u) + /** Peripheral RTC0 base address */ + #define RTC0_BASE_NS (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Peripheral RTC0 base pointer */ + #define RTC0_NS ((RTC_Type *)RTC0_BASE_NS) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS_NS { RTC0_BASE_NS } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS_NS { RTC0_NS } +#else + /** Peripheral RTC0 base address */ + #define RTC0_BASE (0x4004C000u) + /** Peripheral RTC0 base pointer */ + #define RTC0 ((RTC_Type *)RTC0_BASE) + /** Array initializer of RTC peripheral base addresses */ + #define RTC_BASE_ADDRS { RTC0_BASE } + /** Array initializer of RTC peripheral base pointers */ + #define RTC_BASE_PTRS { RTC0 } +#endif +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } +/* Backward compatibility for RTC */ +#define RTC RTC0 + + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- S50 Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup S50_Peripheral_Access_Layer S50 Peripheral Access Layer + * @{ + */ + +/** S50 - Register Layout Typedef */ +typedef struct { + __I uint32_t ELS_STATUS; /**< Status Register, offset: 0x0 */ + __IO uint32_t ELS_CTRL; /**< Control Register, offset: 0x4 */ + __IO uint32_t ELS_CMDCFG0; /**< Command Configuration, offset: 0x8 */ + __IO uint32_t ELS_CFG; /**< Configuration Register, offset: 0xC */ + __IO uint32_t ELS_KIDX0; /**< Keystore Index 0, offset: 0x10 */ + __IO uint32_t ELS_KIDX1; /**< Keystore Index 1, offset: 0x14 */ + __IO uint32_t ELS_KPROPIN; /**< Key Properties Request, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ELS_DMA_SRC0; /**< DMA Source 0, offset: 0x20 */ + __IO uint32_t ELS_DMA_SRC0_LEN; /**< DMA Source 0 Length, offset: 0x24 */ + __IO uint32_t ELS_DMA_SRC1; /**< DMA Source 1, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ELS_DMA_SRC2; /**< DMA Source 2, offset: 0x30 */ + __IO uint32_t ELS_DMA_SRC2_LEN; /**< DMA Source 2 Length, offset: 0x34 */ + __IO uint32_t ELS_DMA_RES0; /**< DMA Result 0, offset: 0x38 */ + __IO uint32_t ELS_DMA_RES0_LEN; /**< DMA Result 0 Length, offset: 0x3C */ + __IO uint32_t ELS_INT_ENABLE; /**< Interrupt Enable, offset: 0x40 */ + __O uint32_t ELS_INT_STATUS_CLR; /**< Interrupt Status Clear, offset: 0x44 */ + __O uint32_t ELS_INT_STATUS_SET; /**< Interrupt Status Set, offset: 0x48 */ + __I uint32_t ELS_ERR_STATUS; /**< Error Status, offset: 0x4C */ + __O uint32_t ELS_ERR_STATUS_CLR; /**< Error Status Clear, offset: 0x50 */ + __I uint32_t ELS_VERSION; /**< Version Register, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __I uint32_t ELS_PRNG_DATOUT; /**< PRNG SW Read Out, offset: 0x5C */ + __IO uint32_t ELS_CMDCRC_CTRL; /**< CRC Configuration, offset: 0x60 */ + __I uint32_t ELS_CMDCRC; /**< Command CRC Value, offset: 0x64 */ + __IO uint32_t ELS_SESSION_ID; /**< Session ID, offset: 0x68 */ + uint8_t RESERVED_3[4]; + __I uint32_t ELS_DMA_FIN_ADDR; /**< Final DMA Address, offset: 0x70 */ + __IO uint32_t ELS_MASTER_ID; /**< Master ID, offset: 0x74 */ + __IO uint32_t ELS_KIDX2; /**< Keystore Index 2, offset: 0x78 */ + uint8_t RESERVED_4[212]; + __I uint32_t ELS_KS0; /**< Status Register, offset: 0x150 */ + __I uint32_t ELS_KS1; /**< Status Register, offset: 0x154 */ + __I uint32_t ELS_KS2; /**< Status Register, offset: 0x158 */ + __I uint32_t ELS_KS3; /**< Status Register, offset: 0x15C */ + __I uint32_t ELS_KS4; /**< Status Register, offset: 0x160 */ + __I uint32_t ELS_KS5; /**< Status Register, offset: 0x164 */ + __I uint32_t ELS_KS6; /**< Status Register, offset: 0x168 */ + __I uint32_t ELS_KS7; /**< Status Register, offset: 0x16C */ + __I uint32_t ELS_KS8; /**< Status Register, offset: 0x170 */ + __I uint32_t ELS_KS9; /**< Status Register, offset: 0x174 */ + __I uint32_t ELS_KS10; /**< Status Register, offset: 0x178 */ + __I uint32_t ELS_KS11; /**< Status Register, offset: 0x17C */ + __I uint32_t ELS_KS12; /**< Status Register, offset: 0x180 */ + __I uint32_t ELS_KS13; /**< Status Register, offset: 0x184 */ + __I uint32_t ELS_KS14; /**< Status Register, offset: 0x188 */ + __I uint32_t ELS_KS15; /**< Status Register, offset: 0x18C */ + __I uint32_t ELS_KS16; /**< Status Register, offset: 0x190 */ + __I uint32_t ELS_KS17; /**< Status Register, offset: 0x194 */ + __I uint32_t ELS_KS18; /**< Status Register, offset: 0x198 */ + __I uint32_t ELS_KS19; /**< Status Register, offset: 0x19C */ +} S50_Type; + +/* ---------------------------------------------------------------------------- + -- S50 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup S50_Register_Masks S50 Register Masks + * @{ + */ + +/*! @name ELS_STATUS - Status Register */ +/*! @{ */ + +#define S50_ELS_STATUS_ELS_BUSY_MASK (0x1U) +#define S50_ELS_STATUS_ELS_BUSY_SHIFT (0U) +/*! ELS_BUSY + * 0b1..Crypto sequence executing + * 0b0..Crypto sequence not executing + */ +#define S50_ELS_STATUS_ELS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_BUSY_SHIFT)) & S50_ELS_STATUS_ELS_BUSY_MASK) + +#define S50_ELS_STATUS_ELS_IRQ_MASK (0x2U) +#define S50_ELS_STATUS_ELS_IRQ_SHIFT (1U) +/*! ELS_IRQ + * 0b1..Active interrupt + * 0b0..No active interrupt + */ +#define S50_ELS_STATUS_ELS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_IRQ_SHIFT)) & S50_ELS_STATUS_ELS_IRQ_MASK) + +#define S50_ELS_STATUS_ELS_ERR_MASK (0x4U) +#define S50_ELS_STATUS_ELS_ERR_SHIFT (2U) +/*! ELS_ERR + * 0b1..Internal error detected + * 0b0..Internal error not detected + */ +#define S50_ELS_STATUS_ELS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_ERR_SHIFT)) & S50_ELS_STATUS_ELS_ERR_MASK) + +#define S50_ELS_STATUS_PRNG_RDY_MASK (0x8U) +#define S50_ELS_STATUS_PRNG_RDY_SHIFT (3U) +/*! PRNG_RDY + * 0b0..Internal PRNG not ready + * 0b1..Internal PRNG ready + */ +#define S50_ELS_STATUS_PRNG_RDY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PRNG_RDY_SHIFT)) & S50_ELS_STATUS_PRNG_RDY_MASK) + +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK (0x30U) +#define S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT (4U) +/*! ECDSA_VFY_STATUS + * 0b11..Invalid, Error + * 0b00..No verify run + * 0b01..Signature verify failed + * 0b10..Signature verify passed + */ +#define S50_ELS_STATUS_ECDSA_VFY_STATUS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ECDSA_VFY_STATUS_SHIFT)) & S50_ELS_STATUS_ECDSA_VFY_STATUS_MASK) + +#define S50_ELS_STATUS_PPROT_MASK (0xC0U) +#define S50_ELS_STATUS_PPROT_SHIFT (6U) +/*! PPROT + * 0b10..Non-secure, non-privileged + * 0b11..Non-secure, privileged + * 0b00..Secure, non-privileged + * 0b01..Secure, privileged + */ +#define S50_ELS_STATUS_PPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_PPROT_SHIFT)) & S50_ELS_STATUS_PPROT_MASK) + +#define S50_ELS_STATUS_DRBG_ENT_LVL_MASK (0x300U) +#define S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT (8U) +/*! DRBG_ENT_LVL + * 0b10..HIGH, DRBG generates random numbers of high quality entropy + * 0b01..LOW, DRBG generates random numbers of low quality entropy + * 0b00..NONE + * 0b11..RFU, Reserved for Future Use + */ +#define S50_ELS_STATUS_DRBG_ENT_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DRBG_ENT_LVL_SHIFT)) & S50_ELS_STATUS_DRBG_ENT_LVL_MASK) + +#define S50_ELS_STATUS_DTRNG_BUSY_MASK (0x400U) +#define S50_ELS_STATUS_DTRNG_BUSY_SHIFT (10U) +/*! DTRNG_BUSY + * 0b1..Gathering entropy + * 0b0..Not gathering entropy + */ +#define S50_ELS_STATUS_DTRNG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_DTRNG_BUSY_SHIFT)) & S50_ELS_STATUS_DTRNG_BUSY_MASK) + +#define S50_ELS_STATUS_ELS_LOCKED_MASK (0x10000U) +#define S50_ELS_STATUS_ELS_LOCKED_SHIFT (16U) +/*! ELS_LOCKED + * 0b1..Locked by master + * 0b0..Not locked by master + */ +#define S50_ELS_STATUS_ELS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_STATUS_ELS_LOCKED_SHIFT)) & S50_ELS_STATUS_ELS_LOCKED_MASK) +/*! @} */ + +/*! @name ELS_CTRL - Control Register */ +/*! @{ */ + +#define S50_ELS_CTRL_ELS_EN_MASK (0x1U) +#define S50_ELS_CTRL_ELS_EN_SHIFT (0U) +/*! ELS_EN + * 0b0..Disabled + * 0b1..Enabled + */ +#define S50_ELS_CTRL_ELS_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_EN_SHIFT)) & S50_ELS_CTRL_ELS_EN_MASK) + +#define S50_ELS_CTRL_ELS_START_MASK (0x2U) +#define S50_ELS_CTRL_ELS_START_SHIFT (1U) +#define S50_ELS_CTRL_ELS_START(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_START_SHIFT)) & S50_ELS_CTRL_ELS_START_MASK) + +#define S50_ELS_CTRL_ELS_RESET_MASK (0x4U) +#define S50_ELS_CTRL_ELS_RESET_SHIFT (2U) +#define S50_ELS_CTRL_ELS_RESET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_RESET_SHIFT)) & S50_ELS_CTRL_ELS_RESET_MASK) + +#define S50_ELS_CTRL_ELS_CMD_MASK (0xF8U) +#define S50_ELS_CTRL_ELS_CMD_SHIFT (3U) +/*! ELS_CMD - ELS Command ID */ +#define S50_ELS_CTRL_ELS_CMD(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_ELS_CMD_SHIFT)) & S50_ELS_CTRL_ELS_CMD_MASK) + +#define S50_ELS_CTRL_BYTE_ORDER_MASK (0x100U) +#define S50_ELS_CTRL_BYTE_ORDER_SHIFT (8U) +/*! BYTE_ORDER + * 0b1..Big endian + * 0b0..Little endian + */ +#define S50_ELS_CTRL_BYTE_ORDER(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CTRL_BYTE_ORDER_SHIFT)) & S50_ELS_CTRL_BYTE_ORDER_MASK) +/*! @} */ + +/*! @name ELS_CMDCFG0 - Command Configuration */ +/*! @{ */ + +#define S50_ELS_CMDCFG0_CMDCFG0_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCFG0_CMDCFG0_SHIFT (0U) +#define S50_ELS_CMDCFG0_CMDCFG0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCFG0_CMDCFG0_SHIFT)) & S50_ELS_CMDCFG0_CMDCFG0_MASK) +/*! @} */ + +/*! @name ELS_CFG - Configuration Register */ +/*! @{ */ + +#define S50_ELS_CFG_ADCTRL_MASK (0x3FF0000U) +#define S50_ELS_CFG_ADCTRL_SHIFT (16U) +#define S50_ELS_CFG_ADCTRL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CFG_ADCTRL_SHIFT)) & S50_ELS_CFG_ADCTRL_MASK) +/*! @} */ + +/*! @name ELS_KIDX0 - Keystore Index 0 */ +/*! @{ */ + +#define S50_ELS_KIDX0_KIDX0_MASK (0x1FU) +#define S50_ELS_KIDX0_KIDX0_SHIFT (0U) +#define S50_ELS_KIDX0_KIDX0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX0_KIDX0_SHIFT)) & S50_ELS_KIDX0_KIDX0_MASK) +/*! @} */ + +/*! @name ELS_KIDX1 - Keystore Index 1 */ +/*! @{ */ + +#define S50_ELS_KIDX1_KIDX1_MASK (0x1FU) +#define S50_ELS_KIDX1_KIDX1_SHIFT (0U) +#define S50_ELS_KIDX1_KIDX1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX1_KIDX1_SHIFT)) & S50_ELS_KIDX1_KIDX1_MASK) +/*! @} */ + +/*! @name ELS_KPROPIN - Key Properties Request */ +/*! @{ */ + +#define S50_ELS_KPROPIN_KPROPIN_MASK (0xFFFFFFFFU) +#define S50_ELS_KPROPIN_KPROPIN_SHIFT (0U) +#define S50_ELS_KPROPIN_KPROPIN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KPROPIN_KPROPIN_SHIFT)) & S50_ELS_KPROPIN_KPROPIN_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC0 - DMA Source 0 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC0_ADDR_SRC0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT (0U) +#define S50_ELS_DMA_SRC0_ADDR_SRC0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_ADDR_SRC0_SHIFT)) & S50_ELS_DMA_SRC0_ADDR_SRC0_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC0_LEN - DMA Source 0 Length */ +/*! @{ */ + +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_SHIFT)) & S50_ELS_DMA_SRC0_LEN_SIZE_SRC0_LEN_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC1 - DMA Source 1 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC1_ADDR_SRC1_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT (0U) +#define S50_ELS_DMA_SRC1_ADDR_SRC1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC1_ADDR_SRC1_SHIFT)) & S50_ELS_DMA_SRC1_ADDR_SRC1_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC2 - DMA Source 2 */ +/*! @{ */ + +#define S50_ELS_DMA_SRC2_ADDR_SRC2_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT (0U) +#define S50_ELS_DMA_SRC2_ADDR_SRC2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_ADDR_SRC2_SHIFT)) & S50_ELS_DMA_SRC2_ADDR_SRC2_MASK) +/*! @} */ + +/*! @name ELS_DMA_SRC2_LEN - DMA Source 2 Length */ +/*! @{ */ + +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT (0U) +#define S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_SHIFT)) & S50_ELS_DMA_SRC2_LEN_SIZE_SRC2_LEN_MASK) +/*! @} */ + +/*! @name ELS_DMA_RES0 - DMA Result 0 */ +/*! @{ */ + +#define S50_ELS_DMA_RES0_ADDR_RES0_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_ADDR_RES0_SHIFT (0U) +#define S50_ELS_DMA_RES0_ADDR_RES0(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_ADDR_RES0_SHIFT)) & S50_ELS_DMA_RES0_ADDR_RES0_MASK) +/*! @} */ + +/*! @name ELS_DMA_RES0_LEN - DMA Result 0 Length */ +/*! @{ */ + +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT (0U) +#define S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_SHIFT)) & S50_ELS_DMA_RES0_LEN_SIZE_RES0_LEN_MASK) +/*! @} */ + +/*! @name ELS_INT_ENABLE - Interrupt Enable */ +/*! @{ */ + +#define S50_ELS_INT_ENABLE_INT_EN_MASK (0x1U) +#define S50_ELS_INT_ENABLE_INT_EN_SHIFT (0U) +/*! INT_EN + * 0b0..Disables + * 0b1..Enables + */ +#define S50_ELS_INT_ENABLE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_ENABLE_INT_EN_SHIFT)) & S50_ELS_INT_ENABLE_INT_EN_MASK) +/*! @} */ + +/*! @name ELS_INT_STATUS_CLR - Interrupt Status Clear */ +/*! @{ */ + +#define S50_ELS_INT_STATUS_CLR_INT_CLR_MASK (0x1U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT (0U) +#define S50_ELS_INT_STATUS_CLR_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_CLR_INT_CLR_SHIFT)) & S50_ELS_INT_STATUS_CLR_INT_CLR_MASK) +/*! @} */ + +/*! @name ELS_INT_STATUS_SET - Interrupt Status Set */ +/*! @{ */ + +#define S50_ELS_INT_STATUS_SET_INT_SET_MASK (0x1U) +#define S50_ELS_INT_STATUS_SET_INT_SET_SHIFT (0U) +#define S50_ELS_INT_STATUS_SET_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_INT_STATUS_SET_INT_SET_SHIFT)) & S50_ELS_INT_STATUS_SET_INT_SET_MASK) +/*! @} */ + +/*! @name ELS_ERR_STATUS - Error Status */ +/*! @{ */ + +#define S50_ELS_ERR_STATUS_BUS_ERR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_BUS_ERR_SHIFT (0U) +/*! BUS_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_BUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_BUS_ERR_SHIFT)) & S50_ELS_ERR_STATUS_BUS_ERR_MASK) + +#define S50_ELS_ERR_STATUS_OPN_ERR_MASK (0x2U) +#define S50_ELS_ERR_STATUS_OPN_ERR_SHIFT (1U) +/*! OPN_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_OPN_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_OPN_ERR_SHIFT)) & S50_ELS_ERR_STATUS_OPN_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ALG_ERR_MASK (0x4U) +#define S50_ELS_ERR_STATUS_ALG_ERR_SHIFT (2U) +/*! ALG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ALG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ALG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ALG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ITG_ERR_MASK (0x8U) +#define S50_ELS_ERR_STATUS_ITG_ERR_SHIFT (3U) +/*! ITG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_ITG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ITG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_ITG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_FLT_ERR_MASK (0x10U) +#define S50_ELS_ERR_STATUS_FLT_ERR_SHIFT (4U) +/*! FLT_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_FLT_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_FLT_ERR_SHIFT)) & S50_ELS_ERR_STATUS_FLT_ERR_MASK) + +#define S50_ELS_ERR_STATUS_PRNG_ERR_MASK (0x20U) +#define S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT (5U) +/*! PRNG_ERR + * 0b0..No error + * 0b1..Error occurred + */ +#define S50_ELS_ERR_STATUS_PRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_PRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_PRNG_ERR_MASK) + +#define S50_ELS_ERR_STATUS_ERR_LVL_MASK (0xC0U) +#define S50_ELS_ERR_STATUS_ERR_LVL_SHIFT (6U) +#define S50_ELS_ERR_STATUS_ERR_LVL(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_ERR_LVL_SHIFT)) & S50_ELS_ERR_STATUS_ERR_LVL_MASK) + +#define S50_ELS_ERR_STATUS_DTRNG_ERR_MASK (0x100U) +#define S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT (8U) +/*! DTRNG_ERR + * 0b0..No error + * 0b1..TRNG error occurred + */ +#define S50_ELS_ERR_STATUS_DTRNG_ERR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_DTRNG_ERR_SHIFT)) & S50_ELS_ERR_STATUS_DTRNG_ERR_MASK) +/*! @} */ + +/*! @name ELS_ERR_STATUS_CLR - Error Status Clear */ +/*! @{ */ + +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK (0x1U) +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT (0U) +/*! ERR_CLR + * 0b1..Clears ELS error state + * 0b0..Exits ELS error state + */ +#define S50_ELS_ERR_STATUS_CLR_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_ERR_STATUS_CLR_ERR_CLR_SHIFT)) & S50_ELS_ERR_STATUS_CLR_ERR_CLR_MASK) +/*! @} */ + +/*! @name ELS_VERSION - Version Register */ +/*! @{ */ + +#define S50_ELS_VERSION_Z_MASK (0xFU) +#define S50_ELS_VERSION_Z_SHIFT (0U) +#define S50_ELS_VERSION_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Z_SHIFT)) & S50_ELS_VERSION_Z_MASK) + +#define S50_ELS_VERSION_Y2_MASK (0xF0U) +#define S50_ELS_VERSION_Y2_SHIFT (4U) +#define S50_ELS_VERSION_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y2_SHIFT)) & S50_ELS_VERSION_Y2_MASK) + +#define S50_ELS_VERSION_Y1_MASK (0xF00U) +#define S50_ELS_VERSION_Y1_SHIFT (8U) +#define S50_ELS_VERSION_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_Y1_SHIFT)) & S50_ELS_VERSION_Y1_MASK) + +#define S50_ELS_VERSION_X_MASK (0xF000U) +#define S50_ELS_VERSION_X_SHIFT (12U) +#define S50_ELS_VERSION_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_X_SHIFT)) & S50_ELS_VERSION_X_MASK) + +#define S50_ELS_VERSION_SW_Z_MASK (0xF0000U) +#define S50_ELS_VERSION_SW_Z_SHIFT (16U) +#define S50_ELS_VERSION_SW_Z(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Z_SHIFT)) & S50_ELS_VERSION_SW_Z_MASK) + +#define S50_ELS_VERSION_SW_Y2_MASK (0xF00000U) +#define S50_ELS_VERSION_SW_Y2_SHIFT (20U) +#define S50_ELS_VERSION_SW_Y2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y2_SHIFT)) & S50_ELS_VERSION_SW_Y2_MASK) + +#define S50_ELS_VERSION_SW_Y1_MASK (0xF000000U) +#define S50_ELS_VERSION_SW_Y1_SHIFT (24U) +#define S50_ELS_VERSION_SW_Y1(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_Y1_SHIFT)) & S50_ELS_VERSION_SW_Y1_MASK) + +#define S50_ELS_VERSION_SW_X_MASK (0xF0000000U) +#define S50_ELS_VERSION_SW_X_SHIFT (28U) +#define S50_ELS_VERSION_SW_X(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_VERSION_SW_X_SHIFT)) & S50_ELS_VERSION_SW_X_MASK) +/*! @} */ + +/*! @name ELS_PRNG_DATOUT - PRNG SW Read Out */ +/*! @{ */ + +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK (0xFFFFFFFFU) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT (0U) +#define S50_ELS_PRNG_DATOUT_PRNG_DATOUT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_PRNG_DATOUT_PRNG_DATOUT_SHIFT)) & S50_ELS_PRNG_DATOUT_PRNG_DATOUT_MASK) +/*! @} */ + +/*! @name ELS_CMDCRC_CTRL - CRC Configuration */ +/*! @{ */ + +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK (0x1U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT (0U) +/*! CMDCRC_RST + * 0b1..Resets the CRC command to its default value + * 0b0..No effect + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_RST(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_RST_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_RST_MASK) + +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK (0x2U) +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT (1U) +/*! CMDCRC_EN + * 0b1..Enables the CRC command. The CRC command will be updated on completion of each ELS command. + * 0b0..Disables the CRC command CRC. The CRC command will not be updated on completion of each ELS command. + */ +#define S50_ELS_CMDCRC_CTRL_CMDCRC_EN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CTRL_CMDCRC_EN_SHIFT)) & S50_ELS_CMDCRC_CTRL_CMDCRC_EN_MASK) +/*! @} */ + +/*! @name ELS_CMDCRC - Command CRC Value */ +/*! @{ */ + +#define S50_ELS_CMDCRC_CMDCRC_MASK (0xFFFFFFFFU) +#define S50_ELS_CMDCRC_CMDCRC_SHIFT (0U) +#define S50_ELS_CMDCRC_CMDCRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_CMDCRC_CMDCRC_SHIFT)) & S50_ELS_CMDCRC_CMDCRC_MASK) +/*! @} */ + +/*! @name ELS_SESSION_ID - Session ID */ +/*! @{ */ + +#define S50_ELS_SESSION_ID_SESSION_ID_MASK (0xFFFFFFFFU) +#define S50_ELS_SESSION_ID_SESSION_ID_SHIFT (0U) +#define S50_ELS_SESSION_ID_SESSION_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_SESSION_ID_SESSION_ID_SHIFT)) & S50_ELS_SESSION_ID_SESSION_ID_MASK) +/*! @} */ + +/*! @name ELS_DMA_FIN_ADDR - Final DMA Address */ +/*! @{ */ + +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK (0xFFFFFFFFU) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT (0U) +#define S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_SHIFT)) & S50_ELS_DMA_FIN_ADDR_DMA_FIN_ADDR_MASK) +/*! @} */ + +/*! @name ELS_MASTER_ID - Master ID */ +/*! @{ */ + +#define S50_ELS_MASTER_ID_MASTER_ID_MASK (0x1FU) +#define S50_ELS_MASTER_ID_MASTER_ID_SHIFT (0U) +#define S50_ELS_MASTER_ID_MASTER_ID(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_MASTER_ID_MASTER_ID_SHIFT)) & S50_ELS_MASTER_ID_MASTER_ID_MASK) +/*! @} */ + +/*! @name ELS_KIDX2 - Keystore Index 2 */ +/*! @{ */ + +#define S50_ELS_KIDX2_KIDX2_MASK (0x1FU) +#define S50_ELS_KIDX2_KIDX2_SHIFT (0U) +#define S50_ELS_KIDX2_KIDX2(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KIDX2_KIDX2_SHIFT)) & S50_ELS_KIDX2_KIDX2_MASK) +/*! @} */ + +/*! @name ELS_KS0 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS0_KS0_KSIZE_MASK (0x3U) +#define S50_ELS_KS0_KS0_KSIZE_SHIFT (0U) +/*! KS0_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS0_KS0_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KSIZE_SHIFT)) & S50_ELS_KS0_KS0_KSIZE_MASK) + +#define S50_ELS_KS0_KS0_KACT_MASK (0x20U) +#define S50_ELS_KS0_KS0_KACT_SHIFT (5U) +#define S50_ELS_KS0_KS0_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KACT_SHIFT)) & S50_ELS_KS0_KS0_KACT_MASK) + +#define S50_ELS_KS0_KS0_KBASE_MASK (0x40U) +#define S50_ELS_KS0_KS0_KBASE_SHIFT (6U) +#define S50_ELS_KS0_KS0_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_KBASE_SHIFT)) & S50_ELS_KS0_KS0_KBASE_MASK) + +#define S50_ELS_KS0_KS0_FGP_MASK (0x80U) +#define S50_ELS_KS0_KS0_FGP_SHIFT (7U) +#define S50_ELS_KS0_KS0_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FGP_SHIFT)) & S50_ELS_KS0_KS0_FGP_MASK) + +#define S50_ELS_KS0_KS0_FRTN_MASK (0x100U) +#define S50_ELS_KS0_KS0_FRTN_SHIFT (8U) +#define S50_ELS_KS0_KS0_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FRTN_SHIFT)) & S50_ELS_KS0_KS0_FRTN_MASK) + +#define S50_ELS_KS0_KS0_FHWO_MASK (0x200U) +#define S50_ELS_KS0_KS0_FHWO_SHIFT (9U) +#define S50_ELS_KS0_KS0_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_FHWO_SHIFT)) & S50_ELS_KS0_KS0_FHWO_MASK) + +#define S50_ELS_KS0_KS0_UKPUK_MASK (0x800U) +#define S50_ELS_KS0_KS0_UKPUK_SHIFT (11U) +#define S50_ELS_KS0_KS0_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKPUK_SHIFT)) & S50_ELS_KS0_KS0_UKPUK_MASK) + +#define S50_ELS_KS0_KS0_UTECDH_MASK (0x1000U) +#define S50_ELS_KS0_KS0_UTECDH_SHIFT (12U) +#define S50_ELS_KS0_KS0_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTECDH_SHIFT)) & S50_ELS_KS0_KS0_UTECDH_MASK) + +#define S50_ELS_KS0_KS0_UCMAC_MASK (0x2000U) +#define S50_ELS_KS0_KS0_UCMAC_SHIFT (13U) +#define S50_ELS_KS0_KS0_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCMAC_SHIFT)) & S50_ELS_KS0_KS0_UCMAC_MASK) + +#define S50_ELS_KS0_KS0_UKSK_MASK (0x4000U) +#define S50_ELS_KS0_KS0_UKSK_SHIFT (14U) +#define S50_ELS_KS0_KS0_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKSK_SHIFT)) & S50_ELS_KS0_KS0_UKSK_MASK) + +#define S50_ELS_KS0_KS0_URTF_MASK (0x8000U) +#define S50_ELS_KS0_KS0_URTF_SHIFT (15U) +#define S50_ELS_KS0_KS0_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_URTF_SHIFT)) & S50_ELS_KS0_KS0_URTF_MASK) + +#define S50_ELS_KS0_KS0_UCKDF_MASK (0x10000U) +#define S50_ELS_KS0_KS0_UCKDF_SHIFT (16U) +#define S50_ELS_KS0_KS0_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UCKDF_SHIFT)) & S50_ELS_KS0_KS0_UCKDF_MASK) + +#define S50_ELS_KS0_KS0_UHKDF_MASK (0x20000U) +#define S50_ELS_KS0_KS0_UHKDF_SHIFT (17U) +#define S50_ELS_KS0_KS0_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHKDF_SHIFT)) & S50_ELS_KS0_KS0_UHKDF_MASK) + +#define S50_ELS_KS0_KS0_UECSG_MASK (0x40000U) +#define S50_ELS_KS0_KS0_UECSG_SHIFT (18U) +#define S50_ELS_KS0_KS0_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECSG_SHIFT)) & S50_ELS_KS0_KS0_UECSG_MASK) + +#define S50_ELS_KS0_KS0_UECDH_MASK (0x80000U) +#define S50_ELS_KS0_KS0_UECDH_SHIFT (19U) +#define S50_ELS_KS0_KS0_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UECDH_SHIFT)) & S50_ELS_KS0_KS0_UECDH_MASK) + +#define S50_ELS_KS0_KS0_UAES_MASK (0x100000U) +#define S50_ELS_KS0_KS0_UAES_SHIFT (20U) +#define S50_ELS_KS0_KS0_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UAES_SHIFT)) & S50_ELS_KS0_KS0_UAES_MASK) + +#define S50_ELS_KS0_KS0_UHMAC_MASK (0x200000U) +#define S50_ELS_KS0_KS0_UHMAC_SHIFT (21U) +#define S50_ELS_KS0_KS0_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHMAC_SHIFT)) & S50_ELS_KS0_KS0_UHMAC_MASK) + +#define S50_ELS_KS0_KS0_UKWK_MASK (0x400000U) +#define S50_ELS_KS0_KS0_UKWK_SHIFT (22U) +#define S50_ELS_KS0_KS0_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKWK_SHIFT)) & S50_ELS_KS0_KS0_UKWK_MASK) + +#define S50_ELS_KS0_KS0_UKUOK_MASK (0x800000U) +#define S50_ELS_KS0_KS0_UKUOK_SHIFT (23U) +#define S50_ELS_KS0_KS0_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKUOK_SHIFT)) & S50_ELS_KS0_KS0_UKUOK_MASK) + +#define S50_ELS_KS0_KS0_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS0_KS0_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS0_KS0_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSPMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSPMS_MASK) + +#define S50_ELS_KS0_KS0_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS0_KS0_UTLSMS_SHIFT (25U) +#define S50_ELS_KS0_KS0_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UTLSMS_SHIFT)) & S50_ELS_KS0_KS0_UTLSMS_MASK) + +#define S50_ELS_KS0_KS0_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS0_KS0_UKGSRC_SHIFT (26U) +#define S50_ELS_KS0_KS0_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UKGSRC_SHIFT)) & S50_ELS_KS0_KS0_UKGSRC_MASK) + +#define S50_ELS_KS0_KS0_UHWO_MASK (0x8000000U) +#define S50_ELS_KS0_KS0_UHWO_SHIFT (27U) +#define S50_ELS_KS0_KS0_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UHWO_SHIFT)) & S50_ELS_KS0_KS0_UHWO_MASK) + +#define S50_ELS_KS0_KS0_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS0_KS0_UWRPOK_SHIFT (28U) +#define S50_ELS_KS0_KS0_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UWRPOK_SHIFT)) & S50_ELS_KS0_KS0_UWRPOK_MASK) + +#define S50_ELS_KS0_KS0_UDUK_MASK (0x20000000U) +#define S50_ELS_KS0_KS0_UDUK_SHIFT (29U) +#define S50_ELS_KS0_KS0_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UDUK_SHIFT)) & S50_ELS_KS0_KS0_UDUK_MASK) + +#define S50_ELS_KS0_KS0_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS0_KS0_UPPROT_SHIFT (30U) +#define S50_ELS_KS0_KS0_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS0_KS0_UPPROT_SHIFT)) & S50_ELS_KS0_KS0_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS1 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS1_KS1_KSIZE_MASK (0x3U) +#define S50_ELS_KS1_KS1_KSIZE_SHIFT (0U) +/*! KS1_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS1_KS1_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KSIZE_SHIFT)) & S50_ELS_KS1_KS1_KSIZE_MASK) + +#define S50_ELS_KS1_KS1_KACT_MASK (0x20U) +#define S50_ELS_KS1_KS1_KACT_SHIFT (5U) +#define S50_ELS_KS1_KS1_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KACT_SHIFT)) & S50_ELS_KS1_KS1_KACT_MASK) + +#define S50_ELS_KS1_KS1_KBASE_MASK (0x40U) +#define S50_ELS_KS1_KS1_KBASE_SHIFT (6U) +#define S50_ELS_KS1_KS1_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_KBASE_SHIFT)) & S50_ELS_KS1_KS1_KBASE_MASK) + +#define S50_ELS_KS1_KS1_FGP_MASK (0x80U) +#define S50_ELS_KS1_KS1_FGP_SHIFT (7U) +#define S50_ELS_KS1_KS1_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FGP_SHIFT)) & S50_ELS_KS1_KS1_FGP_MASK) + +#define S50_ELS_KS1_KS1_FRTN_MASK (0x100U) +#define S50_ELS_KS1_KS1_FRTN_SHIFT (8U) +#define S50_ELS_KS1_KS1_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FRTN_SHIFT)) & S50_ELS_KS1_KS1_FRTN_MASK) + +#define S50_ELS_KS1_KS1_FHWO_MASK (0x200U) +#define S50_ELS_KS1_KS1_FHWO_SHIFT (9U) +#define S50_ELS_KS1_KS1_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_FHWO_SHIFT)) & S50_ELS_KS1_KS1_FHWO_MASK) + +#define S50_ELS_KS1_KS1_UKPUK_MASK (0x800U) +#define S50_ELS_KS1_KS1_UKPUK_SHIFT (11U) +#define S50_ELS_KS1_KS1_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKPUK_SHIFT)) & S50_ELS_KS1_KS1_UKPUK_MASK) + +#define S50_ELS_KS1_KS1_UTECDH_MASK (0x1000U) +#define S50_ELS_KS1_KS1_UTECDH_SHIFT (12U) +#define S50_ELS_KS1_KS1_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTECDH_SHIFT)) & S50_ELS_KS1_KS1_UTECDH_MASK) + +#define S50_ELS_KS1_KS1_UCMAC_MASK (0x2000U) +#define S50_ELS_KS1_KS1_UCMAC_SHIFT (13U) +#define S50_ELS_KS1_KS1_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCMAC_SHIFT)) & S50_ELS_KS1_KS1_UCMAC_MASK) + +#define S50_ELS_KS1_KS1_UKSK_MASK (0x4000U) +#define S50_ELS_KS1_KS1_UKSK_SHIFT (14U) +#define S50_ELS_KS1_KS1_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKSK_SHIFT)) & S50_ELS_KS1_KS1_UKSK_MASK) + +#define S50_ELS_KS1_KS1_URTF_MASK (0x8000U) +#define S50_ELS_KS1_KS1_URTF_SHIFT (15U) +#define S50_ELS_KS1_KS1_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_URTF_SHIFT)) & S50_ELS_KS1_KS1_URTF_MASK) + +#define S50_ELS_KS1_KS1_UCKDF_MASK (0x10000U) +#define S50_ELS_KS1_KS1_UCKDF_SHIFT (16U) +#define S50_ELS_KS1_KS1_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UCKDF_SHIFT)) & S50_ELS_KS1_KS1_UCKDF_MASK) + +#define S50_ELS_KS1_KS1_UHKDF_MASK (0x20000U) +#define S50_ELS_KS1_KS1_UHKDF_SHIFT (17U) +#define S50_ELS_KS1_KS1_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHKDF_SHIFT)) & S50_ELS_KS1_KS1_UHKDF_MASK) + +#define S50_ELS_KS1_KS1_UECSG_MASK (0x40000U) +#define S50_ELS_KS1_KS1_UECSG_SHIFT (18U) +#define S50_ELS_KS1_KS1_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECSG_SHIFT)) & S50_ELS_KS1_KS1_UECSG_MASK) + +#define S50_ELS_KS1_KS1_UECDH_MASK (0x80000U) +#define S50_ELS_KS1_KS1_UECDH_SHIFT (19U) +#define S50_ELS_KS1_KS1_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UECDH_SHIFT)) & S50_ELS_KS1_KS1_UECDH_MASK) + +#define S50_ELS_KS1_KS1_UAES_MASK (0x100000U) +#define S50_ELS_KS1_KS1_UAES_SHIFT (20U) +#define S50_ELS_KS1_KS1_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UAES_SHIFT)) & S50_ELS_KS1_KS1_UAES_MASK) + +#define S50_ELS_KS1_KS1_UHMAC_MASK (0x200000U) +#define S50_ELS_KS1_KS1_UHMAC_SHIFT (21U) +#define S50_ELS_KS1_KS1_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHMAC_SHIFT)) & S50_ELS_KS1_KS1_UHMAC_MASK) + +#define S50_ELS_KS1_KS1_UKWK_MASK (0x400000U) +#define S50_ELS_KS1_KS1_UKWK_SHIFT (22U) +#define S50_ELS_KS1_KS1_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKWK_SHIFT)) & S50_ELS_KS1_KS1_UKWK_MASK) + +#define S50_ELS_KS1_KS1_UKUOK_MASK (0x800000U) +#define S50_ELS_KS1_KS1_UKUOK_SHIFT (23U) +#define S50_ELS_KS1_KS1_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKUOK_SHIFT)) & S50_ELS_KS1_KS1_UKUOK_MASK) + +#define S50_ELS_KS1_KS1_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS1_KS1_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS1_KS1_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSPMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSPMS_MASK) + +#define S50_ELS_KS1_KS1_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS1_KS1_UTLSMS_SHIFT (25U) +#define S50_ELS_KS1_KS1_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UTLSMS_SHIFT)) & S50_ELS_KS1_KS1_UTLSMS_MASK) + +#define S50_ELS_KS1_KS1_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS1_KS1_UKGSRC_SHIFT (26U) +#define S50_ELS_KS1_KS1_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UKGSRC_SHIFT)) & S50_ELS_KS1_KS1_UKGSRC_MASK) + +#define S50_ELS_KS1_KS1_UHWO_MASK (0x8000000U) +#define S50_ELS_KS1_KS1_UHWO_SHIFT (27U) +#define S50_ELS_KS1_KS1_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UHWO_SHIFT)) & S50_ELS_KS1_KS1_UHWO_MASK) + +#define S50_ELS_KS1_KS1_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS1_KS1_UWRPOK_SHIFT (28U) +#define S50_ELS_KS1_KS1_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UWRPOK_SHIFT)) & S50_ELS_KS1_KS1_UWRPOK_MASK) + +#define S50_ELS_KS1_KS1_UDUK_MASK (0x20000000U) +#define S50_ELS_KS1_KS1_UDUK_SHIFT (29U) +#define S50_ELS_KS1_KS1_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UDUK_SHIFT)) & S50_ELS_KS1_KS1_UDUK_MASK) + +#define S50_ELS_KS1_KS1_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS1_KS1_UPPROT_SHIFT (30U) +#define S50_ELS_KS1_KS1_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS1_KS1_UPPROT_SHIFT)) & S50_ELS_KS1_KS1_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS2 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS2_KS2_KSIZE_MASK (0x3U) +#define S50_ELS_KS2_KS2_KSIZE_SHIFT (0U) +/*! KS2_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS2_KS2_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KSIZE_SHIFT)) & S50_ELS_KS2_KS2_KSIZE_MASK) + +#define S50_ELS_KS2_KS2_KACT_MASK (0x20U) +#define S50_ELS_KS2_KS2_KACT_SHIFT (5U) +#define S50_ELS_KS2_KS2_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KACT_SHIFT)) & S50_ELS_KS2_KS2_KACT_MASK) + +#define S50_ELS_KS2_KS2_KBASE_MASK (0x40U) +#define S50_ELS_KS2_KS2_KBASE_SHIFT (6U) +#define S50_ELS_KS2_KS2_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_KBASE_SHIFT)) & S50_ELS_KS2_KS2_KBASE_MASK) + +#define S50_ELS_KS2_KS2_FGP_MASK (0x80U) +#define S50_ELS_KS2_KS2_FGP_SHIFT (7U) +#define S50_ELS_KS2_KS2_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FGP_SHIFT)) & S50_ELS_KS2_KS2_FGP_MASK) + +#define S50_ELS_KS2_KS2_FRTN_MASK (0x100U) +#define S50_ELS_KS2_KS2_FRTN_SHIFT (8U) +#define S50_ELS_KS2_KS2_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FRTN_SHIFT)) & S50_ELS_KS2_KS2_FRTN_MASK) + +#define S50_ELS_KS2_KS2_FHWO_MASK (0x200U) +#define S50_ELS_KS2_KS2_FHWO_SHIFT (9U) +#define S50_ELS_KS2_KS2_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_FHWO_SHIFT)) & S50_ELS_KS2_KS2_FHWO_MASK) + +#define S50_ELS_KS2_KS2_UKPUK_MASK (0x800U) +#define S50_ELS_KS2_KS2_UKPUK_SHIFT (11U) +#define S50_ELS_KS2_KS2_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKPUK_SHIFT)) & S50_ELS_KS2_KS2_UKPUK_MASK) + +#define S50_ELS_KS2_KS2_UTECDH_MASK (0x1000U) +#define S50_ELS_KS2_KS2_UTECDH_SHIFT (12U) +#define S50_ELS_KS2_KS2_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTECDH_SHIFT)) & S50_ELS_KS2_KS2_UTECDH_MASK) + +#define S50_ELS_KS2_KS2_UCMAC_MASK (0x2000U) +#define S50_ELS_KS2_KS2_UCMAC_SHIFT (13U) +#define S50_ELS_KS2_KS2_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCMAC_SHIFT)) & S50_ELS_KS2_KS2_UCMAC_MASK) + +#define S50_ELS_KS2_KS2_UKSK_MASK (0x4000U) +#define S50_ELS_KS2_KS2_UKSK_SHIFT (14U) +#define S50_ELS_KS2_KS2_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKSK_SHIFT)) & S50_ELS_KS2_KS2_UKSK_MASK) + +#define S50_ELS_KS2_KS2_URTF_MASK (0x8000U) +#define S50_ELS_KS2_KS2_URTF_SHIFT (15U) +#define S50_ELS_KS2_KS2_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_URTF_SHIFT)) & S50_ELS_KS2_KS2_URTF_MASK) + +#define S50_ELS_KS2_KS2_UCKDF_MASK (0x10000U) +#define S50_ELS_KS2_KS2_UCKDF_SHIFT (16U) +#define S50_ELS_KS2_KS2_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UCKDF_SHIFT)) & S50_ELS_KS2_KS2_UCKDF_MASK) + +#define S50_ELS_KS2_KS2_UHKDF_MASK (0x20000U) +#define S50_ELS_KS2_KS2_UHKDF_SHIFT (17U) +#define S50_ELS_KS2_KS2_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHKDF_SHIFT)) & S50_ELS_KS2_KS2_UHKDF_MASK) + +#define S50_ELS_KS2_KS2_UECSG_MASK (0x40000U) +#define S50_ELS_KS2_KS2_UECSG_SHIFT (18U) +#define S50_ELS_KS2_KS2_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECSG_SHIFT)) & S50_ELS_KS2_KS2_UECSG_MASK) + +#define S50_ELS_KS2_KS2_UECDH_MASK (0x80000U) +#define S50_ELS_KS2_KS2_UECDH_SHIFT (19U) +#define S50_ELS_KS2_KS2_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UECDH_SHIFT)) & S50_ELS_KS2_KS2_UECDH_MASK) + +#define S50_ELS_KS2_KS2_UAES_MASK (0x100000U) +#define S50_ELS_KS2_KS2_UAES_SHIFT (20U) +#define S50_ELS_KS2_KS2_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UAES_SHIFT)) & S50_ELS_KS2_KS2_UAES_MASK) + +#define S50_ELS_KS2_KS2_UHMAC_MASK (0x200000U) +#define S50_ELS_KS2_KS2_UHMAC_SHIFT (21U) +#define S50_ELS_KS2_KS2_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHMAC_SHIFT)) & S50_ELS_KS2_KS2_UHMAC_MASK) + +#define S50_ELS_KS2_KS2_UKWK_MASK (0x400000U) +#define S50_ELS_KS2_KS2_UKWK_SHIFT (22U) +#define S50_ELS_KS2_KS2_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKWK_SHIFT)) & S50_ELS_KS2_KS2_UKWK_MASK) + +#define S50_ELS_KS2_KS2_UKUOK_MASK (0x800000U) +#define S50_ELS_KS2_KS2_UKUOK_SHIFT (23U) +#define S50_ELS_KS2_KS2_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKUOK_SHIFT)) & S50_ELS_KS2_KS2_UKUOK_MASK) + +#define S50_ELS_KS2_KS2_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS2_KS2_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS2_KS2_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSPMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSPMS_MASK) + +#define S50_ELS_KS2_KS2_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS2_KS2_UTLSMS_SHIFT (25U) +#define S50_ELS_KS2_KS2_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UTLSMS_SHIFT)) & S50_ELS_KS2_KS2_UTLSMS_MASK) + +#define S50_ELS_KS2_KS2_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS2_KS2_UKGSRC_SHIFT (26U) +#define S50_ELS_KS2_KS2_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UKGSRC_SHIFT)) & S50_ELS_KS2_KS2_UKGSRC_MASK) + +#define S50_ELS_KS2_KS2_UHWO_MASK (0x8000000U) +#define S50_ELS_KS2_KS2_UHWO_SHIFT (27U) +#define S50_ELS_KS2_KS2_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UHWO_SHIFT)) & S50_ELS_KS2_KS2_UHWO_MASK) + +#define S50_ELS_KS2_KS2_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS2_KS2_UWRPOK_SHIFT (28U) +#define S50_ELS_KS2_KS2_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UWRPOK_SHIFT)) & S50_ELS_KS2_KS2_UWRPOK_MASK) + +#define S50_ELS_KS2_KS2_UDUK_MASK (0x20000000U) +#define S50_ELS_KS2_KS2_UDUK_SHIFT (29U) +#define S50_ELS_KS2_KS2_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UDUK_SHIFT)) & S50_ELS_KS2_KS2_UDUK_MASK) + +#define S50_ELS_KS2_KS2_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS2_KS2_UPPROT_SHIFT (30U) +#define S50_ELS_KS2_KS2_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS2_KS2_UPPROT_SHIFT)) & S50_ELS_KS2_KS2_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS3 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS3_KS3_KSIZE_MASK (0x3U) +#define S50_ELS_KS3_KS3_KSIZE_SHIFT (0U) +/*! KS3_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS3_KS3_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KSIZE_SHIFT)) & S50_ELS_KS3_KS3_KSIZE_MASK) + +#define S50_ELS_KS3_KS3_KACT_MASK (0x20U) +#define S50_ELS_KS3_KS3_KACT_SHIFT (5U) +#define S50_ELS_KS3_KS3_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KACT_SHIFT)) & S50_ELS_KS3_KS3_KACT_MASK) + +#define S50_ELS_KS3_KS3_KBASE_MASK (0x40U) +#define S50_ELS_KS3_KS3_KBASE_SHIFT (6U) +#define S50_ELS_KS3_KS3_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_KBASE_SHIFT)) & S50_ELS_KS3_KS3_KBASE_MASK) + +#define S50_ELS_KS3_KS3_FGP_MASK (0x80U) +#define S50_ELS_KS3_KS3_FGP_SHIFT (7U) +#define S50_ELS_KS3_KS3_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FGP_SHIFT)) & S50_ELS_KS3_KS3_FGP_MASK) + +#define S50_ELS_KS3_KS3_FRTN_MASK (0x100U) +#define S50_ELS_KS3_KS3_FRTN_SHIFT (8U) +#define S50_ELS_KS3_KS3_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FRTN_SHIFT)) & S50_ELS_KS3_KS3_FRTN_MASK) + +#define S50_ELS_KS3_KS3_FHWO_MASK (0x200U) +#define S50_ELS_KS3_KS3_FHWO_SHIFT (9U) +#define S50_ELS_KS3_KS3_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_FHWO_SHIFT)) & S50_ELS_KS3_KS3_FHWO_MASK) + +#define S50_ELS_KS3_KS3_UKPUK_MASK (0x800U) +#define S50_ELS_KS3_KS3_UKPUK_SHIFT (11U) +#define S50_ELS_KS3_KS3_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKPUK_SHIFT)) & S50_ELS_KS3_KS3_UKPUK_MASK) + +#define S50_ELS_KS3_KS3_UTECDH_MASK (0x1000U) +#define S50_ELS_KS3_KS3_UTECDH_SHIFT (12U) +#define S50_ELS_KS3_KS3_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTECDH_SHIFT)) & S50_ELS_KS3_KS3_UTECDH_MASK) + +#define S50_ELS_KS3_KS3_UCMAC_MASK (0x2000U) +#define S50_ELS_KS3_KS3_UCMAC_SHIFT (13U) +#define S50_ELS_KS3_KS3_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCMAC_SHIFT)) & S50_ELS_KS3_KS3_UCMAC_MASK) + +#define S50_ELS_KS3_KS3_UKSK_MASK (0x4000U) +#define S50_ELS_KS3_KS3_UKSK_SHIFT (14U) +#define S50_ELS_KS3_KS3_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKSK_SHIFT)) & S50_ELS_KS3_KS3_UKSK_MASK) + +#define S50_ELS_KS3_KS3_URTF_MASK (0x8000U) +#define S50_ELS_KS3_KS3_URTF_SHIFT (15U) +#define S50_ELS_KS3_KS3_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_URTF_SHIFT)) & S50_ELS_KS3_KS3_URTF_MASK) + +#define S50_ELS_KS3_KS3_UCKDF_MASK (0x10000U) +#define S50_ELS_KS3_KS3_UCKDF_SHIFT (16U) +#define S50_ELS_KS3_KS3_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UCKDF_SHIFT)) & S50_ELS_KS3_KS3_UCKDF_MASK) + +#define S50_ELS_KS3_KS3_UHKDF_MASK (0x20000U) +#define S50_ELS_KS3_KS3_UHKDF_SHIFT (17U) +#define S50_ELS_KS3_KS3_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHKDF_SHIFT)) & S50_ELS_KS3_KS3_UHKDF_MASK) + +#define S50_ELS_KS3_KS3_UECSG_MASK (0x40000U) +#define S50_ELS_KS3_KS3_UECSG_SHIFT (18U) +#define S50_ELS_KS3_KS3_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECSG_SHIFT)) & S50_ELS_KS3_KS3_UECSG_MASK) + +#define S50_ELS_KS3_KS3_UECDH_MASK (0x80000U) +#define S50_ELS_KS3_KS3_UECDH_SHIFT (19U) +#define S50_ELS_KS3_KS3_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UECDH_SHIFT)) & S50_ELS_KS3_KS3_UECDH_MASK) + +#define S50_ELS_KS3_KS3_UAES_MASK (0x100000U) +#define S50_ELS_KS3_KS3_UAES_SHIFT (20U) +#define S50_ELS_KS3_KS3_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UAES_SHIFT)) & S50_ELS_KS3_KS3_UAES_MASK) + +#define S50_ELS_KS3_KS3_UHMAC_MASK (0x200000U) +#define S50_ELS_KS3_KS3_UHMAC_SHIFT (21U) +#define S50_ELS_KS3_KS3_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHMAC_SHIFT)) & S50_ELS_KS3_KS3_UHMAC_MASK) + +#define S50_ELS_KS3_KS3_UKWK_MASK (0x400000U) +#define S50_ELS_KS3_KS3_UKWK_SHIFT (22U) +#define S50_ELS_KS3_KS3_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKWK_SHIFT)) & S50_ELS_KS3_KS3_UKWK_MASK) + +#define S50_ELS_KS3_KS3_UKUOK_MASK (0x800000U) +#define S50_ELS_KS3_KS3_UKUOK_SHIFT (23U) +#define S50_ELS_KS3_KS3_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKUOK_SHIFT)) & S50_ELS_KS3_KS3_UKUOK_MASK) + +#define S50_ELS_KS3_KS3_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS3_KS3_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS3_KS3_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSPMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSPMS_MASK) + +#define S50_ELS_KS3_KS3_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS3_KS3_UTLSMS_SHIFT (25U) +#define S50_ELS_KS3_KS3_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UTLSMS_SHIFT)) & S50_ELS_KS3_KS3_UTLSMS_MASK) + +#define S50_ELS_KS3_KS3_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS3_KS3_UKGSRC_SHIFT (26U) +#define S50_ELS_KS3_KS3_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UKGSRC_SHIFT)) & S50_ELS_KS3_KS3_UKGSRC_MASK) + +#define S50_ELS_KS3_KS3_UHWO_MASK (0x8000000U) +#define S50_ELS_KS3_KS3_UHWO_SHIFT (27U) +#define S50_ELS_KS3_KS3_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UHWO_SHIFT)) & S50_ELS_KS3_KS3_UHWO_MASK) + +#define S50_ELS_KS3_KS3_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS3_KS3_UWRPOK_SHIFT (28U) +#define S50_ELS_KS3_KS3_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UWRPOK_SHIFT)) & S50_ELS_KS3_KS3_UWRPOK_MASK) + +#define S50_ELS_KS3_KS3_UDUK_MASK (0x20000000U) +#define S50_ELS_KS3_KS3_UDUK_SHIFT (29U) +#define S50_ELS_KS3_KS3_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UDUK_SHIFT)) & S50_ELS_KS3_KS3_UDUK_MASK) + +#define S50_ELS_KS3_KS3_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS3_KS3_UPPROT_SHIFT (30U) +#define S50_ELS_KS3_KS3_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS3_KS3_UPPROT_SHIFT)) & S50_ELS_KS3_KS3_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS4 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS4_KS4_KSIZE_MASK (0x3U) +#define S50_ELS_KS4_KS4_KSIZE_SHIFT (0U) +/*! KS4_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS4_KS4_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KSIZE_SHIFT)) & S50_ELS_KS4_KS4_KSIZE_MASK) + +#define S50_ELS_KS4_KS4_KACT_MASK (0x20U) +#define S50_ELS_KS4_KS4_KACT_SHIFT (5U) +#define S50_ELS_KS4_KS4_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KACT_SHIFT)) & S50_ELS_KS4_KS4_KACT_MASK) + +#define S50_ELS_KS4_KS4_KBASE_MASK (0x40U) +#define S50_ELS_KS4_KS4_KBASE_SHIFT (6U) +#define S50_ELS_KS4_KS4_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_KBASE_SHIFT)) & S50_ELS_KS4_KS4_KBASE_MASK) + +#define S50_ELS_KS4_KS4_FGP_MASK (0x80U) +#define S50_ELS_KS4_KS4_FGP_SHIFT (7U) +#define S50_ELS_KS4_KS4_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FGP_SHIFT)) & S50_ELS_KS4_KS4_FGP_MASK) + +#define S50_ELS_KS4_KS4_FRTN_MASK (0x100U) +#define S50_ELS_KS4_KS4_FRTN_SHIFT (8U) +#define S50_ELS_KS4_KS4_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FRTN_SHIFT)) & S50_ELS_KS4_KS4_FRTN_MASK) + +#define S50_ELS_KS4_KS4_FHWO_MASK (0x200U) +#define S50_ELS_KS4_KS4_FHWO_SHIFT (9U) +#define S50_ELS_KS4_KS4_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_FHWO_SHIFT)) & S50_ELS_KS4_KS4_FHWO_MASK) + +#define S50_ELS_KS4_KS4_UKPUK_MASK (0x800U) +#define S50_ELS_KS4_KS4_UKPUK_SHIFT (11U) +#define S50_ELS_KS4_KS4_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKPUK_SHIFT)) & S50_ELS_KS4_KS4_UKPUK_MASK) + +#define S50_ELS_KS4_KS4_UTECDH_MASK (0x1000U) +#define S50_ELS_KS4_KS4_UTECDH_SHIFT (12U) +#define S50_ELS_KS4_KS4_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTECDH_SHIFT)) & S50_ELS_KS4_KS4_UTECDH_MASK) + +#define S50_ELS_KS4_KS4_UCMAC_MASK (0x2000U) +#define S50_ELS_KS4_KS4_UCMAC_SHIFT (13U) +#define S50_ELS_KS4_KS4_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCMAC_SHIFT)) & S50_ELS_KS4_KS4_UCMAC_MASK) + +#define S50_ELS_KS4_KS4_UKSK_MASK (0x4000U) +#define S50_ELS_KS4_KS4_UKSK_SHIFT (14U) +#define S50_ELS_KS4_KS4_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKSK_SHIFT)) & S50_ELS_KS4_KS4_UKSK_MASK) + +#define S50_ELS_KS4_KS4_URTF_MASK (0x8000U) +#define S50_ELS_KS4_KS4_URTF_SHIFT (15U) +#define S50_ELS_KS4_KS4_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_URTF_SHIFT)) & S50_ELS_KS4_KS4_URTF_MASK) + +#define S50_ELS_KS4_KS4_UCKDF_MASK (0x10000U) +#define S50_ELS_KS4_KS4_UCKDF_SHIFT (16U) +#define S50_ELS_KS4_KS4_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UCKDF_SHIFT)) & S50_ELS_KS4_KS4_UCKDF_MASK) + +#define S50_ELS_KS4_KS4_UHKDF_MASK (0x20000U) +#define S50_ELS_KS4_KS4_UHKDF_SHIFT (17U) +#define S50_ELS_KS4_KS4_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHKDF_SHIFT)) & S50_ELS_KS4_KS4_UHKDF_MASK) + +#define S50_ELS_KS4_KS4_UECSG_MASK (0x40000U) +#define S50_ELS_KS4_KS4_UECSG_SHIFT (18U) +#define S50_ELS_KS4_KS4_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECSG_SHIFT)) & S50_ELS_KS4_KS4_UECSG_MASK) + +#define S50_ELS_KS4_KS4_UECDH_MASK (0x80000U) +#define S50_ELS_KS4_KS4_UECDH_SHIFT (19U) +#define S50_ELS_KS4_KS4_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UECDH_SHIFT)) & S50_ELS_KS4_KS4_UECDH_MASK) + +#define S50_ELS_KS4_KS4_UAES_MASK (0x100000U) +#define S50_ELS_KS4_KS4_UAES_SHIFT (20U) +#define S50_ELS_KS4_KS4_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UAES_SHIFT)) & S50_ELS_KS4_KS4_UAES_MASK) + +#define S50_ELS_KS4_KS4_UHMAC_MASK (0x200000U) +#define S50_ELS_KS4_KS4_UHMAC_SHIFT (21U) +#define S50_ELS_KS4_KS4_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHMAC_SHIFT)) & S50_ELS_KS4_KS4_UHMAC_MASK) + +#define S50_ELS_KS4_KS4_UKWK_MASK (0x400000U) +#define S50_ELS_KS4_KS4_UKWK_SHIFT (22U) +#define S50_ELS_KS4_KS4_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKWK_SHIFT)) & S50_ELS_KS4_KS4_UKWK_MASK) + +#define S50_ELS_KS4_KS4_UKUOK_MASK (0x800000U) +#define S50_ELS_KS4_KS4_UKUOK_SHIFT (23U) +#define S50_ELS_KS4_KS4_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKUOK_SHIFT)) & S50_ELS_KS4_KS4_UKUOK_MASK) + +#define S50_ELS_KS4_KS4_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS4_KS4_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS4_KS4_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSPMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSPMS_MASK) + +#define S50_ELS_KS4_KS4_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS4_KS4_UTLSMS_SHIFT (25U) +#define S50_ELS_KS4_KS4_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UTLSMS_SHIFT)) & S50_ELS_KS4_KS4_UTLSMS_MASK) + +#define S50_ELS_KS4_KS4_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS4_KS4_UKGSRC_SHIFT (26U) +#define S50_ELS_KS4_KS4_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UKGSRC_SHIFT)) & S50_ELS_KS4_KS4_UKGSRC_MASK) + +#define S50_ELS_KS4_KS4_UHWO_MASK (0x8000000U) +#define S50_ELS_KS4_KS4_UHWO_SHIFT (27U) +#define S50_ELS_KS4_KS4_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UHWO_SHIFT)) & S50_ELS_KS4_KS4_UHWO_MASK) + +#define S50_ELS_KS4_KS4_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS4_KS4_UWRPOK_SHIFT (28U) +#define S50_ELS_KS4_KS4_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UWRPOK_SHIFT)) & S50_ELS_KS4_KS4_UWRPOK_MASK) + +#define S50_ELS_KS4_KS4_UDUK_MASK (0x20000000U) +#define S50_ELS_KS4_KS4_UDUK_SHIFT (29U) +#define S50_ELS_KS4_KS4_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UDUK_SHIFT)) & S50_ELS_KS4_KS4_UDUK_MASK) + +#define S50_ELS_KS4_KS4_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS4_KS4_UPPROT_SHIFT (30U) +#define S50_ELS_KS4_KS4_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS4_KS4_UPPROT_SHIFT)) & S50_ELS_KS4_KS4_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS5 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS5_KS5_KSIZE_MASK (0x3U) +#define S50_ELS_KS5_KS5_KSIZE_SHIFT (0U) +/*! KS5_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS5_KS5_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KSIZE_SHIFT)) & S50_ELS_KS5_KS5_KSIZE_MASK) + +#define S50_ELS_KS5_KS5_KACT_MASK (0x20U) +#define S50_ELS_KS5_KS5_KACT_SHIFT (5U) +#define S50_ELS_KS5_KS5_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KACT_SHIFT)) & S50_ELS_KS5_KS5_KACT_MASK) + +#define S50_ELS_KS5_KS5_KBASE_MASK (0x40U) +#define S50_ELS_KS5_KS5_KBASE_SHIFT (6U) +#define S50_ELS_KS5_KS5_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_KBASE_SHIFT)) & S50_ELS_KS5_KS5_KBASE_MASK) + +#define S50_ELS_KS5_KS5_FGP_MASK (0x80U) +#define S50_ELS_KS5_KS5_FGP_SHIFT (7U) +#define S50_ELS_KS5_KS5_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FGP_SHIFT)) & S50_ELS_KS5_KS5_FGP_MASK) + +#define S50_ELS_KS5_KS5_FRTN_MASK (0x100U) +#define S50_ELS_KS5_KS5_FRTN_SHIFT (8U) +#define S50_ELS_KS5_KS5_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FRTN_SHIFT)) & S50_ELS_KS5_KS5_FRTN_MASK) + +#define S50_ELS_KS5_KS5_FHWO_MASK (0x200U) +#define S50_ELS_KS5_KS5_FHWO_SHIFT (9U) +#define S50_ELS_KS5_KS5_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_FHWO_SHIFT)) & S50_ELS_KS5_KS5_FHWO_MASK) + +#define S50_ELS_KS5_KS5_UKPUK_MASK (0x800U) +#define S50_ELS_KS5_KS5_UKPUK_SHIFT (11U) +#define S50_ELS_KS5_KS5_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKPUK_SHIFT)) & S50_ELS_KS5_KS5_UKPUK_MASK) + +#define S50_ELS_KS5_KS5_UTECDH_MASK (0x1000U) +#define S50_ELS_KS5_KS5_UTECDH_SHIFT (12U) +#define S50_ELS_KS5_KS5_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTECDH_SHIFT)) & S50_ELS_KS5_KS5_UTECDH_MASK) + +#define S50_ELS_KS5_KS5_UCMAC_MASK (0x2000U) +#define S50_ELS_KS5_KS5_UCMAC_SHIFT (13U) +#define S50_ELS_KS5_KS5_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCMAC_SHIFT)) & S50_ELS_KS5_KS5_UCMAC_MASK) + +#define S50_ELS_KS5_KS5_UKSK_MASK (0x4000U) +#define S50_ELS_KS5_KS5_UKSK_SHIFT (14U) +#define S50_ELS_KS5_KS5_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKSK_SHIFT)) & S50_ELS_KS5_KS5_UKSK_MASK) + +#define S50_ELS_KS5_KS5_URTF_MASK (0x8000U) +#define S50_ELS_KS5_KS5_URTF_SHIFT (15U) +#define S50_ELS_KS5_KS5_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_URTF_SHIFT)) & S50_ELS_KS5_KS5_URTF_MASK) + +#define S50_ELS_KS5_KS5_UCKDF_MASK (0x10000U) +#define S50_ELS_KS5_KS5_UCKDF_SHIFT (16U) +#define S50_ELS_KS5_KS5_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UCKDF_SHIFT)) & S50_ELS_KS5_KS5_UCKDF_MASK) + +#define S50_ELS_KS5_KS5_UHKDF_MASK (0x20000U) +#define S50_ELS_KS5_KS5_UHKDF_SHIFT (17U) +#define S50_ELS_KS5_KS5_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHKDF_SHIFT)) & S50_ELS_KS5_KS5_UHKDF_MASK) + +#define S50_ELS_KS5_KS5_UECSG_MASK (0x40000U) +#define S50_ELS_KS5_KS5_UECSG_SHIFT (18U) +#define S50_ELS_KS5_KS5_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECSG_SHIFT)) & S50_ELS_KS5_KS5_UECSG_MASK) + +#define S50_ELS_KS5_KS5_UECDH_MASK (0x80000U) +#define S50_ELS_KS5_KS5_UECDH_SHIFT (19U) +#define S50_ELS_KS5_KS5_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UECDH_SHIFT)) & S50_ELS_KS5_KS5_UECDH_MASK) + +#define S50_ELS_KS5_KS5_UAES_MASK (0x100000U) +#define S50_ELS_KS5_KS5_UAES_SHIFT (20U) +#define S50_ELS_KS5_KS5_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UAES_SHIFT)) & S50_ELS_KS5_KS5_UAES_MASK) + +#define S50_ELS_KS5_KS5_UHMAC_MASK (0x200000U) +#define S50_ELS_KS5_KS5_UHMAC_SHIFT (21U) +#define S50_ELS_KS5_KS5_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHMAC_SHIFT)) & S50_ELS_KS5_KS5_UHMAC_MASK) + +#define S50_ELS_KS5_KS5_UKWK_MASK (0x400000U) +#define S50_ELS_KS5_KS5_UKWK_SHIFT (22U) +#define S50_ELS_KS5_KS5_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKWK_SHIFT)) & S50_ELS_KS5_KS5_UKWK_MASK) + +#define S50_ELS_KS5_KS5_UKUOK_MASK (0x800000U) +#define S50_ELS_KS5_KS5_UKUOK_SHIFT (23U) +#define S50_ELS_KS5_KS5_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKUOK_SHIFT)) & S50_ELS_KS5_KS5_UKUOK_MASK) + +#define S50_ELS_KS5_KS5_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS5_KS5_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS5_KS5_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSPMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSPMS_MASK) + +#define S50_ELS_KS5_KS5_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS5_KS5_UTLSMS_SHIFT (25U) +#define S50_ELS_KS5_KS5_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UTLSMS_SHIFT)) & S50_ELS_KS5_KS5_UTLSMS_MASK) + +#define S50_ELS_KS5_KS5_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS5_KS5_UKGSRC_SHIFT (26U) +#define S50_ELS_KS5_KS5_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UKGSRC_SHIFT)) & S50_ELS_KS5_KS5_UKGSRC_MASK) + +#define S50_ELS_KS5_KS5_UHWO_MASK (0x8000000U) +#define S50_ELS_KS5_KS5_UHWO_SHIFT (27U) +#define S50_ELS_KS5_KS5_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UHWO_SHIFT)) & S50_ELS_KS5_KS5_UHWO_MASK) + +#define S50_ELS_KS5_KS5_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS5_KS5_UWRPOK_SHIFT (28U) +#define S50_ELS_KS5_KS5_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UWRPOK_SHIFT)) & S50_ELS_KS5_KS5_UWRPOK_MASK) + +#define S50_ELS_KS5_KS5_UDUK_MASK (0x20000000U) +#define S50_ELS_KS5_KS5_UDUK_SHIFT (29U) +#define S50_ELS_KS5_KS5_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UDUK_SHIFT)) & S50_ELS_KS5_KS5_UDUK_MASK) + +#define S50_ELS_KS5_KS5_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS5_KS5_UPPROT_SHIFT (30U) +#define S50_ELS_KS5_KS5_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS5_KS5_UPPROT_SHIFT)) & S50_ELS_KS5_KS5_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS6 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS6_KS6_KSIZE_MASK (0x3U) +#define S50_ELS_KS6_KS6_KSIZE_SHIFT (0U) +/*! KS6_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS6_KS6_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KSIZE_SHIFT)) & S50_ELS_KS6_KS6_KSIZE_MASK) + +#define S50_ELS_KS6_KS6_KACT_MASK (0x20U) +#define S50_ELS_KS6_KS6_KACT_SHIFT (5U) +#define S50_ELS_KS6_KS6_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KACT_SHIFT)) & S50_ELS_KS6_KS6_KACT_MASK) + +#define S50_ELS_KS6_KS6_KBASE_MASK (0x40U) +#define S50_ELS_KS6_KS6_KBASE_SHIFT (6U) +#define S50_ELS_KS6_KS6_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_KBASE_SHIFT)) & S50_ELS_KS6_KS6_KBASE_MASK) + +#define S50_ELS_KS6_KS6_FGP_MASK (0x80U) +#define S50_ELS_KS6_KS6_FGP_SHIFT (7U) +#define S50_ELS_KS6_KS6_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FGP_SHIFT)) & S50_ELS_KS6_KS6_FGP_MASK) + +#define S50_ELS_KS6_KS6_FRTN_MASK (0x100U) +#define S50_ELS_KS6_KS6_FRTN_SHIFT (8U) +#define S50_ELS_KS6_KS6_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FRTN_SHIFT)) & S50_ELS_KS6_KS6_FRTN_MASK) + +#define S50_ELS_KS6_KS6_FHWO_MASK (0x200U) +#define S50_ELS_KS6_KS6_FHWO_SHIFT (9U) +#define S50_ELS_KS6_KS6_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_FHWO_SHIFT)) & S50_ELS_KS6_KS6_FHWO_MASK) + +#define S50_ELS_KS6_KS6_UKPUK_MASK (0x800U) +#define S50_ELS_KS6_KS6_UKPUK_SHIFT (11U) +#define S50_ELS_KS6_KS6_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKPUK_SHIFT)) & S50_ELS_KS6_KS6_UKPUK_MASK) + +#define S50_ELS_KS6_KS6_UTECDH_MASK (0x1000U) +#define S50_ELS_KS6_KS6_UTECDH_SHIFT (12U) +#define S50_ELS_KS6_KS6_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTECDH_SHIFT)) & S50_ELS_KS6_KS6_UTECDH_MASK) + +#define S50_ELS_KS6_KS6_UCMAC_MASK (0x2000U) +#define S50_ELS_KS6_KS6_UCMAC_SHIFT (13U) +#define S50_ELS_KS6_KS6_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCMAC_SHIFT)) & S50_ELS_KS6_KS6_UCMAC_MASK) + +#define S50_ELS_KS6_KS6_UKSK_MASK (0x4000U) +#define S50_ELS_KS6_KS6_UKSK_SHIFT (14U) +#define S50_ELS_KS6_KS6_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKSK_SHIFT)) & S50_ELS_KS6_KS6_UKSK_MASK) + +#define S50_ELS_KS6_KS6_URTF_MASK (0x8000U) +#define S50_ELS_KS6_KS6_URTF_SHIFT (15U) +#define S50_ELS_KS6_KS6_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_URTF_SHIFT)) & S50_ELS_KS6_KS6_URTF_MASK) + +#define S50_ELS_KS6_KS6_UCKDF_MASK (0x10000U) +#define S50_ELS_KS6_KS6_UCKDF_SHIFT (16U) +#define S50_ELS_KS6_KS6_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UCKDF_SHIFT)) & S50_ELS_KS6_KS6_UCKDF_MASK) + +#define S50_ELS_KS6_KS6_UHKDF_MASK (0x20000U) +#define S50_ELS_KS6_KS6_UHKDF_SHIFT (17U) +#define S50_ELS_KS6_KS6_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHKDF_SHIFT)) & S50_ELS_KS6_KS6_UHKDF_MASK) + +#define S50_ELS_KS6_KS6_UECSG_MASK (0x40000U) +#define S50_ELS_KS6_KS6_UECSG_SHIFT (18U) +#define S50_ELS_KS6_KS6_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECSG_SHIFT)) & S50_ELS_KS6_KS6_UECSG_MASK) + +#define S50_ELS_KS6_KS6_UECDH_MASK (0x80000U) +#define S50_ELS_KS6_KS6_UECDH_SHIFT (19U) +#define S50_ELS_KS6_KS6_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UECDH_SHIFT)) & S50_ELS_KS6_KS6_UECDH_MASK) + +#define S50_ELS_KS6_KS6_UAES_MASK (0x100000U) +#define S50_ELS_KS6_KS6_UAES_SHIFT (20U) +#define S50_ELS_KS6_KS6_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UAES_SHIFT)) & S50_ELS_KS6_KS6_UAES_MASK) + +#define S50_ELS_KS6_KS6_UHMAC_MASK (0x200000U) +#define S50_ELS_KS6_KS6_UHMAC_SHIFT (21U) +#define S50_ELS_KS6_KS6_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHMAC_SHIFT)) & S50_ELS_KS6_KS6_UHMAC_MASK) + +#define S50_ELS_KS6_KS6_UKWK_MASK (0x400000U) +#define S50_ELS_KS6_KS6_UKWK_SHIFT (22U) +#define S50_ELS_KS6_KS6_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKWK_SHIFT)) & S50_ELS_KS6_KS6_UKWK_MASK) + +#define S50_ELS_KS6_KS6_UKUOK_MASK (0x800000U) +#define S50_ELS_KS6_KS6_UKUOK_SHIFT (23U) +#define S50_ELS_KS6_KS6_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKUOK_SHIFT)) & S50_ELS_KS6_KS6_UKUOK_MASK) + +#define S50_ELS_KS6_KS6_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS6_KS6_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS6_KS6_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSPMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSPMS_MASK) + +#define S50_ELS_KS6_KS6_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS6_KS6_UTLSMS_SHIFT (25U) +#define S50_ELS_KS6_KS6_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UTLSMS_SHIFT)) & S50_ELS_KS6_KS6_UTLSMS_MASK) + +#define S50_ELS_KS6_KS6_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS6_KS6_UKGSRC_SHIFT (26U) +#define S50_ELS_KS6_KS6_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UKGSRC_SHIFT)) & S50_ELS_KS6_KS6_UKGSRC_MASK) + +#define S50_ELS_KS6_KS6_UHWO_MASK (0x8000000U) +#define S50_ELS_KS6_KS6_UHWO_SHIFT (27U) +#define S50_ELS_KS6_KS6_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UHWO_SHIFT)) & S50_ELS_KS6_KS6_UHWO_MASK) + +#define S50_ELS_KS6_KS6_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS6_KS6_UWRPOK_SHIFT (28U) +#define S50_ELS_KS6_KS6_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UWRPOK_SHIFT)) & S50_ELS_KS6_KS6_UWRPOK_MASK) + +#define S50_ELS_KS6_KS6_UDUK_MASK (0x20000000U) +#define S50_ELS_KS6_KS6_UDUK_SHIFT (29U) +#define S50_ELS_KS6_KS6_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UDUK_SHIFT)) & S50_ELS_KS6_KS6_UDUK_MASK) + +#define S50_ELS_KS6_KS6_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS6_KS6_UPPROT_SHIFT (30U) +#define S50_ELS_KS6_KS6_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS6_KS6_UPPROT_SHIFT)) & S50_ELS_KS6_KS6_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS7 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS7_KS7_KSIZE_MASK (0x3U) +#define S50_ELS_KS7_KS7_KSIZE_SHIFT (0U) +/*! KS7_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS7_KS7_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KSIZE_SHIFT)) & S50_ELS_KS7_KS7_KSIZE_MASK) + +#define S50_ELS_KS7_KS7_KACT_MASK (0x20U) +#define S50_ELS_KS7_KS7_KACT_SHIFT (5U) +#define S50_ELS_KS7_KS7_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KACT_SHIFT)) & S50_ELS_KS7_KS7_KACT_MASK) + +#define S50_ELS_KS7_KS7_KBASE_MASK (0x40U) +#define S50_ELS_KS7_KS7_KBASE_SHIFT (6U) +#define S50_ELS_KS7_KS7_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_KBASE_SHIFT)) & S50_ELS_KS7_KS7_KBASE_MASK) + +#define S50_ELS_KS7_KS7_FGP_MASK (0x80U) +#define S50_ELS_KS7_KS7_FGP_SHIFT (7U) +#define S50_ELS_KS7_KS7_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FGP_SHIFT)) & S50_ELS_KS7_KS7_FGP_MASK) + +#define S50_ELS_KS7_KS7_FRTN_MASK (0x100U) +#define S50_ELS_KS7_KS7_FRTN_SHIFT (8U) +#define S50_ELS_KS7_KS7_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FRTN_SHIFT)) & S50_ELS_KS7_KS7_FRTN_MASK) + +#define S50_ELS_KS7_KS7_FHWO_MASK (0x200U) +#define S50_ELS_KS7_KS7_FHWO_SHIFT (9U) +#define S50_ELS_KS7_KS7_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_FHWO_SHIFT)) & S50_ELS_KS7_KS7_FHWO_MASK) + +#define S50_ELS_KS7_KS7_UKPUK_MASK (0x800U) +#define S50_ELS_KS7_KS7_UKPUK_SHIFT (11U) +#define S50_ELS_KS7_KS7_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKPUK_SHIFT)) & S50_ELS_KS7_KS7_UKPUK_MASK) + +#define S50_ELS_KS7_KS7_UTECDH_MASK (0x1000U) +#define S50_ELS_KS7_KS7_UTECDH_SHIFT (12U) +#define S50_ELS_KS7_KS7_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTECDH_SHIFT)) & S50_ELS_KS7_KS7_UTECDH_MASK) + +#define S50_ELS_KS7_KS7_UCMAC_MASK (0x2000U) +#define S50_ELS_KS7_KS7_UCMAC_SHIFT (13U) +#define S50_ELS_KS7_KS7_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCMAC_SHIFT)) & S50_ELS_KS7_KS7_UCMAC_MASK) + +#define S50_ELS_KS7_KS7_UKSK_MASK (0x4000U) +#define S50_ELS_KS7_KS7_UKSK_SHIFT (14U) +#define S50_ELS_KS7_KS7_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKSK_SHIFT)) & S50_ELS_KS7_KS7_UKSK_MASK) + +#define S50_ELS_KS7_KS7_URTF_MASK (0x8000U) +#define S50_ELS_KS7_KS7_URTF_SHIFT (15U) +#define S50_ELS_KS7_KS7_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_URTF_SHIFT)) & S50_ELS_KS7_KS7_URTF_MASK) + +#define S50_ELS_KS7_KS7_UCKDF_MASK (0x10000U) +#define S50_ELS_KS7_KS7_UCKDF_SHIFT (16U) +#define S50_ELS_KS7_KS7_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UCKDF_SHIFT)) & S50_ELS_KS7_KS7_UCKDF_MASK) + +#define S50_ELS_KS7_KS7_UHKDF_MASK (0x20000U) +#define S50_ELS_KS7_KS7_UHKDF_SHIFT (17U) +#define S50_ELS_KS7_KS7_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHKDF_SHIFT)) & S50_ELS_KS7_KS7_UHKDF_MASK) + +#define S50_ELS_KS7_KS7_UECSG_MASK (0x40000U) +#define S50_ELS_KS7_KS7_UECSG_SHIFT (18U) +#define S50_ELS_KS7_KS7_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECSG_SHIFT)) & S50_ELS_KS7_KS7_UECSG_MASK) + +#define S50_ELS_KS7_KS7_UECDH_MASK (0x80000U) +#define S50_ELS_KS7_KS7_UECDH_SHIFT (19U) +#define S50_ELS_KS7_KS7_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UECDH_SHIFT)) & S50_ELS_KS7_KS7_UECDH_MASK) + +#define S50_ELS_KS7_KS7_UAES_MASK (0x100000U) +#define S50_ELS_KS7_KS7_UAES_SHIFT (20U) +#define S50_ELS_KS7_KS7_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UAES_SHIFT)) & S50_ELS_KS7_KS7_UAES_MASK) + +#define S50_ELS_KS7_KS7_UHMAC_MASK (0x200000U) +#define S50_ELS_KS7_KS7_UHMAC_SHIFT (21U) +#define S50_ELS_KS7_KS7_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHMAC_SHIFT)) & S50_ELS_KS7_KS7_UHMAC_MASK) + +#define S50_ELS_KS7_KS7_UKWK_MASK (0x400000U) +#define S50_ELS_KS7_KS7_UKWK_SHIFT (22U) +#define S50_ELS_KS7_KS7_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKWK_SHIFT)) & S50_ELS_KS7_KS7_UKWK_MASK) + +#define S50_ELS_KS7_KS7_UKUOK_MASK (0x800000U) +#define S50_ELS_KS7_KS7_UKUOK_SHIFT (23U) +#define S50_ELS_KS7_KS7_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKUOK_SHIFT)) & S50_ELS_KS7_KS7_UKUOK_MASK) + +#define S50_ELS_KS7_KS7_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS7_KS7_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS7_KS7_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSPMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSPMS_MASK) + +#define S50_ELS_KS7_KS7_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS7_KS7_UTLSMS_SHIFT (25U) +#define S50_ELS_KS7_KS7_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UTLSMS_SHIFT)) & S50_ELS_KS7_KS7_UTLSMS_MASK) + +#define S50_ELS_KS7_KS7_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS7_KS7_UKGSRC_SHIFT (26U) +#define S50_ELS_KS7_KS7_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UKGSRC_SHIFT)) & S50_ELS_KS7_KS7_UKGSRC_MASK) + +#define S50_ELS_KS7_KS7_UHWO_MASK (0x8000000U) +#define S50_ELS_KS7_KS7_UHWO_SHIFT (27U) +#define S50_ELS_KS7_KS7_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UHWO_SHIFT)) & S50_ELS_KS7_KS7_UHWO_MASK) + +#define S50_ELS_KS7_KS7_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS7_KS7_UWRPOK_SHIFT (28U) +#define S50_ELS_KS7_KS7_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UWRPOK_SHIFT)) & S50_ELS_KS7_KS7_UWRPOK_MASK) + +#define S50_ELS_KS7_KS7_UDUK_MASK (0x20000000U) +#define S50_ELS_KS7_KS7_UDUK_SHIFT (29U) +#define S50_ELS_KS7_KS7_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UDUK_SHIFT)) & S50_ELS_KS7_KS7_UDUK_MASK) + +#define S50_ELS_KS7_KS7_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS7_KS7_UPPROT_SHIFT (30U) +#define S50_ELS_KS7_KS7_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS7_KS7_UPPROT_SHIFT)) & S50_ELS_KS7_KS7_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS8 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS8_KS8_KSIZE_MASK (0x3U) +#define S50_ELS_KS8_KS8_KSIZE_SHIFT (0U) +/*! KS8_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS8_KS8_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KSIZE_SHIFT)) & S50_ELS_KS8_KS8_KSIZE_MASK) + +#define S50_ELS_KS8_KS8_KACT_MASK (0x20U) +#define S50_ELS_KS8_KS8_KACT_SHIFT (5U) +#define S50_ELS_KS8_KS8_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KACT_SHIFT)) & S50_ELS_KS8_KS8_KACT_MASK) + +#define S50_ELS_KS8_KS8_KBASE_MASK (0x40U) +#define S50_ELS_KS8_KS8_KBASE_SHIFT (6U) +#define S50_ELS_KS8_KS8_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_KBASE_SHIFT)) & S50_ELS_KS8_KS8_KBASE_MASK) + +#define S50_ELS_KS8_KS8_FGP_MASK (0x80U) +#define S50_ELS_KS8_KS8_FGP_SHIFT (7U) +#define S50_ELS_KS8_KS8_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FGP_SHIFT)) & S50_ELS_KS8_KS8_FGP_MASK) + +#define S50_ELS_KS8_KS8_FRTN_MASK (0x100U) +#define S50_ELS_KS8_KS8_FRTN_SHIFT (8U) +#define S50_ELS_KS8_KS8_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FRTN_SHIFT)) & S50_ELS_KS8_KS8_FRTN_MASK) + +#define S50_ELS_KS8_KS8_FHWO_MASK (0x200U) +#define S50_ELS_KS8_KS8_FHWO_SHIFT (9U) +#define S50_ELS_KS8_KS8_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_FHWO_SHIFT)) & S50_ELS_KS8_KS8_FHWO_MASK) + +#define S50_ELS_KS8_KS8_UKPUK_MASK (0x800U) +#define S50_ELS_KS8_KS8_UKPUK_SHIFT (11U) +#define S50_ELS_KS8_KS8_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKPUK_SHIFT)) & S50_ELS_KS8_KS8_UKPUK_MASK) + +#define S50_ELS_KS8_KS8_UTECDH_MASK (0x1000U) +#define S50_ELS_KS8_KS8_UTECDH_SHIFT (12U) +#define S50_ELS_KS8_KS8_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTECDH_SHIFT)) & S50_ELS_KS8_KS8_UTECDH_MASK) + +#define S50_ELS_KS8_KS8_UCMAC_MASK (0x2000U) +#define S50_ELS_KS8_KS8_UCMAC_SHIFT (13U) +#define S50_ELS_KS8_KS8_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCMAC_SHIFT)) & S50_ELS_KS8_KS8_UCMAC_MASK) + +#define S50_ELS_KS8_KS8_UKSK_MASK (0x4000U) +#define S50_ELS_KS8_KS8_UKSK_SHIFT (14U) +#define S50_ELS_KS8_KS8_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKSK_SHIFT)) & S50_ELS_KS8_KS8_UKSK_MASK) + +#define S50_ELS_KS8_KS8_URTF_MASK (0x8000U) +#define S50_ELS_KS8_KS8_URTF_SHIFT (15U) +#define S50_ELS_KS8_KS8_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_URTF_SHIFT)) & S50_ELS_KS8_KS8_URTF_MASK) + +#define S50_ELS_KS8_KS8_UCKDF_MASK (0x10000U) +#define S50_ELS_KS8_KS8_UCKDF_SHIFT (16U) +#define S50_ELS_KS8_KS8_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UCKDF_SHIFT)) & S50_ELS_KS8_KS8_UCKDF_MASK) + +#define S50_ELS_KS8_KS8_UHKDF_MASK (0x20000U) +#define S50_ELS_KS8_KS8_UHKDF_SHIFT (17U) +#define S50_ELS_KS8_KS8_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHKDF_SHIFT)) & S50_ELS_KS8_KS8_UHKDF_MASK) + +#define S50_ELS_KS8_KS8_UECSG_MASK (0x40000U) +#define S50_ELS_KS8_KS8_UECSG_SHIFT (18U) +#define S50_ELS_KS8_KS8_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECSG_SHIFT)) & S50_ELS_KS8_KS8_UECSG_MASK) + +#define S50_ELS_KS8_KS8_UECDH_MASK (0x80000U) +#define S50_ELS_KS8_KS8_UECDH_SHIFT (19U) +#define S50_ELS_KS8_KS8_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UECDH_SHIFT)) & S50_ELS_KS8_KS8_UECDH_MASK) + +#define S50_ELS_KS8_KS8_UAES_MASK (0x100000U) +#define S50_ELS_KS8_KS8_UAES_SHIFT (20U) +#define S50_ELS_KS8_KS8_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UAES_SHIFT)) & S50_ELS_KS8_KS8_UAES_MASK) + +#define S50_ELS_KS8_KS8_UHMAC_MASK (0x200000U) +#define S50_ELS_KS8_KS8_UHMAC_SHIFT (21U) +#define S50_ELS_KS8_KS8_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHMAC_SHIFT)) & S50_ELS_KS8_KS8_UHMAC_MASK) + +#define S50_ELS_KS8_KS8_UKWK_MASK (0x400000U) +#define S50_ELS_KS8_KS8_UKWK_SHIFT (22U) +#define S50_ELS_KS8_KS8_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKWK_SHIFT)) & S50_ELS_KS8_KS8_UKWK_MASK) + +#define S50_ELS_KS8_KS8_UKUOK_MASK (0x800000U) +#define S50_ELS_KS8_KS8_UKUOK_SHIFT (23U) +#define S50_ELS_KS8_KS8_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKUOK_SHIFT)) & S50_ELS_KS8_KS8_UKUOK_MASK) + +#define S50_ELS_KS8_KS8_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS8_KS8_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS8_KS8_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSPMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSPMS_MASK) + +#define S50_ELS_KS8_KS8_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS8_KS8_UTLSMS_SHIFT (25U) +#define S50_ELS_KS8_KS8_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UTLSMS_SHIFT)) & S50_ELS_KS8_KS8_UTLSMS_MASK) + +#define S50_ELS_KS8_KS8_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS8_KS8_UKGSRC_SHIFT (26U) +#define S50_ELS_KS8_KS8_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UKGSRC_SHIFT)) & S50_ELS_KS8_KS8_UKGSRC_MASK) + +#define S50_ELS_KS8_KS8_UHWO_MASK (0x8000000U) +#define S50_ELS_KS8_KS8_UHWO_SHIFT (27U) +#define S50_ELS_KS8_KS8_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UHWO_SHIFT)) & S50_ELS_KS8_KS8_UHWO_MASK) + +#define S50_ELS_KS8_KS8_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS8_KS8_UWRPOK_SHIFT (28U) +#define S50_ELS_KS8_KS8_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UWRPOK_SHIFT)) & S50_ELS_KS8_KS8_UWRPOK_MASK) + +#define S50_ELS_KS8_KS8_UDUK_MASK (0x20000000U) +#define S50_ELS_KS8_KS8_UDUK_SHIFT (29U) +#define S50_ELS_KS8_KS8_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UDUK_SHIFT)) & S50_ELS_KS8_KS8_UDUK_MASK) + +#define S50_ELS_KS8_KS8_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS8_KS8_UPPROT_SHIFT (30U) +#define S50_ELS_KS8_KS8_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS8_KS8_UPPROT_SHIFT)) & S50_ELS_KS8_KS8_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS9 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS9_KS9_KSIZE_MASK (0x3U) +#define S50_ELS_KS9_KS9_KSIZE_SHIFT (0U) +/*! KS9_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS9_KS9_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KSIZE_SHIFT)) & S50_ELS_KS9_KS9_KSIZE_MASK) + +#define S50_ELS_KS9_KS9_KACT_MASK (0x20U) +#define S50_ELS_KS9_KS9_KACT_SHIFT (5U) +#define S50_ELS_KS9_KS9_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KACT_SHIFT)) & S50_ELS_KS9_KS9_KACT_MASK) + +#define S50_ELS_KS9_KS9_KBASE_MASK (0x40U) +#define S50_ELS_KS9_KS9_KBASE_SHIFT (6U) +#define S50_ELS_KS9_KS9_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_KBASE_SHIFT)) & S50_ELS_KS9_KS9_KBASE_MASK) + +#define S50_ELS_KS9_KS9_FGP_MASK (0x80U) +#define S50_ELS_KS9_KS9_FGP_SHIFT (7U) +#define S50_ELS_KS9_KS9_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FGP_SHIFT)) & S50_ELS_KS9_KS9_FGP_MASK) + +#define S50_ELS_KS9_KS9_FRTN_MASK (0x100U) +#define S50_ELS_KS9_KS9_FRTN_SHIFT (8U) +#define S50_ELS_KS9_KS9_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FRTN_SHIFT)) & S50_ELS_KS9_KS9_FRTN_MASK) + +#define S50_ELS_KS9_KS9_FHWO_MASK (0x200U) +#define S50_ELS_KS9_KS9_FHWO_SHIFT (9U) +#define S50_ELS_KS9_KS9_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_FHWO_SHIFT)) & S50_ELS_KS9_KS9_FHWO_MASK) + +#define S50_ELS_KS9_KS9_UKPUK_MASK (0x800U) +#define S50_ELS_KS9_KS9_UKPUK_SHIFT (11U) +#define S50_ELS_KS9_KS9_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKPUK_SHIFT)) & S50_ELS_KS9_KS9_UKPUK_MASK) + +#define S50_ELS_KS9_KS9_UTECDH_MASK (0x1000U) +#define S50_ELS_KS9_KS9_UTECDH_SHIFT (12U) +#define S50_ELS_KS9_KS9_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTECDH_SHIFT)) & S50_ELS_KS9_KS9_UTECDH_MASK) + +#define S50_ELS_KS9_KS9_UCMAC_MASK (0x2000U) +#define S50_ELS_KS9_KS9_UCMAC_SHIFT (13U) +#define S50_ELS_KS9_KS9_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCMAC_SHIFT)) & S50_ELS_KS9_KS9_UCMAC_MASK) + +#define S50_ELS_KS9_KS9_UKSK_MASK (0x4000U) +#define S50_ELS_KS9_KS9_UKSK_SHIFT (14U) +#define S50_ELS_KS9_KS9_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKSK_SHIFT)) & S50_ELS_KS9_KS9_UKSK_MASK) + +#define S50_ELS_KS9_KS9_URTF_MASK (0x8000U) +#define S50_ELS_KS9_KS9_URTF_SHIFT (15U) +#define S50_ELS_KS9_KS9_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_URTF_SHIFT)) & S50_ELS_KS9_KS9_URTF_MASK) + +#define S50_ELS_KS9_KS9_UCKDF_MASK (0x10000U) +#define S50_ELS_KS9_KS9_UCKDF_SHIFT (16U) +#define S50_ELS_KS9_KS9_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UCKDF_SHIFT)) & S50_ELS_KS9_KS9_UCKDF_MASK) + +#define S50_ELS_KS9_KS9_UHKDF_MASK (0x20000U) +#define S50_ELS_KS9_KS9_UHKDF_SHIFT (17U) +#define S50_ELS_KS9_KS9_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHKDF_SHIFT)) & S50_ELS_KS9_KS9_UHKDF_MASK) + +#define S50_ELS_KS9_KS9_UECSG_MASK (0x40000U) +#define S50_ELS_KS9_KS9_UECSG_SHIFT (18U) +#define S50_ELS_KS9_KS9_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECSG_SHIFT)) & S50_ELS_KS9_KS9_UECSG_MASK) + +#define S50_ELS_KS9_KS9_UECDH_MASK (0x80000U) +#define S50_ELS_KS9_KS9_UECDH_SHIFT (19U) +#define S50_ELS_KS9_KS9_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UECDH_SHIFT)) & S50_ELS_KS9_KS9_UECDH_MASK) + +#define S50_ELS_KS9_KS9_UAES_MASK (0x100000U) +#define S50_ELS_KS9_KS9_UAES_SHIFT (20U) +#define S50_ELS_KS9_KS9_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UAES_SHIFT)) & S50_ELS_KS9_KS9_UAES_MASK) + +#define S50_ELS_KS9_KS9_UHMAC_MASK (0x200000U) +#define S50_ELS_KS9_KS9_UHMAC_SHIFT (21U) +#define S50_ELS_KS9_KS9_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHMAC_SHIFT)) & S50_ELS_KS9_KS9_UHMAC_MASK) + +#define S50_ELS_KS9_KS9_UKWK_MASK (0x400000U) +#define S50_ELS_KS9_KS9_UKWK_SHIFT (22U) +#define S50_ELS_KS9_KS9_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKWK_SHIFT)) & S50_ELS_KS9_KS9_UKWK_MASK) + +#define S50_ELS_KS9_KS9_UKUOK_MASK (0x800000U) +#define S50_ELS_KS9_KS9_UKUOK_SHIFT (23U) +#define S50_ELS_KS9_KS9_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKUOK_SHIFT)) & S50_ELS_KS9_KS9_UKUOK_MASK) + +#define S50_ELS_KS9_KS9_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS9_KS9_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS9_KS9_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSPMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSPMS_MASK) + +#define S50_ELS_KS9_KS9_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS9_KS9_UTLSMS_SHIFT (25U) +#define S50_ELS_KS9_KS9_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UTLSMS_SHIFT)) & S50_ELS_KS9_KS9_UTLSMS_MASK) + +#define S50_ELS_KS9_KS9_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS9_KS9_UKGSRC_SHIFT (26U) +#define S50_ELS_KS9_KS9_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UKGSRC_SHIFT)) & S50_ELS_KS9_KS9_UKGSRC_MASK) + +#define S50_ELS_KS9_KS9_UHWO_MASK (0x8000000U) +#define S50_ELS_KS9_KS9_UHWO_SHIFT (27U) +#define S50_ELS_KS9_KS9_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UHWO_SHIFT)) & S50_ELS_KS9_KS9_UHWO_MASK) + +#define S50_ELS_KS9_KS9_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS9_KS9_UWRPOK_SHIFT (28U) +#define S50_ELS_KS9_KS9_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UWRPOK_SHIFT)) & S50_ELS_KS9_KS9_UWRPOK_MASK) + +#define S50_ELS_KS9_KS9_UDUK_MASK (0x20000000U) +#define S50_ELS_KS9_KS9_UDUK_SHIFT (29U) +#define S50_ELS_KS9_KS9_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UDUK_SHIFT)) & S50_ELS_KS9_KS9_UDUK_MASK) + +#define S50_ELS_KS9_KS9_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS9_KS9_UPPROT_SHIFT (30U) +#define S50_ELS_KS9_KS9_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS9_KS9_UPPROT_SHIFT)) & S50_ELS_KS9_KS9_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS10 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS10_KS10_KSIZE_MASK (0x3U) +#define S50_ELS_KS10_KS10_KSIZE_SHIFT (0U) +/*! KS10_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS10_KS10_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KSIZE_SHIFT)) & S50_ELS_KS10_KS10_KSIZE_MASK) + +#define S50_ELS_KS10_KS10_KACT_MASK (0x20U) +#define S50_ELS_KS10_KS10_KACT_SHIFT (5U) +#define S50_ELS_KS10_KS10_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KACT_SHIFT)) & S50_ELS_KS10_KS10_KACT_MASK) + +#define S50_ELS_KS10_KS10_KBASE_MASK (0x40U) +#define S50_ELS_KS10_KS10_KBASE_SHIFT (6U) +#define S50_ELS_KS10_KS10_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_KBASE_SHIFT)) & S50_ELS_KS10_KS10_KBASE_MASK) + +#define S50_ELS_KS10_KS10_FGP_MASK (0x80U) +#define S50_ELS_KS10_KS10_FGP_SHIFT (7U) +#define S50_ELS_KS10_KS10_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FGP_SHIFT)) & S50_ELS_KS10_KS10_FGP_MASK) + +#define S50_ELS_KS10_KS10_FRTN_MASK (0x100U) +#define S50_ELS_KS10_KS10_FRTN_SHIFT (8U) +#define S50_ELS_KS10_KS10_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FRTN_SHIFT)) & S50_ELS_KS10_KS10_FRTN_MASK) + +#define S50_ELS_KS10_KS10_FHWO_MASK (0x200U) +#define S50_ELS_KS10_KS10_FHWO_SHIFT (9U) +#define S50_ELS_KS10_KS10_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_FHWO_SHIFT)) & S50_ELS_KS10_KS10_FHWO_MASK) + +#define S50_ELS_KS10_KS10_UKPUK_MASK (0x800U) +#define S50_ELS_KS10_KS10_UKPUK_SHIFT (11U) +#define S50_ELS_KS10_KS10_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKPUK_SHIFT)) & S50_ELS_KS10_KS10_UKPUK_MASK) + +#define S50_ELS_KS10_KS10_UTECDH_MASK (0x1000U) +#define S50_ELS_KS10_KS10_UTECDH_SHIFT (12U) +#define S50_ELS_KS10_KS10_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTECDH_SHIFT)) & S50_ELS_KS10_KS10_UTECDH_MASK) + +#define S50_ELS_KS10_KS10_UCMAC_MASK (0x2000U) +#define S50_ELS_KS10_KS10_UCMAC_SHIFT (13U) +#define S50_ELS_KS10_KS10_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCMAC_SHIFT)) & S50_ELS_KS10_KS10_UCMAC_MASK) + +#define S50_ELS_KS10_KS10_UKSK_MASK (0x4000U) +#define S50_ELS_KS10_KS10_UKSK_SHIFT (14U) +#define S50_ELS_KS10_KS10_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKSK_SHIFT)) & S50_ELS_KS10_KS10_UKSK_MASK) + +#define S50_ELS_KS10_KS10_URTF_MASK (0x8000U) +#define S50_ELS_KS10_KS10_URTF_SHIFT (15U) +#define S50_ELS_KS10_KS10_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_URTF_SHIFT)) & S50_ELS_KS10_KS10_URTF_MASK) + +#define S50_ELS_KS10_KS10_UCKDF_MASK (0x10000U) +#define S50_ELS_KS10_KS10_UCKDF_SHIFT (16U) +#define S50_ELS_KS10_KS10_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UCKDF_SHIFT)) & S50_ELS_KS10_KS10_UCKDF_MASK) + +#define S50_ELS_KS10_KS10_UHKDF_MASK (0x20000U) +#define S50_ELS_KS10_KS10_UHKDF_SHIFT (17U) +#define S50_ELS_KS10_KS10_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHKDF_SHIFT)) & S50_ELS_KS10_KS10_UHKDF_MASK) + +#define S50_ELS_KS10_KS10_UECSG_MASK (0x40000U) +#define S50_ELS_KS10_KS10_UECSG_SHIFT (18U) +#define S50_ELS_KS10_KS10_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECSG_SHIFT)) & S50_ELS_KS10_KS10_UECSG_MASK) + +#define S50_ELS_KS10_KS10_UECDH_MASK (0x80000U) +#define S50_ELS_KS10_KS10_UECDH_SHIFT (19U) +#define S50_ELS_KS10_KS10_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UECDH_SHIFT)) & S50_ELS_KS10_KS10_UECDH_MASK) + +#define S50_ELS_KS10_KS10_UAES_MASK (0x100000U) +#define S50_ELS_KS10_KS10_UAES_SHIFT (20U) +#define S50_ELS_KS10_KS10_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UAES_SHIFT)) & S50_ELS_KS10_KS10_UAES_MASK) + +#define S50_ELS_KS10_KS10_UHMAC_MASK (0x200000U) +#define S50_ELS_KS10_KS10_UHMAC_SHIFT (21U) +#define S50_ELS_KS10_KS10_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHMAC_SHIFT)) & S50_ELS_KS10_KS10_UHMAC_MASK) + +#define S50_ELS_KS10_KS10_UKWK_MASK (0x400000U) +#define S50_ELS_KS10_KS10_UKWK_SHIFT (22U) +#define S50_ELS_KS10_KS10_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKWK_SHIFT)) & S50_ELS_KS10_KS10_UKWK_MASK) + +#define S50_ELS_KS10_KS10_UKUOK_MASK (0x800000U) +#define S50_ELS_KS10_KS10_UKUOK_SHIFT (23U) +#define S50_ELS_KS10_KS10_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKUOK_SHIFT)) & S50_ELS_KS10_KS10_UKUOK_MASK) + +#define S50_ELS_KS10_KS10_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS10_KS10_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS10_KS10_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSPMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSPMS_MASK) + +#define S50_ELS_KS10_KS10_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS10_KS10_UTLSMS_SHIFT (25U) +#define S50_ELS_KS10_KS10_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UTLSMS_SHIFT)) & S50_ELS_KS10_KS10_UTLSMS_MASK) + +#define S50_ELS_KS10_KS10_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS10_KS10_UKGSRC_SHIFT (26U) +#define S50_ELS_KS10_KS10_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UKGSRC_SHIFT)) & S50_ELS_KS10_KS10_UKGSRC_MASK) + +#define S50_ELS_KS10_KS10_UHWO_MASK (0x8000000U) +#define S50_ELS_KS10_KS10_UHWO_SHIFT (27U) +#define S50_ELS_KS10_KS10_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UHWO_SHIFT)) & S50_ELS_KS10_KS10_UHWO_MASK) + +#define S50_ELS_KS10_KS10_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS10_KS10_UWRPOK_SHIFT (28U) +#define S50_ELS_KS10_KS10_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UWRPOK_SHIFT)) & S50_ELS_KS10_KS10_UWRPOK_MASK) + +#define S50_ELS_KS10_KS10_UDUK_MASK (0x20000000U) +#define S50_ELS_KS10_KS10_UDUK_SHIFT (29U) +#define S50_ELS_KS10_KS10_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UDUK_SHIFT)) & S50_ELS_KS10_KS10_UDUK_MASK) + +#define S50_ELS_KS10_KS10_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS10_KS10_UPPROT_SHIFT (30U) +#define S50_ELS_KS10_KS10_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS10_KS10_UPPROT_SHIFT)) & S50_ELS_KS10_KS10_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS11 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS11_KS11_KSIZE_MASK (0x3U) +#define S50_ELS_KS11_KS11_KSIZE_SHIFT (0U) +/*! KS11_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS11_KS11_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KSIZE_SHIFT)) & S50_ELS_KS11_KS11_KSIZE_MASK) + +#define S50_ELS_KS11_KS11_KACT_MASK (0x20U) +#define S50_ELS_KS11_KS11_KACT_SHIFT (5U) +#define S50_ELS_KS11_KS11_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KACT_SHIFT)) & S50_ELS_KS11_KS11_KACT_MASK) + +#define S50_ELS_KS11_KS11_KBASE_MASK (0x40U) +#define S50_ELS_KS11_KS11_KBASE_SHIFT (6U) +#define S50_ELS_KS11_KS11_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_KBASE_SHIFT)) & S50_ELS_KS11_KS11_KBASE_MASK) + +#define S50_ELS_KS11_KS11_FGP_MASK (0x80U) +#define S50_ELS_KS11_KS11_FGP_SHIFT (7U) +#define S50_ELS_KS11_KS11_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FGP_SHIFT)) & S50_ELS_KS11_KS11_FGP_MASK) + +#define S50_ELS_KS11_KS11_FRTN_MASK (0x100U) +#define S50_ELS_KS11_KS11_FRTN_SHIFT (8U) +#define S50_ELS_KS11_KS11_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FRTN_SHIFT)) & S50_ELS_KS11_KS11_FRTN_MASK) + +#define S50_ELS_KS11_KS11_FHWO_MASK (0x200U) +#define S50_ELS_KS11_KS11_FHWO_SHIFT (9U) +#define S50_ELS_KS11_KS11_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_FHWO_SHIFT)) & S50_ELS_KS11_KS11_FHWO_MASK) + +#define S50_ELS_KS11_KS11_UKPUK_MASK (0x800U) +#define S50_ELS_KS11_KS11_UKPUK_SHIFT (11U) +#define S50_ELS_KS11_KS11_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKPUK_SHIFT)) & S50_ELS_KS11_KS11_UKPUK_MASK) + +#define S50_ELS_KS11_KS11_UTECDH_MASK (0x1000U) +#define S50_ELS_KS11_KS11_UTECDH_SHIFT (12U) +#define S50_ELS_KS11_KS11_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTECDH_SHIFT)) & S50_ELS_KS11_KS11_UTECDH_MASK) + +#define S50_ELS_KS11_KS11_UCMAC_MASK (0x2000U) +#define S50_ELS_KS11_KS11_UCMAC_SHIFT (13U) +#define S50_ELS_KS11_KS11_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCMAC_SHIFT)) & S50_ELS_KS11_KS11_UCMAC_MASK) + +#define S50_ELS_KS11_KS11_UKSK_MASK (0x4000U) +#define S50_ELS_KS11_KS11_UKSK_SHIFT (14U) +#define S50_ELS_KS11_KS11_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKSK_SHIFT)) & S50_ELS_KS11_KS11_UKSK_MASK) + +#define S50_ELS_KS11_KS11_URTF_MASK (0x8000U) +#define S50_ELS_KS11_KS11_URTF_SHIFT (15U) +#define S50_ELS_KS11_KS11_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_URTF_SHIFT)) & S50_ELS_KS11_KS11_URTF_MASK) + +#define S50_ELS_KS11_KS11_UCKDF_MASK (0x10000U) +#define S50_ELS_KS11_KS11_UCKDF_SHIFT (16U) +#define S50_ELS_KS11_KS11_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UCKDF_SHIFT)) & S50_ELS_KS11_KS11_UCKDF_MASK) + +#define S50_ELS_KS11_KS11_UHKDF_MASK (0x20000U) +#define S50_ELS_KS11_KS11_UHKDF_SHIFT (17U) +#define S50_ELS_KS11_KS11_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHKDF_SHIFT)) & S50_ELS_KS11_KS11_UHKDF_MASK) + +#define S50_ELS_KS11_KS11_UECSG_MASK (0x40000U) +#define S50_ELS_KS11_KS11_UECSG_SHIFT (18U) +#define S50_ELS_KS11_KS11_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECSG_SHIFT)) & S50_ELS_KS11_KS11_UECSG_MASK) + +#define S50_ELS_KS11_KS11_UECDH_MASK (0x80000U) +#define S50_ELS_KS11_KS11_UECDH_SHIFT (19U) +#define S50_ELS_KS11_KS11_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UECDH_SHIFT)) & S50_ELS_KS11_KS11_UECDH_MASK) + +#define S50_ELS_KS11_KS11_UAES_MASK (0x100000U) +#define S50_ELS_KS11_KS11_UAES_SHIFT (20U) +#define S50_ELS_KS11_KS11_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UAES_SHIFT)) & S50_ELS_KS11_KS11_UAES_MASK) + +#define S50_ELS_KS11_KS11_UHMAC_MASK (0x200000U) +#define S50_ELS_KS11_KS11_UHMAC_SHIFT (21U) +#define S50_ELS_KS11_KS11_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHMAC_SHIFT)) & S50_ELS_KS11_KS11_UHMAC_MASK) + +#define S50_ELS_KS11_KS11_UKWK_MASK (0x400000U) +#define S50_ELS_KS11_KS11_UKWK_SHIFT (22U) +#define S50_ELS_KS11_KS11_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKWK_SHIFT)) & S50_ELS_KS11_KS11_UKWK_MASK) + +#define S50_ELS_KS11_KS11_UKUOK_MASK (0x800000U) +#define S50_ELS_KS11_KS11_UKUOK_SHIFT (23U) +#define S50_ELS_KS11_KS11_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKUOK_SHIFT)) & S50_ELS_KS11_KS11_UKUOK_MASK) + +#define S50_ELS_KS11_KS11_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS11_KS11_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS11_KS11_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSPMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSPMS_MASK) + +#define S50_ELS_KS11_KS11_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS11_KS11_UTLSMS_SHIFT (25U) +#define S50_ELS_KS11_KS11_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UTLSMS_SHIFT)) & S50_ELS_KS11_KS11_UTLSMS_MASK) + +#define S50_ELS_KS11_KS11_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS11_KS11_UKGSRC_SHIFT (26U) +#define S50_ELS_KS11_KS11_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UKGSRC_SHIFT)) & S50_ELS_KS11_KS11_UKGSRC_MASK) + +#define S50_ELS_KS11_KS11_UHWO_MASK (0x8000000U) +#define S50_ELS_KS11_KS11_UHWO_SHIFT (27U) +#define S50_ELS_KS11_KS11_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UHWO_SHIFT)) & S50_ELS_KS11_KS11_UHWO_MASK) + +#define S50_ELS_KS11_KS11_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS11_KS11_UWRPOK_SHIFT (28U) +#define S50_ELS_KS11_KS11_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UWRPOK_SHIFT)) & S50_ELS_KS11_KS11_UWRPOK_MASK) + +#define S50_ELS_KS11_KS11_UDUK_MASK (0x20000000U) +#define S50_ELS_KS11_KS11_UDUK_SHIFT (29U) +#define S50_ELS_KS11_KS11_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UDUK_SHIFT)) & S50_ELS_KS11_KS11_UDUK_MASK) + +#define S50_ELS_KS11_KS11_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS11_KS11_UPPROT_SHIFT (30U) +#define S50_ELS_KS11_KS11_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS11_KS11_UPPROT_SHIFT)) & S50_ELS_KS11_KS11_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS12 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS12_KS12_KSIZE_MASK (0x3U) +#define S50_ELS_KS12_KS12_KSIZE_SHIFT (0U) +/*! KS12_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS12_KS12_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KSIZE_SHIFT)) & S50_ELS_KS12_KS12_KSIZE_MASK) + +#define S50_ELS_KS12_KS12_KACT_MASK (0x20U) +#define S50_ELS_KS12_KS12_KACT_SHIFT (5U) +#define S50_ELS_KS12_KS12_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KACT_SHIFT)) & S50_ELS_KS12_KS12_KACT_MASK) + +#define S50_ELS_KS12_KS12_KBASE_MASK (0x40U) +#define S50_ELS_KS12_KS12_KBASE_SHIFT (6U) +#define S50_ELS_KS12_KS12_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_KBASE_SHIFT)) & S50_ELS_KS12_KS12_KBASE_MASK) + +#define S50_ELS_KS12_KS12_FGP_MASK (0x80U) +#define S50_ELS_KS12_KS12_FGP_SHIFT (7U) +#define S50_ELS_KS12_KS12_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FGP_SHIFT)) & S50_ELS_KS12_KS12_FGP_MASK) + +#define S50_ELS_KS12_KS12_FRTN_MASK (0x100U) +#define S50_ELS_KS12_KS12_FRTN_SHIFT (8U) +#define S50_ELS_KS12_KS12_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FRTN_SHIFT)) & S50_ELS_KS12_KS12_FRTN_MASK) + +#define S50_ELS_KS12_KS12_FHWO_MASK (0x200U) +#define S50_ELS_KS12_KS12_FHWO_SHIFT (9U) +#define S50_ELS_KS12_KS12_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_FHWO_SHIFT)) & S50_ELS_KS12_KS12_FHWO_MASK) + +#define S50_ELS_KS12_KS12_UKPUK_MASK (0x800U) +#define S50_ELS_KS12_KS12_UKPUK_SHIFT (11U) +#define S50_ELS_KS12_KS12_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKPUK_SHIFT)) & S50_ELS_KS12_KS12_UKPUK_MASK) + +#define S50_ELS_KS12_KS12_UTECDH_MASK (0x1000U) +#define S50_ELS_KS12_KS12_UTECDH_SHIFT (12U) +#define S50_ELS_KS12_KS12_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTECDH_SHIFT)) & S50_ELS_KS12_KS12_UTECDH_MASK) + +#define S50_ELS_KS12_KS12_UCMAC_MASK (0x2000U) +#define S50_ELS_KS12_KS12_UCMAC_SHIFT (13U) +#define S50_ELS_KS12_KS12_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCMAC_SHIFT)) & S50_ELS_KS12_KS12_UCMAC_MASK) + +#define S50_ELS_KS12_KS12_UKSK_MASK (0x4000U) +#define S50_ELS_KS12_KS12_UKSK_SHIFT (14U) +#define S50_ELS_KS12_KS12_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKSK_SHIFT)) & S50_ELS_KS12_KS12_UKSK_MASK) + +#define S50_ELS_KS12_KS12_URTF_MASK (0x8000U) +#define S50_ELS_KS12_KS12_URTF_SHIFT (15U) +#define S50_ELS_KS12_KS12_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_URTF_SHIFT)) & S50_ELS_KS12_KS12_URTF_MASK) + +#define S50_ELS_KS12_KS12_UCKDF_MASK (0x10000U) +#define S50_ELS_KS12_KS12_UCKDF_SHIFT (16U) +#define S50_ELS_KS12_KS12_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UCKDF_SHIFT)) & S50_ELS_KS12_KS12_UCKDF_MASK) + +#define S50_ELS_KS12_KS12_UHKDF_MASK (0x20000U) +#define S50_ELS_KS12_KS12_UHKDF_SHIFT (17U) +#define S50_ELS_KS12_KS12_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHKDF_SHIFT)) & S50_ELS_KS12_KS12_UHKDF_MASK) + +#define S50_ELS_KS12_KS12_UECSG_MASK (0x40000U) +#define S50_ELS_KS12_KS12_UECSG_SHIFT (18U) +#define S50_ELS_KS12_KS12_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECSG_SHIFT)) & S50_ELS_KS12_KS12_UECSG_MASK) + +#define S50_ELS_KS12_KS12_UECDH_MASK (0x80000U) +#define S50_ELS_KS12_KS12_UECDH_SHIFT (19U) +#define S50_ELS_KS12_KS12_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UECDH_SHIFT)) & S50_ELS_KS12_KS12_UECDH_MASK) + +#define S50_ELS_KS12_KS12_UAES_MASK (0x100000U) +#define S50_ELS_KS12_KS12_UAES_SHIFT (20U) +#define S50_ELS_KS12_KS12_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UAES_SHIFT)) & S50_ELS_KS12_KS12_UAES_MASK) + +#define S50_ELS_KS12_KS12_UHMAC_MASK (0x200000U) +#define S50_ELS_KS12_KS12_UHMAC_SHIFT (21U) +#define S50_ELS_KS12_KS12_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHMAC_SHIFT)) & S50_ELS_KS12_KS12_UHMAC_MASK) + +#define S50_ELS_KS12_KS12_UKWK_MASK (0x400000U) +#define S50_ELS_KS12_KS12_UKWK_SHIFT (22U) +#define S50_ELS_KS12_KS12_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKWK_SHIFT)) & S50_ELS_KS12_KS12_UKWK_MASK) + +#define S50_ELS_KS12_KS12_UKUOK_MASK (0x800000U) +#define S50_ELS_KS12_KS12_UKUOK_SHIFT (23U) +#define S50_ELS_KS12_KS12_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKUOK_SHIFT)) & S50_ELS_KS12_KS12_UKUOK_MASK) + +#define S50_ELS_KS12_KS12_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS12_KS12_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS12_KS12_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSPMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSPMS_MASK) + +#define S50_ELS_KS12_KS12_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS12_KS12_UTLSMS_SHIFT (25U) +#define S50_ELS_KS12_KS12_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UTLSMS_SHIFT)) & S50_ELS_KS12_KS12_UTLSMS_MASK) + +#define S50_ELS_KS12_KS12_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS12_KS12_UKGSRC_SHIFT (26U) +#define S50_ELS_KS12_KS12_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UKGSRC_SHIFT)) & S50_ELS_KS12_KS12_UKGSRC_MASK) + +#define S50_ELS_KS12_KS12_UHWO_MASK (0x8000000U) +#define S50_ELS_KS12_KS12_UHWO_SHIFT (27U) +#define S50_ELS_KS12_KS12_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UHWO_SHIFT)) & S50_ELS_KS12_KS12_UHWO_MASK) + +#define S50_ELS_KS12_KS12_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS12_KS12_UWRPOK_SHIFT (28U) +#define S50_ELS_KS12_KS12_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UWRPOK_SHIFT)) & S50_ELS_KS12_KS12_UWRPOK_MASK) + +#define S50_ELS_KS12_KS12_UDUK_MASK (0x20000000U) +#define S50_ELS_KS12_KS12_UDUK_SHIFT (29U) +#define S50_ELS_KS12_KS12_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UDUK_SHIFT)) & S50_ELS_KS12_KS12_UDUK_MASK) + +#define S50_ELS_KS12_KS12_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS12_KS12_UPPROT_SHIFT (30U) +#define S50_ELS_KS12_KS12_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS12_KS12_UPPROT_SHIFT)) & S50_ELS_KS12_KS12_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS13 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS13_KS13_KSIZE_MASK (0x3U) +#define S50_ELS_KS13_KS13_KSIZE_SHIFT (0U) +/*! KS13_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS13_KS13_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KSIZE_SHIFT)) & S50_ELS_KS13_KS13_KSIZE_MASK) + +#define S50_ELS_KS13_KS13_KACT_MASK (0x20U) +#define S50_ELS_KS13_KS13_KACT_SHIFT (5U) +#define S50_ELS_KS13_KS13_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KACT_SHIFT)) & S50_ELS_KS13_KS13_KACT_MASK) + +#define S50_ELS_KS13_KS13_KBASE_MASK (0x40U) +#define S50_ELS_KS13_KS13_KBASE_SHIFT (6U) +#define S50_ELS_KS13_KS13_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_KBASE_SHIFT)) & S50_ELS_KS13_KS13_KBASE_MASK) + +#define S50_ELS_KS13_KS13_FGP_MASK (0x80U) +#define S50_ELS_KS13_KS13_FGP_SHIFT (7U) +#define S50_ELS_KS13_KS13_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FGP_SHIFT)) & S50_ELS_KS13_KS13_FGP_MASK) + +#define S50_ELS_KS13_KS13_FRTN_MASK (0x100U) +#define S50_ELS_KS13_KS13_FRTN_SHIFT (8U) +#define S50_ELS_KS13_KS13_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FRTN_SHIFT)) & S50_ELS_KS13_KS13_FRTN_MASK) + +#define S50_ELS_KS13_KS13_FHWO_MASK (0x200U) +#define S50_ELS_KS13_KS13_FHWO_SHIFT (9U) +#define S50_ELS_KS13_KS13_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_FHWO_SHIFT)) & S50_ELS_KS13_KS13_FHWO_MASK) + +#define S50_ELS_KS13_KS13_UKPUK_MASK (0x800U) +#define S50_ELS_KS13_KS13_UKPUK_SHIFT (11U) +#define S50_ELS_KS13_KS13_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKPUK_SHIFT)) & S50_ELS_KS13_KS13_UKPUK_MASK) + +#define S50_ELS_KS13_KS13_UTECDH_MASK (0x1000U) +#define S50_ELS_KS13_KS13_UTECDH_SHIFT (12U) +#define S50_ELS_KS13_KS13_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTECDH_SHIFT)) & S50_ELS_KS13_KS13_UTECDH_MASK) + +#define S50_ELS_KS13_KS13_UCMAC_MASK (0x2000U) +#define S50_ELS_KS13_KS13_UCMAC_SHIFT (13U) +#define S50_ELS_KS13_KS13_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCMAC_SHIFT)) & S50_ELS_KS13_KS13_UCMAC_MASK) + +#define S50_ELS_KS13_KS13_UKSK_MASK (0x4000U) +#define S50_ELS_KS13_KS13_UKSK_SHIFT (14U) +#define S50_ELS_KS13_KS13_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKSK_SHIFT)) & S50_ELS_KS13_KS13_UKSK_MASK) + +#define S50_ELS_KS13_KS13_URTF_MASK (0x8000U) +#define S50_ELS_KS13_KS13_URTF_SHIFT (15U) +#define S50_ELS_KS13_KS13_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_URTF_SHIFT)) & S50_ELS_KS13_KS13_URTF_MASK) + +#define S50_ELS_KS13_KS13_UCKDF_MASK (0x10000U) +#define S50_ELS_KS13_KS13_UCKDF_SHIFT (16U) +#define S50_ELS_KS13_KS13_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UCKDF_SHIFT)) & S50_ELS_KS13_KS13_UCKDF_MASK) + +#define S50_ELS_KS13_KS13_UHKDF_MASK (0x20000U) +#define S50_ELS_KS13_KS13_UHKDF_SHIFT (17U) +#define S50_ELS_KS13_KS13_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHKDF_SHIFT)) & S50_ELS_KS13_KS13_UHKDF_MASK) + +#define S50_ELS_KS13_KS13_UECSG_MASK (0x40000U) +#define S50_ELS_KS13_KS13_UECSG_SHIFT (18U) +#define S50_ELS_KS13_KS13_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECSG_SHIFT)) & S50_ELS_KS13_KS13_UECSG_MASK) + +#define S50_ELS_KS13_KS13_UECDH_MASK (0x80000U) +#define S50_ELS_KS13_KS13_UECDH_SHIFT (19U) +#define S50_ELS_KS13_KS13_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UECDH_SHIFT)) & S50_ELS_KS13_KS13_UECDH_MASK) + +#define S50_ELS_KS13_KS13_UAES_MASK (0x100000U) +#define S50_ELS_KS13_KS13_UAES_SHIFT (20U) +#define S50_ELS_KS13_KS13_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UAES_SHIFT)) & S50_ELS_KS13_KS13_UAES_MASK) + +#define S50_ELS_KS13_KS13_UHMAC_MASK (0x200000U) +#define S50_ELS_KS13_KS13_UHMAC_SHIFT (21U) +#define S50_ELS_KS13_KS13_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHMAC_SHIFT)) & S50_ELS_KS13_KS13_UHMAC_MASK) + +#define S50_ELS_KS13_KS13_UKWK_MASK (0x400000U) +#define S50_ELS_KS13_KS13_UKWK_SHIFT (22U) +#define S50_ELS_KS13_KS13_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKWK_SHIFT)) & S50_ELS_KS13_KS13_UKWK_MASK) + +#define S50_ELS_KS13_KS13_UKUOK_MASK (0x800000U) +#define S50_ELS_KS13_KS13_UKUOK_SHIFT (23U) +#define S50_ELS_KS13_KS13_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKUOK_SHIFT)) & S50_ELS_KS13_KS13_UKUOK_MASK) + +#define S50_ELS_KS13_KS13_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS13_KS13_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS13_KS13_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSPMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSPMS_MASK) + +#define S50_ELS_KS13_KS13_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS13_KS13_UTLSMS_SHIFT (25U) +#define S50_ELS_KS13_KS13_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UTLSMS_SHIFT)) & S50_ELS_KS13_KS13_UTLSMS_MASK) + +#define S50_ELS_KS13_KS13_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS13_KS13_UKGSRC_SHIFT (26U) +#define S50_ELS_KS13_KS13_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UKGSRC_SHIFT)) & S50_ELS_KS13_KS13_UKGSRC_MASK) + +#define S50_ELS_KS13_KS13_UHWO_MASK (0x8000000U) +#define S50_ELS_KS13_KS13_UHWO_SHIFT (27U) +#define S50_ELS_KS13_KS13_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UHWO_SHIFT)) & S50_ELS_KS13_KS13_UHWO_MASK) + +#define S50_ELS_KS13_KS13_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS13_KS13_UWRPOK_SHIFT (28U) +#define S50_ELS_KS13_KS13_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UWRPOK_SHIFT)) & S50_ELS_KS13_KS13_UWRPOK_MASK) + +#define S50_ELS_KS13_KS13_UDUK_MASK (0x20000000U) +#define S50_ELS_KS13_KS13_UDUK_SHIFT (29U) +#define S50_ELS_KS13_KS13_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UDUK_SHIFT)) & S50_ELS_KS13_KS13_UDUK_MASK) + +#define S50_ELS_KS13_KS13_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS13_KS13_UPPROT_SHIFT (30U) +#define S50_ELS_KS13_KS13_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS13_KS13_UPPROT_SHIFT)) & S50_ELS_KS13_KS13_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS14 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS14_KS14_KSIZE_MASK (0x3U) +#define S50_ELS_KS14_KS14_KSIZE_SHIFT (0U) +/*! KS14_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS14_KS14_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KSIZE_SHIFT)) & S50_ELS_KS14_KS14_KSIZE_MASK) + +#define S50_ELS_KS14_KS14_KACT_MASK (0x20U) +#define S50_ELS_KS14_KS14_KACT_SHIFT (5U) +#define S50_ELS_KS14_KS14_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KACT_SHIFT)) & S50_ELS_KS14_KS14_KACT_MASK) + +#define S50_ELS_KS14_KS14_KBASE_MASK (0x40U) +#define S50_ELS_KS14_KS14_KBASE_SHIFT (6U) +#define S50_ELS_KS14_KS14_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_KBASE_SHIFT)) & S50_ELS_KS14_KS14_KBASE_MASK) + +#define S50_ELS_KS14_KS14_FGP_MASK (0x80U) +#define S50_ELS_KS14_KS14_FGP_SHIFT (7U) +#define S50_ELS_KS14_KS14_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FGP_SHIFT)) & S50_ELS_KS14_KS14_FGP_MASK) + +#define S50_ELS_KS14_KS14_FRTN_MASK (0x100U) +#define S50_ELS_KS14_KS14_FRTN_SHIFT (8U) +#define S50_ELS_KS14_KS14_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FRTN_SHIFT)) & S50_ELS_KS14_KS14_FRTN_MASK) + +#define S50_ELS_KS14_KS14_FHWO_MASK (0x200U) +#define S50_ELS_KS14_KS14_FHWO_SHIFT (9U) +#define S50_ELS_KS14_KS14_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_FHWO_SHIFT)) & S50_ELS_KS14_KS14_FHWO_MASK) + +#define S50_ELS_KS14_KS14_UKPUK_MASK (0x800U) +#define S50_ELS_KS14_KS14_UKPUK_SHIFT (11U) +#define S50_ELS_KS14_KS14_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKPUK_SHIFT)) & S50_ELS_KS14_KS14_UKPUK_MASK) + +#define S50_ELS_KS14_KS14_UTECDH_MASK (0x1000U) +#define S50_ELS_KS14_KS14_UTECDH_SHIFT (12U) +#define S50_ELS_KS14_KS14_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTECDH_SHIFT)) & S50_ELS_KS14_KS14_UTECDH_MASK) + +#define S50_ELS_KS14_KS14_UCMAC_MASK (0x2000U) +#define S50_ELS_KS14_KS14_UCMAC_SHIFT (13U) +#define S50_ELS_KS14_KS14_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCMAC_SHIFT)) & S50_ELS_KS14_KS14_UCMAC_MASK) + +#define S50_ELS_KS14_KS14_UKSK_MASK (0x4000U) +#define S50_ELS_KS14_KS14_UKSK_SHIFT (14U) +#define S50_ELS_KS14_KS14_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKSK_SHIFT)) & S50_ELS_KS14_KS14_UKSK_MASK) + +#define S50_ELS_KS14_KS14_URTF_MASK (0x8000U) +#define S50_ELS_KS14_KS14_URTF_SHIFT (15U) +#define S50_ELS_KS14_KS14_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_URTF_SHIFT)) & S50_ELS_KS14_KS14_URTF_MASK) + +#define S50_ELS_KS14_KS14_UCKDF_MASK (0x10000U) +#define S50_ELS_KS14_KS14_UCKDF_SHIFT (16U) +#define S50_ELS_KS14_KS14_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UCKDF_SHIFT)) & S50_ELS_KS14_KS14_UCKDF_MASK) + +#define S50_ELS_KS14_KS14_UHKDF_MASK (0x20000U) +#define S50_ELS_KS14_KS14_UHKDF_SHIFT (17U) +#define S50_ELS_KS14_KS14_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHKDF_SHIFT)) & S50_ELS_KS14_KS14_UHKDF_MASK) + +#define S50_ELS_KS14_KS14_UECSG_MASK (0x40000U) +#define S50_ELS_KS14_KS14_UECSG_SHIFT (18U) +#define S50_ELS_KS14_KS14_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECSG_SHIFT)) & S50_ELS_KS14_KS14_UECSG_MASK) + +#define S50_ELS_KS14_KS14_UECDH_MASK (0x80000U) +#define S50_ELS_KS14_KS14_UECDH_SHIFT (19U) +#define S50_ELS_KS14_KS14_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UECDH_SHIFT)) & S50_ELS_KS14_KS14_UECDH_MASK) + +#define S50_ELS_KS14_KS14_UAES_MASK (0x100000U) +#define S50_ELS_KS14_KS14_UAES_SHIFT (20U) +#define S50_ELS_KS14_KS14_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UAES_SHIFT)) & S50_ELS_KS14_KS14_UAES_MASK) + +#define S50_ELS_KS14_KS14_UHMAC_MASK (0x200000U) +#define S50_ELS_KS14_KS14_UHMAC_SHIFT (21U) +#define S50_ELS_KS14_KS14_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHMAC_SHIFT)) & S50_ELS_KS14_KS14_UHMAC_MASK) + +#define S50_ELS_KS14_KS14_UKWK_MASK (0x400000U) +#define S50_ELS_KS14_KS14_UKWK_SHIFT (22U) +#define S50_ELS_KS14_KS14_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKWK_SHIFT)) & S50_ELS_KS14_KS14_UKWK_MASK) + +#define S50_ELS_KS14_KS14_UKUOK_MASK (0x800000U) +#define S50_ELS_KS14_KS14_UKUOK_SHIFT (23U) +#define S50_ELS_KS14_KS14_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKUOK_SHIFT)) & S50_ELS_KS14_KS14_UKUOK_MASK) + +#define S50_ELS_KS14_KS14_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS14_KS14_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS14_KS14_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSPMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSPMS_MASK) + +#define S50_ELS_KS14_KS14_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS14_KS14_UTLSMS_SHIFT (25U) +#define S50_ELS_KS14_KS14_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UTLSMS_SHIFT)) & S50_ELS_KS14_KS14_UTLSMS_MASK) + +#define S50_ELS_KS14_KS14_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS14_KS14_UKGSRC_SHIFT (26U) +#define S50_ELS_KS14_KS14_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UKGSRC_SHIFT)) & S50_ELS_KS14_KS14_UKGSRC_MASK) + +#define S50_ELS_KS14_KS14_UHWO_MASK (0x8000000U) +#define S50_ELS_KS14_KS14_UHWO_SHIFT (27U) +#define S50_ELS_KS14_KS14_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UHWO_SHIFT)) & S50_ELS_KS14_KS14_UHWO_MASK) + +#define S50_ELS_KS14_KS14_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS14_KS14_UWRPOK_SHIFT (28U) +#define S50_ELS_KS14_KS14_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UWRPOK_SHIFT)) & S50_ELS_KS14_KS14_UWRPOK_MASK) + +#define S50_ELS_KS14_KS14_UDUK_MASK (0x20000000U) +#define S50_ELS_KS14_KS14_UDUK_SHIFT (29U) +#define S50_ELS_KS14_KS14_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UDUK_SHIFT)) & S50_ELS_KS14_KS14_UDUK_MASK) + +#define S50_ELS_KS14_KS14_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS14_KS14_UPPROT_SHIFT (30U) +#define S50_ELS_KS14_KS14_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS14_KS14_UPPROT_SHIFT)) & S50_ELS_KS14_KS14_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS15 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS15_KS15_KSIZE_MASK (0x3U) +#define S50_ELS_KS15_KS15_KSIZE_SHIFT (0U) +/*! KS15_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS15_KS15_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KSIZE_SHIFT)) & S50_ELS_KS15_KS15_KSIZE_MASK) + +#define S50_ELS_KS15_KS15_KACT_MASK (0x20U) +#define S50_ELS_KS15_KS15_KACT_SHIFT (5U) +#define S50_ELS_KS15_KS15_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KACT_SHIFT)) & S50_ELS_KS15_KS15_KACT_MASK) + +#define S50_ELS_KS15_KS15_KBASE_MASK (0x40U) +#define S50_ELS_KS15_KS15_KBASE_SHIFT (6U) +#define S50_ELS_KS15_KS15_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_KBASE_SHIFT)) & S50_ELS_KS15_KS15_KBASE_MASK) + +#define S50_ELS_KS15_KS15_FGP_MASK (0x80U) +#define S50_ELS_KS15_KS15_FGP_SHIFT (7U) +#define S50_ELS_KS15_KS15_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FGP_SHIFT)) & S50_ELS_KS15_KS15_FGP_MASK) + +#define S50_ELS_KS15_KS15_FRTN_MASK (0x100U) +#define S50_ELS_KS15_KS15_FRTN_SHIFT (8U) +#define S50_ELS_KS15_KS15_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FRTN_SHIFT)) & S50_ELS_KS15_KS15_FRTN_MASK) + +#define S50_ELS_KS15_KS15_FHWO_MASK (0x200U) +#define S50_ELS_KS15_KS15_FHWO_SHIFT (9U) +#define S50_ELS_KS15_KS15_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_FHWO_SHIFT)) & S50_ELS_KS15_KS15_FHWO_MASK) + +#define S50_ELS_KS15_KS15_UKPUK_MASK (0x800U) +#define S50_ELS_KS15_KS15_UKPUK_SHIFT (11U) +#define S50_ELS_KS15_KS15_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKPUK_SHIFT)) & S50_ELS_KS15_KS15_UKPUK_MASK) + +#define S50_ELS_KS15_KS15_UTECDH_MASK (0x1000U) +#define S50_ELS_KS15_KS15_UTECDH_SHIFT (12U) +#define S50_ELS_KS15_KS15_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTECDH_SHIFT)) & S50_ELS_KS15_KS15_UTECDH_MASK) + +#define S50_ELS_KS15_KS15_UCMAC_MASK (0x2000U) +#define S50_ELS_KS15_KS15_UCMAC_SHIFT (13U) +#define S50_ELS_KS15_KS15_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCMAC_SHIFT)) & S50_ELS_KS15_KS15_UCMAC_MASK) + +#define S50_ELS_KS15_KS15_UKSK_MASK (0x4000U) +#define S50_ELS_KS15_KS15_UKSK_SHIFT (14U) +#define S50_ELS_KS15_KS15_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKSK_SHIFT)) & S50_ELS_KS15_KS15_UKSK_MASK) + +#define S50_ELS_KS15_KS15_URTF_MASK (0x8000U) +#define S50_ELS_KS15_KS15_URTF_SHIFT (15U) +#define S50_ELS_KS15_KS15_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_URTF_SHIFT)) & S50_ELS_KS15_KS15_URTF_MASK) + +#define S50_ELS_KS15_KS15_UCKDF_MASK (0x10000U) +#define S50_ELS_KS15_KS15_UCKDF_SHIFT (16U) +#define S50_ELS_KS15_KS15_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UCKDF_SHIFT)) & S50_ELS_KS15_KS15_UCKDF_MASK) + +#define S50_ELS_KS15_KS15_UHKDF_MASK (0x20000U) +#define S50_ELS_KS15_KS15_UHKDF_SHIFT (17U) +#define S50_ELS_KS15_KS15_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHKDF_SHIFT)) & S50_ELS_KS15_KS15_UHKDF_MASK) + +#define S50_ELS_KS15_KS15_UECSG_MASK (0x40000U) +#define S50_ELS_KS15_KS15_UECSG_SHIFT (18U) +#define S50_ELS_KS15_KS15_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECSG_SHIFT)) & S50_ELS_KS15_KS15_UECSG_MASK) + +#define S50_ELS_KS15_KS15_UECDH_MASK (0x80000U) +#define S50_ELS_KS15_KS15_UECDH_SHIFT (19U) +#define S50_ELS_KS15_KS15_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UECDH_SHIFT)) & S50_ELS_KS15_KS15_UECDH_MASK) + +#define S50_ELS_KS15_KS15_UAES_MASK (0x100000U) +#define S50_ELS_KS15_KS15_UAES_SHIFT (20U) +#define S50_ELS_KS15_KS15_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UAES_SHIFT)) & S50_ELS_KS15_KS15_UAES_MASK) + +#define S50_ELS_KS15_KS15_UHMAC_MASK (0x200000U) +#define S50_ELS_KS15_KS15_UHMAC_SHIFT (21U) +#define S50_ELS_KS15_KS15_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHMAC_SHIFT)) & S50_ELS_KS15_KS15_UHMAC_MASK) + +#define S50_ELS_KS15_KS15_UKWK_MASK (0x400000U) +#define S50_ELS_KS15_KS15_UKWK_SHIFT (22U) +#define S50_ELS_KS15_KS15_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKWK_SHIFT)) & S50_ELS_KS15_KS15_UKWK_MASK) + +#define S50_ELS_KS15_KS15_UKUOK_MASK (0x800000U) +#define S50_ELS_KS15_KS15_UKUOK_SHIFT (23U) +#define S50_ELS_KS15_KS15_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKUOK_SHIFT)) & S50_ELS_KS15_KS15_UKUOK_MASK) + +#define S50_ELS_KS15_KS15_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS15_KS15_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS15_KS15_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSPMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSPMS_MASK) + +#define S50_ELS_KS15_KS15_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS15_KS15_UTLSMS_SHIFT (25U) +#define S50_ELS_KS15_KS15_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UTLSMS_SHIFT)) & S50_ELS_KS15_KS15_UTLSMS_MASK) + +#define S50_ELS_KS15_KS15_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS15_KS15_UKGSRC_SHIFT (26U) +#define S50_ELS_KS15_KS15_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UKGSRC_SHIFT)) & S50_ELS_KS15_KS15_UKGSRC_MASK) + +#define S50_ELS_KS15_KS15_UHWO_MASK (0x8000000U) +#define S50_ELS_KS15_KS15_UHWO_SHIFT (27U) +#define S50_ELS_KS15_KS15_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UHWO_SHIFT)) & S50_ELS_KS15_KS15_UHWO_MASK) + +#define S50_ELS_KS15_KS15_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS15_KS15_UWRPOK_SHIFT (28U) +#define S50_ELS_KS15_KS15_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UWRPOK_SHIFT)) & S50_ELS_KS15_KS15_UWRPOK_MASK) + +#define S50_ELS_KS15_KS15_UDUK_MASK (0x20000000U) +#define S50_ELS_KS15_KS15_UDUK_SHIFT (29U) +#define S50_ELS_KS15_KS15_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UDUK_SHIFT)) & S50_ELS_KS15_KS15_UDUK_MASK) + +#define S50_ELS_KS15_KS15_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS15_KS15_UPPROT_SHIFT (30U) +#define S50_ELS_KS15_KS15_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS15_KS15_UPPROT_SHIFT)) & S50_ELS_KS15_KS15_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS16 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS16_KS16_KSIZE_MASK (0x3U) +#define S50_ELS_KS16_KS16_KSIZE_SHIFT (0U) +/*! KS16_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS16_KS16_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KSIZE_SHIFT)) & S50_ELS_KS16_KS16_KSIZE_MASK) + +#define S50_ELS_KS16_KS16_KACT_MASK (0x20U) +#define S50_ELS_KS16_KS16_KACT_SHIFT (5U) +#define S50_ELS_KS16_KS16_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KACT_SHIFT)) & S50_ELS_KS16_KS16_KACT_MASK) + +#define S50_ELS_KS16_KS16_KBASE_MASK (0x40U) +#define S50_ELS_KS16_KS16_KBASE_SHIFT (6U) +#define S50_ELS_KS16_KS16_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_KBASE_SHIFT)) & S50_ELS_KS16_KS16_KBASE_MASK) + +#define S50_ELS_KS16_KS16_FGP_MASK (0x80U) +#define S50_ELS_KS16_KS16_FGP_SHIFT (7U) +#define S50_ELS_KS16_KS16_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FGP_SHIFT)) & S50_ELS_KS16_KS16_FGP_MASK) + +#define S50_ELS_KS16_KS16_FRTN_MASK (0x100U) +#define S50_ELS_KS16_KS16_FRTN_SHIFT (8U) +#define S50_ELS_KS16_KS16_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FRTN_SHIFT)) & S50_ELS_KS16_KS16_FRTN_MASK) + +#define S50_ELS_KS16_KS16_FHWO_MASK (0x200U) +#define S50_ELS_KS16_KS16_FHWO_SHIFT (9U) +#define S50_ELS_KS16_KS16_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_FHWO_SHIFT)) & S50_ELS_KS16_KS16_FHWO_MASK) + +#define S50_ELS_KS16_KS16_UKPUK_MASK (0x800U) +#define S50_ELS_KS16_KS16_UKPUK_SHIFT (11U) +#define S50_ELS_KS16_KS16_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKPUK_SHIFT)) & S50_ELS_KS16_KS16_UKPUK_MASK) + +#define S50_ELS_KS16_KS16_UTECDH_MASK (0x1000U) +#define S50_ELS_KS16_KS16_UTECDH_SHIFT (12U) +#define S50_ELS_KS16_KS16_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTECDH_SHIFT)) & S50_ELS_KS16_KS16_UTECDH_MASK) + +#define S50_ELS_KS16_KS16_UCMAC_MASK (0x2000U) +#define S50_ELS_KS16_KS16_UCMAC_SHIFT (13U) +#define S50_ELS_KS16_KS16_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCMAC_SHIFT)) & S50_ELS_KS16_KS16_UCMAC_MASK) + +#define S50_ELS_KS16_KS16_UKSK_MASK (0x4000U) +#define S50_ELS_KS16_KS16_UKSK_SHIFT (14U) +#define S50_ELS_KS16_KS16_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKSK_SHIFT)) & S50_ELS_KS16_KS16_UKSK_MASK) + +#define S50_ELS_KS16_KS16_URTF_MASK (0x8000U) +#define S50_ELS_KS16_KS16_URTF_SHIFT (15U) +#define S50_ELS_KS16_KS16_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_URTF_SHIFT)) & S50_ELS_KS16_KS16_URTF_MASK) + +#define S50_ELS_KS16_KS16_UCKDF_MASK (0x10000U) +#define S50_ELS_KS16_KS16_UCKDF_SHIFT (16U) +#define S50_ELS_KS16_KS16_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UCKDF_SHIFT)) & S50_ELS_KS16_KS16_UCKDF_MASK) + +#define S50_ELS_KS16_KS16_UHKDF_MASK (0x20000U) +#define S50_ELS_KS16_KS16_UHKDF_SHIFT (17U) +#define S50_ELS_KS16_KS16_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHKDF_SHIFT)) & S50_ELS_KS16_KS16_UHKDF_MASK) + +#define S50_ELS_KS16_KS16_UECSG_MASK (0x40000U) +#define S50_ELS_KS16_KS16_UECSG_SHIFT (18U) +#define S50_ELS_KS16_KS16_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECSG_SHIFT)) & S50_ELS_KS16_KS16_UECSG_MASK) + +#define S50_ELS_KS16_KS16_UECDH_MASK (0x80000U) +#define S50_ELS_KS16_KS16_UECDH_SHIFT (19U) +#define S50_ELS_KS16_KS16_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UECDH_SHIFT)) & S50_ELS_KS16_KS16_UECDH_MASK) + +#define S50_ELS_KS16_KS16_UAES_MASK (0x100000U) +#define S50_ELS_KS16_KS16_UAES_SHIFT (20U) +#define S50_ELS_KS16_KS16_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UAES_SHIFT)) & S50_ELS_KS16_KS16_UAES_MASK) + +#define S50_ELS_KS16_KS16_UHMAC_MASK (0x200000U) +#define S50_ELS_KS16_KS16_UHMAC_SHIFT (21U) +#define S50_ELS_KS16_KS16_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHMAC_SHIFT)) & S50_ELS_KS16_KS16_UHMAC_MASK) + +#define S50_ELS_KS16_KS16_UKWK_MASK (0x400000U) +#define S50_ELS_KS16_KS16_UKWK_SHIFT (22U) +#define S50_ELS_KS16_KS16_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKWK_SHIFT)) & S50_ELS_KS16_KS16_UKWK_MASK) + +#define S50_ELS_KS16_KS16_UKUOK_MASK (0x800000U) +#define S50_ELS_KS16_KS16_UKUOK_SHIFT (23U) +#define S50_ELS_KS16_KS16_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKUOK_SHIFT)) & S50_ELS_KS16_KS16_UKUOK_MASK) + +#define S50_ELS_KS16_KS16_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS16_KS16_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS16_KS16_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSPMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSPMS_MASK) + +#define S50_ELS_KS16_KS16_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS16_KS16_UTLSMS_SHIFT (25U) +#define S50_ELS_KS16_KS16_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UTLSMS_SHIFT)) & S50_ELS_KS16_KS16_UTLSMS_MASK) + +#define S50_ELS_KS16_KS16_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS16_KS16_UKGSRC_SHIFT (26U) +#define S50_ELS_KS16_KS16_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UKGSRC_SHIFT)) & S50_ELS_KS16_KS16_UKGSRC_MASK) + +#define S50_ELS_KS16_KS16_UHWO_MASK (0x8000000U) +#define S50_ELS_KS16_KS16_UHWO_SHIFT (27U) +#define S50_ELS_KS16_KS16_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UHWO_SHIFT)) & S50_ELS_KS16_KS16_UHWO_MASK) + +#define S50_ELS_KS16_KS16_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS16_KS16_UWRPOK_SHIFT (28U) +#define S50_ELS_KS16_KS16_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UWRPOK_SHIFT)) & S50_ELS_KS16_KS16_UWRPOK_MASK) + +#define S50_ELS_KS16_KS16_UDUK_MASK (0x20000000U) +#define S50_ELS_KS16_KS16_UDUK_SHIFT (29U) +#define S50_ELS_KS16_KS16_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UDUK_SHIFT)) & S50_ELS_KS16_KS16_UDUK_MASK) + +#define S50_ELS_KS16_KS16_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS16_KS16_UPPROT_SHIFT (30U) +#define S50_ELS_KS16_KS16_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS16_KS16_UPPROT_SHIFT)) & S50_ELS_KS16_KS16_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS17 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS17_KS17_KSIZE_MASK (0x3U) +#define S50_ELS_KS17_KS17_KSIZE_SHIFT (0U) +/*! KS17_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS17_KS17_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KSIZE_SHIFT)) & S50_ELS_KS17_KS17_KSIZE_MASK) + +#define S50_ELS_KS17_KS17_KACT_MASK (0x20U) +#define S50_ELS_KS17_KS17_KACT_SHIFT (5U) +#define S50_ELS_KS17_KS17_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KACT_SHIFT)) & S50_ELS_KS17_KS17_KACT_MASK) + +#define S50_ELS_KS17_KS17_KBASE_MASK (0x40U) +#define S50_ELS_KS17_KS17_KBASE_SHIFT (6U) +#define S50_ELS_KS17_KS17_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_KBASE_SHIFT)) & S50_ELS_KS17_KS17_KBASE_MASK) + +#define S50_ELS_KS17_KS17_FGP_MASK (0x80U) +#define S50_ELS_KS17_KS17_FGP_SHIFT (7U) +#define S50_ELS_KS17_KS17_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FGP_SHIFT)) & S50_ELS_KS17_KS17_FGP_MASK) + +#define S50_ELS_KS17_KS17_FRTN_MASK (0x100U) +#define S50_ELS_KS17_KS17_FRTN_SHIFT (8U) +#define S50_ELS_KS17_KS17_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FRTN_SHIFT)) & S50_ELS_KS17_KS17_FRTN_MASK) + +#define S50_ELS_KS17_KS17_FHWO_MASK (0x200U) +#define S50_ELS_KS17_KS17_FHWO_SHIFT (9U) +#define S50_ELS_KS17_KS17_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_FHWO_SHIFT)) & S50_ELS_KS17_KS17_FHWO_MASK) + +#define S50_ELS_KS17_KS17_UKPUK_MASK (0x800U) +#define S50_ELS_KS17_KS17_UKPUK_SHIFT (11U) +#define S50_ELS_KS17_KS17_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKPUK_SHIFT)) & S50_ELS_KS17_KS17_UKPUK_MASK) + +#define S50_ELS_KS17_KS17_UTECDH_MASK (0x1000U) +#define S50_ELS_KS17_KS17_UTECDH_SHIFT (12U) +#define S50_ELS_KS17_KS17_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTECDH_SHIFT)) & S50_ELS_KS17_KS17_UTECDH_MASK) + +#define S50_ELS_KS17_KS17_UCMAC_MASK (0x2000U) +#define S50_ELS_KS17_KS17_UCMAC_SHIFT (13U) +#define S50_ELS_KS17_KS17_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCMAC_SHIFT)) & S50_ELS_KS17_KS17_UCMAC_MASK) + +#define S50_ELS_KS17_KS17_UKSK_MASK (0x4000U) +#define S50_ELS_KS17_KS17_UKSK_SHIFT (14U) +#define S50_ELS_KS17_KS17_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKSK_SHIFT)) & S50_ELS_KS17_KS17_UKSK_MASK) + +#define S50_ELS_KS17_KS17_URTF_MASK (0x8000U) +#define S50_ELS_KS17_KS17_URTF_SHIFT (15U) +#define S50_ELS_KS17_KS17_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_URTF_SHIFT)) & S50_ELS_KS17_KS17_URTF_MASK) + +#define S50_ELS_KS17_KS17_UCKDF_MASK (0x10000U) +#define S50_ELS_KS17_KS17_UCKDF_SHIFT (16U) +#define S50_ELS_KS17_KS17_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UCKDF_SHIFT)) & S50_ELS_KS17_KS17_UCKDF_MASK) + +#define S50_ELS_KS17_KS17_UHKDF_MASK (0x20000U) +#define S50_ELS_KS17_KS17_UHKDF_SHIFT (17U) +#define S50_ELS_KS17_KS17_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHKDF_SHIFT)) & S50_ELS_KS17_KS17_UHKDF_MASK) + +#define S50_ELS_KS17_KS17_UECSG_MASK (0x40000U) +#define S50_ELS_KS17_KS17_UECSG_SHIFT (18U) +#define S50_ELS_KS17_KS17_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECSG_SHIFT)) & S50_ELS_KS17_KS17_UECSG_MASK) + +#define S50_ELS_KS17_KS17_UECDH_MASK (0x80000U) +#define S50_ELS_KS17_KS17_UECDH_SHIFT (19U) +#define S50_ELS_KS17_KS17_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UECDH_SHIFT)) & S50_ELS_KS17_KS17_UECDH_MASK) + +#define S50_ELS_KS17_KS17_UAES_MASK (0x100000U) +#define S50_ELS_KS17_KS17_UAES_SHIFT (20U) +#define S50_ELS_KS17_KS17_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UAES_SHIFT)) & S50_ELS_KS17_KS17_UAES_MASK) + +#define S50_ELS_KS17_KS17_UHMAC_MASK (0x200000U) +#define S50_ELS_KS17_KS17_UHMAC_SHIFT (21U) +#define S50_ELS_KS17_KS17_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHMAC_SHIFT)) & S50_ELS_KS17_KS17_UHMAC_MASK) + +#define S50_ELS_KS17_KS17_UKWK_MASK (0x400000U) +#define S50_ELS_KS17_KS17_UKWK_SHIFT (22U) +#define S50_ELS_KS17_KS17_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKWK_SHIFT)) & S50_ELS_KS17_KS17_UKWK_MASK) + +#define S50_ELS_KS17_KS17_UKUOK_MASK (0x800000U) +#define S50_ELS_KS17_KS17_UKUOK_SHIFT (23U) +#define S50_ELS_KS17_KS17_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKUOK_SHIFT)) & S50_ELS_KS17_KS17_UKUOK_MASK) + +#define S50_ELS_KS17_KS17_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS17_KS17_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS17_KS17_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSPMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSPMS_MASK) + +#define S50_ELS_KS17_KS17_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS17_KS17_UTLSMS_SHIFT (25U) +#define S50_ELS_KS17_KS17_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UTLSMS_SHIFT)) & S50_ELS_KS17_KS17_UTLSMS_MASK) + +#define S50_ELS_KS17_KS17_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS17_KS17_UKGSRC_SHIFT (26U) +#define S50_ELS_KS17_KS17_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UKGSRC_SHIFT)) & S50_ELS_KS17_KS17_UKGSRC_MASK) + +#define S50_ELS_KS17_KS17_UHWO_MASK (0x8000000U) +#define S50_ELS_KS17_KS17_UHWO_SHIFT (27U) +#define S50_ELS_KS17_KS17_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UHWO_SHIFT)) & S50_ELS_KS17_KS17_UHWO_MASK) + +#define S50_ELS_KS17_KS17_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS17_KS17_UWRPOK_SHIFT (28U) +#define S50_ELS_KS17_KS17_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UWRPOK_SHIFT)) & S50_ELS_KS17_KS17_UWRPOK_MASK) + +#define S50_ELS_KS17_KS17_UDUK_MASK (0x20000000U) +#define S50_ELS_KS17_KS17_UDUK_SHIFT (29U) +#define S50_ELS_KS17_KS17_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UDUK_SHIFT)) & S50_ELS_KS17_KS17_UDUK_MASK) + +#define S50_ELS_KS17_KS17_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS17_KS17_UPPROT_SHIFT (30U) +#define S50_ELS_KS17_KS17_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS17_KS17_UPPROT_SHIFT)) & S50_ELS_KS17_KS17_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS18 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS18_KS18_KSIZE_MASK (0x3U) +#define S50_ELS_KS18_KS18_KSIZE_SHIFT (0U) +/*! KS18_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS18_KS18_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KSIZE_SHIFT)) & S50_ELS_KS18_KS18_KSIZE_MASK) + +#define S50_ELS_KS18_KS18_KACT_MASK (0x20U) +#define S50_ELS_KS18_KS18_KACT_SHIFT (5U) +#define S50_ELS_KS18_KS18_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KACT_SHIFT)) & S50_ELS_KS18_KS18_KACT_MASK) + +#define S50_ELS_KS18_KS18_KBASE_MASK (0x40U) +#define S50_ELS_KS18_KS18_KBASE_SHIFT (6U) +#define S50_ELS_KS18_KS18_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_KBASE_SHIFT)) & S50_ELS_KS18_KS18_KBASE_MASK) + +#define S50_ELS_KS18_KS18_FGP_MASK (0x80U) +#define S50_ELS_KS18_KS18_FGP_SHIFT (7U) +#define S50_ELS_KS18_KS18_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FGP_SHIFT)) & S50_ELS_KS18_KS18_FGP_MASK) + +#define S50_ELS_KS18_KS18_FRTN_MASK (0x100U) +#define S50_ELS_KS18_KS18_FRTN_SHIFT (8U) +#define S50_ELS_KS18_KS18_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FRTN_SHIFT)) & S50_ELS_KS18_KS18_FRTN_MASK) + +#define S50_ELS_KS18_KS18_FHWO_MASK (0x200U) +#define S50_ELS_KS18_KS18_FHWO_SHIFT (9U) +#define S50_ELS_KS18_KS18_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_FHWO_SHIFT)) & S50_ELS_KS18_KS18_FHWO_MASK) + +#define S50_ELS_KS18_KS18_UKPUK_MASK (0x800U) +#define S50_ELS_KS18_KS18_UKPUK_SHIFT (11U) +#define S50_ELS_KS18_KS18_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKPUK_SHIFT)) & S50_ELS_KS18_KS18_UKPUK_MASK) + +#define S50_ELS_KS18_KS18_UTECDH_MASK (0x1000U) +#define S50_ELS_KS18_KS18_UTECDH_SHIFT (12U) +#define S50_ELS_KS18_KS18_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTECDH_SHIFT)) & S50_ELS_KS18_KS18_UTECDH_MASK) + +#define S50_ELS_KS18_KS18_UCMAC_MASK (0x2000U) +#define S50_ELS_KS18_KS18_UCMAC_SHIFT (13U) +#define S50_ELS_KS18_KS18_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCMAC_SHIFT)) & S50_ELS_KS18_KS18_UCMAC_MASK) + +#define S50_ELS_KS18_KS18_UKSK_MASK (0x4000U) +#define S50_ELS_KS18_KS18_UKSK_SHIFT (14U) +#define S50_ELS_KS18_KS18_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKSK_SHIFT)) & S50_ELS_KS18_KS18_UKSK_MASK) + +#define S50_ELS_KS18_KS18_URTF_MASK (0x8000U) +#define S50_ELS_KS18_KS18_URTF_SHIFT (15U) +#define S50_ELS_KS18_KS18_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_URTF_SHIFT)) & S50_ELS_KS18_KS18_URTF_MASK) + +#define S50_ELS_KS18_KS18_UCKDF_MASK (0x10000U) +#define S50_ELS_KS18_KS18_UCKDF_SHIFT (16U) +#define S50_ELS_KS18_KS18_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UCKDF_SHIFT)) & S50_ELS_KS18_KS18_UCKDF_MASK) + +#define S50_ELS_KS18_KS18_UHKDF_MASK (0x20000U) +#define S50_ELS_KS18_KS18_UHKDF_SHIFT (17U) +#define S50_ELS_KS18_KS18_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHKDF_SHIFT)) & S50_ELS_KS18_KS18_UHKDF_MASK) + +#define S50_ELS_KS18_KS18_UECSG_MASK (0x40000U) +#define S50_ELS_KS18_KS18_UECSG_SHIFT (18U) +#define S50_ELS_KS18_KS18_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECSG_SHIFT)) & S50_ELS_KS18_KS18_UECSG_MASK) + +#define S50_ELS_KS18_KS18_UECDH_MASK (0x80000U) +#define S50_ELS_KS18_KS18_UECDH_SHIFT (19U) +#define S50_ELS_KS18_KS18_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UECDH_SHIFT)) & S50_ELS_KS18_KS18_UECDH_MASK) + +#define S50_ELS_KS18_KS18_UAES_MASK (0x100000U) +#define S50_ELS_KS18_KS18_UAES_SHIFT (20U) +#define S50_ELS_KS18_KS18_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UAES_SHIFT)) & S50_ELS_KS18_KS18_UAES_MASK) + +#define S50_ELS_KS18_KS18_UHMAC_MASK (0x200000U) +#define S50_ELS_KS18_KS18_UHMAC_SHIFT (21U) +#define S50_ELS_KS18_KS18_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHMAC_SHIFT)) & S50_ELS_KS18_KS18_UHMAC_MASK) + +#define S50_ELS_KS18_KS18_UKWK_MASK (0x400000U) +#define S50_ELS_KS18_KS18_UKWK_SHIFT (22U) +#define S50_ELS_KS18_KS18_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKWK_SHIFT)) & S50_ELS_KS18_KS18_UKWK_MASK) + +#define S50_ELS_KS18_KS18_UKUOK_MASK (0x800000U) +#define S50_ELS_KS18_KS18_UKUOK_SHIFT (23U) +#define S50_ELS_KS18_KS18_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKUOK_SHIFT)) & S50_ELS_KS18_KS18_UKUOK_MASK) + +#define S50_ELS_KS18_KS18_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS18_KS18_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS18_KS18_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSPMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSPMS_MASK) + +#define S50_ELS_KS18_KS18_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS18_KS18_UTLSMS_SHIFT (25U) +#define S50_ELS_KS18_KS18_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UTLSMS_SHIFT)) & S50_ELS_KS18_KS18_UTLSMS_MASK) + +#define S50_ELS_KS18_KS18_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS18_KS18_UKGSRC_SHIFT (26U) +#define S50_ELS_KS18_KS18_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UKGSRC_SHIFT)) & S50_ELS_KS18_KS18_UKGSRC_MASK) + +#define S50_ELS_KS18_KS18_UHWO_MASK (0x8000000U) +#define S50_ELS_KS18_KS18_UHWO_SHIFT (27U) +#define S50_ELS_KS18_KS18_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UHWO_SHIFT)) & S50_ELS_KS18_KS18_UHWO_MASK) + +#define S50_ELS_KS18_KS18_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS18_KS18_UWRPOK_SHIFT (28U) +#define S50_ELS_KS18_KS18_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UWRPOK_SHIFT)) & S50_ELS_KS18_KS18_UWRPOK_MASK) + +#define S50_ELS_KS18_KS18_UDUK_MASK (0x20000000U) +#define S50_ELS_KS18_KS18_UDUK_SHIFT (29U) +#define S50_ELS_KS18_KS18_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UDUK_SHIFT)) & S50_ELS_KS18_KS18_UDUK_MASK) + +#define S50_ELS_KS18_KS18_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS18_KS18_UPPROT_SHIFT (30U) +#define S50_ELS_KS18_KS18_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS18_KS18_UPPROT_SHIFT)) & S50_ELS_KS18_KS18_UPPROT_MASK) +/*! @} */ + +/*! @name ELS_KS19 - Status Register */ +/*! @{ */ + +#define S50_ELS_KS19_KS19_KSIZE_MASK (0x3U) +#define S50_ELS_KS19_KS19_KSIZE_SHIFT (0U) +/*! KS19_KSIZE + * 0b00..128 + * 0b01..256 + */ +#define S50_ELS_KS19_KS19_KSIZE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KSIZE_SHIFT)) & S50_ELS_KS19_KS19_KSIZE_MASK) + +#define S50_ELS_KS19_KS19_KACT_MASK (0x20U) +#define S50_ELS_KS19_KS19_KACT_SHIFT (5U) +#define S50_ELS_KS19_KS19_KACT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KACT_SHIFT)) & S50_ELS_KS19_KS19_KACT_MASK) + +#define S50_ELS_KS19_KS19_KBASE_MASK (0x40U) +#define S50_ELS_KS19_KS19_KBASE_SHIFT (6U) +#define S50_ELS_KS19_KS19_KBASE(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_KBASE_SHIFT)) & S50_ELS_KS19_KS19_KBASE_MASK) + +#define S50_ELS_KS19_KS19_FGP_MASK (0x80U) +#define S50_ELS_KS19_KS19_FGP_SHIFT (7U) +#define S50_ELS_KS19_KS19_FGP(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FGP_SHIFT)) & S50_ELS_KS19_KS19_FGP_MASK) + +#define S50_ELS_KS19_KS19_FRTN_MASK (0x100U) +#define S50_ELS_KS19_KS19_FRTN_SHIFT (8U) +#define S50_ELS_KS19_KS19_FRTN(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FRTN_SHIFT)) & S50_ELS_KS19_KS19_FRTN_MASK) + +#define S50_ELS_KS19_KS19_FHWO_MASK (0x200U) +#define S50_ELS_KS19_KS19_FHWO_SHIFT (9U) +#define S50_ELS_KS19_KS19_FHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_FHWO_SHIFT)) & S50_ELS_KS19_KS19_FHWO_MASK) + +#define S50_ELS_KS19_KS19_UKPUK_MASK (0x800U) +#define S50_ELS_KS19_KS19_UKPUK_SHIFT (11U) +#define S50_ELS_KS19_KS19_UKPUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKPUK_SHIFT)) & S50_ELS_KS19_KS19_UKPUK_MASK) + +#define S50_ELS_KS19_KS19_UTECDH_MASK (0x1000U) +#define S50_ELS_KS19_KS19_UTECDH_SHIFT (12U) +#define S50_ELS_KS19_KS19_UTECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTECDH_SHIFT)) & S50_ELS_KS19_KS19_UTECDH_MASK) + +#define S50_ELS_KS19_KS19_UCMAC_MASK (0x2000U) +#define S50_ELS_KS19_KS19_UCMAC_SHIFT (13U) +#define S50_ELS_KS19_KS19_UCMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCMAC_SHIFT)) & S50_ELS_KS19_KS19_UCMAC_MASK) + +#define S50_ELS_KS19_KS19_UKSK_MASK (0x4000U) +#define S50_ELS_KS19_KS19_UKSK_SHIFT (14U) +#define S50_ELS_KS19_KS19_UKSK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKSK_SHIFT)) & S50_ELS_KS19_KS19_UKSK_MASK) + +#define S50_ELS_KS19_KS19_URTF_MASK (0x8000U) +#define S50_ELS_KS19_KS19_URTF_SHIFT (15U) +#define S50_ELS_KS19_KS19_URTF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_URTF_SHIFT)) & S50_ELS_KS19_KS19_URTF_MASK) + +#define S50_ELS_KS19_KS19_UCKDF_MASK (0x10000U) +#define S50_ELS_KS19_KS19_UCKDF_SHIFT (16U) +#define S50_ELS_KS19_KS19_UCKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UCKDF_SHIFT)) & S50_ELS_KS19_KS19_UCKDF_MASK) + +#define S50_ELS_KS19_KS19_UHKDF_MASK (0x20000U) +#define S50_ELS_KS19_KS19_UHKDF_SHIFT (17U) +#define S50_ELS_KS19_KS19_UHKDF(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHKDF_SHIFT)) & S50_ELS_KS19_KS19_UHKDF_MASK) + +#define S50_ELS_KS19_KS19_UECSG_MASK (0x40000U) +#define S50_ELS_KS19_KS19_UECSG_SHIFT (18U) +#define S50_ELS_KS19_KS19_UECSG(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECSG_SHIFT)) & S50_ELS_KS19_KS19_UECSG_MASK) + +#define S50_ELS_KS19_KS19_UECDH_MASK (0x80000U) +#define S50_ELS_KS19_KS19_UECDH_SHIFT (19U) +#define S50_ELS_KS19_KS19_UECDH(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UECDH_SHIFT)) & S50_ELS_KS19_KS19_UECDH_MASK) + +#define S50_ELS_KS19_KS19_UAES_MASK (0x100000U) +#define S50_ELS_KS19_KS19_UAES_SHIFT (20U) +#define S50_ELS_KS19_KS19_UAES(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UAES_SHIFT)) & S50_ELS_KS19_KS19_UAES_MASK) + +#define S50_ELS_KS19_KS19_UHMAC_MASK (0x200000U) +#define S50_ELS_KS19_KS19_UHMAC_SHIFT (21U) +#define S50_ELS_KS19_KS19_UHMAC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHMAC_SHIFT)) & S50_ELS_KS19_KS19_UHMAC_MASK) + +#define S50_ELS_KS19_KS19_UKWK_MASK (0x400000U) +#define S50_ELS_KS19_KS19_UKWK_SHIFT (22U) +#define S50_ELS_KS19_KS19_UKWK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKWK_SHIFT)) & S50_ELS_KS19_KS19_UKWK_MASK) + +#define S50_ELS_KS19_KS19_UKUOK_MASK (0x800000U) +#define S50_ELS_KS19_KS19_UKUOK_SHIFT (23U) +#define S50_ELS_KS19_KS19_UKUOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKUOK_SHIFT)) & S50_ELS_KS19_KS19_UKUOK_MASK) + +#define S50_ELS_KS19_KS19_UTLSPMS_MASK (0x1000000U) +#define S50_ELS_KS19_KS19_UTLSPMS_SHIFT (24U) +#define S50_ELS_KS19_KS19_UTLSPMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSPMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSPMS_MASK) + +#define S50_ELS_KS19_KS19_UTLSMS_MASK (0x2000000U) +#define S50_ELS_KS19_KS19_UTLSMS_SHIFT (25U) +#define S50_ELS_KS19_KS19_UTLSMS(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UTLSMS_SHIFT)) & S50_ELS_KS19_KS19_UTLSMS_MASK) + +#define S50_ELS_KS19_KS19_UKGSRC_MASK (0x4000000U) +#define S50_ELS_KS19_KS19_UKGSRC_SHIFT (26U) +#define S50_ELS_KS19_KS19_UKGSRC(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UKGSRC_SHIFT)) & S50_ELS_KS19_KS19_UKGSRC_MASK) + +#define S50_ELS_KS19_KS19_UHWO_MASK (0x8000000U) +#define S50_ELS_KS19_KS19_UHWO_SHIFT (27U) +#define S50_ELS_KS19_KS19_UHWO(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UHWO_SHIFT)) & S50_ELS_KS19_KS19_UHWO_MASK) + +#define S50_ELS_KS19_KS19_UWRPOK_MASK (0x10000000U) +#define S50_ELS_KS19_KS19_UWRPOK_SHIFT (28U) +#define S50_ELS_KS19_KS19_UWRPOK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UWRPOK_SHIFT)) & S50_ELS_KS19_KS19_UWRPOK_MASK) + +#define S50_ELS_KS19_KS19_UDUK_MASK (0x20000000U) +#define S50_ELS_KS19_KS19_UDUK_SHIFT (29U) +#define S50_ELS_KS19_KS19_UDUK(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UDUK_SHIFT)) & S50_ELS_KS19_KS19_UDUK_MASK) + +#define S50_ELS_KS19_KS19_UPPROT_MASK (0xC0000000U) +#define S50_ELS_KS19_KS19_UPPROT_SHIFT (30U) +#define S50_ELS_KS19_KS19_UPPROT(x) (((uint32_t)(((uint32_t)(x)) << S50_ELS_KS19_KS19_UPPROT_SHIFT)) & S50_ELS_KS19_KS19_UPPROT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group S50_Register_Masks */ + + +/* S50 - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral ELS base address */ + #define ELS_BASE (0x50054000u) + /** Peripheral ELS base address */ + #define ELS_BASE_NS (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS base pointer */ + #define ELS_NS ((S50_Type *)ELS_BASE_NS) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x50055000u) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE_NS (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1_NS ((S50_Type *)ELS_ALIAS1_BASE_NS) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x50056000u) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE_NS (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2_NS ((S50_Type *)ELS_ALIAS2_BASE_NS) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x50057000u) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE_NS (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3_NS ((S50_Type *)ELS_ALIAS3_BASE_NS) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS_NS { ELS_BASE_NS, ELS_ALIAS1_BASE_NS, ELS_ALIAS2_BASE_NS, ELS_ALIAS3_BASE_NS } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS_NS { ELS_NS, ELS_ALIAS1_NS, ELS_ALIAS2_NS, ELS_ALIAS3_NS } +#else + /** Peripheral ELS base address */ + #define ELS_BASE (0x40054000u) + /** Peripheral ELS base pointer */ + #define ELS ((S50_Type *)ELS_BASE) + /** Peripheral ELS_ALIAS1 base address */ + #define ELS_ALIAS1_BASE (0x40055000u) + /** Peripheral ELS_ALIAS1 base pointer */ + #define ELS_ALIAS1 ((S50_Type *)ELS_ALIAS1_BASE) + /** Peripheral ELS_ALIAS2 base address */ + #define ELS_ALIAS2_BASE (0x40056000u) + /** Peripheral ELS_ALIAS2 base pointer */ + #define ELS_ALIAS2 ((S50_Type *)ELS_ALIAS2_BASE) + /** Peripheral ELS_ALIAS3 base address */ + #define ELS_ALIAS3_BASE (0x40057000u) + /** Peripheral ELS_ALIAS3 base pointer */ + #define ELS_ALIAS3 ((S50_Type *)ELS_ALIAS3_BASE) + /** Array initializer of S50 peripheral base addresses */ + #define S50_BASE_ADDRS { ELS_BASE, ELS_ALIAS1_BASE, ELS_ALIAS2_BASE, ELS_ALIAS3_BASE } + /** Array initializer of S50 peripheral base pointers */ + #define S50_BASE_PTRS { ELS, ELS_ALIAS1, ELS_ALIAS2, ELS_ALIAS3 } +#endif + +/*! + * @} + */ /* end of group S50_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer + * @{ + */ + +/** SCG - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TRIM_LOCK; /**< Trim Lock register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ + __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __IO uint32_t SOSCCSR; /**< SOSC Control Status Register, offset: 0x100 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOSCCFG; /**< SOSC Configuration Register, offset: 0x108 */ + uint8_t RESERVED_3[244]; + __IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */ + __IO uint32_t SIRCTRIM; /**< SIRC Trim Register, offset: 0x210 */ + uint8_t RESERVED_5[4]; + __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */ + uint8_t RESERVED_6[228]; + __IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */ + uint8_t RESERVED_7[4]; + __IO uint32_t FIRCCFG; /**< FIRC Configuration Register, offset: 0x308 */ + __IO uint32_t FIRCTCFG; /**< FIRC Trim Configuration Register, offset: 0x30C */ + __IO uint32_t FIRCTRIM; /**< FIRC Trim Register, offset: 0x310 */ + uint8_t RESERVED_8[4]; + __IO uint32_t FIRCSTAT; /**< FIRC Auto-trimming Status Register, offset: 0x318 */ + uint8_t RESERVED_9[228]; + __IO uint32_t ROSCCSR; /**< ROSC Control Status Register, offset: 0x400 */ + uint8_t RESERVED_10[252]; + __IO uint32_t APLLCSR; /**< APLL Control Status Register, offset: 0x500 */ + __IO uint32_t APLLCTRL; /**< APLL Control Register, offset: 0x504 */ + __I uint32_t APLLSTAT; /**< APLL Status Register, offset: 0x508 */ + __IO uint32_t APLLNDIV; /**< APLL N Divider Register, offset: 0x50C */ + __IO uint32_t APLLMDIV; /**< APLL M Divider Register, offset: 0x510 */ + __IO uint32_t APLLPDIV; /**< APLL P Divider Register, offset: 0x514 */ + __IO uint32_t APLLLOCK_CNFG; /**< APLL LOCK Configuration Register, offset: 0x518 */ + uint8_t RESERVED_11[4]; + __I uint32_t APLLSSCGSTAT; /**< APLL SSCG Status Register, offset: 0x520 */ + __IO uint32_t APLLSSCG0; /**< APLL Spread Spectrum Control 0 Register, offset: 0x524 */ + __IO uint32_t APLLSSCG1; /**< APLL Spread Spectrum Control 1 Register, offset: 0x528 */ + uint8_t RESERVED_12[200]; + __IO uint32_t APLL_OVRD; /**< APLL Override Register, offset: 0x5F4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t SPLLCSR; /**< SPLL Control Status Register, offset: 0x600 */ + __IO uint32_t SPLLCTRL; /**< SPLL Control Register, offset: 0x604 */ + __I uint32_t SPLLSTAT; /**< SPLL Status Register, offset: 0x608 */ + __IO uint32_t SPLLNDIV; /**< SPLL N Divider Register, offset: 0x60C */ + __IO uint32_t SPLLMDIV; /**< SPLL M Divider Register, offset: 0x610 */ + __IO uint32_t SPLLPDIV; /**< SPLL P Divider Register, offset: 0x614 */ + __IO uint32_t SPLLLOCK_CNFG; /**< SPLL LOCK Configuration Register, offset: 0x618 */ + uint8_t RESERVED_14[4]; + __I uint32_t SPLLSSCGSTAT; /**< SPLL SSCG Status Register, offset: 0x620 */ + __IO uint32_t SPLLSSCG0; /**< SPLL Spread Spectrum Control 0 Register, offset: 0x624 */ + __IO uint32_t SPLLSSCG1; /**< SPLL Spread Spectrum Control 1 Register, offset: 0x628 */ + uint8_t RESERVED_15[200]; + __IO uint32_t SPLL_OVRD; /**< SPLL Override Register, offset: 0x6F4 */ + uint8_t RESERVED_16[8]; + __IO uint32_t UPLLCSR; /**< UPLL Control Status Register, offset: 0x700 */ + uint8_t RESERVED_17[252]; + __IO uint32_t LDOCSR; /**< LDO Control and Status Register, offset: 0x800 */ + uint8_t RESERVED_18[252]; + __IO uint32_t TROCSR; /**< TRO Control Status Register, offset: 0x900 */ +} SCG_Type; + +/* ---------------------------------------------------------------------------- + -- SCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Register_Masks SCG Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) +#define SCG_VERID_VERSION_SHIFT (0U) +/*! VERSION - SCG Version Number */ +#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define SCG_PARAM_SOSCCLKPRES_MASK (0x2U) +#define SCG_PARAM_SOSCCLKPRES_SHIFT (1U) +/*! SOSCCLKPRES - SOSC Clock Present + * 0b1..SOSC clock source is present + * 0b0..SOSC clock source is not present + */ +#define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK) + +#define SCG_PARAM_SIRCCLKPRES_MASK (0x4U) +#define SCG_PARAM_SIRCCLKPRES_SHIFT (2U) +/*! SIRCCLKPRES - SIRC Clock Present + * 0b1..SIRC clock source is present + * 0b0..SIRC clock source is not present + */ +#define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK) + +#define SCG_PARAM_FIRCCLKPRES_MASK (0x8U) +#define SCG_PARAM_FIRCCLKPRES_SHIFT (3U) +/*! FIRCCLKPRES - FIRC Clock Present + * 0b1..FIRC clock source is present + * 0b0..FIRC clock source is not present + */ +#define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK) + +#define SCG_PARAM_ROSCCLKPRES_MASK (0x10U) +#define SCG_PARAM_ROSCCLKPRES_SHIFT (4U) +/*! ROSCCLKPRES - ROSC Clock Present + * 0b1..ROSC clock source is present + * 0b0..ROSC clock source is not present + */ +#define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK) + +#define SCG_PARAM_APLLCLKPRES_MASK (0x20U) +#define SCG_PARAM_APLLCLKPRES_SHIFT (5U) +/*! APLLCLKPRES - APLL Clock Present + * 0b1..APLL clock source is present + * 0b0..APLL clock source is not present + */ +#define SCG_PARAM_APLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_APLLCLKPRES_SHIFT)) & SCG_PARAM_APLLCLKPRES_MASK) + +#define SCG_PARAM_SPLLCLKPRES_MASK (0x40U) +#define SCG_PARAM_SPLLCLKPRES_SHIFT (6U) +/*! SPLLCLKPRES - SPLL Clock Present + * 0b1..SPLL clock source is present + * 0b0..SPLL clock source is not present + */ +#define SCG_PARAM_SPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SPLLCLKPRES_SHIFT)) & SCG_PARAM_SPLLCLKPRES_MASK) + +#define SCG_PARAM_UPLLCLKPRES_MASK (0x80U) +#define SCG_PARAM_UPLLCLKPRES_SHIFT (7U) +/*! UPLLCLKPRES - UPLL Clock Present + * 0b1..UPLL clock source is present + * 0b0..UPLL clock source is not present + */ +#define SCG_PARAM_UPLLCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_UPLLCLKPRES_SHIFT)) & SCG_PARAM_UPLLCLKPRES_MASK) + +#define SCG_PARAM_TROCLKPRES_MASK (0x100U) +#define SCG_PARAM_TROCLKPRES_SHIFT (8U) +/*! TROCLKPRES - TRO Clock Present + * 0b1..TRO clock source is present + * 0b0..TRO clock source is not present + */ +#define SCG_PARAM_TROCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_TROCLKPRES_SHIFT)) & SCG_PARAM_TROCLKPRES_MASK) +/*! @} */ + +/*! @name TRIM_LOCK - Trim Lock register */ +/*! @{ */ + +#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U) +#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U) +/*! TRIM_UNLOCK - TRIM_UNLOCK + * 0b0..SCG Trim registers are locked and not writable. + * 0b1..SCG Trim registers are unlocked and writable. + */ +#define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK) + +#define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U) +#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U) +/*! IFR_DISABLE - IFR_DISABLE + * 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. + * 0b1..IFR write access to SCG trim registers during system reset is blocked. + */ +#define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK) + +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U) +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U) +/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */ +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK) +/*! @} */ + +/*! @name CSR - Clock Status Register */ +/*! @{ */ + +#define SCG_CSR_SCS_MASK (0xF000000U) +#define SCG_CSR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b0000..Reserved + * 0b0001..SOSC + * 0b0010..SIRC + * 0b0011..FIRC + * 0b0100..ROSC + * 0b0101..APLL + * 0b0110..SPLL + * 0b0111..UPLL + * 0b1000..TRO + * 0b1001-0b1111..Reserved + */ +#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) +/*! @} */ + +/*! @name RCCR - Run Clock Control Register */ +/*! @{ */ + +#define SCG_RCCR_SCS_MASK (0xF000000U) +#define SCG_RCCR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b0000..Reserved + * 0b0001..SOSC + * 0b0010..SIRC + * 0b0011..FIRC + * 0b0100..ROSC + * 0b0101..APLL + * 0b0110..SPLL + * 0b0111..UPLL + * 0b1000..TRO + * 0b1001-0b1111..Reserved + */ +#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) +/*! @} */ + +/*! @name SOSCCSR - SOSC Control Status Register */ +/*! @{ */ + +#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) +#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) +/*! SOSCEN - SOSC Enable + * 0b0..SOSC is disabled + * 0b1..SOSC is enabled + */ +#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) + +#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) +#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) +/*! SOSCSTEN - SOSC Stop Enable + * 0b0..SOSC is disabled in Deep Sleep mode + * 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set + */ +#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) + +#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) +#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) +/*! SOSCCM - SOSC Clock Monitor Enable + * 0b0..SOSC Clock Monitor is disabled + * 0b1..SOSC Clock Monitor is enabled + */ +#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) + +#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) +#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) +/*! SOSCCMRE - SOSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) + +#define SCG_SOSCCSR_LK_MASK (0x800000U) +#define SCG_SOSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..This Control Status Register can be written + * 0b1..This Control Status Register cannot be written + */ +#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) + +#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) +#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) +/*! SOSCVLD - SOSC Valid + * 0b0..SOSC is not enabled or clock is not valid + * 0b1..SOSC is enabled and output clock is valid + */ +#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) + +#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) +#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) +/*! SOSCSEL - SOSC Selected + * 0b0..SOSC is not the system clock source + * 0b1..SOSC is the system clock source + */ +#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) + +#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) +#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) +/*! SOSCERR - SOSC Clock Error + * 0b0..SOSC Clock Monitor is disabled or has not detected an error + * 0b1..SOSC Clock Monitor is enabled and detected an error + */ +#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) + +#define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U) +#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U) +/*! SOSCVLD_IE - SOSC Valid Interrupt Enable + * 0b0..SOSCVLD interrupt is not enabled + * 0b1..SOSCVLD interrupt is enabled + */ +#define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK) +/*! @} */ + +/*! @name SOSCCFG - SOSC Configuration Register */ +/*! @{ */ + +#define SCG_SOSCCFG_EREFS_MASK (0x4U) +#define SCG_SOSCCFG_EREFS_SHIFT (2U) +/*! EREFS - External Reference Select + * 0b0..External reference clock selected. LDO can be disabled in this case. + * 0b1..Internal crystal oscillator of OSC selected. + */ +#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) + +#define SCG_SOSCCFG_RANGE_MASK (0x30U) +#define SCG_SOSCCFG_RANGE_SHIFT (4U) +/*! RANGE - SOSC Range Select + * 0b00..Frequency range select of 16-20 MHz. + * 0b01..Frequency range select of 20-30 MHz. + * 0b10..Frequency range select of 30-50 MHz. + * 0b11..Frequency range select of 50-66 MHz. + */ +#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) +/*! @} */ + +/*! @name SIRCCSR - SIRC Control Status Register */ +/*! @{ */ + +#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) +#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) +/*! SIRCSTEN - SIRC Stop Enable + * 0b0..SIRC is disabled in Deep Sleep mode + * 0b1..SIRC is enabled in Deep Sleep mode + */ +#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) + +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U) +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U) +/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable + * 0b0..SIRC clock to peripherals is disabled + * 0b1..SIRC clock to peripherals is enabled + */ +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) + +#define SCG_SIRCCSR_SIRCTREN_MASK (0x100U) +#define SCG_SIRCCSR_SIRCTREN_SHIFT (8U) +/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) + * 0b0..Disables trimming SIRC to an external clock source + * 0b1..Enables trimming SIRC to an external clock source + */ +#define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK) + +#define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U) +#define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U) +/*! SIRCTRUP - SIRC Trim Update + * 0b0..Disables SIRC trimming updates + * 0b1..Enables SIRC trimming updates + */ +#define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK) + +#define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - SIRC TRIM LOCK + * 0b0..SIRC auto trim not locked to target frequency range + * 0b1..SIRC auto trim locked to target frequency range + */ +#define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK) + +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..SIRC coarse auto-trim is not bypassed + * 0b1..SIRC coarse auto-trim is bypassed + */ +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_SIRCCSR_LK_MASK (0x800000U) +#define SCG_SIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) + +#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) +#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) +/*! SIRCVLD - SIRC Valid + * 0b0..SIRC is not enabled or clock is not valid + * 0b1..SIRC is enabled and output clock is valid + */ +#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) + +#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) +#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) +/*! SIRCSEL - SIRC Selected + * 0b0..SIRC is not the system clock source + * 0b1..SIRC is the system clock source + */ +#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) + +#define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U) +#define SCG_SIRCCSR_SIRCERR_SHIFT (26U) +/*! SIRCERR - SIRC Clock Error + * 0b0..Error not detected with the SIRC trimming + * 0b1..Error detected with the SIRC trimming + */ +#define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK) + +#define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U) +#define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U) +/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable + * 0b0..SIRCERR interrupt is not enabled + * 0b1..SIRCERR interrupt is enabled + */ +#define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK) +/*! @} */ + +/*! @name SIRCTCFG - SIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..Reserved + * 0b01..Reserved + * 0b10..SOSC + * 0b11..ROSC (32.768 kHz) + */ +#define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK) + +#define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - SIRC Trim Predivider */ +#define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name SIRCTRIM - SIRC Trim Register */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + +/*! @name SIRCSTAT - SIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK) + +#define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCSTAT_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK) +/*! @} */ + +/*! @name FIRCCSR - FIRC Control Status Register */ +/*! @{ */ + +#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) +#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) +/*! FIRCEN - FIRC Enable + * 0b0..FIRC is disabled + * 0b1..FIRC is enabled + */ +#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) + +#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) +#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) +/*! FIRCSTEN - FIRC Stop Enable + * 0b0..FIRC is disabled in Deep Sleep mode + * 0b1..FIRC is enabled in Deep Sleep mode + */ +#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) + +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U) +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U) +/*! FIRC_SCLK_PERIPH_EN - FIRC 48 MHz Clock to peripherals Enable + * 0b0..FIRC 48 MHz to peripherals is disabled + * 0b1..FIRC 48 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U) +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U) +/*! FIRC_FCLK_PERIPH_EN - FIRC 144 MHz Clock to peripherals Enable + * 0b0..FIRC 144 MHz to peripherals is disabled + * 0b1..FIRC 144 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) +#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) +/*! FIRCTREN - FIRC 144 MHz Trim Enable (FIRCCFG[RANGE]=1) + * 0b0..Disables trimming FIRC to an external clock source + * 0b1..Enables trimming FIRC to an external clock source + */ +#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) + +#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) +#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) +/*! FIRCTRUP - FIRC Trim Update + * 0b0..Disables FIRC trimming updates + * 0b1..Enables FIRC trimming updates + */ +#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) + +#define SCG_FIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_FIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - FIRC TRIM LOCK + * 0b0..FIRC auto trim not locked to target frequency range + * 0b1..FIRC auto trim locked to target frequency range + */ +#define SCG_FIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK) + +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..FIRC coarse auto trim is not bypassed + * 0b1..FIRC coarse auto trim is bypassed + */ +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_FIRCCSR_LK_MASK (0x800000U) +#define SCG_FIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) + +#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) +#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) +/*! FIRCVLD - FIRC Valid status + * 0b0..FIRC is not enabled or clock is not valid. + * 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) + +#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) +#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) +/*! FIRCSEL - FIRC Selected + * 0b0..FIRC is not the system clock source + * 0b1..FIRC is the system clock source + */ +#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) + +#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) +#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) +/*! FIRCERR - FIRC Clock Error + * 0b0..Error not detected with the FIRC trimming + * 0b1..Error detected with the FIRC trimming + */ +#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) + +#define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) +#define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U) +/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable + * 0b0..FIRCERR interrupt is not enabled + * 0b1..FIRCERR interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U) +#define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U) +/*! FIRCACC_IE - FIRC Accurate Interrupt Enable + * 0b0..FIRCACC interrupt is not enabled + * 0b1..FIRCACC interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U) +#define SCG_FIRCCSR_FIRCACC_SHIFT (31U) +/*! FIRCACC - FIRC Frequency Accurate + * 0b0..FIRC is not enabled or clock is not accurate. + * 0b1..FIRC is enabled and output clock is accurate. The clock is accurate after 4096 clock cycles of 144 MHz + * (RANGE=1) or 1365 clock cycles of 48 MHz(RANGE=0) from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK) +/*! @} */ + +/*! @name FIRCCFG - FIRC Configuration Register */ +/*! @{ */ + +#define SCG_FIRCCFG_RANGE_MASK (0x1U) +#define SCG_FIRCCFG_RANGE_SHIFT (0U) +/*! RANGE - Frequency Range + * 0b0..48 MHz FIRC clock selected + * 0b1..144 MHz FIRC clock selected + */ +#define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_RANGE_SHIFT)) & SCG_FIRCCFG_RANGE_MASK) +/*! @} */ + +/*! @name FIRCTCFG - FIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..USB0 Start of Frame (1 kHz). This option does not use TRIMDIV + * 0b01..Reserved + * 0b10..SOSC + * 0b11..ROSC + */ +#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) + +#define SCG_FIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_FIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - FIRC Trim Predivider */ +#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name FIRCTRIM - FIRC Trim Register */ +/*! @{ */ + +#define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK) + +#define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK) + +#define SCG_FIRCTRIM_TRIMTEMP_MASK (0x30000U) +#define SCG_FIRCTRIM_TRIMTEMP_SHIFT (16U) +/*! TRIMTEMP - Trim Temperature */ +#define SCG_FIRCTRIM_TRIMTEMP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP_MASK) + +#define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U) +#define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U) +/*! TRIMSTART - Trim Start */ +#define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK) +/*! @} */ + +/*! @name FIRCSTAT - FIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_FIRCSTAT_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) + +#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) +/*! @} */ + +/*! @name ROSCCSR - ROSC Control Status Register */ +/*! @{ */ + +#define SCG_ROSCCSR_ROSCCM_MASK (0x10000U) +#define SCG_ROSCCSR_ROSCCM_SHIFT (16U) +/*! ROSCCM - ROSC Clock Monitor + * 0b0..ROSC clock monitor is disabled + * 0b1..ROSC clock monitor is enabled + */ +#define SCG_ROSCCSR_ROSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCM_SHIFT)) & SCG_ROSCCSR_ROSCCM_MASK) + +#define SCG_ROSCCSR_ROSCCMRE_MASK (0x20000U) +#define SCG_ROSCCSR_ROSCCMRE_SHIFT (17U) +/*! ROSCCMRE - ROSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_ROSCCSR_ROSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCCMRE_SHIFT)) & SCG_ROSCCSR_ROSCCMRE_MASK) + +#define SCG_ROSCCSR_LK_MASK (0x800000U) +#define SCG_ROSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) + +#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) +#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) +/*! ROSCVLD - ROSC Valid + * 0b0..ROSC is not enabled or clock is not valid + * 0b1..ROSC is enabled and output clock is valid + */ +#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) + +#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) +#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) +/*! ROSCSEL - ROSC Selected + * 0b0..ROSC is not the system clock source + * 0b1..ROSC is the system clock source + */ +#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) + +#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) +#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) +/*! ROSCERR - ROSC Clock Error + * 0b0..ROSC Clock Monitor is disabled or has not detected an error + * 0b1..ROSC Clock Monitor is enabled and detected an RTC loss of clock error + */ +#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) +/*! @} */ + +/*! @name APLLCSR - APLL Control Status Register */ +/*! @{ */ + +#define SCG_APLLCSR_APLLPWREN_MASK (0x1U) +#define SCG_APLLCSR_APLLPWREN_SHIFT (0U) +/*! APLLPWREN - APLL Power Enable + * 0b0..APLL clock is powered off + * 0b1..APLL clock is powered on + */ +#define SCG_APLLCSR_APLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLPWREN_SHIFT)) & SCG_APLLCSR_APLLPWREN_MASK) + +#define SCG_APLLCSR_APLLCLKEN_MASK (0x2U) +#define SCG_APLLCSR_APLLCLKEN_SHIFT (1U) +/*! APLLCLKEN - APLL Clock Enable + * 0b0..APLL clock is disabled + * 0b1..APLL clock is enabled + */ +#define SCG_APLLCSR_APLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCLKEN_SHIFT)) & SCG_APLLCSR_APLLCLKEN_MASK) + +#define SCG_APLLCSR_APLLSTEN_MASK (0x4U) +#define SCG_APLLCSR_APLLSTEN_SHIFT (2U) +/*! APLLSTEN - APLL Stop Enable + * 0b0..APLL is disabled in Deep Sleep mode + * 0b1..APLL is enabled in Deep Sleep mode + */ +#define SCG_APLLCSR_APLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSTEN_SHIFT)) & SCG_APLLCSR_APLLSTEN_MASK) + +#define SCG_APLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) +#define SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) +/*! FRM_CLOCKSTABLE - Free running mode clock stable + * 0b0..Free running mode clockstable is disabled + * 0b1..Free running mode clockstable is enabled + */ +#define SCG_APLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_APLLCSR_FRM_CLOCKSTABLE_MASK) + +#define SCG_APLLCSR_APLLCM_MASK (0x10000U) +#define SCG_APLLCSR_APLLCM_SHIFT (16U) +/*! APLLCM - APLL Clock Monitor + * 0b0..APLL Clock Monitor is disabled + * 0b1..APLL Clock Monitor is enabled + */ +#define SCG_APLLCSR_APLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCM_SHIFT)) & SCG_APLLCSR_APLLCM_MASK) + +#define SCG_APLLCSR_APLLCMRE_MASK (0x20000U) +#define SCG_APLLCSR_APLLCMRE_SHIFT (17U) +/*! APLLCMRE - APLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_APLLCSR_APLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLCMRE_SHIFT)) & SCG_APLLCSR_APLLCMRE_MASK) + +#define SCG_APLLCSR_LK_MASK (0x800000U) +#define SCG_APLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_APLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_LK_SHIFT)) & SCG_APLLCSR_LK_MASK) + +#define SCG_APLLCSR_APLL_LOCK_MASK (0x1000000U) +#define SCG_APLLCSR_APLL_LOCK_SHIFT (24U) +/*! APLL_LOCK - APLL LOCK + * 0b0..APLL is not powered on or not locked + * 0b1..APLL is locked + */ +#define SCG_APLLCSR_APLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_SHIFT)) & SCG_APLLCSR_APLL_LOCK_MASK) + +#define SCG_APLLCSR_APLLSEL_MASK (0x2000000U) +#define SCG_APLLCSR_APLLSEL_SHIFT (25U) +/*! APLLSEL - APLL Selected + * 0b0..APLL is not the system clock source + * 0b1..APLL is the system clock source + */ +#define SCG_APLLCSR_APLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLSEL_SHIFT)) & SCG_APLLCSR_APLLSEL_MASK) + +#define SCG_APLLCSR_APLLERR_MASK (0x4000000U) +#define SCG_APLLCSR_APLLERR_SHIFT (26U) +/*! APLLERR - APLL Clock Error + * 0b0..APLL Clock Monitor is disabled or has not detected an error + * 0b1..APLL Clock Monitor is enabled and detected an error + */ +#define SCG_APLLCSR_APLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLLERR_SHIFT)) & SCG_APLLCSR_APLLERR_MASK) + +#define SCG_APLLCSR_APLL_LOCK_IE_MASK (0x40000000U) +#define SCG_APLLCSR_APLL_LOCK_IE_SHIFT (30U) +/*! APLL_LOCK_IE - APLL LOCK Interrupt Enable + * 0b0..APLL_LOCK interrupt is not enabled + * 0b1..APLL_LOCK interrupt is enabled + */ +#define SCG_APLLCSR_APLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCSR_APLL_LOCK_IE_SHIFT)) & SCG_APLLCSR_APLL_LOCK_IE_MASK) +/*! @} */ + +/*! @name APLLCTRL - APLL Control Register */ +/*! @{ */ + +#define SCG_APLLCTRL_SELR_MASK (0xFU) +#define SCG_APLLCTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R (resistor) value. */ +#define SCG_APLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELR_SHIFT)) & SCG_APLLCTRL_SELR_MASK) + +#define SCG_APLLCTRL_SELI_MASK (0x3F0U) +#define SCG_APLLCTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I (integration) value. */ +#define SCG_APLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELI_SHIFT)) & SCG_APLLCTRL_SELI_MASK) + +#define SCG_APLLCTRL_SELP_MASK (0x7C00U) +#define SCG_APLLCTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P (proportional) value. */ +#define SCG_APLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SELP_SHIFT)) & SCG_APLLCTRL_SELP_MASK) + +#define SCG_APLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider + * 0b0..Use the divide-by-2 divider in the postdivider + * 0b1..Bypass of the divide-by-2 divider in the postdivider + */ +#define SCG_APLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) + +#define SCG_APLLCTRL_LIMUPOFF_MASK (0x20000U) +#define SCG_APLLCTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - Up Limiter + * 0b0..Application set to non-Spectrum and Fractional applications. + * 0b1..Application set to Spectrum and Fractional applications. + */ +#define SCG_APLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_LIMUPOFF_SHIFT)) & SCG_APLLCTRL_LIMUPOFF_MASK) + +#define SCG_APLLCTRL_BANDDIRECT_MASK (0x40000U) +#define SCG_APLLCTRL_BANDDIRECT_SHIFT (18U) +/*! BANDDIRECT - Control of the bandwidth of the PLL. + * 0b0..The bandwidth is changed synchronously with the feedback-divider + * 0b1..Modifies the bandwidth of the PLL directly + */ +#define SCG_APLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BANDDIRECT_SHIFT)) & SCG_APLLCTRL_BANDDIRECT_MASK) + +#define SCG_APLLCTRL_BYPASSPREDIV_MASK (0x80000U) +#define SCG_APLLCTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - Bypass of the predivider + * 0b0..Use the predivider. + * 0b1..Bypass of the predivider. + */ +#define SCG_APLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPREDIV_MASK) + +#define SCG_APLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - Bypass of the postdivider + * 0b0..Use the postdivider. + * 0b1..Bypass of the postdivider + */ +#define SCG_APLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) + +#define SCG_APLLCTRL_FRM_MASK (0x400000U) +#define SCG_APLLCTRL_FRM_SHIFT (22U) +/*! FRM - Free Running Mode Enable + * 0b0..Free running mode disabled + * 0b1..Free running mode enabled + */ +#define SCG_APLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_FRM_SHIFT)) & SCG_APLLCTRL_FRM_MASK) + +#define SCG_APLLCTRL_SOURCE_MASK (0x6000000U) +#define SCG_APLLCTRL_SOURCE_SHIFT (25U) +/*! SOURCE - Clock Source + * 0b00..SOSC + * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. + * 0b10..ROSC + * 0b11..No clock + */ +#define SCG_APLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLCTRL_SOURCE_SHIFT)) & SCG_APLLCTRL_SOURCE_MASK) +/*! @} */ + +/*! @name APLLSTAT - APLL Status Register */ +/*! @{ */ + +#define SCG_APLLSTAT_NDIVACK_MASK (0x2U) +#define SCG_APLLSTAT_NDIVACK_SHIFT (1U) +/*! NDIVACK - Predivider(N) ratio change acknowledge. + * 0b0..The predivider (N) ratio change is not accepted by the analog PLL + * 0b1..The predivider (N) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_NDIVACK_SHIFT)) & SCG_APLLSTAT_NDIVACK_MASK) + +#define SCG_APLLSTAT_MDIVACK_MASK (0x4U) +#define SCG_APLLSTAT_MDIVACK_SHIFT (2U) +/*! MDIVACK - Feedback(M) divider ratio change acknowledge. + * 0b0..The feedback (M) ratio change is not accepted by the analog PLL + * 0b1..The feedback (M) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_MDIVACK_SHIFT)) & SCG_APLLSTAT_MDIVACK_MASK) + +#define SCG_APLLSTAT_PDIVACK_MASK (0x8U) +#define SCG_APLLSTAT_PDIVACK_SHIFT (3U) +/*! PDIVACK - Postdivider(P) ratio change acknowledge. + * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL + * 0b1..The postdivider (P) ratio change is accepted by the analog PLL + */ +#define SCG_APLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_PDIVACK_SHIFT)) & SCG_APLLSTAT_PDIVACK_MASK) + +#define SCG_APLLSTAT_FRMDET_MASK (0x10U) +#define SCG_APLLSTAT_FRMDET_SHIFT (4U) +/*! FRMDET - Free running detector (active high) + * 0b0..Free running is not detected + * 0b1..Free running is detected + */ +#define SCG_APLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSTAT_FRMDET_SHIFT)) & SCG_APLLSTAT_FRMDET_MASK) +/*! @} */ + +/*! @name APLLNDIV - APLL N Divider Register */ +/*! @{ */ + +#define SCG_APLLNDIV_NDIV_MASK (0xFFU) +#define SCG_APLLNDIV_NDIV_SHIFT (0U) +/*! NDIV - Predivider divider ratio (N-divider). */ +#define SCG_APLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NDIV_SHIFT)) & SCG_APLLNDIV_NDIV_MASK) + +#define SCG_APLLNDIV_NREQ_MASK (0x80000000U) +#define SCG_APLLNDIV_NREQ_SHIFT (31U) +/*! NREQ - Predivider ratio change request. + * 0b0..Predivider ratio change is not requested + * 0b1..Predivider ratio change is requested + */ +#define SCG_APLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLNDIV_NREQ_SHIFT)) & SCG_APLLNDIV_NREQ_MASK) +/*! @} */ + +/*! @name APLLMDIV - APLL M Divider Register */ +/*! @{ */ + +#define SCG_APLLMDIV_MDIV_MASK (0xFFFFU) +#define SCG_APLLMDIV_MDIV_SHIFT (0U) +/*! MDIV - Feedback divider divider ratio (M-divider). */ +#define SCG_APLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MDIV_SHIFT)) & SCG_APLLMDIV_MDIV_MASK) + +#define SCG_APLLMDIV_MREQ_MASK (0x80000000U) +#define SCG_APLLMDIV_MREQ_SHIFT (31U) +/*! MREQ - Feedback ratio change request. + * 0b0..Feedback ratio change is not requested + * 0b1..Feedback ratio change is requested + */ +#define SCG_APLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLMDIV_MREQ_SHIFT)) & SCG_APLLMDIV_MREQ_MASK) +/*! @} */ + +/*! @name APLLPDIV - APLL P Divider Register */ +/*! @{ */ + +#define SCG_APLLPDIV_PDIV_MASK (0x1FU) +#define SCG_APLLPDIV_PDIV_SHIFT (0U) +/*! PDIV - Postdivider divider ratio (P-divider) */ +#define SCG_APLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PDIV_SHIFT)) & SCG_APLLPDIV_PDIV_MASK) + +#define SCG_APLLPDIV_PREQ_MASK (0x80000000U) +#define SCG_APLLPDIV_PREQ_SHIFT (31U) +/*! PREQ - Postdivider ratio change request + * 0b0..Postdivider ratio change is not requested + * 0b1..Postdivider ratio change is requested + */ +#define SCG_APLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLPDIV_PREQ_SHIFT)) & SCG_APLLPDIV_PREQ_MASK) +/*! @} */ + +/*! @name APLLLOCK_CNFG - APLL LOCK Configuration Register */ +/*! @{ */ + +#define SCG_APLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) +#define SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) +/*! LOCK_TIME - Configures the number of reference clocks to count before APLL is considered locked. */ +#define SCG_APLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_APLLLOCK_CNFG_LOCK_TIME_MASK) +/*! @} */ + +/*! @name APLLSSCGSTAT - APLL SSCG Status Register */ +/*! @{ */ + +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) +/*! SS_MDIV_ACK - SS_MDIV change acknowledge + * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL + * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL + */ +#define SCG_APLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_APLLSSCGSTAT_SS_MDIV_ACK_MASK) +/*! @} */ + +/*! @name APLLSSCG0 - APLL Spread Spectrum Control 0 Register */ +/*! @{ */ + +#define SCG_APLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) +#define SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT (0U) +/*! SS_MDIV_LSB - SS_MDIV */ +#define SCG_APLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_APLLSSCG0_SS_MDIV_LSB_MASK) +/*! @} */ + +/*! @name APLLSSCG1 - APLL Spread Spectrum Control 1 Register */ +/*! @{ */ + +#define SCG_APLLSSCG1_SS_MDIV_MSB_MASK (0x1U) +#define SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT (0U) +/*! SS_MDIV_MSB - SS_MDIV[32] */ +#define SCG_APLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) + +#define SCG_APLLSSCG1_SS_MDIV_REQ_MASK (0x2U) +#define SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT (1U) +/*! SS_MDIV_REQ - SS_MDIV[32:0] change request. + * 0b0..SS_MDIV change is not requested + * 0b1..SS_MDIV change is requested + */ +#define SCG_APLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_APLLSSCG1_SS_MDIV_REQ_MASK) + +#define SCG_APLLSSCG1_MF_MASK (0x1CU) +#define SCG_APLLSSCG1_MF_SHIFT (2U) +/*! MF - Modulation Frequency Control */ +#define SCG_APLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MF_SHIFT)) & SCG_APLLSSCG1_MF_MASK) + +#define SCG_APLLSSCG1_MR_MASK (0xE0U) +#define SCG_APLLSSCG1_MR_SHIFT (5U) +/*! MR - Modulation Depth Control */ +#define SCG_APLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MR_SHIFT)) & SCG_APLLSSCG1_MR_MASK) + +#define SCG_APLLSSCG1_MC_MASK (0x300U) +#define SCG_APLLSSCG1_MC_SHIFT (8U) +/*! MC - Modulation Waveform Control + * 0b00..MC[1:0] no compensation + * 0b11..MC[1:0] maximum compensation + */ +#define SCG_APLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_MC_SHIFT)) & SCG_APLLSSCG1_MC_MASK) + +#define SCG_APLLSSCG1_DITHER_MASK (0x400U) +#define SCG_APLLSSCG1_DITHER_SHIFT (10U) +/*! DITHER - Dither Enable + * 0b0..Dither is not enabled + * 0b1..Dither is enabled + */ +#define SCG_APLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_DITHER_SHIFT)) & SCG_APLLSSCG1_DITHER_MASK) + +#define SCG_APLLSSCG1_SEL_SS_MDIV_MASK (0x800U) +#define SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT (11U) +/*! SEL_SS_MDIV - SS_MDIV select. + * 0b0..Feedback divider ratio is MDIV[15:0] + * 0b1..Feedback divider ratio is SS_MDIV[32:0] + */ +#define SCG_APLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) + +#define SCG_APLLSSCG1_SS_PD_MASK (0x80000000U) +#define SCG_APLLSSCG1_SS_PD_SHIFT (31U) +/*! SS_PD - SSCG Power Down + * 0b0..SSCG is powered on + * 0b1..SSCG is powered off + */ +#define SCG_APLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLLSSCG1_SS_PD_SHIFT)) & SCG_APLLSSCG1_SS_PD_MASK) +/*! @} */ + +/*! @name APLL_OVRD - APLL Override Register */ +/*! @{ */ + +#define SCG_APLL_OVRD_APLLPWREN_OVRD_MASK (0x1U) +#define SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT (0U) +/*! APLLPWREN_OVRD - APLL Power Enable Override if APLL_OVRD_EN=1 + * 0b0..APLL clock is powered off + * 0b1..APLL clock is powered on + */ +#define SCG_APLL_OVRD_APLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLPWREN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLPWREN_OVRD_MASK) + +#define SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK (0x2U) +#define SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT (1U) +/*! APLLCLKEN_OVRD - APLL Clock Enable Override if APLL_OVRD_EN=1 + * 0b0..APLL clock is disabled + * 0b1..APLL clock is enabled + */ +#define SCG_APLL_OVRD_APLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLLCLKEN_OVRD_SHIFT)) & SCG_APLL_OVRD_APLLCLKEN_OVRD_MASK) + +#define SCG_APLL_OVRD_APLL_OVRD_EN_MASK (0x80000000U) +#define SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT (31U) +/*! APLL_OVRD_EN - APLL Override Enable + * 0b0..APLL override is disabled + * 0b1..APLL override is enabled + */ +#define SCG_APLL_OVRD_APLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_APLL_OVRD_APLL_OVRD_EN_SHIFT)) & SCG_APLL_OVRD_APLL_OVRD_EN_MASK) +/*! @} */ + +/*! @name SPLLCSR - SPLL Control Status Register */ +/*! @{ */ + +#define SCG_SPLLCSR_SPLLPWREN_MASK (0x1U) +#define SCG_SPLLCSR_SPLLPWREN_SHIFT (0U) +/*! SPLLPWREN - SPLL Power Enable + * 0b0..SPLL clock is powered off + * 0b1..SPLL clock is powered on + */ +#define SCG_SPLLCSR_SPLLPWREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLPWREN_SHIFT)) & SCG_SPLLCSR_SPLLPWREN_MASK) + +#define SCG_SPLLCSR_SPLLCLKEN_MASK (0x2U) +#define SCG_SPLLCSR_SPLLCLKEN_SHIFT (1U) +/*! SPLLCLKEN - SPLL Clock Enable + * 0b0..SPLL clock is disabled + * 0b1..SPLL clock is enabled + */ +#define SCG_SPLLCSR_SPLLCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCLKEN_SHIFT)) & SCG_SPLLCSR_SPLLCLKEN_MASK) + +#define SCG_SPLLCSR_SPLLSTEN_MASK (0x4U) +#define SCG_SPLLCSR_SPLLSTEN_SHIFT (2U) +/*! SPLLSTEN - SPLL Stop Enable + * 0b0..SPLL is disabled in Deep Sleep mode + * 0b1..SPLL is enabled in Deep Sleep mode + */ +#define SCG_SPLLCSR_SPLLSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSTEN_SHIFT)) & SCG_SPLLCSR_SPLLSTEN_MASK) + +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK (0x8U) +#define SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT (3U) +/*! FRM_CLOCKSTABLE - Free running mode clock stable + * 0b0..Free running mode clockstable is disabled + * 0b1..Free running mode clockstable is enabled + */ +#define SCG_SPLLCSR_FRM_CLOCKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_FRM_CLOCKSTABLE_SHIFT)) & SCG_SPLLCSR_FRM_CLOCKSTABLE_MASK) + +#define SCG_SPLLCSR_SPLLCM_MASK (0x10000U) +#define SCG_SPLLCSR_SPLLCM_SHIFT (16U) +/*! SPLLCM - SPLL Clock Monitor + * 0b0..SPLL Clock Monitor is disabled + * 0b1..SPLL Clock Monitor is enabled + */ +#define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCM_SHIFT)) & SCG_SPLLCSR_SPLLCM_MASK) + +#define SCG_SPLLCSR_SPLLCMRE_MASK (0x20000U) +#define SCG_SPLLCSR_SPLLCMRE_SHIFT (17U) +/*! SPLLCMRE - SPLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLCMRE_SHIFT)) & SCG_SPLLCSR_SPLLCMRE_MASK) + +#define SCG_SPLLCSR_LK_MASK (0x800000U) +#define SCG_SPLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_LK_SHIFT)) & SCG_SPLLCSR_LK_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_MASK (0x1000000U) +#define SCG_SPLLCSR_SPLL_LOCK_SHIFT (24U) +/*! SPLL_LOCK - SPLL LOCK + * 0b0..SPLL is not powered on or not locked + * 0b1..SPLL is locked + */ +#define SCG_SPLLCSR_SPLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_MASK) + +#define SCG_SPLLCSR_SPLLSEL_MASK (0x2000000U) +#define SCG_SPLLCSR_SPLLSEL_SHIFT (25U) +/*! SPLLSEL - SPLL Selected + * 0b0..SPLL is not the system clock source + * 0b1..SPLL is the system clock source + */ +#define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLSEL_SHIFT)) & SCG_SPLLCSR_SPLLSEL_MASK) + +#define SCG_SPLLCSR_SPLLERR_MASK (0x4000000U) +#define SCG_SPLLCSR_SPLLERR_SHIFT (26U) +/*! SPLLERR - SPLL Clock Error + * 0b0..SPLL Clock Monitor is disabled or has not detected an error + * 0b1..SPLL Clock Monitor is enabled and detected an error + */ +#define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLLERR_SHIFT)) & SCG_SPLLCSR_SPLLERR_MASK) + +#define SCG_SPLLCSR_SPLL_LOCK_IE_MASK (0x40000000U) +#define SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT (30U) +/*! SPLL_LOCK_IE - SPLL LOCK Interrupt Enable + * 0b0..SPLL_LOCK interrupt is not enabled + * 0b1..SPLL_LOCK interrupt is enabled + */ +#define SCG_SPLLCSR_SPLL_LOCK_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCSR_SPLL_LOCK_IE_SHIFT)) & SCG_SPLLCSR_SPLL_LOCK_IE_MASK) +/*! @} */ + +/*! @name SPLLCTRL - SPLL Control Register */ +/*! @{ */ + +#define SCG_SPLLCTRL_SELR_MASK (0xFU) +#define SCG_SPLLCTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R (resistor) value. */ +#define SCG_SPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELR_SHIFT)) & SCG_SPLLCTRL_SELR_MASK) + +#define SCG_SPLLCTRL_SELI_MASK (0x3F0U) +#define SCG_SPLLCTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I (integration) value. */ +#define SCG_SPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELI_SHIFT)) & SCG_SPLLCTRL_SELI_MASK) + +#define SCG_SPLLCTRL_SELP_MASK (0x7C00U) +#define SCG_SPLLCTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P (proportional) value. */ +#define SCG_SPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SELP_SHIFT)) & SCG_SPLLCTRL_SELP_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK (0x10000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT (16U) +/*! BYPASSPOSTDIV2 - Bypass of Divide-by-2 Divider + * 0b0..Use the divide-by-2 divider in the postdivider. + * 0b1..Bypass of the divide-by-2 divider in the postdivider + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV2_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) + +#define SCG_SPLLCTRL_LIMUPOFF_MASK (0x20000U) +#define SCG_SPLLCTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - Up Limiter. + * 0b0..Application set to non-Spectrum and Fractional applications. + * 0b1..Application set to Spectrum and Fractional applications. + */ +#define SCG_SPLLCTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_LIMUPOFF_SHIFT)) & SCG_SPLLCTRL_LIMUPOFF_MASK) + +#define SCG_SPLLCTRL_BANDDIRECT_MASK (0x40000U) +#define SCG_SPLLCTRL_BANDDIRECT_SHIFT (18U) +/*! BANDDIRECT - Control of the bandwidth of the PLL. + * 0b0..The bandwidth is changed synchronously with the feedback-divider + * 0b1..Modifies the bandwidth of the PLL directly + */ +#define SCG_SPLLCTRL_BANDDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BANDDIRECT_SHIFT)) & SCG_SPLLCTRL_BANDDIRECT_MASK) + +#define SCG_SPLLCTRL_BYPASSPREDIV_MASK (0x80000U) +#define SCG_SPLLCTRL_BYPASSPREDIV_SHIFT (19U) +/*! BYPASSPREDIV - Bypass of the predivider. + * 0b0..Use the predivider + * 0b1..Bypass of the predivider + */ +#define SCG_SPLLCTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPREDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPREDIV_MASK) + +#define SCG_SPLLCTRL_BYPASSPOSTDIV_MASK (0x100000U) +#define SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT (20U) +/*! BYPASSPOSTDIV - Bypass of the postdivider. + * 0b0..Use the postdivider + * 0b1..Bypass of the postdivider + */ +#define SCG_SPLLCTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_BYPASSPOSTDIV_SHIFT)) & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) + +#define SCG_SPLLCTRL_FRM_MASK (0x400000U) +#define SCG_SPLLCTRL_FRM_SHIFT (22U) +/*! FRM - Free Running Mode Enable + * 0b0..Free running mode disabled + * 0b1..Free running mode enabled + */ +#define SCG_SPLLCTRL_FRM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_FRM_SHIFT)) & SCG_SPLLCTRL_FRM_MASK) + +#define SCG_SPLLCTRL_SOURCE_MASK (0x6000000U) +#define SCG_SPLLCTRL_SOURCE_SHIFT (25U) +/*! SOURCE - Clock Source + * 0b00..SOSC + * 0b01..FIRC 48 MHz clock. FIRC_SCLK_PERIPH_EN must be set to use FIRC 48 MHz clock. + * 0b10..ROSC + * 0b11..No clock + */ +#define SCG_SPLLCTRL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLCTRL_SOURCE_SHIFT)) & SCG_SPLLCTRL_SOURCE_MASK) +/*! @} */ + +/*! @name SPLLSTAT - SPLL Status Register */ +/*! @{ */ + +#define SCG_SPLLSTAT_NDIVACK_MASK (0x2U) +#define SCG_SPLLSTAT_NDIVACK_SHIFT (1U) +/*! NDIVACK - Predivider (N) ratio change acknowledge + * 0b0..The predivider (N) ratio change is not accepted by the analog PLL. + * 0b1..The predivider (N) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_NDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_NDIVACK_SHIFT)) & SCG_SPLLSTAT_NDIVACK_MASK) + +#define SCG_SPLLSTAT_MDIVACK_MASK (0x4U) +#define SCG_SPLLSTAT_MDIVACK_SHIFT (2U) +/*! MDIVACK - Feedback (M) divider ratio change acknowledge + * 0b0..The feedback (M) ratio change is not accepted by the analog PLL. + * 0b1..The feedback (M) ratio change is accepted by the analog PLL. + */ +#define SCG_SPLLSTAT_MDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_MDIVACK_SHIFT)) & SCG_SPLLSTAT_MDIVACK_MASK) + +#define SCG_SPLLSTAT_PDIVACK_MASK (0x8U) +#define SCG_SPLLSTAT_PDIVACK_SHIFT (3U) +/*! PDIVACK - Postdivider (P) ratio change acknowledge + * 0b0..The postdivider (P) ratio change is not accepted by the analog PLL + * 0b1..The postdivider (P) ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSTAT_PDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_PDIVACK_SHIFT)) & SCG_SPLLSTAT_PDIVACK_MASK) + +#define SCG_SPLLSTAT_FRMDET_MASK (0x10U) +#define SCG_SPLLSTAT_FRMDET_SHIFT (4U) +/*! FRMDET - Free running detector (active high) + * 0b0..Free running is not detected + * 0b1..Free running is detected + */ +#define SCG_SPLLSTAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSTAT_FRMDET_SHIFT)) & SCG_SPLLSTAT_FRMDET_MASK) +/*! @} */ + +/*! @name SPLLNDIV - SPLL N Divider Register */ +/*! @{ */ + +#define SCG_SPLLNDIV_NDIV_MASK (0xFFU) +#define SCG_SPLLNDIV_NDIV_SHIFT (0U) +/*! NDIV - Predivider divider ratio (N-divider). */ +#define SCG_SPLLNDIV_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NDIV_SHIFT)) & SCG_SPLLNDIV_NDIV_MASK) + +#define SCG_SPLLNDIV_NREQ_MASK (0x80000000U) +#define SCG_SPLLNDIV_NREQ_SHIFT (31U) +/*! NREQ - Predivider ratio change request. + * 0b0..Predivider ratio change is not requested + * 0b1..Predivider ratio change is requested + */ +#define SCG_SPLLNDIV_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLNDIV_NREQ_SHIFT)) & SCG_SPLLNDIV_NREQ_MASK) +/*! @} */ + +/*! @name SPLLMDIV - SPLL M Divider Register */ +/*! @{ */ + +#define SCG_SPLLMDIV_MDIV_MASK (0xFFFFU) +#define SCG_SPLLMDIV_MDIV_SHIFT (0U) +/*! MDIV - Feedback divider divider ratio (M-divider). */ +#define SCG_SPLLMDIV_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MDIV_SHIFT)) & SCG_SPLLMDIV_MDIV_MASK) + +#define SCG_SPLLMDIV_MREQ_MASK (0x80000000U) +#define SCG_SPLLMDIV_MREQ_SHIFT (31U) +/*! MREQ - Feedback ratio change request. + * 0b0..Feedback ratio change is not requested + * 0b1..Feedback ratio change is requested + */ +#define SCG_SPLLMDIV_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLMDIV_MREQ_SHIFT)) & SCG_SPLLMDIV_MREQ_MASK) +/*! @} */ + +/*! @name SPLLPDIV - SPLL P Divider Register */ +/*! @{ */ + +#define SCG_SPLLPDIV_PDIV_MASK (0x1FU) +#define SCG_SPLLPDIV_PDIV_SHIFT (0U) +/*! PDIV - Postdivider divider ratio (P-divider) */ +#define SCG_SPLLPDIV_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PDIV_SHIFT)) & SCG_SPLLPDIV_PDIV_MASK) + +#define SCG_SPLLPDIV_PREQ_MASK (0x80000000U) +#define SCG_SPLLPDIV_PREQ_SHIFT (31U) +/*! PREQ - Postdivider ratio change request + * 0b0..Postdivider ratio change is not requested + * 0b1..Postdivider ratio change is requested + */ +#define SCG_SPLLPDIV_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLPDIV_PREQ_SHIFT)) & SCG_SPLLPDIV_PREQ_MASK) +/*! @} */ + +/*! @name SPLLLOCK_CNFG - SPLL LOCK Configuration Register */ +/*! @{ */ + +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK (0x1FFFFU) +#define SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT (0U) +/*! LOCK_TIME - Configures the number of reference clocks to count before SPLL is considered locked. */ +#define SCG_SPLLLOCK_CNFG_LOCK_TIME(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLLOCK_CNFG_LOCK_TIME_SHIFT)) & SCG_SPLLLOCK_CNFG_LOCK_TIME_MASK) +/*! @} */ + +/*! @name SPLLSSCGSTAT - SPLL SSCG Status Register */ +/*! @{ */ + +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK (0x1U) +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT (0U) +/*! SS_MDIV_ACK - SS_MDIV change acknowledge + * 0b0..The SS_MDIV, MF, MR, and MC ratio change is not accepted by the analog PLL + * 0b1..The SS_MDIV, MF, MR, and MC ratio change is accepted by the analog PLL + */ +#define SCG_SPLLSSCGSTAT_SS_MDIV_ACK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCGSTAT_SS_MDIV_ACK_SHIFT)) & SCG_SPLLSSCGSTAT_SS_MDIV_ACK_MASK) +/*! @} */ + +/*! @name SPLLSSCG0 - SPLL Spread Spectrum Control 0 Register */ +/*! @{ */ + +#define SCG_SPLLSSCG0_SS_MDIV_LSB_MASK (0xFFFFFFFFU) +#define SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT (0U) +/*! SS_MDIV_LSB - SS_MDIV[31:0] */ +#define SCG_SPLLSSCG0_SS_MDIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG0_SS_MDIV_LSB_SHIFT)) & SCG_SPLLSSCG0_SS_MDIV_LSB_MASK) +/*! @} */ + +/*! @name SPLLSSCG1 - SPLL Spread Spectrum Control 1 Register */ +/*! @{ */ + +#define SCG_SPLLSSCG1_SS_MDIV_MSB_MASK (0x1U) +#define SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT (0U) +/*! SS_MDIV_MSB - SS_MDIV[32] */ +#define SCG_SPLLSSCG1_SS_MDIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_MSB_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) + +#define SCG_SPLLSSCG1_SS_MDIV_REQ_MASK (0x2U) +#define SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT (1U) +/*! SS_MDIV_REQ - SS_MDIV[32:0] change request. + * 0b0..SS_MDIV change is not requested + * 0b1..SS_MDIV change is requested + */ +#define SCG_SPLLSSCG1_SS_MDIV_REQ(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_MDIV_REQ_SHIFT)) & SCG_SPLLSSCG1_SS_MDIV_REQ_MASK) + +#define SCG_SPLLSSCG1_MF_MASK (0x1CU) +#define SCG_SPLLSSCG1_MF_SHIFT (2U) +/*! MF - Modulation Frequency Control */ +#define SCG_SPLLSSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MF_SHIFT)) & SCG_SPLLSSCG1_MF_MASK) + +#define SCG_SPLLSSCG1_MR_MASK (0xE0U) +#define SCG_SPLLSSCG1_MR_SHIFT (5U) +/*! MR - Modulation Depth Control */ +#define SCG_SPLLSSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MR_SHIFT)) & SCG_SPLLSSCG1_MR_MASK) + +#define SCG_SPLLSSCG1_MC_MASK (0x300U) +#define SCG_SPLLSSCG1_MC_SHIFT (8U) +/*! MC - Modulation Waveform Control + * 0b00..MC[1:0] no compensation + * 0b11..MC[1:0] maximum compensation + */ +#define SCG_SPLLSSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_MC_SHIFT)) & SCG_SPLLSSCG1_MC_MASK) + +#define SCG_SPLLSSCG1_DITHER_MASK (0x400U) +#define SCG_SPLLSSCG1_DITHER_SHIFT (10U) +/*! DITHER - Dither Enable + * 0b0..Dither is not enabled + * 0b1..Dither is enabled + */ +#define SCG_SPLLSSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_DITHER_SHIFT)) & SCG_SPLLSSCG1_DITHER_MASK) + +#define SCG_SPLLSSCG1_SEL_SS_MDIV_MASK (0x800U) +#define SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT (11U) +/*! SEL_SS_MDIV - SS_MDIV select. + * 0b0..Feedback divider ratio is MDIV[15:0] + * 0b1..Feedback divider ratio is SS_MDIV[32:0] + */ +#define SCG_SPLLSSCG1_SEL_SS_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SEL_SS_MDIV_SHIFT)) & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) + +#define SCG_SPLLSSCG1_SS_PD_MASK (0x80000000U) +#define SCG_SPLLSSCG1_SS_PD_SHIFT (31U) +/*! SS_PD - SSCG Power Down + * 0b0..SSCG is powered on + * 0b1..SSCG is powered off + */ +#define SCG_SPLLSSCG1_SS_PD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLLSSCG1_SS_PD_SHIFT)) & SCG_SPLLSSCG1_SS_PD_MASK) +/*! @} */ + +/*! @name SPLL_OVRD - SPLL Override Register */ +/*! @{ */ + +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK (0x1U) +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT (0U) +/*! SPLLPWREN_OVRD - SPLL Power Enable Override if SPLL_OVRD_EN=1 + * 0b0..SPLL clock is powered off + * 0b1..SPLL clock is powered on + */ +#define SCG_SPLL_OVRD_SPLLPWREN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLPWREN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLPWREN_OVRD_MASK) + +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK (0x2U) +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT (1U) +/*! SPLLCLKEN_OVRD - SPLL Clock Enable Override if SPLL_OVRD_EN=1 + * 0b0..SPLL clock is disabled + * 0b1..SPLL clock is enabled + */ +#define SCG_SPLL_OVRD_SPLLCLKEN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLLCLKEN_OVRD_SHIFT)) & SCG_SPLL_OVRD_SPLLCLKEN_OVRD_MASK) + +#define SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK (0x80000000U) +#define SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT (31U) +/*! SPLL_OVRD_EN - SPLL Override Enable + * 0b0..SPLL override is disabled + * 0b1..SPLL override is enabled + */ +#define SCG_SPLL_OVRD_SPLL_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SPLL_OVRD_SPLL_OVRD_EN_SHIFT)) & SCG_SPLL_OVRD_SPLL_OVRD_EN_MASK) +/*! @} */ + +/*! @name UPLLCSR - UPLL Control Status Register */ +/*! @{ */ + +#define SCG_UPLLCSR_UPLLCM_MASK (0x10000U) +#define SCG_UPLLCSR_UPLLCM_SHIFT (16U) +/*! UPLLCM - UPLL Clock Monitor + * 0b0..UPLL Clock Monitor is disabled + * 0b1..UPLL Clock Monitor is enabled + */ +#define SCG_UPLLCSR_UPLLCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCM_SHIFT)) & SCG_UPLLCSR_UPLLCM_MASK) + +#define SCG_UPLLCSR_UPLLCMRE_MASK (0x20000U) +#define SCG_UPLLCSR_UPLLCMRE_SHIFT (17U) +/*! UPLLCMRE - UPLL Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_UPLLCSR_UPLLCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLCMRE_SHIFT)) & SCG_UPLLCSR_UPLLCMRE_MASK) + +#define SCG_UPLLCSR_LK_MASK (0x800000U) +#define SCG_UPLLCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_UPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_LK_SHIFT)) & SCG_UPLLCSR_LK_MASK) + +#define SCG_UPLLCSR_UPLLVLD_MASK (0x1000000U) +#define SCG_UPLLCSR_UPLLVLD_SHIFT (24U) +/*! UPLLVLD - UPLL Valid + * 0b0..UPLL is not enabled or clock is not valid + * 0b1..UPLL is enabled and output clock is valid + */ +#define SCG_UPLLCSR_UPLLVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVLD_SHIFT)) & SCG_UPLLCSR_UPLLVLD_MASK) + +#define SCG_UPLLCSR_UPLLSEL_MASK (0x2000000U) +#define SCG_UPLLCSR_UPLLSEL_SHIFT (25U) +/*! UPLLSEL - UPLL Selected + * 0b0..UPLL is not the system clock source + * 0b1..UPLL is the system clock source + */ +#define SCG_UPLLCSR_UPLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLSEL_SHIFT)) & SCG_UPLLCSR_UPLLSEL_MASK) + +#define SCG_UPLLCSR_UPLLERR_MASK (0x4000000U) +#define SCG_UPLLCSR_UPLLERR_SHIFT (26U) +/*! UPLLERR - UPLL Clock Error + * 0b0..UPLL Clock Monitor is disabled or has not detected an error + * 0b1..UPLL Clock Monitor is enabled and detected an error + */ +#define SCG_UPLLCSR_UPLLERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLERR_SHIFT)) & SCG_UPLLCSR_UPLLERR_MASK) + +#define SCG_UPLLCSR_UPLLVOR_MASK (0x40000000U) +#define SCG_UPLLCSR_UPLLVOR_SHIFT (30U) +/*! UPLLVOR - USB PLL Valid Flag Override Value + * 0b0..Override to 0b + * 0b1..Override to 1b + */ +#define SCG_UPLLCSR_UPLLVOR(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVOR_SHIFT)) & SCG_UPLLCSR_UPLLVOR_MASK) + +#define SCG_UPLLCSR_UPLLVORE_MASK (0x80000000U) +#define SCG_UPLLCSR_UPLLVORE_SHIFT (31U) +/*! UPLLVORE - USB PLL Valid Flag Override Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SCG_UPLLCSR_UPLLVORE(x) (((uint32_t)(((uint32_t)(x)) << SCG_UPLLCSR_UPLLVORE_SHIFT)) & SCG_UPLLCSR_UPLLVORE_MASK) +/*! @} */ + +/*! @name LDOCSR - LDO Control and Status Register */ +/*! @{ */ + +#define SCG_LDOCSR_LDOEN_MASK (0x1U) +#define SCG_LDOCSR_LDOEN_SHIFT (0U) +/*! LDOEN - LDO Enable + * 0b0..LDO is disabled + * 0b1..LDO is enabled + */ +#define SCG_LDOCSR_LDOEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOEN_SHIFT)) & SCG_LDOCSR_LDOEN_MASK) + +#define SCG_LDOCSR_VOUT_SEL_MASK (0xEU) +#define SCG_LDOCSR_VOUT_SEL_SHIFT (1U) +/*! VOUT_SEL - LDO output voltage select + * 0b000..VOUT = 1V + * 0b001..VOUT = 1V + * 0b010..VOUT = 1V + * 0b011..VOUT = 1.05V + * 0b100..VOUT = 1.1V + * 0b101..VOUT = 1.15V + * 0b110..VOUT = 1.2V + * 0b111..VOUT = 1.25V + */ +#define SCG_LDOCSR_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_SEL_SHIFT)) & SCG_LDOCSR_VOUT_SEL_MASK) + +#define SCG_LDOCSR_LDOBYPASS_MASK (0x10U) +#define SCG_LDOCSR_LDOBYPASS_SHIFT (4U) +/*! LDOBYPASS - LDO Bypass + * 0b0..LDO is not bypassed + * 0b1..LDO is bypassed + */ +#define SCG_LDOCSR_LDOBYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_LDOBYPASS_SHIFT)) & SCG_LDOCSR_LDOBYPASS_MASK) + +#define SCG_LDOCSR_VOUT_OK_MASK (0x80000000U) +#define SCG_LDOCSR_VOUT_OK_SHIFT (31U) +/*! VOUT_OK - LDO VOUT OK Inform. + * 0b0..LDO output VOUT is not OK + * 0b1..LDO output VOUT is OK + */ +#define SCG_LDOCSR_VOUT_OK(x) (((uint32_t)(((uint32_t)(x)) << SCG_LDOCSR_VOUT_OK_SHIFT)) & SCG_LDOCSR_VOUT_OK_MASK) +/*! @} */ + +/*! @name TROCSR - TRO Control Status Register */ +/*! @{ */ + +#define SCG_TROCSR_TROCM_MASK (0x10000U) +#define SCG_TROCSR_TROCM_SHIFT (16U) +/*! TROCM - TRO Clock Monitor + * 0b0..TRO Clock Monitor is disabled + * 0b1..TRO Clock Monitor is enabled + */ +#define SCG_TROCSR_TROCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCM_SHIFT)) & SCG_TROCSR_TROCM_MASK) + +#define SCG_TROCSR_TROCMRE_MASK (0x20000U) +#define SCG_TROCSR_TROCMRE_SHIFT (17U) +/*! TROCMRE - TRO Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_TROCSR_TROCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROCMRE_SHIFT)) & SCG_TROCSR_TROCMRE_MASK) + +#define SCG_TROCSR_TRO_REFCLK_SEL_MASK (0xC0000U) +#define SCG_TROCSR_TRO_REFCLK_SEL_SHIFT (18U) +/*! TRO_REFCLK_SEL - TRO reference clock selection + * 0b00..SOSC + * 0b01..SIRC + * 0b10..FIRC (144 MHz or 48 MHz, based on RANGE selection) + * 0b11..Reserved + */ +#define SCG_TROCSR_TRO_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TRO_REFCLK_SEL_SHIFT)) & SCG_TROCSR_TRO_REFCLK_SEL_MASK) + +#define SCG_TROCSR_LK_MASK (0x800000U) +#define SCG_TROCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_TROCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_LK_SHIFT)) & SCG_TROCSR_LK_MASK) + +#define SCG_TROCSR_TROVLD_MASK (0x1000000U) +#define SCG_TROCSR_TROVLD_SHIFT (24U) +/*! TROVLD - TRO Valid + * 0b0..TRO is not enabled or clock is not valid + * 0b1..TRO is enabled and output clock is valid + */ +#define SCG_TROCSR_TROVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROVLD_SHIFT)) & SCG_TROCSR_TROVLD_MASK) + +#define SCG_TROCSR_TROSEL_MASK (0x2000000U) +#define SCG_TROCSR_TROSEL_SHIFT (25U) +/*! TROSEL - TRO Selected + * 0b0..TRO is not the system clock source + * 0b1..TRO is the system clock source + */ +#define SCG_TROCSR_TROSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROSEL_SHIFT)) & SCG_TROCSR_TROSEL_MASK) + +#define SCG_TROCSR_TROERR_MASK (0x4000000U) +#define SCG_TROCSR_TROERR_SHIFT (26U) +/*! TROERR - TRO Clock Error + * 0b0..TRO clock monitor is disabled or has not detected an error + * 0b1..TRO clock monitor is enabled and detected an error + */ +#define SCG_TROCSR_TROERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_TROCSR_TROERR_SHIFT)) & SCG_TROCSR_TROERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SCG_Register_Masks */ + + +/* SCG - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x50044000u) + /** Peripheral SCG0 base address */ + #define SCG0_BASE_NS (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Peripheral SCG0 base pointer */ + #define SCG0_NS ((SCG_Type *)SCG0_BASE_NS) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS_NS { SCG0_BASE_NS } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS_NS { SCG0_NS } +#else + /** Peripheral SCG0 base address */ + #define SCG0_BASE (0x40044000u) + /** Peripheral SCG0 base pointer */ + #define SCG0 ((SCG_Type *)SCG0_BASE) + /** Array initializer of SCG peripheral base addresses */ + #define SCG_BASE_ADDRS { SCG0_BASE } + /** Array initializer of SCG peripheral base pointers */ + #define SCG_BASE_PTRS { SCG0 } +#endif + +/*! + * @} + */ /* end of group SCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Peripheral_Access_Layer SMARTDMA Peripheral Access Layer + * @{ + */ + +/** SMARTDMA - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /**< Boot Address, offset: 0x20 */ + __IO uint32_t CTRL; /**< Control, offset: 0x24 */ + __I uint32_t PC; /**< Program Counter, offset: 0x28 */ + __I uint32_t SP; /**< Stack Pointer, offset: 0x2C */ + __IO uint32_t BREAK_ADDR; /**< Breakpoint Address, offset: 0x30 */ + __IO uint32_t BREAK_VECT; /**< Breakpoint Vector, offset: 0x34 */ + __IO uint32_t EMER_VECT; /**< Emergency Vector, offset: 0x38 */ + __IO uint32_t EMER_SEL; /**< Emergency Select, offset: 0x3C */ + __IO uint32_t ARM2EZH; /**< ARM to EZH Interrupt Control, offset: 0x40 */ + __IO uint32_t EZH2ARM; /**< EZH to ARM Trigger, offset: 0x44 */ + __IO uint32_t PENDTRAP; /**< Pending Trap Control, offset: 0x48 */ +} SMARTDMA_Type; + +/* ---------------------------------------------------------------------------- + -- SMARTDMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SMARTDMA_Register_Masks SMARTDMA Register Masks + * @{ + */ + +/*! @name BOOTADR - Boot Address */ +/*! @{ */ + +#define SMARTDMA_BOOTADR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BOOTADR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit boot address, the boot address should be 4-byte aligned. */ +#define SMARTDMA_BOOTADR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BOOTADR_ADDR_SHIFT)) & SMARTDMA_BOOTADR_ADDR_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define SMARTDMA_CTRL_START_MASK (0x1U) +#define SMARTDMA_CTRL_START_SHIFT (0U) +/*! START - Start Bit Ignition */ +#define SMARTDMA_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_START_SHIFT)) & SMARTDMA_CTRL_START_MASK) + +#define SMARTDMA_CTRL_EXF_MASK (0x2U) +#define SMARTDMA_CTRL_EXF_SHIFT (1U) +/*! EXF - External Flag */ +#define SMARTDMA_CTRL_EXF(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_EXF_SHIFT)) & SMARTDMA_CTRL_EXF_MASK) + +#define SMARTDMA_CTRL_ERRDIS_MASK (0x4U) +#define SMARTDMA_CTRL_ERRDIS_SHIFT (2U) +/*! ERRDIS - Error Disable */ +#define SMARTDMA_CTRL_ERRDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_ERRDIS_SHIFT)) & SMARTDMA_CTRL_ERRDIS_MASK) + +#define SMARTDMA_CTRL_BUFEN_MASK (0x8U) +#define SMARTDMA_CTRL_BUFEN_SHIFT (3U) +/*! BUFEN - Buffer Enable */ +#define SMARTDMA_CTRL_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_BUFEN_SHIFT)) & SMARTDMA_CTRL_BUFEN_MASK) + +#define SMARTDMA_CTRL_SYNCEN_MASK (0x10U) +#define SMARTDMA_CTRL_SYNCEN_SHIFT (4U) +/*! SYNCEN - Sync Enable */ +#define SMARTDMA_CTRL_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_SYNCEN_SHIFT)) & SMARTDMA_CTRL_SYNCEN_MASK) + +#define SMARTDMA_CTRL_WKEY_MASK (0xFFFF0000U) +#define SMARTDMA_CTRL_WKEY_SHIFT (16U) +/*! WKEY - Write Key */ +#define SMARTDMA_CTRL_WKEY(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_CTRL_WKEY_SHIFT)) & SMARTDMA_CTRL_WKEY_MASK) +/*! @} */ + +/*! @name PC - Program Counter */ +/*! @{ */ + +#define SMARTDMA_PC_PC_MASK (0xFFFFFFFFU) +#define SMARTDMA_PC_PC_SHIFT (0U) +/*! PC - Program Counter */ +#define SMARTDMA_PC_PC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PC_PC_SHIFT)) & SMARTDMA_PC_PC_MASK) +/*! @} */ + +/*! @name SP - Stack Pointer */ +/*! @{ */ + +#define SMARTDMA_SP_SP_MASK (0xFFFFFFFFU) +#define SMARTDMA_SP_SP_SHIFT (0U) +/*! SP - Stack Pointer */ +#define SMARTDMA_SP_SP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_SP_SP_SHIFT)) & SMARTDMA_SP_SP_MASK) +/*! @} */ + +/*! @name BREAK_ADDR - Breakpoint Address */ +/*! @{ */ + +#define SMARTDMA_BREAK_ADDR_ADDR_MASK (0xFFFFFFFCU) +#define SMARTDMA_BREAK_ADDR_ADDR_SHIFT (2U) +/*! ADDR - 32-bit address to swap to EZHB_BREAK_VECT location */ +#define SMARTDMA_BREAK_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_ADDR_ADDR_SHIFT)) & SMARTDMA_BREAK_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name BREAK_VECT - Breakpoint Vector */ +/*! @{ */ + +#define SMARTDMA_BREAK_VECT_VEC_MASK (0xFFFFFFFCU) +#define SMARTDMA_BREAK_VECT_VEC_SHIFT (2U) +/*! VEC - Vector address of user debug routine. */ +#define SMARTDMA_BREAK_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_BREAK_VECT_VEC_SHIFT)) & SMARTDMA_BREAK_VECT_VEC_MASK) +/*! @} */ + +/*! @name EMER_VECT - Emergency Vector */ +/*! @{ */ + +#define SMARTDMA_EMER_VECT_VEC_MASK (0xFFFFFFFCU) +#define SMARTDMA_EMER_VECT_VEC_SHIFT (2U) +/*! VEC - Vector address of emergency code routine */ +#define SMARTDMA_EMER_VECT_VEC(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_VECT_VEC_SHIFT)) & SMARTDMA_EMER_VECT_VEC_MASK) +/*! @} */ + +/*! @name EMER_SEL - Emergency Select */ +/*! @{ */ + +#define SMARTDMA_EMER_SEL_EN_MASK (0x100U) +#define SMARTDMA_EMER_SEL_EN_SHIFT (8U) +/*! EN - Emergency code routine */ +#define SMARTDMA_EMER_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_EN_SHIFT)) & SMARTDMA_EMER_SEL_EN_MASK) + +#define SMARTDMA_EMER_SEL_RQ_MASK (0x200U) +#define SMARTDMA_EMER_SEL_RQ_SHIFT (9U) +/*! RQ - Software emergency request */ +#define SMARTDMA_EMER_SEL_RQ(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EMER_SEL_RQ_SHIFT)) & SMARTDMA_EMER_SEL_RQ_MASK) +/*! @} */ + +/*! @name ARM2EZH - ARM to EZH Interrupt Control */ +/*! @{ */ + +#define SMARTDMA_ARM2EZH_IE_MASK (0x3U) +#define SMARTDMA_ARM2EZH_IE_SHIFT (0U) +/*! IE - Interrupt Enable */ +#define SMARTDMA_ARM2EZH_IE(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_IE_SHIFT)) & SMARTDMA_ARM2EZH_IE_MASK) + +#define SMARTDMA_ARM2EZH_GP_MASK (0xFFFFFFFCU) +#define SMARTDMA_ARM2EZH_GP_SHIFT (2U) +/*! GP - General purpose register bits */ +#define SMARTDMA_ARM2EZH_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_ARM2EZH_GP_SHIFT)) & SMARTDMA_ARM2EZH_GP_MASK) +/*! @} */ + +/*! @name EZH2ARM - EZH to ARM Trigger */ +/*! @{ */ + +#define SMARTDMA_EZH2ARM_GP_MASK (0xFFFFFFFFU) +#define SMARTDMA_EZH2ARM_GP_SHIFT (0U) +/*! GP - General purpose register bits Writing to EZH2ARM triggers the ARM interrupt when ARM2EZH [1:0] == 2h */ +#define SMARTDMA_EZH2ARM_GP(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_EZH2ARM_GP_SHIFT)) & SMARTDMA_EZH2ARM_GP_MASK) +/*! @} */ + +/*! @name PENDTRAP - Pending Trap Control */ +/*! @{ */ + +#define SMARTDMA_PENDTRAP_STATUS_MASK (0xFFU) +#define SMARTDMA_PENDTRAP_STATUS_SHIFT (0U) +/*! STATUS - Status Flag or Pending Trap Request */ +#define SMARTDMA_PENDTRAP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_STATUS_SHIFT)) & SMARTDMA_PENDTRAP_STATUS_MASK) + +#define SMARTDMA_PENDTRAP_POL_MASK (0xFF00U) +#define SMARTDMA_PENDTRAP_POL_SHIFT (8U) +/*! POL - Polarity */ +#define SMARTDMA_PENDTRAP_POL(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_POL_SHIFT)) & SMARTDMA_PENDTRAP_POL_MASK) + +#define SMARTDMA_PENDTRAP_EN_MASK (0xFF0000U) +#define SMARTDMA_PENDTRAP_EN_SHIFT (16U) +/*! EN - Enable Pending Trap */ +#define SMARTDMA_PENDTRAP_EN(x) (((uint32_t)(((uint32_t)(x)) << SMARTDMA_PENDTRAP_EN_SHIFT)) & SMARTDMA_PENDTRAP_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SMARTDMA_Register_Masks */ + + +/* SMARTDMA - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x50033000u) + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE_NS (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0_NS ((SMARTDMA_Type *)SMARTDMA0_BASE_NS) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS_NS { SMARTDMA0_BASE_NS } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS_NS { SMARTDMA0_NS } +#else + /** Peripheral SMARTDMA0 base address */ + #define SMARTDMA0_BASE (0x40033000u) + /** Peripheral SMARTDMA0 base pointer */ + #define SMARTDMA0 ((SMARTDMA_Type *)SMARTDMA0_BASE) + /** Array initializer of SMARTDMA peripheral base addresses */ + #define SMARTDMA_BASE_ADDRS { SMARTDMA0_BASE } + /** Array initializer of SMARTDMA peripheral base pointers */ + #define SMARTDMA_BASE_PTRS { SMARTDMA0 } +#endif + +/*! + * @} + */ /* end of group SMARTDMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer + * @{ + */ + +/** SPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SC; /**< Status Control, offset: 0x10 */ + __IO uint32_t CNTRL; /**< SPC Regulator Control, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PD_STATUS[2]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */ + uint8_t RESERVED_4[188]; + __IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */ + __IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */ + __IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */ + __IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */ + uint8_t RESERVED_5[16]; + __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */ + __IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */ + uint8_t RESERVED_6[8]; + __IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */ + __IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */ + __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ + __IO uint32_t VD_IO_CFG; /**< IO Voltage Detect Configuration, offset: 0x13C */ + __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ + __IO uint32_t GLITCH_DETECT_SC; /**< Glitch Detect Status Control, offset: 0x144 */ + uint8_t RESERVED_7[440]; + __IO uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ + uint8_t RESERVED_8[252]; + __IO uint32_t SYSLDO_CFG; /**< LDO_SYS Configuration, offset: 0x400 */ + uint8_t RESERVED_9[252]; + __IO uint32_t DCDC_CFG; /**< DCDC Configuration, offset: 0x500 */ + __IO uint32_t DCDC_BURST_CFG; /**< DCDC Burst Configuration, offset: 0x504 */ +} SPC_Type; + +/* ---------------------------------------------------------------------------- + -- SPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Register_Masks SPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SPC_VERID_FEATURE_MASK (0xFFFFU) +#define SPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features + * *.. + */ +#define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK) + +#define SPC_VERID_MINOR_MASK (0xFF0000U) +#define SPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK) + +#define SPC_VERID_MAJOR_MASK (0xFF000000U) +#define SPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name SC - Status Control */ +/*! @{ */ + +#define SPC_SC_BUSY_MASK (0x1U) +#define SPC_SC_BUSY_SHIFT (0U) +/*! BUSY - SPC Busy Status Flag + * 0b0..Not busy + * 0b1..Busy + */ +#define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK) + +#define SPC_SC_SPC_LP_REQ_MASK (0x2U) +#define SPC_SC_SPC_LP_REQ_SHIFT (1U) +/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag + * 0b0..SPC is in Active or Sleep mode; the ACTIVE_CFG register has control + * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK) + +#define SPC_SC_SPC_LP_MODE_MASK (0xF0U) +#define SPC_SC_SPC_LP_MODE_SHIFT (4U) +/*! SPC_LP_MODE - Power Domain Low-Power Mode Request + * 0b0000..Sleep mode with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK) + +#define SPC_SC_ISO_CLR_MASK (0x30000U) +#define SPC_SC_ISO_CLR_SHIFT (16U) +/*! ISO_CLR - Isolation Clear Flags */ +#define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK) +/*! @} */ + +/*! @name CNTRL - SPC Regulator Control */ +/*! @{ */ + +#define SPC_CNTRL_CORELDO_EN_MASK (0x1U) +#define SPC_CNTRL_CORELDO_EN_SHIFT (0U) +/*! CORELDO_EN - LDO_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_CORELDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_CORELDO_EN_SHIFT)) & SPC_CNTRL_CORELDO_EN_MASK) + +#define SPC_CNTRL_SYSLDO_EN_MASK (0x2U) +#define SPC_CNTRL_SYSLDO_EN_SHIFT (1U) +/*! SYSLDO_EN - LDO_SYS Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_SYSLDO_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_SYSLDO_EN_SHIFT)) & SPC_CNTRL_SYSLDO_EN_MASK) + +#define SPC_CNTRL_DCDC_EN_MASK (0x4U) +#define SPC_CNTRL_DCDC_EN_SHIFT (2U) +/*! DCDC_EN - DCDC_CORE Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_CNTRL_DCDC_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_CNTRL_DCDC_EN_SHIFT)) & SPC_CNTRL_DCDC_EN_MASK) +/*! @} */ + +/*! @name LPREQ_CFG - Low-Power Request Configuration */ +/*! @{ */ + +#define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U) +#define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U) +/*! LPREQOE - Low-Power Request Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK) + +#define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U) +#define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U) +/*! LPREQPOL - Low-Power Request Output Pin Polarity Control + * 0b0..High + * 0b1..Low + */ +#define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK) + +#define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU) +#define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U) +/*! LPREQOV - Low-Power Request Output Override + * 0b00..Not forced + * 0b01.. + * 0b10..Forced low (ignore LPREQPOL settings) + * 0b11..Forced high (ignore LPREQPOL settings) + */ +#define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK) +/*! @} */ + +/*! @name PD_STATUS - SPC Power Domain Mode Status */ +/*! @{ */ + +#define SPC_PD_STATUS_PWR_REQ_STATUS_MASK (0x1U) +#define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT (0U) +/*! PWR_REQ_STATUS - Power Request Status Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PWR_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) + +#define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U) +#define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U) +/*! PD_LP_REQ - Power Domain Low Power Request Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK) + +#define SPC_PD_STATUS_LP_MODE_MASK (0xF00U) +#define SPC_PD_STATUS_LP_MODE_SHIFT (8U) +/*! LP_MODE - Power Domain Low Power Mode Request + * 0b0000..SLEEP with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK) +/*! @} */ + +/* The count of SPC_PD_STATUS */ +#define SPC_PD_STATUS_COUNT (2U) + +/*! @name SRAMCTL - SRAM Control */ +/*! @{ */ + +#define SPC_SRAMCTL_VSM_MASK (0x3U) +#define SPC_SRAMCTL_VSM_SHIFT (0U) +/*! VSM - Voltage Select Margin + * 0b00.. + * 0b01..1.0 V + * 0b10..1.1 V + * 0b11.. + */ +#define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) + +#define SPC_SRAMCTL_REQ_MASK (0x40000000U) +#define SPC_SRAMCTL_REQ_SHIFT (30U) +/*! REQ - SRAM Voltage Update Request + * 0b0..Do not request + * 0b1..Request + */ +#define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK) + +#define SPC_SRAMCTL_ACK_MASK (0x80000000U) +#define SPC_SRAMCTL_ACK_SHIFT (31U) +/*! ACK - SRAM Voltage Update Request Acknowledge + * 0b0..Not acknowledged + * 0b1..Acknowledged + */ +#define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG - Active Power Mode Configuration */ +/*! @{ */ + +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00.. + * 0b01..Regulate to mid voltage (1.0 V) + * 0b10..Regulate to normal voltage (1.1 V) + * 0b11..Reserved + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK (0x10U) +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT (4U) +/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK (0x40U) +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT (6U) +/*! SYSLDO_VDD_LVL - LDO_SYS VDD Regulator Voltage Level + * 0b0..Normal voltage (1.8 V) + * 0b1..Overdrive voltage (2.5 V) + */ +#define SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK (0x300U) +#define SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT (8U) +/*! DCDC_VDD_DS - DCDC VDD Drive Strength + * 0b01..Low + * 0b10..Normal + * *.. + */ +#define SPC_ACTIVE_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK (0xC00U) +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT (10U) +/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level + * 0b00..Reserved + * 0b01..Midvoltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.2 V) + */ +#define SPC_ACTIVE_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Low Voltage Glitch Detect enabled + * 0b1..Low Voltage Glitch Detect disabled + */ +#define SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_LPBUFF_EN_MASK (0x40000U) +#define SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT (18U) +/*! LPBUFF_EN - CMP Bandgap Buffer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_LPBUFF_EN_SHIFT)) & SPC_ACTIVE_CFG_LPBUFF_EN_MASK) + +#define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U) +#define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK) + +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK (0x800000U) +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT (23U) +/*! VDD_VD_DISABLE - VDD Voltage Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK) + +#define SPC_ACTIVE_CFG_IO_LVDE_MASK (0x4000000U) +#define SPC_ACTIVE_CFG_IO_LVDE_SHIFT (26U) +/*! IO_LVDE - IO Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_LVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_LVDE_MASK) + +#define SPC_ACTIVE_CFG_CORE_HVDE_MASK (0x8000000U) +#define SPC_ACTIVE_CFG_CORE_HVDE_SHIFT (27U) +/*! CORE_HVDE - Core High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_HVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_HVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) + +#define SPC_ACTIVE_CFG_IO_HVDE_MASK (0x20000000U) +#define SPC_ACTIVE_CFG_IO_HVDE_SHIFT (29U) +/*! IO_HVDE - IO High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_IO_HVDE_SHIFT)) & SPC_ACTIVE_CFG_IO_HVDE_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Active Config Chip Control */ +#define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LP_CFG - Low-Power Mode Configuration */ +/*! @{ */ + +#define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00..Retention voltage + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.15 V) + */ +#define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_LP_CFG_SYSLDO_VDD_DS_MASK (0x10U) +#define SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT (4U) +/*! SYSLDO_VDD_DS - LDO_SYS VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_SYSLDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT)) & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) + +#define SPC_LP_CFG_DCDC_VDD_DS_MASK (0x300U) +#define SPC_LP_CFG_DCDC_VDD_DS_SHIFT (8U) +/*! DCDC_VDD_DS - DCDC VDD Drive Strength + * 0b00..Pulse refresh + * 0b01..Low + * 0b10..Normal + * 0b11.. + */ +#define SPC_LP_CFG_DCDC_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_DS_SHIFT)) & SPC_LP_CFG_DCDC_VDD_DS_MASK) + +#define SPC_LP_CFG_DCDC_VDD_LVL_MASK (0xC00U) +#define SPC_LP_CFG_DCDC_VDD_LVL_SHIFT (10U) +/*! DCDC_VDD_LVL - DCDC VDD Regulator Voltage Level + * 0b00..Retention voltage (0.7 V) + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Overdrive voltage (1.2 V) + */ +#define SPC_LP_CFG_DCDC_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)) & SPC_LP_CFG_DCDC_VDD_LVL_MASK) + +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK (0x1000U) +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT (12U) +/*! GLITCH_DETECT_DISABLE - Glitch Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_LP_CFG_GLITCH_DETECT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_GLITCH_DETECT_DISABLE_SHIFT)) & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) + +#define SPC_LP_CFG_COREVDD_IVS_EN_MASK (0x20000U) +#define SPC_LP_CFG_COREVDD_IVS_EN_SHIFT (17U) +/*! COREVDD_IVS_EN - CORE VDD Internal Voltage Scaling (IVS) Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_COREVDD_IVS_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_COREVDD_IVS_EN_SHIFT)) & SPC_LP_CFG_COREVDD_IVS_EN_MASK) + +#define SPC_LP_CFG_LPBUFF_EN_MASK (0x40000U) +#define SPC_LP_CFG_LPBUFF_EN_SHIFT (18U) +/*! LPBUFF_EN - CMP Bandgap Buffer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_LPBUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LPBUFF_EN_SHIFT)) & SPC_LP_CFG_LPBUFF_EN_MASK) + +#define SPC_LP_CFG_BGMODE_MASK (0x300000U) +#define SPC_LP_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK) + +#define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U) +#define SPC_LP_CFG_LP_IREFEN_SHIFT (23U) +/*! LP_IREFEN - Low-Power IREF Enable + * 0b0..Disable for power saving in Deep Power Down mode + * 0b1..Enable + */ +#define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK) + +#define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_LP_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK) + +#define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_LP_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK) + +#define SPC_LP_CFG_IO_LVDE_MASK (0x4000000U) +#define SPC_LP_CFG_IO_LVDE_SHIFT (26U) +/*! IO_LVDE - IO Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_IO_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_LVDE_SHIFT)) & SPC_LP_CFG_IO_LVDE_MASK) + +#define SPC_LP_CFG_CORE_HVDE_MASK (0x8000000U) +#define SPC_LP_CFG_CORE_HVDE_SHIFT (27U) +/*! CORE_HVDE - Core High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_HVDE_SHIFT)) & SPC_LP_CFG_CORE_HVDE_MASK) + +#define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_LP_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK) + +#define SPC_LP_CFG_IO_HVDE_MASK (0x20000000U) +#define SPC_LP_CFG_IO_HVDE_SHIFT (29U) +/*! IO_HVDE - IO High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_IO_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_IO_HVDE_SHIFT)) & SPC_LP_CFG_IO_HVDE_MASK) +/*! @} */ + +/*! @name LP_CFG1 - Low Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Low-Power Configuration Chip Control */ +#define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */ +/*! @{ */ + +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU) +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U) +/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */ +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK) +/*! @} */ + +/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */ +/*! @{ */ + +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU) +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U) +/*! ACTIVE_VDELAY - Active Voltage Delay */ +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK) +/*! @} */ + +/*! @name VD_STAT - Voltage Detect Status */ +/*! @{ */ + +#define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) +#define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) +#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK) + +#define SPC_VD_STAT_IOVDD_LVDF_MASK (0x4U) +#define SPC_VD_STAT_IOVDD_LVDF_SHIFT (2U) +/*! IOVDD_LVDF - IO VDD LVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_IOVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_LVDF_SHIFT)) & SPC_VD_STAT_IOVDD_LVDF_MASK) + +#define SPC_VD_STAT_COREVDD_HVDF_MASK (0x10U) +#define SPC_VD_STAT_COREVDD_HVDF_SHIFT (4U) +/*! COREVDD_HVDF - Core VDD HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_COREVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_HVDF_SHIFT)) & SPC_VD_STAT_COREVDD_HVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) +#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) +/*! SYSVDD_HVDF - System HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK) + +#define SPC_VD_STAT_IOVDD_HVDF_MASK (0x40U) +#define SPC_VD_STAT_IOVDD_HVDF_SHIFT (6U) +/*! IOVDD_HVDF - IO VDD HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_IOVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_IOVDD_HVDF_SHIFT)) & SPC_VD_STAT_IOVDD_HVDF_MASK) +/*! @} */ + +/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - Core LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK) + +#define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - Core LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK) + +#define SPC_VD_CORE_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_CORE_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - Core VDD HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDRE_SHIFT)) & SPC_VD_CORE_CFG_HVDRE_MASK) + +#define SPC_VD_CORE_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_CORE_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - Core VDD HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_HVDIE_SHIFT)) & SPC_VD_CORE_CFG_HVDIE_MASK) + +#define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_CORE_CFG_LOCK_SHIFT (16U) +/*! LOCK - Core Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_SYS_CFG - System Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - System LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK) + +#define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - System LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK) + +#define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - System HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK) + +#define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - System HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) + +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + +#define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) +/*! LOCK - System Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_IO_CFG - IO Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_IO_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_IO_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - IO VDD LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDRE_SHIFT)) & SPC_VD_IO_CFG_LVDRE_MASK) + +#define SPC_VD_IO_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_IO_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - IO VDD LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVDIE_SHIFT)) & SPC_VD_IO_CFG_LVDIE_MASK) + +#define SPC_VD_IO_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_IO_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - IO VDD HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDRE_SHIFT)) & SPC_VD_IO_CFG_HVDRE_MASK) + +#define SPC_VD_IO_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_IO_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - IO VDD HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_IO_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_HVDIE_SHIFT)) & SPC_VD_IO_CFG_HVDIE_MASK) + +#define SPC_VD_IO_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_IO_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - IO VDD Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_IO_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LVSEL_SHIFT)) & SPC_VD_IO_CFG_LVSEL_MASK) + +#define SPC_VD_IO_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_IO_CFG_LOCK_SHIFT (16U) +/*! LOCK - IO Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_IO_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_IO_CFG_LOCK_SHIFT)) & SPC_VD_IO_CFG_LOCK_MASK) +/*! @} */ + +/*! @name EVD_CFG - External Voltage Domain Configuration */ +/*! @{ */ + +#define SPC_EVD_CFG_EVDISO_MASK (0x3FU) +#define SPC_EVD_CFG_EVDISO_SHIFT (0U) +/*! EVDISO - External Voltage Domain Isolation */ +#define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK) + +#define SPC_EVD_CFG_EVDLPISO_MASK (0x3F00U) +#define SPC_EVD_CFG_EVDLPISO_SHIFT (8U) +/*! EVDLPISO - External Voltage Domain Low-Power Isolation */ +#define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK) + +#define SPC_EVD_CFG_EVDSTAT_MASK (0x3F0000U) +#define SPC_EVD_CFG_EVDSTAT_SHIFT (16U) +/*! EVDSTAT - External Voltage Domain Status */ +#define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) +/*! @} */ + +/*! @name GLITCH_DETECT_SC - Glitch Detect Status Control */ +/*! @{ */ + +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK (0x3U) +#define SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT (0U) +/*! CNT_SELECT - Counter Select + * 0b00..0 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ +#define SPC_GLITCH_DETECT_SC_CNT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_CNT_SELECT_SHIFT)) & SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK) + +#define SPC_GLITCH_DETECT_SC_TIMEOUT_MASK (0x3CU) +#define SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT (2U) +/*! TIMEOUT - Timeout */ +#define SPC_GLITCH_DETECT_SC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_TIMEOUT_SHIFT)) & SPC_GLITCH_DETECT_SC_TIMEOUT_MASK) + +#define SPC_GLITCH_DETECT_SC_RE_MASK (0x40U) +#define SPC_GLITCH_DETECT_SC_RE_SHIFT (6U) +/*! RE - Glitch Detect Reset Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate POR/LVD reset + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate POR/LVD reset + */ +#define SPC_GLITCH_DETECT_SC_RE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_RE_SHIFT)) & SPC_GLITCH_DETECT_SC_RE_MASK) + +#define SPC_GLITCH_DETECT_SC_IE_MASK (0x80U) +#define SPC_GLITCH_DETECT_SC_IE_SHIFT (7U) +/*! IE - Glitch Detect Interrupt Enable + * 0b0..GLITCH_DETECT_FLAG[CNT_SELECT] does not generate hardware interrupt (user polling) + * 0b1..GLITCH_DETECT_FLAG[CNT_SELECT] does generate hardware interrupt + */ +#define SPC_GLITCH_DETECT_SC_IE(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_IE_SHIFT)) & SPC_GLITCH_DETECT_SC_IE_MASK) + +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK (0xF00U) +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT (8U) +/*! GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG */ +#define SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_SHIFT)) & SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) + +#define SPC_GLITCH_DETECT_SC_LOCK_MASK (0x10000U) +#define SPC_GLITCH_DETECT_SC_LOCK_SHIFT (16U) +/*! LOCK - Glitch Detect Reset Enable Lock Bit + * 0b0..Writes to RE are allowed. + * 0b1..Writes to RE are ignored. + */ +#define SPC_GLITCH_DETECT_SC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_GLITCH_DETECT_SC_LOCK_SHIFT)) & SPC_GLITCH_DETECT_SC_LOCK_MASK) +/*! @} */ + +/*! @name CORELDO_CFG - LDO_CORE Configuration */ +/*! @{ */ + +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK (0x10000U) +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT (16U) +/*! DPDOWN_PULLDOWN_DISABLE - LDO_CORE Deep Power Down Pulldown Disable + * 0b0..LDO_CORE pulldown in Deep Power Down not disabled + * 0b1..LDO_CORE pulldown in Deep Power Down disabled + */ +#define SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_SHIFT)) & SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK) +/*! @} */ + +/*! @name SYSLDO_CFG - LDO_SYS Configuration */ +/*! @{ */ + +#define SPC_SYSLDO_CFG_ISINKEN_MASK (0x1U) +#define SPC_SYSLDO_CFG_ISINKEN_SHIFT (0U) +/*! ISINKEN - Current Sink Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_SYSLDO_CFG_ISINKEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SYSLDO_CFG_ISINKEN_SHIFT)) & SPC_SYSLDO_CFG_ISINKEN_MASK) +/*! @} */ + +/*! @name DCDC_CFG - DCDC Configuration */ +/*! @{ */ + +#define SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK (0x1U) +#define SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT (0U) +/*! FREQ_CNTRL_ON - DCDC Burst Frequency Control Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_DCDC_CFG_FREQ_CNTRL_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_ON_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK) + +#define SPC_DCDC_CFG_FREQ_CNTRL_MASK (0x3F00U) +#define SPC_DCDC_CFG_FREQ_CNTRL_SHIFT (8U) +/*! FREQ_CNTRL - DCDC Burst Frequency Control */ +#define SPC_DCDC_CFG_FREQ_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_FREQ_CNTRL_SHIFT)) & SPC_DCDC_CFG_FREQ_CNTRL_MASK) + +#define SPC_DCDC_CFG_BLEED_EN_MASK (0x80000U) +#define SPC_DCDC_CFG_BLEED_EN_SHIFT (19U) +/*! BLEED_EN - DCDC Bleed Enable + * 0b0..Do not add + * 0b1..Add + */ +#define SPC_DCDC_CFG_BLEED_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_CFG_BLEED_EN_SHIFT)) & SPC_DCDC_CFG_BLEED_EN_MASK) +/*! @} */ + +/*! @name DCDC_BURST_CFG - DCDC Burst Configuration */ +/*! @{ */ + +#define SPC_DCDC_BURST_CFG_BURST_REQ_MASK (0x1U) +#define SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT (0U) +/*! BURST_REQ - Software Burst Request + * 0b0..Do not generate + * 0b1..Generate + */ +#define SPC_DCDC_BURST_CFG_BURST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_REQ_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_REQ_MASK) + +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK (0x2U) +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT (1U) +/*! EXT_BURST_EN - External Burst Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_DCDC_BURST_CFG_EXT_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_EXT_BURST_EN_SHIFT)) & SPC_DCDC_BURST_CFG_EXT_BURST_EN_MASK) + +#define SPC_DCDC_BURST_CFG_BURST_ACK_MASK (0x8U) +#define SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT (3U) +/*! BURST_ACK - Burst Acknowledge Flag + * 0b0..Did not complete + * 0b1..Completed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_DCDC_BURST_CFG_BURST_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_BURST_ACK_SHIFT)) & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) + +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK (0xFFFF0000U) +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT (16U) +/*! PULSE_REFRESH_CNT - Refresh Count Value */ +#define SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_SHIFT)) & SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPC_Register_Masks */ + + +/* SPC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x50045000u) + /** Peripheral SPC0 base address */ + #define SPC0_BASE_NS (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Peripheral SPC0 base pointer */ + #define SPC0_NS ((SPC_Type *)SPC0_BASE_NS) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS_NS { SPC0_BASE_NS } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS_NS { SPC0_NS } +#else + /** Peripheral SPC0 base address */ + #define SPC0_BASE (0x40045000u) + /** Peripheral SPC0 base pointer */ + #define SPC0 ((SPC_Type *)SPC0_BASE) + /** Array initializer of SPC peripheral base addresses */ + #define SPC_BASE_ADDRS { SPC0_BASE } + /** Array initializer of SPC peripheral base pointers */ + #define SPC_BASE_PTRS { SPC0 } +#endif + +/*! + * @} + */ /* end of group SPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x10 */ + uint8_t RESERVED_1[36]; + __IO uint32_t CPU0STCKCAL; /**< Secure CPU0 System Tick Calibration, offset: 0x38 */ + __IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + uint8_t RESERVED_3[180]; + __IO uint32_t PRESETCTRL0; /**< Peripheral Reset Control 0, offset: 0x100 */ + __IO uint32_t PRESETCTRL1; /**< Peripheral Reset Control 1, offset: 0x104 */ + __IO uint32_t PRESETCTRL2; /**< Peripheral Reset Control 2, offset: 0x108 */ + __IO uint32_t PRESETCTRL3; /**< Peripheral Reset Control 3, offset: 0x10C */ + uint8_t RESERVED_4[16]; + __O uint32_t PRESETCTRLSET[4]; /**< Peripheral Reset Control Set, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_5[16]; + __O uint32_t PRESETCTRLCLR[4]; /**< Peripheral Reset Control Clear, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_6[176]; + __IO uint32_t AHBCLKCTRL0; /**< AHB Clock Control 0, offset: 0x200 */ + __IO uint32_t AHBCLKCTRL1; /**< AHB Clock Control 1, offset: 0x204 */ + __IO uint32_t AHBCLKCTRL2; /**< AHB Clock Control 2, offset: 0x208 */ + __IO uint32_t AHBCLKCTRL3; /**< AHB Clock Control 3, offset: 0x20C */ + uint8_t RESERVED_7[16]; + __O uint32_t AHBCLKCTRLSET[4]; /**< AHB Clock Control Set, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_8[16]; + __O uint32_t AHBCLKCTRLCLR[4]; /**< AHB Clock Control Clear, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_9[16]; + __IO uint32_t SYSTICKCLKSEL0; /**< CPU0 System Tick Timer Source Select, offset: 0x260 */ + uint8_t RESERVED_10[4]; + __IO uint32_t TRACECLKSEL; /**< Trace Clock Source Select, offset: 0x268 */ + __IO uint32_t CTIMERCLKSEL[5]; /**< CTIMER Clock Source Select, array offset: 0x26C, array step: 0x4 */ + uint8_t RESERVED_11[8]; + __IO uint32_t CLKOUTSEL; /**< CLKOUT Clock Source Select, offset: 0x288 */ + uint8_t RESERVED_12[24]; + __IO uint32_t ADC0CLKSEL; /**< ADC0 Clock Source Select, offset: 0x2A4 */ + uint8_t RESERVED_13[8]; + __IO uint32_t FCCLKSEL[8]; /**< LP_FLEXCOMM Clock Source Select for Fractional Rate Divider, array offset: 0x2B0, array step: 0x4 */ + uint8_t RESERVED_14[48]; + __IO uint32_t SYSTICKCLKDIV[1]; /**< CPU0 System Tick Timer Divider, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_15[4]; + __IO uint32_t TRACECLKDIV; /**< TRACE Clock Divider, offset: 0x308 */ + uint8_t RESERVED_16[108]; + __IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */ + uint8_t RESERVED_17[4]; + __IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT Clock Divider, offset: 0x384 */ + __IO uint32_t FROHFDIV; /**< FRO_HF_DIV Clock Divider, offset: 0x388 */ + __IO uint32_t WDT0CLKDIV; /**< WDT0 Clock Divider, offset: 0x38C */ + uint8_t RESERVED_18[4]; + __IO uint32_t ADC0CLKDIV; /**< ADC0 Clock Divider, offset: 0x394 */ + uint8_t RESERVED_19[44]; + __IO uint32_t PLLCLKDIV; /**< PLL Clock Divider, offset: 0x3C4 */ + uint8_t RESERVED_20[8]; + __IO uint32_t CTIMERCLKDIV[5]; /**< CTimer Clock Divider, array offset: 0x3D0, array step: 0x4 */ + __IO uint32_t PLL1CLK0DIV; /**< PLL1 Clock 0 Divider, offset: 0x3E4 */ + __IO uint32_t PLL1CLK1DIV; /**< PLL1 Clock 1 Divider, offset: 0x3E8 */ + uint8_t RESERVED_21[4]; + __IO uint32_t UTICKCLKDIV; /**< UTICK Clock Divider, offset: 0x3F0 */ + __IO uint32_t CLKOUT_FRGCTRL; /**< CLKOUT FRG Control, offset: 0x3F4 */ + uint8_t RESERVED_22[4]; + __IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */ + __IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */ + __IO uint32_t ROMCR; /**< ROM Wait State, offset: 0x404 */ + uint8_t RESERVED_23[12]; + __IO uint32_t SMARTDMAINT; /**< SmartDMA Interrupt Hijack, offset: 0x414 */ + uint8_t RESERVED_24[76]; + __IO uint32_t ADC1CLKSEL; /**< ADC1 Clock Source Select, offset: 0x464 */ + __IO uint32_t ADC1CLKDIV; /**< ADC1 Clock Divider, offset: 0x468 */ + uint8_t RESERVED_25[4]; + __IO uint32_t RAM_INTERLEAVE; /**< Control PKC RAM Interleave Access, offset: 0x470 */ + uint8_t RESERVED_26[184]; + __IO uint32_t PLLCLKDIVSEL; /**< PLL Clock Divider Clock Selection, offset: 0x52C */ + __IO uint32_t I3C0FCLKSEL; /**< I3C0 Functional Clock Selection, offset: 0x530 */ + uint8_t RESERVED_27[12]; + __IO uint32_t I3C0FCLKDIV; /**< I3C0 Functional Clock FCLK Divider, offset: 0x540 */ + uint8_t RESERVED_28[4]; + __IO uint32_t MICFILFCLKSEL; /**< MICFIL Clock Selection, offset: 0x548 */ + __IO uint32_t MICFILFCLKDIV; /**< MICFIL Clock Division, offset: 0x54C */ + uint8_t RESERVED_29[16]; + __IO uint32_t FLEXIOCLKSEL; /**< FLEXIO Clock Selection, offset: 0x560 */ + __IO uint32_t FLEXIOCLKDIV; /**< FLEXIO Function Clock Divider, offset: 0x564 */ + uint8_t RESERVED_30[56]; + __IO uint32_t FLEXCAN0CLKSEL; /**< FLEXCAN0 Clock Selection, offset: 0x5A0 */ + __IO uint32_t FLEXCAN0CLKDIV; /**< FLEXCAN0 Function Clock Divider, offset: 0x5A4 */ + __IO uint32_t FLEXCAN1CLKSEL; /**< FLEXCAN1 Clock Selection, offset: 0x5A8 */ + __IO uint32_t FLEXCAN1CLKDIV; /**< FLEXCAN1 Function Clock Divider, offset: 0x5AC */ + uint8_t RESERVED_31[36]; + __IO uint32_t EWM0CLKSEL; /**< EWM0 Clock Selection, offset: 0x5D4 */ + __IO uint32_t WDT1CLKSEL; /**< WDT1 Clock Selection, offset: 0x5D8 */ + __IO uint32_t WDT1CLKDIV; /**< WDT1 Function Clock Divider, offset: 0x5DC */ + __IO uint32_t OSTIMERCLKSEL; /**< OSTIMER Clock Selection, offset: 0x5E0 */ + uint8_t RESERVED_32[12]; + __IO uint32_t CMP0FCLKSEL; /**< CMP0 Function Clock Selection, offset: 0x5F0 */ + __IO uint32_t CMP0FCLKDIV; /**< CMP0 Function Clock Divider, offset: 0x5F4 */ + __IO uint32_t CMP0RRCLKSEL; /**< CMP0 Round Robin Clock Selection, offset: 0x5F8 */ + __IO uint32_t CMP0RRCLKDIV; /**< CMP0 Round Robin Clock Divider, offset: 0x5FC */ + __IO uint32_t CMP1FCLKSEL; /**< CMP1 Function Clock Selection, offset: 0x600 */ + __IO uint32_t CMP1FCLKDIV; /**< CMP1 Function Clock Divider, offset: 0x604 */ + __IO uint32_t CMP1RRCLKSEL; /**< CMP1 Round Robin Clock Source Select, offset: 0x608 */ + __IO uint32_t CMP1RRCLKDIV; /**< CMP1 Round Robin Clock Division, offset: 0x60C */ + uint8_t RESERVED_33[508]; + __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_34[20]; + __IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */ + uint8_t RESERVED_35[40]; + __IO uint32_t FLEXCOMMCLKDIV[8]; /**< LP_FLEXCOMM Clock Divider, array offset: 0x850, array step: 0x4 */ + uint8_t RESERVED_36[8]; + __IO uint32_t UTICKCLKSEL; /**< UTICK Function Clock Source Select, offset: 0x878 */ + uint8_t RESERVED_37[4]; + __IO uint32_t SAI0CLKSEL; /**< SAI0 Function Clock Source Select, offset: 0x880 */ + __IO uint32_t SAI1CLKSEL; /**< SAI1 Function Clock Source Select, offset: 0x884 */ + __IO uint32_t SAI0CLKDIV; /**< SAI0 Function Clock Division, offset: 0x888 */ + __IO uint32_t SAI1CLKDIV; /**< SAI1 Function Clock Division, offset: 0x88C */ + uint8_t RESERVED_38[192]; + __IO uint32_t KEY_RETAIN_CTRL; /**< Key Retain Control, offset: 0x950 */ + uint8_t RESERVED_39[12]; + __IO uint32_t REF_CLK_CTRL; /**< FRO 48MHz Reference Clock Control, offset: 0x960 */ + __O uint32_t REF_CLK_CTRL_SET; /**< FRO 48MHz Reference Clock Control Set, offset: 0x964 */ + __O uint32_t REF_CLK_CTRL_CLR; /**< FRO 48MHz Reference Clock Control Clear, offset: 0x968 */ + __IO uint32_t GDET_CTRL[2]; /**< GDET Control Register, array offset: 0x96C, array step: 0x4 */ + __IO uint32_t ELS_ASSET_PROT; /**< ELS Asset Protection Register, offset: 0x974 */ + __IO uint32_t ELS_LOCK_CTRL; /**< ELS Lock Control, offset: 0x978 */ + __IO uint32_t ELS_LOCK_CTRL_DP; /**< ELS Lock Control DP, offset: 0x97C */ + __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0x980 */ + __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0x984 */ + __IO uint32_t ELS_TEMPORAL_STATE; /**< ELS Temporal State, offset: 0x988 */ + __IO uint32_t ELS_KDF_MASK; /**< Key Derivation Function Mask, offset: 0x98C */ + uint8_t RESERVED_40[64]; + __I uint32_t ELS_AS_CFG0; /**< ELS AS Configuration, offset: 0x9D0 */ + __I uint32_t ELS_AS_CFG1; /**< ELS AS Configuration1, offset: 0x9D4 */ + __I uint32_t ELS_AS_CFG2; /**< ELS AS Configuration2, offset: 0x9D8 */ + __I uint32_t ELS_AS_CFG3; /**< ELS AS Configuration3, offset: 0x9DC */ + __I uint32_t ELS_AS_ST0; /**< ELS AS State Register, offset: 0x9E0 */ + __I uint32_t ELS_AS_ST1; /**< ELS AS State1, offset: 0x9E4 */ + __I uint32_t ELS_AS_BOOT_LOG0; /**< Boot state captured during boot: Main ROM log, offset: 0x9E8 */ + __I uint32_t ELS_AS_BOOT_LOG1; /**< Boot state captured during boot: Library log, offset: 0x9EC */ + __I uint32_t ELS_AS_BOOT_LOG2; /**< Boot state captured during boot: Hardware status signals log, offset: 0x9F0 */ + __I uint32_t ELS_AS_BOOT_LOG3; /**< Boot state captured during boot: Security log, offset: 0x9F4 */ + __I uint32_t ELS_AS_FLAG0; /**< ELS AS Flag0, offset: 0x9F8 */ + __I uint32_t ELS_AS_FLAG1; /**< ELS AS Flag1, offset: 0x9FC */ + uint8_t RESERVED_41[24]; + __IO uint32_t CLOCK_CTRL; /**< Clock Control, offset: 0xA18 */ + uint8_t RESERVED_42[276]; + __IO uint32_t I3C1FCLKSEL; /**< I3C1 Functional Clock Selection, offset: 0xB30 */ + uint8_t RESERVED_43[12]; + __IO uint32_t I3C1FCLKDIV; /**< I3C1 Functional Clock FCLK Divider, offset: 0xB40 */ + uint8_t RESERVED_44[28]; + __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray code_gray[31:0], offset: 0xB60 */ + __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray code_gray[41:32], offset: 0xB64 */ + __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ + __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ + uint8_t RESERVED_45[660]; + __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control Automatic Clock Gating, offset: 0xE04 */ + uint8_t RESERVED_46[36]; + __IO uint32_t AUTOCLKGATEOVERRIDEC; /**< Control Automatic Clock Gating C, offset: 0xE2C */ + uint8_t RESERVED_47[8]; + __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0xE38 */ + __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0xE3C */ + __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0xE40 */ + __IO uint32_t ECC_ENABLE_CTRL; /**< RAM ECC Enable Control, offset: 0xE44 */ + uint8_t RESERVED_48[344]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ + uint8_t RESERVED_49[8]; + __IO uint32_t SWD_ACCESS_CPU[1]; /**< CPU0 Software Debug Access, array offset: 0xFB4, array step: 0x4 */ + uint8_t RESERVED_50[8]; + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ + uint8_t RESERVED_51[44]; + __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ + __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip Revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name AHBMATPRIO - AHB Matrix Priority Control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U) +#define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U) +/*! DMA0 - DMA0 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK) + +#define SYSCON_AHBMATPRIO_DMA1_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_DMA1_SHIFT (10U) +/*! DMA1 - DMA1 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA1_SHIFT)) & SYSCON_AHBMATPRIO_DMA1_MASK) + +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK (0x3000U) +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT (12U) +/*! PRI_PKC_ELS - PKC and ELS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_PKC_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PKC_ELS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PKC_ELS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC000000U) +#define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (26U) +/*! PRI_USB_HS - USB-HS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) +/*! @} */ + +/*! @name CPU0STCKCAL - Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + +#define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + +#define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + * 0b1..Enable. + * 0b0..Disable. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name PRESETCTRL0 - Peripheral Reset Control 0 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL0_FMU_RST_MASK (0x200U) +#define SYSCON_PRESETCTRL0_FMU_RST_SHIFT (9U) +/*! FMU_RST - Flash management unit reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_FMU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMU_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMU_RST_MASK) + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (12U) +/*! MUX_RST - INPUTMUX reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT0_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL0_PORT0_RST_SHIFT (13U) +/*! PORT0_RST - PORT0 controller reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT0_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT0_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT1_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL0_PORT1_RST_SHIFT (14U) +/*! PORT1_RST - PORT1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT1_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT1_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT2_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL0_PORT2_RST_SHIFT (15U) +/*! PORT2_RST - PORT2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT2_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT2_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT3_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL0_PORT3_RST_SHIFT (16U) +/*! PORT3_RST - PORT3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT3_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT3_RST_MASK) + +#define SYSCON_PRESETCTRL0_PORT4_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL0_PORT4_RST_SHIFT (17U) +/*! PORT4_RST - PORT4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PORT4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PORT4_RST_SHIFT)) & SYSCON_PRESETCTRL0_PORT4_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (19U) +/*! GPIO0_RST - GPIO0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (20U) +/*! GPIO1_RST - GPIO1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (21U) +/*! GPIO2_RST - GPIO2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (22U) +/*! GPIO3_RST - GPIO3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + +#define SYSCON_PRESETCTRL0_GPIO4_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT (23U) +/*! GPIO4_RST - GPIO4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO4_RST_MASK) + +#define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (25U) +/*! PINT_RST - PINT reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + +#define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (26U) +/*! DMA0_RST - DMA0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + +#define SYSCON_PRESETCTRL0_CRC_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL0_CRC_RST_SHIFT (27U) +/*! CRC_RST - CRC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL0_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL1 - Peripheral Reset Control 1 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) +/*! MRT_RST - MRT reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_ADC0_RST_MASK (0x8U) +#define SYSCON_PRESETCTRL1_ADC0_RST_SHIFT (3U) +/*! ADC0_RST - ADC0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_ADC1_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL1_ADC1_RST_SHIFT (4U) +/*! ADC1_RST - ADC1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_ADC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_ADC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_ADC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_RTC_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL1_RTC_RST_SHIFT (6U) +/*! RTC_RST - RTC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL1_RTC_RST_MASK) + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) +/*! FC0_RST - LP_FLEXCOMM0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) +/*! FC1_RST - LP_FLEXCOMM1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) +/*! FC2_RST - LP_FLEXCOMM2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) +/*! FC3_RST - LP_FLEXCOMM3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) +/*! FC4_RST - LP_FLEXCOMM4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) +/*! FC5_RST - LP_FLEXCOMM5 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) +/*! FC6_RST - LP_FLEXCOMM6 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + +#define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) +/*! FC7_RST - LP_FLEXCOMM7 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + +#define SYSCON_PRESETCTRL1_MICFIL_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT (21U) +/*! MICFIL_RST - MICFIL reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_MICFIL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MICFIL_RST_SHIFT)) & SYSCON_PRESETCTRL1_MICFIL_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) +/*! TIMER2_RST - CTIMER2 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) +/*! TIMER0_RST - CTIMER0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + +#define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) +/*! TIMER1_RST - CTIMER1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) + +#define SYSCON_PRESETCTRL1_SmartDMA_RST_MASK (0x80000000U) +#define SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT (31U) +/*! SmartDMA_RST - SmartDMA reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL1_SmartDMA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SmartDMA_RST_SHIFT)) & SYSCON_PRESETCTRL1_SmartDMA_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL2 - Peripheral Reset Control 2 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) +/*! DMA1_RST - DMA1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXIO_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT (4U) +/*! FLEXIO_RST - FLEXIO reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXIO_RST_MASK) + +#define SYSCON_PRESETCTRL2_SAI0_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL2_SAI0_RST_SHIFT (5U) +/*! SAI0_RST - SAI0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_SAI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI0_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI0_RST_MASK) + +#define SYSCON_PRESETCTRL2_SAI1_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL2_SAI1_RST_SHIFT (6U) +/*! SAI1_RST - SAI1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_SAI1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SAI1_RST_SHIFT)) & SYSCON_PRESETCTRL2_SAI1_RST_MASK) + +#define SYSCON_PRESETCTRL2_TRO_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL2_TRO_RST_SHIFT (7U) +/*! TRO_RST - TRO reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TRO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TRO_RST_SHIFT)) & SYSCON_PRESETCTRL2_TRO_RST_MASK) + +#define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) +/*! FREQME_RST - FREQME reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT (14U) +/*! FLEXCAN0_RST - CAN0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN0_RST_MASK) + +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT (15U) +/*! FLEXCAN1_RST - CAN1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_FLEXCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FLEXCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL2_FLEXCAN1_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB_HS_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT (16U) +/*! USB_HS_RST - USB HS reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_USB_HS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_RST_MASK) + +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT (17U) +/*! USB_HS_PHY_RST - USB HS PHY reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_USB_HS_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB_HS_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB_HS_PHY_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) +/*! TIMER3_RST - CTIMER3 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + +#define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) +/*! TIMER4_RST - CTIMER4 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + +#define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) +/*! PUF_RST - PUF reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + +#define SYSCON_PRESETCTRL2_PKC_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL2_PKC_RST_SHIFT (24U) +/*! PKC_RST - PKC reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL2_PKC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PKC_RST_SHIFT)) & SYSCON_PRESETCTRL2_PKC_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRL3 - Peripheral Reset Control 3 */ +/*! @{ */ + +#define SYSCON_PRESETCTRL3_I3C0_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL3_I3C0_RST_SHIFT (0U) +/*! I3C0_RST - I3C0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_I3C0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C0_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C0_RST_MASK) + +#define SYSCON_PRESETCTRL3_I3C1_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL3_I3C1_RST_SHIFT (1U) +/*! I3C1_RST - I3C1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_I3C1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_I3C1_RST_SHIFT)) & SYSCON_PRESETCTRL3_I3C1_RST_MASK) + +#define SYSCON_PRESETCTRL3_QDC0_RST_MASK (0x10U) +#define SYSCON_PRESETCTRL3_QDC0_RST_SHIFT (4U) +/*! QDC0_RST - QDC0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_QDC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC0_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC0_RST_MASK) + +#define SYSCON_PRESETCTRL3_QDC1_RST_MASK (0x20U) +#define SYSCON_PRESETCTRL3_QDC1_RST_SHIFT (5U) +/*! QDC1_RST - QDC1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_QDC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_QDC1_RST_SHIFT)) & SYSCON_PRESETCTRL3_QDC1_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM0_RST_MASK (0x40U) +#define SYSCON_PRESETCTRL3_PWM0_RST_SHIFT (6U) +/*! PWM0_RST - PWM0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_PWM0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM0_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM0_RST_MASK) + +#define SYSCON_PRESETCTRL3_PWM1_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL3_PWM1_RST_SHIFT (7U) +/*! PWM1_RST - PWM1 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_PWM1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_PWM1_RST_SHIFT)) & SYSCON_PRESETCTRL3_PWM1_RST_MASK) + +#define SYSCON_PRESETCTRL3_AOI0_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL3_AOI0_RST_SHIFT (8U) +/*! AOI0_RST - AOI0 reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_AOI0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_AOI0_RST_SHIFT)) & SYSCON_PRESETCTRL3_AOI0_RST_MASK) + +#define SYSCON_PRESETCTRL3_VREF_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL3_VREF_RST_SHIFT (19U) +/*! VREF_RST - VREF reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_VREF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_VREF_RST_SHIFT)) & SYSCON_PRESETCTRL3_VREF_RST_MASK) + +#define SYSCON_PRESETCTRL3_EWM_RST_MASK (0x800000U) +#define SYSCON_PRESETCTRL3_EWM_RST_SHIFT (23U) +/*! EWM_RST - EWM reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_EWM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EWM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EWM_RST_MASK) + +#define SYSCON_PRESETCTRL3_EIM_RST_MASK (0x1000000U) +#define SYSCON_PRESETCTRL3_EIM_RST_SHIFT (24U) +/*! EIM_RST - EIM reset control + * 0b1..Block is reset + * 0b0..Block is not reset + */ +#define SYSCON_PRESETCTRL3_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL3_EIM_RST_SHIFT)) & SYSCON_PRESETCTRL3_EIM_RST_MASK) +/*! @} */ + +/*! @name PRESETCTRLSET - Peripheral Reset Control Set */ +/*! @{ */ + +#define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ +#define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (4U) + +/*! @name PRESETCTRLCLR - Peripheral Reset Control Clear */ +/*! @{ */ + +#define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in PRESETCTRLn. */ +#define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (4U) + +/*! @name AHBCLKCTRL0 - AHB Clock Control 0 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) +/*! ROM - Enables the clock for the ROM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK (0x4U) +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT (2U) +/*! RAMB_CTRL - Enables the clock for the RAMB Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMB_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMB_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK (0x8U) +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT (3U) +/*! RAMC_CTRL - Enables the clock for the RAMC Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMC_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMC_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK (0x10U) +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT (4U) +/*! RAMD_CTRL - Enables the clock for the RAMD Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAMD_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAMD_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK (0x20U) +#define SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT (5U) +/*! RAME_CTRL - Enables the clock for the RAME Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RAME_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL0_RAME_CTRL_MASK) + +#define SYSCON_AHBCLKCTRL0_FMU_MASK (0x200U) +#define SYSCON_AHBCLKCTRL0_FMU_SHIFT (9U) +/*! FMU - Enables the clock for the Flash Management Unit + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_FMU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMU_SHIFT)) & SYSCON_AHBCLKCTRL0_FMU_MASK) + +#define SYSCON_AHBCLKCTRL0_FMC_MASK (0x400U) +#define SYSCON_AHBCLKCTRL0_FMC_SHIFT (10U) +/*! FMC - Enables the clock for the Flash Memory Controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (12U) +/*! MUX - Enables the clock for INPUTMUX + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT0_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL0_PORT0_SHIFT (13U) +/*! PORT0 - Enables the clock for PORT0 controller + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT0_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT0_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT1_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL0_PORT1_SHIFT (14U) +/*! PORT1 - Enables the clock for PORT1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT1_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT1_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT2_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL0_PORT2_SHIFT (15U) +/*! PORT2 - Enables the clock for PORT2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT2_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT2_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT3_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL0_PORT3_SHIFT (16U) +/*! PORT3 - Enables the clock for PORT3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT3_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT3_MASK) + +#define SYSCON_AHBCLKCTRL0_PORT4_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL0_PORT4_SHIFT (17U) +/*! PORT4 - Enables the clock for PORT4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PORT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PORT4_SHIFT)) & SYSCON_AHBCLKCTRL0_PORT4_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (19U) +/*! GPIO0 - Enables the clock for GPIO0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (20U) +/*! GPIO1 - Enables the clock for GPIO1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (21U) +/*! GPIO2 - Enables the clock for GPIO2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (22U) +/*! GPIO3 - Enables the clock for GPIO3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + +#define SYSCON_AHBCLKCTRL0_GPIO4_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL0_GPIO4_SHIFT (23U) +/*! GPIO4 - Enables the clock for GPIO4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO4_MASK) + +#define SYSCON_AHBCLKCTRL0_PINT_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL0_PINT_SHIFT (25U) +/*! PINT - Enables the clock for PINT + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + +#define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (26U) +/*! DMA0 - Enables the clock for DMA0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + +#define SYSCON_AHBCLKCTRL0_CRC_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL0_CRC_SHIFT (27U) +/*! CRC - Enables the clock for CRC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRC_SHIFT)) & SYSCON_AHBCLKCTRL0_CRC_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT0_MASK (0x10000000U) +#define SYSCON_AHBCLKCTRL0_WWDT0_SHIFT (28U) +/*! WWDT0 - Enables the clock for WWDT0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT0_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT0_MASK) + +#define SYSCON_AHBCLKCTRL0_WWDT1_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL0_WWDT1_SHIFT (29U) +/*! WWDT1 - Enables the clock for WWDT1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL0_WWDT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT1_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT1_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL1 - AHB Clock Control 1 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) +#define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) +/*! MRT - Enables the clock for MRT + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_ADC0_MASK (0x8U) +#define SYSCON_AHBCLKCTRL1_ADC0_SHIFT (3U) +/*! ADC0 - Enables the clock for ADC0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC0_MASK) + +#define SYSCON_AHBCLKCTRL1_ADC1_MASK (0x10U) +#define SYSCON_AHBCLKCTRL1_ADC1_SHIFT (4U) +/*! ADC1 - Enables the clock for ADC1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_ADC1_SHIFT)) & SYSCON_AHBCLKCTRL1_ADC1_MASK) + +#define SYSCON_AHBCLKCTRL1_RTC_MASK (0x40U) +#define SYSCON_AHBCLKCTRL1_RTC_SHIFT (6U) +/*! RTC - Enables the clock for RTC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_RTC_SHIFT)) & SYSCON_AHBCLKCTRL1_RTC_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for UTICK + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + +#define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) +/*! FC0 - Enables the clock for LP_FLEXCOMM0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + +#define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) +/*! FC1 - Enables the clock for LP_FLEXCOMM1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + +#define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) +/*! FC2 - Enables the clock for LP_FLEXCOMM2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + +#define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) +/*! FC3 - Enables the clock for LP_FLEXCOMM3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + +#define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) +/*! FC4 - Enables the clock for LP_FLEXCOMM4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + +#define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) +/*! FC5 - Enables the clock for LP_FLEXCOMM5 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + +#define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) +/*! FC6 - Enables the clock for LP_FLEXCOMM6 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + +#define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) +/*! FC7 - Enables the clock for LP_FLEXCOMM7 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + +#define SYSCON_AHBCLKCTRL1_MICFIL_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL1_MICFIL_SHIFT (21U) +/*! MICFIL - Enables the clock for MICFIL + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_MICFIL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MICFIL_SHIFT)) & SYSCON_AHBCLKCTRL1_MICFIL_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) +/*! TIMER2 - Enables the clock for CTIMER2 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) +/*! TIMER0 - Enables the clock for CTIMER0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + +#define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) +/*! TIMER1 - Enables the clock for CTIMER1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) + +#define SYSCON_AHBCLKCTRL1_PKC_RAM_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT (29U) +/*! PKC_RAM - Enables the clock for PKC RAM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_PKC_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PKC_RAM_SHIFT)) & SYSCON_AHBCLKCTRL1_PKC_RAM_MASK) + +#define SYSCON_AHBCLKCTRL1_SmartDMA_MASK (0x80000000U) +#define SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT (31U) +/*! SmartDMA - Enables the clock for SmartDMA + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL1_SmartDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SmartDMA_SHIFT)) & SYSCON_AHBCLKCTRL1_SmartDMA_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL2 - AHB Clock Control 2 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) +/*! DMA1 - Enables the clock for DMA1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXIO_MASK (0x10U) +#define SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT (4U) +/*! FLEXIO - Enables the clock for Flexio + * 0b1..Enable clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXIO_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXIO_MASK) + +#define SYSCON_AHBCLKCTRL2_SAI0_MASK (0x20U) +#define SYSCON_AHBCLKCTRL2_SAI0_SHIFT (5U) +/*! SAI0 - Enables the clock for SAI0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SAI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI0_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI0_MASK) + +#define SYSCON_AHBCLKCTRL2_SAI1_MASK (0x40U) +#define SYSCON_AHBCLKCTRL2_SAI1_SHIFT (6U) +/*! SAI1 - Enables the clock for SAI1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SAI1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SAI1_SHIFT)) & SYSCON_AHBCLKCTRL2_SAI1_MASK) + +#define SYSCON_AHBCLKCTRL2_TRO_MASK (0x80U) +#define SYSCON_AHBCLKCTRL2_TRO_SHIFT (7U) +/*! TRO - Enables the clock for TRO + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TRO_SHIFT)) & SYSCON_AHBCLKCTRL2_TRO_MASK) + +#define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) +#define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) +/*! FREQME - Enables the clock for the Frequency meter + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT (14U) +/*! FLEXCAN0 - Enables the clock for FLEXCAN0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN0_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN0_MASK) + +#define SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT (15U) +/*! FLEXCAN1 - Enables the clock for FLEXCAN1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FLEXCAN1_SHIFT)) & SYSCON_AHBCLKCTRL2_FLEXCAN1_MASK) + +#define SYSCON_AHBCLKCTRL2_USB_HS_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL2_USB_HS_SHIFT (16U) +/*! USB_HS - Enables the clock for USB HS + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_MASK) + +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT (17U) +/*! USB_HS_PHY - Enables the clock for USB HS PHY + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_USB_HS_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB_HS_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK) + +#define SYSCON_AHBCLKCTRL2_ELS_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_ELS_SHIFT (18U) +/*! ELS - Enables the clock for ELS + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_ELS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ELS_SHIFT)) & SYSCON_AHBCLKCTRL2_ELS_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) +/*! TIMER3 - Enables the clock for CTIMER3 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + +#define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) +/*! TIMER4 - Enables the clock for CTIMER4 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + +#define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) +/*! PUF - Enables the clock for PUF + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + +#define SYSCON_AHBCLKCTRL2_PKC_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL2_PKC_SHIFT (24U) +/*! PKC - Enables the clock for PKC + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_PKC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PKC_SHIFT)) & SYSCON_AHBCLKCTRL2_PKC_MASK) + +#define SYSCON_AHBCLKCTRL2_SCG_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL2_SCG_SHIFT (26U) +/*! SCG - Enables the clock for SCG + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_SCG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SCG_SHIFT)) & SYSCON_AHBCLKCTRL2_SCG_MASK) + +#define SYSCON_AHBCLKCTRL2_GDET_MASK (0x20000000U) +#define SYSCON_AHBCLKCTRL2_GDET_SHIFT (29U) +/*! GDET - Enables the clock for GDET0 and GDET1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL2_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GDET_SHIFT)) & SYSCON_AHBCLKCTRL2_GDET_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL3 - AHB Clock Control 3 */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRL3_I3C0_MASK (0x1U) +#define SYSCON_AHBCLKCTRL3_I3C0_SHIFT (0U) +/*! I3C0 - Enables the clock for I3C0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_I3C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C0_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C0_MASK) + +#define SYSCON_AHBCLKCTRL3_I3C1_MASK (0x2U) +#define SYSCON_AHBCLKCTRL3_I3C1_SHIFT (1U) +/*! I3C1 - Enables the clock for I3C1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_I3C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_I3C1_SHIFT)) & SYSCON_AHBCLKCTRL3_I3C1_MASK) + +#define SYSCON_AHBCLKCTRL3_QDC0_MASK (0x10U) +#define SYSCON_AHBCLKCTRL3_QDC0_SHIFT (4U) +/*! QDC0 - Enables the clock for QDC0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_QDC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC0_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC0_MASK) + +#define SYSCON_AHBCLKCTRL3_QDC1_MASK (0x20U) +#define SYSCON_AHBCLKCTRL3_QDC1_SHIFT (5U) +/*! QDC1 - Enables the clock for QDC1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_QDC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_QDC1_SHIFT)) & SYSCON_AHBCLKCTRL3_QDC1_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM0_MASK (0x40U) +#define SYSCON_AHBCLKCTRL3_PWM0_SHIFT (6U) +/*! PWM0 - Enables the clock for PWM0 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_PWM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM0_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM0_MASK) + +#define SYSCON_AHBCLKCTRL3_PWM1_MASK (0x80U) +#define SYSCON_AHBCLKCTRL3_PWM1_SHIFT (7U) +/*! PWM1 - Enables the clock for PWM1 + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_PWM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_PWM1_SHIFT)) & SYSCON_AHBCLKCTRL3_PWM1_MASK) + +#define SYSCON_AHBCLKCTRL3_EVTG_MASK (0x100U) +#define SYSCON_AHBCLKCTRL3_EVTG_SHIFT (8U) +/*! EVTG - Enables the clock for EVTG + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EVTG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EVTG_SHIFT)) & SYSCON_AHBCLKCTRL3_EVTG_MASK) + +#define SYSCON_AHBCLKCTRL3_VREF_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL3_VREF_SHIFT (19U) +/*! VREF - Enables the clock for VREF + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_VREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_VREF_SHIFT)) & SYSCON_AHBCLKCTRL3_VREF_MASK) + +#define SYSCON_AHBCLKCTRL3_EWM_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL3_EWM_SHIFT (23U) +/*! EWM - Enables the clock for EWM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EWM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EWM_SHIFT)) & SYSCON_AHBCLKCTRL3_EWM_MASK) + +#define SYSCON_AHBCLKCTRL3_EIM_MASK (0x1000000U) +#define SYSCON_AHBCLKCTRL3_EIM_SHIFT (24U) +/*! EIM - Enables the clock for EIM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_EIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_EIM_SHIFT)) & SYSCON_AHBCLKCTRL3_EIM_MASK) + +#define SYSCON_AHBCLKCTRL3_ERM_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL3_ERM_SHIFT (25U) +/*! ERM - Enables the clock for ERM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_ERM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_ERM_SHIFT)) & SYSCON_AHBCLKCTRL3_ERM_MASK) + +#define SYSCON_AHBCLKCTRL3_INTM_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL3_INTM_SHIFT (26U) +/*! INTM - Enables the clock for INTM + * 0b1..Enables clock + * 0b0..Disables clock + */ +#define SYSCON_AHBCLKCTRL3_INTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL3_INTM_SHIFT)) & SYSCON_AHBCLKCTRL3_INTM_MASK) +/*! @} */ + +/*! @name AHBCLKCTRLSET - AHB Clock Control Set */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (4U) + +/*! @name AHBCLKCTRLCLR - AHB Clock Control Clear */ +/*! @{ */ + +#define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value */ +#define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (4U) + +/*! @name SYSTICKCLKSEL0 - CPU0 System Tick Timer Source Select */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) +#define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) +/*! SEL - Selects the System Tick Timer for CPU0 source + * 0b000..SYSTICKCLKDIV0 output + * 0b001..Clk 1 MHz clock + * 0b010..LP Oscillator clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_SYSTICKCLKSEL0_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSEL0_SEL_SHIFT)) & SYSCON_SYSTICKCLKSEL0_SEL_MASK) +/*! @} */ + +/*! @name TRACECLKSEL - Trace Clock Source Select */ +/*! @{ */ + +#define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) +#define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the trace clock source. + * 0b000..TRACECLKDIV output + * 0b001..Clk 1 MHz clock + * 0b010..LP Oscillator clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_TRACECLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKSEL_SEL_SHIFT)) & SYSCON_TRACECLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CTIMERCLKSEL - CTIMER Clock Source Select */ +/*! @{ */ + +#define SYSCON_CTIMERCLKSEL_SEL_MASK (0xFU) +#define SYSCON_CTIMERCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CTIMER clock source. + * 0b0000..FRO_1M clock + * 0b0001..PLL0 clock + * 0b0010..PLL1_clk0 clock + * 0b0011..FRO_HF clock + * 0b0100..FRO 12MHz clock + * 0b0101..SAI0 MCLK IN clock + * 0b0110..LP Oscillator clock + * 0b0111..No clock + * 0b1000..SAI1 MCLK IN clock + * 0b1001..SAI0 TX_BCLK clock + * 0b1010..SAI0 RX_BCLK clock + * 0b1011..SAI1 TX_BCLK clock + * 0b1100..SAI1 RX_BCLK clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_CTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSEL_SEL_SHIFT)) & SYSCON_CTIMERCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERCLKSEL */ +#define SYSCON_CTIMERCLKSEL_COUNT (5U) + +/*! @name CLKOUTSEL - CLKOUT Clock Source Select */ +/*! @{ */ + +#define SYSCON_CLKOUTSEL_SEL_MASK (0xFU) +#define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CLKOUT clock source. + * 0b0000..Main clock (main_clk) + * 0b0001..PLL0 clock (pll0_clk) + * 0b0010..CLKIN clock (clk_in) + * 0b0011..FRO_HF clock (fro_hf) + * 0b0100..FRO 12 MHz clock (fro_12m) + * 0b0101..PLL1_clk0 clock (pll1_clk) + * 0b0110..LP Oscillator clock (lp_osc) + * 0b0111..USB PLL clock (usb_pll_clk) + * 0b1000..No clock + * 0b1001..No clock + * 0b1010..No clock + * 0b1011..No clock + * 0b1100..No clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC0CLKSEL - ADC0 Clock Source Select */ +/*! @{ */ + +#define SYSCON_ADC0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the ADC0 clock source. + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO 12 MHz clock + * 0b100..Clk_in + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_ADC0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKSEL_SEL_SHIFT)) & SYSCON_ADC0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FCCLKSEL - LP_FLEXCOMM Clock Source Select for Fractional Rate Divider */ +/*! @{ */ + +#define SYSCON_FCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FCCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the LP_FLEXCOMM clock source for Fractional Rate Divider. + * 0b000..No clock + * 0b001..PLL divided clock + * 0b010..FRO 12 MHz clock + * 0b011..fro_hf_div clock + * 0b100..clk_1m clock + * 0b101..USB PLL clock + * 0b110..LP Oscillator clock + * 0b111..No clock + */ +#define SYSCON_FCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSEL_SEL_SHIFT)) & SYSCON_FCCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FCCLKSEL */ +#define SYSCON_FCCLKSEL_COUNT (8U) + +/*! @name SYSTICKCLKDIV - CPU0 System Tick Timer Divider */ +/*! @{ */ + +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) + +#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset. + * 0b0..Divider is not reset + */ +#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) + +#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) + +#define SYSCON_SYSTICKCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SYSTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_SYSTICKCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_SYSTICKCLKDIV */ +#define SYSCON_SYSTICKCLKDIV_COUNT (1U) + +/*! @name TRACECLKDIV - TRACE Clock Divider */ +/*! @{ */ + +#define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) +#define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + +#define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + +#define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + +#define SYSCON_TRACECLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_TRACECLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_TRACECLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_UNSTAB_SHIFT)) & SYSCON_TRACECLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK) + +#define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK) + +#define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - System Clock Divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT Clock Divider */ +/*! @{ */ + +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + +#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) +#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + +#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) +#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + +#define SYSCON_CLKOUTDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CLKOUTDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CLKOUTDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_UNSTAB_SHIFT)) & SYSCON_CLKOUTDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FROHFDIV - FRO_HF_DIV Clock Divider */ +/*! @{ */ + +#define SYSCON_FROHFDIV_DIV_MASK (0xFFU) +#define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + +#define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) +#define SYSCON_FROHFDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running, this bit is set to 0 when the register is written. + */ +#define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + +#define SYSCON_FROHFDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FROHFDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FROHFDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_UNSTAB_SHIFT)) & SYSCON_FROHFDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name WDT0CLKDIV - WDT0 Clock Divider */ +/*! @{ */ + +#define SYSCON_WDT0CLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDT0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_WDT0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_DIV_SHIFT)) & SYSCON_WDT0CLKDIV_DIV_MASK) + +#define SYSCON_WDT0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDT0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_WDT0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_RESET_SHIFT)) & SYSCON_WDT0CLKDIV_RESET_MASK) + +#define SYSCON_WDT0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDT0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_WDT0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_HALT_SHIFT)) & SYSCON_WDT0CLKDIV_HALT_MASK) + +#define SYSCON_WDT0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_WDT0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_WDT0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT0CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name ADC0CLKDIV - ADC0 Clock Divider */ +/*! @{ */ + +#define SYSCON_ADC0CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_ADC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_DIV_SHIFT)) & SYSCON_ADC0CLKDIV_DIV_MASK) + +#define SYSCON_ADC0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_ADC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_RESET_SHIFT)) & SYSCON_ADC0CLKDIV_RESET_MASK) + +#define SYSCON_ADC0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_ADC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_HALT_SHIFT)) & SYSCON_ADC0CLKDIV_HALT_MASK) + +#define SYSCON_ADC0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_ADC0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC0CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLLCLKDIV - PLL Clock Divider */ +/*! @{ */ + +#define SYSCON_PLLCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_PLLCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLLCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_DIV_SHIFT)) & SYSCON_PLLCLKDIV_DIV_MASK) + +#define SYSCON_PLLCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_PLLCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLLCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_RESET_SHIFT)) & SYSCON_PLLCLKDIV_RESET_MASK) + +#define SYSCON_PLLCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_PLLCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLLCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_HALT_SHIFT)) & SYSCON_PLLCLKDIV_HALT_MASK) + +#define SYSCON_PLLCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLLCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLLCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIV_UNSTAB_SHIFT)) & SYSCON_PLLCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CTIMERXCLKDIV_CTIMERCLKDIV - CTimer Clock Divider */ +/*! @{ */ + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_DIV_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b0..Divider is not reset + * 0b1..Divider is reset + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_RESET_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock has stopped + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_HALT_MASK) + +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Stable divider clock + * 0b1..Unstable clock frequency + */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_SHIFT)) & SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV */ +#define SYSCON_CTIMERXCLKDIV_CTIMERCLKDIV_COUNT (5U) + +/*! @name PLL1CLK0DIV - PLL1 Clock 0 Divider */ +/*! @{ */ + +#define SYSCON_PLL1CLK0DIV_DIV_MASK (0xFFU) +#define SYSCON_PLL1CLK0DIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLL1CLK0DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_DIV_SHIFT)) & SYSCON_PLL1CLK0DIV_DIV_MASK) + +#define SYSCON_PLL1CLK0DIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL1CLK0DIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLL1CLK0DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_RESET_SHIFT)) & SYSCON_PLL1CLK0DIV_RESET_MASK) + +#define SYSCON_PLL1CLK0DIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL1CLK0DIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLL1CLK0DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_HALT_SHIFT)) & SYSCON_PLL1CLK0DIV_HALT_MASK) + +#define SYSCON_PLL1CLK0DIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLL1CLK0DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK0DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK0DIV_UNSTAB_MASK) +/*! @} */ + +/*! @name PLL1CLK1DIV - PLL1 Clock 1 Divider */ +/*! @{ */ + +#define SYSCON_PLL1CLK1DIV_DIV_MASK (0xFFU) +#define SYSCON_PLL1CLK1DIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_PLL1CLK1DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_DIV_SHIFT)) & SYSCON_PLL1CLK1DIV_DIV_MASK) + +#define SYSCON_PLL1CLK1DIV_RESET_MASK (0x20000000U) +#define SYSCON_PLL1CLK1DIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_PLL1CLK1DIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_RESET_SHIFT)) & SYSCON_PLL1CLK1DIV_RESET_MASK) + +#define SYSCON_PLL1CLK1DIV_HALT_MASK (0x40000000U) +#define SYSCON_PLL1CLK1DIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_PLL1CLK1DIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_HALT_SHIFT)) & SYSCON_PLL1CLK1DIV_HALT_MASK) + +#define SYSCON_PLL1CLK1DIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_PLL1CLK1DIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CLK1DIV_UNSTAB_SHIFT)) & SYSCON_PLL1CLK1DIV_UNSTAB_MASK) +/*! @} */ + +/*! @name UTICKCLKDIV - UTICK Clock Divider */ +/*! @{ */ + +#define SYSCON_UTICKCLKDIV_DIV_MASK (0x3FU) +#define SYSCON_UTICKCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_UTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_DIV_SHIFT)) & SYSCON_UTICKCLKDIV_DIV_MASK) + +#define SYSCON_UTICKCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_UTICKCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_UTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_RESET_SHIFT)) & SYSCON_UTICKCLKDIV_RESET_MASK) + +#define SYSCON_UTICKCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_UTICKCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_UTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_HALT_SHIFT)) & SYSCON_UTICKCLKDIV_HALT_MASK) + +#define SYSCON_UTICKCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_UTICKCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_UTICKCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKDIV_UNSTAB_SHIFT)) & SYSCON_UTICKCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKOUT_FRGCTRL - CLKOUT FRG Control */ +/*! @{ */ + +#define SYSCON_CLKOUT_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT (0U) +/*! DIV - Divider value */ +#define SYSCON_CLKOUT_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_DIV_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_DIV_MASK) + +#define SYSCON_CLKOUT_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT (8U) +/*! MULT - Numerator value */ +#define SYSCON_CLKOUT_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUT_FRGCTRL_MULT_SHIFT)) & SYSCON_CLKOUT_FRGCTRL_MULT_MASK) +/*! @} */ + +/*! @name CLKUNLOCK - Clock Configuration Unlock */ +/*! @{ */ + +#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U) +#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) +/*! UNLOCK - Controls clock configuration registers access (for example, xxxDIV, xxxSEL) + * 0b1..Freezes all clock configuration registers update + * 0b0..Updates are allowed to all clock configuration registers + */ +#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) +/*! @} */ + +/*! @name NVM_CTRL - NVM Control */ +/*! @{ */ + +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U) +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U) +/*! DIS_FLASH_SPEC - Flash speculation control + * 0b0..Enables flash speculation + * 0b1..Disables flash speculation + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U) +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U) +/*! DIS_DATA_SPEC - Flash data speculation control + * 0b0..Enables data speculation + * 0b1..Disables data speculation + */ +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK (0x4U) +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT (2U) +/*! DIS_FLASH_CACHE - Flash cache control + * 0b0..Enables flash cache + * 0b1..Disables flash cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_CACHE_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK (0x8U) +#define SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT (3U) +/*! DIS_FLASH_INST - Flash instruction cache control + * 0b0..Enables flash instruction cache when DIS_FLASH_CACHE=0 + * 0b1..Disables flash instruction cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK (0x10U) +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT (4U) +/*! DIS_FLASH_DATA - Flash data cache control + * 0b0..Enables flash data cache when DIS_FLASH_CACHE=0 + * 0b1..Disables flash data cache + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_DATA_MASK) + +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK (0x20U) +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT (5U) +/*! CLR_FLASH_CACHE - Clear flash cache control + * 0b0..No clear flash cache + * 0b1..Clears flash cache + */ +#define SYSCON_NVM_CTRL_CLR_FLASH_CACHE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_CLR_FLASH_CACHE_SHIFT)) & SYSCON_NVM_CTRL_CLR_FLASH_CACHE_MASK) + +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U) +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U) +/*! FLASH_STALL_EN - FLASH stall on busy control + * 0b0..No stall on FLASH busy + * 0b1..Stall on FLASH busy + */ +#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) +/*! DIS_MBECC_ERR_INST + * 0b0..Enables bus error on multi-bit ECC error for instruction + * 0b1..Disables bus error on multi-bit ECC error for instruction + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) +/*! DIS_MBECC_ERR_DATA + * 0b0..Enables bus error on multi-bit ECC error for data + * 0b1..Disables bus error on multi-bit ECC error for data + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) +/*! @} */ + +/*! @name ROMCR - ROM Wait State */ +/*! @{ */ + +#define SYSCON_ROMCR_ROM_WAIT_MASK (0x1U) +#define SYSCON_ROMCR_ROM_WAIT_SHIFT (0U) +/*! ROM_WAIT - ROM waiting Arm core and other masters for one cycle + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSCON_ROMCR_ROM_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROMCR_ROM_WAIT_SHIFT)) & SYSCON_ROMCR_ROM_WAIT_MASK) +/*! @} */ + +/*! @name SMARTDMAINT - SmartDMA Interrupt Hijack */ +/*! @{ */ + +#define SYSCON_SMARTDMAINT_INT0_MASK (0x1U) +#define SYSCON_SMARTDMAINT_INT0_SHIFT (0U) +/*! INT0 - SmartDMA hijack NVIC IRQ1 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT0_SHIFT)) & SYSCON_SMARTDMAINT_INT0_MASK) + +#define SYSCON_SMARTDMAINT_INT1_MASK (0x2U) +#define SYSCON_SMARTDMAINT_INT1_SHIFT (1U) +/*! INT1 - SmartDMA hijack NVIC IRQ17 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT1_SHIFT)) & SYSCON_SMARTDMAINT_INT1_MASK) + +#define SYSCON_SMARTDMAINT_INT2_MASK (0x4U) +#define SYSCON_SMARTDMAINT_INT2_SHIFT (2U) +/*! INT2 - SmartDMA hijack NVIC IRQ18 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT2_SHIFT)) & SYSCON_SMARTDMAINT_INT2_MASK) + +#define SYSCON_SMARTDMAINT_INT3_MASK (0x8U) +#define SYSCON_SMARTDMAINT_INT3_SHIFT (3U) +/*! INT3 - SmartDMA hijack NVIC IRQ29 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT3_SHIFT)) & SYSCON_SMARTDMAINT_INT3_MASK) + +#define SYSCON_SMARTDMAINT_INT4_MASK (0x10U) +#define SYSCON_SMARTDMAINT_INT4_SHIFT (4U) +/*! INT4 - SmartDMA hijack NVIC IRQ30 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT4_SHIFT)) & SYSCON_SMARTDMAINT_INT4_MASK) + +#define SYSCON_SMARTDMAINT_INT5_MASK (0x20U) +#define SYSCON_SMARTDMAINT_INT5_SHIFT (5U) +/*! INT5 - SmartDMA hijack NVIC IRQ31 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT5_SHIFT)) & SYSCON_SMARTDMAINT_INT5_MASK) + +#define SYSCON_SMARTDMAINT_INT6_MASK (0x40U) +#define SYSCON_SMARTDMAINT_INT6_SHIFT (6U) +/*! INT6 - SmartDMA hijack NVIC IRQ32 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT6_SHIFT)) & SYSCON_SMARTDMAINT_INT6_MASK) + +#define SYSCON_SMARTDMAINT_INT7_MASK (0x80U) +#define SYSCON_SMARTDMAINT_INT7_SHIFT (7U) +/*! INT7 - SmartDMA hijack NVIC IRQ33 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT7_SHIFT)) & SYSCON_SMARTDMAINT_INT7_MASK) + +#define SYSCON_SMARTDMAINT_INT8_MASK (0x100U) +#define SYSCON_SMARTDMAINT_INT8_SHIFT (8U) +/*! INT8 - SmartDMA hijack NVIC IRQ34 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT8_SHIFT)) & SYSCON_SMARTDMAINT_INT8_MASK) + +#define SYSCON_SMARTDMAINT_INT9_MASK (0x200U) +#define SYSCON_SMARTDMAINT_INT9_SHIFT (9U) +/*! INT9 - SmartDMA hijack NVIC IRQ35 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT9_SHIFT)) & SYSCON_SMARTDMAINT_INT9_MASK) + +#define SYSCON_SMARTDMAINT_INT10_MASK (0x400U) +#define SYSCON_SMARTDMAINT_INT10_SHIFT (10U) +/*! INT10 - SmartDMA hijack NVIC IRQ36 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT10(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT10_SHIFT)) & SYSCON_SMARTDMAINT_INT10_MASK) + +#define SYSCON_SMARTDMAINT_INT11_MASK (0x800U) +#define SYSCON_SMARTDMAINT_INT11_SHIFT (11U) +/*! INT11 - SmartDMA hijack NVIC IRQ37 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT11(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT11_SHIFT)) & SYSCON_SMARTDMAINT_INT11_MASK) + +#define SYSCON_SMARTDMAINT_INT12_MASK (0x1000U) +#define SYSCON_SMARTDMAINT_INT12_SHIFT (12U) +/*! INT12 - SmartDMA hijack NVIC IRQ38 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT12(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT12_SHIFT)) & SYSCON_SMARTDMAINT_INT12_MASK) + +#define SYSCON_SMARTDMAINT_INT13_MASK (0x2000U) +#define SYSCON_SMARTDMAINT_INT13_SHIFT (13U) +/*! INT13 - SmartDMA hijack NVIC IRQ39 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT13(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT13_SHIFT)) & SYSCON_SMARTDMAINT_INT13_MASK) + +#define SYSCON_SMARTDMAINT_INT14_MASK (0x4000U) +#define SYSCON_SMARTDMAINT_INT14_SHIFT (14U) +/*! INT14 - SmartDMA hijack NVIC IRQ40 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT14(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT14_SHIFT)) & SYSCON_SMARTDMAINT_INT14_MASK) + +#define SYSCON_SMARTDMAINT_INT15_MASK (0x8000U) +#define SYSCON_SMARTDMAINT_INT15_SHIFT (15U) +/*! INT15 - SmartDMA hijack NVIC IRQ41 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT15(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT15_SHIFT)) & SYSCON_SMARTDMAINT_INT15_MASK) + +#define SYSCON_SMARTDMAINT_INT16_MASK (0x10000U) +#define SYSCON_SMARTDMAINT_INT16_SHIFT (16U) +/*! INT16 - SmartDMA hijack NVIC IRQ42 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT16(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT16_SHIFT)) & SYSCON_SMARTDMAINT_INT16_MASK) + +#define SYSCON_SMARTDMAINT_INT17_MASK (0x20000U) +#define SYSCON_SMARTDMAINT_INT17_SHIFT (17U) +/*! INT17 - SmartDMA hijack NVIC IRQ45 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT17(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT17_SHIFT)) & SYSCON_SMARTDMAINT_INT17_MASK) + +#define SYSCON_SMARTDMAINT_INT18_MASK (0x40000U) +#define SYSCON_SMARTDMAINT_INT18_SHIFT (18U) +/*! INT18 - SmartDMA hijack NVIC IRQ47 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT18(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT18_SHIFT)) & SYSCON_SMARTDMAINT_INT18_MASK) + +#define SYSCON_SMARTDMAINT_INT19_MASK (0x80000U) +#define SYSCON_SMARTDMAINT_INT19_SHIFT (19U) +/*! INT19 - SmartDMA hijack NVIC IRQ50 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT19(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT19_SHIFT)) & SYSCON_SMARTDMAINT_INT19_MASK) + +#define SYSCON_SMARTDMAINT_INT20_MASK (0x100000U) +#define SYSCON_SMARTDMAINT_INT20_SHIFT (20U) +/*! INT20 - SmartDMA hijack NVIC IRQ51 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT20(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT20_SHIFT)) & SYSCON_SMARTDMAINT_INT20_MASK) + +#define SYSCON_SMARTDMAINT_INT21_MASK (0x200000U) +#define SYSCON_SMARTDMAINT_INT21_SHIFT (21U) +/*! INT21 - SmartDMA hijack NVIC IRQ66 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT21(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT21_SHIFT)) & SYSCON_SMARTDMAINT_INT21_MASK) + +#define SYSCON_SMARTDMAINT_INT22_MASK (0x400000U) +#define SYSCON_SMARTDMAINT_INT22_SHIFT (22U) +/*! INT22 - SmartDMA hijack NVIC IRQ67 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT22(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT22_SHIFT)) & SYSCON_SMARTDMAINT_INT22_MASK) + +#define SYSCON_SMARTDMAINT_INT23_MASK (0x800000U) +#define SYSCON_SMARTDMAINT_INT23_SHIFT (23U) +/*! INT23 - SmartDMA hijack NVIC IRQ77 + * 0b0..Disable + * 0b1..Enable + */ +#define SYSCON_SMARTDMAINT_INT23(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SMARTDMAINT_INT23_SHIFT)) & SYSCON_SMARTDMAINT_INT23_MASK) +/*! @} */ + +/*! @name ADC1CLKSEL - ADC1 Clock Source Select */ +/*! @{ */ + +#define SYSCON_ADC1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADC1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the ADC1 clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO 12 MHz clock + * 0b100..Clk_in clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_ADC1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKSEL_SEL_SHIFT)) & SYSCON_ADC1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADC1CLKDIV - ADC1 Clock Divider */ +/*! @{ */ + +#define SYSCON_ADC1CLKDIV_DIV_MASK (0x7U) +#define SYSCON_ADC1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_ADC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_DIV_SHIFT)) & SYSCON_ADC1CLKDIV_DIV_MASK) + +#define SYSCON_ADC1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_ADC1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_ADC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_RESET_SHIFT)) & SYSCON_ADC1CLKDIV_RESET_MASK) + +#define SYSCON_ADC1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_ADC1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_ADC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_HALT_SHIFT)) & SYSCON_ADC1CLKDIV_HALT_MASK) + +#define SYSCON_ADC1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_ADC1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_ADC1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADC1CLKDIV_UNSTAB_SHIFT)) & SYSCON_ADC1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name RAM_INTERLEAVE - Control PKC RAM Interleave Access */ +/*! @{ */ + +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK (0x1U) +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT (0U) +/*! INTERLEAVE - Controls PKC RAM access for PKC RAM 0 and PKC RAM 1 + * 0b1..RAM access to PKC RAM 0 and PKC RAM 1 is interleaved. This setting is need for PKC L0 memory access. + * 0b0..RAM access to PKC RAM 0 and PKC RAM 1 is consecutive. + */ +#define SYSCON_RAM_INTERLEAVE_INTERLEAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_INTERLEAVE_INTERLEAVE_SHIFT)) & SYSCON_RAM_INTERLEAVE_INTERLEAVE_MASK) +/*! @} */ + +/*! @name PLLCLKDIVSEL - PLL Clock Divider Clock Selection */ +/*! @{ */ + +#define SYSCON_PLLCLKDIVSEL_SEL_MASK (0x7U) +#define SYSCON_PLLCLKDIVSEL_SEL_SHIFT (0U) +/*! SEL - Selects the PLL Clock Divider source clock + * 0b000..PLL0 clock + * 0b001..pll1_clk0 + * 0b010..No clock + * 0b011..No clock + * 0b100..No clock + * 0b101..No clock + * 0b110..No clock + * 0b111..No clock + */ +#define SYSCON_PLLCLKDIVSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLLCLKDIVSEL_SEL_SHIFT)) & SYSCON_PLLCLKDIVSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C0FCLKSEL - I3C0 Functional Clock Selection */ +/*! @{ */ + +#define SYSCON_I3C0FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_I3C0FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the I3C0 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..clk_1m clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_I3C0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKSEL_SEL_SHIFT)) & SYSCON_I3C0FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C0FCLKDIV - I3C0 Functional Clock FCLK Divider */ +/*! @{ */ + +#define SYSCON_I3C0FCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_I3C0FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_I3C0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_DIV_SHIFT)) & SYSCON_I3C0FCLKDIV_DIV_MASK) + +#define SYSCON_I3C0FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3C0FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_I3C0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_RESET_SHIFT)) & SYSCON_I3C0FCLKDIV_RESET_MASK) + +#define SYSCON_I3C0FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3C0FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_I3C0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_HALT_SHIFT)) & SYSCON_I3C0FCLKDIV_HALT_MASK) + +#define SYSCON_I3C0FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_I3C0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C0FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MICFILFCLKSEL - MICFIL Clock Selection */ +/*! @{ */ + +#define SYSCON_MICFILFCLKSEL_SEL_MASK (0xFU) +#define SYSCON_MICFILFCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the MICFIL clock + * 0b0000..FRO_12M clock + * 0b0001..PLL0 clock + * 0b0010..CLKIN clock + * 0b0011..FRO_HF clock + * 0b0100..PLL1_clk0 clock + * 0b0101..SAI0_MCLK clock + * 0b0110..USB PLL clock + * 0b0111..No clock + * 0b1000..SAI1_MCLK clock + * 0b1001..No clock + * 0b1010..No clock + * 0b1011..No clock + * 0b1100..No clock + * 0b1101..No clock + * 0b1110..No clock + * 0b1111..No clock + */ +#define SYSCON_MICFILFCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKSEL_SEL_SHIFT)) & SYSCON_MICFILFCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name MICFILFCLKDIV - MICFIL Clock Division */ +/*! @{ */ + +#define SYSCON_MICFILFCLKDIV_DIV_MASK (0x7U) +#define SYSCON_MICFILFCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_MICFILFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_DIV_SHIFT)) & SYSCON_MICFILFCLKDIV_DIV_MASK) + +#define SYSCON_MICFILFCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_MICFILFCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_MICFILFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_RESET_SHIFT)) & SYSCON_MICFILFCLKDIV_RESET_MASK) + +#define SYSCON_MICFILFCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_MICFILFCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_MICFILFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_HALT_SHIFT)) & SYSCON_MICFILFCLKDIV_HALT_MASK) + +#define SYSCON_MICFILFCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_MICFILFCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MICFILFCLKDIV_UNSTAB_SHIFT)) & SYSCON_MICFILFCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXIOCLKSEL - FLEXIO Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXIOCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXIOCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXIO clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..FRO_12M clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKSEL_SEL_SHIFT)) & SYSCON_FLEXIOCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXIOCLKDIV - FLEXIO Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXIOCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_DIV_SHIFT)) & SYSCON_FLEXIOCLKDIV_DIV_MASK) + +#define SYSCON_FLEXIOCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXIOCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_RESET_SHIFT)) & SYSCON_FLEXIOCLKDIV_RESET_MASK) + +#define SYSCON_FLEXIOCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXIOCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_HALT_SHIFT)) & SYSCON_FLEXIOCLKDIV_HALT_MASK) + +#define SYSCON_FLEXIOCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXIOCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXIOCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXIOCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXCAN0CLKSEL - FLEXCAN0 Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXCAN0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXCAN0 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..No clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXCAN0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXCAN0CLKDIV - FLEXCAN0 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCAN0CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_DIV_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_RESET_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_HALT_MASK) + +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCAN0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN0CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name FLEXCAN1CLKSEL - FLEXCAN1 Clock Selection */ +/*! @{ */ + +#define SYSCON_FLEXCAN1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the FLEXCAN1 clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..No clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_FLEXCAN1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKSEL_SEL_SHIFT)) & SYSCON_FLEXCAN1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FLEXCAN1CLKDIV - FLEXCAN1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCAN1CLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_DIV_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_DIV_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_RESET_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_RESET_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_HALT_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_HALT_MASK) + +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCAN1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCAN1CLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCAN1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name EWM0CLKSEL - EWM0 Clock Selection */ +/*! @{ */ + +#define SYSCON_EWM0CLKSEL_SEL_MASK (0x1U) +#define SYSCON_EWM0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the EWM0 clock + * 0b0..clk_16k[2] + * 0b1..xtal32k[2] + */ +#define SYSCON_EWM0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EWM0CLKSEL_SEL_SHIFT)) & SYSCON_EWM0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name WDT1CLKSEL - WDT1 Clock Selection */ +/*! @{ */ + +#define SYSCON_WDT1CLKSEL_SEL_MASK (0x3U) +#define SYSCON_WDT1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the WDT1 clock + * 0b00..FRO16K clock 2 + * 0b01..fro_hf_div clock + * 0b10..clk_1m clock + * 0b11..clk_1m clock + */ +#define SYSCON_WDT1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKSEL_SEL_SHIFT)) & SYSCON_WDT1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name WDT1CLKDIV - WDT1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_WDT1CLKDIV_DIV_MASK (0x3FU) +#define SYSCON_WDT1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_WDT1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_DIV_SHIFT)) & SYSCON_WDT1CLKDIV_DIV_MASK) + +#define SYSCON_WDT1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_WDT1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_WDT1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_RESET_SHIFT)) & SYSCON_WDT1CLKDIV_RESET_MASK) + +#define SYSCON_WDT1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_WDT1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_WDT1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_HALT_SHIFT)) & SYSCON_WDT1CLKDIV_HALT_MASK) + +#define SYSCON_WDT1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_WDT1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_WDT1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDT1CLKDIV_UNSTAB_SHIFT)) & SYSCON_WDT1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name OSTIMERCLKSEL - OSTIMER Clock Selection */ +/*! @{ */ + +#define SYSCON_OSTIMERCLKSEL_SEL_MASK (0x3U) +#define SYSCON_OSTIMERCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the OS Event Timer clock + * 0b00..clk_16k[2] + * 0b01..xtal32k[2] + * 0b10..clk_1m clock + * 0b11..No clock + */ +#define SYSCON_OSTIMERCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_OSTIMERCLKSEL_SEL_SHIFT)) & SYSCON_OSTIMERCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0FCLKSEL - CMP0 Function Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP0FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP0FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP0 function clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP0FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKSEL_SEL_SHIFT)) & SYSCON_CMP0FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0FCLKDIV - CMP0 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP0FCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP0FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP0FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_DIV_SHIFT)) & SYSCON_CMP0FCLKDIV_DIV_MASK) + +#define SYSCON_CMP0FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP0FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP0FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_RESET_SHIFT)) & SYSCON_CMP0FCLKDIV_RESET_MASK) + +#define SYSCON_CMP0FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP0FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP0FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_HALT_SHIFT)) & SYSCON_CMP0FCLKDIV_HALT_MASK) + +#define SYSCON_CMP0FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP0FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP0RRCLKSEL - CMP0 Round Robin Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP0RRCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP0RRCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP0 round robin clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP0RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP0RRCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP0RRCLKDIV - CMP0 Round Robin Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP0RRCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP0RRCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP0RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP0RRCLKDIV_DIV_MASK) + +#define SYSCON_CMP0RRCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP0RRCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP0RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP0RRCLKDIV_RESET_MASK) + +#define SYSCON_CMP0RRCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP0RRCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP0RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP0RRCLKDIV_HALT_MASK) + +#define SYSCON_CMP0RRCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP0RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP0RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP0RRCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP1FCLKSEL - CMP1 Function Clock Selection */ +/*! @{ */ + +#define SYSCON_CMP1FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP1FCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP1 function clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKSEL_SEL_SHIFT)) & SYSCON_CMP1FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP1FCLKDIV - CMP1 Function Clock Divider */ +/*! @{ */ + +#define SYSCON_CMP1FCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP1FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_DIV_SHIFT)) & SYSCON_CMP1FCLKDIV_DIV_MASK) + +#define SYSCON_CMP1FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP1FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_RESET_SHIFT)) & SYSCON_CMP1FCLKDIV_RESET_MASK) + +#define SYSCON_CMP1FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP1FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_HALT_SHIFT)) & SYSCON_CMP1FCLKDIV_HALT_MASK) + +#define SYSCON_CMP1FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CMP1RRCLKSEL - CMP1 Round Robin Clock Source Select */ +/*! @{ */ + +#define SYSCON_CMP1RRCLKSEL_SEL_MASK (0x7U) +#define SYSCON_CMP1RRCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the CMP1 round robin clock + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..FRO_HF clock + * 0b011..FRO_12M clock + * 0b100..CLKIN clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_CMP1RRCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKSEL_SEL_SHIFT)) & SYSCON_CMP1RRCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name CMP1RRCLKDIV - CMP1 Round Robin Clock Division */ +/*! @{ */ + +#define SYSCON_CMP1RRCLKDIV_DIV_MASK (0xFU) +#define SYSCON_CMP1RRCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_CMP1RRCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_DIV_SHIFT)) & SYSCON_CMP1RRCLKDIV_DIV_MASK) + +#define SYSCON_CMP1RRCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_CMP1RRCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_CMP1RRCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_RESET_SHIFT)) & SYSCON_CMP1RRCLKDIV_RESET_MASK) + +#define SYSCON_CMP1RRCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_CMP1RRCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_CMP1RRCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_HALT_SHIFT)) & SYSCON_CMP1RRCLKDIV_HALT_MASK) + +#define SYSCON_CMP1RRCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_CMP1RRCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CMP1RRCLKDIV_UNSTAB_SHIFT)) & SYSCON_CMP1RRCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CPUSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - CPU0 sleeping state + * 0b1..CPU is sleeping + * 0b0..CPU is not sleeping + */ +#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - CPU0 lockup state + * 0b1..CPU is in lockup + * 0b0..CPU is not in lockup + */ +#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name LPCAC_CTRL - LPCAC Control */ +/*! @{ */ + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) +/*! DIS_LPCAC - Disables/enables the cache function. + * 0b0..Enabled + * 0b1..Disabled + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) +/*! CLR_LPCAC - Clears the cache function. + * 0b0..Unclears the cache + * 0b1..Clears the cache + */ +#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) +/*! FRC_NO_ALLOC - Forces no allocation. + * 0b0..Forces allocation + * 0b1..Forces no allocation + */ +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) + +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK (0x8U) +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT (3U) +/*! PARITY_MISS_EN - Enables parity miss. + * 0b0..Disabled + * 0b1..Enables parity, miss on parity error + */ +#define SYSCON_LPCAC_CTRL_PARITY_MISS_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_MISS_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK) + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U) +/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer. + * 0b1..Disables write through buffer + * 0b0..Enables write through buffer + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U) +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U) +/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer. + * 0b1..Write buffer enabled when transaction is cacheable and bufferable + * 0b0..Write buffer enabled when transaction is bufferable. + */ +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK (0x40U) +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT (6U) +/*! PARITY_FAULT_EN - Enable parity error report. + * 0b1..Enables parity error report + * 0b0..Disables parity error report + */ +#define SYSCON_LPCAC_CTRL_PARITY_FAULT_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_SHIFT)) & SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U) +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U) +/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control + * 0b1..Enabled. + * 0b0..Disabled. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK) +/*! @} */ + +/*! @name FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV - LP_FLEXCOMM Clock Divider */ +/*! @{ */ + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_DIV_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_RESET_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_HALT_MASK) + +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_SHIFT)) & SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_UNSTAB_MASK) +/*! @} */ + +/* The count of SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV */ +#define SYSCON_FLEXCOMMXCLKDIV_FLEXCOMMCLKDIV_COUNT (8U) + +/*! @name UTICKCLKSEL - UTICK Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_UTICKCLKSEL_SEL_MASK (0x3U) +#define SYSCON_UTICKCLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b00..clk_in + * 0b01..xtal32k[2] + * 0b10..clk_1m clock + * 0b11..No clock + */ +#define SYSCON_UTICKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UTICKCLKSEL_SEL_SHIFT)) & SYSCON_UTICKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI0CLKSEL - SAI0 Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_SAI0CLKSEL_SEL_MASK (0x7U) +#define SYSCON_SAI0CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..PLL1_CLK0 clock + * 0b101..No clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_SAI0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKSEL_SEL_SHIFT)) & SYSCON_SAI0CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI1CLKSEL - SAI1 Function Clock Source Select */ +/*! @{ */ + +#define SYSCON_SAI1CLKSEL_SEL_MASK (0x7U) +#define SYSCON_SAI1CLKSEL_SEL_SHIFT (0U) +/*! SEL - Selects the clock source + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..PLL1_CLK0 clock + * 0b101..No clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_SAI1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKSEL_SEL_SHIFT)) & SYSCON_SAI1CLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SAI0CLKDIV - SAI0 Function Clock Division */ +/*! @{ */ + +#define SYSCON_SAI0CLKDIV_DIV_MASK (0x7U) +#define SYSCON_SAI0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SAI0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_DIV_SHIFT)) & SYSCON_SAI0CLKDIV_DIV_MASK) + +#define SYSCON_SAI0CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SAI0CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SAI0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_RESET_SHIFT)) & SYSCON_SAI0CLKDIV_RESET_MASK) + +#define SYSCON_SAI0CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SAI0CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SAI0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_HALT_SHIFT)) & SYSCON_SAI0CLKDIV_HALT_MASK) + +#define SYSCON_SAI0CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SAI0CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SAI0CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI0CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI0CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name SAI1CLKDIV - SAI1 Function Clock Division */ +/*! @{ */ + +#define SYSCON_SAI1CLKDIV_DIV_MASK (0x7U) +#define SYSCON_SAI1CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_SAI1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_DIV_SHIFT)) & SYSCON_SAI1CLKDIV_DIV_MASK) + +#define SYSCON_SAI1CLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SAI1CLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SAI1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_RESET_SHIFT)) & SYSCON_SAI1CLKDIV_RESET_MASK) + +#define SYSCON_SAI1CLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SAI1CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SAI1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_HALT_SHIFT)) & SYSCON_SAI1CLKDIV_HALT_MASK) + +#define SYSCON_SAI1CLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SAI1CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SAI1CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SAI1CLKDIV_UNSTAB_SHIFT)) & SYSCON_SAI1CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name KEY_RETAIN_CTRL - Key Retain Control */ +/*! @{ */ + +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK (0x1U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT (0U) +/*! KEY_RETAIN_VALID - Indicates if the PUF key has been retained in the VBAT domain and has not + * been reset or otherwise invalidated by software. + * 0b0..PUF key is not retained in VBAT domain. + * 0b1..PUF key is retained in VBAT domain. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_VALID_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK (0x2U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT (1U) +/*! KEY_RETAIN_DONE - Indicates the successful completion of the key_save or key_load routine. Once + * set, to clear the key_retain_done flag, both key_save and key_load should be cleared by + * software. + * 0b0..Key save / load sequence has not completed. + * 0b1..Key save / load sequence has completed. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_RETAIN_DONE_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK (0x10000U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT (16U) +/*! KEY_SAVE + * 0b0..Key save sequence is disabled. + * 0b1..Key save sequence is enabled. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_SAVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_SAVE_MASK) + +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK (0x20000U) +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT (17U) +/*! KEY_LOAD + * 0b0..Key load sequence is disabled. + * 0b1..Key load sequence is enabled. + */ +#define SYSCON_KEY_RETAIN_CTRL_KEY_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_SHIFT)) & SYSCON_KEY_RETAIN_CTRL_KEY_LOAD_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL - FRO 48MHz Reference Clock Control */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT (0U) +/*! GDET_REFCLK_EN - GDET reference clock enable bit + * 0b1..Enabled + * 0b0..Disabled. + */ +#define SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_GDET_REFCLK_EN_MASK) + +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT (1U) +/*! TRNG_REFCLK_EN - ELS TRNG reference clock enable bit + * 0b1..Enabled + * 0b0..Disabled. + */ +#define SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_SHIFT)) & SYSCON_REF_CLK_CTRL_TRNG_REFCLK_EN_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL_SET - FRO 48MHz Reference Clock Control Set */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT (0U) +/*! GDET_REFCLK_EN_SET - GDET reference clock enable set bit + * 0b1..Set to 1 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_GDET_REFCLK_EN_SET_MASK) + +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT (1U) +/*! TRNG_REFCLK_EN_SET - ELS TRNG reference clock enable set bit + * 0b1..Set to 1 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_SHIFT)) & SYSCON_REF_CLK_CTRL_SET_TRNG_REFCLK_EN_SET_MASK) +/*! @} */ + +/*! @name REF_CLK_CTRL_CLR - FRO 48MHz Reference Clock Control Clear */ +/*! @{ */ + +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK (0x1U) +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT (0U) +/*! GDET_REFCLK_EN_CLR - GDET reference clock enable clear bit + * 0b1..Set to 0 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_GDET_REFCLK_EN_CLR_MASK) + +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK (0x2U) +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT (1U) +/*! TRNG_REFCLK_EN_CLR - ELS TRNG reference clock enable clear bit + * 0b1..Set to 0 + * 0b0..No effect. + */ +#define SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_SHIFT)) & SYSCON_REF_CLK_CTRL_CLR_TRNG_REFCLK_EN_CLR_MASK) +/*! @} */ + +/*! @name GDETX_CTRL_GDET_CTRL - GDET Control Register */ +/*! @{ */ + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK (0x1U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT (0U) +/*! GDET_EVTCNT_CLR - Controls the GDET clean event counter + * 0b1..Clears event counter + * 0b0..Event counter not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_EVTCNT_CLR_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK (0x2U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT (1U) +/*! GDET_ERR_CLR - Clears GDET error status + * 0b1..Clears error status + * 0b0..Error status not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ERR_CLR_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK (0xCU) +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT (2U) +/*! GDET_ISO_SW - GDET isolation control + * 0b10..Isolation is enabled. When both GDET0_CTRL/GDET1_CTRL GDET_ISO_SW are "10", isolation_on is asserted. + * 0b00..Isolation is disabled + * 0b01..Isolation is disabled + * 0b11..Isolation is disabled + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_GDET_ISO_SW_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK (0xFF00U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT (8U) +/*! EVENT_CNT - Event count value */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CNT_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK (0x10000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT (16U) +/*! POS_SYNC - Positive glitch detected + * 0b1..Positive glitch detected + * 0b0..Positive glitch not detected + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_POS_SYNC_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK (0x20000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT (17U) +/*! NEG_SYNC - Negative glitch detected + * 0b1..Negative glitch detected + * 0b0..Negative glitch not detected + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_NEG_SYNC_MASK) + +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK (0x40000U) +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT (18U) +/*! EVENT_CLR_FLAG - Event counter cleared + * 0b1..Event counter cleared + * 0b0..Event counter not cleared + */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_SHIFT)) & SYSCON_GDETX_CTRL_GDET_CTRL_EVENT_CLR_FLAG_MASK) +/*! @} */ + +/* The count of SYSCON_GDETX_CTRL_GDET_CTRL */ +#define SYSCON_GDETX_CTRL_GDET_CTRL_COUNT (2U) + +/*! @name ELS_ASSET_PROT - ELS Asset Protection Register */ +/*! @{ */ + +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK (0x3U) +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT (0U) +/*! ASSET_PROTECTION - ELS asset protection. This field controls the asset protection port to the + * ELS module. Refer to the ELS chapter in the SRM for more details. + * 0b00..ELS asset is protected + * 0b10..ELS asset is protected + * 0b11..ELS asset is protected + * 0b01..ELS asset is not protected + */ +#define SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_SHIFT)) & SYSCON_ELS_ASSET_PROT_ASSET_PROTECTION_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL - ELS Lock Control */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - ELS Lock Control */ +#define SYSCON_ELS_LOCK_CTRL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_SHIFT)) & SYSCON_ELS_LOCK_CTRL_LOCK_CTRL_MASK) +/*! @} */ + +/*! @name ELS_LOCK_CTRL_DP - ELS Lock Control DP */ +/*! @{ */ + +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK (0x3U) +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT (0U) +/*! LOCK_CTRL_DP - Refer to ELS_LOCK_CTRL[1:0] */ +#define SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_SHIFT)) & SYSCON_ELS_LOCK_CTRL_DP_LOCK_CTRL_DP_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U) +/*! OTP_LC_STATE - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U) +/*! OTP_LC_STATE_DP - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK) +/*! @} */ + +/*! @name ELS_TEMPORAL_STATE - ELS Temporal State */ +/*! @{ */ + +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT (0U) +/*! TEMPORAL_STATE - Temporal state */ +#define SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_TEMPORAL_STATE_TEMPORAL_STATE_MASK) +/*! @} */ + +/*! @name ELS_KDF_MASK - Key Derivation Function Mask */ +/*! @{ */ + +#define SYSCON_ELS_KDF_MASK_KDF_MASK_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT (0U) +/*! KDF_MASK - Key derivation function mask */ +#define SYSCON_ELS_KDF_MASK_KDF_MASK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_KDF_MASK_KDF_MASK_SHIFT)) & SYSCON_ELS_KDF_MASK_KDF_MASK_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG0 - ELS AS Configuration */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT (0U) +/*! CFG_LC_STATE - LC state configuration bit */ +#define SYSCON_ELS_AS_CFG0_CFG_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LC_STATE_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LC_STATE_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK (0x200U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT (9U) +/*! CFG_LVD_CORE_RESET_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK (0x800U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT (11U) +/*! CFG_LVD_CORE_IRQ_ENABLED - When SPC CORE LVD analog detector are turned on, and CORE LVD IRQ are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_CORE_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK (0x1000U) +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT (12U) +/*! CFG_WDT0_ENABLED - When WatchDog Timer 0 is activated, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT0_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK (0x2000U) +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT (13U) +/*! CFG_CWDT0_ENABLED - When Code WatchDog Timer 0 is activated, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT0_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK (0x4000U) +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT (14U) +/*! CFG_ELS_GDET_ENABLED - When either GDET is enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ELS_GDET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK (0x8000U) +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT (15U) +/*! CFG_ANA_GDET_RESET_ENABLED - When SPC analog glitch detect reset is enabled, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK (0x10000U) +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT (16U) +/*! CFG_ANA_GDET_IRQ_ENABLED - When SPC analog glitch detect IRQ is enabled, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_ANA_GDET_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK (0x20000U) +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT (17U) +/*! CFG_TAMPER_DET_ENABLED - When tamper detector is enabled in TDET, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK (0x40000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT (18U) +/*! CFG_LVD_VSYS_RESET_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK (0x80000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT (19U) +/*! CFG_LVD_VDDIO_RESET_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK (0x100000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT (20U) +/*! CFG_LVD_VSYS_IRQ_ENABLED - When SPC VSYS LVD analog detector are turned on and VSYS LVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VSYS_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK (0x200000U) +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT (21U) +/*! CFG_LVD_VDDIO_IRQ_ENABLED - When SPC VDDIO LVD analog detector are turned on and VDDIO LVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LVD_VDDIO_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK (0x400000U) +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT (22U) +/*! CFG_WDT1_ENABLED - When WatchDog Timer 1 is activated, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_WDT1_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK (0x800000U) +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT (23U) +/*! CFG_CWDT1_ENABLED - When Code WatchDog Timer 1 is activated, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CWDT1_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK (0x1000000U) +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT (24U) +/*! CFG_TEMPTAMPER_DET_ENABLED - When temperature tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_TEMPTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK (0x2000000U) +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT (25U) +/*! CFG_VOLTAMPER_DET_ENABLED - When voltage tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_VOLTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK (0x4000000U) +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT (26U) +/*! CFG_LHTTAMPER_DET_ENABLED - When light tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_LHTTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK (0x8000000U) +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT (27U) +/*! CFG_CLKTAMPER_DET_ENABLED - When clk tamper detector is enabled in VBAT, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_CLKTAMPER_DET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK (0x10000000U) +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT (28U) +/*! CFG_QK_DISABLE_ENROLL - When QK PUF "qk_disable_enroll" input is driven 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_ENROLL_MASK) + +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK (0x20000000U) +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT (29U) +/*! CFG_QK_DISABLE_WRAP - When QK PUF "qk_disable_wrap" input is driven 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_SHIFT)) & SYSCON_ELS_AS_CFG0_CFG_QK_DISABLE_WRAP_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG1 - ELS AS Configuration1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK (0x2U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT (1U) +/*! CFG_SEC_DIS_STRICT_MODE - When CFG_SEC_ENA_SEC_CHK indicates state 0 or when DISABLE_STRICT_MODE + * bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB secure controller are equal to 01, this + * bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_STRICT_MODE_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK (0x4U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT (2U) +/*! CFG_SEC_DIS_VIOL_ABORT - When the DISABLE_VIOLATION_ABORT bits in MISC_CTRL_REG and + * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_DIS_VIOL_ABORT_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK (0x8U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT (3U) +/*! CFG_SEC_ENA_NS_PRIV_CHK - When the ENABLE_NS_PRIV_CHECK bits in MISC_CTRL_REG and + * MISC_CTRL_DP_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_NS_PRIV_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK (0x10U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT (4U) +/*! CFG_SEC_ENA_S_PRIV_CHK - When the ENABLE_S_PRIV_CHECK bits in MISC_CTRL_REG and MISC_CTRL_DP_REG + * on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_S_PRIV_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK (0x20U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT (5U) +/*! CFG_SEC_ENA_SEC_CHK - When the ENABLE_SECURE_CHECKING bits in MISC_CTRL_REG and MISC_CTRL_DP_REG + * on the AHB secure controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_ENA_SEC_CHK_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK (0x40U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT (6U) +/*! CFG_SEC_IDAU_ALLNS - When the IDAU_ALL_NS bits in MISC_CTRL_REG and MISC_CTRL_DP_REG on the AHB + * secure controller are equal to 01, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_IDAU_ALLNS_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK (0x100U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT (8U) +/*! CFG_SEC_LOCK_NS_MPU - When the LOCK_NS_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_MPU_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK (0x200U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT (9U) +/*! CFG_SEC_LOCK_NS_VTOR - When the LOCK_NS_VTOR bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_NS_VTOR_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK (0x400U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT (10U) +/*! CFG_SEC_LOCK_S_MPU - When the LOCK_S_MPU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_MPU_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK (0x800U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT (11U) +/*! CFG_SEC_LOCK_S_VTAIRCR - When the LOCK_S_VTAIRCR bits in CPU0_LOCK_REG on the AHB secure + * controller are not equal to 10, this bit indicates state 1 + */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_S_VTAIRCR_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK (0x1000U) +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT (12U) +/*! CFG_SEC_LOCK_SAU - When the LOCK_SAU bits in CPU0_LOCK_REG on the AHB secure controller are not equal to 10, this bit indicates state 1 */ +#define SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_SEC_LOCK_SAU_MASK) + +#define SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK (0x1FE000U) +#define SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT (13U) +/*! METAL_VERSION - metal version */ +#define SYSCON_ELS_AS_CFG1_METAL_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_METAL_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_METAL_VERSION_MASK) + +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK (0x1E00000U) +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT (21U) +/*! ROM_PATCH_VERSION - ROM patch version */ +#define SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_SHIFT)) & SYSCON_ELS_AS_CFG1_ROM_PATCH_VERSION_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK (0x4000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT (26U) +/*! CFG_HVD_CORE_RESET_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK (0x8000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT (27U) +/*! CFG_HVD_CORE_IRQ_ENABLED - When SPC CORE HVD analog detector are turned on, and CORE HVD IRQ are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_CORE_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK (0x10000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT (28U) +/*! CFG_HVD_VSYS_RESET_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK (0x20000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT (29U) +/*! CFG_HVD_VDDIO_RESET_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD reset are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_RESET_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK (0x40000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT (30U) +/*! CFG_HVD_VSYS_IRQ_ENABLED - When SPC VSYS HVD analog detector are turned on and VSYS HVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VSYS_IRQ_ENABLED_MASK) + +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK (0x80000000U) +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT (31U) +/*! CFG_HVD_VDDIO_IRQ_ENABLED - When SPC VDDIO HVD analog detector are turned on and VDDIO HVD irq are enabled, this bit indicates state 1. */ +#define SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_SHIFT)) & SYSCON_ELS_AS_CFG1_CFG_HVD_VDDIO_IRQ_ENABLED_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG2 - ELS AS Configuration2 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT (0U) +/*! CFG_ELS_CMD_EN - ELS configuration command enable bit */ +#define SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_SHIFT)) & SYSCON_ELS_AS_CFG2_CFG_ELS_CMD_EN_MASK) +/*! @} */ + +/*! @name ELS_AS_CFG3 - ELS AS Configuration3 */ +/*! @{ */ + +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK (0xFFFFFFFFU) +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT (0U) +/*! DEVICE_TYPE - Device type identification data */ +#define SYSCON_ELS_AS_CFG3_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_CFG3_DEVICE_TYPE_SHIFT)) & SYSCON_ELS_AS_CFG3_DEVICE_TYPE_MASK) +/*! @} */ + +/*! @name ELS_AS_ST0 - ELS AS State Register */ +/*! @{ */ + +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK (0xFU) +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT (0U) +/*! ST_TEMPORAL_STATE - TEMPORAL_STATE[3:0] in the ELS_TEMPORAL_STATE register reflects this register */ +#define SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_SHIFT)) & SYSCON_ELS_AS_ST0_ST_TEMPORAL_STATE_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK (0x10U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT (4U) +/*! ST_CPU0_DBGEN - When CPU0 (CM33) "deben" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_DBGEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK (0x20U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT (5U) +/*! ST_CPU0_NIDEN - When CPU0 (CM33) "niden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_NIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK (0x40U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT (6U) +/*! ST_CPU0_SPIDEN - When CPU0 (CM33) "spiden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK (0x80U) +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT (7U) +/*! ST_CPU0_SPNIDEN - When CPU0 (CM33) "spniden" input is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_SHIFT)) & SYSCON_ELS_AS_ST0_ST_CPU0_SPNIDEN_MASK) + +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK (0x400U) +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT (10U) +/*! ST_DAP_ENABLE_CPU0 - When DAP to AP0 for CPU0 (CM33) debug access is allowed, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_ST0_ST_DAP_ENABLE_CPU0_MASK) + +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK (0x4000U) +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT (14U) +/*! ST_ALLOW_TEST_ACCESS - When JTAG TAP access is allowed, this bit indicates state 1. */ +#define SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_SHIFT)) & SYSCON_ELS_AS_ST0_ST_ALLOW_TEST_ACCESS_MASK) + +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK (0x8000U) +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT (15U) +/*! ST_XO32K_FAILED - When XO32K oscillation fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_XO32K_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO32K_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK (0x10000U) +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT (16U) +/*! ST_XO40M_FAILED - When XO40M oscillation fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_XO40M_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_XO40M_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK (0x20000U) +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT (17U) +/*! ST_IFR_LOAD_FAILED - When IFR load fail flag is state 1, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_SHIFT)) & SYSCON_ELS_AS_ST0_ST_IFR_LOAD_FAILED_MASK) + +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK (0x3C0000U) +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT (18U) +/*! ST_GLITCH_DETECT_FLAG - GLITCH_DETECT_FLAG is state of 4-bit Glitch Ripple Counter output. */ +#define SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_SHIFT)) & SYSCON_ELS_AS_ST0_ST_GLITCH_DETECT_FLAG_MASK) +/*! @} */ + +/*! @name ELS_AS_ST1 - ELS AS State1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK (0xFU) +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT (0U) +/*! ST_QK_PUF_SCORE - These register bits indicate the state of "qk_puf_score[3:0]" outputs from QK PUF block */ +#define SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_PUF_SCORE_MASK) + +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK (0x10U) +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT (4U) +/*! ST_QK_ZEROIZED - This register bit indicates the state of "qk_zeroized" output from QK PUF block */ +#define SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_SHIFT)) & SYSCON_ELS_AS_ST1_ST_QK_ZEROIZED_MASK) + +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK (0x20U) +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT (5U) +/*! ST_MAIN_CLK_IS_EXT - When MAIN_CLK is running from external clock source either XO32M, XO32K or GPIO CLKIN, this bit indicates state 1 */ +#define SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_MAIN_CLK_IS_EXT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK (0xC0U) +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT (6U) +/*! ST_DCDC_VOUT - VOUT[1:0] setting on DCDC0 register in SPC block will reflect to this register. Default is 1.0V */ +#define SYSCON_ELS_AS_ST1_ST_DCDC_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_VOUT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK (0x300U) +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT (8U) +/*! ST_DCDC_DS - DCDC drive strength setting. Default is normal drive. */ +#define SYSCON_ELS_AS_ST1_ST_DCDC_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_DCDC_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_DCDC_DS_MASK) + +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK (0xC00U) +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT (10U) +/*! ST_BOOT_MODE - ISP pin status during boot. By default ISP pin is pulled up. If want to enter ISP + * mode during boot, ISP pin should be pull down when out of reset. + */ +#define SYSCON_ELS_AS_ST1_ST_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_MODE_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_MODE_MASK) + +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK (0xF000U) +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT (12U) +/*! ST_BOOT_RETRY_CNT - BOOT_RETRY_CNT[3:0] in the ELS_BOOT_RETRY_CNT register reflects this register */ +#define SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_BOOT_RETRY_CNT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK (0x30000U) +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT (16U) +/*! ST_LDO_CORE_VOUT - VOUT[1:0] setting on LDO Core register in SPC block will reflect to this register. Default is 1.0V */ +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_VOUT_MASK) + +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK (0xC0000U) +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT (18U) +/*! ST_LDO_CORE_DS - LDO_CORE drive strength setting. Default is normal drive. */ +#define SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_SHIFT)) & SYSCON_ELS_AS_ST1_ST_LDO_CORE_DS_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG0 - Boot state captured during boot: Main ROM log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK (0xFU) +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT (0U) +/*! BOOT_IMAGE - Boot image source used during this boot. + * 0b0000..Internal flash image 0 + * 0b0001..Internal flash image 1 + * 0b0010..FlexSPI flash image 0 + * 0b0011..FlexSPI flash image 1 + * 0b0100..Recovery SPI flash image + * 0b0101..Serial boot image (write-memory and execute ISP command used) + * 0b0110..Receive SB3 containing SB_JUMP command is used. + * 0b0111..Customer SBL/recovery image (Bank1 IFR0). + * 0b1000..NXP MAD recovery image (Bank1 IFR0). + * 0b1001..NXP ROM extension (NMPA - Bank0 IFR0). + * 0b1010..Reserved. + * 0b1011..Reserved. + * 0b1100..Reserved. + * 0b1101..Reserved. + * 0b1110..Reserved. + * 0b1111..Reserved. + */ +#define SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_BOOT_IMAGE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK (0x10U) +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT (4U) +/*! CMAC - CMAC verify is used instead of ECDSA verify on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CMAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CMAC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CMAC_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK (0x40U) +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT (6U) +/*! ECDSA - ECDSA P-384 verification is done on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ECDSA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ECDSA_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ECDSA_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK (0x80U) +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT (7U) +/*! OFF_CHIP - Off-chip Prince is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_OFF_CHIP_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK (0x100U) +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT (8U) +/*! ON_CHIP - On-chip Prince is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ON_CHIP_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK (0x200U) +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT (9U) +/*! CDI_CSR - CDI based device keys are derived for CSR harvesting on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_CSR_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK (0x400U) +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT (10U) +/*! CDI_DICE - CDI per DICE specification is computed on this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_CDI_DICE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK (0x800U) +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT (11U) +/*! TRUSTZONE - TrustZone preset data is loaded during this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_TRUSTZONE_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK (0x1000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT (12U) +/*! DEBUG_AUTH - Debug authentication done in this session prior to boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEBUG_AUTH_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK (0x2000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT (13U) +/*! ITRC - ITRC zeroize event is handled in this session of boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ITRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ITRC_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ITRC_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK (0x4000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT (14U) +/*! DIG_GDET - Digital glitch detector is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DIG_GDET_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK (0x8000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT (15U) +/*! ANA_GDET - Analog glitch detector is enabled during boot. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ANA_GDET_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK (0x10000U) +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT (16U) +/*! DEEP_PD - Boot from deep-power down state. */ +#define SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_DEEP_PD_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK (0xF000000U) +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT (24U) +/*! LOW_POWER - Last low-power mode value. ROM copies SPC_LP_MODE field from SPC->SC[7:4]. */ +#define SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_LOW_POWER_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK (0x80000000U) +#define SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT (31U) +/*! ISP - ISP pin state at boot time. ROM copies CMC->MR0[0]. */ +#define SYSCON_ELS_AS_BOOT_LOG0_ISP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG0_ISP_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG0_ISP_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG1 - Boot state captured during boot: Library log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK (0x3U) +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT (0U) +/*! RoTK - RoTK index used for this boot. */ +#define SYSCON_ELS_AS_BOOT_LOG1_RoTK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_RoTK_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_RoTK_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK (0x3FCU) +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT (2U) +/*! FIPS - FIPS self-test is executed and PASS during this boot. When a bit is set, means self-test + * is executed and it FAILS. When a bit is clear, means corresponding self-test is executed and + * PASS or it is not executed. + */ +#define SYSCON_ELS_AS_BOOT_LOG1_FIPS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_FIPS_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_FIPS_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK (0xC00U) +#define SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT (10U) +/*! SB3 - SB3 type (valid after nboot_sb3_load_manifest()). + * 0b00..customer fw load/update file. + * 0b01..NXP Provisioning FW. + * 0b10..ELS signed OEM Provisioning FW. + */ +#define SYSCON_ELS_AS_BOOT_LOG1_SB3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG1_SB3_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG1_SB3_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG2 - Boot state captured during boot: Hardware status signals log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK (0x3FU) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT (0U) +/*! CMC_SRS0 - CMC->SRS[5:0] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS0_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK (0xC0U) +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT (6U) +/*! VBAT_STATUS0 - VBAT->STATUSA[1:0] | ~VBAT->STATUSB[1:0] */ +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS0_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK (0x1FF00U) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT (8U) +/*! CMC_SRS1 - CMC->SRS[16:8] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS1_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK (0xFC0000U) +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT (18U) +/*! VBAT_STATUS1 - VBAT->STATUSA[11:6] | ~VBAT->STATUSB[11:6] */ +#define SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_VBAT_STATUS1_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK (0xFF000000U) +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT (24U) +/*! CMC_SRS2 - CMC->SRS[31:24] */ +#define SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG2_CMC_SRS2_MASK) +/*! @} */ + +/*! @name ELS_AS_BOOT_LOG3 - Boot state captured during boot: Security log */ +/*! @{ */ + +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK (0xFFU) +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT (0U) +/*! ERR_AUTH_FAIL_COUNT - CFPA->ERR_AUTH_FAIL_COUNT[7:0] */ +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_AUTH_FAIL_COUNT_MASK) + +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK (0xFF00U) +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT (8U) +/*! ERR_ITRC_COUNT - CFPA->ERR_ITRC_COUNT[7:0] */ +#define SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_SHIFT)) & SYSCON_ELS_AS_BOOT_LOG3_ERR_ITRC_COUNT_MASK) +/*! @} */ + +/*! @name ELS_AS_FLAG0 - ELS AS Flag0 */ +/*! @{ */ + +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK (0x1U) +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT (0U) +/*! FLAG_AP_ENABLE_CPU0 - This flag bit is set as 1 when DAP enables AP0 for CPU0 (CM33) debug + * access. The register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_AP_ENABLE_CPU0_MASK) + +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK (0x8U) +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT (3U) +/*! EFUSE_ATTACK_DETECT - OTPC can output attack_detect signal when it detects attack when load + * shadow registers. The output will be cleared by reset. ELS_AS_FLAG is reset by PoR, so the status + * can be recorded. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_SHIFT)) & SYSCON_ELS_AS_FLAG0_EFUSE_ATTACK_DETECT_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK (0x20U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT (5U) +/*! FLAG_LVD_CORE_OCCURED - This flag register is set 1 when VDD_CORE LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_CORE_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK (0x100U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT (8U) +/*! FLAG_WDT0_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 reset is enabled and + * reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK (0x200U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT (9U) +/*! FLAG_CWDT0_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 reset is enabled + * and reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK (0x400U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT (10U) +/*! FLAG_WDT0_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 0 IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT0_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK (0x800U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT (11U) +/*! FLAG_CWDT0_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 0 IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT0_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK (0x1000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT (12U) +/*! FLAG_QK_ERROR - This flag bit is set as 1 when QK_ERROR is flagged from QK PUF block. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_QK_ERROR_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK (0x2000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT (13U) +/*! FLAG_ELS_GLITCH_DETECTED - This flag bit is set as 1 when GDET error is flagged. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ELS_GLITCH_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK (0x4000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT (14U) +/*! FLAG_ANA_GLITCH_DETECTED - This flag bit is set as 1 when ANALOG GDET error is flagged in SYSCON + * block. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_ANA_GLITCH_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK (0x8000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT (15U) +/*! FLAG_TAMPER_EVENT_DETECTED - This flag bit is set as 1 when tamper event is flagged from TDET. + * This register is cleared 0 by AO domain POR or by PMC reset event, if tamper detection event is + * cleared by software. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TAMPER_EVENT_DETECTED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK (0x10000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT (16U) +/*! FLAG_FLASH_ECC_INVALID - This flag bit is set as 1 when FLASH controller indicates ECC error. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_FLASH_ECC_INVALID_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK (0x20000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT (17U) +/*! FLAG_SEC_VIOL_IRQ_OCURRED - This flag bit is set as 1 when security violation is indicated from FLASH sub-system or AHB bus matrix. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_SEC_VIOL_IRQ_OCURRED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK (0x40000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT (18U) +/*! FLAG_CPU0_NS_C_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure code + * transactions. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_C_ACC_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK (0x80000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT (19U) +/*! FLAG_CPU0_NS_D_ACC_OCCURED - This flag bit is set as 1 when CPU0 (CM33) makes non-secure data + * transactions. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CPU0_NS_D_ACC_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK (0x100000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT (20U) +/*! FLAG_LVD_VSYS_OCCURED - This flag register is set 1 when VDD_SYS LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VSYS_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK (0x200000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT (21U) +/*! FLAG_LVD_VDDIO_OCCURED - This flag register is set 1 when VDD LVD event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LVD_VDDIO_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK (0x400000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT (22U) +/*! FLAG_WDT1_RESET_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 reset is enabled and + * reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK (0x800000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT (23U) +/*! FLAG_CWDT1_RESET_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 reset is enabled + * and reset event is triggered. This register is cleared 0 by AO domain POR. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_RESET_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK (0x1000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT (24U) +/*! FLAG_WDT1_IRQ_OCCURED - This flag bit is set as 1 when WatchDog Timer 1 IRQ is enabled and IRQ + * event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_WDT1_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK (0x2000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT (25U) +/*! FLAG_CWDT1_IRQ_OCCURED - This flag bit is set as 1 when Code WatchDog Timer 1 IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CWDT1_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK (0x4000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT (26U) +/*! FLAG_TEMPTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when temperature temper IRQ is + * enabled and IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_TEMPTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK (0x8000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT (27U) +/*! FLAG_VOLTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when voltage temper IRQ is enabled + * and IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_VOLTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK (0x10000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT (28U) +/*! FLAG_LHTTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when light temper IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_LHTTAMPER_DET_IRQ_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK (0x20000000U) +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT (29U) +/*! FLAG_CLKTAMPER_DET_IRQ_OCCURED - This flag bit is set as 1 when clock temper IRQ is enabled and + * IRQ event is triggered. This register is cleared 0 by PMC reset event. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG0_FLAG_CLKTAMPER_DET_IRQ_OCCURED_MASK) +/*! @} */ + +/*! @name ELS_AS_FLAG1 - ELS AS Flag1 */ +/*! @{ */ + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK (0x20000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT (29U) +/*! FLAG_HVD_CORE_OCCURED - This flag bit is set as 1 when HVD from VDD_CORE power domain is triggered. + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_CORE_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK (0x40000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT (30U) +/*! FLAG_HVD_VSYS_OCCURED - This flag bit is set as 1 when HVD from VDD_SYS power domain is triggered + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VSYS_OCCURED_MASK) + +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK (0x80000000U) +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT (31U) +/*! FLAG_HVD_VDDIO_OCCURED - This flag bit is set as 1 when HVD from VDD power domain is triggered + * 0b1..Triggered + * 0b0..Not Triggered + */ +#define SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_SHIFT)) & SYSCON_ELS_AS_FLAG1_FLAG_HVD_VDDIO_OCCURED_MASK) +/*! @} */ + +/*! @name CLOCK_CTRL - Clock Control */ +/*! @{ */ + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK (0x2U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT (1U) +/*! CLKIN_ENA_FM_USBH_LPT - Enables the clk_in clock for the Frequency Measurement, USB HS and LPTMR0/1 modules. + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK (0x4U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT (2U) +/*! FRO1MHZ_ENA - Enables the FRO_1MHz clock for RTC module and for UTICK + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK (0x8U) +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT (3U) +/*! FRO12MHZ_ENA - Enables the FRO_12MHz clock for the Flash, LPTMR0/1, and Frequency Measurement modules + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO12MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK (0x10U) +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT (4U) +/*! FRO_HF_ENA - Enables FRO HF clock for the Frequency Measure module + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO_HF_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) +#define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) +/*! CLKIN_ENA - Enables clk_in clock for MICFIL, CAN0/1, I3C0/1, SAI0/1, clkout. + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) +/*! FRO1MHZ_CLK_ENA - Enables FRO_1MHz clock for clock muxing in clock gen + * 0b1..Clock is enabled + * 0b0..Clock is not enabled + */ +#define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) +/*! @} */ + +/*! @name I3C1FCLKSEL - I3C1 Functional Clock Selection */ +/*! @{ */ + +#define SYSCON_I3C1FCLKSEL_SEL_MASK (0x7U) +#define SYSCON_I3C1FCLKSEL_SEL_SHIFT (0U) +/*! SEL - I3C1 clock select + * 0b000..No clock + * 0b001..PLL0 clock + * 0b010..CLKIN clock + * 0b011..FRO_HF clock + * 0b100..clk_1m clock + * 0b101..PLL1_clk0 clock + * 0b110..USB PLL clock + * 0b111..No clock + */ +#define SYSCON_I3C1FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKSEL_SEL_SHIFT)) & SYSCON_I3C1FCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name I3C1FCLKDIV - I3C1 Functional Clock FCLK Divider */ +/*! @{ */ + +#define SYSCON_I3C1FCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_I3C1FCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_I3C1FCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_DIV_SHIFT)) & SYSCON_I3C1FCLKDIV_DIV_MASK) + +#define SYSCON_I3C1FCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_I3C1FCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_I3C1FCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_RESET_SHIFT)) & SYSCON_I3C1FCLKDIV_RESET_MASK) + +#define SYSCON_I3C1FCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_I3C1FCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_I3C1FCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_HALT_SHIFT)) & SYSCON_I3C1FCLKDIV_HALT_MASK) + +#define SYSCON_I3C1FCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_I3C1FCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I3C1FCLKDIV_UNSTAB_SHIFT)) & SYSCON_I3C1FCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray code_gray[31:0] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT (0U) +/*! code_gray_31_0 - Gray code [31:0] */ +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK) +/*! @} */ + +/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray code_gray[41:32] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK (0x3FFU) +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT (0U) +/*! code_gray_41_32 - Gray code [41:32] */ +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK) +/*! @} */ + +/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT (0U) +/*! code_bin_31_0 - Binary code [31:0] */ +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK) +/*! @} */ + +/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK (0x3FFU) +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT (0U) +/*! code_bin_41_32 - Binary code [41:32] */ +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDE - Control Automatic Clock Gating */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK (0x4U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT (2U) +/*! RAMB_CTRL - Controls automatic clock gating for the RAMB Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMB_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK (0x8U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT (3U) +/*! RAMC_CTRL - Controls automatic clock gating for the RAMC Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMC_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK (0x10U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT (4U) +/*! RAMD_CTRL - Controls automatic clock gating for the RAMD Controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMD_CTRL_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK (0x20U) +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT (5U) +/*! RAME_CTRL - Controls automatic clock gating for the RAMD Controller. + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAME_CTRL_MASK) +/*! @} */ + +/*! @name AUTOCLKGATEOVERRIDEC - Control Automatic Clock Gating C */ +/*! @{ */ + +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK (0x40000000U) +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT (30U) +/*! RAMX - Controls automatic clock gating of the RAMX controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMX_MASK) + +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK (0x80000000U) +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT (31U) +/*! RAMA - Controls automatic clock gating of the RAMA controller + * 0b1..Automatic clock gating is overridden (Automatic clock gating is disabled). + * 0b0..Automatic clock gating is not overridden + */ +#define SYSCON_AUTOCLKGATEOVERRIDEC_RAMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDEC_RAMA_MASK) +/*! @} */ + +/*! @name PWM0SUBCTL - PWM0 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM0 SUB Clock0 */ +#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM0 SUB Clock1 */ +#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM0 SUB Clock2 */ +#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM0 SUB Clock3 */ +#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM0 submodule 0 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM0 submodule 1 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM0 submodule 2 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM0SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM0 submodule 3 DMA compare value done mask */ +#define SYSCON_PWM0SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM0SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name PWM1SUBCTL - PWM1 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM1 SUB Clock0 */ +#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM1 SUB Clock1 */ +#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM1 SUB Clock2 */ +#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM1 SUB Clock3 */ +#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM0_MASK (0x1000U) +#define SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT (12U) +/*! DMAVALM0 - PWM1 submodule 0 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM0_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM0_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM1_MASK (0x2000U) +#define SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT (13U) +/*! DMAVALM1 - PWM1 submodule 1 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM1_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM1_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM2_MASK (0x4000U) +#define SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT (14U) +/*! DMAVALM2 - PWM1 submodule 2 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM2_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM2_MASK) + +#define SYSCON_PWM1SUBCTL_DMAVALM3_MASK (0x8000U) +#define SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT (15U) +/*! DMAVALM3 - PWM1 submodule 3 DMA compare value done mask */ +#define SYSCON_PWM1SUBCTL_DMAVALM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_DMAVALM3_SHIFT)) & SYSCON_PWM1SUBCTL_DMAVALM3_MASK) +/*! @} */ + +/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */ +/*! @{ */ + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) +/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) +/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) +/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) +/*! CTIMER3_CLK_EN - Enables the CTIMER3 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) +/*! CTIMER4_CLK_EN - Enables the CTIMER4 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) +/*! @} */ + +/*! @name ECC_ENABLE_CTRL - RAM ECC Enable Control */ +/*! @{ */ + +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK (0x1U) +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT (0U) +/*! RAMA_ECC_ENABLE - RAMA ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMA_ECC_ENABLE_MASK) + +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK (0x2U) +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT (1U) +/*! RAMB_RAMX_ECC_ENABLE - RAMB and RAMX ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMB_RAMX_ECC_ENABLE_MASK) + +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK (0x4U) +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT (2U) +/*! RAMD_RAMC_ECC_ENABLE - RAMD and RAMC ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_SHIFT)) & SYSCON_ECC_ENABLE_CTRL_RAMD_RAMC_ECC_ENABLE_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control Write Access to Security */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Controls write access to the security registers + * 0b1010..Enables write access to all registers + * 0b0000..Any other value than b1010: disables write access to all registers + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex Debug Features Control */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 secure privileged invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 secure privileged non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU - CPU0 Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678 + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5. + */ +#define SYSCON_SWD_ACCESS_CPU_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU_SEC_CODE_MASK) +/*! @} */ + +/* The count of SYSCON_SWD_ACCESS_CPU */ +#define SYSCON_SWD_ACCESS_CPU_COUNT (1U) + +/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to the application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name JTAG_ID - JTAG Chip ID */ +/*! @{ */ + +#define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U) +/*! JTAG_ID - Indicates the device ID */ +#define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK) +/*! @} */ + +/*! @name DEVICE_TYPE - Device Type */ +/*! @{ */ + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT (0U) +/*! DEVICE_TYPE - Indicates DEVICE TYPE. */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. */ +#define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) +/*! @} */ + +/*! @name DIEID - Chip Revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_MINOR_REVISION_MASK (0xFU) +#define SYSCON_DIEID_MINOR_REVISION_SHIFT (0U) +/*! MINOR_REVISION - Chip minor revision */ +#define SYSCON_DIEID_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK) + +#define SYSCON_DIEID_MAJOR_REVISION_MASK (0xF0U) +#define SYSCON_DIEID_MAJOR_REVISION_SHIFT (4U) +/*! MAJOR_REVISION - Chip major revision */ +#define SYSCON_DIEID_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF00U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (8U) +/*! MCO_NUM_IN_DIE_ID - Chip number */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x50000000u) + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE_NS (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0_NS ((SYSCON_Type *)SYSCON0_BASE_NS) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS_NS { SYSCON0_BASE_NS } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS_NS { SYSCON0_NS } +#else + /** Peripheral SYSCON0 base address */ + #define SYSCON0_BASE (0x40000000u) + /** Peripheral SYSCON0 base pointer */ + #define SYSCON0 ((SYSCON_Type *)SYSCON0_BASE) + /** Array initializer of SYSCON peripheral base addresses */ + #define SYSCON_BASE_ADDRS { SYSCON0_BASE } + /** Array initializer of SYSCON peripheral base pointers */ + #define SYSCON_BASE_PTRS { SYSCON0 } +#endif +/* Backward compatibility */ +#define SYSCON SYSCON0 + + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSPM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSPM_Peripheral_Access_Layer SYSPM Peripheral Access Layer + * @{ + */ + +/** SYSPM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x30 */ + __IO uint32_t PMCR; /**< Performance Monitor Control, array offset: 0x0, array step: 0x30 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x18, array step: index*0x30, index2*0x8 */ + __I uint8_t HI; /**< Performance Monitor Event Counter, array offset: 0x18, array step: index*0x30, index2*0x8 */ + uint8_t RESERVED_0[3]; + __I uint32_t LO; /**< Performance Monitor Event Counter, array offset: 0x1C, array step: index*0x30, index2*0x8 */ + } PMECTR[3]; + } PMCR[1]; +} SYSPM_Type; + +/* ---------------------------------------------------------------------------- + -- SYSPM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSPM_Register_Masks SYSPM Register Masks + * @{ + */ + +/*! @name PMCR - Performance Monitor Control */ +/*! @{ */ + +#define SYSPM_PMCR_MENB_MASK (0x1U) +#define SYSPM_PMCR_MENB_SHIFT (0U) +/*! MENB - Module Is Enabled + * 0b0..Disabled + * 0b1..Enabled + */ +#define SYSPM_PMCR_MENB(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_MENB_SHIFT)) & SYSPM_PMCR_MENB_MASK) + +#define SYSPM_PMCR_SSC_MASK (0xEU) +#define SYSPM_PMCR_SSC_SHIFT (1U) +/*! SSC - Start and Stop Control + * 0b000..Idle or no-op + * 0b001..Local stop + * 0b010, 0b011..Local start + * 0b100.. + * 0b101.. + * 0b110, 0b111.. + */ +#define SYSPM_PMCR_SSC(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SSC_SHIFT)) & SYSPM_PMCR_SSC_MASK) + +#define SYSPM_PMCR_CMODE_MASK (0x30U) +#define SYSPM_PMCR_CMODE_SHIFT (4U) +/*! CMODE - Count Mode + * 0b00..Counted in both User and Privileged modes + * 0b01.. + * 0b10..Counted only in User mode + * 0b11..Counted only in Privileged mode + */ +#define SYSPM_PMCR_CMODE(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_CMODE_SHIFT)) & SYSPM_PMCR_CMODE_MASK) + +#define SYSPM_PMCR_RECTR1_MASK (0x100U) +#define SYSPM_PMCR_RECTR1_SHIFT (8U) +/*! RECTR1 - Reset Event Counter 1 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR1_SHIFT)) & SYSPM_PMCR_RECTR1_MASK) + +#define SYSPM_PMCR_RECTR2_MASK (0x200U) +#define SYSPM_PMCR_RECTR2_SHIFT (9U) +/*! RECTR2 - Reset Event Counter 2 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR2_SHIFT)) & SYSPM_PMCR_RECTR2_MASK) + +#define SYSPM_PMCR_RECTR3_MASK (0x400U) +#define SYSPM_PMCR_RECTR3_SHIFT (10U) +/*! RECTR3 - Reset Event Counter 3 + * 0b0..Run normally + * 0b1..Reset + */ +#define SYSPM_PMCR_RECTR3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_RECTR3_SHIFT)) & SYSPM_PMCR_RECTR3_MASK) + +#define SYSPM_PMCR_SELEVT1_MASK (0x3F800U) +#define SYSPM_PMCR_SELEVT1_SHIFT (11U) +/*! SELEVT1 - Select Event 1 */ +#define SYSPM_PMCR_SELEVT1(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT1_SHIFT)) & SYSPM_PMCR_SELEVT1_MASK) + +#define SYSPM_PMCR_SELEVT2_MASK (0x1FC0000U) +#define SYSPM_PMCR_SELEVT2_SHIFT (18U) +/*! SELEVT2 - Select Event 2 */ +#define SYSPM_PMCR_SELEVT2(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT2_SHIFT)) & SYSPM_PMCR_SELEVT2_MASK) + +#define SYSPM_PMCR_SELEVT3_MASK (0xFE000000U) +#define SYSPM_PMCR_SELEVT3_SHIFT (25U) +/*! SELEVT3 - Select Event 3 */ +#define SYSPM_PMCR_SELEVT3(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_SELEVT3_SHIFT)) & SYSPM_PMCR_SELEVT3_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR */ +#define SYSPM_PMCR_COUNT (1U) + +/*! @name PMCR_PMECTR_HI - Performance Monitor Event Counter */ +/*! @{ */ + +#define SYSPM_PMCR_PMECTR_HI_ECTR_MASK (0xFFU) +#define SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT (0U) +/*! ECTR - Event Counter */ +#define SYSPM_PMCR_PMECTR_HI_ECTR(x) (((uint8_t)(((uint8_t)(x)) << SYSPM_PMCR_PMECTR_HI_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_HI_ECTR_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR_PMECTR_HI */ +#define SYSPM_PMCR_PMECTR_HI_COUNT (1U) + +/* The count of SYSPM_PMCR_PMECTR_HI */ +#define SYSPM_PMCR_PMECTR_HI_COUNT2 (3U) + +/*! @name PMCR_PMECTR_LO - Performance Monitor Event Counter */ +/*! @{ */ + +#define SYSPM_PMCR_PMECTR_LO_ECTR_MASK (0xFFFFFFFFU) +#define SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT (0U) +/*! ECTR - Event Counter */ +#define SYSPM_PMCR_PMECTR_LO_ECTR(x) (((uint32_t)(((uint32_t)(x)) << SYSPM_PMCR_PMECTR_LO_ECTR_SHIFT)) & SYSPM_PMCR_PMECTR_LO_ECTR_MASK) +/*! @} */ + +/* The count of SYSPM_PMCR_PMECTR_LO */ +#define SYSPM_PMCR_PMECTR_LO_COUNT (1U) + +/* The count of SYSPM_PMCR_PMECTR_LO */ +#define SYSPM_PMCR_PMECTR_LO_COUNT2 (3U) + + +/*! + * @} + */ /* end of group SYSPM_Register_Masks */ + + +/* SYSPM - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x500C1000u) + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE_NS (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0_NS ((SYSPM_Type *)CMX_PERFMON0_BASE_NS) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0 } + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS_NS { CMX_PERFMON0_BASE_NS } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS_NS { CMX_PERFMON0_NS } +#else + /** Peripheral CMX_PERFMON0 base address */ + #define CMX_PERFMON0_BASE (0x400C1000u) + /** Peripheral CMX_PERFMON0 base pointer */ + #define CMX_PERFMON0 ((SYSPM_Type *)CMX_PERFMON0_BASE) + /** Array initializer of SYSPM peripheral base addresses */ + #define SYSPM_BASE_ADDRS { CMX_PERFMON0_BASE } + /** Array initializer of SYSPM peripheral base pointers */ + #define SYSPM_BASE_PTRS { CMX_PERFMON0 } +#endif + +/*! + * @} + */ /* end of group SYSPM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer + * @{ + */ + +/** TRDC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1CC */ + __IO uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x14, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x18, array step: 0x1CC */ + __O uint32_t MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1C, array step: 0x1CC */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1CC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_0[224]; + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x140, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_1[56]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1A0, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1CC, index2*0x4 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[1]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x1C8, array step: index*0x1CC, index2*0x4 */ + } MBC_INDEX[1]; +} TRDC_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Register_Masks TRDC Register Masks + * @{ + */ + +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_INDEX - MBC NonSecure Enable Block Index */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK (0x3CU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT (2U) +/*! WNDX - Word index into the block NSE bitmap. It selects the BLK_NSE_Wn register, where WNDX determines the value of n. */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_WNDX_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT (8U) +/*! MEM_SEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_MEM_SEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Selects NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_DID_SEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT (31U) +/*! AI - Auto Increment + * 0b0..No effect. + * 0b1..Add 1 to the WNDX field after the register write. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_AI_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_INDEX_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_SET - MBC NonSecure Enable Block Set */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT (0U) +/*! W1SET - Write-1 Set */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_SET_W1SET_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_SET */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_SET_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR - MBC NonSecure Enable Block Clear */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK (0xFFFFFFFFU) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT (0U) +/*! W1CLR - Write-1 Clear */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_W1CLR_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_COUNT (1U) + +/*! @name MBC_INDEX_MBC_NSE_BLK_CLR_ALL - MBC NonSecure Enable Block Clear All */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK (0xF00U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT (8U) +/*! MEMSEL - Memory Select */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_MEMSEL_MASK) + +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT (16U) +/*! DID_SEL0 - DID Select + * 0b0..No effect. + * 0b1..Clear all NSE bits for this domain. + */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_DID_SEL0_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL */ +#define TRDC_MBC_INDEX_MBC_NSE_BLK_CLR_ALL_COUNT (1U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_NSE_W_MBC_DOM0_MEM0_BLK_NSE_W_COUNT2 (2U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_NSE_W_MBC_DOM0_MEM1_BLK_NSE_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W - MBC Memory Block NonSecure Enable Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT (0U) +/*! BIT0 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT (1U) +/*! BIT1 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT (2U) +/*! BIT2 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT (3U) +/*! BIT3 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT (4U) +/*! BIT4 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT (5U) +/*! BIT5 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT (6U) +/*! BIT6 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT (7U) +/*! BIT7 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT (8U) +/*! BIT8 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT8_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT (9U) +/*! BIT9 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT9_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT (10U) +/*! BIT10 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT10_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT (11U) +/*! BIT11 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT11_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT (12U) +/*! BIT12 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT12_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT (13U) +/*! BIT13 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT13_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT (14U) +/*! BIT14 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT14_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT (15U) +/*! BIT15 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT15_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK (0x10000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT (16U) +/*! BIT16 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT16_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK (0x20000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT (17U) +/*! BIT17 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT17_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK (0x40000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT (18U) +/*! BIT18 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT18_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT (19U) +/*! BIT19 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT19_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK (0x100000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT (20U) +/*! BIT20 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT20_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK (0x200000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT (21U) +/*! BIT21 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT21_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK (0x400000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT (22U) +/*! BIT22 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT22_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT (23U) +/*! BIT23 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT23_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK (0x1000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT (24U) +/*! BIT24 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT24_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK (0x2000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT (25U) +/*! BIT25 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT25_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK (0x4000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT (26U) +/*! BIT26 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT26_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT (27U) +/*! BIT27 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT27_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK (0x10000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT (28U) +/*! BIT28 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT28_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK (0x20000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT (29U) +/*! BIT29 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT29_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK (0x40000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT (30U) +/*! BIT30 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT30_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT (31U) +/*! BIT31 - Bit b NonSecure Enable [b = 0 - 31] + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_BIT31_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_NSE_W_MBC_DOM0_MEM2_BLK_NSE_W_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_Register_Masks */ + + +/* TRDC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x500C7000u) + /** Peripheral TRDC base address */ + #define TRDC_BASE_NS (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Peripheral TRDC base pointer */ + #define TRDC_NS ((TRDC_Type *)TRDC_BASE_NS) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS_NS { TRDC_BASE_NS } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS_NS { TRDC_NS } +#else + /** Peripheral TRDC base address */ + #define TRDC_BASE (0x400C7000u) + /** Peripheral TRDC base pointer */ + #define TRDC ((TRDC_Type *)TRDC_BASE) + /** Array initializer of TRDC peripheral base addresses */ + #define TRDC_BASE_ADDRS { TRDC_BASE } + /** Array initializer of TRDC peripheral base pointers */ + #define TRDC_BASE_PTRS { TRDC } +#endif +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/*! + * @} + */ /* end of group TRDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer + * @{ + */ + +/** USBHS - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & Control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control 0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USBHS_Type; + +/* ---------------------------------------------------------------------------- + -- USBHS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHS_Register_Masks USBHS Register Masks + * @{ + */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define USBHS_ID_ID_MASK (0x3FU) +#define USBHS_ID_ID_SHIFT (0U) +/*! ID - Configuration Number */ +#define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK) + +#define USBHS_ID_NID_MASK (0x3F00U) +#define USBHS_ID_NID_SHIFT (8U) +/*! NID - Complement Version of ID */ +#define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK) + +#define USBHS_ID_REVISION_MASK (0xFF0000U) +#define USBHS_ID_REVISION_SHIFT (16U) +/*! REVISION - Revision Number of the Controller Core */ +#define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ + +#define USBHS_HWGENERAL_PHYW_MASK (0x30U) +#define USBHS_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW - Data width of the transceiver connected to the controller core + * 0b00..8 bit wide data bus (Software non-programmable) + * 0b01..16 bit wide data bus (Software non-programmable) + * 0b10..Reset to 8 bit wide data bus (Software programmable) + * 0b11..Reset to 16 bit wide data bus (Software programmable) + */ +#define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK) + +#define USBHS_HWGENERAL_PHYM_MASK (0x1C0U) +#define USBHS_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM - Transceiver Type + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ +#define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK) + +#define USBHS_HWGENERAL_SM_MASK (0x600U) +#define USBHS_HWGENERAL_SM_SHIFT (9U) +/*! SM - Serial interface mode capability + * 0b00..No Serial Engine, always use parallel signalling + * 0b01..Serial Engine present, always use serial signalling for FS/LS + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWHOST_HC_MASK (0x1U) +#define USBHS_HWHOST_HC_SHIFT (0U) +/*! HC - Host Capable + * 0b1..Supported + * 0b0..Not supported + */ +#define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK) + +#define USBHS_HWHOST_NPORT_MASK (0xEU) +#define USBHS_HWHOST_NPORT_SHIFT (1U) +/*! NPORT - The Number of downstream ports supported by the host controller is (NPORT+1) */ +#define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWDEVICE_DC_MASK (0x1U) +#define USBHS_HWDEVICE_DC_SHIFT (0U) +/*! DC - Device Capable + * 0b1..Supported + * 0b0..Not supported + */ +#define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK) + +#define USBHS_HWDEVICE_DEVEP_MASK (0x3EU) +#define USBHS_HWDEVICE_DEVEP_SHIFT (1U) +/*! DEVEP - Device Endpoint Number */ +#define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWTXBUF_TXBURST_MASK (0xFFU) +#define USBHS_HWTXBUF_TXBURST_SHIFT (0U) +/*! TXBURST - Default burst size for memory to TX buffer transfer */ +#define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK) + +#define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U) +/*! TXCHANADD - TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes */ +#define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ + +#define USBHS_HWRXBUF_RXBURST_MASK (0xFFU) +#define USBHS_HWRXBUF_RXBURST_SHIFT (0U) +/*! RXBURST - Default burst size for memory to RX buffer transfer */ +#define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK) + +#define USBHS_HWRXBUF_RXADD_MASK (0xFF00U) +#define USBHS_HWRXBUF_RXADD_SHIFT (8U) +/*! RXADD - Buffer total size for all receive endpoints is (2^RXADD) */ +#define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ + +#define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U) +/*! GPTLD - General Purpose Timer Load Value */ +#define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ + +#define USBHS_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USBHS_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - General Purpose Timer Counter */ +#define USBHS_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTRL_GPTCNT_MASK) + +#define USBHS_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USBHS_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - General Purpose Timer Mode + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USBHS_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER0CTRL_GPTMODE_MASK) + +#define USBHS_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USBHS_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - General Purpose Timer Reset + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USBHS_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRST_MASK) + +#define USBHS_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USBHS_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - General Purpose Timer Run + * 0b0..Stop counting + * 0b1..Run + */ +#define USBHS_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ + +#define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U) +/*! GPTLD - General Purpose Timer Load Value */ +#define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ + +#define USBHS_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USBHS_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - General Purpose Timer Counter */ +#define USBHS_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTRL_GPTCNT_MASK) + +#define USBHS_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USBHS_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE - General Purpose Timer Mode + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USBHS_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTMODE_SHIFT)) & USBHS_GPTIMER1CTRL_GPTMODE_MASK) + +#define USBHS_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USBHS_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST - General Purpose Timer Reset + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USBHS_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRST_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRST_MASK) + +#define USBHS_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USBHS_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN - General Purpose Timer Run + * 0b0..Stop counting + * 0b1..Run + */ +#define USBHS_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTRL_GPTRUN_SHIFT)) & USBHS_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ + +#define USBHS_SBUSCFG_AHBBRST_MASK (0x7U) +#define USBHS_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST - AHB master interface Burst configuration + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USBHS_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_SBUSCFG_AHBBRST_SHIFT)) & USBHS_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ + +#define USBHS_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USBHS_CAPLENGTH_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - These bits are used as an offset to add to register base to find the beginning of + * the Operational Register. Default value is '40h'. + */ +#define USBHS_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USBHS_CAPLENGTH_CAPLENGTH_SHIFT)) & USBHS_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ + +#define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USBHS_HCIVERSION_HCIVERSION_SHIFT (0U) +/*! HCIVERSION - Host Controller Interface Version Number */ +#define USBHS_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ + +#define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - Number of Downstream Ports */ +#define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK) + +#define USBHS_HCSPARAMS_PPC_MASK (0x10U) +#define USBHS_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - Port Power Control */ +#define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK) + +#define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USBHS_HCSPARAMS_N_PCC_SHIFT (8U) +/*! N_PCC - Number of Ports per Companion Controller */ +#define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK) + +#define USBHS_HCSPARAMS_N_CC_MASK (0xF000U) +#define USBHS_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC - Number of Companion Controller + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported + */ +#define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK) + +#define USBHS_HCSPARAMS_PI_MASK (0x10000U) +#define USBHS_HCSPARAMS_PI_SHIFT (16U) +/*! PI - Port Indicators (P INDICATOR) */ +#define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK) + +#define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USBHS_HCSPARAMS_N_PTT_SHIFT (20U) +/*! N_PTT - Number of Ports per Transaction Translator */ +#define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK) + +#define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USBHS_HCSPARAMS_N_TT_SHIFT (24U) +/*! N_TT - Number of Transaction Translators */ +#define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ + +#define USBHS_HCCPARAMS_ADC_MASK (0x1U) +#define USBHS_HCCPARAMS_ADC_SHIFT (0U) +/*! ADC - 64-bit Addressing Capability */ +#define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK) + +#define USBHS_HCCPARAMS_PFL_MASK (0x2U) +#define USBHS_HCCPARAMS_PFL_SHIFT (1U) +/*! PFL - Programmable Frame List Flag */ +#define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK) + +#define USBHS_HCCPARAMS_ASP_MASK (0x4U) +#define USBHS_HCCPARAMS_ASP_SHIFT (2U) +/*! ASP - Asynchronous Schedule Park Capability */ +#define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK) + +#define USBHS_HCCPARAMS_IST_MASK (0xF0U) +#define USBHS_HCCPARAMS_IST_SHIFT (4U) +/*! IST - Isochronous Scheduling Threshold */ +#define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK) + +#define USBHS_HCCPARAMS_EECP_MASK (0xFF00U) +#define USBHS_HCCPARAMS_EECP_SHIFT (8U) +/*! EECP - EHCI Extended Capabilities Pointer */ +#define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ + +#define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U) +/*! DCIVERSION - Device Controller Interface Version Number */ +#define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ + +#define USBHS_DCCPARAMS_DEN_MASK (0x1FU) +#define USBHS_DCCPARAMS_DEN_SHIFT (0U) +/*! DEN - Device Endpoint Number */ +#define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK) + +#define USBHS_DCCPARAMS_DC_MASK (0x80U) +#define USBHS_DCCPARAMS_DC_SHIFT (7U) +/*! DC - Device Capable */ +#define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK) + +#define USBHS_DCCPARAMS_HC_MASK (0x100U) +#define USBHS_DCCPARAMS_HC_SHIFT (8U) +/*! HC - Host Capable */ +#define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command */ +/*! @{ */ + +#define USBHS_USBCMD_RS_MASK (0x1U) +#define USBHS_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop + * 0b0..Stop + * 0b1..Run + */ +#define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK) + +#define USBHS_USBCMD_RST_MASK (0x2U) +#define USBHS_USBCMD_RST_SHIFT (1U) +/*! RST - Controller Reset */ +#define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK) + +#define USBHS_USBCMD_FS_1_MASK (0xCU) +#define USBHS_USBCMD_FS_1_SHIFT (2U) +/*! FS_1 - Frame List Size */ +#define USBHS_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_1_SHIFT)) & USBHS_USBCMD_FS_1_MASK) + +#define USBHS_USBCMD_PSE_MASK (0x10U) +#define USBHS_USBCMD_PSE_SHIFT (4U) +/*! PSE - Periodic Schedule Enable + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule + */ +#define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK) + +#define USBHS_USBCMD_ASE_MASK (0x20U) +#define USBHS_USBCMD_ASE_SHIFT (5U) +/*! ASE - Asynchronous Schedule Enable + * 0b0..Do not process the Asynchronous Schedule + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule + */ +#define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK) + +#define USBHS_USBCMD_IAA_MASK (0x40U) +#define USBHS_USBCMD_IAA_SHIFT (6U) +/*! IAA - Interrupt on Async Advance Doorbell */ +#define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK) + +#define USBHS_USBCMD_ASP_MASK (0x300U) +#define USBHS_USBCMD_ASP_SHIFT (8U) +/*! ASP - Asynchronous Schedule Park Mode Count */ +#define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK) + +#define USBHS_USBCMD_ASPE_MASK (0x800U) +#define USBHS_USBCMD_ASPE_SHIFT (11U) +/*! ASPE - Asynchronous Schedule Park Mode Enable */ +#define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK) + +#define USBHS_USBCMD_SUTW_MASK (0x2000U) +#define USBHS_USBCMD_SUTW_SHIFT (13U) +/*! SUTW - Setup TripWire [device mode only] */ +#define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK) + +#define USBHS_USBCMD_ATDTW_MASK (0x4000U) +#define USBHS_USBCMD_ATDTW_SHIFT (14U) +/*! ATDTW - Add dTD TripWire[device mode only] */ +#define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK) + +#define USBHS_USBCMD_FS_2_MASK (0x8000U) +#define USBHS_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 - Frame List Size [host mode only] */ +#define USBHS_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_2_SHIFT)) & USBHS_USBCMD_FS_2_MASK) + +#define USBHS_USBCMD_ITC_MASK (0xFF0000U) +#define USBHS_USBCMD_ITC_SHIFT (16U) +/*! ITC - Interrupt Threshold Control + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status */ +/*! @{ */ + +#define USBHS_USBSTS_UI_MASK (0x1U) +#define USBHS_USBSTS_UI_SHIFT (0U) +/*! UI - USB Interrupt (USBINT) */ +#define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK) + +#define USBHS_USBSTS_UEI_MASK (0x2U) +#define USBHS_USBSTS_UEI_SHIFT (1U) +/*! UEI - USB Error Interrupt (USBERRINT) */ +#define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK) + +#define USBHS_USBSTS_PCI_MASK (0x4U) +#define USBHS_USBSTS_PCI_SHIFT (2U) +/*! PCI - Port Change Detect */ +#define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK) + +#define USBHS_USBSTS_FRI_MASK (0x8U) +#define USBHS_USBSTS_FRI_SHIFT (3U) +/*! FRI - Frame List Rollover */ +#define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK) + +#define USBHS_USBSTS_SEI_MASK (0x10U) +#define USBHS_USBSTS_SEI_SHIFT (4U) +/*! SEI - System Error */ +#define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK) + +#define USBHS_USBSTS_AAI_MASK (0x20U) +#define USBHS_USBSTS_AAI_SHIFT (5U) +/*! AAI - Interrupt on Async Advance */ +#define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK) + +#define USBHS_USBSTS_URI_MASK (0x40U) +#define USBHS_USBSTS_URI_SHIFT (6U) +/*! URI - USB Reset Received */ +#define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK) + +#define USBHS_USBSTS_SRI_MASK (0x80U) +#define USBHS_USBSTS_SRI_SHIFT (7U) +/*! SRI - SOF Received */ +#define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK) + +#define USBHS_USBSTS_SLI_MASK (0x100U) +#define USBHS_USBSTS_SLI_SHIFT (8U) +/*! SLI - DCSuspend */ +#define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK) + +#define USBHS_USBSTS_ULPII_MASK (0x400U) +#define USBHS_USBSTS_ULPII_SHIFT (10U) +/*! ULPII - ULPI Interrupt */ +#define USBHS_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_ULPII_SHIFT)) & USBHS_USBSTS_ULPII_MASK) + +#define USBHS_USBSTS_HCH_MASK (0x1000U) +#define USBHS_USBSTS_HCH_SHIFT (12U) +/*! HCH - HCHaIted */ +#define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK) + +#define USBHS_USBSTS_RCL_MASK (0x2000U) +#define USBHS_USBSTS_RCL_SHIFT (13U) +/*! RCL - Reclamation */ +#define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK) + +#define USBHS_USBSTS_PS_MASK (0x4000U) +#define USBHS_USBSTS_PS_SHIFT (14U) +/*! PS - Periodic Schedule Status */ +#define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK) + +#define USBHS_USBSTS_AS_MASK (0x8000U) +#define USBHS_USBSTS_AS_SHIFT (15U) +/*! AS - Asynchronous Schedule Status */ +#define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK) + +#define USBHS_USBSTS_NAKI_MASK (0x10000U) +#define USBHS_USBSTS_NAKI_SHIFT (16U) +/*! NAKI - NAK Interrupt Bit */ +#define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK) + +#define USBHS_USBSTS_TI0_MASK (0x1000000U) +#define USBHS_USBSTS_TI0_SHIFT (24U) +/*! TI0 - General Purpose Timer Interrupt 0 (GPTINT0) */ +#define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK) + +#define USBHS_USBSTS_TI1_MASK (0x2000000U) +#define USBHS_USBSTS_TI1_SHIFT (25U) +/*! TI1 - General Purpose Timer Interrupt 1 (GPTINT1) */ +#define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable */ +/*! @{ */ + +#define USBHS_USBINTR_UE_MASK (0x1U) +#define USBHS_USBINTR_UE_SHIFT (0U) +/*! UE - USB Interrupt Enable */ +#define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK) + +#define USBHS_USBINTR_UEE_MASK (0x2U) +#define USBHS_USBINTR_UEE_SHIFT (1U) +/*! UEE - USB Error Interrupt Enable */ +#define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK) + +#define USBHS_USBINTR_PCE_MASK (0x4U) +#define USBHS_USBINTR_PCE_SHIFT (2U) +/*! PCE - Port Change Detect Interrupt Enable */ +#define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK) + +#define USBHS_USBINTR_FRE_MASK (0x8U) +#define USBHS_USBINTR_FRE_SHIFT (3U) +/*! FRE - Frame List Rollover Interrupt Enable */ +#define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK) + +#define USBHS_USBINTR_SEE_MASK (0x10U) +#define USBHS_USBINTR_SEE_SHIFT (4U) +/*! SEE - System Error Interrupt Enable */ +#define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK) + +#define USBHS_USBINTR_AAE_MASK (0x20U) +#define USBHS_USBINTR_AAE_SHIFT (5U) +/*! AAE - Async Advance Interrupt Enable */ +#define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK) + +#define USBHS_USBINTR_URE_MASK (0x40U) +#define USBHS_USBINTR_URE_SHIFT (6U) +/*! URE - USB Reset Interrupt Enable */ +#define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK) + +#define USBHS_USBINTR_SRE_MASK (0x80U) +#define USBHS_USBINTR_SRE_SHIFT (7U) +/*! SRE - SOF Received Interrupt Enable */ +#define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK) + +#define USBHS_USBINTR_SLE_MASK (0x100U) +#define USBHS_USBINTR_SLE_SHIFT (8U) +/*! SLE - Sleep Interrupt Enable */ +#define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK) + +#define USBHS_USBINTR_NAKE_MASK (0x10000U) +#define USBHS_USBINTR_NAKE_SHIFT (16U) +/*! NAKE - NAK Interrupt Enable */ +#define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK) + +#define USBHS_USBINTR_UAIE_MASK (0x40000U) +#define USBHS_USBINTR_UAIE_SHIFT (18U) +/*! UAIE - USB Host Asynchronous Interrupt Enable */ +#define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK) + +#define USBHS_USBINTR_UPIE_MASK (0x80000U) +#define USBHS_USBINTR_UPIE_SHIFT (19U) +/*! UPIE - USB Host Periodic Interrupt Enable */ +#define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK) + +#define USBHS_USBINTR_TIE0_MASK (0x1000000U) +#define USBHS_USBINTR_TIE0_SHIFT (24U) +/*! TIE0 - General Purpose Timer #0 Interrupt Enable */ +#define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK) + +#define USBHS_USBINTR_TIE1_MASK (0x2000000U) +#define USBHS_USBINTR_TIE1_SHIFT (25U) +/*! TIE1 - General Purpose Timer #1 Interrupt Enable */ +#define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ + +#define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USBHS_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX - Frame Index + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ + +#define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USBHS_DEVICEADDR_USBADRA_SHIFT (24U) +/*! USBADRA - Device Address Advance */ +#define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK) + +#define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USBHS_DEVICEADDR_USBADR_SHIFT (25U) +/*! USBADR - Device Address */ +#define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ + +#define USBHS_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USBHS_PERIODICLISTBASE_BASEADR_SHIFT (12U) +/*! BASEADR - Base Address (Low) */ +#define USBHS_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_BASEADR_SHIFT)) & USBHS_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ + +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +/*! ASYBASE - Link Pointer Low (LPL) */ +#define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ + +#define USBHS_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USBHS_ENDPTLISTADDR_EPBASE_SHIFT (11U) +/*! EPBASE - Endpoint List Pointer (Low) */ +#define USBHS_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTLISTADDR_EPBASE_SHIFT)) & USBHS_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ + +#define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U) +/*! RXPBURST - Programmable RX Burst Size */ +#define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK) + +#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U) +#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U) +/*! TXPBURST - Programmable TX Burst Size */ +#define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ + +#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU) +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U) +/*! TXSCHOH - Scheduler Overhead */ +#define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK) + +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +/*! TXSCHHEALTH - Scheduler Health Counter */ +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK) + +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +/*! TXFIFOTHRES - FIFO Burst Threshold */ +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ + +#define USBHS_ENDPTNAK_EPRN_MASK (0xFFU) +#define USBHS_ENDPTNAK_EPRN_SHIFT (0U) +/*! EPRN - RX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK) + +#define USBHS_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USBHS_ENDPTNAK_EPTN_SHIFT (16U) +/*! EPTN - TX Endpoint NAK */ +#define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ + +#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U) +/*! EPRNE - RX Endpoint NAK Enable */ +#define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK) + +#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U) +/*! EPTNE - TX Endpoint NAK Enable */ +#define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag */ +/*! @{ */ + +#define USBHS_CONFIGFLAG_CF_MASK (0x1U) +#define USBHS_CONFIGFLAG_CF_SHIFT (0U) +/*! CF - Configure Flag + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller + * 0b1..Port routing control logic default-routes all ports to this host controller + */ +#define USBHS_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USBHS_CONFIGFLAG_CF_SHIFT)) & USBHS_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ + +#define USBHS_PORTSC1_CCS_MASK (0x1U) +#define USBHS_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status + * 0b0..In Host mode: No device is present. In Device mode: Not attached + * 0b1..In Host mode: Device is present on port. In Device mode: Attached + */ +#define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK) + +#define USBHS_PORTSC1_CSC_MASK (0x2U) +#define USBHS_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change + * 0b0..No change + * 0b1..Change in current connect status + */ +#define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK) + +#define USBHS_PORTSC1_PE_MASK (0x4U) +#define USBHS_PORTSC1_PE_SHIFT (2U) +/*! PE - Port Enabled/Disabled + * 0b0..Disable + * 0b1..Enable + */ +#define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK) + +#define USBHS_PORTSC1_PEC_MASK (0x8U) +#define USBHS_PORTSC1_PEC_SHIFT (3U) +/*! PEC - Port Enable/Disable Change + * 0b0..No change + * 0b1..Port enabled/disabled status has changed + */ +#define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK) + +#define USBHS_PORTSC1_OCA_MASK (0x10U) +#define USBHS_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-Current Active + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition + */ +#define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK) + +#define USBHS_PORTSC1_OCC_MASK (0x20U) +#define USBHS_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current Change */ +#define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK) + +#define USBHS_PORTSC1_FPR_MASK (0x40U) +#define USBHS_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume + * 0b0..No resume (K-state) detected/driven on port + * 0b1..Resume detected/driven on port + */ +#define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK) + +#define USBHS_PORTSC1_SUSP_MASK (0x80U) +#define USBHS_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend + * 0b0..Port not in suspend state + * 0b1..Port in suspend state + */ +#define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK) + +#define USBHS_PORTSC1_PR_MASK (0x100U) +#define USBHS_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset + * 0b0..Port is not in reset + * 0b1..Port is in reset + */ +#define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK) + +#define USBHS_PORTSC1_HSP_MASK (0x200U) +#define USBHS_PORTSC1_HSP_SHIFT (9U) +/*! HSP - High-Speed Port */ +#define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK) + +#define USBHS_PORTSC1_LS_MASK (0xC00U) +#define USBHS_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ +#define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK) + +#define USBHS_PORTSC1_PP_MASK (0x1000U) +#define USBHS_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power */ +#define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK) + +#define USBHS_PORTSC1_PO_MASK (0x2000U) +#define USBHS_PORTSC1_PO_SHIFT (13U) +/*! PO - Port Owner */ +#define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK) + +#define USBHS_PORTSC1_PIC_MASK (0xC000U) +#define USBHS_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK) + +#define USBHS_PORTSC1_PTC_MASK (0xF0000U) +#define USBHS_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + * 0b1000-0b1111..Reserved + */ +#define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK) + +#define USBHS_PORTSC1_WKCN_MASK (0x100000U) +#define USBHS_PORTSC1_WKCN_SHIFT (20U) +/*! WKCN - Wake on Connect Enable (WKCNNT_E) */ +#define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK) + +#define USBHS_PORTSC1_WKDC_MASK (0x200000U) +#define USBHS_PORTSC1_WKDC_SHIFT (21U) +/*! WKDC - Wake on Disconnect Enable (WKDSCNNT_E) */ +#define USBHS_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDC_SHIFT)) & USBHS_PORTSC1_WKDC_MASK) + +#define USBHS_PORTSC1_WKOC_MASK (0x400000U) +#define USBHS_PORTSC1_WKOC_SHIFT (22U) +/*! WKOC - Wake on Over-current Enable (WKOC_E) */ +#define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK) + +#define USBHS_PORTSC1_PHCD_MASK (0x800000U) +#define USBHS_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD - PHY Low Power Suspend - Clock Disable (PLPSCD) + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ +#define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK) + +#define USBHS_PORTSC1_PFSC_MASK (0x1000000U) +#define USBHS_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC - Port Force Full Speed Connect + * 0b1..Forced to full speed + * 0b0..Normal operation + */ +#define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK) + +#define USBHS_PORTSC1_PTS_2_MASK (0x2000000U) +#define USBHS_PORTSC1_PTS_2_SHIFT (25U) +/*! PTS_2 - Parallel Transceiver Select */ +#define USBHS_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_2_SHIFT)) & USBHS_PORTSC1_PTS_2_MASK) + +#define USBHS_PORTSC1_PSPD_MASK (0xC000000U) +#define USBHS_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD - Port Speed + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK) + +#define USBHS_PORTSC1_PTW_MASK (0x10000000U) +#define USBHS_PORTSC1_PTW_SHIFT (28U) +/*! PTW - Parallel Transceiver Width - Read/Write + * 0b0..Select the 8-bit UTMI interface [60 MHz] + * 0b1..Select the 16-bit UTMI interface [30 MHz] + */ +#define USBHS_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTW_SHIFT)) & USBHS_PORTSC1_PTW_MASK) + +#define USBHS_PORTSC1_STS_MASK (0x20000000U) +#define USBHS_PORTSC1_STS_SHIFT (29U) +/*! STS - Serial Transceiver Select + * 0b0..Parallel Interface signals is selected + * 0b1..Serial Interface Engine is selected + */ +#define USBHS_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_STS_SHIFT)) & USBHS_PORTSC1_STS_MASK) + +#define USBHS_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USBHS_PORTSC1_PTS_1_SHIFT (30U) +/*! PTS_1 - Parallel Transceiver Select */ +#define USBHS_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_1_SHIFT)) & USBHS_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & Control */ +/*! @{ */ + +#define USBHS_OTGSC_VD_MASK (0x1U) +#define USBHS_OTGSC_VD_SHIFT (0U) +/*! VD - VBUS Discharge */ +#define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK) + +#define USBHS_OTGSC_VC_MASK (0x2U) +#define USBHS_OTGSC_VC_SHIFT (1U) +/*! VC - VBUS Charge */ +#define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK) + +#define USBHS_OTGSC_OT_MASK (0x8U) +#define USBHS_OTGSC_OT_SHIFT (3U) +/*! OT - OTG Termination */ +#define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK) + +#define USBHS_OTGSC_DP_MASK (0x10U) +#define USBHS_OTGSC_DP_SHIFT (4U) +/*! DP - Data Pulsing */ +#define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK) + +#define USBHS_OTGSC_IDPU_MASK (0x20U) +#define USBHS_OTGSC_IDPU_SHIFT (5U) +/*! IDPU - ID Pullup + * 0b0..Off + * 0b1..On + */ +#define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK) + +#define USBHS_OTGSC_ID_MASK (0x100U) +#define USBHS_OTGSC_ID_SHIFT (8U) +/*! ID - USB ID + * 0b0..A device + * 0b1..B device + */ +#define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK) + +#define USBHS_OTGSC_AVV_MASK (0x200U) +#define USBHS_OTGSC_AVV_SHIFT (9U) +/*! AVV - A VBus Valid */ +#define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK) + +#define USBHS_OTGSC_ASV_MASK (0x400U) +#define USBHS_OTGSC_ASV_SHIFT (10U) +/*! ASV - A Session Valid */ +#define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK) + +#define USBHS_OTGSC_BSV_MASK (0x800U) +#define USBHS_OTGSC_BSV_SHIFT (11U) +/*! BSV - B Session Valid */ +#define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK) + +#define USBHS_OTGSC_BSE_MASK (0x1000U) +#define USBHS_OTGSC_BSE_SHIFT (12U) +/*! BSE - B Session End */ +#define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK) + +#define USBHS_OTGSC_TOG_1MS_MASK (0x2000U) +#define USBHS_OTGSC_TOG_1MS_SHIFT (13U) +/*! TOG_1MS - 1 Millisecond Timer Toggle */ +#define USBHS_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_TOG_1MS_SHIFT)) & USBHS_OTGSC_TOG_1MS_MASK) + +#define USBHS_OTGSC_DPS_MASK (0x4000U) +#define USBHS_OTGSC_DPS_SHIFT (14U) +/*! DPS - Data Bus Pulsing Status */ +#define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK) + +#define USBHS_OTGSC_IDIS_MASK (0x10000U) +#define USBHS_OTGSC_IDIS_SHIFT (16U) +/*! IDIS - USB ID Interrupt Status */ +#define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK) + +#define USBHS_OTGSC_AVVIS_MASK (0x20000U) +#define USBHS_OTGSC_AVVIS_SHIFT (17U) +/*! AVVIS - A VBus Valid Interrupt Status */ +#define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK) + +#define USBHS_OTGSC_ASVIS_MASK (0x40000U) +#define USBHS_OTGSC_ASVIS_SHIFT (18U) +/*! ASVIS - A Session Valid Interrupt Status */ +#define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK) + +#define USBHS_OTGSC_BSVIS_MASK (0x80000U) +#define USBHS_OTGSC_BSVIS_SHIFT (19U) +/*! BSVIS - B Session Valid Interrupt Status */ +#define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK) + +#define USBHS_OTGSC_BSEIS_MASK (0x100000U) +#define USBHS_OTGSC_BSEIS_SHIFT (20U) +/*! BSEIS - B Session End Interrupt Status */ +#define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK) + +#define USBHS_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USBHS_OTGSC_STATUS_1MS_SHIFT (21U) +/*! STATUS_1MS - 1 Millisecond Timer Interrupt Status */ +#define USBHS_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_STATUS_1MS_SHIFT)) & USBHS_OTGSC_STATUS_1MS_MASK) + +#define USBHS_OTGSC_DPIS_MASK (0x400000U) +#define USBHS_OTGSC_DPIS_SHIFT (22U) +/*! DPIS - Data Pulse Interrupt Status */ +#define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK) + +#define USBHS_OTGSC_IDIE_MASK (0x1000000U) +#define USBHS_OTGSC_IDIE_SHIFT (24U) +/*! IDIE - USB ID Interrupt Enable */ +#define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK) + +#define USBHS_OTGSC_AVVIE_MASK (0x2000000U) +#define USBHS_OTGSC_AVVIE_SHIFT (25U) +/*! AVVIE - A VBus Valid Interrupt Enable */ +#define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK) + +#define USBHS_OTGSC_ASVIE_MASK (0x4000000U) +#define USBHS_OTGSC_ASVIE_SHIFT (26U) +/*! ASVIE - A Session Valid Interrupt Enable */ +#define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK) + +#define USBHS_OTGSC_BSVIE_MASK (0x8000000U) +#define USBHS_OTGSC_BSVIE_SHIFT (27U) +/*! BSVIE - B Session Valid Interrupt Enable */ +#define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK) + +#define USBHS_OTGSC_BSEIE_MASK (0x10000000U) +#define USBHS_OTGSC_BSEIE_SHIFT (28U) +/*! BSEIE - B Session End Interrupt Enable */ +#define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK) + +#define USBHS_OTGSC_EN_1MS_MASK (0x20000000U) +#define USBHS_OTGSC_EN_1MS_SHIFT (29U) +/*! EN_1MS - 1 Millisecond Timer Interrupt Enable */ +#define USBHS_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_EN_1MS_SHIFT)) & USBHS_OTGSC_EN_1MS_MASK) + +#define USBHS_OTGSC_DPIE_MASK (0x40000000U) +#define USBHS_OTGSC_DPIE_SHIFT (30U) +/*! DPIE - Data Pulse Interrupt Enable */ +#define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ + +#define USBHS_USBMODE_CM_MASK (0x3U) +#define USBHS_USBMODE_CM_SHIFT (0U) +/*! CM - Controller Mode + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK) + +#define USBHS_USBMODE_ES_MASK (0x4U) +#define USBHS_USBMODE_ES_SHIFT (2U) +/*! ES - Endian Select + * 0b0..Little Endian + * 0b1..Big Endian + */ +#define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK) + +#define USBHS_USBMODE_SLOM_MASK (0x8U) +#define USBHS_USBMODE_SLOM_SHIFT (3U) +/*! SLOM - Setup Lockout Mode + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off + */ +#define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK) + +#define USBHS_USBMODE_SDIS_MASK (0x10U) +#define USBHS_USBMODE_SDIS_SHIFT (4U) +/*! SDIS - Stream Disable Mode + * 0b0..Inactive + * 0b1..Active + */ +#define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ + +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +/*! ENDPTSETUPSTAT - Setup Endpoint Status */ +#define USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ + +#define USBHS_ENDPTPRIME_PERB_MASK (0xFFU) +#define USBHS_ENDPTPRIME_PERB_SHIFT (0U) +/*! PERB - Prime Endpoint Receive Buffer */ +#define USBHS_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PERB_SHIFT)) & USBHS_ENDPTPRIME_PERB_MASK) + +#define USBHS_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USBHS_ENDPTPRIME_PETB_SHIFT (16U) +/*! PETB - Prime Endpoint Transmit Buffer */ +#define USBHS_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTPRIME_PETB_SHIFT)) & USBHS_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ + +#define USBHS_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USBHS_ENDPTFLUSH_FERB_SHIFT (0U) +/*! FERB - Flush Endpoint Receive Buffer */ +#define USBHS_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FERB_SHIFT)) & USBHS_ENDPTFLUSH_FERB_MASK) + +#define USBHS_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USBHS_ENDPTFLUSH_FETB_SHIFT (16U) +/*! FETB - Flush Endpoint Transmit Buffer */ +#define USBHS_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTFLUSH_FETB_SHIFT)) & USBHS_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ + +#define USBHS_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USBHS_ENDPTSTAT_ERBR_SHIFT (0U) +/*! ERBR - Endpoint Receive Buffer Ready */ +#define USBHS_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ERBR_SHIFT)) & USBHS_ENDPTSTAT_ERBR_MASK) + +#define USBHS_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USBHS_ENDPTSTAT_ETBR_SHIFT (16U) +/*! ETBR - Endpoint Transmit Buffer Ready */ +#define USBHS_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTSTAT_ETBR_SHIFT)) & USBHS_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ + +#define USBHS_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USBHS_ENDPTCOMPLETE_ERCE_SHIFT (0U) +/*! ERCE - Endpoint Receive Complete Event */ +#define USBHS_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ERCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ERCE_MASK) + +#define USBHS_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USBHS_ENDPTCOMPLETE_ETCE_SHIFT (16U) +/*! ETCE - Endpoint Transmit Complete Event */ +#define USBHS_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCOMPLETE_ETCE_SHIFT)) & USBHS_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control 0 */ +/*! @{ */ + +#define USBHS_ENDPTCTRL0_RXS_MASK (0x1U) +#define USBHS_ENDPTCTRL0_RXS_SHIFT (0U) +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXS_SHIFT)) & USBHS_ENDPTCTRL0_RXS_MASK) + +#define USBHS_ENDPTCTRL0_RXT_MASK (0xCU) +#define USBHS_ENDPTCTRL0_RXT_SHIFT (2U) +/*! RXT - RX Endpoint Type + * 0b00..Control + */ +#define USBHS_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXT_SHIFT)) & USBHS_ENDPTCTRL0_RXT_MASK) + +#define USBHS_ENDPTCTRL0_RXE_MASK (0x80U) +#define USBHS_ENDPTCTRL0_RXE_SHIFT (7U) +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_RXE_SHIFT)) & USBHS_ENDPTCTRL0_RXE_MASK) + +#define USBHS_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USBHS_ENDPTCTRL0_TXS_SHIFT (16U) +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXS_SHIFT)) & USBHS_ENDPTCTRL0_TXS_MASK) + +#define USBHS_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USBHS_ENDPTCTRL0_TXT_SHIFT (18U) +/*! TXT - TX Endpoint Type + * 0b00..Control + */ +#define USBHS_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXT_SHIFT)) & USBHS_ENDPTCTRL0_TXT_MASK) + +#define USBHS_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USBHS_ENDPTCTRL0_TXE_SHIFT (23U) +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL0_TXE_SHIFT)) & USBHS_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ + +#define USBHS_ENDPTCTRL_RXS_MASK (0x1U) +#define USBHS_ENDPTCTRL_RXS_SHIFT (0U) +/*! RXS - RX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXS_SHIFT)) & USBHS_ENDPTCTRL_RXS_MASK) + +#define USBHS_ENDPTCTRL_RXD_MASK (0x2U) +#define USBHS_ENDPTCTRL_RXD_SHIFT (1U) +/*! RXD - RX Endpoint Data Sink + * 0b0..Dual Port Memory Buffer/DMA Engine + */ +#define USBHS_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXD_SHIFT)) & USBHS_ENDPTCTRL_RXD_MASK) + +#define USBHS_ENDPTCTRL_RXT_MASK (0xCU) +#define USBHS_ENDPTCTRL_RXT_SHIFT (2U) +/*! RXT - RX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ +#define USBHS_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXT_SHIFT)) & USBHS_ENDPTCTRL_RXT_MASK) + +#define USBHS_ENDPTCTRL_RXI_MASK (0x20U) +#define USBHS_ENDPTCTRL_RXI_SHIFT (5U) +/*! RXI - RX Data Toggle Inhibit + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXI_SHIFT)) & USBHS_ENDPTCTRL_RXI_MASK) + +#define USBHS_ENDPTCTRL_RXR_MASK (0x40U) +#define USBHS_ENDPTCTRL_RXR_SHIFT (6U) +/*! RXR - RX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ +#define USBHS_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXR_SHIFT)) & USBHS_ENDPTCTRL_RXR_MASK) + +#define USBHS_ENDPTCTRL_RXE_MASK (0x80U) +#define USBHS_ENDPTCTRL_RXE_SHIFT (7U) +/*! RXE - RX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_RXE_SHIFT)) & USBHS_ENDPTCTRL_RXE_MASK) + +#define USBHS_ENDPTCTRL_TXS_MASK (0x10000U) +#define USBHS_ENDPTCTRL_TXS_SHIFT (16U) +/*! TXS - TX Endpoint Stall + * 0b0..Endpoint OK + * 0b1..Endpoint stalled + */ +#define USBHS_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXS_SHIFT)) & USBHS_ENDPTCTRL_TXS_MASK) + +#define USBHS_ENDPTCTRL_TXD_MASK (0x20000U) +#define USBHS_ENDPTCTRL_TXD_SHIFT (17U) +/*! TXD - TX Endpoint Data Source + * 0b0..Dual Port Memory Buffer/DMA Engine + */ +#define USBHS_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXD_SHIFT)) & USBHS_ENDPTCTRL_TXD_MASK) + +#define USBHS_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USBHS_ENDPTCTRL_TXT_SHIFT (18U) +/*! TXT - TX Endpoint Type + * 0b00..Control + * 0b01..Isochronous + * 0b10..Bulk + * 0b11..Interrupt + */ +#define USBHS_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXT_SHIFT)) & USBHS_ENDPTCTRL_TXT_MASK) + +#define USBHS_ENDPTCTRL_TXI_MASK (0x200000U) +#define USBHS_ENDPTCTRL_TXI_SHIFT (21U) +/*! TXI - TX Data Toggle Inhibit + * 0b0..PID sequencing enabled + * 0b1..PID sequencing disabled + */ +#define USBHS_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXI_SHIFT)) & USBHS_ENDPTCTRL_TXI_MASK) + +#define USBHS_ENDPTCTRL_TXR_MASK (0x400000U) +#define USBHS_ENDPTCTRL_TXR_SHIFT (22U) +/*! TXR - TX Data Toggle Reset (WS) + * 0b1..Reset PID sequence + */ +#define USBHS_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXR_SHIFT)) & USBHS_ENDPTCTRL_TXR_MASK) + +#define USBHS_ENDPTCTRL_TXE_MASK (0x800000U) +#define USBHS_ENDPTCTRL_TXE_SHIFT (23U) +/*! TXE - TX Endpoint Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define USBHS_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTCTRL_TXE_SHIFT)) & USBHS_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USBHS_ENDPTCTRL */ +#define USBHS_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USBHS_Register_Masks */ + + +/* USBHS - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x5010B000u) + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE_NS (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC_NS ((USBHS_Type *)USBHS1__USBC_BASE_NS) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS_NS { USBHS1__USBC_BASE_NS } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS_NS { USBHS1__USBC_NS } +#else + /** Peripheral USBHS1__USBC base address */ + #define USBHS1__USBC_BASE (0x4010B000u) + /** Peripheral USBHS1__USBC base pointer */ + #define USBHS1__USBC ((USBHS_Type *)USBHS1__USBC_BASE) + /** Array initializer of USBHS peripheral base addresses */ + #define USBHS_BASE_ADDRS { USBHS1__USBC_BASE } + /** Array initializer of USBHS peripheral base pointers */ + #define USBHS_BASE_PTRS { USBHS1__USBC } +#endif +/** Interrupt vectors for the USBHS peripheral type */ +#define USBHS_IRQS { USB1_HS_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USBHS_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USBHS_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USBHS_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USBHS_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USBHS_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USBHS_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USBHS_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USBHS_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USBHS_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USBHS_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USBHS_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USBHS_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USBHS_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USBHS_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USBHS_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USBHS_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USBHS_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USBHS_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USBHS_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USBHS_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USBHS_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USBHS_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USBHS_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USBHS_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USBHS_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USBHS_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USBHS_SBUSCFG_AHBBRST(x) +#define USBHS_USBCMD_FS_MASK USBHS_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USBHS_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USBHS_USBCMD_FS_1(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USBHS_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USBHS_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USBHS_ENDPTLISTADDR_EPBASE(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USBHS_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USBHS_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USBHS_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USBHS_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USBHS_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USBHS_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USBHS_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USBHS_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USBHS_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USBHS_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USBHS_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USBHS_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USBHS_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USBHS_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USBHS_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USBHS_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USBHS_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USBHS_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USBHS_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USBHS_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USBHS_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USBHS_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USBHS_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USBHS_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USBHS_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USBHS_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USBHS_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USBHS_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USBHS_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USBHS_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USBHS_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USBHS_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USBHS_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USBHS_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USBHS_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USBHS_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USBHS_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USBHS_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USBHS_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USBHS_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USBHS_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USBHS_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USBHS_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USBHS_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USBHS_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USBHS_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USBHS_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USBHS_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USBHS_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USBHS_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USBHS_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USBHS_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USBHS_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USBHS_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USBHS_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USBHS_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USBHS_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USBHS_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USBHS_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USBHS_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USBHS_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USBHS_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USBHS_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USBHS_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USBHS_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USBHS_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USBHS_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USBHS_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USBHS_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USBHS_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USBHS_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USBHS_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USBHS_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USBHS_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USBHS_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USBHS_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USBHS_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USBHS_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USBHS_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USBHS_ENDPTCTRL_COUNT +#define USBHS_PORTSC1_WKDS_MASK USBHS_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USBHS_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USBHS_PORTSC1_WKDC(x) +#define USBHS_IRQHandler USB1_HS_IRQHandler + + +/*! + * @} + */ /* end of group USBHS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBHSDCD Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer + * @{ + */ + +/** USBHSDCD - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ + __IO uint32_t CLOCK; /**< Clock, offset: 0x4 */ + __I uint32_t STATUS; /**< Status, offset: 0x8 */ + __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override, offset: 0xC */ + __IO uint32_t TIMER0; /**< TIMER0, offset: 0x10 */ + __IO uint32_t TIMER1; /**< TIMER1, offset: 0x14 */ + union { /* offset: 0x18 */ + __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11, offset: 0x18 */ + __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12, offset: 0x18 */ + }; +} USBHSDCD_Type; + +/* ---------------------------------------------------------------------------- + -- USBHSDCD Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks + * @{ + */ + +/*! @name CONTROL - Control */ +/*! @{ */ + +#define USBHSDCD_CONTROL_IACK_MASK (0x1U) +#define USBHSDCD_CONTROL_IACK_SHIFT (0U) +/*! IACK - Interrupt Acknowledge + * 0b0..Do not clear the interrupt. + * 0b1..Clear the IF field (interrupt flag). + */ +#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK) + +#define USBHSDCD_CONTROL_IF_MASK (0x100U) +#define USBHSDCD_CONTROL_IF_SHIFT (8U) +/*! IF - Interrupt Flag + * 0b0..No interrupt is pending. + * 0b1..An interrupt is pending. + */ +#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK) + +#define USBHSDCD_CONTROL_IE_MASK (0x10000U) +#define USBHSDCD_CONTROL_IE_SHIFT (16U) +/*! IE - Interrupt Enable + * 0b0..Disable interrupts to the system. + * 0b1..Enable interrupts to the system. + */ +#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK) + +#define USBHSDCD_CONTROL_BC12_MASK (0x20000U) +#define USBHSDCD_CONTROL_BC12_SHIFT (17U) +/*! BC12 - Battery Charging Revision 1.2 Compatibility + * 0b0..Compatible with BC1.1 + * 0b1..Compatible with BC1.2 (default) + */ +#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK) + +#define USBHSDCD_CONTROL_START_MASK (0x1000000U) +#define USBHSDCD_CONTROL_START_SHIFT (24U) +/*! START - Start Change Detection Sequence + * 0b0..Do not start the sequence. Writes of this value have no effect. + * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. + */ +#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK) + +#define USBHSDCD_CONTROL_SR_MASK (0x2000000U) +#define USBHSDCD_CONTROL_SR_SHIFT (25U) +/*! SR - Software Reset + * 0b0..Do not perform a software reset. + * 0b1..Perform a software reset. + */ +#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK) +/*! @} */ + +/*! @name CLOCK - Clock */ +/*! @{ */ + +#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) +#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) +/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed + * 0b0..kHz Speed (between 4 kHz and 1023 kHz) + * 0b1..MHz Speed (between 1 MHz and 1023 MHz) + */ +#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK) + +#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) +#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) +/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary */ +#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U) +#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U) +/*! SEQ_RES - Charger Detection Sequence Results + * 0b00..No results to report. + * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. + * 0b10..Attached to a charging port. The exact meaning depends on the STATUS[SEQ_STAT] field (value 0: Attached + * to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The + * charger type detection has completed.) + * 0b11..Attached to a DCP. + */ +#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK) + +#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U) +#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U) +/*! SEQ_STAT - Charger Detection Sequence Status + * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. + * 0b01..Data pin contact detection is complete. + * 0b10..Charging port detection is complete. + * 0b11..Charger type detection is complete. + */ +#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK) + +#define USBHSDCD_STATUS_ERR_MASK (0x100000U) +#define USBHSDCD_STATUS_ERR_SHIFT (20U) +/*! ERR - Error Flag + * 0b0..No sequence errors. + * 0b1..Error in the detection sequence. + */ +#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK) + +#define USBHSDCD_STATUS_TO_MASK (0x200000U) +#define USBHSDCD_STATUS_TO_SHIFT (21U) +/*! TO - Timeout Flag + * 0b0..The detection sequence is not running for over 1 s. + * 0b1..It is over 1 s since the data pin contact was detected and debounced. + */ +#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK) + +#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U) +#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U) +/*! ACTIVE - Active Status Indicator + * 0b0..The sequence is not running. + * 0b1..The sequence is running. + */ +#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK) +/*! @} */ + +/*! @name SIGNAL_OVERRIDE - Signal Override */ +/*! @{ */ + +#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x7U) +#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) +/*! PS - Phase Selection + * 0b000..No overrides. Field must remain at this value during normal USB data communication to prevent + * unexpected conditions on USB_DP and USB_DM pins. (Default) + * 0b001..Reserved, not for customer use. + * 0b010..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. + * 0b011..Reserved, not for customer use. + * 0b100..Enables VDM_SRC voltage source only. + * 0b101..Reserved, not for customer use. + * 0b110..Reserved, not for customer use. + * 0b111..Reserved, not for customer use. + */ +#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK) +/*! @} */ + +/*! @name TIMER0 - TIMER0 */ +/*! @{ */ + +#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU) +#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U) +/*! TUNITCON - Unit Connection Timer Elapse (in ms) */ +#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK) + +#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) +#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U) +/*! TSEQ_INIT - Sequence Initiation Time + * 0b0000000000-0b1111111111..0 ms - 1023 ms + */ +#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK) +/*! @} */ + +/*! @name TIMER1 - TIMER1 */ +/*! @{ */ + +#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) +#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) +/*! TVDPSRC_ON - Time Period Comparator Enabled + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK) + +#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) +#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U) +/*! TDCD_DBNC - Time Period to Debounce D+ Signal + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK) +/*! @} */ + +/*! @name TIMER2_BC11 - TIMER2_BC11 */ +/*! @{ */ + +#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) +#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) +/*! CHECK_DM - Time Before Check of D- Line + * 0b0001-0b1111..1 ms - 15 ms + */ +#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK) + +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) +/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK) +/*! @} */ + +/*! @name TIMER2_BC12 - TIMER2_BC12 */ +/*! @{ */ + +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) +/*! TVDMSRC_ON - TVDMSRC_ON + * 0b0000000000-0b0000101000..0 ms - 40 ms + */ +#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK) + +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) +/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD + * 0b0000000001-0b1111111111..1 ms - 1023 ms + */ +#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBHSDCD_Register_Masks */ + + +/* USBHSDCD - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x5010A000u) + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE_NS (0x4010A000u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD_NS ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE_NS) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS_NS { USBHS1_PHY_DCD_BASE_NS } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS_NS { USBHS1_PHY_DCD_NS } +#else + /** Peripheral USBHS1_PHY_DCD base address */ + #define USBHS1_PHY_DCD_BASE (0x4010A000u) + /** Peripheral USBHS1_PHY_DCD base pointer */ + #define USBHS1_PHY_DCD ((USBHSDCD_Type *)USBHS1_PHY_DCD_BASE) + /** Array initializer of USBHSDCD peripheral base addresses */ + #define USBHSDCD_BASE_ADDRS { USBHS1_PHY_DCD_BASE } + /** Array initializer of USBHSDCD peripheral base pointers */ + #define USBHSDCD_BASE_PTRS { USBHS1_PHY_DCD } +#endif +/* Backward compatibility */ +#define USBHSDCD_IRQS { USB1_HS_PHY_IRQn } +#define USB1_HS_PHY_IRQS USBPHY_IRQS + + +/*! + * @} + */ /* end of group USBHSDCD_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL1; /**< USB OTG Control 1, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control, offset: 0x10 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name CTRL1 - USB OTG Control 1 */ +/*! @{ */ + +#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS - Disable Overcurrent Detection + * 0b1..Disables + * 0b0..Enables + */ +#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) + +#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) +#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL - Polarity of Overcurrent + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ +#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) + +#define USBNC_CTRL1_PWR_POL_MASK (0x200U) +#define USBNC_CTRL1_PWR_POL_SHIFT (9U) +/*! PWR_POL - Power Polarity + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ +#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) + +#define USBNC_CTRL1_WIE_MASK (0x400U) +#define USBNC_CTRL1_WIE_SHIFT (10U) +/*! WIE - Wake-up Interrupt Enable + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ +#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) + +#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN - Software Wake-up Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) + +#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) +#define USBNC_CTRL1_WKUP_SW_SHIFT (15U) +/*! WKUP_SW - Software Wake-up + * 0b1..Force wake-up + * 0b0..Inactive + */ +#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) + +#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN - Wake-up on ID Change Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) + +#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN - Wake-up on VBUS Change Enable + * 0b1..Enables + * 0b0..Disables + */ +#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) + +#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN - Wake-up on DPDM Change Enable + * 0b1..DPDM changes wake-up to be enabled, it is for device only + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0 + */ +#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) + +#define USBNC_CTRL1_WIR_MASK (0x80000000U) +#define USBNC_CTRL1_WIR_SHIFT (31U) +/*! WIR - Wake-up Interrupt Request + * 0b1..Request received + * 0b0..No request received + */ +#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) +/*! @} */ + +/*! @name CTRL2 - USB OTG Control 2 */ +/*! @{ */ + +#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) +#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS Source Select + * 0b00..vbus_valid + * 0b01..sess_valid + * 0b10..sess_valid + * 0b11..sess_valid + */ +#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) + +#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) +#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) +/*! AUTURESUME_EN - Auto Resume Enable + * 0b0..Default + */ +#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) + +#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) +#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) +/*! LOWSPEED_EN - Low Speed Enable + * 0b0..Default + */ +#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) + +#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD - UTMI Clock Valid + * 0b0..Default + */ +#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) +/*! @} */ + +/*! @name HSIC_CTRL - USB Host HSIC Control */ +/*! @{ */ + +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) +/*! HSIC_CLK_ON - HSIC Clock ON + * 0b1..Active + * 0b0..Inactive + */ +#define USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK) + +#define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) +#define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) +/*! HSIC_EN - Host HSIC Enable + * 0b1..Enabled + * 0b0..Disabled + */ +#define USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK) + +#define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) +#define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) +/*! CLK_VLD - Clock Valid + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x5010B200u) + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE_NS (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC_NS ((USBNC_Type *)USBHS1__USBNC_BASE_NS) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS_NS { USBHS1__USBNC_BASE_NS } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS_NS { USBHS1__USBNC_NS } +#else + /** Peripheral USBHS1__USBNC base address */ + #define USBHS1__USBNC_BASE (0x4010B200u) + /** Peripheral USBHS1__USBNC base pointer */ + #define USBHS1__USBNC ((USBNC_Type *)USBHS1__USBNC_BASE) + /** Array initializer of USBNC peripheral base addresses */ + #define USBNC_BASE_ADDRS { USBHS1__USBNC_BASE } + /** Array initializer of USBNC peripheral base pointers */ + #define USBNC_BASE_PTRS { USBHS1__USBNC } +#endif +/* Backward compatibility */ +#define USB_OTGn_CTRL CTRL1 +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x) +#define USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT +#define USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x) +#define USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT +#define USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x) + + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< Power Down, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< Power Down, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< Power Down, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< Power Down, offset: 0xC */ + __IO uint32_t TX; /**< TX Control, offset: 0x10 */ + __IO uint32_t TX_SET; /**< TX Control, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< TX Control, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< TX Control, offset: 0x1C */ + __IO uint32_t RX; /**< RX Control, offset: 0x20 */ + __IO uint32_t RX_SET; /**< RX Control, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< RX Control, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< RX Control, offset: 0x2C */ + __IO uint32_t CTRL; /**< General Purpose Control, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< General Purpose Control, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< General Purpose Control, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< General Purpose Control, offset: 0x3C */ + __IO uint32_t STATUS; /**< Status, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUG0; /**< Debug 0, offset: 0x50 */ + __IO uint32_t DEBUG0_SET; /**< Debug 0, offset: 0x54 */ + __IO uint32_t DEBUG0_CLR; /**< Debug 0, offset: 0x58 */ + __IO uint32_t DEBUG0_TOG; /**< Debug 0, offset: 0x5C */ + uint8_t RESERVED_1[32]; + __I uint32_t VERSION; /**< Version, offset: 0x80 */ + uint8_t RESERVED_2[12]; + __IO uint32_t IP; /**< IP Block, offset: 0x90 */ + __IO uint32_t IP_SET; /**< IP Block, offset: 0x94 */ + __IO uint32_t IP_CLR; /**< IP Block, offset: 0x98 */ + __IO uint32_t IP_TOG; /**< IP Block, offset: 0x9C */ + __IO uint32_t PLL_SIC; /**< PLL SIC, offset: 0xA0 */ + __IO uint32_t PLL_SIC_SET; /**< PLL SIC, offset: 0xA4 */ + __IO uint32_t PLL_SIC_CLR; /**< PLL SIC, offset: 0xA8 */ + __IO uint32_t PLL_SIC_TOG; /**< PLL SIC, offset: 0xAC */ + uint8_t RESERVED_3[16]; + __IO uint32_t USB1_VBUS_DETECT; /**< VBUS Detect, offset: 0xC0 */ + __IO uint32_t USB1_VBUS_DETECT_SET; /**< VBUS Detect, offset: 0xC4 */ + __IO uint32_t USB1_VBUS_DETECT_CLR; /**< VBUS Detect, offset: 0xC8 */ + __IO uint32_t USB1_VBUS_DETECT_TOG; /**< VBUS Detect, offset: 0xCC */ + __I uint32_t USB1_VBUS_DET_STAT; /**< VBUS Detect Status, offset: 0xD0 */ + __I uint32_t USB1_VBUS_DET_STAT_SET; /**< VBUS Detect Status, offset: 0xD4 */ + __I uint32_t USB1_VBUS_DET_STAT_CLR; /**< VBUS Detect Status, offset: 0xD8 */ + __I uint32_t USB1_VBUS_DET_STAT_TOG; /**< VBUS Detect Status, offset: 0xDC */ + __IO uint32_t USB1_CHRG_DETECT; /**< Charger Detect, offset: 0xE0 */ + __IO uint32_t USB1_CHRG_DETECT_SET; /**< Charger Detect, offset: 0xE4 */ + __IO uint32_t USB1_CHRG_DETECT_CLR; /**< Charger Detect, offset: 0xE8 */ + __IO uint32_t USB1_CHRG_DETECT_TOG; /**< Charger Detect, offset: 0xEC */ + __I uint32_t USB1_CHRG_DET_STAT; /**< Charger Detect Status, offset: 0xF0 */ + __I uint32_t USB1_CHRG_DET_STAT_SET; /**< Charger Detect Status, offset: 0xF4 */ + __I uint32_t USB1_CHRG_DET_STAT_CLR; /**< Charger Detect Status, offset: 0xF8 */ + __I uint32_t USB1_CHRG_DET_STAT_TOG; /**< Charger Detect Status, offset: 0xFC */ + __IO uint32_t ANACTRL; /**< Analog Control, offset: 0x100 */ + __IO uint32_t ANACTRL_SET; /**< Analog Control, offset: 0x104 */ + __IO uint32_t ANACTRL_CLR; /**< Analog Control, offset: 0x108 */ + __IO uint32_t ANACTRL_TOG; /**< Analog Control, offset: 0x10C */ + uint8_t RESERVED_4[32]; + __IO uint32_t TRIM_OVERRIDE_EN; /**< Trim, offset: 0x130 */ + __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< Trim, offset: 0x134 */ + __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< Trim, offset: 0x138 */ + __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< Trim, offset: 0x13C */ + __IO uint32_t PFDA; /**< PFD A, offset: 0x140 */ + __IO uint32_t PFDA_SET; /**< PFD A, offset: 0x144 */ + __IO uint32_t PFDA_CLR; /**< PFD A, offset: 0x148 */ + __IO uint32_t PFDA_TOG; /**< PFD A, offset: 0x14C */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers + * 0b0..Provide bias to enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_SET - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_CLR - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +/*! @} */ + +/*! @name PWD_TOG - Power Down */ +/*! @{ */ + +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +/*! TXPWDFS - Power Down USB FS TX Drivers */ +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +/*! TXPWDIBIAS - Power Down USBPHY TX Current Bias Block */ +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +/*! TXPWDV2I - Power Down USBPHY TX V-I Converter and Current Mirror */ +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +/*! RXPWDENV - Power Down USB HS RX Envelope Detector */ +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +/*! RXPWD1PT1 - Power Down USB FS Differential Receiver */ +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +/*! RXPWDDIFF - Power Down USB HS Differential Receiver */ +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +/*! RXPWDRX - Power Down USBPHY Receiver Circuits */ +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +/*! @} */ + +/*! @name TX - TX Control */ +/*! @{ */ + +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) + +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_SET - TX Control */ +/*! @{ */ + +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) + +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_CLR - TX Control */ +/*! @{ */ + +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) + +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +/*! @} */ + +/*! @name TX_TOG - TX Control */ +/*! @{ */ + +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +/*! D_CAL - HS TX Output Current Trim */ +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - DM Series Termination Resistance Trim */ +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) + +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +/*! TXCAL45DP - DP Series Termination Resistance Trim */ +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +/*! @} */ + +/*! @name RX - RX Control */ +/*! @{ */ + +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point + * 0b000..0.1000 V + * 0b001..0.1125 V + * 0b010..0.1250 V + * 0b011..0.0875 V + * 0b1xx.. + */ +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point + * 0b000..0.56875 V + * 0b001..0.55000 V + * 0b010..0.58125 V + * 0b011..0.60000 V + * 0b1xx.. + */ +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_SET - RX Control */ +/*! @{ */ + +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_CLR - RX Control */ +/*! @{ */ + +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +/*! @} */ + +/*! @name RX_TOG - RX Control */ +/*! @{ */ + +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +/*! ENVADJ - Envelope Detector Trip Point */ +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +/*! DISCONADJ - Disconnect Detector Trip Point */ +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +/*! @} */ + +/*! @name CTRL - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt + * 0b0..Connected + * 0b1..Disconnected + */ +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity + * 0b0..Plugged in + * 0b1..Unplugged + */ +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt + * 0b0..No ID change interrupt + * 0b1..ID change interrupt + */ +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky + * 0b0..During the resume or reset state signaling period + * 0b1..Until you write 0 to it + */ +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt + * 0b0..No resume interrupt + * 0b1..Resume interrupt + */ +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value + * 0b0..Host + * 0b1..Device + */ +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend + * 0b0..Not suspended + * 0b1..Suspended + */ +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate + * 0b0..Run clocks + * 0b1..Gate clocks + */ +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset + * 0b0..Release from reset + * 0b1..Soft-reset + */ +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - General Purpose Control */ +/*! @{ */ + +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - OTG ID Change Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - Host Disconnect Detection Enable */ +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - Enable Interrupt for Host Disconnect */ +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - Host Disconnect Detection Interrupt */ +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enable Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - Device Plug-In Polarity */ +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG ID Change Interrupt */ +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - Enable Internal OTG ID Detector */ +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - Resume Interrupt Sticky */ +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - Resume Detection Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - Resume Interrupt */ +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - Enable Interrupt for Nonstandard Resistive Plugged-In Detection */ +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - Device Plug-In Interrupt */ +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +/*! DATA_ON_LRADC - APB Clock Switch Option */ +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - UTMI Level 2 Enable */ +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - UTMI Level 3 Enable */ +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - Wake-Up Interrupt Enable */ +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - Wake-Up Interrupt */ +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + +#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) +#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - Autoresume Enable */ +#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - Autoclear Clock Gate Enable */ +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - PHY PWD Autoclear Enable */ +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG ID Value */ +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI Suspend */ +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE - UTMI Clock Gate */ +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +/*! SFTRST - Software Reset */ +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +/*! OK_STATUS_3V - USB 3.3 V and 1.8 V Supply Status + * 0b0..Not powered + * 0b1..Powered + */ +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +/*! HOSTDISCONDETECT_STATUS - Host Disconnect Status + * 0b0..Not detected + * 0b1..Detected + */ +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +/*! DEVPLUGIN_STATUS - Status Indicator for Nonstandard Resistive Plugged-In Detection + * 0b0..No attachment detected + * 0b1..Cable attachment detected + */ +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +/*! OTGID_STATUS - OTG ID Status + * 0b0..Host + * 0b1..Device + */ +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) + +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +/*! RESUME_STATUS - Resume Status */ +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +/*! @} */ + +/*! @name DEBUG0 - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode + * 0b00..Disconnect + * 0b01..Connect + */ +#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode + * 0b00..Disable + * 0b01..Enable + */ +#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_SET - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_CLR - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name DEBUG0_TOG - Debug 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - Hold OTG_ID */ +#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - Enable Host Pulldown Overdrive Mode */ +#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) +/*! @} */ + +/*! @name VERSION - Version */ +/*! @{ */ + +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +/*! STEP - Step */ +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) + +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +/*! MINOR - Minor */ +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) + +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +/*! MAJOR - Major */ +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name IP - IP Block */ +/*! @{ */ + +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_SET - IP Block */ +/*! @{ */ + +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_SET_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_CLR - IP Block */ +/*! @{ */ + +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_CLR_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name IP_TOG - IP Block */ +/*! @{ */ + +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK (0x1U) +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT (0U) +/*! POWER_CONTROL_SUSPEND_OPTION - Power Control Suspend Option */ +#define USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_SHIFT)) & USBPHY_IP_TOG_POWER_CONTROL_SUSPEND_OPTION_MASK) +/*! @} */ + +/*! @name PLL_SIC - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control + * 0b0..Power up PLL + * 0b1..Power down PLL + */ +#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control + * 0b0..Power down + * 0b1..Allow powerup + */ +#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL + * 0b0..480 MHz output clock + * 0b1..Input reference clock + */ +#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control + * 0b0..PLL_POWER internal state signal + * 0b1..REFBIAS_PWD + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias + * 0b0..Enable + * 0b1..Disable or power down + */ +#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration + * 0b000..Configure for a 32 MHz input clock (divide by 15) + * 0b001..Configure for a 30 MHz input clock (divide by 16) + * 0b010..Configure for a 24 MHz input clock (divide by 20) + * 0b011..Reserved, not usable for USB operation (divide by 22) + * 0b100..Configure for a 20 MHz input clock (divide by 24) + * 0b101..Configure for a 19.2 MHz input clock (divide by 25) + * 0b110..Configure for a 16 MHz input clock (divide by 30) + * 0b111..Configure for a 12 MHz input clock (divide by 40) + */ +#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator + * 0b0..Not locked + * 0b1..Locked + */ +#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_SET - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_CLR - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SIC_TOG - PLL SIC */ +/*! @{ */ + +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) +/*! MISC2_CONTROL0 - Miscellaneous Control */ +#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL Multi-Phase Clock Outputs Enable */ +#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) +#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - USB PLL Powerup Control */ +#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL Output Clock Enable */ +#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - Bypass USB PLL */ +#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) +/*! REFBIAS_PWD_SEL - Reference Bias Power Control */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) +/*! REFBIAS_PWD - Power Down Reference Bias */ +#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - Enable PLL Regulator */ +#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) +/*! PLL_DIV_SEL - PLL Divider Value Configuration */ +#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) +#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) +/*! PLL_LOCK - USB PLL Lock Status Indicator */ +#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold + * 0b000..4.0 V + * 0b001..4.1 V + * 0b010..4.2 V + * 0b011..4.3 V + * 0b100..4.4 V + * 0b101..4.5 V + * 0b110..4.6 V + * 0b111..4.7 V + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable + * 0b0..Results of VBUS_VALID and session valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND + * 0b1..Override values for VBUS_VALID, AVALID, BVALID, and SESSEND + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection + * 0b0..VBUS_VALID comparator result + * 0b1..VBUS_VALID_3V comparator result + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection + * 0b00..VBUS_VALID comparator result + * 0b01..Session valid comparator result + * 0b10..Session valid comparator result + * 0b11.. + */ +#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override + * 0b0..Use ID pin detector or external override + * 0b1..Allow local override of ID pin detection status + */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable + * 0b0..Internal detector or local override + * 0b1..External ID signal value + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable + * 0b0..Internal detector or local override + * 0b1..External VBUS_VALID value + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection + * 0b0..VBUS_VALID comparator + * 0b1..Session valid detector + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable + * 0bxx0..Disable or power down the VBUS_VALID comparator + * 0bxx1..Enable the VBUS_VALID comparator + * 0bx0x..Disable or power down the session valid detector + * 0bx1x..Enable the session valid detector + * 0b0xx..Disable or power down the VBUS_VALID_3V detector + * 0b1xx..Enable the VBUS_VALID_3V detector + */ +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_SET - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_CLR - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DETECT_TOG - VBUS Detect */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH - VBUS Comparator Threshold */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) +/*! VBUS_OVERRIDE_EN - VBUS Detect Signal Local Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) +/*! SESSEND_OVERRIDE - Override Value for SESSEND */ +#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) +/*! BVALID_OVERRIDE - Override Value for B-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) +/*! AVALID_OVERRIDE - Override Value for A-Device Session Valid */ +#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) +/*! VBUSVALID_OVERRIDE - Override Value for the VBUS_VALID Signal */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) +/*! VBUSVALID_SEL - VBUS_VALID Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) +/*! VBUS_SOURCE_SEL - VBUS_VALID Source Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - Enable Local ID Pin Status Override */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - ID Pin Status Local Override */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN - External ID Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN - External VBUS Override Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK (0x40000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT (18U) +/*! VBUSVALID_TO_B - VBUS_VALID Comparator Selection */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_B_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x700000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +/*! VBUSVALID_PWRUP_CMPS - VBUS_VALID Comparator Enable */ +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +/*! DISCHARGE_VBUS - VBUS Discharge Resistor */ +#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator + * 0b0..Above threshold + * 0b1..Below threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status + * 0b0..Below threshold + * 0b1..Above threshold + */ +#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_SET - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SET_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_CLR - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_CLR_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_VBUS_DET_STAT_TOG - VBUS Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK (0x1U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT (0U) +/*! SESSEND - Session End Indicator */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_SESSEND_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK (0x2U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT (1U) +/*! BVALID - B-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_BVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK (0x4U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT (2U) +/*! AVALID - A-Device Session Valid Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_AVALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK (0x8U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT (3U) +/*! VBUS_VALID - VBUS Voltage Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK (0x10U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT (4U) +/*! VBUS_VALID_3V - VBUS_VALID_3V Detector Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_VBUS_VALID_3V_MASK) + +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK (0x20U) +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT (5U) +/*! EXT_ID - OTG ID External Override Status */ +#define USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_TOG_EXT_ID_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_USB1_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_USB1_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection + * 0b0..Fields in USB1_CHRG_DETECT + * 0b1..Fields and state machines in the USBHSDCD module + */ +#define USBPHY_USB1_CHRG_DETECT_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_SET - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_SET_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_CLR - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DETECT_TOG - Charger Detect */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK (0x2U) +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT (1U) +/*! DETECT_SEC - Secondary Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DETECT_SEC_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - DP Pullup Resistor Enable Override Control */ +#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK (0x10U) +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT (4U) +/*! VDM_SRC_ENABLE - VDM_SRC Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_VDM_SRC_ENABLE_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - BC Data Contact Detect Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - BC Charger Detection Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B - Selection of BC v1.2 Function Enable */ +#define USBPHY_USB1_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_EN_B_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_EN_B_MASK) + +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK (0x80000000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT (31U) +/*! DCDSEL - DCD Selection */ +#define USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_DCDSEL_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output + * 0b0..Not detected + * 0b1..Detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output + * 0b0..SDP detected + * 0b1..Charging port detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage + * 0b0..USB_DM pin voltage is <= 0.8 V + * 0b1..USB_DM pin voltage is >= 2.0 V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage + * 0b0..USB_DP pin voltage is <= 0.8 V + * 0b1..USB_DP pin voltage is >= 2.0 V + */ +#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output + * 0b0..CDP detected + * 0b1..DCP detected + */ +#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_SET - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SET_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_CLR - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CLR_SECDET_DCP_MASK) +/*! @} */ + +/*! @name USB1_CHRG_DET_STAT_TOG - Charger Detect Status */ +/*! @{ */ + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK (0x1U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT - Battery Charging Data Contact Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_PLUG_CONTACT_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK (0x2U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED - Battery Charging Primary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_CHRG_DETECTED_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT (2U) +/*! DM_STATE - DM Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DM_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK (0x8U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT (3U) +/*! DP_STATE - DP Voltage */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_DP_STATE_MASK) + +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK (0x10U) +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT (4U) +/*! SECDET_DCP - Battery Charging Secondary Detection Phase Output */ +#define USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_TOG_SECDET_DCP_MASK) +/*! @} */ + +/*! @name ANACTRL - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection + * 0b00..USB1PFDCLK = USB PLL reference clock + * 0b01..USB1PFDCLK = pfd_clk / 4 + * 0b10..USB1PFDCLK frequency = pfd_clk / 2 + * 0b11..USB1PFDCLK = pfd_clk + */ +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_SET - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_CLR - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name ANACTRL_TOG - Analog Control */ +/*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +/*! LVI_EN - Internal Low Voltage Detector Enable */ +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +/*! PFD_CLK_SEL - PFD Clock Selection */ +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) +/*! DEV_PULLDOWN - Device Pulldown Enable */ +#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value + * 0b0..TRIM_OVERRIDE_EN + * 0b1..PLL_SIC + */ +#define USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim + * 0b0..TRIM_OVERRIDE_EN + * 0b1..TX + */ +#define USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY + * 0b0000..Maximum current, approximately 19% above nominal + * 0b0111..Nominal + * 0b1111..Minimum current, approximately 19% below nominal + */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_SET - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_CLR - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name TRIM_OVERRIDE_EN_TOG - Trim */ +/*! @{ */ + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK (0x1U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! DIV_SEL_OVERRIDE - Override Enable for PLL Divider Value */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_DIV_SEL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK (0x4U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TX_D_CAL_OVERRIDE - Override Enable for HS TX Output Current Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_D_CAL_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK (0x8U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TX_CAL45DP_OVERRIDE - Override Enable for USB_DP Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DP_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT (4U) +/*! TX_CAL45DM_OVERRIDE - Override Enable for USB_DM Series Termination Trim */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK (0x38000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! PLL_CTRL0_DIV_SEL - PLL Divider Value Configuration Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_PLL_CTRL0_DIV_SEL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK (0xF00000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT (20U) +/*! USBPHY_TX_D_CAL - HS TX Output Current Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_D_CAL_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK (0xF000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! USBPHY_TX_CAL45DP - DP Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DP_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! USBPHY_TX_CAL45DN - DM Series Termination Resistance Trim Bits from Outside USBPHY */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_USBPHY_TX_CAL45DN_MASK) +/*! @} */ + +/*! @name PFDA - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate + * 0b0..Enable + * 0b1..Disable + */ +#define USBPHY_PFDA_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal + * 0b0..Not stable + * 0b1..Stable + */ +#define USBPHY_PFDA_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_SET - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_SET_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_SET_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_SET_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_SET_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_SET_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_SET_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_SET_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_SET_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_SET_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_CLR - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_CLR_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_CLR_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_CLR_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_CLR_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_CLR_PFD0_STABLE_MASK) +/*! @} */ + +/*! @name PFDA_TOG - PFD A */ +/*! @{ */ + +#define USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK (0x1U) +#define USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT (0U) +/*! PFD0_CLKGATE - PFD0 Clock Gate */ +#define USBPHY_PFDA_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_CLKGATE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_CLKGATE_MASK) + +#define USBPHY_PFDA_TOG_PFD0_FRAC_MASK (0x7EU) +#define USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT (1U) +/*! PFD0_FRAC - PFD0 Fractional Divider */ +#define USBPHY_PFDA_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_FRAC_SHIFT)) & USBPHY_PFDA_TOG_PFD0_FRAC_MASK) + +#define USBPHY_PFDA_TOG_PFD0_STABLE_MASK (0x80U) +#define USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT (7U) +/*! PFD0_STABLE - PFD0 Stable Signal */ +#define USBPHY_PFDA_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PFDA_TOG_PFD0_STABLE_SHIFT)) & USBPHY_PFDA_TOG_PFD0_STABLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x5010A000u) + /** Peripheral USBPHY base address */ + #define USBPHY_BASE_NS (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Peripheral USBPHY base pointer */ + #define USBPHY_NS ((USBPHY_Type *)USBPHY_BASE_NS) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS_NS { USBPHY_BASE_NS } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS_NS { USBPHY_NS } +#else + /** Peripheral USBPHY base address */ + #define USBPHY_BASE (0x4010A000u) + /** Peripheral USBPHY base pointer */ + #define USBPHY ((USBPHY_Type *)USBPHY_BASE) + /** Array initializer of USBPHY peripheral base addresses */ + #define USBPHY_BASE_ADDRS { USBPHY_BASE } + /** Array initializer of USBPHY peripheral base pointers */ + #define USBPHY_BASE_PTRS { USBPHY } +#endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_HS_PHY_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control, offset: 0x0 */ + __IO uint32_t STAT; /**< Status, offset: 0x4 */ + __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick Interval + * 0b0000000000000000000000000000000.. + * *..Clock cycles as defined in the description + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat Delay + * 0b0..One-time delay + * 0b1..Delay repeats continuously + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt Flag + * 0b0..Not pending + * 0b1..Pending + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Timer Active Flag + * 0b0..Inactive (stopped) + * 0b1..Active + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture Configuration */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture-Polarity 1 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture Clear */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear Capture 0 + * 0b0..Does nothing + * 0b1..Clears the CAP0 register value + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear Capture 1 + * 0b0..Does nothing + * 0b1..Clears the CAP1 register value + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear Capture 2 + * 0b0..Does nothing + * 0b1..Clears the CAP2 register value + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear Capture 3 + * 0b0..Does nothing + * 0b1..Clears the CAP3 register value + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Captured Value for the Related Capture Event */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Captured Value Valid Flag + * 0b0..Valid value not captured + * 0b1..Valid value captured + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x50012000u) + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE_NS (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Peripheral UTICK0 base pointer */ + #define UTICK0_NS ((UTICK_Type *)UTICK0_BASE_NS) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS_NS { UTICK0_BASE_NS } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS_NS { UTICK0_NS } +#else + /** Peripheral UTICK0 base address */ + #define UTICK0_BASE (0x40012000u) + /** Peripheral UTICK0 base pointer */ + #define UTICK0 ((UTICK_Type *)UTICK0_BASE) + /** Array initializer of UTICK peripheral base addresses */ + #define UTICK_BASE_ADDRS { UTICK0_BASE } + /** Array initializer of UTICK peripheral base pointers */ + #define UTICK_BASE_PTRS { UTICK0 } +#endif +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer + * @{ + */ + +/** VBAT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STATUSA; /**< Status A, offset: 0x10 */ + __IO uint32_t STATUSB; /**< Status B, offset: 0x14 */ + __IO uint32_t IRQENA; /**< Interrupt Enable A, offset: 0x18 */ + __IO uint32_t IRQENB; /**< Interrupt Enable B, offset: 0x1C */ + __IO uint32_t WAKENA; /**< Wake-up Enable A, offset: 0x20 */ + __IO uint32_t WAKENB; /**< Wake-up Enable B, offset: 0x24 */ + __IO uint32_t TAMPERA; /**< Tamper Enable A, offset: 0x28 */ + __IO uint32_t TAMPERB; /**< Tamper Enable B, offset: 0x2C */ + __IO uint32_t LOCKA; /**< Lock A, offset: 0x30 */ + __IO uint32_t LOCKB; /**< Lock B, offset: 0x34 */ + __IO uint32_t WAKECFG; /**< Wake-up Configuration, offset: 0x38 */ + uint8_t RESERVED_1[196]; + __IO uint32_t OSCCTLA; /**< Oscillator Control A, offset: 0x100 */ + __IO uint32_t OSCCTLB; /**< Oscillator Control B, offset: 0x104 */ + __IO uint32_t OSCCFGA; /**< Oscillator Configuration A, offset: 0x108 */ + __IO uint32_t OSCCFGB; /**< Oscillator Configuration B, offset: 0x10C */ + uint8_t RESERVED_2[8]; + __IO uint32_t OSCLCKA; /**< Oscillator Lock A, offset: 0x118 */ + __IO uint32_t OSCLCKB; /**< Oscillator Lock B, offset: 0x11C */ + __IO uint32_t OSCCLKE; /**< Oscillator Clock Enable, offset: 0x120 */ + uint8_t RESERVED_3[220]; + __IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */ + __IO uint32_t FROCTLB; /**< FRO16K Control B, offset: 0x204 */ + uint8_t RESERVED_4[16]; + __IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */ + __IO uint32_t FROLCKB; /**< FRO16K Lock B, offset: 0x21C */ + __IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */ + uint8_t RESERVED_5[220]; + __IO uint32_t LDOCTLA; /**< LDO_RAM Control A, offset: 0x300 */ + __IO uint32_t LDOCTLB; /**< LDO_RAM Control B, offset: 0x304 */ + uint8_t RESERVED_6[16]; + __IO uint32_t LDOLCKA; /**< LDO_RAM Lock A, offset: 0x318 */ + __IO uint32_t LDOLCKB; /**< LDO_RAM Lock B, offset: 0x31C */ + __IO uint32_t LDORAMC; /**< RAM Control, offset: 0x320 */ + uint8_t RESERVED_7[12]; + __IO uint32_t LDOTIMER0; /**< Bandgap Timer 0, offset: 0x330 */ + uint8_t RESERVED_8[4]; + __IO uint32_t LDOTIMER1; /**< Bandgap Timer 1, offset: 0x338 */ + uint8_t RESERVED_9[196]; + __IO uint32_t MONCTLA; /**< CLKMON Control A, offset: 0x400 */ + __IO uint32_t MONCTLB; /**< CLKMON Control B, offset: 0x404 */ + __IO uint32_t MONCFGA; /**< CLKMON Configuration A, offset: 0x408 */ + __IO uint32_t MONCFGB; /**< CLKMON Configuration B, offset: 0x40C */ + uint8_t RESERVED_10[8]; + __IO uint32_t MONLCKA; /**< CLKMON Lock A, offset: 0x418 */ + __IO uint32_t MONLCKB; /**< CLKMON Lock B, offset: 0x41C */ + uint8_t RESERVED_11[224]; + __IO uint32_t TAMCTLA; /**< TAMPER Control A, offset: 0x500 */ + __IO uint32_t TAMCTLB; /**< TAMPER Control B, offset: 0x504 */ + uint8_t RESERVED_12[16]; + __IO uint32_t TAMLCKA; /**< TAMPER Lock A, offset: 0x518 */ + __IO uint32_t TAMLCKB; /**< TAMPER Lock B, offset: 0x51C */ + uint8_t RESERVED_13[224]; + __IO uint32_t SWICTLA; /**< Switch Control A, offset: 0x600 */ + __IO uint32_t SWICTLB; /**< Switch Control B, offset: 0x604 */ + uint8_t RESERVED_14[16]; + __IO uint32_t SWILCKA; /**< Switch Lock A, offset: 0x618 */ + __IO uint32_t SWILCKB; /**< Switch Lock B, offset: 0x61C */ + uint8_t RESERVED_15[224]; + struct { /* offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPB; /**< Wakeup 0 Register B, array offset: 0x704, array step: 0x8 */ + } WAKEUP[2]; + uint8_t RESERVED_16[232]; + __IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */ + __IO uint32_t WAKLCKB; /**< Wakeup Lock B, offset: 0x7FC */ +} VBAT_Type; + +/* ---------------------------------------------------------------------------- + -- VBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Register_Masks VBAT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VBAT_VERID_FEATURE_MASK (0xFFFFU) +#define VBAT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK) + +#define VBAT_VERID_MINOR_MASK (0xFF0000U) +#define VBAT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK) + +#define VBAT_VERID_MAJOR_MASK (0xFF000000U) +#define VBAT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name STATUSA - Status A */ +/*! @{ */ + +#define VBAT_STATUSA_POR_DET_MASK (0x1U) +#define VBAT_STATUSA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect Flag + * 0b0..Not reset + * 0b1..Reset + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_POR_DET_SHIFT)) & VBAT_STATUSA_POR_DET_MASK) + +#define VBAT_STATUSA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_STATUSA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wakeup Pin Flag + * 0b0..Not asserted + * 0b1..Asserted + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_WAKEUP_FLAG_SHIFT)) & VBAT_STATUSA_WAKEUP_FLAG_MASK) + +#define VBAT_STATUSA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_STATUSA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 Flag + * 0b0..Not reached + * 0b1..Reached + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER0_FLAG_SHIFT)) & VBAT_STATUSA_TIMER0_FLAG_MASK) + +#define VBAT_STATUSA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_STATUSA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 1 Flag + * 0b0..Not reached + * 0b1..Reached + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TIMER1_FLAG_SHIFT)) & VBAT_STATUSA_TIMER1_FLAG_MASK) + +#define VBAT_STATUSA_LDO_RDY_MASK (0x10U) +#define VBAT_STATUSA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disabled (not ready) + * 0b1..Enabled (ready) + */ +#define VBAT_STATUSA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LDO_RDY_SHIFT)) & VBAT_STATUSA_LDO_RDY_MASK) + +#define VBAT_STATUSA_OSC_RDY_MASK (0x20U) +#define VBAT_STATUSA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32k Ready + * 0b0..Disabled (clock not ready) + * 0b1..Enabled (clock ready) + */ +#define VBAT_STATUSA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_OSC_RDY_SHIFT)) & VBAT_STATUSA_OSC_RDY_MASK) + +#define VBAT_STATUSA_CLOCK_DET_MASK (0x40U) +#define VBAT_STATUSA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Clock error not detected + * 0b1..Clock error detected + */ +#define VBAT_STATUSA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CLOCK_DET_SHIFT)) & VBAT_STATUSA_CLOCK_DET_MASK) + +#define VBAT_STATUSA_CONFIG_DET_MASK (0x80U) +#define VBAT_STATUSA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_CONFIG_DET_SHIFT)) & VBAT_STATUSA_CONFIG_DET_MASK) + +#define VBAT_STATUSA_VOLT_DET_MASK (0x100U) +#define VBAT_STATUSA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define VBAT_STATUSA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_VOLT_DET_SHIFT)) & VBAT_STATUSA_VOLT_DET_MASK) + +#define VBAT_STATUSA_TEMP_DET_MASK (0x200U) +#define VBAT_STATUSA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Temperature error not detected + * 0b1..Temperature error detected + */ +#define VBAT_STATUSA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_TEMP_DET_SHIFT)) & VBAT_STATUSA_TEMP_DET_MASK) + +#define VBAT_STATUSA_LIGHT_DET_MASK (0x400U) +#define VBAT_STATUSA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Light error not detected + * 0b1..Light error detected + */ +#define VBAT_STATUSA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_LIGHT_DET_SHIFT)) & VBAT_STATUSA_LIGHT_DET_MASK) + +#define VBAT_STATUSA_SEC0_DET_MASK (0x1000U) +#define VBAT_STATUSA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Security input 0 not detected + * 0b1..Security input 0 detected + */ +#define VBAT_STATUSA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_SEC0_DET_SHIFT)) & VBAT_STATUSA_SEC0_DET_MASK) + +#define VBAT_STATUSA_IRQ0_DET_MASK (0x10000U) +#define VBAT_STATUSA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ0_DET_SHIFT)) & VBAT_STATUSA_IRQ0_DET_MASK) + +#define VBAT_STATUSA_IRQ1_DET_MASK (0x20000U) +#define VBAT_STATUSA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ1_DET_SHIFT)) & VBAT_STATUSA_IRQ1_DET_MASK) + +#define VBAT_STATUSA_IRQ2_DET_MASK (0x40000U) +#define VBAT_STATUSA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ2_DET_SHIFT)) & VBAT_STATUSA_IRQ2_DET_MASK) + +#define VBAT_STATUSA_IRQ3_DET_MASK (0x80000U) +#define VBAT_STATUSA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Not asserted + * 0b1..Asserted + */ +#define VBAT_STATUSA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSA_IRQ3_DET_SHIFT)) & VBAT_STATUSA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name STATUSB - Status B */ +/*! @{ */ + +#define VBAT_STATUSB_INVERSE_MASK (0xFFFFFU) +#define VBAT_STATUSB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_STATUSB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_STATUSB_INVERSE_SHIFT)) & VBAT_STATUSB_INVERSE_MASK) +/*! @} */ + +/*! @name IRQENA - Interrupt Enable A */ +/*! @{ */ + +#define VBAT_IRQENA_POR_DET_MASK (0x1U) +#define VBAT_IRQENA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_POR_DET_SHIFT)) & VBAT_IRQENA_POR_DET_MASK) + +#define VBAT_IRQENA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_IRQENA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wakeup Pin Flag + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_WAKEUP_FLAG_SHIFT)) & VBAT_IRQENA_WAKEUP_FLAG_MASK) + +#define VBAT_IRQENA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_IRQENA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER0_FLAG_SHIFT)) & VBAT_IRQENA_TIMER0_FLAG_MASK) + +#define VBAT_IRQENA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_IRQENA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 2 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TIMER1_FLAG_SHIFT)) & VBAT_IRQENA_TIMER1_FLAG_MASK) + +#define VBAT_IRQENA_LDO_RDY_MASK (0x10U) +#define VBAT_IRQENA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LDO_RDY_SHIFT)) & VBAT_IRQENA_LDO_RDY_MASK) + +#define VBAT_IRQENA_OSC_RDY_MASK (0x20U) +#define VBAT_IRQENA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32k Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_OSC_RDY_SHIFT)) & VBAT_IRQENA_OSC_RDY_MASK) + +#define VBAT_IRQENA_CLOCK_DET_MASK (0x40U) +#define VBAT_IRQENA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CLOCK_DET_SHIFT)) & VBAT_IRQENA_CLOCK_DET_MASK) + +#define VBAT_IRQENA_CONFIG_DET_MASK (0x80U) +#define VBAT_IRQENA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_CONFIG_DET_SHIFT)) & VBAT_IRQENA_CONFIG_DET_MASK) + +#define VBAT_IRQENA_VOLT_DET_MASK (0x100U) +#define VBAT_IRQENA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_VOLT_DET_SHIFT)) & VBAT_IRQENA_VOLT_DET_MASK) + +#define VBAT_IRQENA_TEMP_DET_MASK (0x200U) +#define VBAT_IRQENA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define VBAT_IRQENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_TEMP_DET_SHIFT)) & VBAT_IRQENA_TEMP_DET_MASK) + +#define VBAT_IRQENA_LIGHT_DET_MASK (0x400U) +#define VBAT_IRQENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_LIGHT_DET_SHIFT)) & VBAT_IRQENA_LIGHT_DET_MASK) + +#define VBAT_IRQENA_SEC0_DET_MASK (0x1000U) +#define VBAT_IRQENA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_SEC0_DET_SHIFT)) & VBAT_IRQENA_SEC0_DET_MASK) + +#define VBAT_IRQENA_IRQ0_DET_MASK (0x10000U) +#define VBAT_IRQENA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ0_DET_SHIFT)) & VBAT_IRQENA_IRQ0_DET_MASK) + +#define VBAT_IRQENA_IRQ1_DET_MASK (0x20000U) +#define VBAT_IRQENA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ1_DET_SHIFT)) & VBAT_IRQENA_IRQ1_DET_MASK) + +#define VBAT_IRQENA_IRQ2_DET_MASK (0x40000U) +#define VBAT_IRQENA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ2_DET_SHIFT)) & VBAT_IRQENA_IRQ2_DET_MASK) + +#define VBAT_IRQENA_IRQ3_DET_MASK (0x80000U) +#define VBAT_IRQENA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_IRQENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENA_IRQ3_DET_SHIFT)) & VBAT_IRQENA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name IRQENB - Interrupt Enable B */ +/*! @{ */ + +#define VBAT_IRQENB_INVERSE_MASK (0xFFFFFU) +#define VBAT_IRQENB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_IRQENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_IRQENB_INVERSE_SHIFT)) & VBAT_IRQENB_INVERSE_MASK) +/*! @} */ + +/*! @name WAKENA - Wake-up Enable A */ +/*! @{ */ + +#define VBAT_WAKENA_POR_DET_MASK (0x1U) +#define VBAT_WAKENA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_POR_DET_SHIFT)) & VBAT_WAKENA_POR_DET_MASK) + +#define VBAT_WAKENA_WAKEUP_FLAG_MASK (0x2U) +#define VBAT_WAKENA_WAKEUP_FLAG_SHIFT (1U) +/*! WAKEUP_FLAG - Wake-up Pin Flag + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_WAKEUP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_WAKEUP_FLAG_SHIFT)) & VBAT_WAKENA_WAKEUP_FLAG_MASK) + +#define VBAT_WAKENA_TIMER0_FLAG_MASK (0x4U) +#define VBAT_WAKENA_TIMER0_FLAG_SHIFT (2U) +/*! TIMER0_FLAG - Bandgap Timer 0 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TIMER0_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER0_FLAG_SHIFT)) & VBAT_WAKENA_TIMER0_FLAG_MASK) + +#define VBAT_WAKENA_TIMER1_FLAG_MASK (0x8U) +#define VBAT_WAKENA_TIMER1_FLAG_SHIFT (3U) +/*! TIMER1_FLAG - Bandgap Timer 2 + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TIMER1_FLAG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TIMER1_FLAG_SHIFT)) & VBAT_WAKENA_TIMER1_FLAG_MASK) + +#define VBAT_WAKENA_LDO_RDY_MASK (0x10U) +#define VBAT_WAKENA_LDO_RDY_SHIFT (4U) +/*! LDO_RDY - LDO Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LDO_RDY_SHIFT)) & VBAT_WAKENA_LDO_RDY_MASK) + +#define VBAT_WAKENA_OSC_RDY_MASK (0x20U) +#define VBAT_WAKENA_OSC_RDY_SHIFT (5U) +/*! OSC_RDY - OSC32K Ready + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_OSC_RDY(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_OSC_RDY_SHIFT)) & VBAT_WAKENA_OSC_RDY_MASK) + +#define VBAT_WAKENA_CLOCK_DET_MASK (0x40U) +#define VBAT_WAKENA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CLOCK_DET_SHIFT)) & VBAT_WAKENA_CLOCK_DET_MASK) + +#define VBAT_WAKENA_CONFIG_DET_MASK (0x80U) +#define VBAT_WAKENA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_CONFIG_DET_SHIFT)) & VBAT_WAKENA_CONFIG_DET_MASK) + +#define VBAT_WAKENA_VOLT_DET_MASK (0x100U) +#define VBAT_WAKENA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_VOLT_DET_SHIFT)) & VBAT_WAKENA_VOLT_DET_MASK) + +#define VBAT_WAKENA_TEMP_DET_MASK (0x200U) +#define VBAT_WAKENA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_TEMP_DET_SHIFT)) & VBAT_WAKENA_TEMP_DET_MASK) + +#define VBAT_WAKENA_LIGHT_DET_MASK (0x400U) +#define VBAT_WAKENA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_LIGHT_DET_SHIFT)) & VBAT_WAKENA_LIGHT_DET_MASK) + +#define VBAT_WAKENA_SEC0_DET_MASK (0x1000U) +#define VBAT_WAKENA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Disabled + * 0b1..Enabled + */ +#define VBAT_WAKENA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_SEC0_DET_SHIFT)) & VBAT_WAKENA_SEC0_DET_MASK) + +#define VBAT_WAKENA_IRQ0_DET_MASK (0x10000U) +#define VBAT_WAKENA_IRQ0_DET_SHIFT (16U) +/*! IRQ0_DET - Interrupt 0 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ0_DET_SHIFT)) & VBAT_WAKENA_IRQ0_DET_MASK) + +#define VBAT_WAKENA_IRQ1_DET_MASK (0x20000U) +#define VBAT_WAKENA_IRQ1_DET_SHIFT (17U) +/*! IRQ1_DET - Interrupt 1 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ1_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ1_DET_SHIFT)) & VBAT_WAKENA_IRQ1_DET_MASK) + +#define VBAT_WAKENA_IRQ2_DET_MASK (0x40000U) +#define VBAT_WAKENA_IRQ2_DET_SHIFT (18U) +/*! IRQ2_DET - Interrupt 2 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ2_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ2_DET_SHIFT)) & VBAT_WAKENA_IRQ2_DET_MASK) + +#define VBAT_WAKENA_IRQ3_DET_MASK (0x80000U) +#define VBAT_WAKENA_IRQ3_DET_SHIFT (19U) +/*! IRQ3_DET - Interrupt 3 Detect + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_WAKENA_IRQ3_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENA_IRQ3_DET_SHIFT)) & VBAT_WAKENA_IRQ3_DET_MASK) +/*! @} */ + +/*! @name WAKENB - Wake-up Enable B */ +/*! @{ */ + +#define VBAT_WAKENB_INVERSE_MASK (0xFFFFFU) +#define VBAT_WAKENB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_WAKENB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKENB_INVERSE_SHIFT)) & VBAT_WAKENB_INVERSE_MASK) +/*! @} */ + +/*! @name TAMPERA - Tamper Enable A */ +/*! @{ */ + +#define VBAT_TAMPERA_POR_DET_MASK (0x1U) +#define VBAT_TAMPERA_POR_DET_SHIFT (0U) +/*! POR_DET - POR Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_POR_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_POR_DET_SHIFT)) & VBAT_TAMPERA_POR_DET_MASK) + +#define VBAT_TAMPERA_CLOCK_DET_MASK (0x40U) +#define VBAT_TAMPERA_CLOCK_DET_SHIFT (6U) +/*! CLOCK_DET - Clock Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_CLOCK_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CLOCK_DET_SHIFT)) & VBAT_TAMPERA_CLOCK_DET_MASK) + +#define VBAT_TAMPERA_CONFIG_DET_MASK (0x80U) +#define VBAT_TAMPERA_CONFIG_DET_SHIFT (7U) +/*! CONFIG_DET - Configuration Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_CONFIG_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_CONFIG_DET_SHIFT)) & VBAT_TAMPERA_CONFIG_DET_MASK) + +#define VBAT_TAMPERA_VOLT_DET_MASK (0x100U) +#define VBAT_TAMPERA_VOLT_DET_SHIFT (8U) +/*! VOLT_DET - Voltage Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_VOLT_DET_SHIFT)) & VBAT_TAMPERA_VOLT_DET_MASK) + +#define VBAT_TAMPERA_TEMP_DET_MASK (0x200U) +#define VBAT_TAMPERA_TEMP_DET_SHIFT (9U) +/*! TEMP_DET - Temperature Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_TEMP_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_TEMP_DET_SHIFT)) & VBAT_TAMPERA_TEMP_DET_MASK) + +#define VBAT_TAMPERA_LIGHT_DET_MASK (0x400U) +#define VBAT_TAMPERA_LIGHT_DET_SHIFT (10U) +/*! LIGHT_DET - Light Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_LIGHT_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_LIGHT_DET_SHIFT)) & VBAT_TAMPERA_LIGHT_DET_MASK) + +#define VBAT_TAMPERA_SEC0_DET_MASK (0x1000U) +#define VBAT_TAMPERA_SEC0_DET_SHIFT (12U) +/*! SEC0_DET - Input 0 Detect + * 0b0..Tamper disabled + * 0b1..Tamper enabled + */ +#define VBAT_TAMPERA_SEC0_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERA_SEC0_DET_SHIFT)) & VBAT_TAMPERA_SEC0_DET_MASK) +/*! @} */ + +/*! @name TAMPERB - Tamper Enable B */ +/*! @{ */ + +#define VBAT_TAMPERB_INVERSE_MASK (0xFFFFU) +#define VBAT_TAMPERB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_TAMPERB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMPERB_INVERSE_SHIFT)) & VBAT_TAMPERB_INVERSE_MASK) +/*! @} */ + +/*! @name LOCKA - Lock A */ +/*! @{ */ + +#define VBAT_LOCKA_LOCK_MASK (0x1U) +#define VBAT_LOCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Disables lock + * 0b1..Enables lock. Cleared by VBAT POR. + */ +#define VBAT_LOCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKA_LOCK_SHIFT)) & VBAT_LOCKA_LOCK_MASK) +/*! @} */ + +/*! @name LOCKB - Lock B */ +/*! @{ */ + +#define VBAT_LOCKB_LOCK_MASK (0x1U) +#define VBAT_LOCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Disables lock + * 0b0..Enables lock + */ +#define VBAT_LOCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LOCKB_LOCK_SHIFT)) & VBAT_LOCKB_LOCK_MASK) +/*! @} */ + +/*! @name WAKECFG - Wake-up Configuration */ +/*! @{ */ + +#define VBAT_WAKECFG_OUT_MASK (0x1U) +#define VBAT_WAKECFG_OUT_SHIFT (0U) +/*! OUT - Output + * 0b0..Logic zero (asserted) + * 0b1..Logic one + */ +#define VBAT_WAKECFG_OUT(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKECFG_OUT_SHIFT)) & VBAT_WAKECFG_OUT_MASK) +/*! @} */ + +/*! @name OSCCTLA - Oscillator Control A */ +/*! @{ */ + +#define VBAT_OSCCTLA_OSC_EN_MASK (0x1U) +#define VBAT_OSCCTLA_OSC_EN_SHIFT (0U) +/*! OSC_EN - Crystal Oscillator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_OSCCTLA_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_EN_SHIFT)) & VBAT_OSCCTLA_OSC_EN_MASK) + +#define VBAT_OSCCTLA_OSC_BYP_EN_MASK (0x2U) +#define VBAT_OSCCTLA_OSC_BYP_EN_SHIFT (1U) +/*! OSC_BYP_EN - Crystal Oscillator Bypass Enable + * 0b0..Does not bypass + * 0b1..Bypass + */ +#define VBAT_OSCCTLA_OSC_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_OSC_BYP_EN_SHIFT)) & VBAT_OSCCTLA_OSC_BYP_EN_MASK) + +#define VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK (0xCU) +#define VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT (2U) +/*! COARSE_AMP_GAIN - Amplifier gain adjustment bits to allow the use of a wide range of external + * crystal ESR values See the device datasheet for the ranges supported by this device + * 0b00..ESR Range 0 + * 0b01..ESR Range 1 + * 0b10..ESR Range 2 + * 0b11..ESR Range 3 + */ +#define VBAT_OSCCTLA_COARSE_AMP_GAIN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_COARSE_AMP_GAIN_SHIFT)) & VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) + +#define VBAT_OSCCTLA_CAP_SEL_EN_MASK (0x80U) +#define VBAT_OSCCTLA_CAP_SEL_EN_SHIFT (7U) +/*! CAP_SEL_EN - Crystal Load Capacitance Selection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_OSCCTLA_CAP_SEL_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_CAP_SEL_EN_SHIFT)) & VBAT_OSCCTLA_CAP_SEL_EN_MASK) + +#define VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK (0xF00U) +#define VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT (8U) +/*! EXTAL_CAP_SEL - Crystal Load Capacitance Selection + * 0b0000..0 pF + * 0b0001..2 pF + * 0b0010..4 pF + * 0b0011..6 pF + * 0b0100..8 pF + * 0b0101..10 pF + * 0b0110..12 pF + * 0b0111..14 pF + * 0b1000..16 pF + * 0b1001..18 pF + * 0b1010..20 pF + * 0b1011..22 pF + * 0b1100..24 pF + * 0b1101..26 pF + * 0b1110..28 pF + * 0b1111..30 pF + */ +#define VBAT_OSCCTLA_EXTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_EXTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK) + +#define VBAT_OSCCTLA_XTAL_CAP_SEL_MASK (0xF000U) +#define VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT (12U) +/*! XTAL_CAP_SEL - Crystal Load Capacitance Selection + * 0b0000..0 pF + * 0b0001..2 pF + * 0b0010..4 pF + * 0b0011..6 pF + * 0b0100..8 pF + * 0b0101..10 pF + * 0b0110..12 pF + * 0b0111..14 pF + * 0b1000..16 pF + * 0b1001..18 pF + * 0b1010..20 pF + * 0b1011..22 pF + * 0b1100..24 pF + * 0b1101..26 pF + * 0b1110..28 pF + * 0b1111..30 pF + */ +#define VBAT_OSCCTLA_XTAL_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_XTAL_CAP_SEL_SHIFT)) & VBAT_OSCCTLA_XTAL_CAP_SEL_MASK) + +#define VBAT_OSCCTLA_MODE_EN_MASK (0x30000U) +#define VBAT_OSCCTLA_MODE_EN_SHIFT (16U) +/*! MODE_EN - Mode Enable + * 0b00..Normal mode + * 0b01..Startup mode + * 0b11..Low power mode + */ +#define VBAT_OSCCTLA_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_MODE_EN_SHIFT)) & VBAT_OSCCTLA_MODE_EN_MASK) + +#define VBAT_OSCCTLA_SUPPLY_DET_MASK (0xC0000U) +#define VBAT_OSCCTLA_SUPPLY_DET_SHIFT (18U) +/*! SUPPLY_DET - Supply Detector Trim + * 0b00..VBAT supply is less than 3V + * 0b01..VBAT supply is greater than 3V + */ +#define VBAT_OSCCTLA_SUPPLY_DET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLA_SUPPLY_DET_SHIFT)) & VBAT_OSCCTLA_SUPPLY_DET_MASK) +/*! @} */ + +/*! @name OSCCTLB - Oscillator Control B */ +/*! @{ */ + +#define VBAT_OSCCTLB_INVERSE_MASK (0xFFFFFU) +#define VBAT_OSCCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_OSCCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCTLB_INVERSE_SHIFT)) & VBAT_OSCCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name OSCCFGA - Oscillator Configuration A */ +/*! @{ */ + +#define VBAT_OSCCFGA_CMP_TRIM_MASK (0x3U) +#define VBAT_OSCCFGA_CMP_TRIM_SHIFT (0U) +/*! CMP_TRIM - Comparator Trim + * 0b00..760 mV + * 0b01..770 mV + * 0b11..740 mV + */ +#define VBAT_OSCCFGA_CMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CMP_TRIM_SHIFT)) & VBAT_OSCCFGA_CMP_TRIM_MASK) + +#define VBAT_OSCCFGA_CAP2_TRIM_MASK (0x4U) +#define VBAT_OSCCFGA_CAP2_TRIM_SHIFT (2U) +/*! CAP2_TRIM - CAP2_TRIM */ +#define VBAT_OSCCFGA_CAP2_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP2_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP2_TRIM_MASK) + +#define VBAT_OSCCFGA_DLY_TRIM_MASK (0x78U) +#define VBAT_OSCCFGA_DLY_TRIM_SHIFT (3U) +/*! DLY_TRIM - Delay Trim + * 0b0000..P current 9(nA) and N Current 6(nA) + * 0b0001..P current 13(nA) and N Current 6(nA) + * 0b0011..P current 4(nA) and N Current 6(nA) + * 0b0100..P current 9(nA) and N Current 4(nA) + * 0b0101..P current 13(nA) and N Current 4(nA) + * 0b0111..P current 4(nA) and N Current 4(nA) + * 0b1000..P current 9(nA) and N Current 2(nA) + * 0b1001..P current 13(nA) and N Current 2(nA) + * 0b1011..P current 4(nA) and N Current 2(nA) + */ +#define VBAT_OSCCFGA_DLY_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_DLY_TRIM_SHIFT)) & VBAT_OSCCFGA_DLY_TRIM_MASK) + +#define VBAT_OSCCFGA_CAP_TRIM_MASK (0x180U) +#define VBAT_OSCCFGA_CAP_TRIM_SHIFT (7U) +/*! CAP_TRIM - Capacitor Trim + * 0b00..Default (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 00 ) + * 0b01..-1us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 01) + * 0b10..-2us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 10) or or +3.5us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 10) + * 0b11..-2.5us (when CAP2_TRIM = 0 and CAP_TRIM[1:0] = 11) or +1us (when CAP2_TRIM = 1 and CAP_TRIM[1:0] = 11) + */ +#define VBAT_OSCCFGA_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_CAP_TRIM_SHIFT)) & VBAT_OSCCFGA_CAP_TRIM_MASK) + +#define VBAT_OSCCFGA_INIT_TRIM_MASK (0xE00U) +#define VBAT_OSCCFGA_INIT_TRIM_SHIFT (9U) +/*! INIT_TRIM - Initialization Trim + * 0b000..8 s + * 0b001..4 s + * 0b010..2 s + * 0b011..1 s + * 0b100..0.5 s + * 0b101..0.25 s + * 0b110..0.125 s + * 0b111..0.5 ms + */ +#define VBAT_OSCCFGA_INIT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGA_INIT_TRIM_SHIFT)) & VBAT_OSCCFGA_INIT_TRIM_MASK) +/*! @} */ + +/*! @name OSCCFGB - Oscillator Configuration B */ +/*! @{ */ + +#define VBAT_OSCCFGB_INVERSE_MASK (0xFFFU) +#define VBAT_OSCCFGB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_OSCCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCFGB_INVERSE_SHIFT)) & VBAT_OSCCFGB_INVERSE_MASK) +/*! @} */ + +/*! @name OSCLCKA - Oscillator Lock A */ +/*! @{ */ + +#define VBAT_OSCLCKA_LOCK_MASK (0x1U) +#define VBAT_OSCLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_OSCLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKA_LOCK_SHIFT)) & VBAT_OSCLCKA_LOCK_MASK) +/*! @} */ + +/*! @name OSCLCKB - Oscillator Lock B */ +/*! @{ */ + +#define VBAT_OSCLCKB_LOCK_MASK (0x1U) +#define VBAT_OSCLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_OSCLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCLCKB_LOCK_SHIFT)) & VBAT_OSCLCKB_LOCK_MASK) +/*! @} */ + +/*! @name OSCCLKE - Oscillator Clock Enable */ +/*! @{ */ + +#define VBAT_OSCCLKE_CLKE_MASK (0xFU) +#define VBAT_OSCCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_OSCCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_OSCCLKE_CLKE_SHIFT)) & VBAT_OSCCLKE_CLKE_MASK) +/*! @} */ + +/*! @name FROCTLA - FRO16K Control A */ +/*! @{ */ + +#define VBAT_FROCTLA_FRO_EN_MASK (0x1U) +#define VBAT_FROCTLA_FRO_EN_SHIFT (0U) +/*! FRO_EN - FRO16K Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK) +/*! @} */ + +/*! @name FROCTLB - FRO16K Control B */ +/*! @{ */ + +#define VBAT_FROCTLB_INVERSE_MASK (0x1U) +#define VBAT_FROCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_FROCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLB_INVERSE_SHIFT)) & VBAT_FROCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name FROLCKA - FRO16K Lock A */ +/*! @{ */ + +#define VBAT_FROLCKA_LOCK_MASK (0x1U) +#define VBAT_FROLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK) +/*! @} */ + +/*! @name FROLCKB - FRO16K Lock B */ +/*! @{ */ + +#define VBAT_FROLCKB_LOCK_MASK (0x1U) +#define VBAT_FROLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_FROLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKB_LOCK_SHIFT)) & VBAT_FROLCKB_LOCK_MASK) +/*! @} */ + +/*! @name FROCLKE - FRO16K Clock Enable */ +/*! @{ */ + +#define VBAT_FROCLKE_CLKE_MASK (0xFU) +#define VBAT_FROCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK) +/*! @} */ + +/*! @name LDOCTLA - LDO_RAM Control A */ +/*! @{ */ + +#define VBAT_LDOCTLA_BG_EN_MASK (0x1U) +#define VBAT_LDOCTLA_BG_EN_SHIFT (0U) +/*! BG_EN - Bandgap Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOCTLA_BG_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_BG_EN_SHIFT)) & VBAT_LDOCTLA_BG_EN_MASK) + +#define VBAT_LDOCTLA_LDO_EN_MASK (0x2U) +#define VBAT_LDOCTLA_LDO_EN_SHIFT (1U) +/*! LDO_EN - LDO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOCTLA_LDO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_LDO_EN_SHIFT)) & VBAT_LDOCTLA_LDO_EN_MASK) + +#define VBAT_LDOCTLA_REFRESH_EN_MASK (0x4U) +#define VBAT_LDOCTLA_REFRESH_EN_SHIFT (2U) +/*! REFRESH_EN - Refresh Enable + * 0b0..Refresh mode is disabled + * 0b1..Refresh mode is enabled for low power operation + */ +#define VBAT_LDOCTLA_REFRESH_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLA_REFRESH_EN_SHIFT)) & VBAT_LDOCTLA_REFRESH_EN_MASK) +/*! @} */ + +/*! @name LDOCTLB - LDO_RAM Control B */ +/*! @{ */ + +#define VBAT_LDOCTLB_INVERSE_MASK (0x7U) +#define VBAT_LDOCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_LDOCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOCTLB_INVERSE_SHIFT)) & VBAT_LDOCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name LDOLCKA - LDO_RAM Lock A */ +/*! @{ */ + +#define VBAT_LDOLCKA_LOCK_MASK (0x1U) +#define VBAT_LDOLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_LDOLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKA_LOCK_SHIFT)) & VBAT_LDOLCKA_LOCK_MASK) +/*! @} */ + +/*! @name LDOLCKB - LDO_RAM Lock B */ +/*! @{ */ + +#define VBAT_LDOLCKB_LOCK_MASK (0x1U) +#define VBAT_LDOLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_LDOLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOLCKB_LOCK_SHIFT)) & VBAT_LDOLCKB_LOCK_MASK) +/*! @} */ + +/*! @name LDORAMC - RAM Control */ +/*! @{ */ + +#define VBAT_LDORAMC_ISO_MASK (0x1U) +#define VBAT_LDORAMC_ISO_SHIFT (0U) +/*! ISO - Isolate SRAM + * 0b0..State follows the chip power modes + * 0b1..Isolates SRAM and places it in Low-Power Retention mode + */ +#define VBAT_LDORAMC_ISO(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_ISO_SHIFT)) & VBAT_LDORAMC_ISO_MASK) + +#define VBAT_LDORAMC_SWI_MASK (0x2U) +#define VBAT_LDORAMC_SWI_SHIFT (1U) +/*! SWI - Switch SRAM + * 0b0..Supply follows the chip power modes + * 0b1..LDO_RAM powers the array + */ +#define VBAT_LDORAMC_SWI(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_SWI_SHIFT)) & VBAT_LDORAMC_SWI_MASK) + +#define VBAT_LDORAMC_RET0_MASK (0x100U) +#define VBAT_LDORAMC_RET0_SHIFT (8U) +/*! RET0 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET0(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET0_SHIFT)) & VBAT_LDORAMC_RET0_MASK) + +#define VBAT_LDORAMC_RET1_MASK (0x200U) +#define VBAT_LDORAMC_RET1_SHIFT (9U) +/*! RET1 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET1(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET1_SHIFT)) & VBAT_LDORAMC_RET1_MASK) + +#define VBAT_LDORAMC_RET2_MASK (0x400U) +#define VBAT_LDORAMC_RET2_SHIFT (10U) +/*! RET2 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET2(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET2_SHIFT)) & VBAT_LDORAMC_RET2_MASK) + +#define VBAT_LDORAMC_RET3_MASK (0x800U) +#define VBAT_LDORAMC_RET3_SHIFT (11U) +/*! RET3 - Retention + * 0b0..Corresponding SRAM array is retained in low-power modes + * 0b1..Corresponding SRAM array is not retained in low-power modes + */ +#define VBAT_LDORAMC_RET3(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET3_SHIFT)) & VBAT_LDORAMC_RET3_MASK) +/*! @} */ + +/*! @name LDOTIMER0 - Bandgap Timer 0 */ +/*! @{ */ + +#define VBAT_LDOTIMER0_TIMCFG_MASK (0x7U) +#define VBAT_LDOTIMER0_TIMCFG_SHIFT (0U) +/*! TIMCFG - Timeout Configuration + * 0b111..7.8125 ms + * 0b110..15.625 ms + * 0b101..31.25 ms + * 0b100..62.5 ms + * 0b011..125 ms + * 0b010..250 ms + * 0b001..500 ms + * 0b000..1 s + */ +#define VBAT_LDOTIMER0_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMCFG_SHIFT)) & VBAT_LDOTIMER0_TIMCFG_MASK) + +#define VBAT_LDOTIMER0_TIMEN_MASK (0x80000000U) +#define VBAT_LDOTIMER0_TIMEN_SHIFT (31U) +/*! TIMEN - Bandgap Timeout Period Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOTIMER0_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER0_TIMEN_SHIFT)) & VBAT_LDOTIMER0_TIMEN_MASK) +/*! @} */ + +/*! @name LDOTIMER1 - Bandgap Timer 1 */ +/*! @{ */ + +#define VBAT_LDOTIMER1_TIMCFG_MASK (0xFFFFFFU) +#define VBAT_LDOTIMER1_TIMCFG_SHIFT (0U) +/*! TIMCFG - Timeout Configuration */ +#define VBAT_LDOTIMER1_TIMCFG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMCFG_SHIFT)) & VBAT_LDOTIMER1_TIMCFG_MASK) + +#define VBAT_LDOTIMER1_TIMEN_MASK (0x80000000U) +#define VBAT_LDOTIMER1_TIMEN_SHIFT (31U) +/*! TIMEN - Bandgap Timeout Period Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_LDOTIMER1_TIMEN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDOTIMER1_TIMEN_SHIFT)) & VBAT_LDOTIMER1_TIMEN_MASK) +/*! @} */ + +/*! @name MONCTLA - CLKMON Control A */ +/*! @{ */ + +#define VBAT_MONCTLA_MON_EN_MASK (0x1U) +#define VBAT_MONCTLA_MON_EN_SHIFT (0U) +/*! MON_EN - CLKMON Enable + * 0b0..CLKMON is disabled + * 0b1..CLKMON is enabled + */ +#define VBAT_MONCTLA_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLA_MON_EN_SHIFT)) & VBAT_MONCTLA_MON_EN_MASK) +/*! @} */ + +/*! @name MONCTLB - CLKMON Control B */ +/*! @{ */ + +#define VBAT_MONCTLB_INVERSE_MASK (0x1U) +#define VBAT_MONCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_MONCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCTLB_INVERSE_SHIFT)) & VBAT_MONCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name MONCFGA - CLKMON Configuration A */ +/*! @{ */ + +#define VBAT_MONCFGA_FREQ_TRIM_MASK (0x3U) +#define VBAT_MONCFGA_FREQ_TRIM_SHIFT (0U) +/*! FREQ_TRIM - Frequency Trim + * 0b00..Clock monitor asserts 2 cycle after expected edge + * 0b01..Clock monitor asserts 4 cycles after expected edge + * 0b10..Clock monitor asserts 6 cycles after expected edge + * 0b11..Clock monitor asserts 8 cycles after expected edge + */ +#define VBAT_MONCFGA_FREQ_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_FREQ_TRIM_SHIFT)) & VBAT_MONCFGA_FREQ_TRIM_MASK) + +#define VBAT_MONCFGA_DIVIDE_TRIM_MASK (0x4U) +#define VBAT_MONCFGA_DIVIDE_TRIM_SHIFT (2U) +/*! DIVIDE_TRIM - Divide Trim + * 0b0..Clock monitor operates at 1 kHz + * 0b1..Clock monitor operates at 64 Hz + */ +#define VBAT_MONCFGA_DIVIDE_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_DIVIDE_TRIM_SHIFT)) & VBAT_MONCFGA_DIVIDE_TRIM_MASK) + +#define VBAT_MONCFGA_RSVD_TRIM_MASK (0xF8U) +#define VBAT_MONCFGA_RSVD_TRIM_SHIFT (3U) +/*! RSVD_TRIM - Reserved Trim */ +#define VBAT_MONCFGA_RSVD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGA_RSVD_TRIM_SHIFT)) & VBAT_MONCFGA_RSVD_TRIM_MASK) +/*! @} */ + +/*! @name MONCFGB - CLKMON Configuration B */ +/*! @{ */ + +#define VBAT_MONCFGB_INVERSE_MASK (0xFFU) +#define VBAT_MONCFGB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_MONCFGB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONCFGB_INVERSE_SHIFT)) & VBAT_MONCFGB_INVERSE_MASK) +/*! @} */ + +/*! @name MONLCKA - CLKMON Lock A */ +/*! @{ */ + +#define VBAT_MONLCKA_LOCK_MASK (0x1U) +#define VBAT_MONLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_MONLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKA_LOCK_SHIFT)) & VBAT_MONLCKA_LOCK_MASK) +/*! @} */ + +/*! @name MONLCKB - CLKMON Lock B */ +/*! @{ */ + +#define VBAT_MONLCKB_LOCK_MASK (0x1U) +#define VBAT_MONLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_MONLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_MONLCKB_LOCK_SHIFT)) & VBAT_MONLCKB_LOCK_MASK) +/*! @} */ + +/*! @name TAMCTLA - TAMPER Control A */ +/*! @{ */ + +#define VBAT_TAMCTLA_VOLT_EN_MASK (0x1U) +#define VBAT_TAMCTLA_VOLT_EN_SHIFT (0U) +/*! VOLT_EN - Voltage Detect Enable + * 0b0..Voltage detect is disabled + * 0b1..Voltage detect is enabled + */ +#define VBAT_TAMCTLA_VOLT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_VOLT_EN_SHIFT)) & VBAT_TAMCTLA_VOLT_EN_MASK) + +#define VBAT_TAMCTLA_TEMP_EN_MASK (0x2U) +#define VBAT_TAMCTLA_TEMP_EN_SHIFT (1U) +/*! TEMP_EN - Temperature Detect Enable + * 0b0..Temperature detect is disabled + * 0b1..Temperature detect is enabled + */ +#define VBAT_TAMCTLA_TEMP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_TEMP_EN_SHIFT)) & VBAT_TAMCTLA_TEMP_EN_MASK) + +#define VBAT_TAMCTLA_LIGHT_EN_MASK (0x4U) +#define VBAT_TAMCTLA_LIGHT_EN_SHIFT (2U) +/*! LIGHT_EN - Light Detect Enable + * 0b0..Light detect is disabled + * 0b1..Light detect is enabled + */ +#define VBAT_TAMCTLA_LIGHT_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLA_LIGHT_EN_SHIFT)) & VBAT_TAMCTLA_LIGHT_EN_MASK) +/*! @} */ + +/*! @name TAMCTLB - TAMPER Control B */ +/*! @{ */ + +#define VBAT_TAMCTLB_INVERSE_MASK (0xFU) +#define VBAT_TAMCTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_TAMCTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMCTLB_INVERSE_SHIFT)) & VBAT_TAMCTLB_INVERSE_MASK) +/*! @} */ + +/*! @name TAMLCKA - TAMPER Lock A */ +/*! @{ */ + +#define VBAT_TAMLCKA_LOCK_MASK (0x1U) +#define VBAT_TAMLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_TAMLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKA_LOCK_SHIFT)) & VBAT_TAMLCKA_LOCK_MASK) +/*! @} */ + +/*! @name TAMLCKB - TAMPER Lock B */ +/*! @{ */ + +#define VBAT_TAMLCKB_LOCK_MASK (0x1U) +#define VBAT_TAMLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_TAMLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_TAMLCKB_LOCK_SHIFT)) & VBAT_TAMLCKB_LOCK_MASK) +/*! @} */ + +/*! @name SWICTLA - Switch Control A */ +/*! @{ */ + +#define VBAT_SWICTLA_SWI_EN_MASK (0x1U) +#define VBAT_SWICTLA_SWI_EN_SHIFT (0U) +/*! SWI_EN - Switch Enable + * 0b0..VDD_BAT + * 0b1..VDD_SYS + */ +#define VBAT_SWICTLA_SWI_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_SWI_EN_SHIFT)) & VBAT_SWICTLA_SWI_EN_MASK) + +#define VBAT_SWICTLA_LP_EN_MASK (0x2U) +#define VBAT_SWICTLA_LP_EN_SHIFT (1U) +/*! LP_EN - Low Power Enable + * 0b0..VDD_BAT always supplies VBAT modules in low-power modes + * 0b1..VDD_SYS always supplies VBAT modules if SWI_EN is also 1 + */ +#define VBAT_SWICTLA_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLA_LP_EN_SHIFT)) & VBAT_SWICTLA_LP_EN_MASK) +/*! @} */ + +/*! @name SWICTLB - Switch Control B */ +/*! @{ */ + +#define VBAT_SWICTLB_INVERSE_MASK (0x3U) +#define VBAT_SWICTLB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse Value */ +#define VBAT_SWICTLB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWICTLB_INVERSE_SHIFT)) & VBAT_SWICTLB_INVERSE_MASK) +/*! @} */ + +/*! @name SWILCKA - Switch Lock A */ +/*! @{ */ + +#define VBAT_SWILCKA_LOCK_MASK (0x1U) +#define VBAT_SWILCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_SWILCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKA_LOCK_SHIFT)) & VBAT_SWILCKA_LOCK_MASK) +/*! @} */ + +/*! @name SWILCKB - Switch Lock B */ +/*! @{ */ + +#define VBAT_SWILCKB_LOCK_MASK (0x1U) +#define VBAT_SWILCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Do not block + * 0b0..Block + */ +#define VBAT_SWILCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_SWILCKB_LOCK_SHIFT)) & VBAT_SWILCKB_LOCK_MASK) +/*! @} */ + +/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U) +/*! REG - Register */ +#define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPA */ +#define VBAT_WAKEUP_WAKEUPA_COUNT (2U) + +/*! @name WAKEUP_WAKEUPB - Wakeup 0 Register B */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPB_INVERSE_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT (0U) +/*! INVERSE - Inverse value */ +#define VBAT_WAKEUP_WAKEUPB_INVERSE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPB_INVERSE_SHIFT)) & VBAT_WAKEUP_WAKEUPB_INVERSE_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPB */ +#define VBAT_WAKEUP_WAKEUPB_COUNT (2U) + +/*! @name WAKLCKA - Wakeup Lock A */ +/*! @{ */ + +#define VBAT_WAKLCKA_LOCK_MASK (0x1U) +#define VBAT_WAKLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK) +/*! @} */ + +/*! @name WAKLCKB - Wakeup Lock B */ +/*! @{ */ + +#define VBAT_WAKLCKB_LOCK_MASK (0x1U) +#define VBAT_WAKLCKB_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b1..Lock is disabled + * 0b0..Lock is enabled + */ +#define VBAT_WAKLCKB_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKB_LOCK_SHIFT)) & VBAT_WAKLCKB_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VBAT_Register_Masks */ + + +/* VBAT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x50059000u) + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE_NS (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Peripheral VBAT0 base pointer */ + #define VBAT0_NS ((VBAT_Type *)VBAT0_BASE_NS) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS_NS { VBAT0_BASE_NS } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS_NS { VBAT0_NS } +#else + /** Peripheral VBAT0 base address */ + #define VBAT0_BASE (0x40059000u) + /** Peripheral VBAT0 base pointer */ + #define VBAT0 ((VBAT_Type *)VBAT0_BASE) + /** Array initializer of VBAT peripheral base addresses */ + #define VBAT_BASE_ADDRS { VBAT0_BASE } + /** Array initializer of VBAT peripheral base pointers */ + #define VBAT_BASE_PTRS { VBAT0 } +#endif + +/*! + * @} + */ /* end of group VBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VREF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer + * @{ + */ + +/** VREF - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSR; /**< Control and Status, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t UTRIM; /**< User Trim, offset: 0x10 */ +} VREF_Type; + +/* ---------------------------------------------------------------------------- + -- VREF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VREF_Register_Masks VREF Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VREF_VERID_FEATURE_MASK (0xFFFFU) +#define VREF_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VREF_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_FEATURE_SHIFT)) & VREF_VERID_FEATURE_MASK) + +#define VREF_VERID_MINOR_MASK (0xFF0000U) +#define VREF_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VREF_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MINOR_SHIFT)) & VREF_VERID_MINOR_MASK) + +#define VREF_VERID_MAJOR_MASK (0xFF000000U) +#define VREF_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VREF_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VREF_VERID_MAJOR_SHIFT)) & VREF_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CSR - Control and Status */ +/*! @{ */ + +#define VREF_CSR_HCBGEN_MASK (0x1U) +#define VREF_CSR_HCBGEN_SHIFT (0U) +/*! HCBGEN - HC Bandgap Enabled + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_HCBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HCBGEN_SHIFT)) & VREF_CSR_HCBGEN_MASK) + +#define VREF_CSR_LPBGEN_MASK (0x2U) +#define VREF_CSR_LPBGEN_SHIFT (1U) +/*! LPBGEN - Low-Power Bandgap Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_LPBGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBGEN_SHIFT)) & VREF_CSR_LPBGEN_MASK) + +#define VREF_CSR_LPBG_BUF_EN_MASK (0x4U) +#define VREF_CSR_LPBG_BUF_EN_SHIFT (2U) +/*! LPBG_BUF_EN - Low-Power Bandgap Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_LPBG_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_LPBG_BUF_EN_SHIFT)) & VREF_CSR_LPBG_BUF_EN_MASK) + +#define VREF_CSR_CHOPEN_MASK (0x8U) +#define VREF_CSR_CHOPEN_SHIFT (3U) +/*! CHOPEN - Chop Oscillator Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_CHOPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_CHOPEN_SHIFT)) & VREF_CSR_CHOPEN_MASK) + +#define VREF_CSR_ICOMPEN_MASK (0x10U) +#define VREF_CSR_ICOMPEN_SHIFT (4U) +/*! ICOMPEN - Current Compensation Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_ICOMPEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_ICOMPEN_SHIFT)) & VREF_CSR_ICOMPEN_MASK) + +#define VREF_CSR_REGEN_MASK (0x20U) +#define VREF_CSR_REGEN_SHIFT (5U) +/*! REGEN - Regulator Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_REGEN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_REGEN_SHIFT)) & VREF_CSR_REGEN_MASK) + +#define VREF_CSR_HI_PWR_LV_MASK (0x800U) +#define VREF_CSR_HI_PWR_LV_SHIFT (11U) +/*! HI_PWR_LV - High-Power Level + * 0b0..Low-power + * 0b1..High-power + */ +#define VREF_CSR_HI_PWR_LV(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_HI_PWR_LV_SHIFT)) & VREF_CSR_HI_PWR_LV_MASK) + +#define VREF_CSR_BUF21EN_MASK (0x10000U) +#define VREF_CSR_BUF21EN_SHIFT (16U) +/*! BUF21EN - Internal Buffer21 Enable + * 0b0..Disables + * 0b1..Enables + */ +#define VREF_CSR_BUF21EN(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_BUF21EN_SHIFT)) & VREF_CSR_BUF21EN_MASK) + +#define VREF_CSR_VREFST_MASK (0x80000000U) +#define VREF_CSR_VREFST_SHIFT (31U) +/*! VREFST - Internal HC Voltage Reference Stable + * 0b0..Disabled and unstable + * 0b1..Stable + */ +#define VREF_CSR_VREFST(x) (((uint32_t)(((uint32_t)(x)) << VREF_CSR_VREFST_SHIFT)) & VREF_CSR_VREFST_MASK) +/*! @} */ + +/*! @name UTRIM - User Trim */ +/*! @{ */ + +#define VREF_UTRIM_TRIM2V1_MASK (0xFU) +#define VREF_UTRIM_TRIM2V1_SHIFT (0U) +/*! TRIM2V1 - VREF 2.1 V Trim */ +#define VREF_UTRIM_TRIM2V1(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_TRIM2V1_SHIFT)) & VREF_UTRIM_TRIM2V1_MASK) + +#define VREF_UTRIM_VREFTRIM_MASK (0x3F00U) +#define VREF_UTRIM_VREFTRIM_SHIFT (8U) +/*! VREFTRIM - VREF Trim */ +#define VREF_UTRIM_VREFTRIM(x) (((uint32_t)(((uint32_t)(x)) << VREF_UTRIM_VREFTRIM_SHIFT)) & VREF_UTRIM_VREFTRIM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VREF_Register_Masks */ + + +/* VREF - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x50111000u) + /** Peripheral VREF0 base address */ + #define VREF0_BASE_NS (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Peripheral VREF0 base pointer */ + #define VREF0_NS ((VREF_Type *)VREF0_BASE_NS) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS_NS { VREF0_BASE_NS } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS_NS { VREF0_NS } +#else + /** Peripheral VREF0 base address */ + #define VREF0_BASE (0x40111000u) + /** Peripheral VREF0 base pointer */ + #define VREF0 ((VREF_Type *)VREF0_BASE) + /** Array initializer of VREF peripheral base addresses */ + #define VREF_BASE_ADDRS { VREF0_BASE } + /** Array initializer of VREF peripheral base pointers */ + #define VREF_BASE_PTRS { VREF0 } +#endif + +/*! + * @} + */ /* end of group VREF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WUU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer + * @{ + */ + +/** WUU - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */ + __IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */ + uint8_t RESERVED_0[8]; + __IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */ + __IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */ + __IO uint32_t PF; /**< Pin Flag, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */ + __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */ + uint8_t RESERVED_3[8]; + __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */ +} WUU_Type; + +/* ---------------------------------------------------------------------------- + -- WUU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Register_Masks WUU Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define WUU_VERID_FEATURE_MASK (0xFFFFU) +#define WUU_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for + * external pin/filter detection during all power modes enabled. + * *.. + */ +#define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) + +#define WUU_VERID_MINOR_MASK (0xFF0000U) +#define WUU_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK) + +#define WUU_VERID_MAJOR_MASK (0xFF000000U) +#define WUU_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define WUU_PARAM_FILTERS_MASK (0xFFU) +#define WUU_PARAM_FILTERS_SHIFT (0U) +/*! FILTERS - Filter Number */ +#define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK) + +#define WUU_PARAM_DMAS_MASK (0xFF00U) +#define WUU_PARAM_DMAS_SHIFT (8U) +/*! DMAS - DMA Number */ +#define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK) + +#define WUU_PARAM_MODULES_MASK (0xFF0000U) +#define WUU_PARAM_MODULES_SHIFT (16U) +/*! MODULES - Module Number */ +#define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK) + +#define WUU_PARAM_PINS_MASK (0xFF000000U) +#define WUU_PARAM_PINS_SHIFT (24U) +/*! PINS - Pin Number */ +#define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK) +/*! @} */ + +/*! @name PE1 - Pin Enable 1 */ +/*! @{ */ + +#define WUU_PE1_WUPE0_MASK (0x3U) +#define WUU_PE1_WUPE0_SHIFT (0U) +/*! WUPE0 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE0_SHIFT)) & WUU_PE1_WUPE0_MASK) + +#define WUU_PE1_WUPE1_MASK (0xCU) +#define WUU_PE1_WUPE1_SHIFT (2U) +/*! WUPE1 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE1_SHIFT)) & WUU_PE1_WUPE1_MASK) + +#define WUU_PE1_WUPE2_MASK (0x30U) +#define WUU_PE1_WUPE2_SHIFT (4U) +/*! WUPE2 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK) + +#define WUU_PE1_WUPE3_MASK (0xC0U) +#define WUU_PE1_WUPE3_SHIFT (6U) +/*! WUPE3 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE3_SHIFT)) & WUU_PE1_WUPE3_MASK) + +#define WUU_PE1_WUPE4_MASK (0x300U) +#define WUU_PE1_WUPE4_SHIFT (8U) +/*! WUPE4 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE4_SHIFT)) & WUU_PE1_WUPE4_MASK) + +#define WUU_PE1_WUPE5_MASK (0xC00U) +#define WUU_PE1_WUPE5_SHIFT (10U) +/*! WUPE5 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE5_SHIFT)) & WUU_PE1_WUPE5_MASK) + +#define WUU_PE1_WUPE6_MASK (0x3000U) +#define WUU_PE1_WUPE6_SHIFT (12U) +/*! WUPE6 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK) + +#define WUU_PE1_WUPE7_MASK (0xC000U) +#define WUU_PE1_WUPE7_SHIFT (14U) +/*! WUPE7 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK) + +#define WUU_PE1_WUPE8_MASK (0x30000U) +#define WUU_PE1_WUPE8_SHIFT (16U) +/*! WUPE8 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK) + +#define WUU_PE1_WUPE9_MASK (0xC0000U) +#define WUU_PE1_WUPE9_SHIFT (18U) +/*! WUPE9 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK) + +#define WUU_PE1_WUPE10_MASK (0x300000U) +#define WUU_PE1_WUPE10_SHIFT (20U) +/*! WUPE10 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK) + +#define WUU_PE1_WUPE11_MASK (0xC00000U) +#define WUU_PE1_WUPE11_SHIFT (22U) +/*! WUPE11 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK) + +#define WUU_PE1_WUPE12_MASK (0x3000000U) +#define WUU_PE1_WUPE12_SHIFT (24U) +/*! WUPE12 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK) + +#define WUU_PE1_WUPE13_MASK (0xC000000U) +#define WUU_PE1_WUPE13_SHIFT (26U) +/*! WUPE13 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE13_SHIFT)) & WUU_PE1_WUPE13_MASK) + +#define WUU_PE1_WUPE14_MASK (0x30000000U) +#define WUU_PE1_WUPE14_SHIFT (28U) +/*! WUPE14 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE14_SHIFT)) & WUU_PE1_WUPE14_MASK) + +#define WUU_PE1_WUPE15_MASK (0xC0000000U) +#define WUU_PE1_WUPE15_SHIFT (30U) +/*! WUPE15 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE15_SHIFT)) & WUU_PE1_WUPE15_MASK) +/*! @} */ + +/*! @name PE2 - Pin Enable 2 */ +/*! @{ */ + +#define WUU_PE2_WUPE16_MASK (0x3U) +#define WUU_PE2_WUPE16_SHIFT (0U) +/*! WUPE16 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK) + +#define WUU_PE2_WUPE17_MASK (0xCU) +#define WUU_PE2_WUPE17_SHIFT (2U) +/*! WUPE17 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK) + +#define WUU_PE2_WUPE18_MASK (0x30U) +#define WUU_PE2_WUPE18_SHIFT (4U) +/*! WUPE18 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK) + +#define WUU_PE2_WUPE19_MASK (0xC0U) +#define WUU_PE2_WUPE19_SHIFT (6U) +/*! WUPE19 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK) + +#define WUU_PE2_WUPE20_MASK (0x300U) +#define WUU_PE2_WUPE20_SHIFT (8U) +/*! WUPE20 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK) + +#define WUU_PE2_WUPE21_MASK (0xC00U) +#define WUU_PE2_WUPE21_SHIFT (10U) +/*! WUPE21 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE21_SHIFT)) & WUU_PE2_WUPE21_MASK) + +#define WUU_PE2_WUPE22_MASK (0x3000U) +#define WUU_PE2_WUPE22_SHIFT (12U) +/*! WUPE22 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK) + +#define WUU_PE2_WUPE23_MASK (0xC000U) +#define WUU_PE2_WUPE23_SHIFT (14U) +/*! WUPE23 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK) + +#define WUU_PE2_WUPE24_MASK (0x30000U) +#define WUU_PE2_WUPE24_SHIFT (16U) +/*! WUPE24 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK) + +#define WUU_PE2_WUPE25_MASK (0xC0000U) +#define WUU_PE2_WUPE25_SHIFT (18U) +/*! WUPE25 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK) + +#define WUU_PE2_WUPE26_MASK (0x300000U) +#define WUU_PE2_WUPE26_SHIFT (20U) +/*! WUPE26 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK) + +#define WUU_PE2_WUPE27_MASK (0xC00000U) +#define WUU_PE2_WUPE27_SHIFT (22U) +/*! WUPE27 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK) + +#define WUU_PE2_Reserved28_MASK (0x3000000U) +#define WUU_PE2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved28_SHIFT)) & WUU_PE2_Reserved28_MASK) + +#define WUU_PE2_Reserved29_MASK (0xC000000U) +#define WUU_PE2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved29_SHIFT)) & WUU_PE2_Reserved29_MASK) + +#define WUU_PE2_Reserved30_MASK (0x30000000U) +#define WUU_PE2_Reserved30_SHIFT (28U) +/*! Reserved30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved30_SHIFT)) & WUU_PE2_Reserved30_MASK) + +#define WUU_PE2_Reserved31_MASK (0xC0000000U) +#define WUU_PE2_Reserved31_SHIFT (30U) +/*! Reserved31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved31_SHIFT)) & WUU_PE2_Reserved31_MASK) +/*! @} */ + +/*! @name ME - Module Interrupt Enable */ +/*! @{ */ + +#define WUU_ME_WUME0_MASK (0x1U) +#define WUU_ME_WUME0_SHIFT (0U) +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) + +#define WUU_ME_WUME1_MASK (0x2U) +#define WUU_ME_WUME1_SHIFT (1U) +/*! WUME1 - Module Interrupt Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME1(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME1_SHIFT)) & WUU_ME_WUME1_MASK) + +#define WUU_ME_WUME2_MASK (0x4U) +#define WUU_ME_WUME2_SHIFT (2U) +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) + +#define WUU_ME_WUME3_MASK (0x8U) +#define WUU_ME_WUME3_SHIFT (3U) +/*! WUME3 - Module Interrupt Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME3(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME3_SHIFT)) & WUU_ME_WUME3_MASK) + +#define WUU_ME_WUME4_MASK (0x10U) +#define WUU_ME_WUME4_SHIFT (4U) +/*! WUME4 - Module Interrupt Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME4(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME4_SHIFT)) & WUU_ME_WUME4_MASK) + +#define WUU_ME_WUME5_MASK (0x20U) +#define WUU_ME_WUME5_SHIFT (5U) +/*! WUME5 - Module Interrupt Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME5(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME5_SHIFT)) & WUU_ME_WUME5_MASK) + +#define WUU_ME_WUME6_MASK (0x40U) +#define WUU_ME_WUME6_SHIFT (6U) +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) + +#define WUU_ME_WUME7_MASK (0x80U) +#define WUU_ME_WUME7_SHIFT (7U) +/*! WUME7 - Module Interrupt Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME7(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME7_SHIFT)) & WUU_ME_WUME7_MASK) + +#define WUU_ME_WUME8_MASK (0x100U) +#define WUU_ME_WUME8_SHIFT (8U) +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) + +#define WUU_ME_WUME9_MASK (0x200U) +#define WUU_ME_WUME9_SHIFT (9U) +/*! WUME9 - Module Interrupt Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME9(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME9_SHIFT)) & WUU_ME_WUME9_MASK) +/*! @} */ + +/*! @name DE - Module DMA/Trigger Enable */ +/*! @{ */ + +#define WUU_DE_WUDE0_MASK (0x1U) +#define WUU_DE_WUDE0_SHIFT (0U) +/*! WUDE0 - DMA/Trigger Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE0(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE0_SHIFT)) & WUU_DE_WUDE0_MASK) + +#define WUU_DE_WUDE1_MASK (0x2U) +#define WUU_DE_WUDE1_SHIFT (1U) +/*! WUDE1 - DMA/Trigger Wake-up Enable for Module 1 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE1_SHIFT)) & WUU_DE_WUDE1_MASK) + +#define WUU_DE_WUDE2_MASK (0x4U) +#define WUU_DE_WUDE2_SHIFT (2U) +/*! WUDE2 - DMA/Trigger Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE2_SHIFT)) & WUU_DE_WUDE2_MASK) + +#define WUU_DE_WUDE3_MASK (0x8U) +#define WUU_DE_WUDE3_SHIFT (3U) +/*! WUDE3 - DMA/Trigger Wake-up Enable for Module 3 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE3(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE3_SHIFT)) & WUU_DE_WUDE3_MASK) + +#define WUU_DE_WUDE4_MASK (0x10U) +#define WUU_DE_WUDE4_SHIFT (4U) +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) + +#define WUU_DE_WUDE5_MASK (0x20U) +#define WUU_DE_WUDE5_SHIFT (5U) +/*! WUDE5 - DMA/Trigger Wake-up Enable for Module 5 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE5(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE5_SHIFT)) & WUU_DE_WUDE5_MASK) + +#define WUU_DE_WUDE6_MASK (0x40U) +#define WUU_DE_WUDE6_SHIFT (6U) +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) + +#define WUU_DE_WUDE7_MASK (0x80U) +#define WUU_DE_WUDE7_SHIFT (7U) +/*! WUDE7 - DMA/Trigger Wake-up Enable for Module 7 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE7_SHIFT)) & WUU_DE_WUDE7_MASK) + +#define WUU_DE_WUDE8_MASK (0x100U) +#define WUU_DE_WUDE8_SHIFT (8U) +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) + +#define WUU_DE_WUDE9_MASK (0x200U) +#define WUU_DE_WUDE9_SHIFT (9U) +/*! WUDE9 - DMA/Trigger Wake-up Enable for Module 9 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE9_SHIFT)) & WUU_DE_WUDE9_MASK) +/*! @} */ + +/*! @name PF - Pin Flag */ +/*! @{ */ + +#define WUU_PF_WUF0_MASK (0x1U) +#define WUU_PF_WUF0_SHIFT (0U) +/*! WUF0 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF0_SHIFT)) & WUU_PF_WUF0_MASK) + +#define WUU_PF_WUF1_MASK (0x2U) +#define WUU_PF_WUF1_SHIFT (1U) +/*! WUF1 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF1_SHIFT)) & WUU_PF_WUF1_MASK) + +#define WUU_PF_WUF2_MASK (0x4U) +#define WUU_PF_WUF2_SHIFT (2U) +/*! WUF2 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK) + +#define WUU_PF_WUF3_MASK (0x8U) +#define WUU_PF_WUF3_SHIFT (3U) +/*! WUF3 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF3_SHIFT)) & WUU_PF_WUF3_MASK) + +#define WUU_PF_WUF4_MASK (0x10U) +#define WUU_PF_WUF4_SHIFT (4U) +/*! WUF4 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF4_SHIFT)) & WUU_PF_WUF4_MASK) + +#define WUU_PF_WUF5_MASK (0x20U) +#define WUU_PF_WUF5_SHIFT (5U) +/*! WUF5 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF5_SHIFT)) & WUU_PF_WUF5_MASK) + +#define WUU_PF_WUF6_MASK (0x40U) +#define WUU_PF_WUF6_SHIFT (6U) +/*! WUF6 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK) + +#define WUU_PF_WUF7_MASK (0x80U) +#define WUU_PF_WUF7_SHIFT (7U) +/*! WUF7 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK) + +#define WUU_PF_WUF8_MASK (0x100U) +#define WUU_PF_WUF8_SHIFT (8U) +/*! WUF8 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK) + +#define WUU_PF_WUF9_MASK (0x200U) +#define WUU_PF_WUF9_SHIFT (9U) +/*! WUF9 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK) + +#define WUU_PF_WUF10_MASK (0x400U) +#define WUU_PF_WUF10_SHIFT (10U) +/*! WUF10 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK) + +#define WUU_PF_WUF11_MASK (0x800U) +#define WUU_PF_WUF11_SHIFT (11U) +/*! WUF11 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK) + +#define WUU_PF_WUF12_MASK (0x1000U) +#define WUU_PF_WUF12_SHIFT (12U) +/*! WUF12 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK) + +#define WUU_PF_WUF13_MASK (0x2000U) +#define WUU_PF_WUF13_SHIFT (13U) +/*! WUF13 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF13_SHIFT)) & WUU_PF_WUF13_MASK) + +#define WUU_PF_WUF14_MASK (0x4000U) +#define WUU_PF_WUF14_SHIFT (14U) +/*! WUF14 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF14_SHIFT)) & WUU_PF_WUF14_MASK) + +#define WUU_PF_WUF15_MASK (0x8000U) +#define WUU_PF_WUF15_SHIFT (15U) +/*! WUF15 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF15_SHIFT)) & WUU_PF_WUF15_MASK) + +#define WUU_PF_WUF16_MASK (0x10000U) +#define WUU_PF_WUF16_SHIFT (16U) +/*! WUF16 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK) + +#define WUU_PF_WUF17_MASK (0x20000U) +#define WUU_PF_WUF17_SHIFT (17U) +/*! WUF17 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK) + +#define WUU_PF_WUF18_MASK (0x40000U) +#define WUU_PF_WUF18_SHIFT (18U) +/*! WUF18 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK) + +#define WUU_PF_WUF19_MASK (0x80000U) +#define WUU_PF_WUF19_SHIFT (19U) +/*! WUF19 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK) + +#define WUU_PF_WUF20_MASK (0x100000U) +#define WUU_PF_WUF20_SHIFT (20U) +/*! WUF20 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK) + +#define WUU_PF_WUF21_MASK (0x200000U) +#define WUU_PF_WUF21_SHIFT (21U) +/*! WUF21 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF21_SHIFT)) & WUU_PF_WUF21_MASK) + +#define WUU_PF_WUF22_MASK (0x400000U) +#define WUU_PF_WUF22_SHIFT (22U) +/*! WUF22 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK) + +#define WUU_PF_WUF23_MASK (0x800000U) +#define WUU_PF_WUF23_SHIFT (23U) +/*! WUF23 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK) + +#define WUU_PF_WUF24_MASK (0x1000000U) +#define WUU_PF_WUF24_SHIFT (24U) +/*! WUF24 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK) + +#define WUU_PF_WUF25_MASK (0x2000000U) +#define WUU_PF_WUF25_SHIFT (25U) +/*! WUF25 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK) + +#define WUU_PF_WUF26_MASK (0x4000000U) +#define WUU_PF_WUF26_SHIFT (26U) +/*! WUF26 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK) + +#define WUU_PF_WUF27_MASK (0x8000000U) +#define WUU_PF_WUF27_SHIFT (27U) +/*! WUF27 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK) + +#define WUU_PF_Reserved28_MASK (0x10000000U) +#define WUU_PF_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved28_SHIFT)) & WUU_PF_Reserved28_MASK) + +#define WUU_PF_Reserved29_MASK (0x20000000U) +#define WUU_PF_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved29_SHIFT)) & WUU_PF_Reserved29_MASK) + +#define WUU_PF_Reserved30_MASK (0x40000000U) +#define WUU_PF_Reserved30_SHIFT (30U) +/*! Reserved30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved30_SHIFT)) & WUU_PF_Reserved30_MASK) + +#define WUU_PF_Reserved31_MASK (0x80000000U) +#define WUU_PF_Reserved31_SHIFT (31U) +/*! Reserved31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved31_SHIFT)) & WUU_PF_Reserved31_MASK) +/*! @} */ + +/*! @name FILT - Pin Filter */ +/*! @{ */ + +#define WUU_FILT_FILTSEL1_MASK (0x1FU) +#define WUU_FILT_FILTSEL1_SHIFT (0U) +/*! FILTSEL1 - Filter 1 Pin Select */ +#define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK) + +#define WUU_FILT_FILTE1_MASK (0x60U) +#define WUU_FILT_FILTE1_SHIFT (5U) +/*! FILTE1 - Filter 1 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK) + +#define WUU_FILT_FILTF1_MASK (0x80U) +#define WUU_FILT_FILTF1_SHIFT (7U) +/*! FILTF1 - Filter 1 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK) + +#define WUU_FILT_FILTSEL2_MASK (0x1F00U) +#define WUU_FILT_FILTSEL2_SHIFT (8U) +/*! FILTSEL2 - Filter 2 Pin Select */ +#define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK) + +#define WUU_FILT_FILTE2_MASK (0x6000U) +#define WUU_FILT_FILTE2_SHIFT (13U) +/*! FILTE2 - Filter 2 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK) + +#define WUU_FILT_FILTF2_MASK (0x8000U) +#define WUU_FILT_FILTF2_SHIFT (15U) +/*! FILTF2 - Filter 2 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK) +/*! @} */ + +/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */ +/*! @{ */ + +#define WUU_PDC1_WUPDC0_MASK (0x3U) +#define WUU_PDC1_WUPDC0_SHIFT (0U) +/*! WUPDC0 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC0_SHIFT)) & WUU_PDC1_WUPDC0_MASK) + +#define WUU_PDC1_WUPDC1_MASK (0xCU) +#define WUU_PDC1_WUPDC1_SHIFT (2U) +/*! WUPDC1 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC1_SHIFT)) & WUU_PDC1_WUPDC1_MASK) + +#define WUU_PDC1_WUPDC2_MASK (0x30U) +#define WUU_PDC1_WUPDC2_SHIFT (4U) +/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK) + +#define WUU_PDC1_WUPDC3_MASK (0xC0U) +#define WUU_PDC1_WUPDC3_SHIFT (6U) +/*! WUPDC3 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC3_SHIFT)) & WUU_PDC1_WUPDC3_MASK) + +#define WUU_PDC1_WUPDC4_MASK (0x300U) +#define WUU_PDC1_WUPDC4_SHIFT (8U) +/*! WUPDC4 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC4_SHIFT)) & WUU_PDC1_WUPDC4_MASK) + +#define WUU_PDC1_WUPDC5_MASK (0xC00U) +#define WUU_PDC1_WUPDC5_SHIFT (10U) +/*! WUPDC5 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC5_SHIFT)) & WUU_PDC1_WUPDC5_MASK) + +#define WUU_PDC1_WUPDC6_MASK (0x3000U) +#define WUU_PDC1_WUPDC6_SHIFT (12U) +/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK) + +#define WUU_PDC1_WUPDC7_MASK (0xC000U) +#define WUU_PDC1_WUPDC7_SHIFT (14U) +/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK) + +#define WUU_PDC1_WUPDC8_MASK (0x30000U) +#define WUU_PDC1_WUPDC8_SHIFT (16U) +/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK) + +#define WUU_PDC1_WUPDC9_MASK (0xC0000U) +#define WUU_PDC1_WUPDC9_SHIFT (18U) +/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK) + +#define WUU_PDC1_WUPDC10_MASK (0x300000U) +#define WUU_PDC1_WUPDC10_SHIFT (20U) +/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK) + +#define WUU_PDC1_WUPDC11_MASK (0xC00000U) +#define WUU_PDC1_WUPDC11_SHIFT (22U) +/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK) + +#define WUU_PDC1_WUPDC12_MASK (0x3000000U) +#define WUU_PDC1_WUPDC12_SHIFT (24U) +/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK) + +#define WUU_PDC1_WUPDC13_MASK (0xC000000U) +#define WUU_PDC1_WUPDC13_SHIFT (26U) +/*! WUPDC13 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC13_SHIFT)) & WUU_PDC1_WUPDC13_MASK) + +#define WUU_PDC1_WUPDC14_MASK (0x30000000U) +#define WUU_PDC1_WUPDC14_SHIFT (28U) +/*! WUPDC14 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC14_SHIFT)) & WUU_PDC1_WUPDC14_MASK) + +#define WUU_PDC1_WUPDC15_MASK (0xC0000000U) +#define WUU_PDC1_WUPDC15_SHIFT (30U) +/*! WUPDC15 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC15_SHIFT)) & WUU_PDC1_WUPDC15_MASK) +/*! @} */ + +/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */ +/*! @{ */ + +#define WUU_PDC2_WUPDC16_MASK (0x3U) +#define WUU_PDC2_WUPDC16_SHIFT (0U) +/*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK) + +#define WUU_PDC2_WUPDC17_MASK (0xCU) +#define WUU_PDC2_WUPDC17_SHIFT (2U) +/*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK) + +#define WUU_PDC2_WUPDC18_MASK (0x30U) +#define WUU_PDC2_WUPDC18_SHIFT (4U) +/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK) + +#define WUU_PDC2_WUPDC19_MASK (0xC0U) +#define WUU_PDC2_WUPDC19_SHIFT (6U) +/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK) + +#define WUU_PDC2_WUPDC20_MASK (0x300U) +#define WUU_PDC2_WUPDC20_SHIFT (8U) +/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK) + +#define WUU_PDC2_WUPDC21_MASK (0xC00U) +#define WUU_PDC2_WUPDC21_SHIFT (10U) +/*! WUPDC21 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC21_SHIFT)) & WUU_PDC2_WUPDC21_MASK) + +#define WUU_PDC2_WUPDC22_MASK (0x3000U) +#define WUU_PDC2_WUPDC22_SHIFT (12U) +/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK) + +#define WUU_PDC2_WUPDC23_MASK (0xC000U) +#define WUU_PDC2_WUPDC23_SHIFT (14U) +/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK) + +#define WUU_PDC2_WUPDC24_MASK (0x30000U) +#define WUU_PDC2_WUPDC24_SHIFT (16U) +/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK) + +#define WUU_PDC2_WUPDC25_MASK (0xC0000U) +#define WUU_PDC2_WUPDC25_SHIFT (18U) +/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK) + +#define WUU_PDC2_WUPDC26_MASK (0x300000U) +#define WUU_PDC2_WUPDC26_SHIFT (20U) +/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK) + +#define WUU_PDC2_WUPDC27_MASK (0xC00000U) +#define WUU_PDC2_WUPDC27_SHIFT (22U) +/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK) + +#define WUU_PDC2_Reserved28_MASK (0x3000000U) +#define WUU_PDC2_Reserved28_SHIFT (24U) +/*! Reserved28 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved28_SHIFT)) & WUU_PDC2_Reserved28_MASK) + +#define WUU_PDC2_Reserved29_MASK (0xC000000U) +#define WUU_PDC2_Reserved29_SHIFT (26U) +/*! Reserved29 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved29_SHIFT)) & WUU_PDC2_Reserved29_MASK) + +#define WUU_PDC2_Reserved30_MASK (0x30000000U) +#define WUU_PDC2_Reserved30_SHIFT (28U) +/*! Reserved30 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved30_SHIFT)) & WUU_PDC2_Reserved30_MASK) + +#define WUU_PDC2_Reserved31_MASK (0xC0000000U) +#define WUU_PDC2_Reserved31_SHIFT (30U) +/*! Reserved31 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved31_SHIFT)) & WUU_PDC2_Reserved31_MASK) +/*! @} */ + +/*! @name FDC - Pin Filter DMA/Trigger Configuration */ +/*! @{ */ + +#define WUU_FDC_FILTC1_MASK (0x3U) +#define WUU_FDC_FILTC1_SHIFT (0U) +/*! FILTC1 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK) + +#define WUU_FDC_FILTC2_MASK (0xCU) +#define WUU_FDC_FILTC2_SHIFT (2U) +/*! FILTC2 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK) +/*! @} */ + +/*! @name PMC - Pin Mode Configuration */ +/*! @{ */ + +#define WUU_PMC_WUPMC0_MASK (0x1U) +#define WUU_PMC_WUPMC0_SHIFT (0U) +/*! WUPMC0 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC0_SHIFT)) & WUU_PMC_WUPMC0_MASK) + +#define WUU_PMC_WUPMC1_MASK (0x2U) +#define WUU_PMC_WUPMC1_SHIFT (1U) +/*! WUPMC1 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC1_SHIFT)) & WUU_PMC_WUPMC1_MASK) + +#define WUU_PMC_WUPMC2_MASK (0x4U) +#define WUU_PMC_WUPMC2_SHIFT (2U) +/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK) + +#define WUU_PMC_WUPMC3_MASK (0x8U) +#define WUU_PMC_WUPMC3_SHIFT (3U) +/*! WUPMC3 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC3_SHIFT)) & WUU_PMC_WUPMC3_MASK) + +#define WUU_PMC_WUPMC4_MASK (0x10U) +#define WUU_PMC_WUPMC4_SHIFT (4U) +/*! WUPMC4 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC4_SHIFT)) & WUU_PMC_WUPMC4_MASK) + +#define WUU_PMC_WUPMC5_MASK (0x20U) +#define WUU_PMC_WUPMC5_SHIFT (5U) +/*! WUPMC5 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC5_SHIFT)) & WUU_PMC_WUPMC5_MASK) + +#define WUU_PMC_WUPMC6_MASK (0x40U) +#define WUU_PMC_WUPMC6_SHIFT (6U) +/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK) + +#define WUU_PMC_WUPMC7_MASK (0x80U) +#define WUU_PMC_WUPMC7_SHIFT (7U) +/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK) + +#define WUU_PMC_WUPMC8_MASK (0x100U) +#define WUU_PMC_WUPMC8_SHIFT (8U) +/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK) + +#define WUU_PMC_WUPMC9_MASK (0x200U) +#define WUU_PMC_WUPMC9_SHIFT (9U) +/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK) + +#define WUU_PMC_WUPMC10_MASK (0x400U) +#define WUU_PMC_WUPMC10_SHIFT (10U) +/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK) + +#define WUU_PMC_WUPMC11_MASK (0x800U) +#define WUU_PMC_WUPMC11_SHIFT (11U) +/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK) + +#define WUU_PMC_WUPMC12_MASK (0x1000U) +#define WUU_PMC_WUPMC12_SHIFT (12U) +/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK) + +#define WUU_PMC_WUPMC13_MASK (0x2000U) +#define WUU_PMC_WUPMC13_SHIFT (13U) +/*! WUPMC13 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC13_SHIFT)) & WUU_PMC_WUPMC13_MASK) + +#define WUU_PMC_WUPMC14_MASK (0x4000U) +#define WUU_PMC_WUPMC14_SHIFT (14U) +/*! WUPMC14 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC14_SHIFT)) & WUU_PMC_WUPMC14_MASK) + +#define WUU_PMC_WUPMC15_MASK (0x8000U) +#define WUU_PMC_WUPMC15_SHIFT (15U) +/*! WUPMC15 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC15_SHIFT)) & WUU_PMC_WUPMC15_MASK) + +#define WUU_PMC_WUPMC16_MASK (0x10000U) +#define WUU_PMC_WUPMC16_SHIFT (16U) +/*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK) + +#define WUU_PMC_WUPMC17_MASK (0x20000U) +#define WUU_PMC_WUPMC17_SHIFT (17U) +/*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK) + +#define WUU_PMC_WUPMC18_MASK (0x40000U) +#define WUU_PMC_WUPMC18_SHIFT (18U) +/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK) + +#define WUU_PMC_WUPMC19_MASK (0x80000U) +#define WUU_PMC_WUPMC19_SHIFT (19U) +/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK) + +#define WUU_PMC_WUPMC20_MASK (0x100000U) +#define WUU_PMC_WUPMC20_SHIFT (20U) +/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK) + +#define WUU_PMC_WUPMC21_MASK (0x200000U) +#define WUU_PMC_WUPMC21_SHIFT (21U) +/*! WUPMC21 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC21_SHIFT)) & WUU_PMC_WUPMC21_MASK) + +#define WUU_PMC_WUPMC22_MASK (0x400000U) +#define WUU_PMC_WUPMC22_SHIFT (22U) +/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK) + +#define WUU_PMC_WUPMC23_MASK (0x800000U) +#define WUU_PMC_WUPMC23_SHIFT (23U) +/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK) + +#define WUU_PMC_WUPMC24_MASK (0x1000000U) +#define WUU_PMC_WUPMC24_SHIFT (24U) +/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK) + +#define WUU_PMC_WUPMC25_MASK (0x2000000U) +#define WUU_PMC_WUPMC25_SHIFT (25U) +/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK) + +#define WUU_PMC_WUPMC26_MASK (0x4000000U) +#define WUU_PMC_WUPMC26_SHIFT (26U) +/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK) + +#define WUU_PMC_WUPMC27_MASK (0x8000000U) +#define WUU_PMC_WUPMC27_SHIFT (27U) +/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK) + +#define WUU_PMC_Reserved28_MASK (0x10000000U) +#define WUU_PMC_Reserved28_SHIFT (28U) +/*! Reserved28 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved28_SHIFT)) & WUU_PMC_Reserved28_MASK) + +#define WUU_PMC_Reserved29_MASK (0x20000000U) +#define WUU_PMC_Reserved29_SHIFT (29U) +/*! Reserved29 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved29_SHIFT)) & WUU_PMC_Reserved29_MASK) + +#define WUU_PMC_Reserved30_MASK (0x40000000U) +#define WUU_PMC_Reserved30_SHIFT (30U) +/*! Reserved30 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved30_SHIFT)) & WUU_PMC_Reserved30_MASK) + +#define WUU_PMC_Reserved31_MASK (0x80000000U) +#define WUU_PMC_Reserved31_SHIFT (31U) +/*! Reserved31 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved31_SHIFT)) & WUU_PMC_Reserved31_MASK) +/*! @} */ + +/*! @name FMC - Pin Filter Mode Configuration */ +/*! @{ */ + +#define WUU_FMC_FILTM1_MASK (0x1U) +#define WUU_FMC_FILTM1_SHIFT (0U) +/*! FILTM1 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) + +#define WUU_FMC_FILTM2_MASK (0x2U) +#define WUU_FMC_FILTM2_SHIFT (1U) +/*! FILTM2 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WUU_Register_Masks */ + + +/* WUU - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x50046000u) + /** Peripheral WUU0 base address */ + #define WUU0_BASE_NS (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Peripheral WUU0 base pointer */ + #define WUU0_NS ((WUU_Type *)WUU0_BASE_NS) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS_NS { WUU0_BASE_NS } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS_NS { WUU0_NS } +#else + /** Peripheral WUU0 base address */ + #define WUU0_BASE (0x40046000u) + /** Peripheral WUU0 base pointer */ + #define WUU0 ((WUU_Type *)WUU0_BASE) + /** Array initializer of WUU peripheral base addresses */ + #define WUU_BASE_ADDRS { WUU0_BASE } + /** Array initializer of WUU peripheral base pointers */ + #define WUU_BASE_PTRS { WUU0 } +#endif + +/*! + * @} + */ /* end of group WUU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Mode, offset: 0x0 */ + __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ + __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ + __I uint32_t TV; /**< Timer Value, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ + __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Mode */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog Enable + * 0b0..Timer stopped + * 0b1..Timer running + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog Reset Enable + * 0b0..Interrupt + * 0b1..Reset + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog Timeout Flag + * 0b0..Watchdog event has not occurred. + * 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1). + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning Interrupt Flag + * 0b0..No flag + * 0b1..Flag + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog Update Mode + * 0b0..Flexible + * 0b1..Threshold + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) + +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +/*! LOCK - Lock + * 0b0..No Lock + * 0b1..Lock + */ +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) + +#define WWDT_MOD_DEBUG_EN_MASK (0x40U) +#define WWDT_MOD_DEBUG_EN_SHIFT (6U) +/*! DEBUG_EN - Debug Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define WWDT_MOD_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK) +/*! @} */ + +/*! @name TC - Timer Constant */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog Timeout Value */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Feed Sequence */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed Value */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Timer Value */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter Timer Value */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Warning Interrupt Compare Value */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog Warning Interrupt Compare Value */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Window Compare Value */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog Window Value */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x50016000u) + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE_NS (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT0 base pointer */ + #define WWDT0_NS ((WWDT_Type *)WWDT0_BASE_NS) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x50017000u) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE_NS (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Peripheral WWDT1 base pointer */ + #define WWDT1_NS ((WWDT_Type *)WWDT1_BASE_NS) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS_NS { WWDT0_BASE_NS, WWDT1_BASE_NS } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS_NS { WWDT0_NS, WWDT1_NS } +#else + /** Peripheral WWDT0 base address */ + #define WWDT0_BASE (0x40016000u) + /** Peripheral WWDT0 base pointer */ + #define WWDT0 ((WWDT_Type *)WWDT0_BASE) + /** Peripheral WWDT1 base address */ + #define WWDT1_BASE (0x40017000u) + /** Peripheral WWDT1 base pointer */ + #define WWDT1 ((WWDT_Type *)WWDT1_BASE) + /** Array initializer of WWDT peripheral base addresses */ + #define WWDT_BASE_ADDRS { WWDT0_BASE, WWDT1_BASE } + /** Array initializer of WWDT peripheral base pointers */ + #define WWDT_BASE_PTRS { WWDT0, WWDT1 } +#endif +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WWDT0_IRQn, WWDT1_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXN236_H_ */ + diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/MCXN236_features.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/MCXN236_features.h new file mode 100644 index 0000000000..d343f88e85 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/MCXN236_features.h @@ -0,0 +1,900 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2021-08-03 +** Build: b240407 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2021-08-03) +** Initial version based on SPEC1.6 +** +** ################################################################### +*/ + +#ifndef _MCXN236_FEATURES_H_ +#define _MCXN236_FEATURES_H_ + +/* SOC module features */ + +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (2) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (2) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EVTG availability on the SoC. */ +#define FSL_FEATURE_SOC_EVTG_COUNT (1) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (12) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief ITRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ITRC_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (8) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (8) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (2) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PDM availability on the SoC. */ +#define FSL_FEATURE_SOC_PDM_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PKC availability on the SoC. */ +#define FSL_FEATURE_SOC_PKC_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (6) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief PUF availability on the SoC. */ +#define FSL_FEATURE_SOC_PUF_COUNT (4) +/* @brief QDC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDC_COUNT (2) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SMARTDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTDMA_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief SYSPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSPM_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (1) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (2) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (2) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (1) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (1) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (297U) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (9.63f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* FLEXCAN module features */ + +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) +/* @brief FlexCAN maximum data rate. */ +#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000) + +/* CDOG module features */ + +/* @brief CDOG Has No Reset */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1) +/* @brief Has no bitfield FLASHWAKE in FLASHCR register */ +#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) +/* @brief Has no CCR0 CMP_STOP_EN bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (1) + +/* SYSPM module features */ + +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0) +/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */ +#define FSL_FEATURE_SYSPM_PMCR_COUNT (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0) +/* @brief whether has prot register */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0) +/* @brief whether has MP channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) \ + (((x) == DMA0) ? (16) : \ + (((x) == DMA1) ? (8) : (-1))) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0) +/* @brief edma5 has different tcd type. */ +#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0) +/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16) + +/* EVTG module features */ + +/* @brief OPAMP support force bypass */ +#define FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (1) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (1) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief SOC doesn't support slave IBI/MR/HJ. */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has ERRATA_051617. */ +#define FSL_FEATURE_I3C_HAS_ERRATA_051617 (1) + +/* INPUTMUX module features */ + +/* @brief Inputmux has DMA Request Enable */ +#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1) +/* @brief Inputmux has channel mux control */ +#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0) + +/* INTM module features */ + +/* @brief Up to 4 programmable interrupt monitors */ +#define FSL_FEATURE_INTM_MONITOR_COUNT (4) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (8) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Belong to LPFLEXCOMM */ +#define FSL_FEATURE_LPUART_IS_LPFLEXCOMM (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (1) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (1) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (1) + +/* LP_FLEXCOMM module features */ + +/* No feature definitions */ + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* PDM module features */ + +/* @brief PDM FIFO offset */ +#define FSL_FEATURE_PDM_FIFO_OFFSET (4) +/* @brief PDM Channel Number */ +#define FSL_FEATURE_PDM_CHANNEL_NUM (4) +/* @brief PDM FIFO WIDTH Size */ +#define FSL_FEATURE_PDM_FIFO_WIDTH (4) +/* @brief PDM FIFO DEPTH Size */ +#define FSL_FEATURE_PDM_FIFO_DEPTH (16) +/* @brief PDM has RANGE_CTRL register */ +#define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1) +/* @brief PDM Has Low Frequency */ +#define FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ (0) +/* @brief PDM Has No VADEF Bitfield In PDM VAD0_STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_VADEF (1) +/* @brief PDM Has no minimum clkdiv */ +#define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1) +/* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */ +#define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1) +/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */ +#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0) +/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */ +#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0) +/* @brief PDM Has DC_OUT_CTRL */ +#define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1) +/* @brief PDM Has Fixed DC CTRL VALUE. */ +#define FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED (1) +/* @brief PDM Has no independent error IRQ */ +#define FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ (1) +/* @brief PDM has no hardware Voice Activity Detector */ +#define FSL_FEATURE_PDM_HAS_NO_HWVAD (1) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* @brief PINT Interrupt Combine */ +#define FSL_FEATURE_PINT_INTERRUPT_COMBINE (1) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (0) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (1) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* PUF module features */ + +/* @brief Puf Activation Code Address. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304) +/* @brief Puf Activation Code Size. */ +#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) + +/* QDC module features */ + +/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */ +#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0) +/* @brief Has register CTRL3. */ +#define FSL_FEATURE_QDC_HAS_CTRL3 (1) +/* @brief Has register LASTEDGE or LASTEDGEH. */ +#define FSL_FEATURE_QDC_HAS_LASTEDGE (1) +/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */ +#define FSL_FEATURE_QDC_HAS_POSDPER (1) +/* @brief Has bitfiled FILT[FILT_PRSC]. */ +#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1) + +/* RTC module features */ + +/* @brief Has Tamper Direction Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION (0) +/* @brief Has Tamper Queue Status and Control Register support. */ +#define FSL_FEATURE_RTC_HAS_TAMPER_QUEUE (0) +/* @brief Has RTC subsystem. */ +#define FSL_FEATURE_RTC_HAS_SUBSYSTEM (1) +/* @brief Has RTC Tamper 23 Filter Configuration Register support. */ +#define FSL_FEATURE_RTC_HAS_FILTER23_CFG (0) +/* @brief Has WAKEUP_MODE bitfile in CTRL2 register. */ +#define FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE (1) +/* @brief Has CLK_SEL bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1) +/* @brief Has CLKO_DIS bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1) +/* @brief Has No Tamper in RTC. */ +#define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1) +/* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1) +/* @brief Has RST_SRC bitfile in STATUS register. */ +#define FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG (1) +/* @brief Has GP_DATA_REG register. */ +#define FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG (1) +/* @brief Has TIMER_STB_MASK bitfile in CTRL register. */ +#define FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK (1) + +/* SAI module features */ + +/* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */ +#define FSL_FEATURE_SAI_HAS_FIFO (1) +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (1) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) +/* @brief Support synchronous with another SAI. */ +#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) +/* @brief Support ROMAPI. */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices.. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* USBPHY module features */ + +/* @brief USBPHY contain DCD analog module */ +#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0) +/* @brief USBPHY has register TRIM_OVERRIDE_EN */ +#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (1) +/* @brief USBPHY is 28FDSOI */ +#define FSL_FEATURE_USBPHY_28FDSOI (0) + +/* UTICK module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) +/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0) + +/* WWDT module features */ + +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) +/* @brief WWDT does not support power down configure */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + +#endif /* _MCXN236_FEATURES_H_ */ + diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/arm/startup_MCXN236.S b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/arm/startup_MCXN236.S new file mode 100644 index 0000000000..2868c3a127 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/arm/startup_MCXN236.S @@ -0,0 +1,1858 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MCXN236.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* MCXN236 */ +/* @version: 1.0 */ +/* @date: 2023-10-1 */ +/* @build: b240409 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2024 NXP */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv8-m.main + .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long OR_IRQHandler /* OR IRQ*/ + .long EDMA_0_CH0_IRQHandler /* eDMA_0_CH0 error or transfer complete*/ + .long EDMA_0_CH1_IRQHandler /* eDMA_0_CH1 error or transfer complete*/ + .long EDMA_0_CH2_IRQHandler /* eDMA_0_CH2 error or transfer complete*/ + .long EDMA_0_CH3_IRQHandler /* eDMA_0_CH3 error or transfer complete*/ + .long EDMA_0_CH4_IRQHandler /* eDMA_0_CH4 error or transfer complete*/ + .long EDMA_0_CH5_IRQHandler /* eDMA_0_CH5 error or transfer complete*/ + .long EDMA_0_CH6_IRQHandler /* eDMA_0_CH6 error or transfer complete*/ + .long EDMA_0_CH7_IRQHandler /* eDMA_0_CH7 error or transfer complete*/ + .long EDMA_0_CH8_IRQHandler /* eDMA_0_CH8 error or transfer complete*/ + .long EDMA_0_CH9_IRQHandler /* eDMA_0_CH9 error or transfer complete*/ + .long EDMA_0_CH10_IRQHandler /* eDMA_0_CH10 error or transfer complete*/ + .long EDMA_0_CH11_IRQHandler /* eDMA_0_CH11 error or transfer complete*/ + .long EDMA_0_CH12_IRQHandler /* eDMA_0_CH12 error or transfer complete*/ + .long EDMA_0_CH13_IRQHandler /* eDMA_0_CH13 error or transfer complete*/ + .long EDMA_0_CH14_IRQHandler /* eDMA_0_CH14 error or transfer complete*/ + .long EDMA_0_CH15_IRQHandler /* eDMA_0_CH15 error or transfer complete*/ + .long GPIO00_IRQHandler /* GPIO0 interrupt 0*/ + .long GPIO01_IRQHandler /* GPIO0 interrupt 1*/ + .long GPIO10_IRQHandler /* GPIO1 interrupt 0*/ + .long GPIO11_IRQHandler /* GPIO1 interrupt 1*/ + .long GPIO20_IRQHandler /* GPIO2 interrupt 0*/ + .long GPIO21_IRQHandler /* GPIO2 interrupt 1*/ + .long GPIO30_IRQHandler /* GPIO3 interrupt 0*/ + .long GPIO31_IRQHandler /* GPIO3 interrupt 1*/ + .long GPIO40_IRQHandler /* GPIO4 interrupt 0*/ + .long GPIO41_IRQHandler /* GPIO4 interrupt 1*/ + .long GPIO50_IRQHandler /* GPIO5 interrupt 0*/ + .long GPIO51_IRQHandler /* GPIO5 interrupt 1*/ + .long UTICK0_IRQHandler /* Micro-Tick Timer interrupt*/ + .long MRT0_IRQHandler /* Multi-Rate Timer interrupt*/ + .long CTIMER0_IRQHandler /* Standard counter/timer 0 interrupt*/ + .long CTIMER1_IRQHandler /* Standard counter/timer 1 interrupt*/ + .long Reserved49_IRQHandler /* Reserved interrupt*/ + .long CTIMER2_IRQHandler /* Standard counter/timer 2 interrupt*/ + .long LP_FLEXCOMM0_IRQHandler /* LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM1_IRQHandler /* LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM2_IRQHandler /* LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM3_IRQHandler /* LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM4_IRQHandler /* LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM5_IRQHandler /* LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM6_IRQHandler /* LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM7_IRQHandler /* LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long Reserved59_IRQHandler /* Reserved interrupt*/ + .long Reserved60_IRQHandler /* Reserved interrupt*/ + .long ADC0_IRQHandler /* Analog-to-Digital Converter 0 - General Purpose interrupt*/ + .long ADC1_IRQHandler /* Analog-to-Digital Converter 1 - General Purpose interrupt*/ + .long PINT0_IRQHandler /* Pin Interrupt Pattern Match Interrupt*/ + .long PDM_EVENT_IRQHandler /* Microphone Interface interrupt */ + .long Reserved65_IRQHandler /* Reserved interrupt*/ + .long Reserved66_IRQHandler /* Reserved interrupt*/ + .long USB0_DCD_IRQHandler /* Universal Serial Bus - Device Charge Detect interrupt*/ + .long RTC_IRQHandler /* RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt)*/ + .long SMARTDMA_IRQHandler /* SmartDMA_IRQ*/ + .long Reserved70_IRQHandler /* Reserved interrupt*/ + .long CTIMER3_IRQHandler /* Standard counter/timer 3 interrupt*/ + .long CTIMER4_IRQHandler /* Standard counter/timer 4 interrupt*/ + .long OS_EVENT_IRQHandler /* OS event timer interrupt*/ + .long Reserved74_IRQHandler /* Reserved interrupt*/ + .long SAI0_IRQHandler /* Serial Audio Interface 0 interrupt*/ + .long SAI1_IRQHandler /* Serial Audio Interface 1 interrupt*/ + .long Reserved77_IRQHandler /* Reserved interrupt*/ + .long CAN0_IRQHandler /* Controller Area Network 0 interrupt*/ + .long CAN1_IRQHandler /* Controller Area Network 1 interrupt*/ + .long Reserved80_IRQHandler /* Reserved interrupt*/ + .long Reserved81_IRQHandler /* Reserved interrupt*/ + .long USB1_HS_PHY_IRQHandler /* USBHS DCD or USBHS Phy interrupt*/ + .long USB1_HS_IRQHandler /* USB High Speed OTG Controller interrupt */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* AHB Secure Controller hypervisor call interrupt*/ + .long Reserved85_IRQHandler /* Reserved interrupt*/ + .long Reserved86_IRQHandler /* Reserved interrupt*/ + .long Freqme_IRQHandler /* Frequency Measurement interrupt*/ + .long SEC_VIO_IRQHandler /* Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt)*/ + .long ELS_IRQHandler /* ELS interrupt*/ + .long PKC_IRQHandler /* PKC interrupt*/ + .long PUF_IRQHandler /* Physical Unclonable Function interrupt*/ + .long Reserved92_IRQHandler /* Reserved interrupt*/ + .long EDMA_1_CH0_IRQHandler /* eDMA_1_CH0 error or transfer complete*/ + .long EDMA_1_CH1_IRQHandler /* eDMA_1_CH1 error or transfer complete*/ + .long EDMA_1_CH2_IRQHandler /* eDMA_1_CH2 error or transfer complete*/ + .long EDMA_1_CH3_IRQHandler /* eDMA_1_CH3 error or transfer complete*/ + .long EDMA_1_CH4_IRQHandler /* eDMA_1_CH4 error or transfer complete*/ + .long EDMA_1_CH5_IRQHandler /* eDMA_1_CH5 error or transfer complete*/ + .long EDMA_1_CH6_IRQHandler /* eDMA_1_CH6 error or transfer complete*/ + .long EDMA_1_CH7_IRQHandler /* eDMA_1_CH7 error or transfer complete*/ + .long Reserved101_IRQHandler /* Reserved interrupt*/ + .long Reserved102_IRQHandler /* Reserved interrupt*/ + .long Reserved103_IRQHandler /* Reserved interrupt*/ + .long Reserved104_IRQHandler /* Reserved interrupt*/ + .long Reserved105_IRQHandler /* Reserved interrupt*/ + .long Reserved106_IRQHandler /* Reserved interrupt*/ + .long Reserved107_IRQHandler /* Reserved interrupt*/ + .long Reserved108_IRQHandler /* Reserved interrupt*/ + .long CDOG0_IRQHandler /* Code Watchdog Timer 0 interrupt*/ + .long CDOG1_IRQHandler /* Code Watchdog Timer 1 interrupt*/ + .long I3C0_IRQHandler /* Improved Inter Integrated Circuit interrupt 0*/ + .long I3C1_IRQHandler /* Improved Inter Integrated Circuit interrupt 1*/ + .long Reserved113_IRQHandler /* Reserved interrupt*/ + .long GDET_IRQHandler /* Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt*/ + .long VBAT0_IRQHandler /* VBAT interrupt( VBAT interrupt or digital tamper interrupt)*/ + .long EWM0_IRQHandler /* External Watchdog Monitor interrupt*/ + .long Reserved117_IRQHandler /* Reserved interrupt*/ + .long Reserved118_IRQHandler /* Reserved interrupt*/ + .long Reserved119_IRQHandler /* Reserved interrupt*/ + .long Reserved120_IRQHandler /* Reserved interrupt*/ + .long FLEXIO_IRQHandler /* Flexible Input/Output interrupt*/ + .long Reserved122_IRQHandler /* Reserved interrupt*/ + .long Reserved123_IRQHandler /* Reserved interrupt*/ + .long Reserved124_IRQHandler /* Reserved interrupt*/ + .long HSCMP0_IRQHandler /* High-Speed comparator0 interrupt*/ + .long HSCMP1_IRQHandler /* High-Speed comparator1 interrupt*/ + .long Reserved127_IRQHandler /* Reserved interrupt*/ + .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* FlexPWM0_reload_error interrupt*/ + .long FLEXPWM0_FAULT_IRQHandler /* FlexPWM0_fault interrupt*/ + .long FLEXPWM0_SUBMODULE0_IRQHandler /* FlexPWM0 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE1_IRQHandler /* FlexPWM0 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE2_IRQHandler /* FlexPWM0 Submodule 2 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE3_IRQHandler /* FlexPWM0 Submodule 3 capture/compare/reload interrupt*/ + .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* FlexPWM1_reload_error interrupt*/ + .long FLEXPWM1_FAULT_IRQHandler /* FlexPWM1_fault interrupt*/ + .long FLEXPWM1_SUBMODULE0_IRQHandler /* FlexPWM1 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ + .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ + .long Reserved149_IRQHandler /* Reserved interrupt*/ + .long ELS_ERR_IRQHandler /* ELS error interrupt*/ + .long PKC_ERR_IRQHandler /* PKC error interrupt*/ + .long ERM_SINGLE_BIT_ERROR_IRQHandler /* ERM Single Bit error interrupt*/ + .long ERM_MULTI_BIT_ERROR_IRQHandler /* ERM Multi Bit error interrupt*/ + .long FMU0_IRQHandler /* Flash Management Unit interrupt*/ + .long Reserved155_IRQHandler /* Reserved interrupt*/ + .long Reserved156_IRQHandler /* Reserved interrupt*/ + .long Reserved157_IRQHandler /* Reserved interrupt*/ + .long Reserved158_IRQHandler /* Reserved interrupt*/ + .long LPTMR0_IRQHandler /* Low Power Timer 0 interrupt*/ + .long LPTMR1_IRQHandler /* Low Power Timer 1 interrupt*/ + .long SCG_IRQHandler /* System Clock Generator interrupt*/ + .long SPC_IRQHandler /* System Power Controller interrupt*/ + .long WUU_IRQHandler /* Wake Up Unit interrupt*/ + .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ + .long Reserved165_IRQHandler /* Reserved interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ + .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ + .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ + .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ + .long Reserved171_IRQHandler /* Reserved interrupt*/ + + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Base + msr msplim, r0 + ldr r0,=SystemInit + blx r0 + cpsie i /* Unmask interrupts */ + ldr r0,=__main + bx r0 + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak OR_IRQHandler + .type OR_IRQHandler, %function +OR_IRQHandler: + ldr r0,=OR_DriverIRQHandler + bx r0 + .size OR_IRQHandler, . - OR_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH0_IRQHandler + .type EDMA_0_CH0_IRQHandler, %function +EDMA_0_CH0_IRQHandler: + ldr r0,=EDMA_0_CH0_DriverIRQHandler + bx r0 + .size EDMA_0_CH0_IRQHandler, . - EDMA_0_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH1_IRQHandler + .type EDMA_0_CH1_IRQHandler, %function +EDMA_0_CH1_IRQHandler: + ldr r0,=EDMA_0_CH1_DriverIRQHandler + bx r0 + .size EDMA_0_CH1_IRQHandler, . - EDMA_0_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH2_IRQHandler + .type EDMA_0_CH2_IRQHandler, %function +EDMA_0_CH2_IRQHandler: + ldr r0,=EDMA_0_CH2_DriverIRQHandler + bx r0 + .size EDMA_0_CH2_IRQHandler, . - EDMA_0_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH3_IRQHandler + .type EDMA_0_CH3_IRQHandler, %function +EDMA_0_CH3_IRQHandler: + ldr r0,=EDMA_0_CH3_DriverIRQHandler + bx r0 + .size EDMA_0_CH3_IRQHandler, . - EDMA_0_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH4_IRQHandler + .type EDMA_0_CH4_IRQHandler, %function +EDMA_0_CH4_IRQHandler: + ldr r0,=EDMA_0_CH4_DriverIRQHandler + bx r0 + .size EDMA_0_CH4_IRQHandler, . - EDMA_0_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH5_IRQHandler + .type EDMA_0_CH5_IRQHandler, %function +EDMA_0_CH5_IRQHandler: + ldr r0,=EDMA_0_CH5_DriverIRQHandler + bx r0 + .size EDMA_0_CH5_IRQHandler, . - EDMA_0_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH6_IRQHandler + .type EDMA_0_CH6_IRQHandler, %function +EDMA_0_CH6_IRQHandler: + ldr r0,=EDMA_0_CH6_DriverIRQHandler + bx r0 + .size EDMA_0_CH6_IRQHandler, . - EDMA_0_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH7_IRQHandler + .type EDMA_0_CH7_IRQHandler, %function +EDMA_0_CH7_IRQHandler: + ldr r0,=EDMA_0_CH7_DriverIRQHandler + bx r0 + .size EDMA_0_CH7_IRQHandler, . - EDMA_0_CH7_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH8_IRQHandler + .type EDMA_0_CH8_IRQHandler, %function +EDMA_0_CH8_IRQHandler: + ldr r0,=EDMA_0_CH8_DriverIRQHandler + bx r0 + .size EDMA_0_CH8_IRQHandler, . - EDMA_0_CH8_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH9_IRQHandler + .type EDMA_0_CH9_IRQHandler, %function +EDMA_0_CH9_IRQHandler: + ldr r0,=EDMA_0_CH9_DriverIRQHandler + bx r0 + .size EDMA_0_CH9_IRQHandler, . - EDMA_0_CH9_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH10_IRQHandler + .type EDMA_0_CH10_IRQHandler, %function +EDMA_0_CH10_IRQHandler: + ldr r0,=EDMA_0_CH10_DriverIRQHandler + bx r0 + .size EDMA_0_CH10_IRQHandler, . - EDMA_0_CH10_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH11_IRQHandler + .type EDMA_0_CH11_IRQHandler, %function +EDMA_0_CH11_IRQHandler: + ldr r0,=EDMA_0_CH11_DriverIRQHandler + bx r0 + .size EDMA_0_CH11_IRQHandler, . - EDMA_0_CH11_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH12_IRQHandler + .type EDMA_0_CH12_IRQHandler, %function +EDMA_0_CH12_IRQHandler: + ldr r0,=EDMA_0_CH12_DriverIRQHandler + bx r0 + .size EDMA_0_CH12_IRQHandler, . - EDMA_0_CH12_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH13_IRQHandler + .type EDMA_0_CH13_IRQHandler, %function +EDMA_0_CH13_IRQHandler: + ldr r0,=EDMA_0_CH13_DriverIRQHandler + bx r0 + .size EDMA_0_CH13_IRQHandler, . - EDMA_0_CH13_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH14_IRQHandler + .type EDMA_0_CH14_IRQHandler, %function +EDMA_0_CH14_IRQHandler: + ldr r0,=EDMA_0_CH14_DriverIRQHandler + bx r0 + .size EDMA_0_CH14_IRQHandler, . - EDMA_0_CH14_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH15_IRQHandler + .type EDMA_0_CH15_IRQHandler, %function +EDMA_0_CH15_IRQHandler: + ldr r0,=EDMA_0_CH15_DriverIRQHandler + bx r0 + .size EDMA_0_CH15_IRQHandler, . - EDMA_0_CH15_IRQHandler + + .align 1 + .thumb_func + .weak GPIO00_IRQHandler + .type GPIO00_IRQHandler, %function +GPIO00_IRQHandler: + ldr r0,=GPIO00_DriverIRQHandler + bx r0 + .size GPIO00_IRQHandler, . - GPIO00_IRQHandler + + .align 1 + .thumb_func + .weak GPIO01_IRQHandler + .type GPIO01_IRQHandler, %function +GPIO01_IRQHandler: + ldr r0,=GPIO01_DriverIRQHandler + bx r0 + .size GPIO01_IRQHandler, . - GPIO01_IRQHandler + + .align 1 + .thumb_func + .weak GPIO10_IRQHandler + .type GPIO10_IRQHandler, %function +GPIO10_IRQHandler: + ldr r0,=GPIO10_DriverIRQHandler + bx r0 + .size GPIO10_IRQHandler, . - GPIO10_IRQHandler + + .align 1 + .thumb_func + .weak GPIO11_IRQHandler + .type GPIO11_IRQHandler, %function +GPIO11_IRQHandler: + ldr r0,=GPIO11_DriverIRQHandler + bx r0 + .size GPIO11_IRQHandler, . - GPIO11_IRQHandler + + .align 1 + .thumb_func + .weak GPIO20_IRQHandler + .type GPIO20_IRQHandler, %function +GPIO20_IRQHandler: + ldr r0,=GPIO20_DriverIRQHandler + bx r0 + .size GPIO20_IRQHandler, . - GPIO20_IRQHandler + + .align 1 + .thumb_func + .weak GPIO21_IRQHandler + .type GPIO21_IRQHandler, %function +GPIO21_IRQHandler: + ldr r0,=GPIO21_DriverIRQHandler + bx r0 + .size GPIO21_IRQHandler, . - GPIO21_IRQHandler + + .align 1 + .thumb_func + .weak GPIO30_IRQHandler + .type GPIO30_IRQHandler, %function +GPIO30_IRQHandler: + ldr r0,=GPIO30_DriverIRQHandler + bx r0 + .size GPIO30_IRQHandler, . - GPIO30_IRQHandler + + .align 1 + .thumb_func + .weak GPIO31_IRQHandler + .type GPIO31_IRQHandler, %function +GPIO31_IRQHandler: + ldr r0,=GPIO31_DriverIRQHandler + bx r0 + .size GPIO31_IRQHandler, . - GPIO31_IRQHandler + + .align 1 + .thumb_func + .weak GPIO40_IRQHandler + .type GPIO40_IRQHandler, %function +GPIO40_IRQHandler: + ldr r0,=GPIO40_DriverIRQHandler + bx r0 + .size GPIO40_IRQHandler, . - GPIO40_IRQHandler + + .align 1 + .thumb_func + .weak GPIO41_IRQHandler + .type GPIO41_IRQHandler, %function +GPIO41_IRQHandler: + ldr r0,=GPIO41_DriverIRQHandler + bx r0 + .size GPIO41_IRQHandler, . - GPIO41_IRQHandler + + .align 1 + .thumb_func + .weak GPIO50_IRQHandler + .type GPIO50_IRQHandler, %function +GPIO50_IRQHandler: + ldr r0,=GPIO50_DriverIRQHandler + bx r0 + .size GPIO50_IRQHandler, . - GPIO50_IRQHandler + + .align 1 + .thumb_func + .weak GPIO51_IRQHandler + .type GPIO51_IRQHandler, %function +GPIO51_IRQHandler: + ldr r0,=GPIO51_DriverIRQHandler + bx r0 + .size GPIO51_IRQHandler, . - GPIO51_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved49_IRQHandler + .type Reserved49_IRQHandler, %function +Reserved49_IRQHandler: + ldr r0,=Reserved49_DriverIRQHandler + bx r0 + .size Reserved49_IRQHandler, . - Reserved49_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM0_IRQHandler + .type LP_FLEXCOMM0_IRQHandler, %function +LP_FLEXCOMM0_IRQHandler: + ldr r0,=LP_FLEXCOMM0_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM0_IRQHandler, . - LP_FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM1_IRQHandler + .type LP_FLEXCOMM1_IRQHandler, %function +LP_FLEXCOMM1_IRQHandler: + ldr r0,=LP_FLEXCOMM1_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM1_IRQHandler, . - LP_FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM2_IRQHandler + .type LP_FLEXCOMM2_IRQHandler, %function +LP_FLEXCOMM2_IRQHandler: + ldr r0,=LP_FLEXCOMM2_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM2_IRQHandler, . - LP_FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM3_IRQHandler + .type LP_FLEXCOMM3_IRQHandler, %function +LP_FLEXCOMM3_IRQHandler: + ldr r0,=LP_FLEXCOMM3_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM3_IRQHandler, . - LP_FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM4_IRQHandler + .type LP_FLEXCOMM4_IRQHandler, %function +LP_FLEXCOMM4_IRQHandler: + ldr r0,=LP_FLEXCOMM4_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM4_IRQHandler, . - LP_FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM5_IRQHandler + .type LP_FLEXCOMM5_IRQHandler, %function +LP_FLEXCOMM5_IRQHandler: + ldr r0,=LP_FLEXCOMM5_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM5_IRQHandler, . - LP_FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM6_IRQHandler + .type LP_FLEXCOMM6_IRQHandler, %function +LP_FLEXCOMM6_IRQHandler: + ldr r0,=LP_FLEXCOMM6_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM6_IRQHandler, . - LP_FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM7_IRQHandler + .type LP_FLEXCOMM7_IRQHandler, %function +LP_FLEXCOMM7_IRQHandler: + ldr r0,=LP_FLEXCOMM7_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM7_IRQHandler, . - LP_FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak ADC1_IRQHandler + .type ADC1_IRQHandler, %function +ADC1_IRQHandler: + ldr r0,=ADC1_DriverIRQHandler + bx r0 + .size ADC1_IRQHandler, . - ADC1_IRQHandler + + .align 1 + .thumb_func + .weak PINT0_IRQHandler + .type PINT0_IRQHandler, %function +PINT0_IRQHandler: + ldr r0,=PINT0_DriverIRQHandler + bx r0 + .size PINT0_IRQHandler, . - PINT0_IRQHandler + + .align 1 + .thumb_func + .weak PDM_EVENT_IRQHandler + .type PDM_EVENT_IRQHandler, %function +PDM_EVENT_IRQHandler: + ldr r0,=PDM_EVENT_DriverIRQHandler + bx r0 + .size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved65_IRQHandler + .type Reserved65_IRQHandler, %function +Reserved65_IRQHandler: + ldr r0,=Reserved65_DriverIRQHandler + bx r0 + .size Reserved65_IRQHandler, . - Reserved65_IRQHandler + + .align 1 + .thumb_func + .weak Reserved66_IRQHandler + .type Reserved66_IRQHandler, %function +Reserved66_IRQHandler: + ldr r0,=Reserved66_DriverIRQHandler + bx r0 + .size Reserved66_IRQHandler, . - Reserved66_IRQHandler + + .align 1 + .thumb_func + .weak USB0_DCD_IRQHandler + .type USB0_DCD_IRQHandler, %function +USB0_DCD_IRQHandler: + ldr r0,=USB0_DCD_DriverIRQHandler + bx r0 + .size USB0_DCD_IRQHandler, . - USB0_DCD_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak SMARTDMA_IRQHandler + .type SMARTDMA_IRQHandler, %function +SMARTDMA_IRQHandler: + ldr r0,=SMARTDMA_DriverIRQHandler + bx r0 + .size SMARTDMA_IRQHandler, . - SMARTDMA_IRQHandler + + .align 1 + .thumb_func + .weak Reserved70_IRQHandler + .type Reserved70_IRQHandler, %function +Reserved70_IRQHandler: + ldr r0,=Reserved70_DriverIRQHandler + bx r0 + .size Reserved70_IRQHandler, . - Reserved70_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved74_IRQHandler + .type Reserved74_IRQHandler, %function +Reserved74_IRQHandler: + ldr r0,=Reserved74_DriverIRQHandler + bx r0 + .size Reserved74_IRQHandler, . - Reserved74_IRQHandler + + .align 1 + .thumb_func + .weak SAI0_IRQHandler + .type SAI0_IRQHandler, %function +SAI0_IRQHandler: + ldr r0,=SAI0_DriverIRQHandler + bx r0 + .size SAI0_IRQHandler, . - SAI0_IRQHandler + + .align 1 + .thumb_func + .weak SAI1_IRQHandler + .type SAI1_IRQHandler, %function +SAI1_IRQHandler: + ldr r0,=SAI1_DriverIRQHandler + bx r0 + .size SAI1_IRQHandler, . - SAI1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved77_IRQHandler + .type Reserved77_IRQHandler, %function +Reserved77_IRQHandler: + ldr r0,=Reserved77_DriverIRQHandler + bx r0 + .size Reserved77_IRQHandler, . - Reserved77_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQHandler + .type CAN0_IRQHandler, %function +CAN0_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_IRQHandler, . - CAN0_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_IRQHandler + .type CAN1_IRQHandler, %function +CAN1_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_IRQHandler, . - CAN1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved80_IRQHandler + .type Reserved80_IRQHandler, %function +Reserved80_IRQHandler: + ldr r0,=Reserved80_DriverIRQHandler + bx r0 + .size Reserved80_IRQHandler, . - Reserved80_IRQHandler + + .align 1 + .thumb_func + .weak Reserved81_IRQHandler + .type Reserved81_IRQHandler, %function +Reserved81_IRQHandler: + ldr r0,=Reserved81_DriverIRQHandler + bx r0 + .size Reserved81_IRQHandler, . - Reserved81_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_PHY_IRQHandler + .type USB1_HS_PHY_IRQHandler, %function +USB1_HS_PHY_IRQHandler: + ldr r0,=USB1_HS_PHY_DriverIRQHandler + bx r0 + .size USB1_HS_PHY_IRQHandler, . - USB1_HS_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_IRQHandler + .type USB1_HS_IRQHandler, %function +USB1_HS_IRQHandler: + ldr r0,=USB1_HS_DriverIRQHandler + bx r0 + .size USB1_HS_IRQHandler, . - USB1_HS_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak Reserved85_IRQHandler + .type Reserved85_IRQHandler, %function +Reserved85_IRQHandler: + ldr r0,=Reserved85_DriverIRQHandler + bx r0 + .size Reserved85_IRQHandler, . - Reserved85_IRQHandler + + .align 1 + .thumb_func + .weak Reserved86_IRQHandler + .type Reserved86_IRQHandler, %function +Reserved86_IRQHandler: + ldr r0,=Reserved86_DriverIRQHandler + bx r0 + .size Reserved86_IRQHandler, . - Reserved86_IRQHandler + + .align 1 + .thumb_func + .weak Freqme_IRQHandler + .type Freqme_IRQHandler, %function +Freqme_IRQHandler: + ldr r0,=Freqme_DriverIRQHandler + bx r0 + .size Freqme_IRQHandler, . - Freqme_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak ELS_IRQHandler + .type ELS_IRQHandler, %function +ELS_IRQHandler: + ldr r0,=ELS_DriverIRQHandler + bx r0 + .size ELS_IRQHandler, . - ELS_IRQHandler + + .align 1 + .thumb_func + .weak PKC_IRQHandler + .type PKC_IRQHandler, %function +PKC_IRQHandler: + ldr r0,=PKC_DriverIRQHandler + bx r0 + .size PKC_IRQHandler, . - PKC_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak Reserved92_IRQHandler + .type Reserved92_IRQHandler, %function +Reserved92_IRQHandler: + ldr r0,=Reserved92_DriverIRQHandler + bx r0 + .size Reserved92_IRQHandler, . - Reserved92_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH0_IRQHandler + .type EDMA_1_CH0_IRQHandler, %function +EDMA_1_CH0_IRQHandler: + ldr r0,=EDMA_1_CH0_DriverIRQHandler + bx r0 + .size EDMA_1_CH0_IRQHandler, . - EDMA_1_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH1_IRQHandler + .type EDMA_1_CH1_IRQHandler, %function +EDMA_1_CH1_IRQHandler: + ldr r0,=EDMA_1_CH1_DriverIRQHandler + bx r0 + .size EDMA_1_CH1_IRQHandler, . - EDMA_1_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH2_IRQHandler + .type EDMA_1_CH2_IRQHandler, %function +EDMA_1_CH2_IRQHandler: + ldr r0,=EDMA_1_CH2_DriverIRQHandler + bx r0 + .size EDMA_1_CH2_IRQHandler, . - EDMA_1_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH3_IRQHandler + .type EDMA_1_CH3_IRQHandler, %function +EDMA_1_CH3_IRQHandler: + ldr r0,=EDMA_1_CH3_DriverIRQHandler + bx r0 + .size EDMA_1_CH3_IRQHandler, . - EDMA_1_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH4_IRQHandler + .type EDMA_1_CH4_IRQHandler, %function +EDMA_1_CH4_IRQHandler: + ldr r0,=EDMA_1_CH4_DriverIRQHandler + bx r0 + .size EDMA_1_CH4_IRQHandler, . - EDMA_1_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH5_IRQHandler + .type EDMA_1_CH5_IRQHandler, %function +EDMA_1_CH5_IRQHandler: + ldr r0,=EDMA_1_CH5_DriverIRQHandler + bx r0 + .size EDMA_1_CH5_IRQHandler, . - EDMA_1_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH6_IRQHandler + .type EDMA_1_CH6_IRQHandler, %function +EDMA_1_CH6_IRQHandler: + ldr r0,=EDMA_1_CH6_DriverIRQHandler + bx r0 + .size EDMA_1_CH6_IRQHandler, . - EDMA_1_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH7_IRQHandler + .type EDMA_1_CH7_IRQHandler, %function +EDMA_1_CH7_IRQHandler: + ldr r0,=EDMA_1_CH7_DriverIRQHandler + bx r0 + .size EDMA_1_CH7_IRQHandler, . - EDMA_1_CH7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved101_IRQHandler + .type Reserved101_IRQHandler, %function +Reserved101_IRQHandler: + ldr r0,=Reserved101_DriverIRQHandler + bx r0 + .size Reserved101_IRQHandler, . - Reserved101_IRQHandler + + .align 1 + .thumb_func + .weak Reserved102_IRQHandler + .type Reserved102_IRQHandler, %function +Reserved102_IRQHandler: + ldr r0,=Reserved102_DriverIRQHandler + bx r0 + .size Reserved102_IRQHandler, . - Reserved102_IRQHandler + + .align 1 + .thumb_func + .weak Reserved103_IRQHandler + .type Reserved103_IRQHandler, %function +Reserved103_IRQHandler: + ldr r0,=Reserved103_DriverIRQHandler + bx r0 + .size Reserved103_IRQHandler, . - Reserved103_IRQHandler + + .align 1 + .thumb_func + .weak Reserved104_IRQHandler + .type Reserved104_IRQHandler, %function +Reserved104_IRQHandler: + ldr r0,=Reserved104_DriverIRQHandler + bx r0 + .size Reserved104_IRQHandler, . - Reserved104_IRQHandler + + .align 1 + .thumb_func + .weak Reserved105_IRQHandler + .type Reserved105_IRQHandler, %function +Reserved105_IRQHandler: + ldr r0,=Reserved105_DriverIRQHandler + bx r0 + .size Reserved105_IRQHandler, . - Reserved105_IRQHandler + + .align 1 + .thumb_func + .weak Reserved106_IRQHandler + .type Reserved106_IRQHandler, %function +Reserved106_IRQHandler: + ldr r0,=Reserved106_DriverIRQHandler + bx r0 + .size Reserved106_IRQHandler, . - Reserved106_IRQHandler + + .align 1 + .thumb_func + .weak Reserved107_IRQHandler + .type Reserved107_IRQHandler, %function +Reserved107_IRQHandler: + ldr r0,=Reserved107_DriverIRQHandler + bx r0 + .size Reserved107_IRQHandler, . - Reserved107_IRQHandler + + .align 1 + .thumb_func + .weak Reserved108_IRQHandler + .type Reserved108_IRQHandler, %function +Reserved108_IRQHandler: + ldr r0,=Reserved108_DriverIRQHandler + bx r0 + .size Reserved108_IRQHandler, . - Reserved108_IRQHandler + + .align 1 + .thumb_func + .weak CDOG0_IRQHandler + .type CDOG0_IRQHandler, %function +CDOG0_IRQHandler: + ldr r0,=CDOG0_DriverIRQHandler + bx r0 + .size CDOG0_IRQHandler, . - CDOG0_IRQHandler + + .align 1 + .thumb_func + .weak CDOG1_IRQHandler + .type CDOG1_IRQHandler, %function +CDOG1_IRQHandler: + ldr r0,=CDOG1_DriverIRQHandler + bx r0 + .size CDOG1_IRQHandler, . - CDOG1_IRQHandler + + .align 1 + .thumb_func + .weak I3C0_IRQHandler + .type I3C0_IRQHandler, %function +I3C0_IRQHandler: + ldr r0,=I3C0_DriverIRQHandler + bx r0 + .size I3C0_IRQHandler, . - I3C0_IRQHandler + + .align 1 + .thumb_func + .weak I3C1_IRQHandler + .type I3C1_IRQHandler, %function +I3C1_IRQHandler: + ldr r0,=I3C1_DriverIRQHandler + bx r0 + .size I3C1_IRQHandler, . - I3C1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved113_IRQHandler + .type Reserved113_IRQHandler, %function +Reserved113_IRQHandler: + ldr r0,=Reserved113_DriverIRQHandler + bx r0 + .size Reserved113_IRQHandler, . - Reserved113_IRQHandler + + .align 1 + .thumb_func + .weak GDET_IRQHandler + .type GDET_IRQHandler, %function +GDET_IRQHandler: + ldr r0,=GDET_DriverIRQHandler + bx r0 + .size GDET_IRQHandler, . - GDET_IRQHandler + + .align 1 + .thumb_func + .weak VBAT0_IRQHandler + .type VBAT0_IRQHandler, %function +VBAT0_IRQHandler: + ldr r0,=VBAT0_DriverIRQHandler + bx r0 + .size VBAT0_IRQHandler, . - VBAT0_IRQHandler + + .align 1 + .thumb_func + .weak EWM0_IRQHandler + .type EWM0_IRQHandler, %function +EWM0_IRQHandler: + ldr r0,=EWM0_DriverIRQHandler + bx r0 + .size EWM0_IRQHandler, . - EWM0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved117_IRQHandler + .type Reserved117_IRQHandler, %function +Reserved117_IRQHandler: + ldr r0,=Reserved117_DriverIRQHandler + bx r0 + .size Reserved117_IRQHandler, . - Reserved117_IRQHandler + + .align 1 + .thumb_func + .weak Reserved118_IRQHandler + .type Reserved118_IRQHandler, %function +Reserved118_IRQHandler: + ldr r0,=Reserved118_DriverIRQHandler + bx r0 + .size Reserved118_IRQHandler, . - Reserved118_IRQHandler + + .align 1 + .thumb_func + .weak Reserved119_IRQHandler + .type Reserved119_IRQHandler, %function +Reserved119_IRQHandler: + ldr r0,=Reserved119_DriverIRQHandler + bx r0 + .size Reserved119_IRQHandler, . - Reserved119_IRQHandler + + .align 1 + .thumb_func + .weak Reserved120_IRQHandler + .type Reserved120_IRQHandler, %function +Reserved120_IRQHandler: + ldr r0,=Reserved120_DriverIRQHandler + bx r0 + .size Reserved120_IRQHandler, . - Reserved120_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO_IRQHandler + .type FLEXIO_IRQHandler, %function +FLEXIO_IRQHandler: + ldr r0,=FLEXIO_DriverIRQHandler + bx r0 + .size FLEXIO_IRQHandler, . - FLEXIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved122_IRQHandler + .type Reserved122_IRQHandler, %function +Reserved122_IRQHandler: + ldr r0,=Reserved122_DriverIRQHandler + bx r0 + .size Reserved122_IRQHandler, . - Reserved122_IRQHandler + + .align 1 + .thumb_func + .weak Reserved123_IRQHandler + .type Reserved123_IRQHandler, %function +Reserved123_IRQHandler: + ldr r0,=Reserved123_DriverIRQHandler + bx r0 + .size Reserved123_IRQHandler, . - Reserved123_IRQHandler + + .align 1 + .thumb_func + .weak Reserved124_IRQHandler + .type Reserved124_IRQHandler, %function +Reserved124_IRQHandler: + ldr r0,=Reserved124_DriverIRQHandler + bx r0 + .size Reserved124_IRQHandler, . - Reserved124_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP0_IRQHandler + .type HSCMP0_IRQHandler, %function +HSCMP0_IRQHandler: + ldr r0,=HSCMP0_DriverIRQHandler + bx r0 + .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP1_IRQHandler + .type HSCMP1_IRQHandler, %function +HSCMP1_IRQHandler: + ldr r0,=HSCMP1_DriverIRQHandler + bx r0 + .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved127_IRQHandler + .type Reserved127_IRQHandler, %function +Reserved127_IRQHandler: + ldr r0,=Reserved127_DriverIRQHandler + bx r0 + .size Reserved127_IRQHandler, . - Reserved127_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD_ERROR_IRQHandler + .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function +FLEXPWM0_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_FAULT_IRQHandler + .type FLEXPWM0_FAULT_IRQHandler, %function +FLEXPWM0_FAULT_IRQHandler: + ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE0_IRQHandler + .type FLEXPWM0_SUBMODULE0_IRQHandler, %function +FLEXPWM0_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE0_IRQHandler, . - FLEXPWM0_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE1_IRQHandler + .type FLEXPWM0_SUBMODULE1_IRQHandler, %function +FLEXPWM0_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE1_IRQHandler, . - FLEXPWM0_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE2_IRQHandler + .type FLEXPWM0_SUBMODULE2_IRQHandler, %function +FLEXPWM0_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE2_IRQHandler, . - FLEXPWM0_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE3_IRQHandler + .type FLEXPWM0_SUBMODULE3_IRQHandler, %function +FLEXPWM0_SUBMODULE3_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE3_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE3_IRQHandler, . - FLEXPWM0_SUBMODULE3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD_ERROR_IRQHandler + .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function +FLEXPWM1_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_FAULT_IRQHandler + .type FLEXPWM1_FAULT_IRQHandler, %function +FLEXPWM1_FAULT_IRQHandler: + ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE0_IRQHandler + .type FLEXPWM1_SUBMODULE0_IRQHandler, %function +FLEXPWM1_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE0_IRQHandler, . - FLEXPWM1_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE1_IRQHandler + .type FLEXPWM1_SUBMODULE1_IRQHandler, %function +FLEXPWM1_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE1_IRQHandler, . - FLEXPWM1_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE2_IRQHandler + .type FLEXPWM1_SUBMODULE2_IRQHandler, %function +FLEXPWM1_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE2_IRQHandler, . - FLEXPWM1_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE3_IRQHandler + .type FLEXPWM1_SUBMODULE3_IRQHandler, %function +FLEXPWM1_SUBMODULE3_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE3_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE3_IRQHandler, . - FLEXPWM1_SUBMODULE3_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler + bx r0 + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler + bx r0 + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler + bx r0 + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler + bx r0 + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler + bx r0 + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler + bx r0 + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ITRC0_IRQHandler + .type ITRC0_IRQHandler, %function +ITRC0_IRQHandler: + ldr r0,=ITRC0_DriverIRQHandler + bx r0 + .size ITRC0_IRQHandler, . - ITRC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved149_IRQHandler + .type Reserved149_IRQHandler, %function +Reserved149_IRQHandler: + ldr r0,=Reserved149_DriverIRQHandler + bx r0 + .size Reserved149_IRQHandler, . - Reserved149_IRQHandler + + .align 1 + .thumb_func + .weak ELS_ERR_IRQHandler + .type ELS_ERR_IRQHandler, %function +ELS_ERR_IRQHandler: + ldr r0,=ELS_ERR_DriverIRQHandler + bx r0 + .size ELS_ERR_IRQHandler, . - ELS_ERR_IRQHandler + + .align 1 + .thumb_func + .weak PKC_ERR_IRQHandler + .type PKC_ERR_IRQHandler, %function +PKC_ERR_IRQHandler: + ldr r0,=PKC_ERR_DriverIRQHandler + bx r0 + .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_SINGLE_BIT_ERROR_IRQHandler + .type ERM_SINGLE_BIT_ERROR_IRQHandler, %function +ERM_SINGLE_BIT_ERROR_IRQHandler: + ldr r0,=ERM_SINGLE_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_SINGLE_BIT_ERROR_IRQHandler, . - ERM_SINGLE_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_MULTI_BIT_ERROR_IRQHandler + .type ERM_MULTI_BIT_ERROR_IRQHandler, %function +ERM_MULTI_BIT_ERROR_IRQHandler: + ldr r0,=ERM_MULTI_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_MULTI_BIT_ERROR_IRQHandler, . - ERM_MULTI_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FMU0_IRQHandler + .type FMU0_IRQHandler, %function +FMU0_IRQHandler: + ldr r0,=FMU0_DriverIRQHandler + bx r0 + .size FMU0_IRQHandler, . - FMU0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved155_IRQHandler + .type Reserved155_IRQHandler, %function +Reserved155_IRQHandler: + ldr r0,=Reserved155_DriverIRQHandler + bx r0 + .size Reserved155_IRQHandler, . - Reserved155_IRQHandler + + .align 1 + .thumb_func + .weak Reserved156_IRQHandler + .type Reserved156_IRQHandler, %function +Reserved156_IRQHandler: + ldr r0,=Reserved156_DriverIRQHandler + bx r0 + .size Reserved156_IRQHandler, . - Reserved156_IRQHandler + + .align 1 + .thumb_func + .weak Reserved157_IRQHandler + .type Reserved157_IRQHandler, %function +Reserved157_IRQHandler: + ldr r0,=Reserved157_DriverIRQHandler + bx r0 + .size Reserved157_IRQHandler, . - Reserved157_IRQHandler + + .align 1 + .thumb_func + .weak Reserved158_IRQHandler + .type Reserved158_IRQHandler, %function +Reserved158_IRQHandler: + ldr r0,=Reserved158_DriverIRQHandler + bx r0 + .size Reserved158_IRQHandler, . - Reserved158_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR0_IRQHandler + .type LPTMR0_IRQHandler, %function +LPTMR0_IRQHandler: + ldr r0,=LPTMR0_DriverIRQHandler + bx r0 + .size LPTMR0_IRQHandler, . - LPTMR0_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR1_IRQHandler + .type LPTMR1_IRQHandler, %function +LPTMR1_IRQHandler: + ldr r0,=LPTMR1_DriverIRQHandler + bx r0 + .size LPTMR1_IRQHandler, . - LPTMR1_IRQHandler + + .align 1 + .thumb_func + .weak SCG_IRQHandler + .type SCG_IRQHandler, %function +SCG_IRQHandler: + ldr r0,=SCG_DriverIRQHandler + bx r0 + .size SCG_IRQHandler, . - SCG_IRQHandler + + .align 1 + .thumb_func + .weak SPC_IRQHandler + .type SPC_IRQHandler, %function +SPC_IRQHandler: + ldr r0,=SPC_DriverIRQHandler + bx r0 + .size SPC_IRQHandler, . - SPC_IRQHandler + + .align 1 + .thumb_func + .weak WUU_IRQHandler + .type WUU_IRQHandler, %function +WUU_IRQHandler: + ldr r0,=WUU_DriverIRQHandler + bx r0 + .size WUU_IRQHandler, . - WUU_IRQHandler + + .align 1 + .thumb_func + .weak PORT_EFT_IRQHandler + .type PORT_EFT_IRQHandler, %function +PORT_EFT_IRQHandler: + ldr r0,=PORT_EFT_DriverIRQHandler + bx r0 + .size PORT_EFT_IRQHandler, . - PORT_EFT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved165_IRQHandler + .type Reserved165_IRQHandler, %function +Reserved165_IRQHandler: + ldr r0,=Reserved165_DriverIRQHandler + bx r0 + .size Reserved165_IRQHandler, . - Reserved165_IRQHandler + + .align 1 + .thumb_func + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler + bx r0 + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler + + .align 1 + .thumb_func + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler + bx r0 + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler + + .align 1 + .thumb_func + .weak WWDT0_IRQHandler + .type WWDT0_IRQHandler, %function +WWDT0_IRQHandler: + ldr r0,=WWDT0_DriverIRQHandler + bx r0 + .size WWDT0_IRQHandler, . - WWDT0_IRQHandler + + .align 1 + .thumb_func + .weak WWDT1_IRQHandler + .type WWDT1_IRQHandler, %function +WWDT1_IRQHandler: + ldr r0,=WWDT1_DriverIRQHandler + bx r0 + .size WWDT1_IRQHandler, . - WWDT1_IRQHandler + + .align 1 + .thumb_func + .weak CMC0_IRQHandler + .type CMC0_IRQHandler, %function +CMC0_IRQHandler: + ldr r0,=CMC0_DriverIRQHandler + bx r0 + .size CMC0_IRQHandler, . - CMC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved171_IRQHandler + .type Reserved171_IRQHandler, %function +Reserved171_IRQHandler: + ldr r0,=Reserved171_DriverIRQHandler + bx r0 + .size Reserved171_IRQHandler, . - Reserved171_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler OR_DriverIRQHandler + def_irq_handler EDMA_0_CH0_DriverIRQHandler + def_irq_handler EDMA_0_CH1_DriverIRQHandler + def_irq_handler EDMA_0_CH2_DriverIRQHandler + def_irq_handler EDMA_0_CH3_DriverIRQHandler + def_irq_handler EDMA_0_CH4_DriverIRQHandler + def_irq_handler EDMA_0_CH5_DriverIRQHandler + def_irq_handler EDMA_0_CH6_DriverIRQHandler + def_irq_handler EDMA_0_CH7_DriverIRQHandler + def_irq_handler EDMA_0_CH8_DriverIRQHandler + def_irq_handler EDMA_0_CH9_DriverIRQHandler + def_irq_handler EDMA_0_CH10_DriverIRQHandler + def_irq_handler EDMA_0_CH11_DriverIRQHandler + def_irq_handler EDMA_0_CH12_DriverIRQHandler + def_irq_handler EDMA_0_CH13_DriverIRQHandler + def_irq_handler EDMA_0_CH14_DriverIRQHandler + def_irq_handler EDMA_0_CH15_DriverIRQHandler + def_irq_handler GPIO00_DriverIRQHandler + def_irq_handler GPIO01_DriverIRQHandler + def_irq_handler GPIO10_DriverIRQHandler + def_irq_handler GPIO11_DriverIRQHandler + def_irq_handler GPIO20_DriverIRQHandler + def_irq_handler GPIO21_DriverIRQHandler + def_irq_handler GPIO30_DriverIRQHandler + def_irq_handler GPIO31_DriverIRQHandler + def_irq_handler GPIO40_DriverIRQHandler + def_irq_handler GPIO41_DriverIRQHandler + def_irq_handler GPIO50_DriverIRQHandler + def_irq_handler GPIO51_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler Reserved49_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM0_DriverIRQHandler + def_irq_handler LP_FLEXCOMM1_DriverIRQHandler + def_irq_handler LP_FLEXCOMM2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM3_DriverIRQHandler + def_irq_handler LP_FLEXCOMM4_DriverIRQHandler + def_irq_handler LP_FLEXCOMM5_DriverIRQHandler + def_irq_handler LP_FLEXCOMM6_DriverIRQHandler + def_irq_handler LP_FLEXCOMM7_DriverIRQHandler + def_irq_handler Reserved59_DriverIRQHandler + def_irq_handler Reserved60_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler ADC1_DriverIRQHandler + def_irq_handler PINT0_DriverIRQHandler + def_irq_handler PDM_EVENT_DriverIRQHandler + def_irq_handler Reserved65_DriverIRQHandler + def_irq_handler Reserved66_DriverIRQHandler + def_irq_handler USB0_DCD_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler SMARTDMA_DriverIRQHandler + def_irq_handler Reserved70_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler Reserved74_DriverIRQHandler + def_irq_handler SAI0_DriverIRQHandler + def_irq_handler SAI1_DriverIRQHandler + def_irq_handler Reserved77_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler CAN1_DriverIRQHandler + def_irq_handler Reserved80_DriverIRQHandler + def_irq_handler Reserved81_DriverIRQHandler + def_irq_handler USB1_HS_PHY_DriverIRQHandler + def_irq_handler USB1_HS_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler Reserved85_DriverIRQHandler + def_irq_handler Reserved86_DriverIRQHandler + def_irq_handler Freqme_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler ELS_DriverIRQHandler + def_irq_handler PKC_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler Reserved92_DriverIRQHandler + def_irq_handler EDMA_1_CH0_DriverIRQHandler + def_irq_handler EDMA_1_CH1_DriverIRQHandler + def_irq_handler EDMA_1_CH2_DriverIRQHandler + def_irq_handler EDMA_1_CH3_DriverIRQHandler + def_irq_handler EDMA_1_CH4_DriverIRQHandler + def_irq_handler EDMA_1_CH5_DriverIRQHandler + def_irq_handler EDMA_1_CH6_DriverIRQHandler + def_irq_handler EDMA_1_CH7_DriverIRQHandler + def_irq_handler Reserved101_DriverIRQHandler + def_irq_handler Reserved102_DriverIRQHandler + def_irq_handler Reserved103_DriverIRQHandler + def_irq_handler Reserved104_DriverIRQHandler + def_irq_handler Reserved105_DriverIRQHandler + def_irq_handler Reserved106_DriverIRQHandler + def_irq_handler Reserved107_DriverIRQHandler + def_irq_handler Reserved108_DriverIRQHandler + def_irq_handler CDOG0_DriverIRQHandler + def_irq_handler CDOG1_DriverIRQHandler + def_irq_handler I3C0_DriverIRQHandler + def_irq_handler I3C1_DriverIRQHandler + def_irq_handler Reserved113_DriverIRQHandler + def_irq_handler GDET_DriverIRQHandler + def_irq_handler VBAT0_DriverIRQHandler + def_irq_handler EWM0_DriverIRQHandler + def_irq_handler Reserved117_DriverIRQHandler + def_irq_handler Reserved118_DriverIRQHandler + def_irq_handler Reserved119_DriverIRQHandler + def_irq_handler Reserved120_DriverIRQHandler + def_irq_handler FLEXIO_DriverIRQHandler + def_irq_handler Reserved122_DriverIRQHandler + def_irq_handler Reserved123_DriverIRQHandler + def_irq_handler Reserved124_DriverIRQHandler + def_irq_handler HSCMP0_DriverIRQHandler + def_irq_handler HSCMP1_DriverIRQHandler + def_irq_handler Reserved127_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE2_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE3_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler + def_irq_handler ITRC0_DriverIRQHandler + def_irq_handler Reserved149_DriverIRQHandler + def_irq_handler ELS_ERR_DriverIRQHandler + def_irq_handler PKC_ERR_DriverIRQHandler + def_irq_handler ERM_SINGLE_BIT_ERROR_DriverIRQHandler + def_irq_handler ERM_MULTI_BIT_ERROR_DriverIRQHandler + def_irq_handler FMU0_DriverIRQHandler + def_irq_handler Reserved155_DriverIRQHandler + def_irq_handler Reserved156_DriverIRQHandler + def_irq_handler Reserved157_DriverIRQHandler + def_irq_handler Reserved158_DriverIRQHandler + def_irq_handler LPTMR0_DriverIRQHandler + def_irq_handler LPTMR1_DriverIRQHandler + def_irq_handler SCG_DriverIRQHandler + def_irq_handler SPC_DriverIRQHandler + def_irq_handler WUU_DriverIRQHandler + def_irq_handler PORT_EFT_DriverIRQHandler + def_irq_handler Reserved165_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler + def_irq_handler WWDT0_DriverIRQHandler + def_irq_handler WWDT1_DriverIRQHandler + def_irq_handler CMC0_DriverIRQHandler + def_irq_handler Reserved171_DriverIRQHandler + + .end diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cache_lpcac.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cache_lpcac.c new file mode 100644 index 0000000000..31b4415e13 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cache_lpcac.c @@ -0,0 +1,20 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache_lpcac.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_lpcac" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cache_lpcac.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cache_lpcac.h new file mode 100644 index 0000000000..54dd1fd840 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cache_lpcac.h @@ -0,0 +1,184 @@ +/* + * Copyright 2021-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CACHE_LPCAC_H_ +#define FSL_CACHE_LPCAC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_lpcac + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version */ +#define FSL_CACHE_LPCAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name cache control for the L1 low power cache controller + *@{ + */ + +/*! + * @brief Enables the processor code bus cache. + * + */ +static inline void L1CACHE_EnableCodeCache(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; +} + +/*! + * @brief Disables the processor code bus cache. + * + */ +static inline void L1CACHE_DisableCodeCache(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; +} + +/*! + * @brief Clears cache. + * + */ +static inline void L1CACHE_InvalidateCodeCache(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK; +} + +/*! + * @brief Enables allocation. + * + */ +static inline void L1CACHE_EnableAllocation(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; +} + +/*! + * @brief Disables allocation. + * + */ +static inline void L1CACHE_DisableAllocation(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK; +} + +/*! + * @brief Enables parity. + * + */ +static inline void L1CACHE_EnableParity(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; +} + +/*! + * @brief Disable parity. + * + */ +static inline void L1CACHE_DisableParity(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_MISS_EN_MASK; +} + +#if defined(FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL) && FSL_FEATURE_LPCAC_SUPPORT_WRITE_BUFFER_CONTROL +/*! + * @brief Enables write through buffer. + * + */ +static inline void L1CACHE_EnableWriteBuffer(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK; +} + +/*! + * @brief Disables write through buffer. + * + */ +static inline void L1CACHE_DisableWriteBuffer(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK; +} + +/*! + * @brief Limits write through buffer. + * + */ +static inline void L1CACHE_LimitWriteBuffer(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK; +} + +/*! + * @brief Unlimits write through buffer. + * + */ +static inline void L1CACHE_UnlimitParity(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK; +} + +/*! + * @brief Enables parity error report. + * + */ +static inline void L1CACHE_EnableParityErrorReport(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK; +} + +/*! + * @brief Disables parity error report. + * + */ +static inline void L1CACHE_DisableParityErrorReport(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_PARITY_FAULT_EN_MASK; +} + +/*! + * @brief Enables XOM(eXecute-Only-Memory) control. + * + */ +static inline void L1CACHE_EnableXOMControl(void) +{ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK; +} + +/*! + * @brief Disables XOM(eXecute-Only-Memory) control. + * + */ +static inline void L1CACHE_DisableXOMControl(void) +{ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK; +} +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_CACHE_LPCAC_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cdog.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cdog.c new file mode 100644 index 0000000000..301dd0907b --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cdog.c @@ -0,0 +1,396 @@ +/* + * Copyright 2020-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cdog.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cdog" +#endif + +/* Reset CONTROL mask */ +#define RESERVED_CTRL_MASK 0x800u + +#if defined(CDOG_IRQS) +/* Array of IRQs */ +static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS; +#endif /* CDOG_IRQS */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(CDOG) +/*! + * Weak implementation of CDOG IRQ, should be re-defined by user when using CDOG IRQ + */ +__WEAK void CDOG_DriverIRQHandler(void) +{ + /* NVIC_DisableIRQ(CDOG_IRQn); + * CDOG_Stop(CDOG, s_start); + * CDOG->FLAGS = 0x0U; + * CDOG_Start(CDOG, 0xFFFFFFU, s_start); + * NVIC_EnableIRQ(CDOG_IRQn); + */ +} +#endif + +#if defined(CDOG0) +/*! + * Weak implementation of CDOG0 IRQ, should be re-defined by user when using CDOG IRQ + */ +__WEAK void CDOG0_DriverIRQHandler(void) +{ + /* NVIC_DisableIRQ(CDOG0_IRQn); + * CDOG_Stop(CDOG0, s_start); + * CDOG0->FLAGS = 0x0U; + * CDOG_Start(CDOG0, 0xFFFFFFU, s_start); + * NVIC_EnableIRQ(CDOG0_IRQn); + */ +} +#endif + +#if defined(CDOG1) +/*! + * Weak implementation of CDOG1 IRQ, should be re-defined by user when using CDOG IRQ + */ +__WEAK void CDOG1_DriverIRQHandler(void) +{ + /* NVIC_DisableIRQ(CDOG1_IRQn); + * CDOG_Stop(CDOG1, s_start); + * CDOG1->FLAGS = 0x0U; + * CDOG_Start(CDOG1, 0xFFFFFFU, s_start); + * NVIC_EnableIRQ(CDOG1_IRQn); + */ +} +#endif + +/*! + * brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf) +{ + /* Default configuration after reset */ + conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */ + conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */ + conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */ + conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */ + conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */ + conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */ + conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */ + conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */ + return; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers for instruction timer. + * + * param base CDOG peripheral base address + * param reload reload value + * param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start) +{ + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state of CDOG to IDLE. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop) +{ + base->STOP = stop; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + * param reload reload value for instruction timer + * param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start) +{ + base->STOP = stop; + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add) +{ + base->ADD = (secure_counter_t)add; +} + +/*! + * brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add1(CDOG_Type *base) +{ + base->ADD1 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add16(CDOG_Type *base) +{ + base->ADD16 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add256(CDOG_Type *base) +{ + base->ADD256 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub) +{ + base->SUB = (secure_counter_t)sub; +} + +/*! + * brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base) +{ + base->SUB1 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base) +{ + base->SUB16 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base) +{ + base->SUB256 = (secure_counter_t)0x1U; +} + +/*! + * brief Checks secure counter. + * + * This function compares stop value with secure counter value + * by writting to RELOAD refister. + * + * param base CDOG peripheral base address + * param check expected (stop) value. + */ +void CDOG_Check(CDOG_Type *base, uint32_t check) +{ + base->RESTART = check; +} + +/*! + * brief Set the CDOG persistent word. + * + * param base CDOG peripheral base address. + * param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value) +{ + base->PERSISTENT = value; +} + +/*! + * brief Get the CDOG persistent word. + * + * param base CDOG peripheral base address. + * return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base) +{ + return base->PERSISTENT; +} + +/*! + * brief Initialize CDOG + * + * This function initializes CDOG setting and enable all interrupts. + * + * param base CDOG peripheral base address + * param conf CDOG configuration structure + * return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) +{ + /* Ungate clock to CDOG engine and reset it */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifdef CDOG_CLOCKS + CLOCK_EnableClock(kCLOCK_Cdog); +#endif /* CDOG_CLOCKS */ +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + + if (base->CONTROL == 0x0U) + { + /* CDOG is not in IDLE mode, which may be cause after SW reset. */ + /* Writing to CONTROL register will trigger fault. */ + return kStatus_Fail; + } + + /* Clear pending errors, otherwise the device will reset */ + /* itself immediately after enable Code Watchdog */ + if ((uint32_t)kCDOG_LockCtrl_Lock == + ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT)) + + { + base->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) | + CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) | + CDOG_FLAGS_POR_FLAG(1U); + } + else + { +/* load default values for CDOG->CONTROL before flags clear */ +#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0) + cdog_config_t default_conf; + + /* Initialize CDOG */ + CDOG_GetDefaultConfig(&default_conf); + + /* Write default value to CDOG->CONTROL*/ + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(default_conf.state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */ + CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */ +#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */ + + base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | + CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | + CDOG_FLAGS_POR_FLAG(0U); + } + + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL(conf->debug_halt) | /* Halt CDOG timer during debug */ + CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */ + +#if defined(CDOG_IRQS) + /* Enable peripheral IRQs, if defined in array */ + for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++) + { + NVIC_EnableIRQ(s_CdogIrqs[i]); + } +#endif /* CDOG_IRQS */ + + return kStatus_Success; +} + +/*! + * brief Deinitialize CDOG + * + * This function stops CDOG secure counter. + * + * param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base) +{ +#if defined(CDOG_IRQS) + /* Enable peripheral IRQs, if defined in array */ + for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++) + { + NVIC_DisableIRQ(s_CdogIrqs[i]); + } +#endif /* CDOG_IRQS */ + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifdef CDOG_CLOCKS + CLOCK_DisableClock(kCLOCK_Cdog); +#endif /* CDOG_CLOCKS */ +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cdog.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cdog.h new file mode 100644 index 0000000000..924ac5684c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cdog.h @@ -0,0 +1,337 @@ +/* + * Copyright 2020-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CDOG_H_ +#define FSL_CDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup CDOG + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines CDOG driver version 2.1.2. + * + * Change log: + * - Version 2.1.2 + * - Support multiple IRQs + * - Fix default CONTROL values + * - Version 2.1.1 + * - Remove bit CONTROL[CONTROL_CTRL] + * - Version 2.1.0 + * - Rename CWT to CDOG + * - Version 2.0.2 + * - Fix MISRA-2012 issues + * - Version 2.0.1 + * - Fix doxygen issues + * - Version 2.0.0 + * - initial version + */ +#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*@}*/ + +typedef struct +{ + uint8_t lock : 2; + uint8_t timeout : 3; + uint8_t miscompare : 3; + uint8_t sequence : 3; + uint8_t state : 3; + uint8_t address : 3; + uint8_t reserved : 8; + uint8_t irq_pause : 2; + uint8_t debug_halt : 2; +} cdog_config_t; + +enum __cdog_debug_Action_ctrl_enum +{ + kCDOG_DebugHaltCtrl_Run = 0x1, + kCDOG_DebugHaltCtrl_Pause = 0x2, +}; + +enum __cdog_irq_pause_ctrl_enum +{ + kCDOG_IrqPauseCtrl_Run = 0x1, + kCDOG_IrqPauseCtrl_Pause = 0x2, +}; + +enum __cdog_fault_ctrl_enum +{ + kCDOG_FaultCtrl_EnableReset = 0x1U, + kCDOG_FaultCtrl_EnableInterrupt = 0x2U, + kCDOG_FaultCtrl_NoAction = 0x4U, +}; + +enum __code_lock_ctrl_enum +{ + kCDOG_LockCtrl_Lock = 0x1, + kCDOG_LockCtrl_Unlock = 0x2, +}; + +typedef uint32_t secure_counter_t; + +#define SC_ADD(add) \ + do \ + { \ + CDOG->ADD = (secure_counter_t)(add); \ + } while (0) + +#define SC_ADD1 \ + do \ + { \ + CDOG->ADD1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD16 \ + do \ + { \ + CDOG->ADD16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD256 \ + do \ + { \ + CDOG->ADD256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB(sub) \ + do \ + { \ + CDOG->SUB = (secure_counter_t)(sub); \ + } while (0) + +#define SC_SUB1 \ + do \ + { \ + CDOG->SUB1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB16 \ + do \ + { \ + CDOG->SUB16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB256 \ + do \ + { \ + CDOG->SUB256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_CHECK(val) \ + do \ + { \ + CDOG->RESTART = (secure_counter_t)val; \ + } while (0) + +/******************************************************************************* + * API + *******************************************************************************/ +#if defined(CDOG) +extern void CDOG_DriverIRQHandler(void); +#endif + +#if defined(CDOG0) +extern void CDOG0_DriverIRQHandler(void); +#endif + +#if defined(CDOG1) +extern void CDOG1_DriverIRQHandler(void); +#endif + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name CDOG Functional Operation + * @{ + */ + +/*! + * @brief Initialize CDOG + * + * This function initializes CDOG block and setting. + * + * @param base CDOG peripheral base address + * @param conf CDOG configuration structure + * @return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf); + +/*! + * @brief Deinitialize CDOG + * + * This function deinitializes CDOG secure counter. + * + * @param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base); + +/*! + * @brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * @param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf); + +/*! + * @brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state od CDOG to IDLE. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers + * for instruction timer and secure counter + * + * @param base CDOG peripheral base address + * @param reload reload value + * @param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start); + +/*! + * @brief Checks secure counter. + * + * This function compares stop value in handler with secure counter value + * by writting to RELOAD refister. + * + * @param base CDOG peripheral base address + * @param check expected (stop) value + */ +void CDOG_Check(CDOG_Type *base, uint32_t check); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + * @param reload reload value for instruction timer + * @param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start); + +/*! + * @brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * @param base CDOG peripheral base address. + * @param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add); + +/*! + * @brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add1(CDOG_Type *base); + +/*! + * @brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add16(CDOG_Type *base); + +/*! + * @brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add256(CDOG_Type *base); + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub); + +/*! + * @brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base); + +/*! + * @brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base); + +/*! + * @brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base); + +/*! + * @brief Set the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value); + +/*! + * @brief Get the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group cdog */ + +#endif /* FSL_CDOG_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_clock.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_clock.c new file mode 100644 index 0000000000..c9c30292d4 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_clock.c @@ -0,0 +1,2695 @@ +/* + * Copyright 2022-2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x10000U) + +#define PLL_MAX_N_DIV 0x100U + +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_NDIV_VAL_P (0U) /* NDIV is in bits 7:0 */ +#define PLL_NDIV_VAL_M (0xFFUL << PLL_NDIV_VAL_P) +#define PLL_MDIV_VAL_P (0U) /* MDIV is in bits 15:0 */ +#define PLL_MDIV_VAL_M (0xFFFFULL << PLL_MDIV_VAL_P) +#define PLL_PDIV_VAL_P (0U) /* PDIV is in bits 4:0 */ +#define PLL_PDIV_VAL_M (0x1FUL << PLL_PDIV_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (275000000U) +#define PLL_MAX_CCO_FREQ_MHZ (550000000U) +#define PLL_LOWER_IN_LIMIT (32000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_MAX_IN_SSMODE \ + (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ + +/* PLL NDIV reg */ +#define PLL_NDIV_VAL_SET(value) (((unsigned long)(value) << PLL_NDIV_VAL_P) & PLL_NDIV_VAL_M) +/* PLL MDIV reg */ +#define PLL_MDIV_VAL_SET(value) (((unsigned long long)(value) << PLL_MDIV_VAL_P) & PLL_MDIV_VAL_M) +/* PLL PDIV reg */ +#define PLL_PDIV_VAL_SET(value) (((unsigned long)(value) << PLL_PDIV_VAL_P) & PLL_PDIV_VAL_M) + +/* PLL SSCG control1 */ +#define PLL_SSCG_MD_FRACT_P 0U +#define PLL_SSCG_MD_INT_P 25U +#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P) +#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P) + +#define PLL_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_FRACT_P) & PLL_SSCG_MD_FRACT_M) +#define PLL_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL_SSCG_MD_INT_P) & PLL_SSCG_MD_INT_M) + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +volatile static uint32_t s_Ext_Clk_Freq = 16000000U; +/*! @brief External XTAL32K clock frequency. */ +volatile static uint32_t s_Xtal32_Freq = 32768U; +/*! @brief SAI MCLK clock frequency. */ +volatile static uint32_t s_Sai_Mclk_Freq[2] = {0U}; +/*! @brief SAI TX BCLK clock frequency. */ +volatile static uint32_t s_Sai_Tx_Bclk_Freq[2] = {0U}; +/*! @brief SAI RX BCLK clock frequency. */ +volatile static uint32_t s_Sai_Rx_Bclk_Freq[2] = {0U}; + +/*! @brief external UPLL clock frequency. */ +static uint32_t s_extUpllFreq = 0U; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Get FRO 12M Clk */ +static uint32_t CLOCK_GetFro12MFreq(void); +/* Get CLK 1M Clk */ +static uint32_t CLOCK_GetClk1MFreq(void); +/* Get HF FRO Clk */ +static uint32_t CLOCK_GetFroHfFreq(void); +/* Get CLK 48M Clk */ +static uint32_t CLOCK_GetClk48MFreq(void); +/* Get CLK 144M Clk */ +static uint32_t CLOCK_GetClk144MFreq(void); +/* Get CLK 16K Clk */ +static uint32_t CLOCK_GetClk16KFreq(uint32_t id); +/* Get EXT OSC Clk */ +static uint32_t CLOCK_GetExtClkFreq(void); +/* Get OSC 32K Clk */ +static uint32_t CLOCK_GetOsc32KFreq(uint32_t id); +/* Get Systick Clk */ +static uint32_t CLOCK_GetSystickClkFreq(uint32_t id); +/* Get CLOCK OUT Clk */ +static uint32_t CLOCK_GetClockOutClkFreq(void); +/* Get LP_OSC Clk */ +static uint32_t CLOCK_GetLposcFreq(void); + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL0 NDIV setting */ +static uint32_t findPll0PreDiv(void); +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void); +/* Get postdivider (P) from PLL0 PDIV setting */ +static uint32_t findPll0PostDiv(void); +/* Get postdivider (P) from PLL1 PDIV setting */ +static uint32_t findPll1PostDiv(void); +/* Get multiplier (M) from PLL0 MDIV and SSCG settings */ +static float findPll0MMult(void); +/* Get multiplier (M) from PLL1 MDIV and SSCG settings */ +static float findPll1MMult(void); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Set PLL0 output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS); +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup); +/* Get predivider (N) from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup); +/* Get postdivider (P) from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup); +/* Get multiplier (M) from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/** + * @brief Initialize the Core clock to given frequency (48 or 144 MHz). + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency (must be one of CLK_FRO_48MHZ or CLK_FRO_144MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) +{ + if ((iFreq != 48000000U) && (iFreq != 144000000U)) + { + return kStatus_Fail; + } + + /* Select 48MHz or 144MHz for FIRC clock */ + SCG0->FIRCCFG = SCG_FIRCCFG_RANGE((iFreq == 48000000U) ? 0 : 1); + + /* Unlock FIRCCSR */ + SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; + + /* Enable FIRC 48 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; + /* Enable FIRC 144 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; + + /* Enable FIRC */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return kStatus_Success; +} + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 16000000U) && (iFreq < 20000000U)) + { + range = 0U; + } + else if ((iFreq >= 20000000U) && (iFreq < 30000000U)) + { + range = 1U; + } + else if ((iFreq >= 30000000U) && (iFreq < 50000000U)) + { + range = 2U; + } + else if ((iFreq >= 50000000U) && (iFreq < 66000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If clock is used by system, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (internal crystal oscillator) and Configure SOSC range */ + SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 16000000U) && (iFreq < 20000000U)) + { + range = 0U; + } + else if ((iFreq >= 20000000U) && (iFreq < 30000000U)) + { + range = 1U; + } + else if ((iFreq >= 30000000U) && (iFreq < 50000000U)) + { + range = 2U; + } + else if ((iFreq >= 50000000U) && (iFreq < 66000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If clock is used by system, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U) + { + return (status_t)kStatus_SCG_Busy; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Select SOSC source (external reference clock)*/ + SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; + + /*Configure SOSC range */ + SCG0->SOSCCFG |= SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/** + * @brief Initialize the OSC 32K. + * @param id : OSC 32 kHz output clock to specified modules + * @return returns success or fail status. + */ +status_t CLOCK_SetupOsc32KClocking(uint32_t id) +{ + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK | SCG_LDOCSR_VOUT_OK_MASK; + + VBAT0->OSCCTLA = + (VBAT0->OSCCTLA & ~(VBAT_OSCCTLA_MODE_EN_MASK | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK)) | + VBAT_OSCCTLA_MODE_EN(0x2) | VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK; + VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xDFF7E); + /* Wait for STATUSA[OSC_RDY] to set. */ + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + VBAT0->OSCLCKA = VBAT_OSCLCKA_LOCK_MASK; + VBAT0->OSCLCKB &= ~VBAT_OSCLCKA_LOCK_MASK; + + VBAT0->OSCCLKE |= VBAT_OSCCLKE_CLKE(id); + + /* De-initializes the SCG ROSC */ + SCG0->ROSCCSR = SCG_ROSCCSR_ROSCERR_MASK; + + /* Unlock ROSCCSR */ + SCG0->ROSCCSR &= ~SCG_ROSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable ROSC */ + SCG0->ROSCCSR |= SCG_ROSCCSR_ROSCCM_MASK; + + /* Wait for ROSC clock to be valid. */ + while ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) == 0U) + { + } + + s_Xtal32_Freq = 32768U; + + return kStatus_Success; +} + +/** + * @brief Initialize the CLK16K clock. + * @param id : CLK 16 kHz output clock to specified modules + * @return returns success or fail status. + */ +status_t CLOCK_SetupClk16KClocking(uint32_t id) +{ + VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; + VBAT0->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK; + + VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; + VBAT0->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK; + + VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(id); + + return kStatus_Success; +} + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config) +{ + SCG0->FIRCTCFG = SCG_FIRCTCFG_TRIMDIV(config.trimDiv) | SCG_FIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_FircTrimNonUpdate == config.trimMode) + { + SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine); + } + + /* Set trim mode. */ + SCG0->FIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config) +{ + SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_SircTrimNonUpdate == config.trimMode) + { + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim); + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim); + } + + /* Set trim mode. */ + SCG0->SIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SOSCCSR; + + reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SOSCCSR = reg; +} + +/*! + * @brief Sets the ROSC monitor mode. + * + * This function sets the ROSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetRoscMonitorMode(scg_rosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->ROSCCSR; + + reg &= ~(SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->ROSCCSR = reg; +} + +/*! + * @brief Sets the UPLL monitor mode. + * + * This function sets the UPLL monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetUpllMonitorMode(scg_upll_monitor_mode_t mode) +{ + uint32_t reg = SCG0->UPLLCSR; + + reg &= ~(SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->UPLLCSR = reg; +} + +/*! + * @brief Sets the PLL0 monitor mode. + * + * This function sets the PLL0 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(scg_pll0_monitor_mode_t mode) +{ + uint32_t reg = SCG0->APLLCSR; + + reg &= ~(SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->APLLCSR = reg; +} + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SPLLCSR; + + reg &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SPLLCSR = reg; +} + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode) +{ + uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */ + switch ( mode ) + { + case kMD_Mode: + { + if (system_freq_hz > 50000000) + { + return kStatus_Fail; + } + if (system_freq_hz >24000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case kSD_Mode: + { + if (system_freq_hz > 100000000) + { + return kStatus_Fail; + } + if (system_freq_hz > 64000000) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + break; + } + case kOD_Mode: + { + if (system_freq_hz > 150000000) + { + return kStatus_Fail; + } + if (system_freq_hz > 100000000) + { + num_wait_states_added = 3U; + } + else if (system_freq_hz > 64000000) + { + num_wait_states_added = 2U; + } + else if (system_freq_hz > 36000000) + { + num_wait_states_added = 1U; + } + else + { + num_wait_states_added = 0U; + } + } + } + + /* additional wait-states are added */ + FMU0 -> FCTRL = (FMU0 -> FCTRL & 0xFFFFFFF0UL) | (num_wait_states_added & 0xFUL); + + return kStatus_Success; +} + +/*! + * @brief Config 32k Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param config The pointer to the structure \ref vbat_osc_config_t. + */ +void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config) +{ + uint32_t tmp32; + + if (config->enableCrystalOscillatorBypass == true) + { + base->OSCCTLA |= VBAT_OSCCTLA_OSC_BYP_EN_MASK; + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + } + else + { + tmp32 = base->OSCCTLA; + + if (config != NULL) + { + if (config->enableInternalCapBank) + { + tmp32 &= ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK); + tmp32 |= VBAT_OSCCTLA_EXTAL_CAP_SEL(config->extalCap) | VBAT_OSCCTLA_XTAL_CAP_SEL(config->xtalCap); + tmp32 |= VBAT_OSCCTLA_CAP_SEL_EN_MASK; + } + else + { + /* Disable the internal capacitance bank. */ + tmp32 &= ~VBAT_OSCCTLA_CAP_SEL_EN_MASK; + } + + tmp32 &= ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK); + tmp32 |= VBAT_OSCCTLA_COARSE_AMP_GAIN(config->coarseAdjustment); + } + base->OSCCTLA = tmp32; + while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U) + { + } + } +} + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint16_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item != 0U) + { + mux = (uint16_t)GET_ID_ITEM_MUX(item); + sel = (uint8_t)GET_ID_ITEM_SEL(item); + if (mux == CM_SCGRCCRSCSCLKSEL) + { + SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(sel); + while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(sel)) + { + } + } + else + { + ((volatile uint32_t *)pClkSel)[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint16_t mux; + uint32_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->SYSTICKCLKSEL0); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = (uint16_t)GET_ID_ITEM_MUX(tmp32); + if (tmp32 != 0UL) + { + if (mux == CM_SCGRCCRSCSCLKSEL) + { + actualSel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); + } + else + { + actualSel = (uint32_t)((volatile uint32_t *)pClkSel)[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + /* halt and reset clock dividers */ + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 0x3UL << 29U; + + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); + } +} + +/* Get IP clock dividers */ +/** + * brief Get peripheral clock dividers. + * param div_name : Clock divider name + * return peripheral clock dividers + */ +uint32_t CLOCK_GetClkDiv(clock_div_name_t div_name) +{ + uint32_t div; + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + + if ((uint32_t)(((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] & (0x3UL << 29U)) != 0UL) + { + div = 0U; + } + else + { + div = (uint32_t)((((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] & 0xFFU) + 1U); + } + + return div; +} + +/* Halt IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param Halt : Clock divider name + * return Nothing + */ +void CLOCK_HaltClkDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV[0]); + + /* halt clock dividers */ + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + + return; +} + +/* enable system clocks */ +/** + * brief system clocks enable controls. + * param mask : system clocks enable value + * return Nothing + */ +void CLOCK_SetupClockCtrl(uint32_t mask) +{ + SYSCON->CLOCK_CTRL |= mask; + + return; +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq = 0U; + + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_SystickClk0: + freq = CLOCK_GetSystickClkFreq(0U); + break; + case kCLOCK_ClockOut: + freq = CLOCK_GetClockOutClkFreq(); + break; + case kCLOCK_Clk1M: + freq = CLOCK_GetClk1MFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Clk48M: + freq = CLOCK_GetClk48MFreq(); + break; + case kCLOCK_Clk144M: + freq = CLOCK_GetClk144MFreq(); + break; + case kCLOCK_Clk16K0: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); + break; + case kCLOCK_Clk16K1: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVsys); + break; + case kCLOCK_Clk16K2: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case kCLOCK_Clk16K3: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToMain); + break; + case kCLOCK_ExtClk: + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_Osc32K0: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + case kCLOCK_Osc32K1: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVsys); + break; + case kCLOCK_Osc32K2: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case kCLOCK_Osc32K3: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToMain); + break; + case kCLOCK_Pll0Out: + freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_Pll1Out: + freq = CLOCK_GetPll1OutFreq(); + break; + case kCLOCK_UsbPllOut: + // freq = CLOCK_GetPll0OutFreq(); + break; + case kCLOCK_LpOsc: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->CTIMERCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetClk1MFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetSaiMclkFreq(0U); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + case 8U: + freq = CLOCK_GetSaiMclkFreq(1U); + break; + case 9U: + freq = CLOCK_GetSaiTxBclkFreq(0U); + break; + case 10U: + freq = CLOCK_GetSaiRxBclkFreq(0U); + break; + case 11U: + freq = CLOCK_GetSaiTxBclkFreq(1U); + break; + case 12U: + freq = CLOCK_GetSaiRxBclkFreq(1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->CTIMERCLKDIV[id] & 0xffU) + 1U); +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->ADC0CLKSEL) : (SYSCON->ADC1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->ADC0CLKDIV & SYSCON_ADC0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->ADC1CLKDIV & SYSCON_ADC1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get LPFLEXCOMM Clk */ +/*! brief Return Frequency of LPFLEXCOMM Clock + * return Frequency of LPFLEXCOMM Clock. + */ +uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->FCCLKSEL[id]) + { + case 1U: + freq = CLOCK_GetPllClkDivFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 4U: + freq = CLOCK_GetClk1MFreq(); + break; + case 5U: + // freq = CLOCK_GetUPllOutFreq(); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXCOMMCLKDIV[id] & 0xffU) + 1U); +} + + +/* Get SYSTEM PLL0 Clk */ +/*! brief Return Frequency of PLL0 + * return Frequency of PLL0 + */ +uint32_t CLOCK_GetPll0OutFreq(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL0InClockRate(); + + /* If PLL0 is work */ + if (CLOCK_IsPLL0Locked() == true) + { + prediv = findPll0PreDiv(); + postdiv = findPll0PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll0MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Get SYSTEM PLL1 Clk */ +/*! brief Return Frequency of PLL1 + * return Frequency of PLL1 + */ +uint32_t CLOCK_GetPll1OutFreq(void) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLL1InClockRate(); + + /* If PLL1 is work */ + if (CLOCK_IsPLL1Locked() == true) + { + prediv = findPll1PreDiv(); + postdiv = findPll1PostDiv(); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPll1MMult(); + workRate /= (float)postdiv; + } + + return (uint32_t)workRate; +} + +/* Get PLLClkDiv Clk */ +/*! brief Return Frequency of PLLClkDiv + * return Frequency of PLLClkDiv + */ +uint32_t CLOCK_GetPllClkDivFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->PLLCLKDIVSEL) + { + case 0U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 1U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->PLLCLKDIV & SYSCON_PLLCLKDIV_DIV_MASK) + 1U); +} + +/*! + * brief Gets the external UPLL frequency. + * + * This function gets the external UPLL frequency in Hz. + * + * return The frequency of the external UPLL. + */ +uint32_t CLOCK_GetExtUpllFreq(void) +{ + return s_extUpllFreq; +} + +/*! + * brief Sets the external UPLL frequency. + * + * This function sets the external UPLL frequency in Hz. + * Call this function after the external PLL frequency is changed. + * Otherwise, the APIs, which are used to get the frequency, may return an incorrect value. + * + * param The frequency of external UPLL. + */ +void CLOCK_SetExtUpllFreq(uint32_t freq) +{ + s_extUpllFreq = freq; +} + +/* Get I3C function Clk */ +/*! brief Return Frequency of I3C function clock + * return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->I3C0FCLKSEL) : (SYSCON->I3C1FCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetClk1MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->I3C0FCLKDIV & SYSCON_I3C0FCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->I3C1FCLKDIV & SYSCON_I3C1FCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get MICFIL Clk */ +/*! brief Return Frequency of MICFIL + * return Frequency of MICFIL + */ +uint32_t CLOCK_GetMicfilClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->MICFILFCLKSEL) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 5U: + freq = CLOCK_GetSaiMclkFreq(0U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + case 8U: + freq = CLOCK_GetSaiMclkFreq(1U); + break; + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->MICFILFCLKDIV & SYSCON_MICFILFCLKDIV_DIV_MASK) + 1U); +} + +/* Get FLEXIO Clk */ +/*! brief Return Frequency of FLEXIO + * return Frequency of FLEXIO + */ +uint32_t CLOCK_GetFlexioClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->FLEXIOCLKSEL) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + return freq / ((SYSCON->FLEXIOCLKDIV & SYSCON_FLEXIOCLKDIV_DIV_MASK) + 1U); +} + +/* Get FLEXCAN Clk */ +/*! brief Return Frequency of FLEXCAN + * return Frequency of FLEXCAN + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->FLEXCAN0CLKSEL) : (SYSCON->FLEXCAN1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->FLEXCAN0CLKDIV & SYSCON_FLEXCAN0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->FLEXCAN1CLKDIV & SYSCON_FLEXCAN1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get EWM0 Clk */ +/*! brief Return Frequency of EWM0 + * return Frequency of EWM0 + */ +uint32_t CLOCK_GetEwm0ClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->EWM0CLKSEL) + { + case 1U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 2U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get Watchdog Clk */ +/*! brief Return Frequency of Watchdog + * return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + if (id == 0U) + { + freq = CLOCK_GetClk1MFreq(); + } + else + { + switch (SYSCON->WDT1CLKSEL) + { + case 0U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 1U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFDIV & 0xffU) + 1U); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + case 3U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + } + + div = ((id == 0U) ? ((SYSCON->WDT0CLKDIV & SYSCON_WDT0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->WDT1CLKDIV & SYSCON_WDT1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get OSTIMER Clk */ +/*! brief Return Frequency of OSTIMER + * return Frequency of OSTIMER + */ +uint32_t CLOCK_GetOstimerClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->OSTIMERCLKSEL) + { + case 0U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToWake); + break; + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CMP Function Clk */ +/*! brief Return Frequency of CMP Function + * return Frequency of CMP Function + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->CMP0FCLKSEL) : (SYSCON->CMP1FCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->CMP0FCLKDIV & SYSCON_CMP0FCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->CMP1FCLKDIV & SYSCON_CMP1FCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get CMP Round Robin Clk */ +/*! brief Return Frequency of CMP Round Robin + * return Frequency of CMP Round Robin + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->CMP0RRCLKSEL) : (SYSCON->CMP1RRCLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetFro12MFreq(); + break; + case 4U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->CMP0RRCLKDIV & SYSCON_CMP0RRCLKDIV_DIV_MASK) + 1U) : + ((SYSCON->CMP1RRCLKDIV & SYSCON_CMP1RRCLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get UTICK Clk */ +/*! brief Return Frequency of UTICK + * return Frequency of UTICK + */ +uint32_t CLOCK_GetUtickClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t div = ((SYSCON->UTICKCLKDIV & SYSCON_UTICKCLKDIV_DIV_MASK) + 1U); + + switch (SYSCON->UTICKCLKSEL) + { + case 0U: + freq = CLOCK_GetExtClkFreq(); + break; + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + return freq / div; +} + +/* Get SAI Clk */ +/*! brief Return Frequency of SAI + * return Frequency of SAI + */ +uint32_t CLOCK_GetSaiClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t div = 0U; + + switch ((id == 0U) ? (SYSCON->SAI0CLKSEL) : (SYSCON->SAI1CLKSEL)) + { + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + // freq = CLOCK_GetUPllOutFreq(); + default: + freq = 0U; + break; + } + + div = ((id == 0U) ? ((SYSCON->SAI0CLKDIV & SYSCON_SAI0CLKDIV_DIV_MASK) + 1U) : + ((SYSCON->SAI1CLKDIV & SYSCON_SAI1CLKDIV_DIV_MASK) + 1U)); + + return freq / div; +} + +/* Get SAI MCLK */ +/*! brief Initialize the SAI MCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiMclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Mclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI TX BCLK */ +/*! brief Initialize the SAI TX BCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiTxBclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Tx_Bclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI RX BCLK */ +/*! brief Initialize the SAI RX BCLK to given frequency. + * return Nothing + */ +void CLOCK_SetupSaiRxBclk(uint32_t id, uint32_t iFreq) +{ + s_Sai_Rx_Bclk_Freq[id] = iFreq; + + return; +} + +/* Get SAI MCLK */ +/*! brief Return Frequency of SAI MCLK + * return Frequency of SAI MCLK + */ +uint32_t CLOCK_GetSaiMclkFreq(uint32_t id) +{ + return s_Sai_Mclk_Freq[id]; +} + +/* Get SAI TX BCLK */ +/*! brief Return Frequency of SAI TX BCLK + * return Frequency of SAI TX BCLK + */ +uint32_t CLOCK_GetSaiTxBclkFreq(uint32_t id) +{ + return s_Sai_Tx_Bclk_Freq[id]; +} + +/* Get SAI RX BCLK */ +/*! brief Return Frequency of SAI RX BCLK + * return Frequency of SAI RX BCLK + */ +uint32_t CLOCK_GetSaiRxBclkFreq(uint32_t id) +{ + return s_Sai_Rx_Bclk_Freq[id]; +} + +/* Return System PLL input clock rate */ +/*! brief Return PLL0 input clock rate + * return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) >> SCG_APLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL1 input clock rate */ +uint32_t CLOCK_GetPLL1InClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) >> SCG_SPLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return PLL output clock rate from setup structure */ +/*! brief Return PLL0 output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return PLL0 output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + float workRate = 0.0F; + + /* Get the input clock frequency of PLL. */ + clkRate = CLOCK_GetPLLInClockRateFromSetup(pSetup); + + prediv = findPllPreDivFromSetup(pSetup); + postdiv = findPllPostDivFromSetup(pSetup); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* MDEC used for rate */ + workRate = (float)clkRate * (float)findPllMMultFromSetup(pSetup); + workRate /= (float)postdiv; + + return (uint32_t)workRate; +} + +/* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0UL); + + pll_error_t pllError; + + /* Get PLL Input Clock Rate */ + switch (pControl->inputSource) + { + case (uint32_t)kPll_ClkSrcSysOsc: + inRate = CLOCK_GetExtClkFreq(); + break; + case (uint32_t)kPll_ClkSrcFirc: + inRate = CLOCK_GetClk48MFreq(); + break; + case (uint32_t)kPll_ClkSrcRosc: + inRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + inRate = 0U; + break; + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useSS); + pSetup->pllctrl |= (uint32_t)pControl->inputSource; + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->pllsscg[1] |= (1UL << SCG_APLLSSCG1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL0 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Power off PLL0 and disable PLL0 clock during setup changes */ + SCG0->APLLCSR &= ~(SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); + + /* Write PLL setup data */ + SCG0->APLLCTRL = pSetup->pllctrl; + SCG0->APLLNDIV = pSetup->pllndiv; + SCG0->APLLNDIV = pSetup->pllndiv | (1UL << SCG_APLLNDIV_NREQ_SHIFT); /* latch */ + SCG0->APLLPDIV = pSetup->pllpdiv; + SCG0->APLLPDIV = pSetup->pllpdiv | (1UL << SCG_APLLPDIV_PREQ_SHIFT); /* latch */ + SCG0->APLLMDIV = pSetup->pllmdiv; + SCG0->APLLMDIV = pSetup->pllmdiv | (1UL << SCG_APLLMDIV_MREQ_SHIFT); /* latch */ + SCG0->APLLSSCG0 = pSetup->pllsscg[0]; + SCG0->APLLSSCG1 = pSetup->pllsscg[1]; + + /* Unlock APLLLOCK_CNFG register */ + SCG0->TRIM_LOCK = 0x5a5a0001; + + /* Configure lock time of APLL stable, value = 500us/x+300, where x is the period of clk_ref (clk_in/N). */ + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + SCG0->APLLLOCK_CNFG = SCG_APLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); + + /* Power on PLL0 and enable PLL0 clock */ + SCG0->APLLCSR |= (SCG_APLLCSR_APLLPWREN_MASK | SCG_APLLCSR_APLLCLKEN_MASK); + + /* Wait for APLL lock */ + while (CLOCK_IsPLL0Locked() == false) + { + } + + if (pSetup->pllRate != CLOCK_GetPll0OutFreq()) + { + return kStatus_PLL_OutputError; + } + + return kStatus_PLL_Success; +} + +/* Setup PLL1 Frequency from pre-calculated value */ +/** + * brief Set PLL1 output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) +{ + uint32_t inRate, clkRate, prediv; + + /* Enable LDO */ + SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK; + + /* Power off PLL1 and disable PLL1 clock during setup changes */ + SCG0->SPLLCSR &= ~(SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Write PLL setup data */ + SCG0->SPLLCTRL = pSetup->pllctrl; + SCG0->SPLLNDIV = pSetup->pllndiv; + SCG0->SPLLNDIV = pSetup->pllndiv | (1UL << SCG_SPLLNDIV_NREQ_SHIFT); /* latch */ + SCG0->SPLLPDIV = pSetup->pllpdiv; + SCG0->SPLLPDIV = pSetup->pllpdiv | (1UL << SCG_SPLLPDIV_PREQ_SHIFT); /* latch */ + SCG0->SPLLMDIV = pSetup->pllmdiv; + SCG0->SPLLMDIV = pSetup->pllmdiv | (1UL << SCG_SPLLMDIV_MREQ_SHIFT); /* latch */ + SCG0->SPLLSSCG0 = pSetup->pllsscg[0]; + SCG0->SPLLSSCG1 = pSetup->pllsscg[1]; + + /* Unlock SPLLLOCK_CNFG register */ + SCG0->TRIM_LOCK = 0x5a5a0001; + + /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */ + inRate = CLOCK_GetPLL1InClockRate(); + prediv = findPll1PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + SCG0->SPLLLOCK_CNFG = SCG_SPLLLOCK_CNFG_LOCK_TIME(clkRate / 2000U + 300U); + + /* Power on PLL1 and enable PLL1 clock */ + SCG0->SPLLCSR |= (SCG_SPLLCSR_SPLLPWREN_MASK | SCG_SPLLCSR_SPLLCLKEN_MASK); + + /* Wait for APLL lock */ + while (CLOCK_IsPLL1Locked() == false) + { + } + + if (pSetup->pllRate != CLOCK_GetPll1OutFreq()) + { + return kStatus_PLL_OutputError; + } + + return kStatus_PLL_Success; +} + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void) +{ + // PMC->OSEVENTTIMER |= PMC_OSEVENTTIMER_CLOCKENABLE_MASK; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0UL) ? 12000000U : 0U; +} + +/* Get CLK 1M Clk */ +/*! brief Return Frequency of CLK 1MHz + * return Frequency of CLK 1MHz + */ +static uint32_t CLOCK_GetClk1MFreq(void) +{ + return 1000000U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + uint32_t freq; + + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0UL) + { + freq = 0; + } + else if ((SCG0->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) != 0UL) + { + freq = 144000000U; + } + else + { + freq = 48000000U; + } + + return freq; +} + +/* Get CLK 48M Clk */ +/*! brief Return Frequency of CLK 48MHz + * return Frequency of CLK 48MHz + */ +static uint32_t CLOCK_GetClk48MFreq(void) +{ + return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) ? 48000000U : 0U; +} + +/* Get CLK 144M Clk */ +/*! brief Return Frequency of CLK 144MHz + * return Frequency of CLK 144MHz + */ +static uint32_t CLOCK_GetClk144MFreq(void) +{ + return ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) != 0U) ? 144000000U : 0U; +} + +/* Get CLK 16K Clk */ +/*! brief Return Frequency of CLK 16KHz + * return Frequency of CLK 16KHz + */ +static uint32_t CLOCK_GetClk16KFreq(uint32_t id) +{ + return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? + (((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE(id)) != 0UL) ? 16000U : 0U) : + 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; +} + +/* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +static uint32_t CLOCK_GetOsc32KFreq(uint32_t id) +{ + return ((SCG0->ROSCCSR & SCG_ROSCCSR_ROSCVLD_MASK) != 0UL) ? + (((VBAT0->OSCCLKE & VBAT_OSCCLKE_CLKE(id)) != 0UL) ? s_Xtal32_Freq : 0U) : + 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + uint32_t freq = 0U; + + switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 1U: + freq = CLOCK_GetExtClkFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToWake); + break; + case 5U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 6U: + freq = CLOCK_GetPll1OutFreq(); + break; + case 7U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get Systick Clk */ +/*! brief Return Frequency of SystickClock + * return Frequency of Systick Clock + */ +static uint32_t CLOCK_GetSystickClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + switch (SYSCON->SYSTICKCLKSEL0) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetClk1MFreq(); + break; + case 2U: + freq = CLOCK_GetLposcFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ +static uint32_t CLOCK_GetClockOutClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPll0OutFreq(); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetFro12MFreq(); + break; + case 5U: + freq = CLOCK_GetPll1OutFreq() / (((SYSCON->PLL1CLK0DIV) & 0xffU) + 1U); + break; + case 6U: + freq = CLOCK_GetLposcFreq(); + break; + case 7U: + // freq = CLOCK_GetUPllOutFreq(); + break; + default: + freq = 0U; + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); +} + +/* Get LP_OSC Clk */ +/*! brief Return Frequency of LP_OSC + * return Frequency of LP_OSC + */ +static uint32_t CLOCK_GetLposcFreq(void) +{ + uint32_t freq = 0U; + + switch ((RTC0->CTRL & RTC_CTRL_CLK_SEL_MASK) >> RTC_CTRL_CLK_SEL_SHIFT) + { + case 1U: + freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + case 2U: + freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + uint32_t seli, selp; + /* bandwidth: compute selP from Multiplier */ + if ((SCG0->APLLCTRL & SCG_APLLCTRL_LIMUPOFF_MASK) == 0UL) /* normal mode */ + { + selp = (M >> 2U) + 1U; + if (selp >= 31U) + { + selp = 31U; + } + *pSelP = selp; + + if (M >= 8000UL) + { + seli = 1UL; + } + else if (M >= 122UL) + { + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ + } + else + { + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ + } + + if (seli >= 63UL) + { + seli = 63UL; + } + *pSelI = seli; + + *pSelR = 0U; + } + else + { + /* Note: If the spread spectrum and fractional mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ + *pSelP = 3U; + *pSelI = 4U; + *pSelR = 4U; + } +} + +/* Get predivider (N) from PLL0 NDIV setting */ +static uint32_t findPll0PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SCG0->APLLNDIV & SCG_APLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get predivider (N) from PLL1 NDIV setting */ +static uint32_t findPll1PreDiv(void) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = SCG0->SPLLNDIV & SCG_SPLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from PLL0 PDIV setting */ +static uint32_t findPll0PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SCG0->APLLCTRL & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (SCG0->APLLPDIV & SCG_APLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get postdivider (P) from PLL1 PDIV setting. */ +static uint32_t findPll1PostDiv(void) +{ + uint32_t postDiv = 1UL; + + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((SCG0->SPLLCTRL & SCG_SPLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (SCG0->SPLLPDIV & SCG_SPLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ +static float findPll0MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(SCG0->APLLMDIV & SCG_APLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((SCG0->APLLSSCG1 & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((SCG0->APLLSSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = + ((float)(uint32_t)((SCG0->APLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Get multiplier (M) from PLL1 MDEC. */ +static float findPll1MMult(void) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(SCG0->SPLLMDIV & SCG_SPLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((SCG0->SPLLSSCG1 & SCG_SPLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((SCG0->SPLLSSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = + ((float)(uint32_t)((SCG0->SPLLSSCG0) & PLL_SSCG_MD_FRACT_M) / (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/* Find greatest common divisor between m and n */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndiv = s_PllSetupCacheStruct[i].pllndiv; + pSetup->pllmdiv = s_PllSetupCacheStruct[i].pllmdiv; + pSetup->pllpdiv = s_PllSetupCacheStruct[i].pllpdiv; + pSetup->pllsscg[0] = s_PllSetupCacheStruct[i].pllsscg[0]; + pSetup->pllsscg[1] = s_PllSetupCacheStruct[i].pllsscg[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndiv = pSetup->pllndiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllmdiv = pSetup->pllmdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdiv = pSetup->pllpdiv; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[0] = pSetup->pllsscg[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllsscg[1] = pSetup->pllsscg[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL0 setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndiv", "pllpdiv", "pllmdiv" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useSS) +{ + uint32_t nDivOutHz, fccoHz; + uint32_t pllPreDivider, pllMultiplier, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 1U; /* 1 implies post-divider will be disabled */ + pllDirectOutput = 1U; + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 3MHz and 20MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 20MHz */ + if (finHz > (PLL_MAX_IN_SSMODE * NVALMAX)) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + if (finHz > PLL_HIGHER_IN_LIMIT) + { + /* Input clock into the PLL cannot be higher than this */ + return kStatus_PLL_InputTooHigh; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + /* divide-by-2 divider in the post-divider is always work*/ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, finHz); + + if (a > PLL_LOWER_IN_LIMIT) + { + a = finHz / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz); + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, &pllSelP, &pllSelI, &pllSelR); + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->pllmdiv = (uint32_t)PLL_MDIV_VAL_SET(pllMultiplier); + pSetup->pllsscg[1] &= ~SCG_APLLSSCG1_SEL_SS_MDIV_MASK; + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = 0UL; + pllSelI = 0UL; + pllSelP = 0UL; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(uint32_t)(fccoHz % nDivOutHz) << 25UL) / nDivOutHz; + + /* Set multiplier */ + pSetup->pllsscg[0] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) | PLL_SSCG_MD_FRACT_SET((uint32_t)fc)); + pSetup->pllsscg[1] = (uint32_t)(PLL_SSCG_MD_INT_SET(pllMultiplier) >> 32U) | SCG_APLLSSCG1_SEL_SS_MDIV_MASK; + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->pllndiv = PLL_NDIV_VAL_SET(pllPreDivider); + pSetup->pllpdiv = PLL_PDIV_VAL_SET(pllPostDivider); + + /* PLL control */ + pSetup->pllctrl = (pllSelR << SCG_APLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SCG_APLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SCG_APLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (uplimoff << SCG_APLLCTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SCG_APLLCTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SCG_APLLCTRL_BYPASSPOSTDIV_SHIFT); /* Bypass post-divider? */ + + return kStatus_PLL_Success; +} + +/* Get PLL input clock rate from setup structure */ +static uint32_t CLOCK_GetPLLInClockRateFromSetup(pll_setup_t *pSetup) +{ + uint32_t clkRate = 0U; + + switch ((pSetup->pllctrl & SCG_APLLCTRL_SOURCE_MASK) >> SCG_APLLCTRL_SOURCE_SHIFT) + { + case 0x00U: + clkRate = CLOCK_GetExtClkFreq(); + break; + case 0x01U: + clkRate = CLOCK_GetClk48MFreq(); + break; + case 0x02U: + clkRate = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat); + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Get predivider (N) from from setup structure */ +static uint32_t findPllPreDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t preDiv = 1UL; + + /* Direct input is not used? */ + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPREDIV_MASK) == 0UL) + { + preDiv = pSetup->pllndiv & SCG_APLLNDIV_NDIV_MASK; + if (preDiv == 0UL) + { + preDiv = 1UL; + } + } + return preDiv; +} + +/* Get postdivider (P) from from setup structure */ +static uint32_t findPllPostDivFromSetup(pll_setup_t *pSetup) +{ + uint32_t postDiv = 1UL; + + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPOSTDIV_MASK) == 0UL) + { + if ((pSetup->pllctrl & SCG_APLLCTRL_BYPASSPOSTDIV2_MASK) != 0UL) + { + postDiv = pSetup->pllpdiv & SCG_APLLPDIV_PDIV_MASK; + } + else + { + postDiv = 2UL * (pSetup->pllpdiv & SCG_APLLPDIV_PDIV_MASK); + } + if (postDiv == 0UL) + { + postDiv = 2UL; + } + } + + return postDiv; +} + +/* Get multiplier (M) from from setup structure */ +static float findPllMMultFromSetup(pll_setup_t *pSetup) +{ + float mMult = 1.0F; + float mMult_fract; + uint32_t mMult_int; + + if ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SEL_SS_MDIV_MASK) == 0UL) + { + mMult = (float)(uint32_t)(pSetup->pllmdiv & SCG_APLLMDIV_MDIV_MASK); + } + else + { + mMult_int = ((pSetup->pllsscg[1] & SCG_APLLSSCG1_SS_MDIV_MSB_MASK) << 7U); + mMult_int = mMult_int | ((pSetup->pllsscg[0]) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((pSetup->pllsscg[0]) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; + } + if (0ULL == ((uint64_t)mMult)) + { + mMult = 1.0F; + } + return mMult; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsPhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool err = false; + + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + USBPHY->ANACTRL_SET = USBPHY_ANACTRL_LVI_EN_MASK; + USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); + if ((480000000UL % freq) != 0UL) + { + return false; + } + multiplier = (uint16_t)(480000000UL / freq); + + switch (multiplier) + { + case 15: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 16: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 20: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 22: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U); + break; + } + case 24: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 40: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + err = true; + break; + } + } + + if (err) + { + return false; + } + + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; + + USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; + USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + USBPHY->PWD = 0x0U; + + while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhsPhyPllClock(void) +{ + USBPHY->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! brief Enable USB HS clock. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsClock(void) +{ + USBHS1__USBC->USBCMD |= USBHS_USBCMD_RST_MASK; + /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + for (uint32_t i = 0; i < 400000U; i++) + { + __ASM("nop"); + } + return true; +} + +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void) +{ + /* System OSC Clock Monitor is disabled */ + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); + + firc_trim_config_t fircAutoTrimConfig = { + .trimMode = kSCG_FircTrimUpdate, /* FIRC trim is enabled and trim value update is enabled */ + .trimSrc = kSCG_FircTrimSrcUsb0, /* Trim source is USB0 start of frame (1kHz) */ + .trimDiv = 1U, /* Divided value */ + .trimCoar = 0U, /* Trim value, see Reference Manual for more information */ + .trimFine = 0U, /* Trim value, see Reference Manual for more information */ + }; + CLOCK_FROHFTrimConfig(fircAutoTrimConfig); + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return (status_t)kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_clock.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_clock.h new file mode 100644 index 0000000000..649eceb3e9 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_clock.h @@ -0,0 +1,1726 @@ +/* + * Copyright 2022-2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.0.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) +#endif + +/*! @brief Clock ip name array for ROM. */ +#define ROM_CLOCKS \ + { \ + kCLOCK_Rom \ + } +/*! @brief Clock ip name array for SRAM. */ +#define SRAM_CLOCKS \ + { \ + kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3, kCLOCK_Sram4, kCLOCK_Sram5, kCLOCK_Sram6, kCLOCK_Sram7 \ + } +/*! @brief Clock ip name array for FMC. */ +#define FMC_CLOCKS \ + { \ + kCLOCK_Fmc \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4 \ + } +/*! @brief Clock ip name array for PINT. */ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock gate name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma0, kCLOCK_Dma1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc0 \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt0, kCLOCK_Wwdt1 \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_Adc0, kCLOCK_Adc1 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_OsTimer \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ + } +/*! @brief Clock ip name array for LP_FLEXCOMM. */ +#define LP_FLEXCOMM_CLOCKS \ + { \ + kCLOCK_LPFlexComm0, kCLOCK_LPFlexComm1, kCLOCK_LPFlexComm2, kCLOCK_LPFlexComm3, kCLOCK_LPFlexComm4, \ + kCLOCK_LPFlexComm5, kCLOCK_LPFlexComm6, kCLOCK_LPFlexComm7 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_LPUart0, kCLOCK_LPUart1, kCLOCK_LPUart2, kCLOCK_LPUart3, kCLOCK_LPUart4, kCLOCK_LPUart5, \ + kCLOCK_LPUart6, kCLOCK_LPUart7 \ + } +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_LPI2c0, kCLOCK_LPI2c1, kCLOCK_LPI2c2, kCLOCK_LPI2c3, kCLOCK_LPI2c4, kCLOCK_LPI2c5, kCLOCK_LPI2c6, \ + kCLOCK_LPI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_LPSpi0, kCLOCK_LPSpi1, kCLOCK_LPSpi2, kCLOCK_LPSpi3, kCLOCK_LPSpi4, kCLOCK_LPSpi5, kCLOCK_LPSpi6, \ + kCLOCK_LPSpi7 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_Freqme \ + } +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } +/*! @brief Clock ip name array for VREF. */ +#define VREF_CLOCKS \ + { \ + kCLOCK_Vref \ + } +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_Pwm0_Sm0, kCLOCK_Pwm0_Sm1, kCLOCK_Pwm0_Sm2, kCLOCK_Pwm0_Sm3}, \ + { \ + kCLOCK_Pwm1_Sm0, kCLOCK_Pwm1_Sm1, kCLOCK_Pwm1_Sm2, kCLOCK_Pwm1_Sm3 \ + } \ + } +/*! @brief Clock ip name array for QDC. */ +#define QDC_CLOCKS \ + { \ + kCLOCK_Qdc0, kCLOCK_Qdc1 \ + } +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_Flexio \ + } +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_Flexcan0, kCLOCK_Flexcan1 \ + } +/*! @brief Clock ip name array for I3C */ +#define I3C_CLOCKS \ + { \ + kCLOCK_I3c0, kCLOCK_I3c1 \ + } +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_uSdhc \ + } +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_Sai0, kCLOCK_Sai1 \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc0 \ + } +/*! @brief Clock ip name array for PDM. */ +#define PDM_CLOCKS \ + { \ + kCLOCK_Micfil \ + } +/*! @brief Clock ip name array for ERM. */ +#define ERM_CLOCKS \ + { \ + kCLOCK_Erm \ + } +/*! @brief Clock ip name array for EIM. */ +#define EIM_CLOCKS \ + { \ + kCLOCK_Eim \ + } +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } +/*! @brief Clock ip name array for LPCMP. */ +#define LPCMP_CLOCKS \ + { \ + kCLOCK_None, kCLOCK_None, kCLOCK_Cmp2 \ + } +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define AHB_CLK_CTRL2 2 +#define AHB_CLK_CTRL3 3 +#define REG_PWM0SUBCTL 250 +#define REG_PWM1SUBCTL 251 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_None = 0U, /*!< None clock gate. */ + + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 2), /*!< Clock gate name: Sram1. */ + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram2. */ + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram3. */ + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram4. */ + kCLOCK_Sram5 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram5. */ + kCLOCK_Sram6 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Sram6. */ + kCLOCK_Sram7 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Sram7. */ + kCLOCK_Fmu = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), /*!< Clock gate name: Fmu. */ + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), /*!< Clock gate name: Fmc. */ + kCLOCK_InputMux0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 12), /*!< Clock gate name: InputMux0. */ + kCLOCK_Port0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Port0. */ + kCLOCK_Port1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Port1. */ + kCLOCK_Port2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Port2. */ + kCLOCK_Port3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Port3. */ + kCLOCK_Port4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Port4. */ + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gpio0. */ + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Gpio1. */ + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Gpio2. */ + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Gpio3. */ + kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Gpio4. */ + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 25), /*!< Clock gate name: Pint. */ + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Dma0. */ + kCLOCK_Crc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Crc. */ + kCLOCK_Wwdt0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 28), /*!< Clock gate name: Wwdt0. */ + kCLOCK_Wwdt1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 29), /*!< Clock gate name: Wwdt1. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + kCLOCK_OsTimer = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer. */ + kCLOCK_Sct = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct. */ + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 3), /*!< Clock gate name: Adc0. */ + kCLOCK_Adc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 4), /*!< Clock gate name: Adc1. */ + kCLOCK_Rtc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), /*!< Clock gate name: Rtc. */ + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick. */ + kCLOCK_LPFlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPFlexComm0. */ + kCLOCK_LPFlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPFlexComm1. */ + kCLOCK_LPFlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPFlexComm2. */ + kCLOCK_LPFlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPFlexComm3. */ + kCLOCK_LPFlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPFlexComm4. */ + kCLOCK_LPFlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPFlexComm5. */ + kCLOCK_LPFlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPFlexComm6. */ + kCLOCK_LPFlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPFlexComm7. */ + kCLOCK_LPUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPUart0. */ + kCLOCK_LPUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPUart1. */ + kCLOCK_LPUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPUart2. */ + kCLOCK_LPUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPUart3. */ + kCLOCK_LPUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPUart4. */ + kCLOCK_LPUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPUart5. */ + kCLOCK_LPUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPUart6. */ + kCLOCK_LPUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPUart7. */ + kCLOCK_LPSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPSpi0. */ + kCLOCK_LPSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPSpi1. */ + kCLOCK_LPSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPSpi2. */ + kCLOCK_LPSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPSpi3. */ + kCLOCK_LPSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPSpi4. */ + kCLOCK_LPSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPSpi5. */ + kCLOCK_LPSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPSpi6. */ + kCLOCK_LPSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPSpi7. */ + kCLOCK_LPI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LPI2c0. */ + kCLOCK_LPI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LPI2c1. */ + kCLOCK_LPI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LPI2c2. */ + kCLOCK_LPI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LPI2c3. */ + kCLOCK_LPI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LPI2c4. */ + kCLOCK_LPI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LPI2c5. */ + kCLOCK_LPI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LPI2c6. */ + kCLOCK_LPI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LPI2c7. */ + kCLOCK_Micfil = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 21), /*!< Clock gate name: Micfil. */ + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + kCLOCK_Usb0FsDcd = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 24), /*!< Clock gate name: Usb0FsDcd. */ + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + kCLOCK_PkcRam = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), /*!< Clock gate name: PkcRam. */ + kCLOCK_Smartdma = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: SmartDma. */ + + kCLOCK_Espi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 0), /*!< Clock gate name: Espi. */ + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + kCLOCK_Flexio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Flexio. */ + kCLOCK_Sai0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Sai0. */ + kCLOCK_Sai1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: Sai1. */ + kCLOCK_Tro = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Tro. */ + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + kCLOCK_Trng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Trng. */ + kCLOCK_Flexcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: Flexcan0. */ + kCLOCK_Flexcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Flexcan1. */ + kCLOCK_UsbHs = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: UsbHs. */ + kCLOCK_UsbHsPhy = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: UsbHsPhy. */ + kCLOCK_Css = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: Css. */ + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + kCLOCK_Pkc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Pkc. */ + kCLOCK_Scg = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 26), /*!< Clock gate name: Scg. */ + kCLOCK_Gdet = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: Gdet. */ + kCLOCK_Sm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30), /*!< Clock gate name: Sm3. */ + + kCLOCK_I3c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 0), /*!< Clock gate name: I3c0. */ + kCLOCK_I3c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 1), /*!< Clock gate name: I3c1. */ + kCLOCK_Qdc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 4), /*!< Clock gate name: Qdc0. */ + kCLOCK_Qdc1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 5), /*!< Clock gate name: Qdc1. */ + kCLOCK_Pwm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 6), /*!< Clock gate name: Pwm0. */ + kCLOCK_Pwm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 7), /*!< Clock gate name: Pwm1. */ + kCLOCK_Evtg = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 8), /*!< Clock gate name: Evtg. */ + kCLOCK_Cmp2 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 18), /*!< Clock gate name: Cmp2. */ + kCLOCK_Vref = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 19), /*!< Clock gate name: Vref. */ + kCLOCK_Ewm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Ewm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 23), /*!< Clock gate name: Ewm. */ + kCLOCK_Eim = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 24), /*!< Clock gate name: Eim. */ + kCLOCK_Erm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 25), /*!< Clock gate name: Erm. */ + kCLOCK_Intm = CLK_GATE_DEFINE(AHB_CLK_CTRL3, 26), /*!< Clock gate name: Intm. */ + + kCLOCK_Pwm0_Sm0 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 0U), /*!< Clock gate name: PWM0 SM0. */ + kCLOCK_Pwm0_Sm1 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 1U), /*!< Clock gate name: PWM0 SM1. */ + kCLOCK_Pwm0_Sm2 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 2U), /*!< Clock gate name: PWM0 SM2. */ + kCLOCK_Pwm0_Sm3 = CLK_GATE_DEFINE(REG_PWM0SUBCTL, 3U), /*!< Clock gate name: PWM0 SM3. */ + + kCLOCK_Pwm1_Sm0 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 0U), /*!< Clock gate name: PWM1 SM0. */ + kCLOCK_Pwm1_Sm1 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 1U), /*!< Clock gate name: PWM1 SM1. */ + kCLOCK_Pwm1_Sm2 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 2U), /*!< Clock gate name: PWM1 SM2. */ + kCLOCK_Pwm1_Sm3 = CLK_GATE_DEFINE(REG_PWM1SUBCTL, 3U) /*!< Clock gate name: PWM1 SM3. */ + +} clock_ip_name_t; + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +#define I2C0_CLK_SRC BUS_CLK + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_SystickClk0, /*!< Systick clock0 */ + kCLOCK_ClockOut, /*!< CLOCKOUT */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Clk1M, /*!< CLK1M */ + kCLOCK_FroHf, /*!< FRO48/144 */ + kCLOCK_Clk48M, /*!< CLK48M */ + kCLOCK_Clk144M, /*!< CLK144M */ + kCLOCK_Clk16K0, /*!< CLK16K[0] */ + kCLOCK_Clk16K1, /*!< CLK16K[1] */ + kCLOCK_Clk16K2, /*!< CLK16K[2] */ + kCLOCK_Clk16K3, /*!< CLK16K[3] */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_Osc32K0, /*!< OSC32K[0] */ + kCLOCK_Osc32K1, /*!< OSC32K[1] */ + kCLOCK_Osc32K2, /*!< OSC32K[2] */ + kCLOCK_Osc32K3, /*!< OSC32K[3] */ + kCLOCK_Pll0Out, /*!< PLL0 Output */ + kCLOCK_Pll1Out, /*!< PLL1 Output */ + kCLOCK_UsbPllOut, /*!< USB PLL Output */ + kCLOCK_LpOsc, /*!< lp_osc */ +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 12U) << ((uint32_t)(pos)*16U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 16U) +#define GET_ID_ITEM_MUX(connection) (((uint16_t)connection) & 0xFFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF000U) >> 12U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_SYSTICKCLKSEL0 0U +#define CM_TRACECLKSEL ((0x268 - 0x260) / 4) +#define CM_CTIMERCLKSEL0 ((0x26C - 0x260) / 4) +#define CM_CTIMERCLKSEL1 ((0x270 - 0x260) / 4) +#define CM_CTIMERCLKSEL2 ((0x274 - 0x260) / 4) +#define CM_CTIMERCLKSEL3 ((0x278 - 0x260) / 4) +#define CM_CTIMERCLKSEL4 ((0x27C - 0x260) / 4) +#define CM_CLKOUTCLKSEL ((0x288 - 0x260) / 4) +#define CM_ADC0CLKSEL ((0x2A4 - 0x260) / 4) +#define CM_FCCLKSEL0 ((0x2B0 - 0x260) / 4) +#define CM_FCCLKSEL1 ((0x2B4 - 0x260) / 4) +#define CM_FCCLKSEL2 ((0x2B8 - 0x260) / 4) +#define CM_FCCLKSEL3 ((0x2BC - 0x260) / 4) +#define CM_FCCLKSEL4 ((0x2C0 - 0x260) / 4) +#define CM_FCCLKSEL5 ((0x2C4 - 0x260) / 4) +#define CM_FCCLKSEL6 ((0x2C8 - 0x260) / 4) +#define CM_FCCLKSEL7 ((0x2CC - 0x260) / 4) +#define CM_ADC1CLKSEL ((0x464 - 0x260) / 4) +#define CM_PLLCLKDIVSEL ((0x52C - 0x260) / 4) +#define CM_I3C0FCLKSEL ((0x530 - 0x260) / 4) +#define CM_MICFILFCLKSEL ((0x548 - 0x260) / 4) +#define CM_FLEXIOCLKSEL ((0x560 - 0x260) / 4) +#define CM_FLEXCAN0CLKSEL ((0x5A0 - 0x260) / 4) +#define CM_FLEXCAN1CLKSEL ((0x5A8 - 0x260) / 4) +#define CM_EWM0CLKSEL ((0x5D4 - 0x260) / 4) +#define CM_WDT1CLKSEL ((0x5D8 - 0x260) / 4) +#define CM_OSTIMERCLKSEL ((0x5E0 - 0x260) / 4) +#define CM_CMP0FCLKSEL ((0x5F0 - 0x260) / 4) +#define CM_CMP0RRCLKSEL ((0x5F8 - 0x260) / 4) +#define CM_CMP1FCLKSEL ((0x600 - 0x260) / 4) +#define CM_CMP1RRCLKSEL ((0x608 - 0x260) / 4) +#define CM_UTICKCLKSEL ((0x878 - 0x260) / 4) +#define CM_SAI0CLKSEL ((0x880 - 0x260) / 4) +#define CM_SAI1CLKSEL ((0x884 - 0x260) / 4) +#define CM_I3C1FCLKSEL ((0xB30 - 0x260) / 4) + +#define CM_SCGRCCRSCSCLKSEL 0x3FEU + +/*! + * @brief The enumerator of clock attach Id. + */ +typedef enum _clock_attach_id +{ + kCLK_IN_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 1), /*!< Attach clk_in to MAIN_CLK. */ + kFRO12M_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 2), /*!< Attach FRO_12M to MAIN_CLK. */ + kFRO_HF_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 3), /*!< Attach FRO_HF to MAIN_CLK. */ + kXTAL32K2_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 4), /*!< Attach xtal32k[2] to MAIN_CLK. */ + kPLL0_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 5), /*!< Attach PLL0 to MAIN_CLK. */ + kPLL1_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 6), /*!< Attach PLL1 to MAIN_CLK. */ + kUSB_PLL_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 7), /*!< Attach USB PLL to MAIN_CLK. */ + kNONE_to_MAIN_CLK = MUX_A(CM_SCGRCCRSCSCLKSEL, 15), /*!< Attach NONE to MAIN_CLK. */ + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + kCLK_1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach Clk 1 MHz to SYSTICK0. */ + kLPOSC_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach LP Oscillator to SYSTICK0. */ + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + kCLK_1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach Clk 1 MHz to TRACE. */ + kLPOSC_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach LP Oscillator to TRACE. */ + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kCLK_1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach CLK_1M to CTIMER0. */ + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + kPLL1_CLK0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 2), /*!< Attach PLL1_clk0 to CTIMER0. */ + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + kFRO12M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO 12MHz to CTIMER0. */ + kSAI0_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach SAI0 MCLK IN to CTIMER0. */ + kLPOSC_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach LP Oscillator to CTIMER0. */ + kSAI1_MCLK_IN_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 8), /*!< Attach SAI1 MCLK IN to CTIMER0. */ + kSAI0_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 9), /*!< Attach SAI0 TX_BCLK to CTIMER0. */ + kSAI0_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 10), /*!< Attach SAI0 RX_BCLK to CTIMER0. */ + kSAI1_TX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 11), /*!< Attach SAI1 TX_BCLK to CTIMER0. */ + kSAI1_RX_BCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 12), /*!< Attach SAI1 RX_BCLK to CTIMER0. */ + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 15), /*!< Attach NONE to CTIMER0. */ + + kCLK_1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach CLK_1M to CTIMER1. */ + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + kPLL1_CLK0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 2), /*!< Attach PLL1_clk0 to CTIMER1. */ + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + kFRO12M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO 12MHz to CTIMER1. */ + kSAI0_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach SAI0 MCLK IN to CTIMER1. */ + kLPOSC_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach LP Oscillator to CTIMER1. */ + kSAI1_MCLK_IN_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 8), /*!< Attach SAI1 MCLK IN to CTIMER1. */ + kSAI0_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 9), /*!< Attach SAI0 TX_BCLK to CTIMER1. */ + kSAI0_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 10), /*!< Attach SAI0 RX_BCLK to CTIMER1. */ + kSAI1_TX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 11), /*!< Attach SAI1 TX_BCLK to CTIMER1. */ + kSAI1_RX_BCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 12), /*!< Attach SAI1 RX_BCLK to CTIMER1. */ + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 15), /*!< Attach NONE to CTIMER1. */ + + kCLK_1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach CLK_1M to CTIMER2. */ + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + kPLL1_CLK0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 2), /*!< Attach PLL1_clk0 to CTIMER2. */ + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + kFRO12M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO 12MHz to CTIMER2. */ + kSAI0_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach SAI0 MCLK IN to CTIMER2. */ + kLPOSC_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach LP Oscillator to CTIMER2. */ + kSAI1_MCLK_IN_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 8), /*!< Attach SAI1 MCLK IN to CTIMER2. */ + kSAI0_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 9), /*!< Attach SAI0 TX_BCLK to CTIMER2. */ + kSAI0_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 10), /*!< Attach SAI0 RX_BCLK to CTIMER2. */ + kSAI1_TX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 11), /*!< Attach SAI1 TX_BCLK to CTIMER2. */ + kSAI1_RX_BCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 12), /*!< Attach SAI1 RX_BCLK to CTIMER2. */ + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 15), /*!< Attach NONE to CTIMER2. */ + + kCLK_1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach CLK_1M to CTIMER3. */ + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + kPLL1_CLK0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 2), /*!< Attach PLL1_clk0 to CTIMER3. */ + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + kFRO12M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO 12MHz to CTIMER3. */ + kSAI0_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach SAI0 MCLK IN to CTIMER3. */ + kLPOSC_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach LP Oscillator to CTIMER3. */ + kSAI1_MCLK_IN_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 8), /*!< Attach SAI1 MCLK IN to CTIMER3. */ + kSAI0_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 9), /*!< Attach SAI0 TX_BCLK to CTIMER3. */ + kSAI0_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 10), /*!< Attach SAI0 RX_BCLK to CTIMER3. */ + kSAI1_TX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 11), /*!< Attach SAI1 TX_BCLK to CTIMER3. */ + kSAI1_RX_BCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 12), /*!< Attach SAI1 RX_BCLK to CTIMER3. */ + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 15), /*!< Attach NONE to CTIMER3. */ + + kCLK_1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach CLK_1M to CTIMER4. */ + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + kPLL1_CLK0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 2), /*!< Attach PLL1_clk0 to CTIMER4. */ + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + kFRO12M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO 12MHz to CTIMER4. */ + kSAI0_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach SAI0 MCLK IN to CTIMER4. */ + kLPOSC_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach LP Oscillator to CTIMER4. */ + kSAI1_MCLK_IN_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 8), /*!< Attach SAI1 MCLK IN to CTIMER4. */ + kSAI0_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 9), /*!< Attach SAI0 TX_BCLK to CTIMER4. */ + kSAI0_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 10), /*!< Attach SAI0 RX_BCLK to CTIMER4. */ + kSAI1_TX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 11), /*!< Attach SAI1 TX_BCLK to CTIMER4. */ + kSAI1_RX_BCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 12), /*!< Attach SAI1 RX_BCLK to CTIMER4. */ + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 15), /*!< Attach NONE to CTIMER4. */ + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ + kCLK_IN_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach Clk_in to CLKOUT. */ + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ + kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO 12 MHz to CLKOUT. */ + kPLL1_CLK0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1_clk0 to CLKOUT. */ + kLPOSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach LP Oscillator to CLKOUT. */ + kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach USB_PLL to CLKOUT. */ + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 15), /*!< Attach NONE to CLKOUT. */ + + kPLL0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 1), /*!< Attach PLL0 to ADC0. */ + kFRO_HF_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 2), /*!< Attach FRO_HF to ADC0. */ + kFRO12M_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 3), /*!< Attach FRO 12 MHz to ADC0. */ + kCLK_IN_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 4), /*!< Attach Clk_in to ADC0. */ + kPLL1_CLK0_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC0. */ + kUSB_PLL_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 6), /*!< Attach USB PLL to ADC0. */ + kNONE_to_ADC0 = MUX_A(CM_ADC0CLKSEL, 7), /*!< Attach NONE to ADC0. */ + + kPLL_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 1), /*!< Attach PLL_DIV to FLEXCOMM0. */ + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + kCLK_1M_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 4), /*!< Attach CLK_1MHz to FLEXCOMM0. */ + kUSB_PLL_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 5), /*!< Attach USB_PLL to FLEXCOMM0. */ + kLPOSC_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 6), /*!< Attach LP Oscillator to FLEXCOMM0. */ + kNONE_to_FLEXCOMM0 = MUX_A(CM_FCCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kPLL_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 1), /*!< Attach PLL_DIV to FLEXCOMM1. */ + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + kCLK_1M_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 4), /*!< Attach CLK_1MHz to FLEXCOMM1. */ + kUSB_PLL_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 5), /*!< Attach USB_PLL to FLEXCOMM1. */ + kLPOSC_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 6), /*!< Attach LP Oscillator to FLEXCOMM1. */ + kNONE_to_FLEXCOMM1 = MUX_A(CM_FCCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kPLL_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 1), /*!< Attach PLL_DIV to FLEXCOMM2. */ + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + kCLK_1M_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 4), /*!< Attach CLK_1MHz to FLEXCOMM2. */ + kUSB_PLL_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 5), /*!< Attach USB_PLL to FLEXCOMM2. */ + kLPOSC_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 6), /*!< Attach LP Oscillator to FLEXCOMM2. */ + kNONE_to_FLEXCOMM2 = MUX_A(CM_FCCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kPLL_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 1), /*!< Attach PLL_DIV to FLEXCOMM3. */ + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + kCLK_1M_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 4), /*!< Attach CLK_1MHz to FLEXCOMM3. */ + kUSB_PLL_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 5), /*!< Attach USB_PLL to FLEXCOMM3. */ + kLPOSC_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 6), /*!< Attach LP Oscillator to FLEXCOMM3. */ + kNONE_to_FLEXCOMM3 = MUX_A(CM_FCCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kPLL_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 1), /*!< Attach PLL_DIV to FLEXCOMM4. */ + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + kCLK_1M_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 4), /*!< Attach CLK_1MHz to FLEXCOMM4. */ + kUSB_PLL_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 5), /*!< Attach USB_PLL to FLEXCOMM4. */ + kLPOSC_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 6), /*!< Attach LP Oscillator to FLEXCOMM4. */ + kNONE_to_FLEXCOMM4 = MUX_A(CM_FCCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kPLL_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 1), /*!< Attach PLL_DIV to FLEXCOMM5. */ + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + kCLK_1M_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 4), /*!< Attach CLK_1MHz to FLEXCOMM5. */ + kUSB_PLL_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 5), /*!< Attach USB_PLL to FLEXCOMM5. */ + kLPOSC_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 6), /*!< Attach LP Oscillator to FLEXCOMM5. */ + kNONE_to_FLEXCOMM5 = MUX_A(CM_FCCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kPLL_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 1), /*!< Attach PLL_DIV to FLEXCOMM6. */ + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + kCLK_1M_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 4), /*!< Attach CLK_1MHz to FLEXCOMM6. */ + kUSB_PLL_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 5), /*!< Attach USB_PLL to FLEXCOMM6. */ + kLPOSC_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 6), /*!< Attach LP Oscillator to FLEXCOMM6. */ + kNONE_to_FLEXCOMM6 = MUX_A(CM_FCCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kPLL_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 1), /*!< Attach PLL_DIV to FLEXCOMM7. */ + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + kCLK_1M_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 4), /*!< Attach CLK_1MHz to FLEXCOMM7. */ + kUSB_PLL_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 5), /*!< Attach USB_PLL to FLEXCOMM7. */ + kLPOSC_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 6), /*!< Attach LP Oscillator to FLEXCOMM7. */ + kNONE_to_FLEXCOMM7 = MUX_A(CM_FCCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kPLL0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 1), /*!< Attach PLL0 to ADC1. */ + kFRO_HF_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 2), /*!< Attach FRO_HF to ADC1. */ + kFRO12M_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 3), /*!< Attach FRO12M to ADC1. */ + kCLK_IN_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 4), /*!< Attach clk_in to ADC1. */ + kPLL1_CLK0_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 5), /*!< Attach PLL1_clk0 to ADC1. */ + kUSB_PLL_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 6), /*!< Attach USB PLL to ADC1. */ + kNONE_to_ADC1 = MUX_A(CM_ADC1CLKSEL, 7), /*!< Attach NONE to ADC1. */ + + kPLL0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 0), /*!< Attach PLL0 to PLLCLKDIV. */ + kPLL1_CLK0_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach pll1_clk0 to PLLCLKDIV. */ + kNONE_to_PLLCLKDIV = MUX_A(CM_PLLCLKDIVSEL, 1), /*!< Attach NONE to PLLCLKDIV. */ + + kPLL0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLK. */ + kFRO_HF_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLK. */ + kCLK_1M_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLK. */ + kPLL1_CLK0_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLK. */ + kUSB_PLL_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLK. */ + kNONE_to_I3C0FCLK = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLK. */ + + kPLL0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKSTC. */ + kFRO_HF_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKSTC. */ + kCLK_1M_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKSTC. */ + kPLL1_CLK0_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKSTC. */ + kUSB_PLL_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKSTC. */ + kNONE_to_I3C0FCLKSTC = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKSTC. */ + + kPLL0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 1), /*!< Attach PLL0 to I3C0FCLKS. */ + kFRO_HF_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 3), /*!< Attach FRO_HF to I3C0FCLKS. */ + kCLK_1M_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 4), /*!< Attach CLK_1M to I3C0FCLKS. */ + kPLL1_CLK0_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C0FCLKS. */ + kUSB_PLL_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 6), /*!< Attach USB PLL to I3C0FCLKS. */ + kNONE_to_I3C0FCLKSlow = MUX_A(CM_I3C0FCLKSEL, 7), /*!< Attach NONE to I3C0FCLKS. */ + + kFRO12M_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 0), /*!< Attach FRO_12M to MICFILF. */ + kPLL0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 1), /*!< Attach PLL0 to MICFILF. */ + kCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 2), /*!< Attach Clk_in to MICFILF. */ + kFRO_HF_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 3), /*!< Attach FRO_HF to MICFILF. */ + kPLL1_CLK0_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 4), /*!< Attach PLL1_clk0 to MICFILF. */ + kSAI0_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 5), /*!< Attach SAI0_MCLK to MICFILF. */ + kUSB_PLL_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 6), /*!< Attach USB PLL to MICFILF. */ + kSAI1_MCLK_IN_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 8), /*!< Attach SAI1_MCLK to MICFILF. */ + kNONE_to_MICFILF = MUX_A(CM_MICFILFCLKSEL, 15), /*!< Attach NONE to MICFILF. */ + + kPLL0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 1), /*!< Attach PLL0 to FLEXIO. */ + kCLK_IN_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 2), /*!< Attach Clk_in to FLEXIO. */ + kFRO_HF_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 3), /*!< Attach FRO_HF to FLEXIO. */ + kFRO12M_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 4), /*!< Attach FRO_12M to FLEXIO. */ + kPLL1_CLK0_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 5), /*!< Attach pll1_clk0 to FLEXIO. */ + kUSB_PLL_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 6), /*!< Attach USB PLL to FLEXIO. */ + kNONE_to_FLEXIO = MUX_A(CM_FLEXIOCLKSEL, 7), /*!< Attach NONE to FLEXIO. */ + + kPLL0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN0. */ + kCLK_IN_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN0. */ + kFRO_HF_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN0. */ + kPLL1_CLK0_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN0. */ + kUSB_PLL_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN0. */ + kNONE_to_FLEXCAN0 = MUX_A(CM_FLEXCAN0CLKSEL, 7), /*!< Attach NONE to FLEXCAN0. */ + + kPLL0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 1), /*!< Attach PLL0 to FLEXCAN1. */ + kCLK_IN_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 2), /*!< Attach Clk_in to FLEXCAN1. */ + kFRO_HF_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 3), /*!< Attach FRO_HF to FLEXCAN1. */ + kPLL1_CLK0_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 5), /*!< Attach pll1_clk0 to FLEXCAN1. */ + kUSB_PLL_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 6), /*!< Attach USB PLL to FLEXCAN1. */ + kNONE_to_FLEXCAN1 = MUX_A(CM_FLEXCAN1CLKSEL, 7), /*!< Attach NONE to FLEXCAN1. */ + + kCLK_16K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 0), /*!< Attach clk_16k[2] to EWM0. */ + kXTAL32K2_to_EWM0 = MUX_A(CM_EWM0CLKSEL, 1), /*!< Attach xtal32k[2] to EWM0. */ + + kCLK_16K2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 0), /*!< Attach FRO16K clock 2 to WDT1. */ + kFRO_HF_DIV_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 1), /*!< Attach FRO_HF_DIV to WDT1. */ + kCLK_1M_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 2), /*!< Attach clk_1m to WDT1. */ + kCLK_1M_2_to_WDT1 = MUX_A(CM_WDT1CLKSEL, 3), /*!< Attach clk_1m to WDT1. */ + + kCLK_16K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 0), /*!< Attach clk_16k[2] to OSTIMER. */ + kXTAL32K2_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 1), /*!< Attach xtal32k[2] to OSTIMER. */ + kCLK_1M_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 2), /*!< Attach clk_1m to OSTIMER. */ + kNONE_to_OSTIMER = MUX_A(CM_OSTIMERCLKSEL, 3), /*!< Attach NONE to OSTIMER. */ + + kPLL0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 1), /*!< Attach PLL0 to CMP0F. */ + kFRO_HF_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 2), /*!< Attach FRO_HF to CMP0F. */ + kFRO12M_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 3), /*!< Attach FRO_12M to CMP0F. */ + kCLK_IN_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 4), /*!< Attach Clk_in to CMP0F. */ + kPLL1_CLK0_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0F. */ + kUSB_PLL_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 6), /*!< Attach USB PLL to CMP0F. */ + kNONE_to_CMP0F = MUX_A(CM_CMP0FCLKSEL, 7), /*!< Attach NONE to CMP0F. */ + + kPLL0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 1), /*!< Attach PLL0 to CMP0RR. */ + kFRO_HF_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 2), /*!< Attach FRO_HF to CMP0RR. */ + kFRO12M_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 3), /*!< Attach FRO_12M to CMP0RR. */ + kCLK_IN_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 4), /*!< Attach Clk_in to CMP0RR. */ + kPLL1_CLK0_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP0RR. */ + kUSB_PLL_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 6), /*!< Attach USB PLL to CMP0RR. */ + kNONE_to_CMP0RR = MUX_A(CM_CMP0RRCLKSEL, 7), /*!< Attach NONE to CMP0RR. */ + + kPLL0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 1), /*!< Attach PLL0 to CMP1F. */ + kFRO_HF_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 2), /*!< Attach FRO_HF to CMP1F. */ + kFRO12M_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 3), /*!< Attach FRO_12M to CMP1F. */ + kCLK_IN_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 4), /*!< Attach Clk_in to CMP1F. */ + kPLL1_CLK0_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1F. */ + kUSB_PLL_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 6), /*!< Attach USB PLL to CMP1F. */ + kNONE_to_CMP1F = MUX_A(CM_CMP1FCLKSEL, 7), /*!< Attach NONE to CMP1F. */ + + kPLL0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 1), /*!< Attach PLL0 to CMP1RR. */ + kFRO_HF_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 2), /*!< Attach FRO_HF to CMP1RR. */ + kFRO12M_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 3), /*!< Attach FRO_12M to CMP1RR. */ + kCLK_IN_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 4), /*!< Attach Clk_in to CMP1RR. */ + kPLL1_CLK0_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 5), /*!< Attach PLL1_clk0 to CMP1RR. */ + kUSB_PLL_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 6), /*!< Attach USB PLL to CMP1RR. */ + kNONE_to_CMP1RR = MUX_A(CM_CMP1RRCLKSEL, 7), /*!< Attach NONE to CMP1RR. */ + + kCLK_IN_to_UTICK = MUX_A(CM_UTICKCLKSEL, 0), /*!< Attach Clk_in to UTICK. */ + kXTAL32K2_to_UTICK = MUX_A(CM_UTICKCLKSEL, 1), /*!< Attach xtal32k[2] to UTICK. */ + kCLK_1M_to_UTICK = MUX_A(CM_UTICKCLKSEL, 2), /*!< Attach clk_1m to UTICK. */ + kNONE_to_UTICK = MUX_A(CM_UTICKCLKSEL, 3), /*!< Attach NONE to UTICK. */ + + kPLL0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 1), /*!< Attach PLL0 to SAI0. */ + kCLK_IN_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 2), /*!< Attach Clk_in to SAI0. */ + kFRO_HF_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 3), /*!< Attach FRO_HF to SAI0. */ + kPLL1_CLK0_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI0. */ + kUSB_PLL_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 6), /*!< Attach USB PLL to SAI0. */ + kNONE_to_SAI0 = MUX_A(CM_SAI0CLKSEL, 7), /*!< Attach NONE to SAI0. */ + + kPLL0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 1), /*!< Attach PLL0 to SAI1. */ + kCLK_IN_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 2), /*!< Attach Clk_in to SAI1. */ + kFRO_HF_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 3), /*!< Attach FRO_HF to SAI1. */ + kPLL1_CLK0_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 4), /*!< Attach PLL1_clk0 to SAI1. */ + kUSB_PLL_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 6), /*!< Attach USB PLL to SAI1. */ + kNONE_to_SAI1 = MUX_A(CM_SAI1CLKSEL, 7), /*!< Attach NONE to SAI1. */ + + kPLL0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLK. */ + kFRO_HF_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLK. */ + kCLK_1M_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLK. */ + kPLL1_CLK0_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLK. */ + kUSB_PLL_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLK. */ + kNONE_to_I3C1FCLK = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLK. */ + + kPLL0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKSTC. */ + kFRO_HF_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKSTC. */ + kCLK_1M_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKSTC. */ + kPLL1_CLK0_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKSTC. */ + kUSB_PLL_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKSTC. */ + kNONE_to_I3C1FCLKSTC = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKSTC. */ + + kPLL0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 1), /*!< Attach PLL0 to I3C1FCLKS. */ + kFRO_HF_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 3), /*!< Attach FRO_HF to I3C1FCLKS. */ + kCLK_1M_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 4), /*!< Attach CLK_1M to I3C1FCLKS. */ + kPLL1_CLK0_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 5), /*!< Attach PLL1_clk0 to I3C1FCLKS. */ + kUSB_PLL_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 6), /*!< Attach USB PLL to I3C1FCLKS. */ + kNONE_to_I3C1FCLKSlow = MUX_A(CM_I3C1FCLKSEL, 7), /*!< Attach NONE to I3C1FCLKS. */ + + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ + +} clock_attach_id_t; + +/*! @brief Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ + kCLOCK_DivTraceClk = ((0x308 - 0x300) / 4), /*!< Trace Clk Divider. */ + kCLOCK_DivSlowClk = ((0x378 - 0x300) / 4), /*!< SLOW CLK Divider. */ + kCLOCK_DivAhbClk = ((0x380 - 0x300) / 4), /*!< Ahb Clk Divider. */ + kCLOCK_DivClkOut = ((0x384 - 0x300) / 4), /*!< ClkOut Clk Divider. */ + kCLOCK_DivFrohfClk = ((0x388 - 0x300) / 4), /*!< Frohf Clk Divider. */ + kCLOCK_DivWdt0Clk = ((0x38C - 0x300) / 4), /*!< Wdt0 Clk Divider. */ + kCLOCK_DivAdc0Clk = ((0x394 - 0x300) / 4), /*!< Adc0 Clk Divider. */ + kCLOCK_DivPllClk = ((0x3C4 - 0x300) / 4), /*!< Pll Clk Divider. */ + kCLOCK_DivCtimer0Clk = ((0x3D0 - 0x300) / 4), /*!< Ctimer0 Clk Divider. */ + kCLOCK_DivCtimer1Clk = ((0x3D4 - 0x300) / 4), /*!< Ctimer1 Clk Divider. */ + kCLOCK_DivCtimer2Clk = ((0x3D8 - 0x300) / 4), /*!< Ctimer2 Clk Divider. */ + kCLOCK_DivCtimer3Clk = ((0x3DC - 0x300) / 4), /*!< Ctimer3 Clk Divider. */ + kCLOCK_DivCtimer4Clk = ((0x3E0 - 0x300) / 4), /*!< Ctimer4 Clk Divider. */ + kCLOCK_DivPLL1Clk0 = ((0x3E4 - 0x300) / 4), /*!< PLL1 Clk0 Divider. */ + kCLOCK_DivPLL1Clk1 = ((0x3E8 - 0x300) / 4), /*!< Pll1 Clk1 Divider. */ + kCLOCK_DivUtickClk = ((0x3F0 - 0x300) / 4), /*!< Utick Clk Divider. */ + kCLOCK_DivFrg = ((0x3F4 - 0x300) / 4), /*!< CLKOUT FRG Clk Divider. */ + kCLOCK_DivAdc1Clk = ((0x468 - 0x300) / 4), /*!< Adc1 Clk Divider. */ + kCLOCK_DivI3c0FClk = ((0x540 - 0x300) / 4), /*!< I3C0 FClk Divider. */ + kCLOCK_DivMicfilFClk = ((0x54C - 0x300) / 4), /*!< MICFILFCLK Divider. */ + kCLOCK_DivFlexioClk = ((0x564 - 0x300) / 4), /*!< Flexio Clk Divider. */ + kCLOCK_DivFlexcan0Clk = ((0x5A4 - 0x300) / 4), /*!< Flexcan0 Clk Divider. */ + kCLOCK_DivFlexcan1Clk = ((0x5AC - 0x300) / 4), /*!< Flexcan1 Clk Divider. */ + kCLOCK_DivWdt1Clk = ((0x5DC - 0x300) / 4), /*!< Wdt1 Clk Divider. */ + kCLOCK_DivCmp0FClk = ((0x5F4 - 0x300) / 4), /*!< Cmp0 FClk Divider. */ + kCLOCK_DivCmp0rrClk = ((0x5FC - 0x300) / 4), /*!< Cmp0rr Clk Divider. */ + kCLOCK_DivCmp1FClk = ((0x604 - 0x300) / 4), /*!< Cmp1 FClk Divider. */ + kCLOCK_DivCmp1rrClk = ((0x60C - 0x300) / 4), /*!< Cmp1rr Clk Divider. */ + kCLOCK_DivFlexcom0Clk = ((0x850 - 0x300) / 4), /*!< Flexcom0 Clk Divider. */ + kCLOCK_DivFlexcom1Clk = ((0x854 - 0x300) / 4), /*!< Flexcom1 Clk Divider. */ + kCLOCK_DivFlexcom2Clk = ((0x858 - 0x300) / 4), /*!< Flexcom2 Clk Divider. */ + kCLOCK_DivFlexcom3Clk = ((0x85C - 0x300) / 4), /*!< Flexcom3 Clk Divider. */ + kCLOCK_DivFlexcom4Clk = ((0x860 - 0x300) / 4), /*!< Flexcom4 Clk Divider. */ + kCLOCK_DivFlexcom5Clk = ((0x864 - 0x300) / 4), /*!< Flexcom5 Clk Divider. */ + kCLOCK_DivFlexcom6Clk = ((0x868 - 0x300) / 4), /*!< Flexcom6 Clk Divider. */ + kCLOCK_DivFlexcom7Clk = ((0x86C - 0x300) / 4), /*!< Flexcom7 Clk Divider. */ + kCLOCK_DivSai0Clk = ((0x888 - 0x300) / 4), /*!< Sai0 Clk Divider. */ + kCLOCK_DivSai1Clk = ((0x88C - 0x300) / 4), /*!< Sai1 Clk Divider. */ + kCLOCK_DivI3c1FClk = ((0xB40 - 0x300) / 4), /*!< I3C1 FClk Divider. */ +} clock_div_name_t; + +/*! @brief OSC32K clock gate */ +typedef enum _osc32k_clk_gate_id +{ + kCLOCK_Osc32kToVbat = 0x1, /*!< OSC32K[0] to VBAT domain. */ + kCLOCK_Osc32kToVsys = 0x2, /*!< OSC32K[1] to VSYS domain. */ + kCLOCK_Osc32kToWake = 0x4, /*!< OSC32K[2] to WAKE domain. */ + kCLOCK_Osc32kToMain = 0x8, /*!< OSC32K[3] to MAIN domain. */ + kCLOCK_Osc32kToAll = 0xF, /*!< OSC32K to VBAT,VSYS,WAKE,MAIN domain. */ +} osc32k_clk_gate_id_t; + +/*! @brief CLK16K clock gate */ +typedef enum _clk16k_clk_gate_id +{ + kCLOCK_Clk16KToVbat = 0x1, /*!< Clk16k[0] to VBAT domain. */ + kCLOCK_Clk16KToVsys = 0x2, /*!< Clk16k[1] to VSYS domain. */ + kCLOCK_Clk16KToWake = 0x4, /*!< Clk16k[2] to WAKE domain. */ + kCLOCK_Clk16KToMain = 0x8, /*!< Clk16k[3] to MAIN domain. */ + kCLOCK_Clk16KToAll = 0xF, /*!< Clk16k to VBAT,VSYS,WAKE,MAIN domain. */ +} clk16k_clk_gate_id_t; + +/*! @brief system clocks enable controls */ +typedef enum _clock_ctrl_enable +{ + kCLOCK_FRO1MHZ_CLK_ENA = + SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK, /*!< Enables FRO_1MHz clock for clock muxing in clock gen. */ + kCLOCK_CLKIN_ENA = SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK, /*!< Enables clk_in clock for MICD, EMVSIM0/1, CAN0/1, I3C0/1, + SAI0/1, clkout */ + kCLOCK_FRO_HF_ENA = + SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK, /*!< Enables FRO HF clock for the Frequency Measure module. */ + kCLOCK_FRO12MHZ_ENA = SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK, /*!< Enables the FRO_12MHz clock for the Flash, + LPTIMER0/1, and Frequency Measurement modules. */ + kCLOCK_FRO1MHZ_ENA = + SYSCON_CLOCK_CTRL_FRO1MHZ_ENA_MASK, /*!< Enables the FRO_1MHz clock for RTC module and for UTICK. */ + kCLOCK_CLKIN_ENA_FM_USBH_LPT = + SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK, /*!< Enables the clk_in clock for the Frequency Measurement, USB + HS and LPTIMER0/1 modules. */ +} clock_ctrl_enable_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*! + * @brief SCG status return codes. + */ +enum _scg_status +{ + kStatus_SCG_Busy = MAKE_STATUS(kStatusGroup_SCG, 1), /*!< Clock is busy. */ + kStatus_SCG_InvalidSrc = MAKE_STATUS(kStatusGroup_SCG, 2) /*!< Invalid source. */ +}; + +/*! + * @brief firc trim mode. + */ +typedef enum _firc_trim_mode +{ + kSCG_FircTrimNonUpdate = SCG_FIRCCSR_FIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref trim_config_t.*/ + + kSCG_FircTrimUpdate = SCG_FIRCCSR_FIRCTREN_MASK | SCG_FIRCCSR_FIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} firc_trim_mode_t; + +/*! + * @brief firc trim source. + */ +typedef enum _firc_trim_src +{ + kSCG_FircTrimSrcUsb0 = 0U, /*!< USB0 start of frame (1kHz). */ + kSCG_FircTrimSrcSysOsc = 2U, /*!< System OSC. */ + kSCG_FircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ +} firc_trim_src_t; + +/*! + * @brief firc trim configuration. + */ +typedef struct _firc_trim_config +{ + firc_trim_mode_t trimMode; /*!< Trim mode. */ + firc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + + uint8_t trimCoar; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t trimFine; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ +} firc_trim_config_t; + +/*! + * @brief sirc trim mode. + */ +typedef enum _sirc_trim_mode +{ + kSCG_SircTrimNonUpdate = SCG_SIRCCSR_SIRCTREN_MASK, + /*!< Trim enable but not enable trim value update. In this mode, the + trim value is fixed to the initialized value which is defined by + trimCoar and trimFine in configure structure \ref trim_config_t.*/ + + kSCG_SircTrimUpdate = SCG_SIRCCSR_SIRCTREN_MASK | SCG_SIRCCSR_SIRCTRUP_MASK + /*!< Trim enable and trim value update enable. In this mode, the trim + value is auto update. */ + +} sirc_trim_mode_t; + +/*! + * @brief sirc trim source. + */ +typedef enum _sirc_trim_src +{ + kSCG_SircTrimSrcSysOsc = 2U, /*!< System OSC. */ + kSCG_SircTrimSrcRtcOsc = 3U, /*!< RTC OSC (32.768 kHz). */ +} sirc_trim_src_t; + +/*! + * @brief sirc trim configuration. + */ +typedef struct _sirc_trim_config +{ + sirc_trim_mode_t trimMode; /*!< Trim mode. */ + sirc_trim_src_t trimSrc; /*!< Trim source. */ + uint16_t trimDiv; /*!< Divider of SOSC. */ + + uint8_t cltrim; /*!< Trim coarse value; Irrelevant if trimMode is kSCG_TrimUpdate. */ + uint8_t ccotrim; /*!< Trim fine value; Irrelevant if trimMode is kSCG_TrimUpdate. */ +} sirc_trim_config_t; + +/*! + * @brief SCG system OSC monitor mode. + */ +typedef enum _scg_sosc_monitor_mode +{ + kSCG_SysOscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_SysOscMonitorInt = SCG_SOSCCSR_SOSCCM_MASK, /*!< Interrupt when the SOSC error is detected. */ + kSCG_SysOscMonitorReset = + SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK /*!< Reset when the SOSC error is detected. */ +} scg_sosc_monitor_mode_t; + +/*! + * @brief SCG ROSC monitor mode. + */ +typedef enum _scg_rosc_monitor_mode +{ + kSCG_RoscMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_RoscMonitorInt = SCG_ROSCCSR_ROSCCM_MASK, /*!< Interrupt when the RTC OSC error is detected. */ + kSCG_RoscMonitorReset = + SCG_ROSCCSR_ROSCCM_MASK | SCG_ROSCCSR_ROSCCMRE_MASK /*!< Reset when the RTC OSC error is detected. */ +} scg_rosc_monitor_mode_t; + +/*! + * @brief SCG UPLL monitor mode. + */ +typedef enum _scg_upll_monitor_mode +{ + kSCG_UpllMonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_UpllMonitorInt = SCG_UPLLCSR_UPLLCM_MASK, /*!< Interrupt when the UPLL error is detected. */ + kSCG_UpllMonitorReset = + SCG_UPLLCSR_UPLLCM_MASK | SCG_UPLLCSR_UPLLCMRE_MASK /*!< Reset when the UPLL error is detected. */ +} scg_upll_monitor_mode_t; + +/*! + * @brief SCG PLL0 monitor mode. + */ +typedef enum _scg_pll0_monitor_mode +{ + kSCG_Pll0MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll0MonitorInt = SCG_APLLCSR_APLLCM_MASK, /*!< Interrupt when the PLL0 Clock error is detected. */ + kSCG_Pll0MonitorReset = + SCG_APLLCSR_APLLCM_MASK | SCG_APLLCSR_APLLCMRE_MASK /*!< Reset when the PLL0 Clock error is detected. */ +} scg_pll0_monitor_mode_t; + +/*! + * @brief SCG PLL1 monitor mode. + */ +typedef enum _scg_pll1_monitor_mode +{ + kSCG_Pll1MonitorDisable = 0U, /*!< Monitor disabled. */ + kSCG_Pll1MonitorInt = SCG_SPLLCSR_SPLLCM_MASK, /*!< Interrupt when the PLL1 Clock error is detected. */ + kSCG_Pll1MonitorReset = + SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK /*!< Reset when the PLL1 Clock error is detected. */ +} scg_pll1_monitor_mode_t; + +/*! + * @brief The enumerator of internal capacitance of OSC's XTAL pin. + */ +typedef enum _vbat_osc_xtal_cap +{ + kVBAT_OscXtal0pFCap = 0x0U, /*!< The internal capacitance for XTAL pin is 0pF. */ + kVBAT_OscXtal2pFCap = 0x1U, /*!< The internal capacitance for XTAL pin is 2pF. */ + kVBAT_OscXtal4pFCap = 0x2U, /*!< The internal capacitance for XTAL pin is 4pF. */ + kVBAT_OscXtal6pFCap = 0x3U, /*!< The internal capacitance for XTAL pin is 6pF. */ + kVBAT_OscXtal8pFCap = 0x4U, /*!< The internal capacitance for XTAL pin is 8pF. */ + kVBAT_OscXtal10pFCap = 0x5U, /*!< The internal capacitance for XTAL pin is 10pF. */ + kVBAT_OscXtal12pFCap = 0x6U, /*!< The internal capacitance for XTAL pin is 12pF. */ + kVBAT_OscXtal14pFCap = 0x7U, /*!< The internal capacitance for XTAL pin is 14pF. */ + kVBAT_OscXtal16pFCap = 0x8U, /*!< The internal capacitance for XTAL pin is 16pF. */ + kVBAT_OscXtal18pFCap = 0x9U, /*!< The internal capacitance for XTAL pin is 18pF. */ + kVBAT_OscXtal20pFCap = 0xAU, /*!< The internal capacitance for XTAL pin is 20pF. */ + kVBAT_OscXtal22pFCap = 0xBU, /*!< The internal capacitance for XTAL pin is 22pF. */ + kVBAT_OscXtal24pFCap = 0xCU, /*!< The internal capacitance for XTAL pin is 24pF. */ + kVBAT_OscXtal26pFCap = 0xDU, /*!< The internal capacitance for XTAL pin is 26pF. */ + kVBAT_OscXtal28pFCap = 0xEU, /*!< The internal capacitance for XTAL pin is 28pF. */ + kVBAT_OscXtal30pFCap = 0xFU, /*!< The internal capacitance for XTAL pin is 30pF. */ +} vbat_osc_xtal_cap_t; + +/*! + * @brief The enumerator of internal capacitance of OSC's EXTAL pin. + */ +typedef enum _vbat_osc_extal_cap +{ + kVBAT_OscExtal0pFCap = 0x0U, /*!< The internal capacitance for EXTAL pin is 0pF. */ + kVBAT_OscExtal2pFCap = 0x1U, /*!< The internal capacitance for EXTAL pin is 2pF. */ + kVBAT_OscExtal4pFCap = 0x2U, /*!< The internal capacitance for EXTAL pin is 4pF. */ + kVBAT_OscExtal6pFCap = 0x3U, /*!< The internal capacitance for EXTAL pin is 6pF. */ + kVBAT_OscExtal8pFCap = 0x4U, /*!< The internal capacitance for EXTAL pin is 8pF. */ + kVBAT_OscExtal10pFCap = 0x5U, /*!< The internal capacitance for EXTAL pin is 10pF. */ + kVBAT_OscExtal12pFCap = 0x6U, /*!< The internal capacitance for EXTAL pin is 12pF. */ + kVBAT_OscExtal14pFCap = 0x7U, /*!< The internal capacitance for EXTAL pin is 14pF. */ + kVBAT_OscExtal16pFCap = 0x8U, /*!< The internal capacitance for EXTAL pin is 16pF. */ + kVBAT_OscExtal18pFCap = 0x9U, /*!< The internal capacitance for EXTAL pin is 18pF. */ + kVBAT_OscExtal20pFCap = 0xAU, /*!< The internal capacitance for EXTAL pin is 20pF. */ + kVBAT_OscExtal22pFCap = 0xBU, /*!< The internal capacitance for EXTAL pin is 22pF. */ + kVBAT_OscExtal24pFCap = 0xCU, /*!< The internal capacitance for EXTAL pin is 24pF. */ + kVBAT_OscExtal26pFCap = 0xDU, /*!< The internal capacitance for EXTAL pin is 26pF. */ + kVBAT_OscExtal28pFCap = 0xEU, /*!< The internal capacitance for EXTAL pin is 28pF. */ + kVBAT_OscExtal30pFCap = 0xFU, /*!< The internal capacitance for EXTAL pin is 30pF. */ +} vbat_osc_extal_cap_t; + +/*! + * @brief The enumerator of osc amplifier gain fine adjustment. + * Changes the oscillator amplitude by modifying the automatic gain control (AGC). + */ +typedef enum _vbat_osc_fine_adjustment_value +{ + kVBAT_OscCoarseAdjustment05 = 0U, + kVBAT_OscCoarseAdjustment10 = 1U, + kVBAT_OscCoarseAdjustment18 = 2U, + kVBAT_OscCoarseAdjustment33 = 3U, +} vbat_osc_coarse_adjustment_value_t; + +/*! + * @brief The structure of oscillator configuration. + */ +typedef struct _vbat_osc_config +{ + bool enableInternalCapBank; /*!< enable/disable the internal capacitance bank. */ + + bool enableCrystalOscillatorBypass; /*!< enable/disable the crystal oscillator bypass. */ + + vbat_osc_xtal_cap_t xtalCap; /*!< The internal capacitance for the OSC XTAL pin from the capacitor bank, + only useful when the internal capacitance bank is enabled. */ + vbat_osc_extal_cap_t extalCap; /*!< The internal capacitance for the OSC EXTAL pin from the capacitor bank, only + useful when the internal capacitance bank is enabled. */ + vbat_osc_coarse_adjustment_value_t + coarseAdjustment; /*!< 32kHz crystal oscillator amplifier coarse adjustment value. */ +} vbat_osc_config_t; + +/*! + * @brief The active run mode (voltage level). + */ +typedef enum _run_mode +{ + kMD_Mode, /*!< Midvoltage (1.0 V). */ + kSD_Mode, /*!< Normal voltage (1.1 V). */ + kOD_Mode, /*!< Overdrive voltage (1.2 V). */ +} run_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** + * @brief Enable the clock for specific IP. + * @param clk : Clock to be enabled. + * @return Nothing + */ +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (clk == kCLOCK_None) + return; + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x40U; + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL |= (1UL << bit); + SYSCON->AHBCLKCTRLSET[3] = 0x80U; + } + else + { + SYSCON->AHBCLKCTRLSET[index] = (1UL << bit); + } +} + +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + uint32_t bit = CLK_GATE_ABSTRACT_BITS_SHIFT(clk); + + if (clk == kCLOCK_None) + return; + + if (index == (uint32_t)REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM0SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x20U; + } + } + else if (index == (uint32_t)REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL &= ~(1UL << bit); + if (0U == (SYSCON->PWM1SUBCTL & 0xFU)) + { + SYSCON->AHBCLKCTRLCLR[3] = 0x40U; + } + } + else + { + SYSCON->AHBCLKCTRLCLR[index] = (1UL << bit); + } +} + +/** + * @brief Initialize the Core clock to given frequency (48 or 144 MHz). + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency (must be one of CLK_FRO_44MHZ or CLK_FRO_144MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq); + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq); + +/** + * @brief Initialize the XTAL32/EXTAL32 input clock to given frequency. + * @param id : OSC 32 kHz output clock to specified modules, it should use osc32k_clk_gate_id_t value + * @return returns success or fail status. + */ +status_t CLOCK_SetupOsc32KClocking(uint32_t id); + +/** + * @brief Initialize the FRO16K input clock to given frequency. + * @param id : FRO 16 kHz output clock to specified modules, it should use clk16k_clk_gate_id_t value + * @return returns success or fail status. + */ +status_t CLOCK_SetupClk16KClocking(uint32_t id); + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config); + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config); + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode); + +/*! + * @brief Sets the ROSC monitor mode. + * + * This function sets the ROSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetRoscMonitorMode(scg_rosc_monitor_mode_t mode); + +/*! + * @brief Sets the UPLL monitor mode. + * + * This function sets the UPLL monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetUpllMonitorMode(scg_upll_monitor_mode_t mode); + +/*! + * @brief Sets the PLL0 monitor mode. + * + * This function sets the PLL0 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll0MonitorMode(scg_pll0_monitor_mode_t mode); + +/*! + * @brief Sets the PLL1 monitor mode. + * + * This function sets the PLL1 monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode); + +/*! + * @brief Config 32k Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param config The pointer to the structure \ref vbat_osc_config_t. + */ +void VBAT_SetOscConfig(VBAT_Type *base, const vbat_osc_config_t *config); + +/*! + * @brief Set the additional number of wait-states added to account for the ratio of system clock period to flash access + * time during full speed power mode. + * @param system_freq_hz : Input frequency + * @param mode : Active run mode (voltage level). + * @return success or fail status + */ +status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode); + +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); + +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); + +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value); + +/** + * @brief Get peripheral clock dividers. + * @param div_name : Clock divider name + * @return peripheral clock dividers + */ +uint32_t CLOCK_GetClkDiv(clock_div_name_t div_name); + +/** + * @brief Halt peripheral clock dividers. + * @param div_name : Clock divider name + * @return Nothing + */ +void CLOCK_HaltClkDiv(clock_div_name_t div_name); + +/** + * @brief system clocks enable controls. + * @param mask : system clocks enable value, it should use clock_ctrl_enable_t value + * @return Nothing + */ +void CLOCK_SetupClockCtrl(uint32_t mask); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Frequency of core + * @return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); + +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPFlexComm Clock + * @return Frequency of LPFlexComm Clock + */ +uint32_t CLOCK_GetLPFlexCommClkFreq(uint32_t id); + +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll0OutFreq(void); +/*! @brief Return Frequency of USB PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPll1OutFreq(void); + +/*! @brief Return Frequency of PLLCLKDIV + * @return Frequency of PLLCLKDIV Clock + */ +uint32_t CLOCK_GetPllClkDivFreq(void); + +/*! @brief Return Frequency of I3C function Clock + * @return Frequency of I3C function Clock + */ +uint32_t CLOCK_GetI3cClkFreq(uint32_t id); + +/*! @brief Return Frequency of MICFIL Clock + * @return Frequency of MICFIL. + */ +uint32_t CLOCK_GetMicfilClkFreq(void); + +/*! @brief Return Frequency of FLEXIO + * @return Frequency of FLEXIO Clock + */ +uint32_t CLOCK_GetFlexioClkFreq(void); + +/*! @brief Return Frequency of FLEXCAN + * @return Frequency of FLEXCAN Clock + */ +uint32_t CLOCK_GetFlexcanClkFreq(uint32_t id); + +/*! @brief Return Frequency of EWM0 Clock + * @return Frequency of EWM0. + */ +uint32_t CLOCK_GetEwm0ClkFreq(void); + +/*! @brief Return Frequency of Watchdog + * @return Frequency of Watchdog + */ +uint32_t CLOCK_GetWdtClkFreq(uint32_t id); + +/*! @brief Return Frequency of OSTIMER + * @return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void); + +/*! @brief Return Frequency of CMP Function Clock + * @return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id); + +/*! @brief Return Frequency of CMP Round Robin Clock + * @return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id); + +/*! @brief Return Frequency of UTICK Clock + * @return Frequency of UTICK Clock. + */ +uint32_t CLOCK_GetUtickClkFreq(void); + +/*! @brief Return Frequency of SAI Clock + * @return Frequency of SAI Clock. + */ +uint32_t CLOCK_GetSaiClkFreq(uint32_t id); + +/** + * @brief Initialize the SAI MCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiMclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Initialize the SAI TX BCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiTxBclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Initialize the SAI RX BCLK to given frequency. + * @param iFreq : Desired frequency + * @return Nothing + */ +void CLOCK_SetupSaiRxBclk(uint32_t id, uint32_t iFreq); + +/** + * @brief Return Frequency of SAI MCLK + * @return Frequency of SAI MCLK + */ +uint32_t CLOCK_GetSaiMclkFreq(uint32_t id); + +/** + * @brief Return Frequency of SAI TX BCLK + * @return Frequency of SAI TX BCLK + */ +uint32_t CLOCK_GetSaiTxBclkFreq(uint32_t id); + +/** + * @brief Return Frequency of SAI RX BCLK + * @return Frequency of SAI RX BCLK + */ +uint32_t CLOCK_GetSaiRxBclkFreq(uint32_t id); + +/*! @brief Return PLL0 input clock rate + * @return PLL0 input clock rate + */ +uint32_t CLOCK_GetPLL0InClockRate(void); + +/*! @brief Return PLL1 input clock rate + * @return PLL1 input clock rate + */ +uint32_t CLOCK_GetPLL1InClockRate(void); + +/*! @brief Gets the external UPLL frequency. + * @return The frequency of the external UPLL. + */ +uint32_t CLOCK_GetExtUpllFreq(void); + +/*! @brief Sets the external UPLL frequency. + * @param The frequency of external UPLL. + */ +void CLOCK_SetExtUpllFreq(uint32_t freq); + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL0Locked(void) +{ + return (bool)((SCG0->APLLCSR & SCG_APLLCSR_APLL_LOCK_MASK) != 0UL); +} + +/*! @brief Check if PLL1 is locked or not + * @return true if the PLL1 is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsPLL1Locked(void) +{ + return (bool)((SCG0->SPLLCSR & SCG_SPLLCSR_SPLL_LOCK_MASK) != 0UL); +} + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) +/*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ + +/*! + * @brief PLL clock source. + */ +typedef enum _pll_clk_src +{ + kPll_ClkSrcSysOsc = (0 << 25), /*!< System OSC. */ + kPll_ClkSrcFirc = (1 << 25), /*!< Fast IRC. */ + kPll_ClkSrcRosc = (2 << 25), /*!< RTC OSC. */ +} pll_clk_src_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 2), /*!< Nss = 512 (fm ~= 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 2), /*!< Nss ~= 384 (fm ~= 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 2), /*!< Nss = 256 (fm ~= 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 2), /*!< Nss = 128 (fm ~= 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 2), /*!< Nss = 64 (fm ~= 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 2), /*!< Nss = 32 (fm ~= 62.5 - 125 kHz) */ + kSS_MF_24 = (6 << 2), /*!< Nss ~= 24 (fm ~= 83.3 - 166.6 kHz) */ + kSS_MF_16 = (7 << 2) /*!< Nss = 16 (fm ~= 125 - 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the PLL0SSCG1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 5), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 5), /*!< k ~= 1 */ + kSS_MR_K1_5 = (2 << 5), /*!< k ~= 1.5 */ + kSS_MR_K2 = (3 << 5), /*!< k ~= 2 */ + kSS_MR_K3 = (4 << 5), /*!< k ~= 3 */ + kSS_MR_K4 = (5 << 5), /*!< k ~= 4 */ + kSS_MR_K6 = (6 << 5), /*!< k ~= 6 */ + kSS_MR_K8 = (7 << 5) /*!< k ~= 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the PLL0SSCG1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 8), /*!< no compensation */ + kSS_MC_RECC = (2 << 8), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 8), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputSource; /*!< PLL input source */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag + */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL0 setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t pllctrl; /*!< PLL Control register APLLCTRL */ + uint32_t pllndiv; /*!< PLL N Divider register APLLNDIV */ + uint32_t pllpdiv; /*!< PLL P Divider register APLLPDIV */ + uint32_t pllmdiv; /*!< PLL M Divider register APLLMDIV */ + uint32_t pllsscg[2]; /*!< PLL Spread Spectrum Control registers APLLSSCG*/ + uint32_t pllRate; /*!< Acutal PLL rate */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_OutputError = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL output rate error */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested output rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 8) /*!< Requested CCO rate isn't possible */ +} pll_error_t; + +/*! @brief Return PLL0 output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate the setup structure will generate + */ +uint32_t CLOCK_GetPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup); + +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing + */ +void CLOCK_EnableOstimer32kClock(void); + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsPhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhsPhyPllClock(void); + +/*! brief Enable USB HS clock. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhsClock(void); + +/** + * @brief FIRC Auto Trim With SOF. + * @return returns success or fail status. + */ +status_t CLOCK_FIRCAutoTrimWithSOF(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cmc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cmc.c new file mode 100644 index 0000000000..f2b7e064ab --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cmc.c @@ -0,0 +1,315 @@ +/* + * Copyright 2022 ~ 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_cmc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_cmc" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +#define CMC_SRAMDIS_RESERVED_MASK \ + (~(kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 | kCMC_RAMD1 | \ + kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 | kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | \ + kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ | kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI)) + +#define CMC_SRAMRET_RESERVED_MASK (CMC_SRAMDIS_RESERVED_MASK) +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t g_savedPrimask; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Sets clock mode. + * + * This function configs the amount of clock gating when the core asserts + * Sleeping due to WFI, WFE or SLEEPONEXIT. + * + * param base CMC peripheral base address. + * param mode System clock mode. + */ +void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode) +{ + uint32_t reg; + + reg = base->CKCTRL; + reg &= ~CMC_CKCTRL_CKMODE_MASK; + reg |= CMC_CKCTRL_CKMODE((mode)); + base->CKCTRL = reg; +} + +/*! + * brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes. This should be done before setting the lowPower mode + * for each power doamin. + * + * The allowed lowpower modes are passed as bit map. For example, to allow + * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). + * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes). + * + * param base CMC peripheral base address. + * param allowedModes Bitmaps of the allowed power modes. + */ +void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes) +{ + uint32_t reg; + + reg = base->PMPROT; + reg &= ~0xFUL; + reg |= allowedModes; + + base->PMPROT = reg; +} + +/*! + * brief Configure reset pin. + * + * This function configures reset pin. When enabled, the low power filter is enabled in both + * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers + * are enabled, they operate in series. + * + * param base CMC peripheral base address. + * param config Pointer to the reset pin config structure. + */ +void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = base->RPC; + + if (config->lowpowerFilterEnable) + { + reg |= CMC_RPC_LPFEN_MASK; + } + else + { + reg &= ~CMC_RPC_LPFEN_MASK; + } + if (config->resetFilterEnable) + { + reg |= (CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG(config->resetFilterWidth)); + } + else + { + reg &= ~(CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG_MASK); + } + base->RPC = reg; +} + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * brief Power off the selected system SRAM always. + * + * This function powers off the selected system SRAM always. The SRAM arrays should + * not be accessed while they are shut down. SRAM array contents are not retained + * if they are powered off. + * + * param base CMC peripheral base address. + * param mask Bitmap of the SRAM arrays to be powered off all modes. + */ +void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask) +{ + uint32_t reg = base->SRAMDIS[0]; + + reg &= ~(CMC_SRAMDIS_DIS_MASK | CMC_SRAMDIS_RESERVED_MASK); + reg |= CMC_SRAMDIS_DIS(mask); + base->SRAMDIS[0] = reg; +} + +/*! + * brief Power off the selected system SRAm during low power mode only. + * + * This function powers off the selected system SRAM only during low power mode. + * SRAM array contents are not retained if they are power off. + * + * param base CMC peripheral base address. + * param mask Bitmap of the SRAM arrays to be power off during low power mode only. + */ +void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) +{ + uint32_t reg = base->SRAMRET[0]; + + reg &= ~(CMC_SRAMRET_RET_MASK | CMC_SRAMRET_RESERVED_MASK); + reg |= CMC_SRAMRET_RET(mask); + base->SRAMRET[0] = reg; +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * param base CMC peripheral base address. + * param doze true: Flash is disabled while core is sleeping + * false: No effect. + * param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable) +{ + uint32_t reg = 0UL; + + reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) | + (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)); + base->FLASHCR = reg; +} +#else +/*! + * brief Configs the low power mode of the on-chip flash memory. + * + * This function config the low power mode of the on-chip flash memory. + * + * param base CMC peripheral base address. + * param wake + * true - Flash will exit low power state during the flash memory accesses. + * false - No effect. + * param doze + * true - Flash is disabled while core is sleeping + * false - No effect. + * param disable + * true - Flash memory is placed in low power state. + * false - No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable) +{ + uint32_t reg = 0UL; + + reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) | + (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)) | + (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U)); + base->FLASHCR = reg; +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ + +/*! + * brief Prepares to enter stop modes. + * + * This function should be called before entering low power modes. + * + */ +void CMC_PreEnterLowPowerMode(void) +{ + g_savedPrimask = DisableGlobalIRQ(); + __ISB(); +} + +/*! + * brief Recovers after wake up from stop modes. + * + * This function should be called after waking up from low power modes. + * This function should be used with CMC_PreEnterLowPowerMode() + * + */ +void CMC_PostExitLowPowerMode(void) +{ + EnableGlobalIRQ(g_savedPrimask); + __ISB(); +} + +/*! + * brief Configs the entry into the same low power mode for each power domains. + * + * This function provides the feature to entry into the same low power mode for each power + * domains. Before invoking this function, please ensure the selected power mode have been allowed. + * + * param base CMC peripheral base address. + * param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details. + * + */ +void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + /* Note: unlock the CKCTRL register if this API will be reinvoked later. */ + CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode); + CMC_SetGlobalPowerMode(base, lowPowerMode); + /* Before executing WFI instruction read back the last register to + * ensure all registers writes have completed. */ + (void)base->GPMCTRL; + /* Set the core into DeepSleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); +} + +/*! + * brief Configs the entry into different low power modes for each of the power domains. + * + * This function provides the feature to entry into different low power modes for + * each power domains. Before invoking this function please ensure the selected + * modes are allowed. + * + * param base CMC peripheral base address. + * param base config Pointer to the cmc_power_domain_config_t structure. + */ +void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config) +{ + assert(config != NULL); + +#if (CMC_PMCTRL_COUNT > 1U) + /* The WAKE domain must never be configured to a lower power mode compared with main power mode. */ + assert(config->wake_domain <= config->main_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode) + { + /* In This case the power domain doesn't need to be placed in low power state. */ + /* Note: unlock the register if this API will be reinvoked later. */ + CMC_SetClockMode(base, config->clock_mode); + + CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode); +#if (CMC_PMCTRL_COUNT > 1U) + CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + /* Before executing WFI instruction read back the last register to + * ensure all registers writes have completed. */ + (void)base->CKCTRL; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); + } + else + { + /* Note: unlock the register if this API will be reinvoked later. */ + CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode); + CMC_SetMAINPowerMode(base, config->main_domain); +#if (CMC_PMCTRL_COUNT > 1U) + CMC_SetWAKEPowerMode(base, config->wake_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + /* Before execute WFI instruction read back the last register to + * ensure all registers writes have completed. */ +#if (CMC_PMCTRL_COUNT > 1U) + if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain)) + { +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); +#if (CMC_PMCTRL_COUNT > 1U) + } +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cmc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cmc.h new file mode 100644 index 0000000000..979c5dfa0a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_cmc.h @@ -0,0 +1,911 @@ +/* + * Copyright 2022 ~ 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CMC_H_ +#define FSL_CMC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_cmc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief CMC driver version 2.2.0. */ +#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/* @} */ + +/*! + * @brief CMC power mode Protection enumeration. + */ +enum _cmc_power_mode_protection +{ + kCMC_AllowDeepSleepMode = 0x1UL, /*!< Allow Deep Sleep mode. */ + kCMC_AllowPowerDownMode = 0x2UL, /*!< Allow Power Down mode. */ + kCMC_AllowDeepPowerDownMode = 0x8UL, /*!< Allow Deep Power Down mode. */ + kCMC_AllowAllLowPowerModes = 0xFUL, /*!< Allow Deep Sleep, Power Down, Deep Power Down modes. */ +}; + +/*! + * @brief Wake up sources from the previous low power mode entry. + * + * @note #kCMC_WakeupFromUsbFs, #kCMC_WakeupFromITRC, #kCMC_WakeupFromCpu1 are not supported in MCXA family. + */ +enum _cmc_wakeup_sources +{ + kCMC_WakeupFromResetInterruptOrPowerDown = + CMC_CKSTAT_WAKEUP(1U << 0U), /*!< Wakeup source is reset interrupt, or wake up from Deep Power Down. */ + kCMC_WakeupFromDebugReuqest = CMC_CKSTAT_WAKEUP(1U << 1U), /*!< Wakeup source is debug request. */ + kCMC_WakeupFromInterrupt = CMC_CKSTAT_WAKEUP(1U << 2U), /*!< Wakeup source is interrupt. */ + kCMC_WakeupFromDMAWakeup = CMC_CKSTAT_WAKEUP(1U << 3U), /*!< Wakeup source is DMA Wakeup. */ + kCMC_WakeupFromWUURequest = CMC_CKSTAT_WAKEUP(1U << 4U), /*!< Wakeup source is WUU request. */ + kCMC_WakeupFromUsbFs = CMC_CKSTAT_WAKEUP(1U << 5U), /*!< Wakeup source is USBFS(USB0). */ + kCMC_WakeupFromITRC = CMC_CKSTAT_WAKEUP(1U << 6U), /*!< Wakeup source is ITRC. */ + kCMC_WakeupFromCpu1 = CMC_CKSTAT_WAKEUP(1U << 7U), /*!< Wakeup source is CPU1. */ +}; + +/*! + * @brief System Reset Interrupt enable enumeration. + */ +enum _cmc_system_reset_interrupt_enable +{ + kCMC_PinResetInterruptEnable = CMC_SRIE_PIN_MASK, /*!< Pin Reset interrupt enable. */ + kCMC_DAPResetInterruptEnable = CMC_SRIE_DAP_MASK, /*!< DAP Reset interrupt enable. */ + kCMC_LowPowerAcknowledgeTimeoutResetInterruptEnable = CMC_SRIE_LPACK_MASK, /*!< Low Power Acknowledge Timeout + Reset interrupt enable. */ + kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK, /*!< Windowed Watchdog 0 reset + interrupt enable. */ + kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */ + kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */ +#if defined(CMC_SRIE_CPU1_MASK) + kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */ +#endif /* CMC_SRIE_CPU1_MASK */ +#if defined(CMC_SRIE_VBAT_MASK) + kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */ +#endif /* CMC_SRIE_VBAT_MASK */ +#if defined(CMC_SRIE_WWDT1_MASK) + kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK, /*!< Windowed Watchdog 1 reset + interrupt enable. */ +#endif /* CMC_SRIE_WWDT1_MASK */ + kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */ +#if defined(CMC_SRIE_CDOG1_MASK) + kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */ +#endif /* CMC_SRIE_CDOG1_MASK */ +}; + +/*! + * @brief CMC System Reset Interrupt Status flag. + */ +enum _cmc_system_reset_interrupt_flag +{ + kCMC_PinResetInterruptFlag = CMC_SRIF_PIN_MASK, /*!< Pin Reset interrupt flag. */ + kCMC_DAPResetInterruptFlag = CMC_SRIF_DAP_MASK, /*!< DAP Reset interrupt flag. */ + kCMC_LowPowerAcknowledgeTimeoutResetFlag = CMC_SRIF_LPACK_MASK, /*!< Low Power Acknowledge + Timeout Reset interrupt flag. */ + kCMC_WindowedWatchdog0ResetInterruptFlag = CMC_SRIF_WWDT0_MASK, /*!< Windowned Watchdog 0 Reset interrupt flag. */ + kCMC_SoftwareResetInterruptFlag = CMC_SRIF_SW_MASK, /*!< Software Reset interrupt flag. */ + kCMC_LockupResetInterruptFlag = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */ +#if defined(CMC_SRIF_CPU1_MASK) + kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */ +#endif /* CMC_SRIF_CPU1_MASK */ +#if defined(CMC_SRIF_VBAT_MASK) + kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */ +#endif /* CMC_SRIF_VBAT_MASK */ +#if defined(CMC_SRIF_WWDT1_MASK) + kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK, /*!< Windowned Watchdog 1 Reset interrupt flag. */ +#endif /* CMC_SRIF_WWDT1_MASK */ + kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */ +#if defined(CMC_SRIF_CDOG1_MASK) + kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */ +#endif /* CMC_SRIF_CDOG1_MASK */ +}; + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * @brief CMC System SRAM arrays low power mode enable enumeration. + */ +enum _cmc_system_sram_arrays +{ + kCMC_RAMX0 = 1UL << 0UL, /*!< Used to control RAMX0. */ + kCMC_RAMX1 = 1UL << 1UL, /*!< Used to control RAMX1. */ + kCMC_RAMX2 = 1UL << 2UL, /*!< Used to control RAMX2. */ + kCMC_RAMB = 1UL << 3UL, /*!< Used to control RAMB. */ + kCMC_RAMC0 = 1UL << 4UL, /*!< Used to control RAMC0. */ + kCMC_RAMC1 = 1UL << 5UL, /*!< Used to control RAMC1. */ + kCMC_RAMD0 = 1UL << 6UL, /*!< Used to control RAMD0. */ + kCMC_RAMD1 = 1UL << 7UL, /*!< Used to control RAMD1. */ + kCMC_RAME0 = 1UL << 8UL, /*!< Used to control RAME0. */ + kCMC_RAME1 = 1UL << 9UL, /*!< Used to control RAME1. */ + kCMC_RAMF0 = 1UL << 10UL, /*!< Used to control RAMF0. */ + kCMC_RAMF1 = 1UL << 11UL, /*!< Used to control RAMF1. */ + kCMC_RAMG0_RAMG1 = 1UL << 12UL, /*!< Used to control RAMG0 and RAMG1. */ + kCMC_RAMG2_RAMG3 = 1UL << 13UL, /*!< Used to control RAMG2 and RAMG3. */ + kCMC_RAMH0_RAMH1 = 1UL << 14UL, /*!< Used to control RAMH0 and RAMH1. */ + kCMC_LPCAC = 1UL << 24UL, /*!< Used to control LPCAC. */ + kCMC_DMA0_DMA1_PKC = 1UL << 25UL, /*!< Used to control DMA0, DMA1 and PKC. */ + kCMC_USB0 = 1UL << 26UL, /*!< Used to control USB0. */ + kCMC_PQ = 1UL << 27UL, /*!< Used to control PQ. */ + kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */ + kCMC_FlexSPI = 1UL << 29UL, /*!< Used to control FlexSPI. */ +}; +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +/*! + * @brief System reset sources enumeration. + */ +enum _cmc_system_reset_sources +{ + kCMC_WakeUpReset = CMC_SRS_WAKEUP_MASK, /*!< The reset caused by a wakeup from Power Down or + Deep Power Down mode. */ + kCMC_PORReset = CMC_SRS_POR_MASK, /*!< The reset caused by power on reset detection logic. */ + kCMC_VDReset = CMC_SRS_VD_MASK, /*!< The reset caused by an LVD or HVD. */ + kCMC_WarmReset = CMC_SRS_WARM_MASK, /*!< The last reset source is a warm reset source. */ + kCMC_FatalReset = CMC_SRS_FATAL_MASK, /*!< The last reset source is a fatal reset source. */ + kCMC_PinReset = CMC_SRS_PIN_MASK, /*!< The reset caused by the RESET_b pin. */ + kCMC_DAPReset = CMC_SRS_DAP_MASK, /*!< The reset caused by a reset request from the Debug Access port. */ + kCMC_ResetTimeout = CMC_SRS_RSTACK_MASK, /*!< The reset caused by a timeout or other error condition in the system + reset generation. */ + kCMC_LowPowerAcknowledgeTimeoutReset = CMC_SRS_LPACK_MASK, /*!< The reset caused by a timeout in + low power mode entry logic. */ + kCMC_SCGReset = CMC_SRS_SCG_MASK, /*!< The reset caused by a loss of clock or loss of lock event in the SCG. */ + kCMC_WindowedWatchdog0Reset = CMC_SRS_WWDT0_MASK, /*!< The reset caused by the Windowed WatchDog 0 timeout. */ + kCMC_SoftwareReset = CMC_SRS_SW_MASK, /*!< The reset caused by a software reset request. */ + kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */ +#if defined(CMC_SRS_CPU1_MASK) + kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */ +#endif /* CMC_SRS_CPU1_MASK */ +#if defined(CMC_SRS_VBAT_MASK) + kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */ +#endif /* CMC_SRS_VBAT_MASK */ +#if defined(CMC_SRS_WWDT1_MASK) + kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK, /*!< The reset caused by the Windowed WatchDog 1 timeout. */ +#endif /* CMC_SRS_WWDT1_MASK */ + kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */ +#if defined(CMC_SRS_CDOG1_MASK) + kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */ +#endif /* CMC_SRS_CDOG1_MASK */ + kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */ +#if defined(CMC_SRS_SECVIO_MASK) + kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */ +#endif /* CMC_SRS_SECVIO_MASK */ +#if defined(CMC_SRS_TAMPER_MASK) + kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */ +#endif /* CMC_SRS_TAMPER_MASK */ +}; + +/*! + * @brief Indicate the core clock was gated. + */ +typedef enum _cmc_core_clock_gate_status +{ + kCMC_CoreClockNotGated = 0U, /*!< Core clock not gated. */ + kCMC_CoreClockGated = 1U /*!< Core clock was gated due to low power mode entry. */ +} cmc_core_clock_gate_status_t; + +/*! + * @brief CMC clock mode enumeration. + */ +typedef enum _cmc_clock_mode +{ + kCMC_GateNoneClock = 0x00U, /*!< No clock gating. */ + kCMC_GateCoreClock = 0x01U, /*!< Gate Core clock. */ + kCMC_GateCorePlatformClock = 0x03U, /*!< Gate Core clock and platform clock. */ + kCMC_GateAllSystemClocks = 0x07U, /*!< Gate all System clocks, without getting core entering into low power mode. */ + kCMC_GateAllSystemClocksEnterLowPowerMode = 0x0FU /*!< Gate all System clocks, with core + entering into low power mode. */ +} cmc_clock_mode_t; + +/*! + * @brief CMC power mode enumeration. + */ +typedef enum _cmc_low_power_mode +{ + kCMC_ActiveOrSleepMode = 0x0U, /*!< Select Active/Sleep mode. */ + kCMC_DeepSleepMode = 0x1U, /*!< Select Deep Sleep mode when a core executes WFI or WFE instruction. */ + kCMC_PowerDownMode = 0x3U, /*!< Select Power Down mode when a core executes WFI or WFE instruction. */ + kCMC_DeepPowerDown = 0xFU, /*!< Select Deep Power Down mode when a core executes WFI or WFE instruction. */ +} cmc_low_power_mode_t; + +/*! + * @brief CMC reset pin configuration. + */ +typedef struct _cmc_reset_pin_config +{ + bool lowpowerFilterEnable; /*!< Low Power Filter enable. */ + bool resetFilterEnable; /*!< Reset Filter enable. */ + uint8_t resetFilterWidth; /*!< Width of the Reset Filter. */ +} cmc_reset_pin_config_t; + +/*! + * @brief power mode configuration for each power domain. + */ +typedef struct _cmc_power_domain_config +{ + cmc_clock_mode_t clock_mode; /*!< Clock mode for each power domain. */ + cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */ +#if (CMC_PMCTRL_COUNT > 1U) + cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */ +#endif /* (CMC_PMCTRL_COUNT > 1U) */ +} cmc_power_domain_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name CLOCK mode configuration. + * @{ + */ + +/*! + * @brief Sets clock mode. + * + * This function configs the amount of clock gating when the core asserts + * Sleeping due to WFI, WFE or SLEEPONEXIT. + * + * @param base CMC peripheral base address. + * @param mode System clock mode. + */ +void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode); + +/*! + * @brief Locks the clock mode setting. + * + * After invoking this function, any clock mode setting will be blocked. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockClockModeSetting(CMC_Type *base) +{ + base->CKCTRL |= CMC_CKCTRL_LOCK_MASK; +} + +/* @} */ + +/*! + * @name Gets/Clears the Clock Mode, the wake up source, the Reset source. + * @{ + */ + +/*! + * @brief Gets the core clock gated status. + * + * This function get the status to indicate whether the core clock is gated. + * The core clock gated status can be cleared by software. + * + * @param base CMC peripheral base address. + * @return The status to indicate whether the core clock is gated. + */ +static inline cmc_core_clock_gate_status_t CMC_GetCoreClockGatedStatus(CMC_Type *base) +{ + return (cmc_core_clock_gate_status_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_VALID_MASK) >> CMC_CKSTAT_VALID_SHIFT); +} + +/*! + * @brief Clears the core clock gated status. + * + * This function clear clock status flag by software. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_ClearCoreClockGatedStatus(CMC_Type *base) +{ + base->CKSTAT |= CMC_CKSTAT_VALID_MASK; +} + +/*! + * @brief Gets the Wakeup Source. + * + * This function gets the Wakeup sources from the previous low power mode entry. + * + * @param base CMC peripheral base address. + * @return The Wakeup sources from the previous low power mode entry. See @ref _cmc_wakeup_sources for details. + */ +static inline uint8_t CMC_GetWakeupSource(CMC_Type *base) +{ + return ((uint8_t)((base->CKSTAT & CMC_CKSTAT_WAKEUP_MASK) >> CMC_CKSTAT_WAKEUP_SHIFT)); +} + +/*! + * @brief Gets the Clock mode. + * + * This function gets the clock mode of the previous low power mode entry. + * + * @param base CMC peripheral base address. + * @return The Low Power status. + */ +static inline cmc_clock_mode_t CMC_GetClockMode(CMC_Type *base) +{ + return (cmc_clock_mode_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_CKMODE_MASK) >> CMC_CKSTAT_CKMODE_SHIFT); +} + +/*! + * @brief Gets the System reset status. + * + * This function returns the system reset status. Those status + * updates on every MAIN Warm Reset to indicate the type/source + * of the most recent reset. + * + * @param base CMC peripheral base address. + * @return The most recent system reset status. See @ref _cmc_system_reset_sources for details. + */ +static inline uint32_t CMC_GetSystemResetStatus(CMC_Type *base) +{ + return base->SRS; +} + +/*! + * @brief Gets the sticky system reset status since the last WAKE Cold Reset. + * + * This function gets all source of system reset that have generated a + * system reset since the last WAKE Cold Reset, and that have not been + * cleared by software. + * + * @param base CMC peripheral base address. + * @return System reset status that have not been cleared by software. See @ref _cmc_system_reset_sources for details. + */ +static inline uint32_t CMC_GetStickySystemResetStatus(CMC_Type *base) +{ + return base->SSRS; +} + +/*! + * @brief Clears the sticky system reset status flags. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the sticky system reset status to be cleared. + */ +static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mask) +{ + base->SSRS = mask; +} + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) && FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) +/*! + * @brief Gets the number of reset sequences completed since the last Cold Reset. + * + * @param base CMC peripheral base address. + * @return The number of reset sequences. + */ +static inline uint8_t CMC_GetResetCount(CMC_Type *base) +{ + return (uint8_t)(base->RSTCNT & CMC_RSTCNT_COUNT_MASK); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG */ + +/* @} */ + +/*! + * @name Power mode configuration. + * @{ + */ + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes. This should be done before set the lowPower mode + * for each power doamin. + * + * The allowed lowpower modes are passed as bit map. For example, to allow + * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). + * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes). + * + * @param base CMC peripheral base address. + * @param allowedModes Bitmaps of the allowed power modes. See @ref _cmc_power_mode_protection for details. + */ +void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes); + +/*! + * @brief Locks the power mode protection. + * + * This function locks the power mode protection. After invoking this function, + * any power mode protection setting will be ignored. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockPowerModeProtectionSetting(CMC_Type *base) +{ + base->PMPROT |= CMC_PMPROT_LOCK_MASK; +} + +/*! + * @brief Config the same lowPower mode for all power domain. + * + * This function configures the same low power mode for MAIN power domian and WAKE power domain. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + */ +static inline void CMC_SetGlobalPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->GPMCTRL = CMC_GPMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Configures entry into low power mode for the MAIN Power domain. + * + * This function configures the low power mode for the MAIN power domian, + * when the core executes WFI/WFE instruction. The available lowPower modes + * are defined in the @ref cmc_low_power_mode_t. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + * + */ +static inline void CMC_SetMAINPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->PMCTRL[0] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Gets the power mode of the MAIN Power domain. + * + * @param base CMC peripheral base address. + * @return The power mode of MAIN Power domain. See @ref cmc_low_power_mode_t for details. + */ +static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base) +{ + return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[0] & CMC_PMCTRL_LPMODE_MASK); +} + +#if (CMC_PMCTRL_COUNT > 1U) +/*! + * @brief Configure entry into low power mode for the WAKE Power domain. + * + * This function configures the low power mode for the WAKE power domian, + * when the core executes WFI/WFE instruction. The available lowPower mode + * are defined in the @ref cmc_low_power_mode_t. + * + * @note The lowPower Mode for the WAKE domain must not be configured to a + * lower power mode than any other power domain. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + * + */ +static inline void CMC_SetWAKEPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->PMCTRL[1] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Gets the power mode of the WAKE Power domain. + * + * @param base CMC peripheral base address. + * @return The power mode of WAKE Power domain. See @ref cmc_low_power_mode_t for details. + */ +static inline cmc_low_power_mode_t CMC_GetWAKEPowerMode(CMC_Type *base) +{ + return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[1] & CMC_PMCTRL_LPMODE_MASK); +} +#endif /* CMC_PMCTRL_COUNT > 1U */ + +/* @} */ + +/*! + * @name Reset Pin configuration. + * @{ + */ + +/*! + * @brief Configure reset pin. + * + * This function configures reset pin. When enabled, the low power filter is enabled in both + * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers + * are enabled, they operate in series. + * + * @param base CMC peripheral base address. + * @param config Pointer to the reset pin config structure. + */ +void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config); + +/* @} */ + +/*! + * @name System Reset Interrupts. + * @{ + */ + +/*! + * @brief Enable system reset interrupts. + * + * This function enables the system reset interrupts. The assertion of + * non-fatal warm reset can be delayed for 258 cycles of the 32K_CLK clock + * while an enabled interrupt is generated. Then Software can perform a graceful + * shutdown or abort the non-fatal warm reset provided the pending reset source is cleared + * by resetting the reset source and then clearing the pending flag. + * + * @param base CMC peripheral base address. + * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details. + * + */ +static inline void CMC_EnableSystemResetInterrupt(CMC_Type *base, uint32_t mask) +{ + base->SRIE |= mask; +} + +/*! + * @brief Disable system reset interrupts. + * + * This function disables the system reset interrupts. + * + * @param base CMC peripheral base address. + * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details. + */ +static inline void CMC_DisableSystemResetInterrupt(CMC_Type *base, uint32_t mask) +{ + base->SRIE &= (uint32_t)(~mask); +} + +/*! + * @brief Gets System Reset interrupt flags. + * + * This function returns the System reset interrupt flags. + * + * @param base CMC peripheral base address. + * @return System reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details. + */ +static inline uint32_t CMC_GetSystemResetInterruptFlags(CMC_Type *base) +{ + return base->SRIF; +} + +/*! + * @brief Clears System Reset interrupt flags. + * + * This function clears system reset interrupt flags. The pending reset source + * can be cleared by resetting the source of the reset and then clearing the pending + * flags. + * + * @param base CMC peripheral base address. + * @param mask System Reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details. + * + */ +static inline void CMC_ClearSystemResetInterruptFlags(CMC_Type *base, uint32_t mask) +{ + base->SRIF = mask; +} + +/* @} */ + +/*! + * @name Non Maskable Pin interrupt. + * @{ + */ + +/*! + * @brief Enable/Disable Non maskable Pin interrupt. + * + * @param base CMC peripheral base address. + * @param enable Enable or disable Non maskable pin interrupt. + * true - enable Non-maskable pin interrupt. + * false - disable Non-maskable pin interupt. + */ +static inline void CMC_EnableNonMaskablePinInterrupt(CMC_Type *base, bool enable) +{ + if (enable) + { + base->CORECTL |= CMC_CORECTL_NPIE_MASK; + } + else + { + base->CORECTL &= ~CMC_CORECTL_NPIE_MASK; + } +} + +/* @} */ + +/*! + * @name Boot Configuration. + * @{ + */ + +/*! + * @brief Gets the logic state of the ISPMODE_n pin. + * + * This function returns the logic state of the ISPMODE_n pin + * on the last negation of RESET_b pin. + * + * @param base CMC peripheral base address. + * @return The logic state of the ISPMODE_n pin on the last negation of RESET_b pin. + */ +static inline uint8_t CMC_GetISPMODEPinLogic(CMC_Type *base) +{ + return (uint8_t)((base->MR[0] & CMC_MR_ISPMODE_n_MASK) >> CMC_MR_ISPMODE_n_SHIFT); +} + +/*! + * @brief Clears ISPMODE_n pin state. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_ClearISPMODEPinLogic(CMC_Type *base) +{ + base->MR[0] = CMC_MR_ISPMODE_n_MASK; +} + +/*! + * @brief Set the logic state of the BOOT_CONFIGn pin. + * + * This function force the logic state of the Boot_Confign pin to assert + * on next system reset. + * + * @param base CMC peripheral base address. + * @param assert Assert the corresponding pin or not. + * true - Assert corresponding pin on next system reset. + * false - No effect. + */ +static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert) +{ + if (assert) + { + base->FM[0] |= CMC_FM_FORCECFG_MASK; + } + else + { + base->FM[0] &= ~CMC_FM_FORCECFG_MASK; + } +} + +/* @} */ + +/*! + * @name BootROM Status. + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BSR_REG) && FSL_FEATURE_MCX_CMC_HAS_BSR_REG) +/*! + * @brief Gets the status information written by the BootROM. + * + * @param base CMC peripheral base address. + * @return The status information written by the BootROM. + */ +static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base) +{ + return base->BSR; +} + +/*! + * @brief Sets the bootROM status value. + * + * @note This function is useful when result of CMC_CheckBootRomRegisterWrittable() is true. + * + * @param base CMC peripheral base address. + * @param stat The state value to set. + */ +static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue) +{ + base->BSR = CMC_BSR_STAT(statValue); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_BSR_REG */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BLR_REG) && FSL_FEATURE_MCX_CMC_HAS_BLR_REG) +/*! + * @brief Check if BootROM status and lock registers is writtable. + * + * @param base CMC peripheral base address. + * @return The result of whether BootROM status and lock register is writtable. + * - \b true BootROM status and lock registers are writtable; + * - \b false BootROM status and lock registers are not writtable. + */ +static inline bool CMC_CheckBootRomRegisterWrittable(CMC_Type *base) +{ + return (base->BLR == 0x2UL); +} + +/*! + * @brief After invoking this function, BootROM status and lock registers cannot be written. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockBootRomStatusWritten(CMC_Type *base) +{ + base->BLR = CMC_BLR_LOCK(0x5U); +} + +/*! + * @brief After invoking this function, BootROM status and lock register can be written.s + * + * @param base + */ +static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base) +{ + base->BLR = CMC_BLR_LOCK(0x2U); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_BLR_REG */ + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * @name System SRAM Configuration. + * @{ + */ + +/*! + * @brief Power off the selected system SRAM always. + * + * This function power off the selected system SRAM always. The SRAM arrays should + * not be accessed while they are shut down. SRAM array contents are not retained + * if they are powered off. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be powered off all modes. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask); + +/*! + * @brief Power on SRAM during all mode. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be powered on all modes. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +static inline void CMC_PowerOnSRAMAllMode(CMC_Type *base, uint32_t mask) +{ + base->SRAMDIS[0] &= CMC_SRAMDIS_DIS((uint32_t)(~mask)); +} + +/*! + * @brief Power off the selected system SRAM during low power modes only. + * + * This function power off the selected system SRAM only during low power mode. + * SRAM array contents are not retained if they are power off. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be power off during low power mode only. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask); + +/*! + * @brief Power on the selected system SRAM during low power modes only. + * + * This function power on the selected system SRAM. The SRAM arrray contents are + * retained in low power modes. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be power on during low power mode only. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) +{ + base->SRAMRET[0] &= CMC_SRAMRET_RET((uint32_t)(~mask)); +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +/*! + * @name Flash Low Power Mode configuration. + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * @brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * @param base CMC peripheral base address. + * @param doze true: Flash is disabled while core is sleeping + * false: No effect. + * @param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable); +#else +/*! + * @brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * @param base CMC peripheral base address. + * @param wake true: Flash will exit low power state during the flash memory accesses. + * false: No effect. + * @param doze true: Flash is disabled while core is sleeping + * false: No effect. + * @param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable); +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ +/* @} */ + +/*! + * @name Debug Configuration. + */ + +/*! + * @brief Enables/Disables debug Operation when the core sleep. + * + * This function configs what happens to debug when core sleeps. + * + * @param base CMC peripheral base address. + * @param enable Enable or disable Debug when Core is sleeping. + * true - Debug remains enabled when the core is sleeping. + * false - Debug is disabled when the core is sleeping. + */ +static inline void CMC_EnableDebugOperation(CMC_Type *base, bool enable) +{ + if (enable) + { + base->DBGCTL &= ~CMC_DBGCTL_SOD_MASK; + } + else + { + base->DBGCTL |= CMC_DBGCTL_SOD_MASK; + } +} + +/* @} */ + +/*! + * @name Low Power modes enter. + * @{ + */ +/*! + * @brief Prepares to enter low power modes. + * + * This function should be called before entering low power modes. + * + */ +void CMC_PreEnterLowPowerMode(void); + +/*! + * @brief Recovers after wake up from low power modes. + * + * This function should be called after wake up from low power modes. + * This function should be used with CMC_PreEnterLowPowerMode() + * + */ +void CMC_PostExitLowPowerMode(void); + +/*! + * @brief Configs the entry into the same low power mode for each power domains. + * + * This function provides the feature to entry into the same low power mode for each power + * domains. Before invoking this function, please ensure the selected power mode have been allowed. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details. + * + */ +void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode); + +/*! + * @brief Configs the entry into different low power modes for each power domains. + * + * This function provides the feature to entry into different low power modes for + * each power domains. Before invoking this function please ensure the selected + * modes are allowed. + * + * @param base CMC peripheral base address. + * @param config Pointer to the cmc_power_domain_config_t structure. + */ +void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ +#endif /* FSL_CMC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common.c new file mode 100644 index 0000000000..d3af9fdfc6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common.h new file mode 100644 index 0000000000..6a06037375 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) + +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */ + kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ + kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. + */ +/* @{ */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif +/* @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); +#endif + +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XTENSA__) +#include "fsl_common_dsp.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* FSL_COMMON_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common_arm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common_arm.c new file mode 100644 index 0000000000..45c7bb379a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common_arm.c @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/* Use WDT. */ +void MSDK_EnableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +uint32_t MSDK_GetCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#endif /* defined(DWT) */ + +#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT)) +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV X0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" + " SUB X0, X0, #1 \n" + " CMP X0, #0 \n" + + " BNE loop \n" + : + : + : "r0"); +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + MSDK_EnableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += MSDK_GetCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < MSDK_GetCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > MSDK_GetCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common_arm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common_arm.h new file mode 100644 index 0000000000..e5004d703b --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_common_arm.h @@ -0,0 +1,842 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * - SDK_ATOMIC_LOCAL_ADD + * - SDK_ATOMIC_LOCAL_SET + * - SDK_ATOMIC_LOCAL_CLEAR + * - SDK_ATOMIC_LOCAL_TOGGLE + * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET + * + * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) -= (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable + * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + */ +/* @{ */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/* @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to Enable. + * @param priNum Priority number set to interrupt controller register. + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); + GIC_EnableIRQ(interrupt); +#else + NVIC_SetPriority(interrupt, priNum); + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Set the IRQ priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); +#else + NVIC_SetPriority(interrupt, priNum); +#endif + } + + return status; +} + +/*! + * @brief Clear the pending IRQ flag. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The flag which IRQ to clear. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_ClearPendingIRQ(interrupt); +#else + NVIC_ClearPendingIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t mask; + +#if defined(CPSR_I_Msk) + mask = __get_CPSR() & CPSR_I_Msk; +#elif defined(DAIF_I_BIT) + mask = __get_DAIF() & DAIF_I_BIT; +#else + mask = __get_PRIMASK(); +#endif + __disable_irq(); + + return mask; +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#elif defined(DAIF_I_BIT) + if (0UL == primask) + { + __enable_irq(); + } +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/*! + * @brief Enable the counter to get CPU cycles. + */ +void MSDK_EnableCpuCycleCounter(void); + +/*! + * @brief Get the current CPU cycle count. + * + * @return Current CPU cycle count. + */ +uint32_t MSDK_GetCpuCycleCount(void); +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_crc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_crc.c new file mode 100644 index 0000000000..f4e303be95 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_crc.c @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.crc" +#endif + +/*! @internal @brief Has data register with name CRC. */ +#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG +#define DATA CRC +#define DATALL CRCLL +#endif + +#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-16-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U +/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#define CRC_DRIVER_DEFAULT_REFLECT_IN false +/*< Default is no transpose */ +#define CRC_DRIVER_DEFAULT_REFLECT_OUT false +/*< Default is transpose bytes */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 +/*< Default is 16-bit CRC protocol */ +#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum +/*< Default is resutl type is final checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ + +#if defined(CRC_RSTS) +#define CRC_RESETS_ARRAY CRC_RSTS +#endif + +/*! @brief CRC type of transpose of read write data */ +typedef enum _crc_transpose_type +{ + kCrcTransposeNone = 0U, /*! No transpose */ + kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ + kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ + kCrcTransposeBytes = 3U, /*! Transpose bytes */ +} crc_transpose_type_t; + +/*! + * @brief CRC module configuration. + * + * This structure holds the configuration for the CRC module. + */ +typedef struct _crc_module_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ + crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ +} crc_module_config_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +/*! + * @brief Get instance number for CRC module. + * + * @param base CRC peripheral base address + */ +static uint32_t CRC_GetInstance(CRC_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static uint32_t CRC_GetInstance(CRC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++) + { + if (s_crcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_crcBases)); + + return instance; +} +#endif + +/*! + * @brief Returns transpose type for CRC protocol reflect in parameter. + * + * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); +} + +/*! + * @brief Returns transpose type for CRC protocol reflect out parameter. + * + * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); +} + +/*! + * @brief Starts checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts the checksum computation by writing the seed value + * + * @param base CRC peripheral address. + * @param config Pointer to protocol configuration structure. + */ +static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) +{ + uint32_t crcControl; + + /* pre-compute value for CRC control registger based on user configuraton without WAS field */ + crcControl = 0U | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | + CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); + + /* make sure the control register is clear - WAS is deasserted, and protocol is set */ + base->CTRL = crcControl; + + /* write polynomial register */ + base->GPOLY = config->polynomial; + + /* write pre-computed control register value along with WAS to start checksum computation */ + base->CTRL = crcControl | CRC_CTRL_WAS(true); + + /* write seed (initial checksum) */ + base->DATA = config->seed; + + /* deassert WAS by writing pre-computed CRC control register value */ + base->CTRL = crcControl; +} + +/*! + * @brief Starts final checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts final checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum + * (output reflection and xor functions are applied). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = protocolConfig->complementChecksum; + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * @brief Starts intermediate checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts intermediate checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = + kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* ungate clock */ + CLOCK_EnableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(CRC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]); +#endif + + /* configure CRC module and write the seed */ + if (config->crcResult == kCrcFinalChecksum) + { + CRC_SetProtocolConfig(base, config); + } + else + { + CRC_SetRawProtocolConfig(base, config); + } +} + +/*! + * brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * endcode + * + * param config CRC protocol configuration structure. + */ +void CRC_GetDefaultConfig(crc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + static const crc_config_t crc16ccit = { + CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, + CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, + CRC_DRIVER_DEFAULT_CRC_RESULT, + }; + + *config = crc16ccit; +} + +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)(uint32_t)data; + while (dataSize >= sizeof(uint32_t)) + { + base->DATA = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize != 0U) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } +} + +/*! + * brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ +uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->DATA; +} + +/*! + * brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + uint32_t retval; + uint32_t totr; /* type of transpose read bitfield */ + + retval = base->DATA; + totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; + + /* check transpose type to get 16-bit out of 32-bit register */ + if (totr >= 2U) + { + /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ + retval &= 0xFFFF0000U; + retval = retval >> 16U; + } + else + { + /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ + retval &= 0x0000FFFFU; + } + return (uint16_t)retval; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_crc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_crc.h new file mode 100644 index 0000000000..8e1c29c6d1 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_crc.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_CRC_H_ +#define FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CRC driver version. Version 2.0.4. + * + * Current version: 2.0.4 + * + * Change log: + * + * - Version 2.0.4 + * - Release peripheral from reset if necessary in init function. + * + * - Version 2.0.3 + * - Fix MISRA issues + * + * - Version 2.0.2 + * - Fix MISRA issues + * + * - Version 2.0.1 + * - move DATA and DATALL macro definition from header file to source file + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ +#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC bit width */ +typedef enum _crc_bits +{ + kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ + kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ +} crc_bits_t; + +/*! @brief CRC result type */ +typedef enum _crc_result +{ + kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. + Reflect out and final xor protocol features are applied. */ + kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). + Reflect out and final xor protocol feature are not applied. + Intermediate checksum can be used as a seed for CRC_Init() + to continue adding data to this checksum. */ +} crc_result_t; + +/*! + * @brief CRC protocol configuration. + * + * This structure holds the configuration for the CRC protocol. + * + */ +typedef struct _crc_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first. + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + bool reflectIn; /*!< Reflect bits on input. */ + bool reflectOut; /*!< Reflect bits on output. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ + crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or + CRC_Get32bitResult() */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This function disables the clock gate in the SIM module for the CRC peripheral. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* gate clock */ + CLOCK_DisableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * @code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * @endcode + * + * @param config CRC protocol configuration structure. + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ +uint32_t CRC_Get32bitResult(CRC_Type *base); + +/*! + * @brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* FSL_CRC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ctimer.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ctimer.c new file mode 100644 index 0000000000..e53bebdd01 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ctimer.c @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/*! + * @brief CTIMER generic IRQ handle function. + * + * @param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { + kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0U); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1U); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the match channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1U; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on PWM pulse channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for PWM pulse channel */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for PWM pulse channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Specified channel pwmPeriodChannel defines the PWM period */ + period = base->MR[pwmPeriodChannel]; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } +} + +/*! + * brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * param base Ctimer peripheral base address + * param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) +{ + return (base->EMR & matchChannel); +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +/*! + * brief CTIMER generic IRQ handle function. + * + * param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0] != NULL) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01UL << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void); +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void); +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void); +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void); +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void); +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ctimer.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ctimer.h new file mode 100644 index 0000000000..713c15a77c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ctimer.h @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CTIMER_H_ +#define FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of external match */ +typedef enum _ctimer_external_match +{ + kCTIMER_External_Match_0 = (1UL << 0), /*!< External match 0 */ + kCTIMER_External_Match_1 = (1UL << 1), /*!< External match 1 */ + kCTIMER_External_Match_2 = (1UL << 2), /*!< External match 2 */ + kCTIMER_External_Match_3 = (1UL << 3) /*!< External match 3 */ +} ctimer_external_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * @param base Ctimer peripheral base address + * @param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * @return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +/*! + * @brief Setup the timer prescale value. + * + * Specifies the maximum value for the Prescale Counter. + * + * @param base Ctimer peripheral base address + * @param prescale Prescale value + */ +static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale) +{ + base->PR = CTIMER_PR_PRVAL(prescale); +} + +/*! + * @brief Get capture channel value. + * + * Get the counter/timer value on the corresponding capture channel. + * + * @param base Ctimer peripheral base address + * @param capture Select capture channel + * + * @return The timer count capture value. + */ +static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture) +{ + return base->CR[capture]; +} + +/*! + * @brief Enable reset match channel. + * + * Set the specified match channel reset operation. + * + * @param base Ctimer peripheral base address + * @param match match channel used + * @param enable Enable match channel reset operation. + */ +static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } +} + +/*! + * @brief Enable stop match channel. + * + * Set the specified match channel stop operation. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable match channel stop operation. + */ +static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Enable reload channel falling edge. + * + * Enable the specified match channel reload match shadow value. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable . + */ +static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +/*! + * @brief Enable capture channel rising edge. + * + * Sets the specified capture channel for rising edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable rising edge capture. + */ +static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +/*! + * @brief Enable capture channel falling edge. + * + * Sets the specified capture channel for falling edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable falling edge capture. + */ +static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Set the specified match shadow channel. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param matchvalue Reload the value of the corresponding match register. + */ +static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue) +{ + base->MSR[match] = matchvalue; +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_CTIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma.c new file mode 100644 index 0000000000..ae3132c14a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma.c @@ -0,0 +1,2224 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma.h" +#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#include "fsl_memory.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma4" +#endif +#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#define CONVERT_TO_DMA_ADDRESS(addr) (MEMORY_ConvertMemoryMapAddress((uint32_t)(addr), kMEMORY_Local2DMA)) +#else +#define CONVERT_TO_DMA_ADDRESS(addr) ((uint32_t)(addr)) +#endif +#if defined(DMA_RSTS_N) +#define EDMA_RESETS_ARRAY DMA_RSTS_N +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Map transfer width. + * + * @param width transfer width. + */ +static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width); + +/*! + * @brief validate edma errata. + * + * @param base edma base address. + * @param tcd edma transfer content descriptor. + */ +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, const edma_tcd_t *tcd); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map EDMA instance number to base pointer. */ +static EDMA_Type *const s_edmaBases[] = EDMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map EDMA instance number to clock name. */ +static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EDMA_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_edmaResets[] = EDMA_RESETS_ARRAY; +#endif + +/*! @brief Array to map EDMA instance number to IRQ number. */ +static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS; + +/*! @brief Pointers to transfer handle for each EDMA channel. */ +static edma_handle_t *s_EDMAHandle[FSL_FEATURE_SOC_EDMA_COUNT][FSL_FEATURE_EDMA_MODULE_CHANNEL]; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EDMA_GetInstance(EDMA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) + { + if (s_edmaBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_edmaBases)); + + return instance; +} + +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, const edma_tcd_t *tcd) +{ + status_t status = kStatus_Success; + /* errata 51327: to use scatter gather feature, NBYTES must be multiple of 8 */ + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(base) == 1U) + { + if ((tcd->NBYTES % 8U) != 0U) + { + assert(false); + status = kStatus_InvalidArgument; + } + } + + return status; +} +#endif + +/*! + * brief Push content of TCD structure into hardware TCD register. + * + * param base EDMA peripheral base address. + * param channel EDMA channel number. + * param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, const edma_tcd_t *tcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + edma_tcd_t *tcdRegs = EDMA_TCD_BASE(base, channel); + +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if ((tcd->DLAST_SGA != 0U) && ((tcd->CSR & (uint16_t)DMA_CSR_ESG_MASK) != 0U) && + (EDMA_CheckErrata(base, tcd) != kStatus_Success)) + { + assert(false); + } +#endif + + /* Clear DONE bit first, otherwise ESG cannot be set */ + DMA_CLEAR_DONE_STATUS(base, channel); + + /* Push tcd into hardware TCD register */ + tcdRegs->SADDR = tcd->SADDR; + tcdRegs->SOFF = tcd->SOFF; + tcdRegs->ATTR = tcd->ATTR; + tcdRegs->NBYTES = tcd->NBYTES; + tcdRegs->SLAST = (uint32_t)tcd->SLAST; + tcdRegs->DADDR = tcd->DADDR; + tcdRegs->DOFF = tcd->DOFF; + tcdRegs->CITER = tcd->CITER; + tcdRegs->DLAST_SGA = (uint32_t)tcd->DLAST_SGA; + tcdRegs->CSR = tcd->CSR; + tcdRegs->BITER = tcd->BITER; +} + +/*! + * brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * param base eDMA peripheral base address. + * param config A pointer to the configuration structure, see "edma_config_t". + * note This function enables the minor loop map feature. + */ +void EDMA_Init(EDMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); + + uint32_t tmpreg, i = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EDMA peripheral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EDMA_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_edmaResets[EDMA_GetInstance(base)]); +#endif + +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA + /* clear all the enabled request, status to make sure EDMA status is in normal condition */ + EDMA_BASE(base)->ERQ = 0U; + EDMA_BASE(base)->INT = 0xFFFFFFFFU; + EDMA_BASE(base)->ERR = 0xFFFFFFFFU; + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = EDMA_BASE(base)->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(1U)); + EDMA_BASE(base)->CR = tmpreg; +#else + tmpreg = EDMA_MP_BASE(base)->MP_CSR; +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + tmpreg = (tmpreg & ~(DMA_MP_CSR_HAE_MASK | DMA_MP_CSR_ERCA_MASK | DMA_MP_CSR_EDBG_MASK | DMA_MP_CSR_GCLC_MASK | + DMA_MP_CSR_GMRC_MASK | DMA_MP_CSR_HALT_MASK)) | + DMA_MP_CSR_GMRC(config->enableMasterIdReplication) | DMA_MP_CSR_HAE(config->enableHaltOnError) | + DMA_MP_CSR_ERCA(config->enableRoundRobinArbitration) | DMA_MP_CSR_EDBG(config->enableDebugMode) | + DMA_MP_CSR_GCLC(config->enableGlobalChannelLink); +#else + tmpreg = (tmpreg & ~(DMA_MP_CSR_HAE_MASK | DMA_MP_CSR_ERCA_MASK | DMA_MP_CSR_EDBG_MASK | DMA_MP_CSR_GCLC_MASK | + DMA_MP_CSR_HALT_MASK)) | + DMA_MP_CSR_HAE(config->enableHaltOnError) | DMA_MP_CSR_ERCA(config->enableRoundRobinArbitration) | + DMA_MP_CSR_EDBG(config->enableDebugMode) | DMA_MP_CSR_GCLC(config->enableGlobalChannelLink); +#endif + EDMA_MP_BASE(base)->MP_CSR = tmpreg; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + /* channel transfer configuration */ + for (i = 0U; i < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base); i++) + { + if (config->channelConfig[i] != NULL) + { + EDMA_InitChannel(base, i, config->channelConfig[i]); + } + } +#endif +#endif +} + +/*! + * brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * param base eDMA peripheral base address. + */ +void EDMA_Deinit(EDMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate EDMA peripheral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +/*! + * brief EDMA Channel initialization + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param channelConfig pointer to user's eDMA channel config structure, see edma_channel_config_t for detail. + */ +void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig) +{ + assert(channelConfig != NULL); + + EDMA_SetChannelPreemptionConfig(base, channel, &channelConfig->channelPreemptionConfig); + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE + EDMA_SetChannelSwapSize(base, channel, channelConfig->channelSwapSize); +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE + EDMA_SetChannelMemoryAttribute(base, channel, channelConfig->channelWriteMemoryAttribute, + channelConfig->channelReadMemoryAttribute); +#endif +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION && FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION + EDMA_SetChannelSignExtension(base, channel, channelConfig->channelDataSignExtensionBitPosition); +#endif +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE + EDMA_SetChannelAccessType(base, channel, channelConfig->channelAccessType); +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + if (0U != (uint32_t)channelConfig->channelRequestSource) + { + /* dma request source */ + EDMA_SetChannelMux(base, channel, (int32_t)channelConfig->channelRequestSource); + } +#endif + + /* master ID replication */ + EDMA_EnableChannelMasterIDReplication(base, channel, channelConfig->enableMasterIDReplication); +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + /* dma transfer security level */ + EDMA_SetChannelSecurityLevel(base, channel, channelConfig->securityLevel); +#endif + /* dma transfer protection level */ + EDMA_SetChannelProtectionLevel(base, channel, channelConfig->protectionLevel); +} +#endif + +/*! + * brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * endcode + * + * param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableRoundRobinArbitration = false; + + config->enableHaltOnError = true; + +#if defined FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE && FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE + config->enableContinuousLinkMode = false; +#endif + +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + config->enableMasterIdReplication = false; +#endif + + config->enableDebugMode = false; + + config->enableGlobalChannelLink = true; +} + +/*! + * brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* reset channel CSR */ + EDMA_ClearChannelStatusFlags(base, channel, (uint32_t)kEDMA_DoneFlag | (uint32_t)kEDMA_ErrorFlag); + /* reset channel TCD */ + EDMA_TcdReset(EDMA_TCD_BASE(base, channel)); +} + +/*! + * brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * endcode + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(EDMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0U); + + EDMA_TcdSetTransferConfig(EDMA_TCD_BASE(base, channel), config, (edma_tcd_t *)CONVERT_TO_DMA_ADDRESS(nextTcd)); +} + +/*! + * brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = EDMA_TCD_BASE(base, channel)->NBYTES; + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + EDMA_TCD_BASE(base, channel)->NBYTES = tmpreg; +} + +/*! + * brief Configures the eDMA channel TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param base eDMA peripheral base address. + * param channel edma channel number. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TCD_BASE(base, channel)->SLAST = (uint32_t)sourceOffset; + EDMA_TCD_BASE(base, channel)->DLAST_SGA = (uint32_t)destOffset; +} + +/*! + * brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number + * param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + + bool tmpEnablePreemptAbility = config->enablePreemptAbility; + bool tmpEnablchannelPreemption = config->enableChannelPreemption; + uint8_t tmpChannelPriority = config->channelPriority; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + + volatile uint8_t *tmpReg = &EDMA_BASE(base)->DCHPRI3; + + ((volatile uint8_t *)tmpReg)[DMA_DCHPRI_INDEX(channel)] = + (DMA_DCHPRI0_DPA((true == tmpEnablePreemptAbility ? 0U : 1U)) | + DMA_DCHPRI0_ECP((true == tmpEnablchannelPreemption ? 1U : 0U)) | DMA_DCHPRI0_CHPRI(tmpChannelPriority)); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_PRI = DMA_CH_PRI_ECP(tmpEnablchannelPreemption) | + DMA_CH_PRI_DPA(tmpEnablePreemptAbility) | + DMA_CH_PRI_APL(tmpChannelPriority); +#endif +} + +/*! + * brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param type A channel link type, which can be one of the following: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TcdSetChannelLink(EDMA_TCD_BASE(base, channel), type, linkedChannel); +} + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param bandWidth A bandwidth setting, which can be one of the following: + * arg kEDMABandwidthStallNone + * arg kEDMABandwidthStall4Cycle + * arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TCD_BASE(base, channel)->CSR = + (uint16_t)((EDMA_TCD_BASE(base, channel)->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint16_t tmpreg = EDMA_TCD_BASE(base, channel)->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_BASE(base, channel)->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + /* Reset channel TCD */ + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; + tcd->DLAST_SGA = 0U; + /* Enable auto disable request feature */ + tcd->CSR = DMA_CSR_DREQ(1U); + tcd->BITER = 0U; +} + +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(config != NULL); + + EDMA_ConfigChannelSoftwareTCD(tcd, config); + + if (nextTcd != NULL) + { + tcd->DLAST_SGA = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * brief Sets TCD fields according to the user's channel transfer configuration structure, see + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * param tcd Pointer to the TCD structure. + * param transfer channel transfer configuration pointer. + * + */ +void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer) +{ + assert(transfer != NULL); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert(((uint32_t)transfer->srcOffset % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert(((uint32_t)transfer->destOffset % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcAddrModulo))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->dstAddrModulo))) == 0U); + + uint16_t tmpreg; + + tcd->SADDR = CONVERT_TO_DMA_ADDRESS(transfer->srcAddr); + /* destination address */ + tcd->DADDR = CONVERT_TO_DMA_ADDRESS(transfer->destAddr); + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(transfer->srcTransferSize) | DMA_ATTR_DSIZE(transfer->destTransferSize); + + /* Source address signed offset */ + tcd->SOFF = (uint16_t)(transfer->srcOffset); + /* Destination address signed offset */ + tcd->DOFF = (uint16_t)(transfer->destOffset); + + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + tcd->NBYTES = DMA_NBYTES_MLOFFYES_NBYTES(transfer->minorLoopBytes) | + DMA_NBYTES_MLOFFYES_MLOFF(transfer->minorLoopOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(transfer->enableDstMinorLoopOffset) | + DMA_NBYTES_MLOFFYES_SMLOE(transfer->enableSrcMinorLoopOffset); + } + else + { + tcd->NBYTES = DMA_NBYTES_MLOFFNO_NBYTES(transfer->minorLoopBytes); + } + + /* Current major iteration count */ + tcd->CITER = (uint16_t)(transfer->majorLoopCounts); + /* Starting major iteration count */ + tcd->BITER = (uint16_t)(transfer->majorLoopCounts); + /* reset CSR firstly */ + tcd->CSR = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (transfer->linkTCD != NULL) + { + tcd->DLAST_SGA = CONVERT_TO_DMA_ADDRESS((uint32_t)((uint8_t *)transfer->linkTCD)); + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + else + { + tcd->CSR &= ~(uint16_t)DMA_CSR_ESG_MASK; + tcd->DLAST_SGA = (uint32_t)transfer->dstMajorLoopOffset; + } + + /* configure interrupt/auto disable channel request */ + tcd->CSR |= (transfer->enabledInterruptMask & (~(uint16_t)kEDMA_ErrorInterruptEnable)); + + /* Minor link config */ + if (transfer->enableChannelMinorLoopLink) + { + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + tcd->BITER = tmpreg; + } + /* Major link config */ + if (transfer->enableChannelMajorLoopLink) + { + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(transfer->majorLoopLinkChannel); + } + + /* clear link relate field if no channel link enabled */ + if ((!transfer->enableChannelMajorLoopLink) && (!transfer->enableChannelMinorLoopLink)) + { + tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } + + /* major loop offset */ + tcd->SLAST = (uint32_t)transfer->srcMajorLoopOffset; + /* modulo feature */ + tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(transfer->dstAddrModulo) | DMA_ATTR_SMOD(transfer->srcAddrModulo); +} + +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint32_t tmpreg; + + tmpreg = tcd->NBYTES & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + tcd->NBYTES = tmpreg; +} + +/*! + * brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param tcd A point to the TCD structure. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->SLAST = (uint32_t)sourceOffset; + tcd->DLAST_SGA = (uint32_t)destOffset; +} + +/*! + * brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint16_t tmpreg; + + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + tcd->BITER = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint16_t tmpreg; + + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } +} + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint16_t tmpreg; + + tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + tcd->CSR |= DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Disables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + tcd->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + tcd->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return Major loop count which has not been transferred yet for the current TCD. + * note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t remainingCount = 0; + + if (0U != DMA_GET_DONE_STATUS(base, channel)) + { + remainingCount = 0; + } + else + { + /* Calculate the unfinished bytes */ + if (0U != (EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKNO_ELINK_MASK)) + { + remainingCount = (((uint32_t)EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKYES_CITER_MASK) >> + DMA_CITER_ELINKYES_CITER_SHIFT); + } + else + { + remainingCount = (((uint32_t)EDMA_TCD_BASE(base, channel)->CITER & DMA_CITER_ELINKNO_CITER_MASK) >> + DMA_CITER_ELINKNO_CITER_SHIFT); + } + } + + return remainingCount; +} + +/*! + * brief Enables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Enable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + DMA_ENABLE_ERROR_INT(base, channel); + } + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + DMA_ENABLE_MAJOR_INT(base, channel); + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + DMA_ENABLE_HALF_INT(base, channel); + } +} + +/*! + * brief Disables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Disable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + DMA_DISABLE_ERROR_INT(base, channel); + } + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + DMA_DISABLE_MAJOR_INT(base, channel); + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + DMA_DISABLE_HALF_INT(base, channel); + } +} + +/*! + * brief Gets the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= DMA_GET_DONE_STATUS(base, channel); + /* Get ERROR bit flag */ + retval |= (DMA_GET_ERROR_STATUS(base, channel) << 1U); + /* Get INT bit flag */ + retval |= (DMA_GET_INT_STATUS(base, channel) << 2U); + + return retval; +} + +/*! + * brief Clears the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Clear DONE bit flag */ + if (0U != (mask & (uint32_t)kEDMA_DoneFlag)) + { + DMA_CLEAR_DONE_STATUS(base, channel); + } + /* Clear ERROR bit flag */ + if (0U != (mask & (uint32_t)kEDMA_ErrorFlag)) + { + DMA_CLEAR_ERROR_STATUS(base, channel); + } + /* Clear INT bit flag */ + if (0U != (mask & (uint32_t)kEDMA_InterruptFlag)) + { + DMA_CLEAR_INT_STATUS(base, channel); + } +} + +/*! + * brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * param base eDMA peripheral base address. + * param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t edmaInstance; + edma_tcd_t *tcdRegs; + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->channel = channel; + + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + s_EDMAHandle[edmaInstance][channel] = handle; + /* Enable NVIC interrupt */ + (void)EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + + handle->tcdBase = EDMA_TCD_BASE(base, channel); + handle->channelBase = EDMA_CHANNEL_BASE(base, channel); + handle->base = base; + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = handle->tcdBase; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; +} + +/*! + * brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * param handle eDMA handle pointer. + * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0U); + + /* Initialize tcd queue attribute. */ + /* header should initial as 1, since that it is used to point to the next TCD to be loaded into TCD memory, + * In EDMA driver IRQ handler, header will be used to calculate how many tcd has done, for example, + * If application submit 4 transfer request, A->B->C->D, + * when A finshed, the header is 0, C is the next TCD to be load, since B is already loaded, + * according to EDMA driver IRQ handler, tcdDone = C - A - header = 2 - header = 2, but actually only 1 TCD done, + * so the issue will be the wrong TCD done count will pass to application in first TCD interrupt. + * During first submit, the header should be assigned to 1, since 0 is current one and 1 is next TCD to be loaded, + * but software cannot know which submission is the first one, so assign 1 to header here. + */ + handle->header = 1; + handle->tcdUsed = 0; + handle->tcdSize = (int8_t)tcdSize; + handle->tcdPool = tcdPool; +} + +/*! + * brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * param handle eDMA handle pointer. + * param callback eDMA callback function pointer. + * param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width) +{ + edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes; + + /* map width to register value */ + switch (width) + { + /* width 8bit */ + case 1U: + transferSize = kEDMA_TransferSize1Bytes; + break; + /* width 16bit */ + case 2U: + transferSize = kEDMA_TransferSize2Bytes; + break; + /* width 32bit */ + case 4U: + transferSize = kEDMA_TransferSize4Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + /* width 64bit */ + case 8U: + transferSize = kEDMA_TransferSize8Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + /* width 128bit */ + case 16U: + transferSize = kEDMA_TransferSize16Bytes; + break; +#endif + /* width 256bit */ + case 32U: + transferSize = kEDMA_TransferSize32Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + /* width 512bit */ + case 64U: + transferSize = kEDMA_TransferSize64Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + /* width 1024bit */ + case 128U: + transferSize = kEDMA_TransferSize128Bytes; + break; +#endif + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + return transferSize; +} + +/*! + * brief Prepares the eDMA transfer structure configurations. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param srcOffset source address offset. + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param destOffset destination address offset. + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. + */ +void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 128U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 128U) && ((destWidth & (destWidth - 1U)) == 0U)); +#elif (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 64U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 64U) && ((destWidth & (destWidth - 1U)) == 0U)); +#else + assert((srcWidth != 0U) && (srcWidth <= 32U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 32U) && ((destWidth & (destWidth - 1U)) == 0U)); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + assert(srcWidth != 8U); + assert(srcWidth != 8U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + assert(srcWidth != 16U); + assert(srcWidth != 16U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert(srcWidth != 64U); + assert(srcWidth != 64U); +#endif + assert((transferBytes % bytesEachRequest) == 0U); + assert((((uint32_t)(uint8_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint8_t *)destAddr) % destWidth) == 0U); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->destAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)destAddr); + config->srcAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)srcAddr); + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + config->srcTransferSize = EDMA_TransferWidthMapping(srcWidth); + config->destTransferSize = EDMA_TransferWidthMapping(destWidth); + config->destOffset = destOffset; + config->srcOffset = srcOffset; + /* enable major interrupt by default */ + config->enabledInterruptMask = (uint16_t)kEDMA_MajorInterruptEnable; +} + +/*! + * brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param type eDMA transfer type. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + + int16_t srcOffset = 0, destOffset = 0; + + switch (type) + { + case kEDMA_MemoryToMemory: + destOffset = (int16_t)destWidth; + srcOffset = (int16_t)srcWidth; + break; + case kEDMA_MemoryToPeripheral: + destOffset = 0; + srcOffset = (int16_t)srcWidth; + break; + case kEDMA_PeripheralToMemory: + destOffset = (int16_t)destWidth; + srcOffset = 0; + break; + case kEDMA_PeripheralToPeripheral: + destOffset = 0; + srcOffset = 0; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + EDMA_PrepareTransferConfig(config, srcAddr, srcWidth, srcOffset, destAddr, destWidth, destOffset, bytesEachRequest, + transferBytes); +} + +/*! + * brief Prepares the eDMA transfer content descriptor. + * + * This function prepares the transfer content descriptor structure according to the user input. + * + * param handle eDMA handle pointer. + * param tcd Pointer to eDMA transfer content descriptor structure. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param srcOffset source address offset. + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param destOffset destination address offset. + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param nextTcd eDMA transfer linked TCD address. + * + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 128U) && ((srcWidth & (srcWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); + assert((destWidth != 0U) && (destWidth <= 128U) && ((destWidth & (destWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#elif (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 64U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 64U) && ((destWidth & (destWidth - 1U)) == 0U)); +#else + assert((srcWidth != 0U) && (srcWidth <= 32U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 32U) && ((destWidth & (destWidth - 1U)) == 0U)); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + assert(srcWidth != 8U); + assert(srcWidth != 8U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + assert(srcWidth != 16U); + assert(srcWidth != 16U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert(srcWidth != 64U); + assert(srcWidth != 64U); +#endif + assert((transferBytes % bytesEachRequest) == 0U); + assert((((uint32_t)(uint32_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint32_t *)destAddr) % destWidth) == 0U); + + edma_transfer_size_t srcTransferSize = EDMA_TransferWidthMapping(srcWidth), + destTransferSize = EDMA_TransferWidthMapping(srcWidth); + + /* Initializes the configure structure to zero. */ + EDMA_TcdReset(tcd); + + assert((bytesEachRequest % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert((bytesEachRequest % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)srcOffset % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)destOffset % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)srcAddr % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)destAddr % (1UL << ((uint32_t)destTransferSize))) == 0U); + + tcd->SADDR = CONVERT_TO_DMA_ADDRESS((uint32_t *)srcAddr); + /* destination address */ + tcd->DADDR = CONVERT_TO_DMA_ADDRESS((uint32_t *)destAddr); + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize); + + /* Source address signed offset */ + tcd->SOFF = (uint16_t)(srcOffset); + /* Destination address signed offset */ + tcd->DOFF = (uint16_t)(destOffset); + + tcd->NBYTES = DMA_NBYTES_MLOFFNO_NBYTES(bytesEachRequest); + + /* Current major iteration count */ + tcd->CITER = (uint16_t)(transferBytes / bytesEachRequest); + /* Starting major iteration count */ + tcd->BITER = (uint16_t)(transferBytes / bytesEachRequest); + /* reset CSR firstly */ + tcd->CSR = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + tcd->DLAST_SGA = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + + /* configure interrupt/auto disable channel request, enable major interrupt by default */ + tcd->CSR |= (tcd->CSR & (~(uint16_t)kEDMA_ErrorInterruptEnable)) | (uint16_t)kEDMA_MajorInterruptEnable; +} + +/*! + * brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * Typical user case: + * 1. submit single transfer + * code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 2. submit static link transfer, + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * + * 3. submit dynamic link transfer + * code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 4. submit loop transfer + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * + * param handle eDMA handle pointer. + * param tcd Pointer to eDMA transfer content descriptor structure. + * + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, const edma_tcd_t *tcd) +{ + assert(handle != NULL); + assert(handle->tcdBase != NULL); + + edma_tcd_t *tcdRegs = handle->tcdBase; + + if (handle->tcdPool == NULL) + { + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel sevice doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((tcdRegs->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((tcdRegs->CITER & DMA_CITER_ELINKNO_CITER_MASK) != (tcdRegs->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_InstallTCD(handle->base, handle->channel, tcd); + /* Enable auto disable request feature */ + EDMA_EnableAutoStopRequest(handle->base, handle->channel, true); + /* Enable major interrupt */ + EDMA_EnableChannelInterrupts(handle->base, handle->channel, kEDMA_MajorInterruptEnable); + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + (void)memcpy(&handle->tcdPool[currentTcd], tcd, sizeof(edma_tcd_t)); + + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + + if ((tcd->DLAST_SGA == 0U) || ((tcd->CSR & DMA_CSR_ESG_MASK) == 0U)) + { + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); + } + + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + /* Enable scatter/gather feature in the previous TCD block. */ + csr = handle->tcdPool[previousTcd].CSR | ((uint16_t)DMA_CSR_ESG_MASK); + csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0UL) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + + return kStatus_Success; + } +} + +/*! + * brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * param handle eDMA handle pointer. + * param config Pointer to eDMA transfer configuration structure. + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + assert(handle->tcdBase != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert(((config->srcTransferSize != kEDMA_TransferSize128Bytes) && + (config->destTransferSize != kEDMA_TransferSize128Bytes)) || + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#endif + edma_tcd_t *tcdRegs = handle->tcdBase; + + if (handle->tcdPool == NULL) + { + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel sevice doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((tcdRegs->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((tcdRegs->CITER & DMA_CITER_ELINKNO_CITER_MASK) != (tcdRegs->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_TcdSetTransferConfig(tcdRegs, config, NULL); + /* Enable auto disable request feature */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + tcdRegs->CSR |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + /* Enable scatter/gather feature in the previous TCD block. */ + csr = handle->tcdPool[previousTcd].CSR | ((uint16_t)DMA_CSR_ESG_MASK); + csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0UL) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + + return kStatus_Success; + } +} + +/*! + * brief Submits the eDMA scatter gather transfer configurations. + * + * The function is target for submit loop transfer request, + * the ring transfer request means that the transfer request TAIL is link to HEAD, such as, + * A->B->C->D->A, or A->A + * + * To use the ring transfer feature, the application should allocate several transfer object, such as + * @code + * edma_channel_transfer_config_t transfer[2]; + * EDMA_TransferSubmitLoopTransfer(handle, &transfer, 2U); + * @endcode + * Then eDMA driver will link transfer[0] and transfer[1] to each other + * + * note Application should check the return value of this function to avoid transfer request + * submit failed + * + * param handle eDMA handle pointer + * param transfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail + * param transferLoopCount the count of the transfer ring, if loop count is 1, that means that the one will link to + * itself. + * + * retval #kStatus_Success It means submit transfer request succeed + * retval #kStatus_EDMA_Busy channel is in busy status + * retval #kStatus_InvalidArgument Invalid Argument + */ +status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount) +{ + assert(transfer != NULL); + assert(handle != NULL); + assert(handle->tcdPool != NULL); + + uint32_t i = 0U; + + if (handle->tcdSize < (int8_t)transferLoopCount) + { + return kStatus_InvalidArgument; + } + + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel service doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((handle->tcdBase->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((handle->tcdBase->CITER & DMA_CITER_ELINKNO_CITER_MASK) != + (handle->tcdBase->BITER & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + + (void)memset(handle->tcdPool, 0, (uint32_t)handle->tcdSize * sizeof(edma_tcd_t)); + for (i = 0U; i < transferLoopCount - 1UL; i++) + { + transfer[i].linkTCD = &handle->tcdPool[i + 1UL]; + EDMA_ConfigChannelSoftwareTCD(&(handle->tcdPool[i]), &transfer[i]); +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &(handle->tcdPool[i])) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + } + + /* prepare last one in the ring and link it to the HEAD of the ring */ + transfer[i].linkTCD = &handle->tcdPool[0]; + EDMA_ConfigChannelSoftwareTCD(&(handle->tcdPool[i]), &transfer[i]); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + EDMA_EnableMinorLoopMapping(handle->psBase, true); + } +#endif + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[0U]); + + /* enable interrupt */ + EDMA_EnableChannelInterrupts(handle->base, handle->channel, + ((uint32_t)transfer->enabledInterruptMask & ~((uint32_t)kEDMA_ErrorInterruptEnable))); + + return kStatus_Success; +} + +/*! + * brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + edma_tcd_t *tcdRegs = handle->tcdBase; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & ((uint32_t)1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + tmpCSR = tcdRegs->CSR; + if ((0U == (tmpCSR & DMA_CSR_DONE_MASK)) || (0U != (tmpCSR & DMA_CSR_ESG_MASK))) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +#else +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && handle->channelBase->CH_MUX == 0U) + { + tcdRegs->CSR |= DMA_CSR_START_MASK; + } + else +#endif + if (handle->tcdPool == NULL) + { + handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; + } + else + { + /* Check if channel request is actually disable. */ + if ((handle->channelBase->CH_CSR & DMA_CH_CSR_ERQ_MASK) == 0U) + { + /* Check if transfer is paused. */ + if ((!((handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK) != 0U)) || + ((tcdRegs->CSR & DMA_CSR_ESG_MASK) != 0U)) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; + } + } + } +#endif +} + +/*! + * brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +#else + handle->channelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_ERQ_MASK)); +#endif +} + +/*! + * brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + EDMA_StopTransfer(handle); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + EDMA_TcdReset(handle->tcdBase); + + /* Handle the tcd */ + if (handle->tcdPool != NULL) + { + handle->header = 1; + handle->tail = 0; + handle->tcdUsed = 0; + } +} + +/*! + * brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + bool transfer_done; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + /* Check if transfer is already finished. */ + transfer_done = ((handle->tcdBase->CSR & DMA_CSR_DONE_MASK) != 0U); +#else + transfer_done = (bool)(handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK); +#endif + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if ((handle->base->INT >> channel) != 0U) + { + handle->base->CINT = channel; + } +#else + if ((handle->channelBase->CH_INT & DMA_CH_INT_INT_MASK) != 0U) + { + handle->channelBase->CH_INT |= DMA_CH_INT_INT_MASK; + } +#endif + + if (handle->tcdPool == NULL) + { + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, transfer_done, 0); + } + } + else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ + { + uint32_t sga = (uint32_t)((edma_tcd_t *)(handle->tcdBase))->DLAST_SGA; + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + bool esg = ((handle->tcdBase->CSR & DMA_CSR_ESG_MASK) != 0U); + + /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga -= CONVERT_TO_DMA_ADDRESS((uint32_t)handle->tcdPool); + /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD to be loaded (current one is already finished) */ + new_header = (uint8_t)sga_index; + } + else + { + /* New header shall point to this descriptor currently loaded (not finished yet) */ + new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == (uint8_t)handle->header) + { + int8_t tmpTcdUsed = handle->tcdUsed; + int8_t tmpTcdSize = handle->tcdSize; + + /* check esg here for the case that application submit only one request, once the request complete: + * new_header(1) = handle->header(1) + * tcdUsed(1) != tcdSize(>1) + * As the application submit only once, so scatter gather must not enabled, then tcds_done should be 1 + */ + if ((tmpTcdUsed == tmpTcdSize) || (!esg)) + { + tcds_done = handle->tcdUsed; + } + else + { + /* No TCD in the memory are going to be loaded or internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = (int32_t)new_header - (int32_t)handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + /* + * While code run to here, it means a TCD transfer Done and a new TCD has loaded to the hardware + * so clear DONE here to allow submit scatter gather transfer request in the callback to avoid TCD + * overwritten. + */ + if (transfer_done) + { +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CDNE = handle->channel; +#else + handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; +#endif + } + } + /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ + handle->header = (int8_t)new_header; + /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ + handle->tcdUsed -= (int8_t)tcds_done; + /* Invoke callback function. */ + if (NULL != handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + + /* + * 1.clear the DONE bit here is meaningful for below cases: + * A new TCD has been loaded to EDMA already: + * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten + * if peripheral request isn't coming before next transfer request. + * 2. Don't clear DONE bit for below case, + * for the case that transfer request submitted in the privious edma callback, this is a case that doesn't + * need scatter gather, so keep DONE bit during the next transfer request submission will re-install the TCD and + * the DONE bit will be cleared together with TCD re-installation. + */ + if (transfer_done) + { + if ((handle->tcdBase->CSR & DMA_CSR_ESG_MASK) != 0U) + { +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CDNE = handle->channel; +#else + handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; +#endif + } + } + } +} + +void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel) +{ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if ((s_edmaBases[instance]->INT >> channel) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[instance][channel]); + } +#else + if ((EDMA_CHANNEL_BASE(s_edmaBases[instance], channel)->CH_INT & DMA_CH_INT_INT_MASK) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[instance][channel]); + } +#endif + SDK_ISR_EXIT_BARRIER; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma.h new file mode 100644 index 0000000000..4cee503c8d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma.h @@ -0,0 +1,1593 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EDMA_H_ +#define FSL_EDMA_H_ + +#include "fsl_common.h" +#include "fsl_edma_core.h" +/*! + * @addtogroup edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 9, 0)) /*!< Version 2.9.0. */ +/*@}*/ + +/*!@brief Macro used for allocate edma TCD */ +#define EDMA_ALLOCATE_TCD(name, number) AT_NONCACHEABLE_SECTION_ALIGN(edma_tcd_t name[number], EDMA_TCD_ALIGN_SIZE) + +/*! @brief _edma_transfer_status eDMA transfer status */ +enum +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3U - ((channel)&0x03U))) + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ +#endif + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +#if (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + kEDMA_TransferSize64Bytes = 0x6U, /*!< Source/Destination data transfer size is 64 bytes every time */ +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + kEDMA_TransferSize128Bytes = 0x7U, /*!< Source/Destination data transfer size is 128 bytes every time */ +#endif +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ +} edma_modulo_t; + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; +#endif + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief _edma_channel_status_flags eDMA channel status flags. */ +enum +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief _edma_error_status_flags eDMA channel error status flags. */ +enum +{ + kEDMA_DestinationBusErrorFlag = DMA_ERR_DBE_FLAG, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ERR_SBE_FLAG, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ERR_SGE_FLAG, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ERR_NCE_FLAG, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ERR_DOE_FLAG, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ERR_DAE_FLAG, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ERR_SOE_FLAG, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ERR_SAE_FLAG, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ERR_ERRCHAN_FLAG, /*!< Error channel number of the cancelled channel number */ +#if defined(FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR) && (FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR > 1) + kEDMA_ChannelPriorityErrorFlag = DMA_ERR_CPE_FLAG, /*!< Channel priority is not unique. */ +#endif + kEDMA_TransferCanceledFlag = DMA_ERR_ECX_FLAG, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) + kEDMA_GroupPriorityErrorFlag = DMA_ERR_GPE_FLAG, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = (int)DMA_ERR_FLAG, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ +}; + +/*! @brief _edma_interrupt_enable eDMA interrupt source */ +enum +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +}; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ + kEDMA_PeripheralToPeripheral, /*!< Transfer from Peripheral to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ +} edma_minor_offset_config_t; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE +/*! @brief eDMA channel memory attribute */ +typedef enum edma_channel_memory_attribute +{ + kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer = + 0x0U, /*!< No write allocate, no read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteNoReadNoCacheBufferable, /*!< No write allocate, no read allocate, non-cacheable, bufferable. + */ + kEDMA_ChannelNoWriteNoReadCacheableNoBuffer, /*!< No write allocate, no read allocate, cacheable, non-bufferable. + */ + kEDMA_ChannelNoWriteNoReadCacheableBufferable, /*!< No write allocate, no read allocate, cacheable, bufferable. */ + kEDMA_ChannelNoWriteReadNoCacheNoBuffer, /*!< No write allocate, read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteReadNoCacheBufferable, /*!< No write allocate, read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelNoWriteReadCacheableNoBuffer, /*!< No write allocate, read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteReadCacheableBufferable, /*!< No write allocate, read allocate, cacheable, bufferable. */ + kEDMA_ChannelWriteNoReadNoCacheNoBuffer, /*!< write allocate, no read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelWriteNoReadNoCacheBufferable, /*!< write allocate, no read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelWriteNoReadCacheableNoBuffer, /*!< write allocate, no read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelWriteNoReadCacheableBufferable, /*!< write allocate, no read allocate, cacheable, bufferable. */ + kEDMA_ChannelWriteReadNoCacheNoBuffer, /*!< write allocate, read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelWriteReadNoCacheBufferable, /*!< write allocate, read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelWriteReadCacheableNoBuffer, /*!< write allocate, read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelWriteReadCacheableBufferable, /*!< write allocate, read allocate, cacheable, bufferable. */ +} edma_channel_memory_attribute_t; +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE +/*! @brief eDMA4 channel swap size */ +typedef enum _edma_channel_swap_size +{ + kEDMA_ChannelSwapDisabled = 0x0U, /*!< Swap is disabled. */ + kEDMA_ChannelReadWith8bitSwap = 0x1U, /*!< Swap occurs with respect to the read 8bit. */ + kEDMA_ChannelReadWith16bitSwap = 0x2U, /*!< Swap occurs with respect to the read 16bit. */ + kEDMA_ChannelReadWith32bitSwap = 0x3U, /*!< Swap occurs with respect to the read 32bit. */ + kEDMA_ChannelWriteWith8bitSwap = 0x9U, /*!< Swap occurs with respect to the write 8bit. */ + kEDMA_ChannelWriteWith16bitSwap = 0x10U, /*!< Swap occurs with respect to the write 16bit. */ + kEDMA_ChannelWriteWith32bitSwap = 0x11U, /*!< Swap occurs with respect to the write 32bit. */ +} edma_channel_swap_size_t; +#endif + +/*! @brief eDMA channel system bus information, _edma_channel_sys_bus_info*/ +enum +{ +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR) + kEDMA_AttributeOutput = DMA_CH_SBR_ATTR_MASK, /*!< DMA's AHB system bus attribute output value. */ +#endif + + kEDMA_PrivilegedAccessLevel = DMA_CH_SBR_PAL_MASK, /*!< Privileged Access Level for DMA transfers. 0b - User + protection level; 1b - Privileged protection level. */ + kEDMA_MasterId = + DMA_CH_SBR_MID_MASK, /*!< DMA's master ID when channel is active and master ID replication is enabled. */ +}; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE +/*! @brief eDMA4 channel access type */ +typedef enum _edma_channel_access_type +{ + kEDMA_ChannelDataAccess = 0x0U, /*!< Data access for eDMA4 transfers. */ + kEDMA_ChannelInstructionAccess = 0x1U, /*!< Instruction access for eDMA4 transfers. */ +} edma_channel_access_type_t; +#endif + +/*! @brief eDMA4 channel protection level */ +typedef enum _edma_channel_protection_level +{ + kEDMA_ChannelProtectionLevelUser = 0x0U, /*!< user protection level for eDMA transfers. */ + kEDMA_ChannelProtectionLevelPrivileged = 0x1U, /*!< Privileged protection level eDMA transfers. */ +} edma_channel_protection_level_t; + +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + +/*! @brief eDMA4 channel security level */ +typedef enum _edma_channel_security_level +{ + kEDMA_ChannelSecurityLevelNonSecure = 0x0U, /*!< non secure level for eDMA transfers. */ + kEDMA_ChannelSecurityLevelSecure = 0x1U, /*!< secure level for eDMA transfers. */ +} edma_channel_security_level_t; +#endif + +/*! @brief eDMA4 channel configuration*/ +typedef struct _edma_channel_config +{ + edma_channel_Preemption_config_t channelPreemptionConfig; /*!< channel preemption configuration */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE + edma_channel_memory_attribute_t channelReadMemoryAttribute; /*!< channel memory read attribute configuration */ + edma_channel_memory_attribute_t channelWriteMemoryAttribute; /*!< channel memory write attribute configuration */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE + edma_channel_swap_size_t channelSwapSize; /*!< channel swap size configuration */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE + edma_channel_access_type_t channelAccessType; /*!< channel access type configuration */ +#endif + + uint8_t channelDataSignExtensionBitPosition; /*!< channel data sign extension bit psition configuration */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + int channelRequestSource; /*!< hardware service request source for the channel */ +#endif + + bool enableMasterIDReplication; /*!< enable master ID replication */ +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + edma_channel_security_level_t securityLevel; /*!< security level */ +#endif + edma_channel_protection_level_t protectionLevel; /*!< protection level */ + +} edma_channel_config_t; +#endif + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure the scatter/gather feature as a next hardware TCD. + */ +typedef edma_core_tcd_t edma_tcd_t; + +/*! @brief edma4 channel transfer configuration + * + * The transfer configuration structure support full feature configuration of the transfer control descriptor. + * + * @note User should pay attention to the transfer size alignment limitation + * 1. the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer + * that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0 + * 2. the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width + * 3. the totalBytes should align with the bytesEachRequest + * 4. the srcAddr should align with the srcWidthOfEachTransfer + * 5. the dstAddr should align with the dstWidthOfEachTransfer + * 6. the srcAddr should align with srcAddrModulo if modulo feature is enabled + * 7. the dstAddr should align with dstAddrModulo if modulo feature is enabled + * If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error. + * + * 1.To perform a simple transfer, below members should be initialized at least + * .srcAddr - source address + * .dstAddr - destination address + * .srcWidthOfEachTransfer - data width of source address + * .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as + * srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total + * bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as + * each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination + * address as each destination write is completed enablchannelRequest - channel request can be enabled together with + * transfer configure submission + * + * 2.The transfer configuration structure also support advance feature: + * Programmable source/destination address range(MODULO) + * Programmable minor loop offset + * Programmable major loop offset + * Programmable channel chain feature + * Programmable channel transfer control descriptor link feature + * + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset value in byte unit applied to the current source + address to form the next-state value as each source read is completed */ + int16_t destOffset; /*!< Sign-extended offset value in byte unit applied to the current destination + address to form the next-state value as each destination write is completed. */ + uint32_t minorLoopBytes; /*!< bytes in each minor loop or each request + * range: 1 - (2^30 -1) when minor loop mapping is enabled + * range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor + * loop offset is enabled + * range: 1 - (2^32 - 1) when minor loop mapping is disabled + */ + uint32_t majorLoopCounts; /*!< minor loop counts in each major loop, should be 1 at least for each + * transfer range: (0 - (2^15 - 1)) when minor loop channel link is + * disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled + * total bytes in a transfer = minorLoopCountsEachMajorLoop * + * bytesEachMinorLoop + */ + + uint16_t enabledInterruptMask; /*!< channel interrupt to enable, can be OR'ed value of _edma_interrupt_enable */ + + edma_modulo_t srcAddrModulo; /*!< source circular data queue range */ + int32_t srcMajorLoopOffset; /*!< source major loop offset */ + + edma_modulo_t dstAddrModulo; /*!< destination circular data queue range */ + int32_t dstMajorLoopOffset; /*!< destination major loop offset */ + + bool enableSrcMinorLoopOffset; /*!< enable source minor loop offset */ + bool enableDstMinorLoopOffset; /*!< enable dest minor loop offset */ + int32_t minorLoopOffset; /*!< burst offset, the offset will be applied after minor loop update */ + + bool enableChannelMajorLoopLink; /*!< channel link when major loop complete */ + uint32_t majorLoopLinkChannel; /*!< major loop link channel number */ + + bool enableChannelMinorLoopLink; /*!< channel link when minor loop complete */ + uint32_t minorLoopLinkChannel; /*!< minor loop link channel number */ + + edma_tcd_t *linkTCD; /*!< pointer to the link transfer control descriptor */ +} edma_transfer_config_t; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ +#if defined FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE && FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + bool enableMasterIdReplication; /*!< Enable (true) master ID replication. If Master ID replication is disabled, the + privileged protection level (supervisor mode) for eDMA4 transfers is used. */ +#endif + + bool enableGlobalChannelLink; /*!< Enable(true) channel linking is available and controlled by each channel's link + settings. */ + + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + + bool enableDebugMode; /*!< Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of + a new channel. Executing channels are allowed to complete. */ + + bool enableRoundRobinArbitration; /*!< Enable(true) channel linking is available and controlled by each channel's + link settings. */ +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + edma_channel_config_t *channelConfig[FSL_FEATURE_EDMA_MODULE_CHANNEL]; /*!< channel preemption configuration */ +#endif +} edma_config_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define callback function for eDMA. + * + * This callback function is called in the EDMA interrupt handle. + * In normal mode, run into callback function means the transfer users need is done. + * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not + * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. + * + * @param handle EDMA handle pointer, users shall not touch the values inside. + * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to + * change in EDMA callback function. + * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter + * gather mode, this parameter shows is the current transfer block in EDMA register is done. As the + * load of core is different, it will be different if the new tcd loaded into EDMA registers while + * this callback called. If true, it always means new tcd still not loaded into registers, while + * false means new tcd already loaded into registers. + * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It + * tells user how many tcds are finished between the last callback and this. + */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + EDMA_ChannelType *channelBase; /*!< eDMA peripheral channel base address. */ +#endif + EDMA_Type *base; /*!< eDMA peripheral base address*/ + EDMA_TCDType *tcdBase; /*!< eDMA peripheral tcd base address. */ + + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint32_t channel; /*!< eDMA channel number. */ + + volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ + volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in + the memory. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ +} edma_handle_t; +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config A pointer to the configuration structure, see "edma_config_t". + * @note This function enables the minor loop map feature. + */ +void EDMA_Init(EDMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(EDMA_Type *base); + +/*! + * @brief Push content of TCD structure into hardware TCD register. + * + * @param base EDMA peripheral base address. + * @param channel EDMA channel number. + * @param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, const edma_tcd_t *tcd); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +#if defined(FSL_FEATURE_DMA_HAS_CONTINUOUS_CHANNEL_LINK) && FSL_FEATURE_DMA_HAS_CONTINUOUS_CHANNEL_LINK +/*! + * @brief Enable/Disable continuous channel link mode. + * + * @note Do not use continuous link mode with a channel linking to itself if there is only one minor loop + * iteration per service request, for example, if the channel's NBYTES value is the same as either + * the source or destination size. The same data transfer profile can be achieved by simply + * increasing the NBYTES value, which provides more efficient, faster processing. + * + * @param base EDMA peripheral base address. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableContinuousChannelLinkMode(EDMA_Type *base, bool enable) +{ + if (enable) + { + EDMA_BASE(base)->CR |= DMA_CR_CLM_MASK; + } + else + { + EDMA_BASE(base)->CR &= ~DMA_CR_CLM_MASK; + } +} +#endif + +#if defined(FSL_FEATURE_DMA_HAS_MINOR_LOOP_MAPPING) && FSL_FEATURE_DMA_HAS_MINOR_LOOP_MAPPING +/*! + * @brief Enable/Disable minor loop mapping. + * + * The TCDn.word2 is redefined to include individual enable fields, an offset field, and the + * NBYTES field. + * + * @param base EDMA peripheral base address. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableMinorLoopMapping(EDMA_Type *base, bool enable) +{ + if (enable) + { + EDMA_BASE(base)->CR |= DMA_CR_EMLM_MASK; + } + else + { + EDMA_BASE(base)->CR &= ~DMA_CR_EMLM_MASK; + } +} +#endif + +/* @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +/*! + * @brief EDMA Channel initialization + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param channelConfig pointer to user's eDMA4 channel config structure, see edma_channel_config_t for detail. + */ +void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig); + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE +/*! + * @brief Set channel memory attribute. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param writeAttribute Attributes associated with a write transaction. + * @param readAttribute Attributes associated with a read transaction. + */ +static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, + uint32_t channel, + edma_channel_memory_attribute_t writeAttribute, + edma_channel_memory_attribute_t readAttribute) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_MATTR = + DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION && FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION +/*! + * @brief Set channel sign extension. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param position A non-zero value specifing the sign extend bit position. + * If 0, sign extension is disabled. + */ +static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR = + (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SIGNEXT_MASK)) | + ((uint32_t)position << DMA_CH_CSR_SIGNEXT_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE +/*! + * @brief Set channel swap size. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param swapSize Swap occurs with respect to the specified transfer size. + * If 0, swap is disabled. + */ +static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR = + (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SWAP_MASK)) | + ((uint32_t)swapSize << DMA_CH_CSR_SWAP_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE +/*! + * @brief Set channel access type. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param channelAccessType eDMA4's transactions type on the system bus when the channel is active. + */ +static inline void EDMA_SetChannelAccessType(EDMA_Type *base, + uint32_t channel, + edma_channel_access_type_t channelAccessType) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR = + (EDMA_CHANNEL_BASE(base, channel)->CH_SBR & (~DMA_CH_SBR_INSTR_MASK)) | + ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX +/*! + * @brief Set channel request source. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param channelRequestSource eDMA hardware service request source for the channel. User need to use + * the dma_request_source_t type as the input parameter. Note that devices + * may use other enum type to express dma request source and User can fined it in + * SOC header or fsl_edma_soc.h. + */ +static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, int32_t channelRequestSource) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(base) == 1U) + { + EDMA_CHANNEL_BASE(base, channel)->CH_MUX = DMA_CH_MUX_SOURCE(channelRequestSource); + } +} +#endif + +/*! + * @brief Gets the channel identification and attribute information on the system bus interface. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of the channel system bus information. Users need to use the + * _edma_channel_sys_bus_info type to decode the return variables. + */ +static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + return EDMA_CHANNEL_BASE(base, channel)->CH_SBR; +} + +/*! + * @brief Set channel master ID replication. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (enable) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_EMI_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_EMI_MASK; + } +} + +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) +/*! + * @brief Set channel security level. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param level security level. + */ +static inline void EDMA_SetChannelSecurityLevel(EDMA_Type *base, uint32_t channel, edma_channel_security_level_t level) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (level == kEDMA_ChannelSecurityLevelSecure) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_SEC_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_SEC_MASK; + } +} +#endif + +/*! + * @brief Set channel security level. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param level security level. + */ +static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, + uint32_t channel, + edma_channel_protection_level_t level) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (level == kEDMA_ChannelProtectionLevelPrivileged) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_PAL_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_PAL_MASK; + } +} + +#endif +/*! + * @brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * @note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(EDMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type A channel link type, which can be one of the following: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->EARS &= ~((uint32_t)1U << channel); + EDMA_BASE(base)->EARS |= ((uint32_t)(true == enable ? 1U : 0U) << channel); +#else + if (enable) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EARQ_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EARQ_MASK; + } +#endif +} +#endif + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (enable) + { + EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_DREQ_MASK; + } + else + { + EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Configures the eDMA channel TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param base eDMA peripheral base address. + * @param channel edma channel number. + * @param sourceOffset source address offset will be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset); + +/* @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ +/*! + * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * @param tcd Pointer to the TCD structure. + * @param transfer channel transfer configuration pointer. + * + * @note This function enables the auto stop request feature. + */ +void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer); + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param tcd A point to the TCD structure. + * @param sourceOffset source address offset wiil be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->SERQ = DMA_SERQ_SERQ(channel); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; +#endif +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->CERQ = DMA_CERQ_CERQ(channel); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; +#endif +} + +/*! + * @brief Starts the eDMA transfer by using the software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->SSRT = DMA_SSRT_SSRT(channel); +#else + EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_START_MASK; +#endif +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Major loop count which has not been transferred yet for the current TCD. + * @note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. Users need to use the + * _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base) +{ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + return EDMA_BASE(base)->ES; +#else + return EDMA_MP_BASE(base)->MP_ES; +#endif +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * @param handle eDMA handle pointer. + * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure configurations. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param srcOffset source address offset. + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param destOffset destination address offset. + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. + */ +void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Prepares the eDMA transfer content descriptor. + * + * This function prepares the transfer content descriptor structure according to the user input. + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param srcOffset source address offset. + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param destOffset destination address offset. + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param nextTcd eDMA transfer linked TCD address. + * + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd); + +/*! + * @brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * Typical user case: + * 1. submit single transfer + * @code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 2. submit static link transfer, + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * 3. submit dynamic link transfer + * @code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 4. submit loop transfer + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, const edma_tcd_t *tcd); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief Submits the eDMA scatter gather transfer configurations. + * + * The function is target for submit loop transfer request, + * the ring transfer request means that the transfer request TAIL is link to HEAD, such as, + * A->B->C->D->A, or A->A + * + * To use the ring transfer feature, the application should allocate several transfer object, such as + * @code + * edma_channel_transfer_config_t transfer[2]; + * EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U); + * @endcode + * Then eDMA driver will link transfer[0] and transfer[1] to each other + * + * @note Application should check the return value of this function to avoid transfer request + * submit failed + * + * @param handle eDMA handle pointer + * @param transfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail + * @param transferLoopCount the count of the transfer ring, if loop count is 1, that means that the one will link to + * itself. + * + * @retval #kStatus_Success It means submit transfer request succeed + * @retval #kStatus_EDMA_Busy channel is in busy status + * @retval #kStatus_InvalidArgument Invalid Argument + */ +status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount); + +/*! + * @brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief Get unused TCD slot number. + * + * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0. + * + * @param handle DMA handle pointer. + * @return The unused tcd slot number. + */ +static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) +{ + int8_t tmpTcdSize = handle->tcdSize; + int8_t tmpTcdUsed = handle->tcdUsed; + return ((uint32_t)tmpTcdSize - (uint32_t)tmpTcdUsed); +} + +/*! + * @brief Get the next tcd address. + * + * This function gets the next tcd address. If this is last TCD, return 0. + * + * @param handle DMA handle pointer. + * @return The next TCD address. + */ +static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) +{ + return (uint32_t)(handle->tcdBase->DLAST_SGA); +} + +/*! + * @brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*FSL_EDMA_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_core.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_core.h new file mode 100644 index 0000000000..e76840e4ee --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_core.h @@ -0,0 +1,299 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_EDMA_CORE_H_ +#define FSL_EDMA_CORE_H_ + +#include "fsl_edma_soc.h" + +/*! + * @addtogroup edma_core + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4 +#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK +#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK +#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK +#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK +#define DMA_CSR_BWC_MASK DMA_TCD_CSR_BWC_MASK +#define DMA_CSR_BWC(x) DMA_TCD_CSR_BWC(x) +#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK +#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK +#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK +#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT +#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK +#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT +#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK +#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK +#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK +#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK +#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK +#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK +#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK +#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK +#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK +#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x) +#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X) +#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x) +#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) +#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x) +#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x) +#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x) +#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x) +#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x) +#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x) +#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK +#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT +#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK +#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT +#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK +#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT +#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x) +#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \ + (!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4)) +#define DMA_CSR_INTMAJOR_MASK DMA_TCD_CSR_INTMAJOR_MASK +#define DMA_CSR_INTHALF_MASK DMA_TCD_CSR_INTHALF_MASK +#define DMA_CSR_DREQ_MASK DMA_TCD_CSR_DREQ_MASK +#define DMA_CSR_ESG_MASK DMA_TCD_CSR_ESG_MASK +#define DMA_CSR_BWC_MASK DMA_TCD_CSR_BWC_MASK +#define DMA_CSR_BWC(x) DMA_TCD_CSR_BWC(x) +#define DMA_CSR_START_MASK DMA_TCD_CSR_START_MASK +#define DMA_CITER_ELINKNO_CITER_MASK DMA_TCD_CITER_ELINKNO_CITER_MASK +#define DMA_BITER_ELINKNO_BITER_MASK DMA_TCD_BITER_ELINKNO_BITER_MASK +#define DMA_CITER_ELINKNO_CITER_SHIFT DMA_TCD_CITER_ELINKNO_CITER_SHIFT +#define DMA_CITER_ELINKYES_CITER_MASK DMA_TCD_CITER_ELINKYES_CITER_MASK +#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT +#define DMA_ATTR_SMOD_MASK DMA_TCD_ATTR_SMOD_MASK +#define DMA_ATTR_DMOD_MASK DMA_TCD_ATTR_DMOD_MASK +#define DMA_CITER_ELINKNO_ELINK_MASK DMA_TCD_CITER_ELINKNO_ELINK_MASK +#define DMA_CSR_MAJORELINK_MASK DMA_TCD_CSR_MAJORELINK_MASK +#define DMA_BITER_ELINKYES_ELINK_MASK DMA_TCD_BITER_ELINKYES_ELINK_MASK +#define DMA_CITER_ELINKYES_ELINK_MASK DMA_TCD_CITER_ELINKYES_ELINK_MASK +#define DMA_CSR_MAJORLINKCH_MASK DMA_TCD_CSR_MAJORLINKCH_MASK +#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK +#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK +#define DMA_ATTR_DMOD(x) DMA_TCD_ATTR_DMOD(x) +#define DMA_ATTR_SMOD(X) DMA_TCD_ATTR_SMOD(X) +#define DMA_BITER_ELINKYES_LINKCH(x) DMA_TCD_BITER_ELINKYES_LINKCH(x) +#define DMA_CITER_ELINKYES_LINKCH(x) DMA_TCD_CITER_ELINKYES_LINKCH(x) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) +#define DMA_ATTR_DSIZE(x) DMA_TCD_ATTR_DSIZE(x) +#define DMA_ATTR_SSIZE(x) DMA_TCD_ATTR_SSIZE(x) +#define DMA_CSR_DREQ(x) DMA_TCD_CSR_DREQ(x) +#define DMA_CSR_MAJORLINKCH(x) DMA_TCD_CSR_MAJORLINKCH(x) +#define DMA_CH_MUX_SOURCE(x) DMA_CH_MUX_SRC(x) +#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \ + (!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3)) +#define DMA_CSR_INTMAJOR_MASK DMA4_CSR_INTMAJOR_MASK +#define DMA_CSR_INTHALF_MASK DMA4_CSR_INTHALF_MASK +#define DMA_CSR_DREQ_MASK DMA4_CSR_DREQ_MASK +#define DMA_CSR_ESG_MASK DMA4_CSR_ESG_MASK +#define DMA_CSR_BWC_MASK DMA4_CSR_BWC_MASK +#define DMA_CSR_BWC(x) DMA4_CSR_BWC(x) +#define DMA_CSR_START_MASK DMA4_CSR_START_MASK +#define DMA_CITER_ELINKNO_CITER_MASK DMA4_CITER_ELINKNO_CITER_MASK +#define DMA_BITER_ELINKNO_BITER_MASK DMA4_BITER_ELINKNO_BITER_MASK +#define DMA_CITER_ELINKNO_CITER_SHIFT DMA4_CITER_ELINKNO_CITER_SHIFT +#define DMA_CITER_ELINKYES_CITER_MASK DMA4_CITER_ELINKYES_CITER_MASK +#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT +#define DMA_ATTR_SMOD_MASK DMA4_ATTR_SMOD_MASK +#define DMA_ATTR_DMOD_MASK DMA4_ATTR_DMOD_MASK +#define DMA_CITER_ELINKNO_ELINK_MASK DMA4_CITER_ELINKNO_ELINK_MASK +#define DMA_CSR_MAJORELINK_MASK DMA4_CSR_MAJORELINK_MASK +#define DMA_BITER_ELINKYES_ELINK_MASK DMA4_BITER_ELINKYES_ELINK_MASK +#define DMA_CITER_ELINKYES_ELINK_MASK DMA4_CITER_ELINKYES_ELINK_MASK +#define DMA_CSR_MAJORLINKCH_MASK DMA4_CSR_MAJORLINKCH_MASK +#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK +#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK +#define DMA_ATTR_DMOD(x) DMA4_ATTR_DMOD(x) +#define DMA_ATTR_SMOD(X) DMA4_ATTR_SMOD(X) +#define DMA_BITER_ELINKYES_LINKCH(x) DMA4_BITER_ELINKYES_LINKCH(x) +#define DMA_CITER_ELINKYES_LINKCH(x) DMA4_CITER_ELINKYES_LINKCH(x) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) DMA4_NBYTES_MLOFFYES_MLOFF(x) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) DMA4_NBYTES_MLOFFYES_DMLOE(x) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) DMA4_NBYTES_MLOFFYES_SMLOE(x) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) DMA4_NBYTES_MLOFFNO_NBYTES(x) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) DMA4_NBYTES_MLOFFYES_NBYTES(x) +#define DMA_ATTR_DSIZE(x) DMA4_ATTR_DSIZE(x) +#define DMA_ATTR_SSIZE(x) DMA4_ATTR_SSIZE(x) +#define DMA_CSR_DREQ(x) DMA4_CSR_DREQ(x) +#define DMA_CSR_MAJORLINKCH(x) DMA4_CSR_MAJORLINKCH(x) +#define DMA_CH_MATTR_WCACHE(x) DMA4_CH_MATTR_WCACHE(x) +#define DMA_CH_MATTR_RCACHE(x) DMA4_CH_MATTR_RCACHE(x) +#define DMA_CH_CSR_SIGNEXT_MASK DMA4_CH_CSR_SIGNEXT_MASK +#define DMA_CH_CSR_SIGNEXT_SHIFT DMA4_CH_CSR_SIGNEXT_SHIFT +#define DMA_CH_CSR_SWAP_MASK DMA4_CH_CSR_SWAP_MASK +#define DMA_CH_CSR_SWAP_SHIFT DMA4_CH_CSR_SWAP_SHIFT +#define DMA_CH_SBR_INSTR_MASK DMA4_CH_SBR_INSTR_MASK +#define DMA_CH_SBR_INSTR_SHIFT DMA4_CH_SBR_INSTR_SHIFT +#define DMA_CH_MUX_SOURCE(x) DMA4_CH_MUX_SRC(x) +#define DMA_CH_CSR_DONE_MASK DMA4_CH_CSR_DONE_MASK +#define DMA_CH_CSR_ERQ_MASK DMA4_CH_CSR_ERQ_MASK +#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA +/*! intentional empty */ +#endif + +/*! @brief DMA error flag */ +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA +#define DMA_ERR_DBE_FLAG DMA_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK +#define DMA_ERR_CPE_FLAG DMA_ES_CPE_MASK +#define DMA_ERR_ECX_FLAG DMA_ES_ECX_MASK +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) +#define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK +#endif +#define DMA_ERR_FLAG DMA_ES_VLD_MASK + +/*! @brief get/clear DONE status*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT) +/*! @brief enable/disable error interrupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (base->EEI |= ((uint32_t)0x1U << channel)) +#define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel))) +/*! @brief get/clear error status*/ +#define DMA_GET_ERROR_STATUS(base, channel) (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U) +#define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel) +/*! @brief get/clear int status*/ +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U)) +#define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel) + +#else + +#define DMA_ERR_DBE_FLAG DMA_MP_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_MP_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_MP_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_MP_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_MP_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_MP_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_MP_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_MP_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_MP_ES_ERRCHN_MASK +#define DMA_ERR_ECX_FLAG DMA_MP_ES_ECX_MASK +#define DMA_ERR_FLAG DMA_MP_ES_VLD_MASK + +/*! @brief get/clear DONE bit*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT) +/*! @brief enable/disable error interupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK) +#define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK) +/*! @brief get/clear error status*/ +#define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK) +#define DMA_GET_ERROR_STATUS(base, channel) \ + (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U) +/*! @brief get/clear INT status*/ +#define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK) +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U)) +#endif /*FSL_EDMA_SOC_IP_EDMA*/ + +/*! @brief enable/dsiable MAJOR/HALF INT*/ +#define DMA_ENABLE_MAJOR_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTMAJOR_MASK) +#define DMA_ENABLE_HALF_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTHALF_MASK) +#define DMA_DISABLE_MAJOR_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK) +#define DMA_DISABLE_HALF_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK) + +/*!@brief EDMA tcd align size */ +#define EDMA_TCD_ALIGN_SIZE (32U) + +/*!@brief edma core channel struture definition */ +typedef struct _edma_core_mp +{ + __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t MP_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ +} edma_core_mp_t; + +/*!@brief edma core channel struture definition */ +typedef struct _edma_core_channel +{ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */ + __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ +} edma_core_channel_t; + +/*!@brief edma core TCD struture definition */ +typedef struct _edma_core_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma_core_tcd_t; + +/*!@brief EDMA typedef */ +typedef edma_core_channel_t EDMA_ChannelType; +typedef edma_core_tcd_t EDMA_TCDType; +typedef void EDMA_Type; + +/*!@brief EDMA base address convert macro */ +#define EDMA_BASE(base) +#define EDMA_CHANNEL_BASE(base, channel) \ + ((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base))) +#define EDMA_TCD_BASE(base, channel) \ + ((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U)) +#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base))) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* FSL_EDMA_CORE_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_soc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_soc.c new file mode 100644 index 0000000000..2706eb37ec --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_soc.c @@ -0,0 +1,289 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma_soc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma_soc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void EDMA_0_CH0_DriverIRQHandler(void); +extern void EDMA_0_CH1_DriverIRQHandler(void); +extern void EDMA_0_CH2_DriverIRQHandler(void); +extern void EDMA_0_CH3_DriverIRQHandler(void); +extern void EDMA_0_CH4_DriverIRQHandler(void); +extern void EDMA_0_CH5_DriverIRQHandler(void); +extern void EDMA_0_CH6_DriverIRQHandler(void); +extern void EDMA_0_CH7_DriverIRQHandler(void); +extern void EDMA_0_CH8_DriverIRQHandler(void); +extern void EDMA_0_CH9_DriverIRQHandler(void); +extern void EDMA_0_CH10_DriverIRQHandler(void); +extern void EDMA_0_CH11_DriverIRQHandler(void); +extern void EDMA_0_CH12_DriverIRQHandler(void); +extern void EDMA_0_CH13_DriverIRQHandler(void); +extern void EDMA_0_CH14_DriverIRQHandler(void); +extern void EDMA_0_CH15_DriverIRQHandler(void); +extern void EDMA_1_CH0_DriverIRQHandler(void); +extern void EDMA_1_CH1_DriverIRQHandler(void); +extern void EDMA_1_CH2_DriverIRQHandler(void); +extern void EDMA_1_CH3_DriverIRQHandler(void); +extern void EDMA_1_CH4_DriverIRQHandler(void); +extern void EDMA_1_CH5_DriverIRQHandler(void); +extern void EDMA_1_CH6_DriverIRQHandler(void); +extern void EDMA_1_CH7_DriverIRQHandler(void); +extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief DMA instance 0, channel 0 IRQ handler. + * + */ +void EDMA_0_CH0_DriverIRQHandler(void) +{ + /* Instance 0 channel 0 */ + EDMA_DriverIRQHandler(0U, 0U); +} + +/*! + * brief DMA instance 0, channel 1 IRQ handler. + * + */ +void EDMA_0_CH1_DriverIRQHandler(void) +{ + /* Instance 0 channel 1 */ + EDMA_DriverIRQHandler(0U, 1U); +} + +/*! + * brief DMA instance 0, channel 2 IRQ handler. + * + */ +void EDMA_0_CH2_DriverIRQHandler(void) +{ + /* Instance 0 channel 2 */ + EDMA_DriverIRQHandler(0U, 2U); +} + +/*! + * brief DMA instance 0, channel 3 IRQ handler. + * + */ +void EDMA_0_CH3_DriverIRQHandler(void) +{ + /* Instance 0 channel 3 */ + EDMA_DriverIRQHandler(0U, 3U); +} + +/*! + * brief DMA instance 0, channel 4 IRQ handler. + * + */ +void EDMA_0_CH4_DriverIRQHandler(void) +{ + /* Instance 0 channel 4 */ + EDMA_DriverIRQHandler(0U, 4U); +} + +/*! + * brief DMA instance 0, channel 5 IRQ handler. + * + */ +void EDMA_0_CH5_DriverIRQHandler(void) +{ + /* Instance 0 channel 5 */ + EDMA_DriverIRQHandler(0U, 5U); +} + +/*! + * brief DMA instance 0, channel 6 IRQ handler. + * + */ +void EDMA_0_CH6_DriverIRQHandler(void) +{ + /* Instance 0 channel 6 */ + EDMA_DriverIRQHandler(0U, 6U); +} + +/*! + * brief DMA instance 0, channel 7 IRQ handler. + * + */ +void EDMA_0_CH7_DriverIRQHandler(void) +{ + /* Instance 0 channel 7 */ + EDMA_DriverIRQHandler(0U, 7U); +} + +/*! + * brief DMA instance 0, channel 8 IRQ handler. + * + */ +void EDMA_0_CH8_DriverIRQHandler(void) +{ + /* Instance 0 channel 8 */ + EDMA_DriverIRQHandler(0U, 8U); +} + +/*! + * brief DMA instance 0, channel 9 IRQ handler. + * + */ +void EDMA_0_CH9_DriverIRQHandler(void) +{ + /* Instance 0 channel 9 */ + EDMA_DriverIRQHandler(0U, 9U); +} + +/*! + * brief DMA instance 0, channel 10 IRQ handler. + * + */ +void EDMA_0_CH10_DriverIRQHandler(void) +{ + /* Instance 0 channel 10 */ + EDMA_DriverIRQHandler(0U, 10U); +} + +/*! + * brief DMA instance 0, channel 11 IRQ handler. + * + */ +void EDMA_0_CH11_DriverIRQHandler(void) +{ + /* Instance 0 channel 11 */ + EDMA_DriverIRQHandler(0U, 11U); +} + +/*! + * brief DMA instance 0, channel 12 IRQ handler. + * + */ +void EDMA_0_CH12_DriverIRQHandler(void) +{ + /* Instance 0 channel 12 */ + EDMA_DriverIRQHandler(0U, 12U); +} + +/*! + * brief DMA instance 0, channel 13 IRQ handler. + * + */ +void EDMA_0_CH13_DriverIRQHandler(void) +{ + /* Instance 0 channel 13 */ + EDMA_DriverIRQHandler(0U, 13U); +} + +/*! + * brief DMA instance 0, channel 14 IRQ handler. + * + */ +void EDMA_0_CH14_DriverIRQHandler(void) +{ + /* Instance 0 channel 14 */ + EDMA_DriverIRQHandler(0U, 14U); +} + +/*! + * brief DMA instance 0, channel 15 IRQ handler. + * + */ +void EDMA_0_CH15_DriverIRQHandler(void) +{ + /* Instance 0 channel 15 */ + EDMA_DriverIRQHandler(0U, 15U); +} + +/*! + * brief DMA instance 1, channel 0 IRQ handler. + * + */ +void EDMA_1_CH0_DriverIRQHandler(void) +{ + /* Instance 1 channel 0 */ + EDMA_DriverIRQHandler(1U, 0U); +} + +/*! + * brief DMA instance 1, channel 1 IRQ handler. + * + */ +void EDMA_1_CH1_DriverIRQHandler(void) +{ + /* Instance 1 channel 1 */ + EDMA_DriverIRQHandler(1U, 1U); +} + +/*! + * brief DMA instance 1, channel 2 IRQ handler. + * + */ +void EDMA_1_CH2_DriverIRQHandler(void) +{ + /* Instance 1 channel 2 */ + EDMA_DriverIRQHandler(1U, 2U); +} + +/*! + * brief DMA instance 1, channel 3 IRQ handler. + * + */ +void EDMA_1_CH3_DriverIRQHandler(void) +{ + /* Instance 1 channel 3 */ + EDMA_DriverIRQHandler(1U, 3U); +} + +/*! + * brief DMA instance 1, channel 4 IRQ handler. + * + */ +void EDMA_1_CH4_DriverIRQHandler(void) +{ + /* Instance 1 channel 4 */ + EDMA_DriverIRQHandler(1U, 4U); +} + +/*! + * brief DMA instance 1, channel 5 IRQ handler. + * + */ +void EDMA_1_CH5_DriverIRQHandler(void) +{ + /* Instance 1 channel 5 */ + EDMA_DriverIRQHandler(1U, 5U); +} + +/*! + * brief DMA instance 1, channel 6 IRQ handler. + * + */ +void EDMA_1_CH6_DriverIRQHandler(void) +{ + /* Instance 1 channel 6 */ + EDMA_DriverIRQHandler(1U, 6U); +} + +/*! + * brief DMA instance 1, channel 7 IRQ handler. + * + */ +void EDMA_1_CH7_DriverIRQHandler(void) +{ + /* Instance 1 channel 7 */ + EDMA_DriverIRQHandler(1U, 7U); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_soc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_soc.h new file mode 100644 index 0000000000..863542cff4 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_edma_soc.h @@ -0,0 +1,68 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_EDMA_SOC_H_ +#define _FSL_EDMA_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 1.0.0. */ +#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/*!@brief DMA IP version */ +#define FSL_EDMA_SOC_IP_DMA3 (1) +#define FSL_EDMA_SOC_IP_DMA4 (0) + +/*!@brief DMA base table */ +#define EDMA_BASE_PTRS \ + { \ + DMA0, DMA1 \ + } + +#define EDMA_CHN_IRQS \ + { \ + {EDMA_0_CH0_IRQn, EDMA_0_CH1_IRQn, EDMA_0_CH2_IRQn, EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn, EDMA_0_CH5_IRQn, \ + EDMA_0_CH6_IRQn, EDMA_0_CH7_IRQn, EDMA_0_CH8_IRQn, EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, \ + EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn}, \ + { \ + EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn, \ + EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, \ + NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn \ + } \ + } + +/*!@brief EDMA base address convert macro */ +#define EDMA_CHANNEL_OFFSET 0x1000U +#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_EDMA_SOC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_eim.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_eim.c new file mode 100644 index 0000000000..bae11683f4 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_eim.c @@ -0,0 +1,312 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_eim.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.eim" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to EIM bases for each instance. */ +static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to EIM clocks for each instance. */ +static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EIM_GetInstance(EIM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_eimBases); instance++) + { + if (s_eimBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_eimBases)); + + return instance; +} + +/*! + * brief EIM module initialization function. + * + * param base EIM base address. + */ +void EIM_Init(EIM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EIM clock. */ + CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->EIMCR = 0x00U; + base->EICHEN = 0x00U; +} + +/*! + * brief Deinitializes the EIM. + * + */ +void EIM_Deinit(EIM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EIM clock. */ + CLOCK_DisableClock(s_eimClocks[EIM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) +{ + switch ((uint8_t)channel) + { + case 0U: + base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask); + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask); + break; +#endif + +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask); + break; +#endif + default: + assert(NULL); + break; + } +} + +uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel) +{ + uint8_t mask = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT); + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif + default: + assert(NULL); + break; + } + + return mask; +} + +void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) +{ + switch ((uint8_t)channel) + { + case 0U: + base->EICHD0_WORD1 = mask; + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + base->EICHD1_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + base->EICHD2_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case kEIM_MemoryChannelRAMC: + base->EICHD3_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case kEIM_MemoryChannelRAMD: + base->EICHD4_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case kEIM_MemoryChannelRAME: + base->EICHD5_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case kEIM_MemoryChannelRAMF: + base->EICHD6_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case kEIM_MemoryChannelLPCACRAM: + base->EICHD7_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case kEIM_MemoryChannelPKCRAM: + base->EICHD8_WORD1 = mask; + break; +#endif + default: + assert(NULL); + break; + } +} + +uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel) +{ + uint32_t mask = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT; + break; + +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return mask; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_eim.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_eim.h new file mode 100644 index 0000000000..4594136c10 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_eim.h @@ -0,0 +1,144 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EIM_H_ +#define FSL_EIM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup eim + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version. */ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*@}*/ + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief EIM module initialization function. + * + * @param base EIM base address. + */ +void EIM_Init(EIM_Type *base); + +/*! + * @brief De-initializes the EIM. + * + */ +void EIM_Deinit(EIM_Type *base); + +/* @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief EIM module enable global error injection. + * + * @param base EIM base address. + * @param mask The interrupts to enable. + */ +static inline void EIM_EnableGlobalErrorInjection(EIM_Type *base, bool enable) +{ + if (enable) + { + base->EIMCR = EIM_EIMCR_GEIEN_MASK; + } + else + { + base->EIMCR = ~EIM_EIMCR_GEIEN_MASK; + } +} + +/*! + * @brief EIM module enable error injection for memory channel n, this function enables the corresponding error + * injection channel. The Global Error Injection Enable function must also be called to enable error injection. + * + * @param base EIM base address. + * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration. + */ +static inline void EIM_EnableErrorInjectionChannels(EIM_Type *base, uint32_t mask) +{ + base->EICHEN |= mask; +} + +/*! + * @brief EIM module disable error injection for memory channel n. + * + * @param base EIM base address. + * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration. + */ +static inline void EIM_DisableErrorInjectionChannels(EIM_Type *base, uint32_t mask) +{ + base->EICHEN &= ~mask; +} + +/*! + * @brief EIM module inject checkbit error for memory channel n, an attempt to invert more than 2 bits in one operation + * might result in undefined behavior. + * + * @param base EIM base address. + * @param channel memory channel. + * @param mask The interrupts to enable. + */ +void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask); + +/*! + * @brief EIM module get checkbit mask for memory channel n. + * + * @param base EIM base address. + * @param channel memory channel. + * @retval return checkbit mask. + */ +uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel); + +/*! + * @brief EIM module inject databit error for memory channel n, an attempt to invert more than 2 bits in one operation + * might result in undefined behavior. + * + * @param base EIM base address. + * @param channel memory channel. + * @param mask The interrupts to enable. + */ +void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask); + +/*! + * @brief EIM module get databit mask for memory channel n. + * + * @param base EIM base address. + * @param channel memory channel. + * @retval return checkbit mask. + */ +uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_erm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_erm.c new file mode 100644 index 0000000000..cdd35b56b0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_erm.c @@ -0,0 +1,317 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_erm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.erm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ERM bases for each instance. */ +static ERM_Type *const s_ermBases[] = ERM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ERM clocks for each instance. */ +static const clock_ip_name_t s_ermClocks[] = ERM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ERM_GetInstance(ERM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ermBases); instance++) + { + if (s_ermBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ermBases)); + + return instance; +} + +/*! + * brief ERM module initialization function. + * + * param base ERM base address. + */ +void ERM_Init(ERM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ERM clock. */ + CLOCK_EnableClock(s_ermClocks[ERM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CR0 = 0x00U; +#ifdef ERM_CR1_ENCIE8_MASK + base->CR1 = 0x00U; +#endif + base->SR0 = 0xFFFFFFFFU; +#ifdef ERM_SR1_SBC8_MASK + base->SR1 = 0xFFFFFFFFU; +#endif +} + +/*! + * brief Deinitializes the ERM. + * + */ +void ERM_Deinit(ERM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ERM clock. */ + CLOCK_DisableClock(s_ermClocks[ERM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t absoluteErrorAddress = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + absoluteErrorAddress = base->EAR0; + break; +#ifdef ERM_EAR1_EAR_MASK + case 1U: + absoluteErrorAddress = base->EAR1; + break; +#endif +#ifdef ERM_EAR2_EAR_MASK + case 2U: + absoluteErrorAddress = base->EAR2; + break; +#endif +#ifdef ERM_EAR3_EAR_MASK + case 3U: + absoluteErrorAddress = base->EAR3; + break; +#endif +#ifdef ERM_EAR4_EAR_MASK + case 4U: + absoluteErrorAddress = base->EAR4; + break; +#endif +#ifdef ERM_EAR5_EAR_MASK + case 5U: + absoluteErrorAddress = base->EAR5; + break; +#endif +#ifdef ERM_EAR6_EAR_MASK + case 6U: + absoluteErrorAddress = base->EAR6; + break; +#endif + default: + assert(NULL); + break; + } + + return absoluteErrorAddress; +} + +uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t syndrome = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT; + break; +#ifdef ERM_SYN1_SYNDROME_MASK + case 1U: + syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN2_SYNDROME_MASK + case 2U: + syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN3_SYNDROME_MASK + case 3U: + syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN4_SYNDROME_MASK + case 4U: + syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN5_SYNDROME_MASK + case 5U: + syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN6_SYNDROME_MASK + case 6U: + syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN7_SYNDROME_MASK + case 7U: + syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN8_SYNDROME_MASK + case 8U: + syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN9_SYNDROME_MASK + case 8U: + syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return syndrome; +} + +uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t count = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT; + break; +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: + count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: + count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: + count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: + count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: + count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: + count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT7_COUNT_MASK + case 7U: + count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: + count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: + count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return count; +} + +void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel) +{ + switch ((uint8_t)channel) + { + case 0U: + base->CORR_ERR_CNT0 = 0x00U; + break; + +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: + base->CORR_ERR_CNT1 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: + base->CORR_ERR_CNT2 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: + base->CORR_ERR_CNT3 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: + base->CORR_ERR_CNT4 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: + base->CORR_ERR_CNT5 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: + base->CORR_ERR_CNT6 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 7U: + base->CORR_ERR_CNT7 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: + base->CORR_ERR_CNT8 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: + base->CORR_ERR_CNT9 = 0x00U; + break; +#endif + default: + assert(NULL); + break; + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_erm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_erm.h new file mode 100644 index 0000000000..c199e74b0e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_erm.h @@ -0,0 +1,235 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_ERM_H_ +#define FSL_ERM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup erm + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version. */ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*@}*/ + +/*! + * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable. + * + * This structure contains the settings for all of the ERM interrupt configurations. + */ +enum +{ + kERM_SingleCorrectionIntEnable = 0x08U, /*!< Single Correction Interrupt Notification enable.*/ + kERM_NonCorrectableIntEnable = 0x04U, /*!< Non-Correction Interrupt Notification enable.*/ + + kERM_AllInterruptsEnable = 0xFFFFFFFFUL, /*!< All Interrupts enable */ +}; + +/*! + * @brief ERM interrupt status, _erm_interrupt_flag. + * + * This provides constants for the ERM event status for use in the ERM functions. + */ +enum +{ + kERM_SingleBitCorrectionIntFlag = 0x08U, /*!< Single-Bit Correction Event.*/ + kERM_NonCorrectableErrorIntFlag = 0x04U, /*!< Non-Correctable Error Event.*/ + + kERM_AllIntsFlag = 0xFFFFFFFFUL, /*!< All Events. */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief ERM module initialization function. + * + * @param base ERM base address. + */ +void ERM_Init(ERM_Type *base); + +/*! + * @brief De-initializes the ERM. + * + */ +void ERM_Deinit(ERM_Type *base); + +/* @} */ + +/*! + * @name Interrupt + * @{ + */ +/*! + * @brief ERM enable interrupts. + * + * @param base ERM peripheral base address. + * @param channel memory channel. + * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region. + * Refer to "_erm_interrupt_enable" enumeration. + */ +static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + uint32_t temp = 0x00U; + if ((uint32_t)channel <= 0x07U) + { + temp = base->CR0; + base->CR0 = + (temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U)); + } +#ifdef ERM_CR1_ESCIE8_MASK + else + { + temp = base->CR1; + base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) | + (mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#endif +} + +/*! + * @brief ERM module disable interrupts. + * + * @param base ERM base address. + * @param channel memory channel. + * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region. + * Refer to "_erm_interrupt_enable" enumeration. + */ +static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + if ((uint32_t)channel <= 0x07U) + { + base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U)); + } +#ifdef ERM_CR1_ESCIE8_MASK + else + { + base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#endif +} + +/*! + * @brief Gets ERM interrupt flags. + * + * @param base ERM peripheral base address. + * @return ERM event flags. + */ +static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel_t channel) +{ + if ((uint32_t)channel <= 0x07U) + { + return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U); + } +#ifdef ERM_SR1_SBC8_MASK + else + { + return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#else + { + return 0; + } +#endif +} + +/*! + * @brief ERM module clear interrupt status flag. + * + * @param base ERM base address. + * @param mask event flag to clear. Refer to "_erm_interrupt_flag" enumeration. + */ +static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + if ((uint32_t)channel <= 0x07U) + { + base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U); + } +#ifdef ERM_SR1_SBC8_MASK + else + { + base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U); + } +#endif +} + +/* @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval memory error absolute address. + */ + +uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM get syndrome, which identifies the pertinent bit position on a correctable, single-bit data inversion or a + * non-correctable, single-bit address inversion. The syndrome value does not provide any additional diagnostic + * information on non-correctable, multi-bit inversions. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval syndrome value. + */ +uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM get error count, which records the count value of the number of correctable ECC error events for Memory + * n. Non-correctable errors are considered a serious fault, so the ERM does not provide any mechanism to count + * non-correctable errors. Only correctable errors are counted. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval error count. + */ +uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM reset error count. + * + * @param base ERM base address. + * @param channel memory channel. + */ +void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_evtg.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_evtg.c new file mode 100644 index 0000000000..7402c428d3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_evtg.c @@ -0,0 +1,418 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_evtg.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.evtg" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize EVTG with a user configuration structure. + * + * param base EVTG base address. + * param evtgIndex EVTG instance index. + * param psConfig EVTG initial configuration structure pointer. + */ +void EVTG_Init(EVTG_Type *base, evtg_index_t evtgIndex, evtg_config_t *psConfig) +{ + /* Configure Flip-Flop as expected mode. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL = EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL((uint16_t)psConfig->flipflopMode); + + if (kEVTG_FFModeJKFF == psConfig->flipflopMode) + { + /* When FF Mode is configured as JK-FF mode, need EVTG_OUTA feedback to EVTG input and replace one of the four + * inputs.*/ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= + EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD((uint16_t)psConfig->outfdbkOverideinput); + } + + if (psConfig->enableFlipflopInitOutput == true) + { + EVTG_ForceFlipflopInitOutput(base, evtgIndex, psConfig->flipflopInitOutputValue); + } + +#if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS( + ((uint16_t)psConfig->enableForceBypassFlipFlopAOI1 << 1U) | (uint16_t)psConfig->enableForceBypassFlipFlopAOI0); +#endif + + /* Configure EVTG input sync. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL( + (((uint16_t)psConfig->enableInputDSync << 3U) | ((uint16_t)psConfig->enableInputCSync << 2U) | + ((uint16_t)psConfig->enableInputBSync << 1U) | ((uint16_t)psConfig->enableInputASync))); + + /* Configure AOI0. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 = + (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC((uint8_t)psConfig->aoi0Config.productTerm0.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC((uint8_t)psConfig->aoi0Config.productTerm0.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC((uint8_t)psConfig->aoi0Config.productTerm0.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC((uint8_t)psConfig->aoi0Config.productTerm0.dInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC((uint8_t)psConfig->aoi0Config.productTerm1.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC((uint8_t)psConfig->aoi0Config.productTerm1.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC((uint8_t)psConfig->aoi0Config.productTerm1.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC((uint8_t)psConfig->aoi0Config.productTerm1.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 = + (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC((uint8_t)psConfig->aoi0Config.productTerm2.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC((uint8_t)psConfig->aoi0Config.productTerm2.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC((uint8_t)psConfig->aoi0Config.productTerm2.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC((uint8_t)psConfig->aoi0Config.productTerm2.dInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC((uint8_t)psConfig->aoi0Config.productTerm3.aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC((uint8_t)psConfig->aoi0Config.productTerm3.bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC((uint8_t)psConfig->aoi0Config.productTerm3.cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC((uint8_t)psConfig->aoi0Config.productTerm3.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_FILT |= + (EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT((uint16_t)psConfig->aoi0Config.aoiOutFilterConfig.sampleCount) | + EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(psConfig->aoi0Config.aoiOutFilterConfig.samplePeriod)); + + /* Configure AOI1. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 = + (EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC((uint8_t)psConfig->aoi1Config.productTerm0.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC((uint8_t)psConfig->aoi1Config.productTerm0.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC((uint8_t)psConfig->aoi1Config.productTerm0.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC((uint8_t)psConfig->aoi1Config.productTerm0.dInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC((uint8_t)psConfig->aoi1Config.productTerm1.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC((uint8_t)psConfig->aoi1Config.productTerm1.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC((uint8_t)psConfig->aoi1Config.productTerm1.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC((uint8_t)psConfig->aoi1Config.productTerm1.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 = + (EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC((uint8_t)psConfig->aoi1Config.productTerm2.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC((uint8_t)psConfig->aoi1Config.productTerm2.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC((uint8_t)psConfig->aoi1Config.productTerm2.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC((uint8_t)psConfig->aoi1Config.productTerm2.dInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC((uint8_t)psConfig->aoi1Config.productTerm3.aInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC((uint8_t)psConfig->aoi1Config.productTerm3.bInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC((uint8_t)psConfig->aoi1Config.productTerm3.cInput) | + EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC((uint8_t)psConfig->aoi1Config.productTerm3.dInput)); + + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_FILT |= + (EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT((uint16_t)psConfig->aoi1Config.aoiOutFilterConfig.sampleCount) | + EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(psConfig->aoi1Config.aoiOutFilterConfig.samplePeriod)); +} + +/*! + * brief Configure AOI product term by initializing the product term + * configuration structure. + * + * param base EVTG base address. + * param evtgIndex EVTG instance index. + * param aoiIndex EVTG AOI index. see enum ref evtg_aoi_index_t + * param productTerm EVTG AOI product term index. + * param psProductTermConfig Pointer to EVTG product term configuration structure. + * see ref _evtg_product_term_config + */ +void EVTG_ConfigAOIProductTerm(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_aoi_index_t aoiIndex, + evtg_aoi_product_term_t productTerm, + evtg_aoi_product_term_config_t *psProductTermConfig) +{ + volatile uint16_t *pu16AOIPT01Config; + volatile uint16_t *pu16AOIPT23Config; + + if (kEVTG_AOI0 == aoiIndex) + { + pu16AOIPT01Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01; + pu16AOIPT23Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23; + } + else + { + pu16AOIPT01Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01; + pu16AOIPT23Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23; + } + + if (kEVTG_ProductTerm0 == productTerm) + { + *pu16AOIPT01Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK); + *pu16AOIPT01Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC((uint8_t)psProductTermConfig->dInput)); + } + else if (kEVTG_ProductTerm1 == productTerm) + { + *pu16AOIPT01Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK); + *pu16AOIPT01Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC((uint8_t)psProductTermConfig->dInput)); + } + else if (kEVTG_ProductTerm2 == productTerm) + { + *pu16AOIPT23Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK); + *pu16AOIPT23Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC((uint8_t)psProductTermConfig->dInput)); + } + else + { + *pu16AOIPT23Config &= + ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK); + *pu16AOIPT23Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC((uint8_t)psProductTermConfig->aInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC((uint8_t)psProductTermConfig->bInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC((uint8_t)psProductTermConfig->cInput) | + EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC((uint8_t)psProductTermConfig->dInput)); + } +} + +/*! + * @brief Loads default values to the EVTG configuration structure. + * + * The purpose of this API is to initialize the configuration structure to default value for @ref EVTG_Init() + * to use. + * The Flip-Flop can be configured as Bypass mode, RS trigger mode, T-FF mode, D-FF mode, JK-FF mode, Latch mode. + * Please check RM INTC chapter for more details. + * + * @param psConfig EVTG initial configuration structure pointer. + * @param flipflopMode EVTG flip flop mode. see @ ref _evtg_flipflop_mode + */ +void EVTG_GetDefaultConfig(evtg_config_t *psConfig, evtg_flipflop_mode_t flipflopMode) +{ + /* Initializes the configure structure to zero. */ + (void)memset(psConfig, 0, sizeof(evtg_config_t)); + + switch (flipflopMode) + { + case kEVTG_FFModeBypass: + + /* + * In this mode, filp-flop will be passed, The two AOI expressions "AOI_0" and "AOI_1" + * will be directly assigned to EVTG outputs(EVTG_OUTA and EVTG_OUTB). + * + * In this mode, user can choose to enable or disable input sync logic and filter function. + * Here disable both input sync logic and filter function. + */ + psConfig->flipflopMode = kEVTG_FFModeBypass; + + psConfig->enableInputASync = false; + psConfig->enableInputBSync = false; + psConfig->enableInputCSync = false; + psConfig->enableInputDSync = false; + + break; + + case kEVTG_FFModeRSTrigger: + + /* + * In this mode, AOI_0 expression is Reset port, and AOI_1 is Set port. Both are active + * high. When "R"(Reset) is high, whatever "S"(Set) is, EVTG_OUTA will be "0". When "R" is + * low and "S" is high, EVTG_OUTA will be "1". If both "R" and "S" are low, EVTG output + * will be kept. EVTG_OUTB is always the complement of EVTG_OUTA. + * + * In this mode, user can choose to enable or disable input sync logic and filter function. + * Here disable both input sync logic and filter function. + */ + psConfig->flipflopMode = kEVTG_FFModeRSTrigger; + + psConfig->enableInputASync = false; + psConfig->enableInputBSync = false; + psConfig->enableInputCSync = false; + psConfig->enableInputDSync = false; + + break; + + case kEVTG_FFModeTFF: + + /* + * In this mode, AOI_0 expression is T port of T-FF, AOI_1 is CLK port. When T assert, + * the Q port (EVTG_OUTA) will turnover at the rising edge of "CLK". When T dis-assert, + * Q(EVTG_OUTA) will be kept. EVTG_OUTB is always the complement of EVTG_OUTA. + * + * In this mode, input sync or filter has to be enabled to remove the possible glitch. + * Here input sync is enabled, filter is disabled. User could override corresponding fields + * depends on the actual user case to choose to enable or disable input sync logic and filter + * function. + */ + psConfig->flipflopMode = kEVTG_FFModeTFF; + + psConfig->enableInputASync = true; + psConfig->enableInputBSync = true; + psConfig->enableInputCSync = true; + psConfig->enableInputDSync = true; + + break; + + case kEVTG_FFModeJKFF: + + /* + * In general, JK Flip-Flop have four input ports: J, K , Q and CLK(Q is output of Flip-Flop). + * And the logical expression is J&~Q | ~K&Q; Here we implement the logic expression by AOI + * so that we can reuse the D-FF to implement JK-FF. Suppose we set EVTG input "An" as "J" port, + * "Cn" as "K" port, "Dn" as "CLK" port, and "Q" port of FF feed back and override "Bn". + * According to the JK logic expression, the AOI_0 expression will be "An&~Bn | Bn&~Cn", + * AOI_1 expression will be "Dn". + * + * In this mode, input sync or filter has to be enabled to remove the possible glitch. + * Here input sync is enabled, filter is disabled. User could override corresponding fields + * depends on the actual user case to choose to enable or disable input sync logic and filter + * function. + * + * When FF Mode is configured as JK-FF mode, need EVTG_OUTA feedback to EVTG input and replace + * one of the four inputs. Here input Bn is replaced, represents which EVTG input(EVTG_OUTA) + * is replaced by FF output. + */ + psConfig->flipflopMode = kEVTG_FFModeJKFF; + psConfig->outfdbkOverideinput = kEVTG_OutputOverrideInputB; + + psConfig->enableInputASync = true; + psConfig->enableInputBSync = true; + psConfig->enableInputCSync = true; + psConfig->enableInputDSync = true; + + break; + + case kEVTG_FFModeLatch: + + /* + * In this mode, AOI_0 expression is D port, AOI_1 is CLK port. Different from D-FF + * mode, in Latch mode, D port will be passed only when CLK is high, and output will be + * kept when CLK is low. EVTG_OUTB is always the complement of EVTG_OUTA. + * + * In this mode, input sync or filter has to be enabled to remove the possible glitch. + * Here input sync is enabled, filter is disabled. User could override corresponding fields + * depends on the actual user case to choose to enable or disable input sync logic and filter + * function. + */ + psConfig->flipflopMode = kEVTG_FFModeLatch; + + psConfig->enableInputASync = true; + psConfig->enableInputBSync = true; + psConfig->enableInputCSync = true; + psConfig->enableInputDSync = true; + + break; + + default: + assert(false); + break; + } + /* User could choose to enable or disable Flip-flop initial output value. */ + psConfig->enableFlipflopInitOutput = false; + psConfig->flipflopInitOutputValue = kEVTG_FFInitOut0; + + /* User could choose to override this fields to enable filter function. */ + psConfig->aoi0Config.aoiOutFilterConfig.sampleCount = kEVTG_AOIOutFilterSampleCount3; + psConfig->aoi0Config.aoiOutFilterConfig.samplePeriod = 0U; + + psConfig->aoi1Config.aoiOutFilterConfig.sampleCount = kEVTG_AOIOutFilterSampleCount3; + psConfig->aoi1Config.aoiOutFilterConfig.samplePeriod = 0U; + +#if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP + psConfig->enableForceBypassFlipFlopAOI0 = false; + psConfig->enableForceBypassFlipFlopAOI1 = false; +#endif + + /* + * For JK-FF Mode, Here we implement the logic expression by AOI so that we can reuse the + * D-FF to implement JK-FF. Suppose we set EVTG input "An" as "J" port, "Cn" as "K" port, "Dn" + * as "CLK" port, and "Q" port of FF feed back and override "Bn". According to the JK logic + * expression, the AOI_0 expression will be "An&~Bn | Bn&~Cn", AOI_1 expression will be "Dn". + * + * For other FF Mode, the default input here is logical 0. User can configure to produce a logical 0 + * or 1 or pass the true or complement of the selected event input according to their requirement. + */ + if (kEVTG_FFModeJKFF == flipflopMode) + { + psConfig->aoi0Config.productTerm0.aInput = kEVTG_InputDirectPass; + psConfig->aoi0Config.productTerm0.bInput = kEVTG_InputComplement; + psConfig->aoi0Config.productTerm0.cInput = kEVTG_InputLogicOne; + psConfig->aoi0Config.productTerm0.dInput = kEVTG_InputLogicOne; + + psConfig->aoi0Config.productTerm1.aInput = kEVTG_InputLogicOne; + psConfig->aoi0Config.productTerm1.bInput = kEVTG_InputDirectPass; + psConfig->aoi0Config.productTerm1.cInput = kEVTG_InputComplement; + psConfig->aoi0Config.productTerm1.dInput = kEVTG_InputLogicOne; + + psConfig->aoi0Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm0.aInput = kEVTG_InputLogicOne; + psConfig->aoi1Config.productTerm0.bInput = kEVTG_InputLogicOne; + psConfig->aoi1Config.productTerm0.cInput = kEVTG_InputLogicOne; + psConfig->aoi1Config.productTerm0.dInput = kEVTG_InputDirectPass; + + psConfig->aoi1Config.productTerm1.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.dInput = kEVTG_InputLogicZero; + } + else + { + psConfig->aoi0Config.productTerm0.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm0.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm0.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm0.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm1.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm1.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm1.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm1.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi0Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi0Config.productTerm3.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm0.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm0.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm0.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm0.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm1.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm1.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm2.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm2.dInput = kEVTG_InputLogicZero; + + psConfig->aoi1Config.productTerm3.aInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.bInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.cInput = kEVTG_InputLogicZero; + psConfig->aoi1Config.productTerm3.dInput = kEVTG_InputLogicZero; + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_evtg.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_evtg.h new file mode 100644 index 0000000000..42a2a746e7 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_evtg.h @@ -0,0 +1,355 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EVTG_H_ +#define FSL_EVTG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup evtg + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EVTG driver version. */ +#define FSL_EVTG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*@}*/ + +/*! @brief EVTG instance index. */ +typedef enum _evtg_index +{ + kEVTG_Index0 = 0x0U, /*!< EVTG instance index 0. */ + kEVTG_Index1, /*!< EVTG instance index 1. */ + kEVTG_Index2, /*!< EVTG instance index 2. */ + kEVTG_Index3, /*!< EVTG instance index 3. */ +} evtg_index_t; + +/*! @brief EVTG input index. */ +typedef enum _evtg_input_index +{ + kEVTG_InputA = 0x0U, /*!< EVTG input A. */ + kEVTG_InputB, /*!< EVTG input B. */ + kEVTG_InputC, /*!< EVTG input C. */ + kEVTG_InputD, /*!< EVTG input D. */ +} evtg_input_index_t; + +/*! @brief EVTG AOI index. */ +typedef enum _evtg_aoi_index +{ + kEVTG_AOI0 = 0x0U, /*!< EVTG AOI index 0. */ + kEVTG_AOI1 = 0x1U, /*!< EVTG AOI index 1. */ +} evtg_aoi_index_t; + +/*! @brief EVTG AOI product term index. */ +typedef enum _evtg_aoi_product_term +{ + kEVTG_ProductTerm0 = 0x0U, /*!< EVTG AOI product term index 0. */ + kEVTG_ProductTerm1, /*!< EVTG AOI product term index 1. */ + kEVTG_ProductTerm2, /*!< EVTG AOI product term index 2. */ + kEVTG_ProductTerm3, /*!< EVTG AOI product term index 3. */ +} evtg_aoi_product_term_t; + +/*! @brief EVTG input configuration. */ +typedef enum _evtg_aoi_input_config +{ + kEVTG_InputLogicZero = 0x0U, /*!< Force input in product term to a logical zero. */ + kEVTG_InputDirectPass, /*!< Pass input in product term. */ + kEVTG_InputComplement, /*!< Complement input in product term. */ + kEVTG_InputLogicOne, /*!< Force input in product term to a logical one. */ +} evtg_aoi_input_config_t; + +/*! @brief EVTG AOI Output Filter Sample Count. */ +typedef enum _evtg_aoi_outfilter_count +{ + kEVTG_AOIOutFilterSampleCount3 = 0x0U, /*!< EVTG AOI output filter sample count is 3. */ + kEVTG_AOIOutFilterSampleCount4, /*!< EVTG AOI output filter sample count is 4. */ + kEVTG_AOIOutFilterSampleCount5, /*!< EVTG AOI output filter sample count is 5. */ + kEVTG_AOIOutFilterSampleCount6, /*!< EVTG AOI output filter sample count is 6. */ + kEVTG_AOIOutFilterSampleCount7, /*!< EVTG AOI output filter sample count is 7. */ + kEVTG_AOIOutFilterSampleCount8, /*!< EVTG AOI output filter sample count is 8. */ + kEVTG_AOIOutFilterSampleCount9, /*!< EVTG AOI output filter sample count is 9. */ + kEVTG_AOIOutFilterSampleCount10, /*!< EVTG AOI output filter sample count is 10. */ +} evtg_aoi_outfilter_count_t; + +/*! + * @brief EVTG output feedback override control mode. When FF is configured as JK-FF mode, + * need EVTG_OUTA feedback to EVTG input and replace one of the four inputs. + */ +typedef enum _evtg_outfdbk_override_input +{ + kEVTG_OutputOverrideInputA = 0x0U, /*!< Replace input A. */ + kEVTG_OutputOverrideInputB, /*!< Replace input B. */ + kEVTG_OutputOverrideInputC, /*!< Replace input C. */ + kEVTG_OutputOverrideInputD, /*!< Replace input D. */ +} evtg_outfdbk_override_input_t; + +/*! @brief EVTG flip flop mode configuration. */ +typedef enum _evtg_flipflop_mode +{ + kEVTG_FFModeBypass = 0x0U, /*!< Bypass mode (default).In this mode, user can choose to enable + or disable input sync logic and filter function. */ + kEVTG_FFModeRSTrigger, /*!< RS trigger mode. In this mode, user can choose to enable + or disable input sync logic and filter function. */ + kEVTG_FFModeTFF, /*!< T-FF mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ + kEVTG_FFModeDFF, /*!< D-FF mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ + kEVTG_FFModeJKFF, /*!< JK-FF mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ + kEVTG_FFModeLatch, /*!< Latch mode. In this mode, input sync or filter has to be enabled + to remove the possible glitch.*/ +} evtg_flipflop_mode_t; + +/*! @brief EVTG flip-flop initial value. */ +typedef enum _evtg_flipflop_init_output +{ + kEVTG_FFInitOut0 = 0x0U, /*!< Configure the positive output of flip-flop as 0. */ + kEVTG_FFInitOut1 = 0x1U, /*!< Configure the positive output of flip-flop as 1. */ +} evtg_flipflop_init_output_t; + +/*! @brief The structure for configuring an AOI output filter sample. + * + * AOI output filter sample count represent the number of consecutive samples that must agree prior to the AOI output + * filter accepting an transition. + * AOI output filter sample period represent the sampling period (in IP bus clock cycles) of the AOI output signals. + * Each AOI output is sampled multiple times at the rate specified by this period. + * + * For the modes with Filter function enabled, filter delay is "(FILT_CNT + 3) x FILT_PER + 2". + * + */ +typedef struct _evtg_aoi_outfilter_config +{ + evtg_aoi_outfilter_count_t sampleCount; /*!< EVTG AOI output filter sample count. + refer to @ref evtg_aoi_outfilter_count_t. */ + uint8_t samplePeriod; /*!< EVTG AOI output filter sample period, within 0~255. If sample period + value is 0x00 (default), then the input filter is bypassed. */ +} evtg_aoi_outfilter_config_t; + +/*! @brief The structure for configuring an AOI product term. */ +typedef struct _evtg_aoi_product_term_config +{ + evtg_aoi_input_config_t aInput; /*!< Input A configuration. */ + evtg_aoi_input_config_t bInput; /*!< Input B configuration. */ + evtg_aoi_input_config_t cInput; /*!< Input C configuration. */ + evtg_aoi_input_config_t dInput; /*!< Input D configuration. */ +} evtg_aoi_product_term_config_t; + +/*! @brief EVTG AOI configuration structure. */ +typedef struct _evtg_aoi_config +{ + /* AOI Output Filter configuration. */ + evtg_aoi_outfilter_config_t aoiOutFilterConfig; /*!< EVTG AOI output filter sample + configuration structure. */ + + /* Product term configuration. */ + evtg_aoi_product_term_config_t productTerm0; /*!< Configure AOI product term0. */ + evtg_aoi_product_term_config_t productTerm1; /*!< Configure AOI product term1. */ + evtg_aoi_product_term_config_t productTerm2; /*!< Configure AOI product term2. */ + evtg_aoi_product_term_config_t productTerm3; /*!< Configure AOI product term3. */ +} evtg_aoi_config_t; + +/*! @brief EVTG configuration covering all configurable fields. */ +typedef struct _evtg_config +{ + /* Input configuration. */ + bool enableInputASync; /*!< Enable/Disable EVTG A input synchronous with bus clk. */ + bool enableInputBSync; /*!< Enable/Disable EVTG B input synchronous with bus clk. */ + bool enableInputCSync; /*!< Enable/Disable EVTG C input synchronous with bus clk. */ + bool enableInputDSync; /*!< Enable/Disable EVTG D input synchronous with bus clk. */ + evtg_outfdbk_override_input_t outfdbkOverideinput; /*!< EVTG output feedback to EVTG input + and replace one of the four inputs. */ + + /* Flip-flop configuration. */ + evtg_flipflop_mode_t flipflopMode; /*!< Flip-Flop can be configured as one of Bypass mode, RS trigger mode, + T-FF mode, D-FF mode, JK-FF mode, Latch mode. */ + bool enableFlipflopInitOutput; /*!< Flip-flop initial output value enable/disable. */ + evtg_flipflop_init_output_t flipflopInitOutputValue; /*!< Flip-flop initial output value configuration. */ + +#if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP + bool enableForceBypassFlipFlopAOI0; /*!< Enable/Disable force bypass Flip-Flop and route the AOI_0(Filter_0) + value directly to EVTG_OUTA */ + bool enableForceBypassFlipFlopAOI1; /*!< Enable/Disable force bypass Flip-Flop and route the AOI_1(Filter_1) + value directly to EVTG_OUTB */ +#endif + + /* AOI configuration. */ + evtg_aoi_config_t aoi0Config; /*!< Configure EVTG AOI0. */ + evtg_aoi_config_t aoi1Config; /*!< Configure EVTG AOI1. */ +} evtg_config_t; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup evtg_driver + * @{ + */ + +/*! + * @name Initialization Interfaces + * @{ + */ + +/*! + * @brief Initialize EVTG with a user configuration structure. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param psConfig EVTG initial configuration structure pointer. + */ +void EVTG_Init(EVTG_Type *base, evtg_index_t evtgIndex, evtg_config_t *psConfig); + +/*! + * @brief Loads default values to the EVTG configuration structure. + * + * The purpose of this API is to initialize the configuration structure to default value for @ref EVTG_Init() + * to use. + * The Flip-Flop can be configured as Bypass mode, RS trigger mode, T-FF mode, D-FF mode, JK-FF mode, Latch mode. + * Please check RM INTC chapter for more details. + * + * @param psConfig EVTG initial configuration structure pointer. + * @param flipflopMode EVTG flip flop mode. see @ ref _evtg_flipflop_mode + */ +void EVTG_GetDefaultConfig(evtg_config_t *psConfig, evtg_flipflop_mode_t flipflopMode); +/*! @} */ + +/*! + * @name Force Init Flipflop Interfaces + * @{ + */ + +/*! + * @brief Force Flip-flop initial output value to be presented on flip-flop positive output. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param flipflopInitOutputValue EVTG flip-flop initial output control. + * see @ref evtg_flipflop_init_output_t + */ +static inline void EVTG_ForceFlipflopInitOutput(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_flipflop_init_output_t flipflopInitOutputValue) +{ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~(uint16_t)EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= + EVTG_EVTG_INST_EVTG_CTRL_FF_INIT((uint16_t)flipflopInitOutputValue); + /* INIT_EN bit should be set after FF_INIT is set. */ + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_INIT_EN_MASK; +} +/*! @} */ + +/*! + * @name Input Interfaces + * @{ + */ +/*! + * @brief Configure each input value of AOI product term. Each selected input term in + * each product term can be configured to produce a logical 0 or 1 or pass the + * true or complement of the selected event input. Adapt to some simple aoi + * expressions. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param aoiIndex EVTG AOI index. see enum ref evtg_aoi_index_t + * @param productTerm EVTG product term index. + * @param inputIndex EVTG input index. + * @param input EVTG input configuration with enum @ref evtg_aoi_input_config_t. + */ +static inline void EVTG_SetProductTermInput(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_aoi_index_t aoiIndex, + evtg_aoi_product_term_t productTerm, + evtg_input_index_t inputIndex, + evtg_aoi_input_config_t input) +{ + if (kEVTG_AOI0 == aoiIndex) + { + if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1)) + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + else + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + } + else if (kEVTG_AOI1 == aoiIndex) + { + if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1)) + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + else + { + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 &= + (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 |= + ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U + + (((3U - (uint8_t)productTerm) % 2U) * 8U))) & + (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))); + } + } + else + { + ; /* No action*/ + } +} + +/*! + * @brief Configure AOI product term by initializing the product term + * configuration structure. + * + * @param base EVTG base address. + * @param evtgIndex EVTG instance index. + * @param aoiIndex EVTG AOI index. see enum @ref evtg_aoi_index_t + * @param productTerm EVTG AOI product term index. + * @param psProductTermConfig Pointer to EVTG product term configuration structure. + * see ref _evtg_aoi_product_term_config + */ +void EVTG_ConfigAOIProductTerm(EVTG_Type *base, + evtg_index_t evtgIndex, + evtg_aoi_index_t aoiIndex, + evtg_aoi_product_term_t productTerm, + evtg_aoi_product_term_config_t *psProductTermConfig); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_EVTG_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ewm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ewm.c new file mode 100644 index 0000000000..593cf87a50 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ewm.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ewm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ewm" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * endcode + * + * param base EWM peripheral base address + * param config The configuration of the EWM + */ +void EWM_Init(EWM_Type *base, const ewm_config_t *config) +{ + assert(NULL != config); + + uint8_t value = 0U; + +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif + value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | + EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + base->CLKPRESCALER = config->prescaler; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + base->CLKCTRL = (uint8_t)config->clockSource; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ + + base->CMPL = config->compareLowValue; + base->CMPH = config->compareHighValue; + base->CTRL = value; +} + +/*! + * brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * param base EWM peripheral base address + */ +void EWM_Deinit(EWM_Type *base) +{ + EWM_DisableInterrupts(base, (uint32_t)kEWM_InterruptEnable); +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ +} + +/*! + * brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * endcode + * + * param config Pointer to the EWM configuration structure. + * see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableEwm = true; + config->enableEwmInput = false; + config->setInputAssertLogic = false; + config->enableInterrupt = false; +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + config->clockSource = kEWM_LpoClockSource0; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + config->prescaler = 0U; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + config->compareLowValue = 0U; + config->compareHighValue = 0xFEU; +} + +/*! + * brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * param base EWM peripheral base address + */ +void EWM_Refresh(EWM_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->SERV = (uint8_t)0xB4U; + base->SERV = (uint8_t)0x2CU; + EnableGlobalIRQ(primaskValue); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ewm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ewm.h new file mode 100644 index 0000000000..ee3face3f1 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ewm.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_EWM_H_ +#define FSL_EWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ewm + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EWM driver version 2.0.3. */ +#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/*! @brief Describes EWM clock source. */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT +typedef enum _ewm_lpo_clock_source +{ + kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/ + kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/ + kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/ + kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/ +} ewm_lpo_clock_source_t; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ + +/*! + * @brief Data structure for EWM configuration. + * + * This structure is used to configure the EWM. + */ +typedef struct _ewm_config +{ + bool enableEwm; /*!< Enable EWM module */ + bool enableEwmInput; /*!< Enable EWM_in input */ + bool setInputAssertLogic; /*!< EWM_in signal assertion state */ + bool enableInterrupt; /*!< Enable EWM interrupt */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + uint8_t prescaler; /*!< Clock prescaler value */ +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + uint8_t compareLowValue; /*!< Compare low-register value */ + uint8_t compareHighValue; /*!< Compare high-register value */ +} ewm_config_t; + +/*! + * @brief EWM interrupt configuration structure with default settings all disabled. + * + * This structure contains the settings for all of EWM interrupt configurations. + */ +enum _ewm_interrupt_enable_t +{ + kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/ +}; + +/*! + * @brief EWM status flags. + * + * This structure contains the constants for the EWM status flags for use in the EWM functions. + */ +enum _ewm_status_flags_t +{ + kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name EWM initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * @code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * @endcode + * + * @param base EWM peripheral base address + * @param config The configuration of the EWM + */ +void EWM_Init(EWM_Type *base, const ewm_config_t *config); + +/*! + * @brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * @param base EWM peripheral base address + */ +void EWM_Deinit(EWM_Type *base); + +/*! + * @brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * @code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * @endcode + * + * @param config Pointer to the EWM configuration structure. + * @see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config); + +/* @} */ + +/*! + * @name EWM functional Operation + * @{ + */ + +/*! + * @brief Enables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL |= (uint8_t)mask; +} + +/*! + * @brief Disables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL &= (uint8_t)(~mask); +} + +/*! + * @brief Gets all status flags. + * + * This function gets all status flags. + * + * This is an example for getting the running flag. + * @code + * uint32_t status; + * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; + * @endcode + * @param base EWM peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t + * - True: a related status flag has been set. + * - False: a related status flag is not set. + */ +static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) +{ + return ((uint32_t)base->CTRL & EWM_CTRL_EWMEN_MASK); +} + +/*! + * @brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * @param base EWM peripheral base address + */ +void EWM_Refresh(EWM_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* FSL_EWM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan.c new file mode 100644 index 0000000000..c3a989f3f8 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan.c @@ -0,0 +1,4895 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexcan.h" + +/* + * $Coverage Justification Reference$ + * + * $Justification flexcan_c_ref_1$ + * The FLEXCAN_ReadRxFifo() return fail only when Rx FIFO is diabled. But in IRQ handler, will first check whether the + * FIFO is enabled, and only call FLEXCAN_ReadRxFifo if the FIFO is enabled. So to cover this line/branch, need to + * interrupt the current execution by a high priority IRQ after confirming that the FIFO is enabled, and disabled the + * FIFO in the high priority interrupt. It is difficult to simulate this situation in unit test, so add Justification. + * + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan" +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +#define RXINTERMISSION (CAN_DBG1_CFSM(0x2f)) +#define TXINTERMISSION (CAN_DBG1_CFSM(0x14)) +#define BUSIDLE (CAN_DBG1_CFSM(0x02)) +#define CBN_VALUE3 (CAN_DBG1_CBN(0x03)) +#define DELAY_BUSIDLE (200) +#endif + +/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ +#define IDEAL_DATA_SP_1 (800U) +#define IDEAL_DATA_SP_2 (750U) +#define IDEAL_DATA_SP_3 (700U) +#define IDEAL_DATA_SP_4 (625U) +#define IDEAL_NOMINAL_SP (800U) + +/* According to CiA doc 301 v4.2.0 and previous version. */ +#define IDEAL_SP_LOW (750U) +#define IDEAL_SP_MID (800U) +#define IDEAL_SP_HIGH (875U) + +#define IDEAL_SP_FACTOR (1000U) + +/* Define the max value of bit timing segments when use different timing register. */ +#define MAX_PROPSEG (CAN_CTRL1_PROPSEG_MASK >> CAN_CTRL1_PROPSEG_SHIFT) +#define MAX_PSEG1 (CAN_CTRL1_PSEG1_MASK >> CAN_CTRL1_PSEG1_SHIFT) +#define MAX_PSEG2 (CAN_CTRL1_PSEG2_MASK >> CAN_CTRL1_PSEG2_SHIFT) +#define MAX_RJW (CAN_CTRL1_RJW_MASK >> CAN_CTRL1_RJW_SHIFT) +#define MAX_PRESDIV (CAN_CTRL1_PRESDIV_MASK >> CAN_CTRL1_PRESDIV_SHIFT) +#define CTRL1_MAX_TIME_QUANTA (1U + MAX_PROPSEG + 1U + MAX_PSEG1 + 1U + MAX_PSEG2 + 1U) +#define CTRL1_MIN_TIME_QUANTA (8U) + +#define MAX_EPROPSEG (CAN_CBT_EPROPSEG_MASK >> CAN_CBT_EPROPSEG_SHIFT) +#define MAX_EPSEG1 (CAN_CBT_EPSEG1_MASK >> CAN_CBT_EPSEG1_SHIFT) +#define MAX_EPSEG2 (CAN_CBT_EPSEG2_MASK >> CAN_CBT_EPSEG2_SHIFT) +#define MAX_ERJW (CAN_CBT_ERJW_MASK >> CAN_CBT_ERJW_SHIFT) +#define MAX_EPRESDIV (CAN_CBT_EPRESDIV_MASK >> CAN_CBT_EPRESDIV_SHIFT) +#define CBT_MAX_TIME_QUANTA (1U + MAX_EPROPSEG + 1U + MAX_EPSEG1 + 1U + MAX_EPSEG2 + 1U) +#define CBT_MIN_TIME_QUANTA (8U) + +#define MAX_FPROPSEG (CAN_FDCBT_FPROPSEG_MASK >> CAN_FDCBT_FPROPSEG_SHIFT) +#define MAX_FPSEG1 (CAN_FDCBT_FPSEG1_MASK >> CAN_FDCBT_FPSEG1_SHIFT) +#define MAX_FPSEG2 (CAN_FDCBT_FPSEG2_MASK >> CAN_FDCBT_FPSEG2_SHIFT) +#define MAX_FRJW (CAN_FDCBT_FRJW_MASK >> CAN_FDCBT_FRJW_SHIFT) +#define MAX_FPRESDIV (CAN_FDCBT_FPRESDIV_MASK >> CAN_FDCBT_FPRESDIV_SHIFT) +#define FDCBT_MAX_TIME_QUANTA (1U + MAX_FPROPSEG + 0U + MAX_FPSEG1 + 1U + MAX_FPSEG2 + 1U) +#define FDCBT_MIN_TIME_QUANTA (5U) + +#define MAX_TDCOFF ((uint32_t)CAN_FDCTRL_TDCOFF_MASK >> CAN_FDCTRL_TDCOFF_SHIFT) + +#define MAX_NTSEG1 (CAN_ENCBT_NTSEG1_MASK >> CAN_ENCBT_NTSEG1_SHIFT) +#define MAX_NTSEG2 (CAN_ENCBT_NTSEG2_MASK >> CAN_ENCBT_NTSEG2_SHIFT) +#define MAX_NRJW (CAN_ENCBT_NRJW_MASK >> CAN_ENCBT_NRJW_SHIFT) +#define MAX_ENPRESDIV (CAN_EPRS_ENPRESDIV_MASK >> CAN_EPRS_ENPRESDIV_SHIFT) +#define ENCBT_MAX_TIME_QUANTA (1U + MAX_NTSEG1 + 1U + MAX_NTSEG2 + 1U) +#define ENCBT_MIN_TIME_QUANTA (8U) + +#define MAX_DTSEG1 (CAN_EDCBT_DTSEG1_MASK >> CAN_EDCBT_DTSEG1_SHIFT) +#define MAX_DTSEG2 (CAN_EDCBT_DTSEG2_MASK >> CAN_EDCBT_DTSEG2_SHIFT) +#define MAX_DRJW (CAN_EDCBT_DRJW_MASK >> CAN_EDCBT_DRJW_SHIFT) +#define MAX_EDPRESDIV (CAN_EPRS_EDPRESDIV_MASK >> CAN_EPRS_EDPRESDIV_SHIFT) +#define EDCBT_MAX_TIME_QUANTA (1U + MAX_DTSEG1 + 1U + MAX_DTSEG2 + 1U) +#define EDCBT_MIN_TIME_QUANTA (5U) + +#define MAX_ETDCOFF ((uint32_t)CAN_ETDC_ETDCOFF_MASK >> CAN_ETDC_ETDCOFF_SHIFT) + +/* TSEG1 corresponds to the sum of xPROPSEG and xPSEG1, TSEG2 corresponds to the xPSEG2 value. */ +#define MIN_TIME_SEGMENT1 (2U) +#define MIN_TIME_SEGMENT2 (2U) + +/* Define maximum CAN and CAN FD bit rate supported by FLEXCAN. */ +#if (defined(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#define MAX_CANFD_BITRATE ((uint32_t)(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#else +#define MAX_CANFD_BITRATE (8000000U) +#endif +#define MAX_CAN_BITRATE (1000000U) + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +#define CAN_ESR1_FLTCONF_BUSOFF CAN_ESR1_FLTCONF(2U) +#endif + +/* Define the range of memory that needs to be initialized when the device has memory error detection feature. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define CAN_INIT_RXFIR ((uintptr_t)base + 0x4Cu) +#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1) +#define CAN_INIT_MEMORY_SIZE_1 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 +#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2) +#define CAN_INIT_MEMORY_SIZE_2 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifndef CAN_CLOCK_CHECK_NO_AFFECTS +/* If no define such MACRO, it mean that the CAN in current device have no clock affect issue. */ +#define CAN_CLOCK_CHECK_NO_AFFECTS (true) +#endif /* CAN_CLOCK_CHECK_NO_AFFECTS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXCAN_RSTS) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS +#elif defined(FLEXCAN_RSTS_N) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS_N +#endif + +/*! @brief FlexCAN Internal State. */ +enum _flexcan_state +{ + kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_mb_code_rx +{ + kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ + kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ + kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ + kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB, The CPU must not access the MB.*/ + kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame and transmit a + Response Frame in return.*/ + kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_mb_code_tx +{ + kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ + kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ + kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or MB is a TX Remote Request + Frame (when MB RTR = 1).*/ + kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from an incoming Remote Request Frame.*/ + kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if !defined(NDEBUG) +/*! + * @brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @return TRUE if the index MB is occupied by Rx FIFO, FALSE if the index MB not occupied by Rx FIFO. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif + +/*! + * @brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_Reset(CAN_Type *base); + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN. + * + * This function use to calculates the Classical CAN segment values which will be set in CTRL1/CBT/ENCBT register. + * + * @param base FlexCAN peripheral base address. + * @param tqNum Number of time quantas per bit, range in 8 ~ 25 when use CTRL1, range in 8 ~ 129 when use CBT, range in + * 8 ~ 385 when use ENCBT. param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_GetSegments(CAN_Type *base, + uint32_t bitRate, + uint32_t tqNum, + flexcan_timing_config_t *pTimingConfig); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Calculates the segment values for a single bit time for CAN FD data phase. + * + * This function use to calculates the CAN FD data phase segment values which will be set in CFDCBT/EDCBT + * register. + * + * @param bitRateFD Data phase bit rate + * @param tqNum Number of time quanta per bit + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_FDGetSegments(uint32_t bitRateFD, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig); + +/*! + * @brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The Calculated timing values will be set in CBT/ENCBT registers. The calculation is based on the recommendation of + * the CiA 1301 v1.0.0 document. + * + * @param bitRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool FLEXCAN_CalculateImprovedNominalTimingValues(uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); + +#endif + +/*! + * @brief Check unhandle interrupt events + * + * @param base FlexCAN peripheral base address. + * @return TRUE if unhandled interrupt action exist, FALSE if no unhandlered interrupt action exist. + */ +static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base); + +/*! + * @brief Sub Handler Data Trasfered Events + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pResult Pointer to the Handle result. + * + * @return the status after handle each data transfered event. + */ +static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint32_t *pResult); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Sub Handler Ehanced Rx FIFO event + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param flags FlexCAN interrupt flags. + * + * @return the status after handle Ehanced Rx FIFO event. + */ +static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64_t flags); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; + +/* Array of FlexCAN IRQ number. */ +static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; +static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; +static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; +static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; +static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; +static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; + +/* Array of FlexCAN handle. */ +static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of FlexCAN clock name. */ +static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +#if defined(FLEXCAN_PERIPH_CLOCKS) +/* Array of FlexCAN serial clock name. */ +static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXCAN_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexcanResets[] = FLEXCAN_RESETS_ARRAY; +#endif + +/* FlexCAN ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR; +#else +static flexcan_isr_t s_flexcanIsr; +#endif + +/******************************************************************************* + * Implementation of 32-bit memset + ******************************************************************************/ + +static void flexcan_memset(void *s, uint32_t c, size_t n) +{ + size_t m; + uint32_t *ptr = s; + + m = n / sizeof(*ptr); + + while ((m--) != (size_t)0) + { + *ptr++ = c; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Determine whether the FlexCAN instance support CAN FD mode at run time. + * + * note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part + * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. + * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be + * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, + * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode. + * + * param base FlexCAN peripheral base address. + * return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode. + */ +bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + /* Enable CAN FD operation. */ + base->MCR |= CAN_MCR_FDEN_MASK; + + /* There are some SoC parts that don't support CAN FD. + * Checking if FDEN bit is really set to 1 is a way to ensure that CAN FD is supported. + * When SoC parts don't support CAN FD, FDEN bit stuck at 0 and can't be set to 1. */ + if (0U == (base->MCR & CAN_MCR_FDEN_MASK)) + { + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + return false; + } + else + { + /* Clear CAN FD operation. */ + base->MCR &= ~CAN_MCR_FDEN_MASK; + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + return true; + } +} +#endif + +/*! + * brief Get the FlexCAN instance from peripheral base address. + * + * param base FlexCAN peripheral base address. + * return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) + { + if (s_flexcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexcanBases)); + + return instance; +} + +/*! + * brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * param base FlexCAN peripheral base address. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + uint32_t u32TimeoutCount = 0U; + uint32_t u32TempMCR = 0U; + uint32_t u32TempIMASK1 = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + + /* Step1: set FRZ enable in MCR. */ + base->MCR |= CAN_MCR_FRZ_MASK; + + /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */ + if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + } + + /* Step3: polling LPMACK. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_LPMACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step4: to check FLTCONF in ESR1 register */ + if (0U == (base->ESR1 & CAN_ESR1_FLTCONF_BUSOFF)) + { + /* Step5B: Set Halt bits. */ + base->MCR |= CAN_MCR_HALT_MASK; + + /* Step6B: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set, timeout need more than 178 + * CAN bit length, so 20 multiply timeout is enough. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 20U; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + } + else + { + /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + + /* Step5A: Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Step6A: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step7A: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step8A: reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Step9A: reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } +} +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341) +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + uint32_t u32TimeoutCount = 0U; + uint32_t u32TempMCR = 0U; + uint32_t u32TempIMASK1 = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + + /* Step1: set FRZ and HALT bit enable in MCR. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + + /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */ + if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + } + + /* Step3: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 100U; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step4: check whether the timeout reached. if no skip step5 to step8. */ + if (0U == u32TimeoutCount) + { + /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + /* Step5: Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Step6: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */ + while (CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) + { + } + + /* Step7: reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Step8: reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } +} +#else +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + while (0U == (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} +#endif + +/*! + * brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * param base FlexCAN peripheral base address. + */ +void FLEXCAN_ExitFreezeMode(CAN_Type *base) +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Clean FlexCAN Access With Non-Correctable Error Interrupt Flag to avoid be put in freeze mode. */ + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag | + (uint64_t)kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag); +#endif + + /* Clear Freeze, Halt bits. */ + base->MCR &= ~CAN_MCR_HALT_MASK; + base->MCR &= ~CAN_MCR_FRZ_MASK; + + /* Wait until the FlexCAN Module exit freeze mode. */ + while (0U != (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} + +#if !defined(NDEBUG) +/*! + * brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * return TRUE if the index MB is occupied by Rx FIFO, FALSE if the index MB not occupied by Rx FIFO. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) +{ + uint8_t lastOccupiedMb; + bool fgRet; + + /* Is Rx FIFO enabled? */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Get RFFN value. */ + lastOccupiedMb = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ + lastOccupiedMb = ((lastOccupiedMb + 1U) * 2U) + 5U; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + /* the first valid MB should be occupied by ERRATA 5461 or 5829. */ + lastOccupiedMb += 1U; +#endif + fgRet = (mbIdx <= lastOccupiedMb); + } + else + { +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + if (0U == mbIdx) + { + fgRet = true; + } + else +#endif + { + fgRet = false; + } + } + + return fgRet; +} +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +/*! + * brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * param base FlexCAN peripheral base address. + * return The first valid Message Buffer Number. + */ +static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint8_t firstValidMbNum; + + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + firstValidMbNum = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1U) * 2U) + 6U; + } + else + { + firstValidMbNum = 0U; + } + + return firstValidMbNum; +} +#endif + +/*! + * brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * param base FlexCAN peripheral base address. + */ +static void FLEXCAN_Reset(CAN_Type *base) +{ + /* The module must should be first exit from low power + * mode, and then soft reset can be applied. + */ + assert(0U == (base->MCR & CAN_MCR_MDIS_MASK)); + + uint8_t i; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base))) + { + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; + } +#endif + + /* Wait until FlexCAN exit from any Low Power Mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + + /* Assert Soft Reset Signal. */ + base->MCR |= CAN_MCR_SOFTRST_MASK; + /* Wait until FlexCAN reset completes. */ + while (0U != (base->MCR & CAN_MCR_SOFTRST_MASK)) + { + } + +/* Reset MCR register. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | + CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); +#else + base->MCR |= + CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); +#endif + + /* Reset CTRL1 and CTRL2 register, default to eanble SMP feature which enable three sample point to determine the + * received bit's value of the. */ + base->CTRL1 = CAN_CTRL1_SMP_MASK; + base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Enable unrestricted write access to FlexCAN memory. */ + base->CTRL2 |= CAN_CTRL2_WRMFRZ_MASK; + /* Do memory initialization for all FlexCAN RAM in order to have the parity bits in memory properly + updated. */ + *(volatile uint32_t *)CAN_INIT_RXFIR = 0x0U; + flexcan_memset(CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1); + flexcan_memset(CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2); + /* Disable unrestricted write access to FlexCAN memory. */ + base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK; + + /* Clean all memory error flags. */ + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag); +#else + /* Only need clean all Message Buffer memory. */ + flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB)); +#endif + + /* Clean all individual Rx Mask of Message Buffers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->RXIMR[i] = 0x3FFFFFFF; + } + + /* Clean Global Mask of Message Buffers. */ + base->RXMGMASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 14. */ + base->RX14MASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 15. */ + base->RX15MASK = 0x3FFFFFFF; + /* Clean Global Mask of Rx FIFO. */ + base->RXFGMASK = 0x3FFFFFFF; +} + +/*! + * brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase. + * + * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on + * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param sourceClock_Hz Source Clock in Hz. + * param bitRate_Bps Bit rate in Bps. + * return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully. + */ +status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps) +{ + flexcan_timing_config_t timingCfg; + status_t result = kStatus_Fail; + + if (FLEXCAN_CalculateImprovedTimingValues(base, bitRate_Bps, sourceClock_Hz, &timingCfg)) + { + FLEXCAN_SetTimingConfig(base, &timingCfg); + result = kStatus_Success; + } + + return result; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Set bit rate of FlexCAN FD frame. + * + * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing + * values. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRateN_Bps Nominal bit Rate in Bps. + * @param bitRateD_Bps Data bit Rate in Bps. + * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully. + */ +status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps) +{ + flexcan_timing_config_t timingCfg; + status_t result = kStatus_Fail; + + if (FLEXCAN_FDCalculateImprovedTimingValues(base, bitRateN_Bps, bitRateD_Bps, sourceClock_Hz, &timingCfg)) + { + FLEXCAN_SetFDTimingConfig(base, &timingCfg); + result = kStatus_Success; + } + + return result; +} +#endif + +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL); + * endcode + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz) +{ + /* Assertion. */ + assert(NULL != pConfig); + assert((pConfig->maxMbNum > 0U) && + (pConfig->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); + + uint32_t mcrTemp; + uint32_t ctrl1Temp; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + flexcan_timing_config_t timingCfg = pConfig->timingConfig; + /* FlexCAN classical CAN frame or CAN FD frame nominal phase timing setting formula: + * quantum = 1 + (phaseSeg1 + 1) + (phaseSeg2 + 1) + (propSeg + 1); + */ + uint32_t quantum = (1U + ((uint32_t)timingCfg.phaseSeg1 + 1U) + ((uint32_t)timingCfg.phaseSeg2 + 1U) + + ((uint32_t)timingCfg.propSeg + 1U)); + uint32_t tqFre = pConfig->bitRate * quantum; + uint16_t maxDivider; + + /* Assertion: Check bit rate value. */ + assert((pConfig->bitRate != 0U) && (pConfig->bitRate <= 1000000U) && (tqFre <= sourceClock_Hz)); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + assert((tqFre * MAX_ENPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_ENPRESDIV; +#else + assert((tqFre * MAX_EPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_EPRESDIV; +#endif + } + else + { + assert((tqFre * MAX_PRESDIV) >= sourceClock_Hz); + maxDivider = MAX_PRESDIV; + } +#else + assert((tqFre * MAX_PRESDIV) >= sourceClock_Hz); + maxDivider = MAX_PRESDIV; +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); + /* Enable FlexCAN clock. */ + (void)CLOCK_EnableClock(s_flexcanClock[instance]); + /* + * Check the CAN clock in this device whether affected by Other clock gate + * If it affected, we'd better to change other clock source, + * If user insist on using that clock source, user need open these gate at same time, + * In this scene, User need to care the power consumption. + */ + assert(CAN_CLOCK_CHECK_NO_AFFECTS); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Enable FlexCAN serial clock. */ + (void)CLOCK_EnableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXCAN_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexcanResets[FLEXCAN_GetInstance(base)]); +#endif + +#if defined(CAN_CTRL1_CLKSRC_MASK) +#if (defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) && FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) + if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + { + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrc0 == pConfig->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : + (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK); + } +#endif /* CAN_CTRL1_CLKSRC_MASK */ + + /* Enable FlexCAN Module for configuration. */ + FLEXCAN_Enable(base, true); + + /* Reset to known status. */ + FLEXCAN_Reset(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Enable to update in MCER. */ + base->CTRL2 |= CAN_CTRL2_ECRWRE_MASK; + base->MECR &= ~CAN_MECR_ECRWRDIS_MASK; + + /* Enable/Disable Memory Error Detection and Correction.*/ + base->MECR = (pConfig->enableMemoryErrorControl) ? (base->MECR & ~CAN_MECR_ECCDIS_MASK) : + (base->MECR | CAN_MECR_ECCDIS_MASK); + + /* Enable/Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode. */ + base->MECR = (pConfig->enableNonCorrectableErrorEnterFreeze) ? (base->MECR | CAN_MECR_NCEFAFRZ_MASK) : + (base->MECR & ~CAN_MECR_NCEFAFRZ_MASK); + /* Lock MCER register. */ + base->CTRL2 &= ~CAN_CTRL2_ECRWRE_MASK; +#endif + + /* Save current CTRL1 value and enable to enter Freeze mode(enabled by default). */ + ctrl1Temp = base->CTRL1; + + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ + mcrTemp = base->MCR; + + /* Enable Loop Back Mode? */ + ctrl1Temp = (pConfig->enableLoopBack) ? (ctrl1Temp | CAN_CTRL1_LPB_MASK) : (ctrl1Temp & ~CAN_CTRL1_LPB_MASK); + + /* Enable Timer Sync? */ + ctrl1Temp = (pConfig->enableTimerSync) ? (ctrl1Temp | CAN_CTRL1_TSYN_MASK) : (ctrl1Temp & ~CAN_CTRL1_TSYN_MASK); + + /* Enable Listen Only Mode? */ + ctrl1Temp = (pConfig->enableListenOnlyMode) ? ctrl1Temp | CAN_CTRL1_LOM_MASK : ctrl1Temp & ~CAN_CTRL1_LOM_MASK; + +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + /* Enable Supervisor Mode? */ + mcrTemp = (pConfig->enableSupervisorMode) ? mcrTemp | CAN_MCR_SUPV_MASK : mcrTemp & ~CAN_MCR_SUPV_MASK; +#endif + + /* Set the maximum number of Message Buffers */ + mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB((uint32_t)pConfig->maxMbNum - 1U); + + /* Enable Self Wake Up Mode and configure the wake up source. */ + mcrTemp = (pConfig->enableSelfWakeup) ? (mcrTemp | CAN_MCR_SLFWAK_MASK) : (mcrTemp & ~CAN_MCR_SLFWAK_MASK); + mcrTemp = (kFLEXCAN_WakeupSrcFiltered == pConfig->wakeupSrc) ? (mcrTemp | CAN_MCR_WAKSRC_MASK) : + (mcrTemp & ~CAN_MCR_WAKSRC_MASK); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Enable Pretended Networking Mode? When Pretended Networking mode is set, Self Wake Up feature must be disabled.*/ + mcrTemp = (pConfig->enablePretendedeNetworking) ? ((mcrTemp & ~CAN_MCR_SLFWAK_MASK) | CAN_MCR_PNET_EN_MASK) : + (mcrTemp & ~CAN_MCR_PNET_EN_MASK); +#endif + + /* Enable Individual Rx Masking and Queue feature? */ + mcrTemp = (pConfig->enableIndividMask) ? (mcrTemp | CAN_MCR_IRMQ_MASK) : (mcrTemp & ~CAN_MCR_IRMQ_MASK); + + /* Disable Self Reception? */ + mcrTemp = (pConfig->disableSelfReception) ? mcrTemp | CAN_MCR_SRXDIS_MASK : mcrTemp & ~CAN_MCR_SRXDIS_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) + { + /* Enable Doze Mode? */ + mcrTemp = (pConfig->enableDoze) ? (mcrTemp | CAN_MCR_DOZE_MASK) : (mcrTemp & ~CAN_MCR_DOZE_MASK); + } +#endif + + /* Write back CTRL1 Configuration to register. */ + base->CTRL1 = ctrl1Temp; + + /* Write back MCR Configuration to register. */ + base->MCR = mcrTemp; + + /* Check whether Nominal Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > maxDivider) + { + timingCfg.preDivider = maxDivider; + } + else + { + timingCfg.preDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + + /* Update actual timing characteristic. */ + FLEXCAN_SetTimingConfig(base, &timingCfg); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true); + * endcode + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs + * to be less than or equal to this value. + * param brs True if bit rate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) +{ + assert((uint32_t)dataSize <= 3U); + assert(((pConfig->bitRate < pConfig->bitRateFD) && brs) || ((pConfig->bitRate == pConfig->bitRateFD) && (!brs))); + + uint32_t fdctrl = 0U; + flexcan_timing_config_t timingCfg = pConfig->timingConfig; + /* FlexCAN FD frame data phase timing setting formula: + * quantum = 1 + (fphaseSeg1 + 1) + (fphaseSeg2 + 1) + fpropSeg; + */ + uint32_t quantum = (1U + ((uint32_t)timingCfg.fphaseSeg1 + 1U) + ((uint32_t)timingCfg.fphaseSeg2 + 1U) + + (uint32_t)timingCfg.fpropSeg); + uint32_t tqFre = pConfig->bitRateFD * quantum; + uint16_t maxDivider; + + /* Check bit rate value. */ + assert((pConfig->bitRateFD <= MAX_CANFD_BITRATE) && (tqFre <= sourceClock_Hz)); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + assert((tqFre * MAX_EDPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_EDPRESDIV; +#else + assert((tqFre * MAX_FPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_FPRESDIV; +#endif + + /* Initialization of classical CAN. */ + FLEXCAN_Init(base, pConfig, sourceClock_Hz); + + /* Check whether Data Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > maxDivider) + { + timingCfg.fpreDivider = maxDivider; + } + else + { + timingCfg.fpreDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + + /* Update actual timing characteristic. */ + FLEXCAN_SetFDTimingConfig(base, &timingCfg); + + /* read FDCTRL register. */ + fdctrl = base->FDCTRL; + + /* Enable FD operation and set bit rate switch. */ + if (brs) + { + fdctrl |= CAN_FDCTRL_FDRATE_MASK; + } + else + { + fdctrl &= ~CAN_FDCTRL_FDRATE_MASK; + } + + /* Before use "|=" operation for multi-bits field, CPU should clean previous Setting. */ + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR0_MASK) | CAN_FDCTRL_MBDSR0(dataSize); +#if defined(CAN_FDCTRL_MBDSR1_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR1_MASK) | CAN_FDCTRL_MBDSR1(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR2_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR2_MASK) | CAN_FDCTRL_MBDSR2(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR3_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR3_MASK) | CAN_FDCTRL_MBDSR3(dataSize); +#endif + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + /* Enable CAN FD operation. */ + base->MCR |= CAN_MCR_FDEN_MASK; + /* Clear SMP bit when CAN FD is enabled (CAN FD only can use one regular sample point plus one optional secondary + * sampling point). */ + base->CTRL1 &= ~CAN_CTRL1_SMP_MASK; + + if (brs && !(pConfig->enableLoopBack)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* The TDC offset should be configured as shown in this equation : offset = DTSEG1 + 2 */ + if (((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U) < + MAX_ETDCOFF) + { + base->ETDC = + CAN_ETDC_ETDCEN_MASK | CAN_ETDC_TDMDIS(!pConfig->enableTransceiverDelayMeasure) | + CAN_ETDC_ETDCOFF(((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U)); + } + else + { + /* Enable the Transceiver Delay Compensation */ + base->ETDC = CAN_ETDC_ETDCEN_MASK | CAN_ETDC_TDMDIS(!pConfig->enableTransceiverDelayMeasure) | + CAN_ETDC_ETDCOFF(MAX_ETDCOFF); + } +#else + /* The TDC offset should be configured as shown in this equation : offset = PSEG1 + PROPSEG + 2 */ + if (((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U) < + MAX_TDCOFF) + { + fdctrl = + (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | + CAN_FDCTRL_TDCOFF(((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U)); + } + else + { + fdctrl = (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | CAN_FDCTRL_TDCOFF(MAX_TDCOFF); + } + /* Enable the Transceiver Delay Compensation */ + fdctrl = (fdctrl & ~CAN_FDCTRL_TDCEN_MASK) | CAN_FDCTRL_TDCEN_MASK; +#endif + } + + /* update the FDCTL register. */ + base->FDCTRL = fdctrl; + + /* Enable CAN FD ISO mode by default. */ + base->CTRL2 |= CAN_CTRL2_ISOCANFDEN_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + /* Reset all Register Contents. */ + FLEXCAN_Reset(base); + + /* Disable FlexCAN module. */ + FLEXCAN_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Disable FlexCAN serial clock. */ + (void)CLOCK_DisableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ + /* Disable FlexCAN clock. */ + (void)CLOCK_DisableClock(s_flexcanClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig->bitRate = 1000000U; + * flexcanConfig->bitRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->disableSelfReception = false; + * flexcanConfig->enableListenOnlyMode = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig->enablePretendedeNetworking = false; + * flexcanConfig->enableMemoryErrorControl = true; + * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; + * flexcanConfig->enableTransceiverDelayMeasure = true; + * flexcanConfig.timingConfig = timingConfig; + * + * param pConfig Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Initializes the configure structure to zero. */ + (void)memset(pConfig, 0, sizeof(*pConfig)); + + /* Initialize FlexCAN Module config struct with default value. */ + pConfig->clkSrc = kFLEXCAN_ClkSrc0; + pConfig->bitRate = 1000000U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + pConfig->bitRateFD = 2000000U; +#endif + pConfig->maxMbNum = 16; + pConfig->enableLoopBack = false; + pConfig->enableTimerSync = true; + pConfig->enableSelfWakeup = false; + pConfig->wakeupSrc = kFLEXCAN_WakeupSrcUnfiltered; + pConfig->enableIndividMask = false; + pConfig->disableSelfReception = false; + pConfig->enableListenOnlyMode = false; +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + pConfig->enableSupervisorMode = true; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + pConfig->enableDoze = false; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + pConfig->enablePretendedeNetworking = false; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + pConfig->enableMemoryErrorControl = true; + pConfig->enableNonCorrectableErrorEnterFreeze = true; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + pConfig->enableTransceiverDelayMeasure = true; +#endif + + /* Default protocol timing configuration, nominal bit time quantum is 10 (80% SP), data bit time quantum is 5 + * (60%). Suggest use FLEXCAN_CalculateImprovedTimingValues/FLEXCAN_FDCalculateImprovedTimingValues to get the + * improved timing configuration.*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + pConfig->timingConfig.phaseSeg1 = 1; + pConfig->timingConfig.phaseSeg2 = 1; + pConfig->timingConfig.propSeg = 4; + pConfig->timingConfig.rJumpwidth = 1; + pConfig->timingConfig.fphaseSeg1 = 1; + pConfig->timingConfig.fphaseSeg2 = 1; + pConfig->timingConfig.fpropSeg = 0; + pConfig->timingConfig.frJumpwidth = 1; +#else + pConfig->timingConfig.phaseSeg1 = 1; + pConfig->timingConfig.phaseSeg2 = 1; + pConfig->timingConfig.propSeg = 4; + pConfig->timingConfig.rJumpwidth = 1; +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * brief Configures the FlexCAN Pretended Networking mode. + * + * This function configures the FlexCAN Pretended Networking mode with given configuration. + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the FlexCAN Rx FIFO configuration structure. + */ +void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + assert(0U != pConfig->matchNum); + uint32_t pnctrl; + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + pnctrl = (pConfig->matchNum > 1U) ? CAN_CTRL1_PN_FCS(0x2U | (uint32_t)pConfig->matchSrc) : + CAN_CTRL1_PN_FCS(pConfig->matchSrc); + pnctrl |= (pConfig->enableMatch) ? (CAN_CTRL1_PN_WUMF_MSK_MASK) : 0U; + pnctrl |= (pConfig->enableTimeout) ? (CAN_CTRL1_PN_WTOF_MSK_MASK) : 0U; + pnctrl |= CAN_CTRL1_PN_NMATCH(pConfig->matchNum) | CAN_CTRL1_PN_IDFS(pConfig->idMatchMode) | + CAN_CTRL1_PN_PLFS(pConfig->dataMatchMode); + base->CTRL1_PN = pnctrl; + base->CTRL2_PN = CAN_CTRL2_PN_MATCHTO(pConfig->timeoutValue); + base->FLT_ID1 = pConfig->idLower; + base->FLT_ID2_IDMASK = pConfig->idUpper; + base->FLT_DLC = CAN_FLT_DLC_FLT_DLC_LO(pConfig->lengthLower) | CAN_FLT_DLC_FLT_DLC_HI(pConfig->lengthUpper); + base->PL1_LO = pConfig->lowerWord0; + base->PL1_HI = pConfig->lowerWord1; + base->PL2_PLMASK_LO = pConfig->upperWord0; + base->PL2_PLMASK_HI = pConfig->upperWord1; + + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag); + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Reads a FlexCAN Message from Wake Up MB. + * + * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers + * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The + * last message is stored in WMB3. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN message frame structure for reception. + * param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3. + * retval kStatus_Success - Read Message from Wake up Message Buffer successfully. + * retval kStatus_Fail - Wake up Message Buffer has no valid content. + */ +status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + assert(mbIdx <= 0x3U); + + uint32_t cs_temp; + status_t status; + + /* Check if Wake Up MB has valid content. */ + if (CAN_WU_MTC_MCOUNTER(mbIdx) < (base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK)) + { + /* Read CS field of wake up Message Buffer. */ + cs_temp = base->WMB[mbIdx].CS; + + /* Store Message ID. */ + pRxFrame->id = base->WMB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Messages received during Pretended Networking mode don't have time stamps, and the respective field in the + WMB structure must be ignored. */ + pRxFrame->timestamp = 0x0; + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->WMB[mbIdx].D03; + pRxFrame->dataWord1 = base->WMB[mbIdx].D47; + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Sets the FlexCAN classical protocol timing characteristic. + * + * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_GetDefaultConfig() + * and get the default timing characteristicsthe, then call FLEXCAN_Init() and fill the + * bit rate field. + * + * note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Enable extended Bit Timing register ENCBT. */ + base->CTRL2 |= CAN_CTRL2_BTE_MASK; + + /* Updating Timing Setting according to configuration structure. */ + base->EPRS = (base->EPRS & (~CAN_EPRS_ENPRESDIV_MASK)) | CAN_EPRS_ENPRESDIV(pConfig->preDivider); + base->ENCBT = CAN_ENCBT_NRJW(pConfig->rJumpwidth) | + CAN_ENCBT_NTSEG1((uint32_t)pConfig->phaseSeg1 + pConfig->propSeg + 1U) | + CAN_ENCBT_NTSEG2(pConfig->phaseSeg2); +#else + /* On RT106x devices, a single write may be ignored, so it is necessary to read back the register value to + * determine whether the value is written successfully. */ + + do + { + /* Enable Bit Timing register CBT, updating Timing Setting according to configuration structure. */ + base->CBT = CAN_CBT_BTF_MASK | CAN_CBT_EPRESDIV(pConfig->preDivider) | CAN_CBT_ERJW(pConfig->rJumpwidth) | + CAN_CBT_EPSEG1(pConfig->phaseSeg1) | CAN_CBT_EPSEG2(pConfig->phaseSeg2) | + CAN_CBT_EPROPSEG(pConfig->propSeg); + + } while ((CAN_CBT_EPRESDIV(pConfig->preDivider) | CAN_CBT_ERJW(pConfig->rJumpwidth) | + CAN_CBT_EPSEG1(pConfig->phaseSeg1) | CAN_CBT_EPSEG2(pConfig->phaseSeg2) | + CAN_CBT_EPROPSEG(pConfig->propSeg)) != + (base->CBT & (CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_EPROPSEG_MASK))); +#endif + } + else + { + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | + CAN_CTRL1_PSEG1(pConfig->phaseSeg1) | CAN_CTRL1_PSEG2(pConfig->phaseSeg2) | + CAN_CTRL1_PROPSEG(pConfig->propSeg)); + } +#else + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | + CAN_CTRL1_PSEG1(pConfig->phaseSeg1) | CAN_CTRL1_PSEG2(pConfig->phaseSeg2) | + CAN_CTRL1_PROPSEG(pConfig->propSeg)); +#endif + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sets the FlexCAN FD data phase timing characteristic. + * + * This function gives user settings to CAN FD data phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_GetDefaultConfig() + * and get the default timing characteristicsthe, then call FLEXCAN_FDInit() and fill the + * data phase bit rate field. + * + * note Calling FLEXCAN_SetFDTimingConfig() overrides the bit rate set + * in FLEXCAN_FDInit(). + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Enable extended Bit Timing register EDCBT. */ + base->CTRL2 |= CAN_CTRL2_BTE_MASK; + + base->EPRS = (base->EPRS & (~CAN_EPRS_EDPRESDIV_MASK)) | CAN_EPRS_EDPRESDIV(pConfig->fpreDivider); + base->EDCBT = CAN_EDCBT_DRJW(pConfig->frJumpwidth) | CAN_EDCBT_DTSEG2(pConfig->fphaseSeg2) | + CAN_EDCBT_DTSEG1((uint32_t)pConfig->fphaseSeg1 + pConfig->fpropSeg); +#else + /* Enable Bit Timing register FDCBT,*/ + base->CBT |= CAN_CBT_BTF_MASK; + + /* On RT106x devices, a single write may be ignored, so it is necessary to read back the register value to determine + * whether the value is written successfully. */ + do + { + /* Updating Timing Setting according to configuration structure. */ + base->FDCBT = (CAN_FDCBT_FPRESDIV(pConfig->fpreDivider) | CAN_FDCBT_FRJW(pConfig->frJumpwidth) | + CAN_FDCBT_FPSEG1(pConfig->fphaseSeg1) | CAN_FDCBT_FPSEG2(pConfig->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(pConfig->fpropSeg)); + } while ((CAN_FDCBT_FPRESDIV(pConfig->fpreDivider) | CAN_FDCBT_FRJW(pConfig->frJumpwidth) | + CAN_FDCBT_FPSEG1(pConfig->fphaseSeg1) | CAN_FDCBT_FPSEG2(pConfig->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(pConfig->fpropSeg)) != + (base->FDCBT & (CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | + CAN_FDCBT_FPSEG2_MASK | CAN_FDCBT_FPROPSEG_MASK))); +#endif + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Message Buffer Global Mask value. */ + base->RXMGMASK = mask; + base->RX14MASK = mask; + base->RX15MASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * param base FlexCAN peripheral base address. + * param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx FIFO Global Mask value. */ + base->RXFGMASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * param base FlexCAN peripheral base address. + * param maskIdx The Index of individual Mask. + * param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +{ + assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Individual Mask value. */ + base->RXIMR[maskIdx] = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + base->MB[mbIdx].CS = 0; + } + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; +} + +/*! + * brief Calculates the segment values for a single bit time for classical CAN. + * + * This function use to calculates the Classical CAN segment values which will be set in CTRL1/CBT/ENCBT register. + * + * param bitRate The classical CAN bit rate in bps. + * param base FlexCAN peripheral base address. + * param tqNum Number of time quantas per bit, range in 8 ~ 25 when use CTRL1, range in 8 ~ 129 when use CBT, range in + * 8 ~ 385 when use ENCBT. param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_GetSegments(CAN_Type *base, + uint32_t bitRate, + uint32_t tqNum, + flexcan_timing_config_t *pTimingConfig) +{ + uint32_t ideal_sp; + uint32_t seg1Max, proSegMax; + uint32_t seg1Temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Maximum value allowed in ENCBT register. */ + seg1Max = MAX_NTSEG2 + 1U; + proSegMax = MAX_NTSEG1 - MAX_NTSEG2; +#else + /* Maximum value allowed in CBT register. */ + seg1Max = MAX_EPSEG1 + 1U; + proSegMax = MAX_EPROPSEG + 1U; +#endif + } + else + { + /* Maximum value allowed in CTRL1 register. */ + seg1Max = MAX_PSEG1 + 1U; + proSegMax = MAX_PROPSEG + 1U; + } +#else + /* Maximum value allowed in CTRL1 register. */ + seg1Max = MAX_PSEG1 + 1U; + proSegMax = MAX_PROPSEG + 1U; +#endif + + /* Try to find the ideal sample point, according to CiA 301 doc.*/ + if (bitRate == 1000000U) + { + ideal_sp = IDEAL_SP_LOW; + } + else if (bitRate >= 800000U) + { + ideal_sp = IDEAL_SP_MID; + } + else + { + ideal_sp = IDEAL_SP_HIGH; + } + /* Calculates phaseSeg2. */ + pTimingConfig->phaseSeg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR); + if (pTimingConfig->phaseSeg2 < MIN_TIME_SEGMENT2) + { + pTimingConfig->phaseSeg2 = MIN_TIME_SEGMENT2; + } + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + if (pTimingConfig->phaseSeg2 > (uint8_t)(MAX_EPSEG2 + 1U)) + { + pTimingConfig->phaseSeg2 = (uint8_t)(MAX_EPSEG2 + 1U); + } +#endif + } +#endif + + /* Calculates phaseSeg1 and propSeg and try to make phaseSeg1 equal to phaseSeg2. */ + if ((tqNum - pTimingConfig->phaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + pTimingConfig->phaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - pTimingConfig->phaseSeg2 - 1U; + } + if (seg1Temp > (pTimingConfig->phaseSeg2 + proSegMax)) + { + pTimingConfig->propSeg = (uint8_t)proSegMax; + pTimingConfig->phaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else + { + pTimingConfig->propSeg = (uint8_t)(seg1Temp - pTimingConfig->phaseSeg2); + pTimingConfig->phaseSeg1 = pTimingConfig->phaseSeg2; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + pTimingConfig->rJumpwidth = + (pTimingConfig->phaseSeg1 > pTimingConfig->phaseSeg2) ? pTimingConfig->phaseSeg2 : pTimingConfig->phaseSeg1; +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (pTimingConfig->rJumpwidth > (MAX_RJW + 1U)) + { + pTimingConfig->rJumpwidth = (uint8_t)(MAX_RJW + 1U); + } +#else + if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + if (pTimingConfig->rJumpwidth > (MAX_RJW + 1U)) + { + pTimingConfig->rJumpwidth = (uint8_t)(MAX_RJW + 1U); + } + } +#endif + + pTimingConfig->phaseSeg1 -= 1U; + pTimingConfig->phaseSeg2 -= 1U; + pTimingConfig->propSeg -= 1U; + pTimingConfig->rJumpwidth -= 1U; +} + +/*! + * brief Calculates the improved timing values by specific bit Rates for classical CAN. + * + * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated + * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 + * v4.2.0 and previous version document. + * + * param base FlexCAN peripheral base address. + * param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums. */ + assert(bitRate <= MAX_CAN_BITRATE); + + uint32_t clk; + uint32_t tqNum, tqMin, pdivMAX; + uint32_t spTemp = 1000U; + flexcan_timing_config_t configTemp = {0}; + bool fgRet = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for ENCBT. */ + tqNum = ENCBT_MAX_TIME_QUANTA; + tqMin = ENCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_ENPRESDIV; +#else + /* Auto Improved Protocal timing for CBT. */ + tqNum = CBT_MAX_TIME_QUANTA; + tqMin = CBT_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; +#endif + } + else + { + /* Auto Improved Protocal timing for CTRL1. */ + tqNum = CTRL1_MAX_TIME_QUANTA; + tqMin = CTRL1_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; + } +#else + /* Auto Improved Protocal timing for CTRL1. */ + tqNum = CTRL1_MAX_TIME_QUANTA; + tqMin = CTRL1_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; +#endif + do + { + clk = bitRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate, the user + should change a divisible bit rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + if (configTemp.preDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider could + not handle it. */ + } + + /* Calculates the best timing configuration under current tqNum. */ + FLEXCAN_GetSegments(base, bitRate, tqNum, &configTemp); + /* Determine whether the calculated timing configuration can get the optimal sampling point. */ + if (((((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum; + pTimingConfig->preDivider = configTemp.preDivider; + pTimingConfig->rJumpwidth = configTemp.rJumpwidth; + pTimingConfig->phaseSeg1 = configTemp.phaseSeg1; + pTimingConfig->phaseSeg2 = configTemp.phaseSeg2; + pTimingConfig->propSeg = configTemp.propSeg; + } + fgRet = true; + } while (--tqNum >= tqMin); + + return fgRet; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * param base FlexCAN peripheral base address. + * param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t offset = 0; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + if (dataSize == (uint32_t)kFLEXCAN_8BperMB) + { + offset = (((uint32_t)mbIdx / 32U) * 512U + ((uint32_t)mbIdx % 32U) * 16U); + } + else if (dataSize == (uint32_t)kFLEXCAN_16BperMB) + { + offset = (((uint32_t)mbIdx / 21U) * 512U + ((uint32_t)mbIdx % 21U) * 24U); + } + else if (dataSize == (uint32_t)kFLEXCAN_32BperMB) + { + offset = (((uint32_t)mbIdx / 12U) * 512U + ((uint32_t)mbIdx % 12U) * 40U); + } + else + { + offset = (((uint32_t)mbIdx / 7U) * 512U + ((uint32_t)mbIdx % 7U) * 72U); + } + + /* To get the dword aligned offset, need to divide by 4. */ + offset = offset / 4U; + return offset; +} + +/*! + * brief Calculates the segment values for a single bit time for CAN FD data phase. + * + * This function use to calculates the CAN FD data phase segment values which will be set in CFDCBT/EDCBT + * register. + * + * param bitRateFD CAN FD data phase bit rate. + * param tqNum Number of time quanta per bit + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_FDGetSegments(uint32_t bitRateFD, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig) +{ + uint32_t ideal_sp; + uint32_t seg1Max, proSegMax, seg2Max; + uint32_t seg1Temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Maximum value allowed in EDCBT register. */ + seg1Max = MAX_DTSEG2 + 1U; + proSegMax = MAX_DTSEG1 - MAX_DTSEG2; + seg2Max = MAX_DTSEG2 + 1U; +#else + /* Maximum value allowed in FDCBT register. */ + seg1Max = MAX_FPSEG1 + 1U; + proSegMax = MAX_FPROPSEG; + seg2Max = MAX_FPSEG2 + 1U; +#endif + + /* According to CiA doc 1301 v1.0.0, which specified data phase sample point postion for CAN FD at 80 MHz. */ + if (bitRateFD <= 1000000U) + { + ideal_sp = IDEAL_DATA_SP_1; + } + else if (bitRateFD <= 2000000U) + { + ideal_sp = IDEAL_DATA_SP_2; + } + else if (bitRateFD <= 4000000U) + { + ideal_sp = IDEAL_DATA_SP_3; + } + else + { + ideal_sp = IDEAL_DATA_SP_4; + } + + /* Calculates fphaseSeg2. */ + pTimingConfig->fphaseSeg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR); + if (pTimingConfig->fphaseSeg2 < MIN_TIME_SEGMENT2) + { + pTimingConfig->fphaseSeg2 = MIN_TIME_SEGMENT2; + } + else if (pTimingConfig->fphaseSeg2 > seg2Max) + { + pTimingConfig->fphaseSeg2 = (uint8_t)seg2Max; + } + else + { + ; /* Intentional empty */ + } + + /* Calculates fphaseSeg1 and fpropSeg and try to make phaseSeg1 equal to phaseSeg2 */ + if ((tqNum - pTimingConfig->fphaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + pTimingConfig->fphaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - pTimingConfig->fphaseSeg2 - 1U; + } + if (seg1Temp > (pTimingConfig->fphaseSeg2 + proSegMax)) + { + pTimingConfig->fpropSeg = (uint8_t)proSegMax; + pTimingConfig->fphaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else if (seg1Temp > pTimingConfig->fphaseSeg2) + { + pTimingConfig->fpropSeg = (uint8_t)(seg1Temp - pTimingConfig->fphaseSeg2); + pTimingConfig->fphaseSeg1 = pTimingConfig->fphaseSeg2; + } + else + { + pTimingConfig->fpropSeg = 0U; + pTimingConfig->fphaseSeg1 = (uint8_t)seg1Temp; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + pTimingConfig->frJumpwidth = + (pTimingConfig->fphaseSeg1 > pTimingConfig->fphaseSeg2) ? pTimingConfig->fphaseSeg2 : pTimingConfig->fphaseSeg1; + + pTimingConfig->fphaseSeg1 -= 1U; + pTimingConfig->fphaseSeg2 -= 1U; + pTimingConfig->frJumpwidth -= 1U; +} + +/*! + * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The Calculated timing values will be set in CBT/ENCBT registers. The calculation is based on the recommendation of + * the CiA 1301 v1.0.0 document. + * + * param bitRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool FLEXCAN_CalculateImprovedNominalTimingValues(uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums. */ + assert(bitRate <= MAX_CAN_BITRATE); + + uint32_t clk; + uint32_t tqNum, tqMin, pdivMAX, seg1Max, proSegMax, seg1Temp; + uint32_t spTemp = 1000U; + flexcan_timing_config_t configTemp = {0}; + bool fgRet = false; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for ENCBT. */ + tqNum = ENCBT_MAX_TIME_QUANTA; + tqMin = ENCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_ENPRESDIV; + seg1Max = MAX_NTSEG2 + 1U; + proSegMax = MAX_NTSEG1 - MAX_NTSEG2; +#else + /* Auto Improved Protocal timing for CBT. */ + tqNum = CBT_MAX_TIME_QUANTA; + tqMin = CBT_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; + seg1Max = MAX_EPSEG1 + 1U; + proSegMax = MAX_EPROPSEG + 1U; +#endif + + do + { + clk = bitRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate, the user + should change a divisible bit rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + if (configTemp.preDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider could + not handle it. */ + } + + /* Calculates the best timing configuration under current tqNum. */ + configTemp.phaseSeg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR); + + /* Calculates phaseSeg1 and propSeg and try to make phaseSeg1 equal to phaseSeg2. */ + if ((tqNum - configTemp.phaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + configTemp.phaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - configTemp.phaseSeg2 - 1U; + } + if (seg1Temp > (configTemp.phaseSeg2 + proSegMax)) + { + configTemp.propSeg = (uint8_t)proSegMax; + configTemp.phaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else + { + configTemp.propSeg = (uint8_t)(seg1Temp - configTemp.phaseSeg2); + configTemp.phaseSeg1 = configTemp.phaseSeg2; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + configTemp.rJumpwidth = + (configTemp.phaseSeg1 > configTemp.phaseSeg2) ? configTemp.phaseSeg2 : configTemp.phaseSeg1; + configTemp.phaseSeg1 -= 1U; + configTemp.phaseSeg2 -= 1U; + configTemp.propSeg -= 1U; + configTemp.rJumpwidth -= 1U; + + if (((((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum; + pTimingConfig->preDivider = configTemp.preDivider; + pTimingConfig->rJumpwidth = configTemp.rJumpwidth; + pTimingConfig->phaseSeg1 = configTemp.phaseSeg1; + pTimingConfig->phaseSeg2 = configTemp.phaseSeg2; + pTimingConfig->propSeg = configTemp.propSeg; + } + fgRet = true; + } while (--tqNum >= tqMin); + + return fgRet; +} + +/*! + * brief Calculates the improved timing values by specific bit rates for CAN FD. + * + * This function use to calculates the CAN FD timing values according to the given nominal phase bit rate and data phase + * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based + * on the recommendation of the CiA 1301 v1.0.0 document. + * + * param bitRate The CAN FD nominal phase speed in bps defined by user. + * param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate + * switching. param sourceClock_Hz The Source clock frequency in Hz. param pTimingConfig Pointer to the FlexCAN timing + * configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t bitRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums */ + assert(bitRate <= MAX_CANFD_BITRATE); + assert(bitRateFD <= MAX_CANFD_BITRATE); + /* Data phase bit rate need greater or equal to nominal phase bit rate. */ + assert(bitRate <= bitRateFD); + + uint32_t clk; + uint32_t tqMin, pdivMAX, tqTemp; + bool fgRet = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for EDCBT. */ + tqTemp = EDCBT_MAX_TIME_QUANTA; + tqMin = EDCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_EDPRESDIV; +#else + /* Auto Improved Protocal timing for FDCBT. */ + tqTemp = FDCBT_MAX_TIME_QUANTA; + tqMin = FDCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_FPRESDIV; +#endif + + if (bitRate != bitRateFD) + { + /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase + and data phase. */ + do + { + clk = bitRateFD * tqTemp; + if (clk > sourceClock_Hz) + { + continue; /* tqTemp too large, clk x tqTemp has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* the frequency of clock source is not divisible by target bit rate. */ + } + + pTimingConfig->fpreDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + + if (pTimingConfig->fpreDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider + could not handle it. */ + } + + /* Calculates the best data phase timing configuration. */ + FLEXCAN_FDGetSegments(bitRateFD, tqTemp, pTimingConfig); + + if (FLEXCAN_CalculateImprovedNominalTimingValues( + bitRate, sourceClock_Hz / ((uint32_t)pTimingConfig->fpreDivider + 1U), pTimingConfig)) + { + fgRet = true; + if (pTimingConfig->preDivider == 0U) + { + pTimingConfig->preDivider = pTimingConfig->fpreDivider; + break; + } + else + { + pTimingConfig->preDivider = + (pTimingConfig->preDivider + 1U) * (pTimingConfig->fpreDivider + 1U) - 1U; + continue; + } + } + } while (--tqTemp >= tqMin); + } + else + { + if (FLEXCAN_CalculateImprovedNominalTimingValues(bitRate, sourceClock_Hz, pTimingConfig)) + { + /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs + feature. */ + pTimingConfig->fpreDivider = 0U; + pTimingConfig->frJumpwidth = 0U; + pTimingConfig->fphaseSeg1 = 0U; + pTimingConfig->fphaseSeg2 = 0U; + pTimingConfig->fpropSeg = 0U; + fgRet = true; + } + } + return fgRet; +} + +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint8_t cnt = 0; + uint8_t payload_dword = 1; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + /* Inactivate by writing CS. */ + mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + mbAddr[offset] = 0x0; + } + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Clean ID. */ + mbAddr[offset + 1U] = 0x0U; + /* Clean Message Buffer content, DWORD by DWORD. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0U; + } + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE */ + +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != pRxMbConfig) || (false == enable))); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + + /* Inactivate Message Buffer. */ + base->MB[mbIdx].CS = 0; + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; + + if (enable) + { + /* Setup Message Buffer ID. */ + base->MB[mbIdx].ID = pRxMbConfig->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == pRxMbConfig->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == pRxMbConfig->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + base->MB[mbIdx].CS = cs_temp; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != pRxMbConfig) || (false == enable))); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + uint8_t cnt = 0; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + uint8_t payload_dword; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + + /* Inactivate Message Buffer. */ + mbAddr[offset] = 0U; + + /* Clean Message Buffer content. */ + mbAddr[offset + 1U] = 0U; + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + payload_dword = (2U << dataSize); + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0; + } + + if (enable) + { + /* Setup Message Buffer ID. */ + mbAddr[offset + 1U] = pRxMbConfig->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == pRxMbConfig->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == pRxMbConfig->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + mbAddr[offset] = cs_temp; + } +} +#endif + +/*! + * brief Configures the FlexCAN Legacy Rx FIFO. + * + * This function configures the FlexCAN Rx FIFO with given configuration. + * note Legacy Rx FIFO only can receive classic CAN message. + * + * param base FlexCAN peripheral base address. + * param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * param enable Enable/disable Legacy Rx FIFO. + * - true: Enable Legacy Rx FIFO. + * - false: Disable Legacy Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable) +{ + /* Assertion. */ + assert((NULL != pRxFifoConfig) || (false == enable)); + + volatile uint32_t *mbAddr; + uint8_t i, j, k, rffn = 0, numMbOccupy; + uint32_t setup_mb = 0; + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + assert(pRxFifoConfig->idFilterNum <= 128U); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time. */ + assert((base->ERFCR & CAN_ERFCR_ERFEN_MASK) == 0U); +#endif + + /* Get the setup_mb value. */ + setup_mb = (uint8_t)((base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT); + setup_mb = (setup_mb < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? + setup_mb : + (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); + + /* Determine RFFN value. */ + for (i = 0; i <= 0xFU; i++) + { + if ((8U * (i + 1U)) >= pRxFifoConfig->idFilterNum) + { + rffn = i; + assert(((setup_mb - 8U) - (2U * rffn)) > 0U); + + base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); + break; + } + } + + /* caculate the Number of Mailboxes occupied by RX Legacy FIFO and the filter. */ + numMbOccupy = 6U + (rffn + 1U) * 2U; + + /* Copy ID filter table to Message Buffer Region (Fix MISRA_C-2012 Rule 18.1). */ + j = 0U; + for (i = 6U; i < numMbOccupy; i++) + { + /* Get address for current mail box. */ + mbAddr = &(base->MB[i].CS); + + /* One Mail box contain 4U DWORD registers. */ + for (k = 0; k < 4U; k++) + { + /* Fill all valid filter in the mail box occupied by filter. + * Disable unused Rx FIFO Filter, the other rest of register in the last Mail box occupied by fiter set + * as 0xffffffff. + */ + mbAddr[k] = (j < pRxFifoConfig->idFilterNum) ? (pRxFifoConfig->idFilterTable[j]) : 0xFFFFFFFFU; + + /* Try to fill next filter in current Mail Box. */ + j++; + } + } + + /* Setup ID Fitlter Type. */ + switch (pRxFifoConfig->idFilterType) + { + case kFLEXCAN_RxFifoFilterTypeA: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); + break; + case kFLEXCAN_RxFifoFilterTypeB: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); + break; + case kFLEXCAN_RxFifoFilterTypeC: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); + break; + case kFLEXCAN_RxFifoFilterTypeD: + /* All frames rejected. */ + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (pRxFifoConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) : + (base->CTRL2 | CAN_CTRL2_MRP_MASK); + + /* Enable Rx Message FIFO. */ + base->MCR |= CAN_MCR_RFEN_MASK; + } + else + { + rffn = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* caculate the Number of Mailboxes occupied by RX Legacy FIFO and the filter. */ + numMbOccupy = 6U + (rffn + 1U) * 2U; + + /* Disable Rx Message FIFO. */ + base->MCR &= ~CAN_MCR_RFEN_MASK; + + /* Clean MB0 ~ MB5 and all MB occupied by ID filters (Fix MISRA_C-2012 Rule 18.1). */ + + for (i = 0; i < numMbOccupy; i++) + { + FLEXCAN_SetRxMbConfig(base, i, NULL, false); + } + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Configures the FlexCAN Enhanced Rx FIFO. + * + * This function configures the Enhanced Rx FIFO with given configuration. + * note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO + * cannot be enabled at the same time. + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * param enable Enable/disable Enhanced Rx FIFO. + * - true: Enable Enhanced Rx FIFO. + * - false: Disable Enhanced Rx FIFO. + */ +void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable) +{ + /* Assertion. */ + assert((NULL != pConfig) || (false == enable)); + uint32_t i; + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + /* Each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two + * standard ID filter elements. */ + assert((((uint32_t)pConfig->idFilterPairNum * 2UL) < + (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER) && + (pConfig->extendIdFilterNum <= pConfig->idFilterPairNum) && (0UL != pConfig->idFilterPairNum)); + + /* The Enhanced Rx FIFO Watermark cannot be greater than the enhanced Rx FIFO size. */ + assert(pConfig->fifoWatermark < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE); + + /* Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time. */ + assert((base->MCR & CAN_MCR_RFEN_MASK) == 0U); + + /* Reset Enhanced Rx FIFO engine and clear flags. */ + base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | + CAN_ERFSR_ERFDA_MASK; + /* Setting Enhanced Rx FIFO. */ + base->ERFCR = CAN_ERFCR_DMALW(pConfig->dmaPerReadLength) | CAN_ERFCR_NEXIF(pConfig->extendIdFilterNum) | + CAN_ERFCR_NFE((uint32_t)pConfig->idFilterPairNum - 1UL) | CAN_ERFCR_ERFWM(pConfig->fifoWatermark); + /* Copy ID filter table to Enhanced Rx FIFO Filter Element registers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER; i++) + { + base->ERFFEL[i] = (i < ((uint32_t)pConfig->idFilterPairNum * 2U)) ? pConfig->idFilterTable[i] : 0xFFFFFFFFU; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (pConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) : + (base->CTRL2 | CAN_CTRL2_MRP_MASK); + /* Enable Enhanced Rx FIFO. */ + base->ERFCR |= CAN_ERFCR_ERFEN_MASK; + } + else + { + /* Disable Enhanced Rx FIFO. */ + base->ERFCR = 0U; + /* Reset Enhanced Rx FIFO engine and clear flags. */ + base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | + CAN_ERFSR_ERFDA_MASK; + /* Clean all Enhanced Rx FIFO Filter Element registers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER; i++) + { + base->ERFFEL[i] = 0xFFFFFFFFU; + } + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * brief Enables or disables the FlexCAN Legacy/Enhanced Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) +{ + if (enable) + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Enable FlexCAN DMA. */ + base->MCR |= CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } + else + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Disable FlexCAN DMA. */ + base->MCR &= ~CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * brief Gets the FlexCAN Memory Error Report registers status. + * + * This function gets the FlexCAN Memory Error Report registers status. + * + * param base FlexCAN peripheral base address. + * param errorStatus Pointer to FlexCAN Memory Error Report registers status structure. + */ +void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus) +{ + uint32_t temp; + /* Disable updates of the error report registers. */ + base->MECR |= CAN_MECR_RERRDIS_MASK; + + errorStatus->accessAddress = (uint16_t)(base->RERRAR & CAN_RERRAR_ERRADDR_MASK); + errorStatus->errorData = base->RERRDR; + errorStatus->errorType = + (base->RERRAR & CAN_RERRAR_NCE_MASK) == 0U ? kFLEXCAN_CorrectableError : kFLEXCAN_NonCorrectableError; + + temp = (base->RERRAR & CAN_RERRAR_SAID_MASK) >> CAN_RERRAR_SAID_SHIFT; + switch (temp) + { + case (uint32_t)kFLEXCAN_MoveOutFlexCanAccess: + case (uint32_t)kFLEXCAN_MoveInAccess: + case (uint32_t)kFLEXCAN_TxArbitrationAccess: + case (uint32_t)kFLEXCAN_RxMatchingAccess: + case (uint32_t)kFLEXCAN_MoveOutHostAccess: + errorStatus->accessType = (flexcan_memory_access_type_t)temp; + break; + default: + assert(false); + break; + } + + for (uint32_t i = 0; i < 4U; i++) + { + temp = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_SYND0_MASK << (i * 8U))) >> (i * 8U); + errorStatus->byteStatus[i].byteIsRead = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_BE0_MASK << (i * 8U))) != 0U; + switch (temp) + { + case CAN_RERRSYNR_SYND0(kFLEXCAN_NoError): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits0Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits1Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits2Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits3Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits4Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits0Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits1Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits2Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits3Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits4Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits5Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits6Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits7Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_AllZeroError): + case CAN_RERRSYNR_SYND0(kFLEXCAN_AllOneError): + errorStatus->byteStatus[i].bitAffected = (flexcan_byte_error_syndrome_t)temp; + break; + default: + errorStatus->byteStatus[i].bitAffected = kFLEXCAN_NonCorrectableErrors; + break; + } + } + + /* Re-enable updates of the error report registers. */ + base->MECR &= CAN_MECR_RERRDIS_MASK; +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! + * FlexCAN: A frame with wrong ID or payload is transmitted into + * the CAN bus when the Message Buffer under transmission is + * either aborted or deactivated while the CAN bus is in the Bus Idle state + * + * This function to do workaround for ERR006032 + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + */ +static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr) +{ + uint32_t dbg_temp = 0U; + uint32_t u32TempCS = 0U; + uint32_t u32Timeout = DELAY_BUSIDLE; + /*disable ALL interrupts to prevent any context switching*/ + uint32_t irqMask = DisableGlobalIRQ(); + dbg_temp = (uint32_t)(base->DBG1); + switch (dbg_temp & CAN_DBG1_CFSM_MASK) + { + case RXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from RXINTERMISSION */ + while (RXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + case TXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from TXINTERMISSION*/ + while (TXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + default: + /* To avoid MISRA-C 2012 rule 16.4 issue. */ + break; + } + /*Anyway, BUSIDLE need to delay*/ + if (BUSIDLE == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + while (u32Timeout-- > 0U) + { + __NOP(); + } + + /*Write 0x0 into Code field of CS word.*/ + u32TempCS = (uint32_t)(*mbCSAddr); + u32TempCS &= ~CAN_CS_CODE_MASK; + *mbCSAddr = u32TempCS; + } + /*restore interruption*/ + EnableGlobalIRQ(irqMask); +} +#endif + +/*! + * brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pTxFrame); + assert(pTxFrame->length <= 8U); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + status_t status; + + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS)); +#endif + /* Inactive Tx Message Buffer. */ + base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + + /* Fill Message ID field. */ + base->MB[mbIdx].ID = pTxFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == pTxFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pTxFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length); + + /* Load Message Payload. */ + base->MB[mbIdx].WORD0 = pTxFrame->dataWord0; + base->MB[mbIdx].WORD1 = pTxFrame->dataWord1; + + /* Activate Tx Message Buffer. */ + base->MB[mbIdx].CS = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + status = kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pTxFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pTxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + status_t status; + uint32_t cs_temp = 0; + uint8_t cnt = 0; + uint32_t can_cs = 0; + uint8_t payload_dword = 1; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + can_cs = mbAddr[offset]; + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(mbAddr[offset])); +#endif + /* Inactive Tx Message Buffer and Fill Message ID field. */ + mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[offset + 1U] = pTxFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == pTxFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pTxFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length) | CAN_CS_EDL(pTxFrame->edl) | + CAN_CS_BRS(pTxFrame->brs); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Load Message Payload and Activate Tx Message Buffer. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = pTxFrame->dataWord[cnt]; + } + mbAddr[offset] = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + status = kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pRxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp; + uint32_t rx_code; + status_t status; + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[mbIdx].CS; + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if (((uint32_t)kFLEXCAN_RxMbFull == rx_code) || ((uint32_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + pRxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->MB[mbIdx].WORD0; + pRxFrame->dataWord1 = base->MB[mbIdx].WORD1; + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pRxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + status_t status; + uint32_t cs_temp; + uint8_t rx_code; + uint8_t cnt = 0; + uint32_t can_id = 0; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + uint8_t payload_dword = 1; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = mbAddr[offset]; + can_id = mbAddr[offset + 1U]; + + /* Get Rx Message Buffer Code field. */ + rx_code = (uint8_t)((cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT); + + /* Check to see if Rx Message Buffer is full. */ + if (((uint8_t)kFLEXCAN_RxMbFull == rx_code) || ((uint8_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + pRxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get Bit Rate Switch flag. */ + pRxFrame->brs = (cs_temp & CAN_CS_BRS_MASK) != 0U ? 1U : 0U; + + /* Get Extended Data Length flag. */ + pRxFrame->edl = (cs_temp & CAN_CS_EDL_MASK) != 0U ? 1U : 0U; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Store Message Payload. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + pRxFrame->dataWord[cnt] = mbAddr[offset + 2U + cnt]; + } + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Reads a FlexCAN Message from Legacy Rx FIFO. + * + * This function reads a CAN message from the FlexCAN Legacy Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + uint32_t cs_temp; + status_t status; + + /* Check if Legacy Rx FIFO is Enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[0].CS; + + /* Read data from Rx FIFO output port. */ + /* Store Message ID. */ + pRxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->MB[0].WORD0; + pRxFrame->dataWord1 = base->MB[0].WORD1; + + /* Store ID Filter Hit Index. */ + pRxFrame->idhit = (uint16_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Reads a FlexCAN Message from Enhanced Rx FIFO. + * + * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + status_t status; + uint32_t idHitOff; + + /* Check if Enhanced Rx FIFO is Enabled. */ + if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */ + idHitOff = (DLC_LENGTH_DECODE(((flexcan_fd_frame_t *)E_RX_FIFO(base))->length) + 3U) / 4U + 3U; + /* Copy CAN FD Message from Enhanced Rx FIFO, should use the DLC value to identify the bytes that belong to the + * message which is being read. */ + (void)memcpy((void *)pRxFrame, (void *)(uint32_t *)E_RX_FIFO(base), sizeof(uint32_t) * idHitOff); + pRxFrame->idhit = pRxFrame->dataWord[idHitOff - 3U]; + /* Clear the unused frame data. */ + for (uint32_t i = (idHitOff - 3U); i < 16U; i++) + { + pRxFrame->dataWord[i] = 0x0; + } + + /* Clear data available flag to let FlexCAN know one frame has been read from the Enhanced Rx FIFO. */ + base->ERFSR = CAN_ERFSR_ERFDA_MASK; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame) +{ + status_t status; + + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame)) + { + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + + /*After TX MB tranfered success, update the Timestamp from MB[mbIdx].CS register*/ + pTxFrame->timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadRxMb(base, mbIdx, pRxFrame); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pTxFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame) +{ + status_t status; + + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame)) + { + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + /*After TX MB tranfered success, update the Timestamp from base->MB[offset for CAN FD].CS register*/ + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + pTxFrame->timestamp = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadFDRxMb(base, mbIdx, pRxFrame); +} +#endif + +/*! + * brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Legacy Rx FIFO non-empty. */ + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag)) + { + } + + /* Read data from Legacy Rx FIFO. */ + rxFifoStatus = FLEXCAN_ReadRxFifo(base, pRxFrame); + + /* Clean Rx Fifo available flag. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + return rxFifoStatus; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Enhanced Rx FIFO non-empty. */ + while (0U == (FLEXCAN_GetStatusFlags(base) & (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag)) + { + } + + /* Read data from Enhanced Rx FIFO */ + rxFifoStatus = FLEXCAN_ReadEnhancedRxFifo(base, pRxFrame); + + return rxFifoStatus; +} +#endif + +/*! + * brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint8_t instance; + + /* Clean FlexCAN transfer handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = (uint8_t)FLEXCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_flexcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of FlexCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + FLEXCAN_EnableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + | (uint64_t)kFLEXCAN_PNMatchWakeUpInterruptEnable | + (uint64_t)kFLEXCAN_PNTimeoutWakeUpInterruptEnable +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + | (uint64_t)kFLEXCAN_HostAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_FlexCanAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_HostOrFlexCanCErrorInterruptEnable +#endif + ); + } + else + { + FLEXCAN_DisableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + | (uint64_t)kFLEXCAN_PNMatchWakeUpInterruptEnable | + (uint64_t)kFLEXCAN_PNTimeoutWakeUpInterruptEnable +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + | (uint64_t)kFLEXCAN_HostAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_FlexCanAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_HostOrFlexCanCErrorInterruptEnable +#endif + ); + } + + /* Enable interrupts in NVIC. */ + (void)EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); +} + +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pMbXfer->frame->type) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + if (kStatus_Success == + FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame)) + { + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + status = kStatus_Success; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_FLEXCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + status_t status; + + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFrameBuf[pMbXfer->mbIdx] = pMbXfer->frame; + + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxBusy; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pMbXfer->framefd->type) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + if (kStatus_Success == + FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd)) + { + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_FLEXCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFDFrameBuf[pMbXfer->mbIdx] = pMbXfer->framefd; + + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxBusy; + } + + return status; +} +#endif + +/*! + * brief Receives a message from Legacy Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pFifoXfer); + + status_t status; + uint32_t irqMask = (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = pFifoXfer->frame; + handle->rxFifoFrameNum = pFifoXfer->frameNum; + handle->rxFifoTransferTotalNum = pFifoXfer->frameNum; + + if (handle->rxFifoTransferTotalNum < 5U) + { + /* Enable data available interrupt. */ + irqMask |= (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag; + } + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, irqMask); + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + + return status; +} + +/*! + * brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param count Number of CAN messages receive so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + status_t result = kStatus_Success; + + if (handle->rxFifoState == (uint32_t)kFLEXCAN_StateIdle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxFifoTransferTotalNum - handle->rxFifoFrameNum; + } + + return result; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Receives a message from Enhanced Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pFifoXfer); + + status_t status; + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + uint64_t irqMask = + (uint64_t)kFLEXCAN_ERxFifoUnderflowInterruptEnable | (uint64_t)kFLEXCAN_ERxFifoOverflowInterruptEnable; + + /* Check if Enhanced Rx FIFO is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFDFrameBuf = pFifoXfer->framefd; + handle->rxFifoFrameNum = pFifoXfer->frameNum; + handle->rxFifoTransferTotalNum = pFifoXfer->frameNum; + + if (handle->rxFifoTransferTotalNum >= watermark) + { + /* Enable watermark interrupt. */ + irqMask |= (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable; + } + else + { + /* Enable data available interrupt. */ + irqMask |= (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable; + } + /* Enable Enhanced Rx FIFO Interrupt. */ + FLEXCAN_EnableInterrupts(base, irqMask); + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + + return status; +} +#endif + +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + uint16_t timestamp; + + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Update the TX frame 's time stamp by MB[mbIdx].cs. */ + timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + handle->timestamp[mbIdx] = timestamp; + + /* Clean Message Buffer. */ + FLEXCAN_SetTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + volatile uint32_t *mbAddr; + uint32_t offset; + uint16_t timestamp; + + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Update the TX frame 's time stamp by base->MB[offset for CAN FD].CS. */ + mbAddr = &(base->MB[0].CS); + offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + timestamp = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + handle->timestamp[mbIdx] = timestamp; + + /* Clean Message Buffer. */ + FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFDFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} +#endif + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive from Legacy Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Legacy Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + /* Check if Rx FIFO is enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Disable Rx Message FIFO Interrupts. */ + FLEXCAN_DisableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag | + (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + /* Un-register handle. */ + handle->rxFifoFrameBuf = NULL; + /* Clear transfer count. */ + handle->rxFifoFrameNum = 0U; + handle->rxFifoTransferTotalNum = 0U; + } + + handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + /* Check if Enhanced Rx FIFO is enabled. */ + if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + /* Disable all Rx Message FIFO interrupts. */ + FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoOverflowInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable); + + /* Un-register handle. */ + handle->rxFifoFDFrameBuf = NULL; + /* Clear transfer count. */ + handle->rxFifoFrameNum = 0U; + handle->rxFifoTransferTotalNum = 0U; + } + + handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle; +} +#endif + +/*! + * brief Gets the detail index of Mailbox's Timestamp by handle. + * + * Then function can only be used when calling non-blocking Data transfer (TX/RX) API, + * After TX/RX data transfer done (User can get the status by handler's callback function), + * we can get the detail index of Mailbox's timestamp by handle, + * Detail non-blocking data transfer API (TX/RX) contain. + * -FLEXCAN_TransferSendNonBlocking + * -FLEXCAN_TransferFDSendNonBlocking + * -FLEXCAN_TransferReceiveNonBlocking + * -FLEXCAN_TransferFDReceiveNonBlocking + * -FLEXCAN_TransferReceiveFifoNonBlocking + * + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * return the index of mailbox 's timestamp stored in the handle. + * + */ +uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + + return (uint32_t)(handle->timestamp[mbIdx]); +} + +/*! + * brief Check unhandle interrupt events + * + * param base FlexCAN peripheral base address. + * return TRUE if unhandled interrupt action exist, FALSE if no unhandlered interrupt action exist. + */ +static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base) +{ + uint64_t tempmask; + uint64_t tempflag; + bool fgRet = false; + + if (0U == (FLEXCAN_GetStatusFlags(base) & + (FLEXCAN_ERROR_AND_STATUS_INIT_FLAG | FLEXCAN_WAKE_UP_FLAG | FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG))) + { + /* If no error, wake_up or enhanced RX FIFO status, Checking whether exist MB interrupt status and legacy RX + * FIFO interrupt status */ + tempmask = (uint64_t)base->IMASK1; + tempflag = (uint64_t)base->IFLAG1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + tempmask |= ((uint64_t)base->IMASK2) << 32; + tempflag |= ((uint64_t)base->IFLAG2) << 32; +#endif + fgRet = (0U != (tempmask & tempflag)); +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + if (0U != (base->IMASK3 & base->IFLAG3)) + { + fgRet = true; + } +#endif +#if defined(CAN_IMASK4_BUF127TO96M_MASK) + if (0U != (base->IMASK4 & base->IFLAG4)) + { + fgRet = true; + } +#endif + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + else if (0U != (FLEXCAN_GetStatusFlags(base) & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG)) + { + /* Checking whether exist enhanced RX FIFO interrupt status. */ + tempmask = (uint64_t)base->ERFIER; + tempflag = (uint64_t)base->ERFSR; + fgRet = (0U != (tempmask & tempflag)); + } +#endif + else + { + /* Exist error or wake up flag. */ + fgRet = true; + } + + return fgRet; +} + +/*! + * brief Sub Handler Legacy Rx FIFO Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param result The MB flag number. + * + * return the status after handle transfered event. + */ +static status_t FLEXCAN_SubHandlerForLegacyRxFIFO(CAN_Type *base, flexcan_handle_t *handle, uint32_t result) +{ + uint32_t u32mask = 1; + status_t status = kStatus_FLEXCAN_UnHandled; + + switch (u32mask << result) + { + case kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case kFLEXCAN_RxFifoWarningFlag: + if ((handle->rxFifoFrameNum > 5U) && (0U != (base->IFLAG1 & (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag))) + { + for (uint32_t i = 0; i < 5UL; i++) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + /* + * $Branch Coverage Justification$ + * (kStatus_Success != status) not covered. $ref flexcan_c_ref_1$. + */ + if (kStatus_Success == status) + { + /* Align the current rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[i] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + /* Clean Rx Fifo available flag to discard the frame that has been read. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + else + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum < 5UL) + { + /* Enable data avaliable interrupt. */ + FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + /* Should enter case kFLEXCAN_RxFifoFrameAvlFlag but not, means previous transfer may have + * overflow*/ + status = kStatus_FLEXCAN_RxFifoWarning; + } + break; + + case kFLEXCAN_RxFifoFrameAvlFlag: + /* Whether still has CAN messages remaining to be received. */ + if (handle->rxFifoFrameNum > 0U) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + /* + * $Branch Coverage Justification$ + * (kStatus_Success != status) not covered. $ref flexcan_c_ref_1$. + */ + if (kStatus_Success == status) + { + /* Align the current (index 0) rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[0] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + } + else + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else + { + /* Continue use data avaliable interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + + return status; +} + +/*! + * brief Sub Handler Message Buffer Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param result The MB flag number. + * + * return the status after handle transfered event. + */ +static status_t FLEXCAN_SubHandlerForMB(CAN_Type *base, flexcan_handle_t *handle, uint32_t result) +{ + status_t status = kStatus_FLEXCAN_UnHandled; + + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame. */ + case (uint8_t)kFLEXCAN_StateRxData: +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFDFrameBuf[result]->timestamp; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + } + } + else +#endif + { + status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + } + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Sove Rx Remote Frame. User need to Read the frame in Mail box in time by Read from MB API. */ + case (uint8_t)kFLEXCAN_StateRxRemote: + status = kStatus_FLEXCAN_RxRemote; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Data Frame. */ + case (uint8_t)kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Remote Frame. */ + case (uint8_t)kFLEXCAN_StateTxRemote: + handle->mbState[result] = (uint8_t)kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + + return status; +} + +/*! + * brief Sub Handler Data Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pResult Pointer to the Handle result. + * + * return the status after handle each data transfered event. + */ +static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint32_t *pResult) +{ + status_t status = kStatus_FLEXCAN_UnHandled; + uint32_t result = 0xFFU; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t intflag[4] = {(base->IMASK1 & base->IFLAG1), (base->IMASK2 & base->IFLAG2), 0U, 0U}; +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + intflag[2] = base->IMASK3 & base->IFLAG3; +#endif +#if defined(CAN_IMASK4_BUF127TO96M_MASK) + intflag[3] = base->IMASK4 & base->IFLAG4; +#endif +#else + uint32_t intflag = base->IMASK1 & base->IFLAG1; +#endif + + /* For this implementation, we solve the Message with lowest MB index first. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + for (uint32_t i = 0U; i < 4U; i++) + { + if (intflag[i] != 0U) + { + for (uint32_t j = 0U; j < 32U; j++) + { + if (0UL != (intflag[i] & ((uint32_t)1UL << j))) + { + result = i * 32U + j; + break; + } + } + break; + } + } +#else + for (result = 0U; result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) + { + if (0UL != (intflag & ((uint32_t)1UL << result))) + { + break; + } + } +#endif + + /* find Message to deal with. */ + if (result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) + { + /* Solve Legacy Rx FIFO interrupt. */ + if (((uint8_t)kFLEXCAN_StateIdle != handle->rxFifoState) && (result <= (uint32_t)CAN_IFLAG1_BUF7I_SHIFT) && + ((base->MCR & CAN_MCR_RFEN_MASK) != 0U)) + { + status = FLEXCAN_SubHandlerForLegacyRxFIFO(base, handle, result); + /* + * $Branch Coverage Justification$ + * (status == kStatus_FLEXCAN_RxFifoDisabled) not covered. $ref flexcan_c_ref_1$. + */ + if (status == kStatus_FLEXCAN_RxFifoDisabled) + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return status; + } + } + else + { + status = FLEXCAN_SubHandlerForMB(base, handle, result); + } + + /* Clear resolved Message Buffer IRQ. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (result >= 64U) + { + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (result - 64U)); + } + else + { + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); +#else + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << result); +#endif + } + + *pResult = result; + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Sub Handler Ehanced Rx FIFO event + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param flags FlexCAN interrupt flags. + * + * return the status after handle Ehanced Rx FIFO event. + */ +static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64_t flags) +{ + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + uint32_t transferFrames; + + status_t status; + /* Solve Ehanced Rx FIFO interrupt. */ + if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFUFWIE_MASK))) + { + status = kStatus_FLEXCAN_RxFifoUnderflow; + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag); + } + else if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFOVFIE_MASK))) + { + status = kStatus_FLEXCAN_RxFifoOverflow; + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag); + } + else if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFWMIIE_MASK))) + { + /* Whether the number of CAN messages remaining to be received is greater than the watermark. */ + transferFrames = (handle->rxFifoFrameNum > watermark) ? watermark : handle->rxFifoFrameNum; + + for (uint32_t i = 0; i < transferFrames; i++) + { + status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); + + if (kStatus_Success == status) + { + handle->rxFifoFDFrameBuf++; + handle->rxFifoFrameNum--; + /* Clear data Watermark flag due to has read back one frame. */ + base->ERFSR = CAN_ERFSR_ERFWMI_MASK; + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else if (handle->rxFifoFrameNum < watermark) + { + /* Disable watermark interrupt and enable data avaliable interrupt. */ + FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable); + FLEXCAN_EnableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable); + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + /* Continue use watermark interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + } + else + { + /* Data available status, check Whether still has CAN messages remaining to be received. */ + if (handle->rxFifoFrameNum > 0U) + { + status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); + + if (kStatus_Success == status) + { + handle->rxFifoFDFrameBuf++; + handle->rxFifoFrameNum--; + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else + { + /* Continue use data avaliable interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + } + return status; +} +#endif + +/*! + * brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + status_t status; + uint32_t mbNum = 0xFFU; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + uint64_t result = 0U; +#else + uint32_t result = 0U; +#endif + do + { + /* Get Current FlexCAN Module Error and Status. */ + result = FLEXCAN_GetStatusFlags(base); + + /* To handle FlexCAN Error and Status Interrupt first. */ + if (0U != (result & FLEXCAN_ERROR_AND_STATUS_INIT_FLAG)) + { + status = kStatus_FLEXCAN_ErrorStatus; + /* Clear FlexCAN Error and Status Interrupt. */ + FLEXCAN_ClearStatusFlags(base, FLEXCAN_ERROR_AND_STATUS_INIT_FLAG); + } + else if (0U != (result & FLEXCAN_WAKE_UP_FLAG)) + { + status = kStatus_FLEXCAN_WakeUp; + FLEXCAN_ClearStatusFlags(base, FLEXCAN_WAKE_UP_FLAG); + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + else if (0U != (FLEXCAN_EFIFO_STATUS_UNMASK(result & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG) & base->ERFIER)) + { + status = FLEXCAN_SubHandlerForEhancedRxFifo(base, handle, result); + } +#endif + else + { + /* To handle Message Buffer or Legacy Rx FIFO transfer. */ + status = FLEXCAN_SubHandlerForDataTransfered(base, handle, &mbNum); + result = mbNum; + } + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + } while (FLEXCAN_CheckUnhandleInterruptEvents(base)); +} + +#if defined(CAN0) +void CAN0_DriverIRQHandler(void); +void CAN0_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[0]); + + s_flexcanIsr(CAN0, s_flexcanHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN1) +void CAN1_DriverIRQHandler(void); +void CAN1_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[1]); + + s_flexcanIsr(CAN1, s_flexcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN2) +void CAN2_DriverIRQHandler(void); +void CAN2_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[2]); + + s_flexcanIsr(CAN2, s_flexcanHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN3) +void CAN3_DriverIRQHandler(void); +void CAN3_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[3]); + + s_flexcanIsr(CAN3, s_flexcanHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN4) +void CAN4_DriverIRQHandler(void); +void CAN4_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[4]); + + s_flexcanIsr(CAN4, s_flexcanHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN0) +void DMA_FLEXCAN0_INT_DriverIRQHandler(void); +void DMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + + s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN1) +void DMA_FLEXCAN1_INT_DriverIRQHandler(void); +void DMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + + s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN2) +void DMA_FLEXCAN2_INT_DriverIRQHandler(void); +void DMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + + s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN0) +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + + s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN1) +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + + s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN2) +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + + s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCAN1) +void CAN_FD1_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[1]); + + s_flexcanIsr(FLEXCAN1, s_flexcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCAN2) +void CAN_FD2_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[2]); + + s_flexcanIsr(FLEXCAN2, s_flexcanHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan.h new file mode 100644 index 0000000000..553e4613cd --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan.h @@ -0,0 +1,2360 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXCAN_H_ +#define FSL_FLEXCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN driver version. */ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 4)) +/*@}*/ + +#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) +/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */ +#define FLEXCAN_WAIT_TIMEOUT (1000U) +#endif + +/*! @brief FlexCAN frame length helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +#define DLC_LENGTH_DECODE(dlc) (((dlc) <= 8U) ? (dlc) : (((dlc) <= 12U) ? (((dlc)-6U) * 4U) : (((dlc)-11U) * 16U))) +#endif + +/*! @brief FlexCAN Frame ID helper macro. */ +#define FLEXCAN_ID_STD(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ +#define FLEXCAN_ID_EXT(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ + (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ + +/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ + +/*! @brief FlexCAN Legacy Rx FIFO Mask helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ + (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ + (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ + 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN Rx FIFO Filter helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx FIFO Filter and Mask helper macro. */ +#define ENHANCED_RX_FIFO_FSCH(x) (((uint32_t)(((uint32_t)(x)) << 30)) & 0xC0000000U) +#define RTR_STD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << 27)) & 0x08000000U) +#define RTR_STD_LOW(x) (((uint32_t)(((uint32_t)(x)) << 11)) & 0x00000800U) +#define RTR_EXT(x) (((uint32_t)(((uint32_t)(x)) << 29)) & 0x40000000U) +#define ID_STD_LOW(id) (((uint32_t)id) & 0x7FFU) +#define ID_STD_HIGH(id) (((uint32_t)(((uint32_t)(id)) << 16)) & 0x07FF0000U) +#define ID_EXT(id) (((uint32_t)id) & 0x1FFFFFFFU) + +/*! Standard ID filter element with filter + mask scheme. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id) | RTR_STD_LOW(rtr_mask) | ID_STD_LOW(id_mask)) +/*! Standard ID filter element with filter range. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id_upper) | RTR_STD_LOW(rtr_mask) | \ + ID_STD_LOW(id_lower)) +/*! Standard ID filter element with two filters without masks. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_STD_HIGH(rtr1) | ID_STD_HIGH(id1) | RTR_STD_LOW(rtr2) | ID_STD_LOW(id2)) +/*! Extended ID filter element with filter + mask scheme low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr) | ID_EXT(id)) +/*! Extended ID filter element with filter + mask scheme high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr_mask) | ID_EXT(id_mask)) +/*! Extended ID filter element with range scheme low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr) | ID_EXT(id_upper)) +/*! Extended ID filter element with range scheme high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr_mask) | ID_EXT(id_lower)) +/*! Extended ID filter element with two filters without masks low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr2) | ID_EXT(id2)) +/*! Extended ID filter element with two filters without masks high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr1) | ID_EXT(id1)) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! @brief FlexCAN Pretended Networking ID Mask helper macro. */ +#define FLEXCAN_PN_STD_MASK(id, rtr) \ + ((uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_PN_EXT_MASK(id, rtr) \ + ((uint32_t)CAN_FLT_ID1_FLT_IDE_MASK | (uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ +#endif + +/*! @brief FlexCAN interrupt/status flag helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +#define FLEXCAN_PN_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0x3000000000000U) +#define FLEXCAN_PN_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0x00030000U) +#define FLEXCAN_PN_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0x300000000U) +#define FLEXCAN_PN_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x00030000U) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define FLEXCAN_EFIFO_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF000000000000000U) +#define FLEXCAN_EFIFO_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0000000U) +#define FLEXCAN_EFIFO_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF003000000000000U) +#define FLEXCAN_EFIFO_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0030000U) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_MECR_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0xD00000000U) +#define FLEXCAN_MECR_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x000D0000U) +#define FLEXCAN_MECR_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 34)) & 0x34003400000000U) +#define FLEXCAN_MECR_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 34)) & 0x000D000DU) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \ + ((uint32_t)kFLEXCAN_ErrorOverrunFlag | (uint32_t)kFLEXCAN_FDErrorIntFlag | (uint32_t)kFLEXCAN_BusoffDoneIntFlag | \ + (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \ + (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG) +#else +#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \ + ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \ + (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +#define FLEXCAN_WAKE_UP_FLAG \ + ((uint32_t)kFLEXCAN_WakeUpIntFlag | (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag) +#else +#define FLEXCAN_WAKE_UP_FLAG ((uint32_t)kFLEXCAN_WakeUpIntFlag) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_MEMORY_ERROR_INIT_FLAG ((uint64_t)kFLEXCAN_AllMemoryErrorFlag) +#else +#define FLEXCAN_MEMORY_ERROR_INIT_FLAG (0U) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG \ + ((uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag | (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag | \ + (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag | (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag) +#endif +/*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U) +#else +#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U) +#endif +/*! @brief FlexCAN transfer status. */ +enum +{ + kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ + kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ + kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( + kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ + kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ + kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ + kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ + kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ + kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ + kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ + kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ + kStatus_FLEXCAN_RxFifoDisabled = + MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< Rx Message FIFO is disabled during reading. */ + kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN Module Error and Status. */ + kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< FlexCAN is waken up from STOP mode. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 13), /*!< UnHadled Interrupt asserted. */ + kStatus_FLEXCAN_RxRemote = MAKE_STATUS(kStatusGroup_FLEXCAN, 14), /*!< Rx Remote Message Received in Mail box. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + kStatus_FLEXCAN_RxFifoUnderflow = + MAKE_STATUS(kStatusGroup_FLEXCAN, 15), /*!< Enhanced Rx Message FIFO is underflow. */ +#endif +}; + +/*! @brief FlexCAN frame format. */ +typedef enum _flexcan_frame_format +{ + kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ + kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ +} flexcan_frame_format_t; + +/*! @brief FlexCAN frame type. */ +typedef enum _flexcan_frame_type +{ + kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} flexcan_frame_type_t; + +/*! @brief FlexCAN clock source. + * @deprecated Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0 + * @deprecated Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1 + */ +typedef enum _flexcan_clock_source +{ + kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ + kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ + kFLEXCAN_ClkSrc0 = 0x0U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 0. */ + kFLEXCAN_ClkSrc1 = 0x1U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 1. */ +} flexcan_clock_source_t; + +/*! @brief FlexCAN wake up source. */ +typedef enum _flexcan_wake_up_source +{ + kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */ + kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */ +} flexcan_wake_up_source_t; + +/*! @brief FlexCAN Rx Fifo Filter type. */ +typedef enum _flexcan_rx_fifo_filter_type +{ + kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ + kFLEXCAN_RxFifoFilterTypeB = + 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeC = + 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ +} flexcan_rx_fifo_filter_type_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief FlexCAN Message Buffer Payload size. + */ +typedef enum _flexcan_mb_size +{ + kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */ + kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */ + kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */ + kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */ +} flexcan_mb_size_t; + +/*! + * @brief FlexCAN CAN FD frame supporting data length (available DLC values). + * + * For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the + * MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. + * For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, + * the high order bytes that do not fit the Payload size will lose. + */ +enum _flexcan_fd_frame_length +{ + kFLEXCAN_0BperFrame = 0x0U, /*!< Frame contains 0 valid data bytes. */ + kFLEXCAN_1BperFrame, /*!< Frame contains 1 valid data bytes. */ + kFLEXCAN_2BperFrame, /*!< Frame contains 2 valid data bytes. */ + kFLEXCAN_3BperFrame, /*!< Frame contains 3 valid data bytes. */ + kFLEXCAN_4BperFrame, /*!< Frame contains 4 valid data bytes. */ + kFLEXCAN_5BperFrame, /*!< Frame contains 5 valid data bytes. */ + kFLEXCAN_6BperFrame, /*!< Frame contains 6 valid data bytes. */ + kFLEXCAN_7BperFrame, /*!< Frame contains 7 valid data bytes. */ + kFLEXCAN_8BperFrame, /*!< Frame contains 8 valid data bytes. */ + kFLEXCAN_12BperFrame, /*!< Frame contains 12 valid data bytes. */ + kFLEXCAN_16BperFrame, /*!< Frame contains 16 valid data bytes. */ + kFLEXCAN_20BperFrame, /*!< Frame contains 20 valid data bytes. */ + kFLEXCAN_24BperFrame, /*!< Frame contains 24 valid data bytes. */ + kFLEXCAN_32BperFrame, /*!< Frame contains 32 valid data bytes. */ + kFLEXCAN_48BperFrame, /*!< Frame contains 48 valid data bytes. */ + kFLEXCAN_64BperFrame, /*!< Frame contains 64 valid data bytes. */ +}; +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations. */ +typedef enum _flexcan_efifo_dma_per_read_length +{ + kFLEXCAN_1WordPerRead = 0x0U, /*!< Transfer 1 32-bit words (CS).*/ + kFLEXCAN_2WordPerRead, /*!< Transfer 2 32-bit words (CS + ID).*/ + kFLEXCAN_3WordPerRead, /*!< Transfer 3 32-bit words (CS + ID + 1~4 bytes data).*/ + kFLEXCAN_4WordPerRead, /*!< Transfer 4 32-bit words (CS + ID + 5~8 bytes data).*/ + kFLEXCAN_5WordPerRead, /*!< Transfer 5 32-bit words (CS + ID + 9~12 bytes data).*/ + kFLEXCAN_6WordPerRead, /*!< Transfer 6 32-bit words (CS + ID + 13~16 bytes data).*/ + kFLEXCAN_7WordPerRead, /*!< Transfer 7 32-bit words (CS + ID + 17~20 bytes data).*/ + kFLEXCAN_8WordPerRead, /*!< Transfer 8 32-bit words (CS + ID + 21~24 bytes data).*/ + kFLEXCAN_9WordPerRead, /*!< Transfer 9 32-bit words (CS + ID + 25~28 bytes data).*/ + kFLEXCAN_10WordPerRead, /*!< Transfer 10 32-bit words (CS + ID + 29~32 bytes data).*/ + kFLEXCAN_11WordPerRead, /*!< Transfer 11 32-bit words (CS + ID + 33~36 bytes data).*/ + kFLEXCAN_12WordPerRead, /*!< Transfer 12 32-bit words (CS + ID + 37~40 bytes data).*/ + kFLEXCAN_13WordPerRead, /*!< Transfer 13 32-bit words (CS + ID + 41~44 bytes data).*/ + kFLEXCAN_14WordPerRead, /*!< Transfer 14 32-bit words (CS + ID + 45~48 bytes data).*/ + kFLEXCAN_15WordPerRead, /*!< Transfer 15 32-bit words (CS + ID + 49~52 bytes data).*/ + kFLEXCAN_16WordPerRead, /*!< Transfer 16 32-bit words (CS + ID + 53~56 bytes data).*/ + kFLEXCAN_17WordPerRead, /*!< Transfer 17 32-bit words (CS + ID + 57~60 bytes data).*/ + kFLEXCAN_18WordPerRead, /*!< Transfer 18 32-bit words (CS + ID + 61~64 bytes data).*/ + kFLEXCAN_19WordPerRead /*!< Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).*/ +} flexcan_efifo_dma_per_read_length_t; +#endif + +/*! + * @brief FlexCAN Enhanced/Legacy Rx FIFO priority. + * + * The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. + * If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with + * the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority. + */ +typedef enum _flexcan_rx_fifo_priority +{ + kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first. */ + kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Enhanced/Legacy Rx FIFO first. */ +} flexcan_rx_fifo_priority_t; + +/*! + * @brief FlexCAN interrupt enable enumerations. + * + * This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions. + * @note FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in. + */ +enum _flexcan_interrupt_enable +{ + kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt, use bit 15. */ + kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */ + kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */ + kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /*! PN Match Wake Up interrupt, use high word bit 17. */ + kFLEXCAN_PNMatchWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WTOF_MSK_MASK), + /*! PN Timeout Wake Up interrupt, use high word bit 16. */ + kFLEXCAN_PNTimeoutWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WUMF_MSK_MASK), +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /*!< Enhanced Rx FIFO Underflow interrupt, use high word bit 31. */ + kFLEXCAN_ERxFifoUnderflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFUFWIE_MASK), + /*!< Enhanced Rx FIFO Overflow interrupt, use high word bit 30. */ + kFLEXCAN_ERxFifoOverflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFOVFIE_MASK), + /*!< Enhanced Rx FIFO Watermark interrupt, use high word bit 29. */ + kFLEXCAN_ERxFifoWatermarkInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFWMIIE_MASK), + /*!< Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28. */ + kFLEXCAN_ERxFifoDataAvlInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFDAIE_MASK), +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /*! Host Access With Non-Correctable Errors interrupt, use high word bit 0. */ + kFLEXCAN_HostAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_HANCEI_MSK_MASK), + /*! FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2. */ + kFLEXCAN_FlexCanAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_FANCEI_MSK_MASK), + /*! Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3. */ + kFLEXCAN_HostOrFlexCanCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_CEI_MSK_MASK), +#endif +}; + +/*! + * @brief FlexCAN status flags. + * + * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. + * @note The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to + * read status flags and distinguish which error is occur using @ref _flexcan_error_flags enumerations. + */ +enum _flexcan_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_ErrorOverrunFlag = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ + kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< CAN FD Error Interrupt Flag. */ + kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Bus Off process completed Interrupt Flag. */ +#endif + kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ + kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ + kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ + kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< FlexCAN In IDLE Status. */ + kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< FlexCAN Fault Confinement State. */ + kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ + kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ + kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ + kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< CAN Error Interrupt Flag. */ + kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Self Wake-Up Interrupt Flag. */ + kFLEXCAN_ErrorFlag = + (uint32_t)(/*!< All FlexCAN Read Clear Error Status. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | + CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | +#endif + CAN_ESR1_TXWRN_MASK | CAN_ESR1_RXWRN_MASK | CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | + CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK), +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + kFLEXCAN_PNMatchIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WUMF_MASK), /*!< PN Matching Event Interrupt Flag. */ + kFLEXCAN_PNTimeoutIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WTOF_MASK), /*!< PN Timeout Event Interrupt Flag. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + kFLEXCAN_ERxFifoUnderflowIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFUFW_MASK), /*!< Enhanced Rx FIFO underflow Interrupt Flag. */ + kFLEXCAN_ERxFifoOverflowIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFOVF_MASK), /*!< Enhanced Rx FIFO overflow Interrupt Flag. */ + kFLEXCAN_ERxFifoWatermarkIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFWMI_MASK), /*!< Enhanced Rx FIFO watermark Interrupt Flag. */ + kFLEXCAN_ERxFifoDataAvlIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFDA_MASK), /*!< Enhanced Rx FIFO data available Interrupt Flag. */ + kFLEXCAN_ERxFifoEmptyFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFE_MASK), /*!< Enhanced Rx FIFO empty status. */ + kFLEXCAN_ERxFifoFullFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFF_MASK), /*!< Enhanced Rx FIFO full status. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /*! Host Access With Non-Correctable Error Interrupt Flag. */ + kFLEXCAN_HostAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIF_MASK), + /*! FlexCAN Access With Non-Correctable Error Interrupt Flag. */ + kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIF_MASK), + /*! Correctable Error Interrupt Flag. */ + kFLEXCAN_CorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIF_MASK), + /*! Host Access With Non-Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIOF_MASK), + /*! FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIOF_MASK), + /*! Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_CorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIOF_MASK), + /*! All Memory Error Flags. */ + kFLEXCAN_AllMemoryErrorFlag = + (kFLEXCAN_HostAccessNonCorrectableErrorIntFlag | kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag | + kFLEXCAN_CorrectableErrorIntFlag | kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag | + kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag | kFLEXCAN_CorrectableErrorOverrunFlag) +#endif +}; + +/*! + * @brief FlexCAN error status flags. + * + * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. + * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations + * to ditermine which error is generated. + */ +enum _flexcan_error_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ + kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ +#endif + kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ + kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ + kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ + kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ + kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ +}; + +/*! + * @brief FlexCAN Legacy Rx FIFO status flags. + * + * The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies + * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding + * Message Buffer status flags. + */ +enum +{ + kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ + kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ + kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ +}; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * @brief FlexCAN Memory Error Type. + */ +typedef enum _flexcan_memory_error_type +{ + kFLEXCAN_CorrectableError = 0U, /*!< The memory error is correctable which means on bit error. */ + kFLEXCAN_NonCorrectableError /*!< The memory error is non-correctable which means two bit errors. */ +} flexcan_memory_error_type_t; + +/*! + * @brief FlexCAN Memory Access Type. + */ +typedef enum _flexcan_memory_access_type +{ + kFLEXCAN_MoveOutFlexCanAccess = 0U, /*!< The memory error was detected during move-out FlexCAN access. */ + kFLEXCAN_MoveInAccess, /*!< The memory error was detected during move-in FlexCAN access. */ + kFLEXCAN_TxArbitrationAccess, /*!< The memory error was detected during Tx Arbitration FlexCAN access. */ + kFLEXCAN_RxMatchingAccess, /*!< The memory error was detected during Rx Matching FlexCAN access. */ + kFLEXCAN_MoveOutHostAccess /*!< The memory error was detected during Rx Matching Host (CPU) access. */ +} flexcan_memory_access_type_t; + +/*! + * @brief FlexCAN Memory Error Byte Syndrome. + */ +typedef enum _flexcan_byte_error_syndrome +{ + kFLEXCAN_NoError = 0U, /*!< No bit error in this byte. */ + kFLEXCAN_ParityBits0Error = 1U, /*!< Parity bit 0 error in this byte. */ + kFLEXCAN_ParityBits1Error = 2U, /*!< Parity bit 1 error in this byte. */ + kFLEXCAN_ParityBits2Error = 4U, /*!< Parity bit 2 error in this byte. */ + kFLEXCAN_ParityBits3Error = 8U, /*!< Parity bit 3 error in this byte. */ + kFLEXCAN_ParityBits4Error = 16U, /*!< Parity bit 4 error in this byte. */ + kFLEXCAN_DataBits0Error = 28U, /*!< Data bit 0 error in this byte. */ + kFLEXCAN_DataBits1Error = 22U, /*!< Data bit 1 error in this byte. */ + kFLEXCAN_DataBits2Error = 19U, /*!< Data bit 2 error in this byte. */ + kFLEXCAN_DataBits3Error = 25U, /*!< Data bit 3 error in this byte. */ + kFLEXCAN_DataBits4Error = 26U, /*!< Data bit 4 error in this byte. */ + kFLEXCAN_DataBits5Error = 7U, /*!< Data bit 5 error in this byte. */ + kFLEXCAN_DataBits6Error = 21U, /*!< Data bit 6 error in this byte. */ + kFLEXCAN_DataBits7Error = 14U, /*!< Data bit 7 error in this byte. */ + kFLEXCAN_AllZeroError = 6U, /*!< All-zeros non-correctable error in this byte. */ + kFLEXCAN_AllOneError = 31U, /*!< All-ones non-correctable error in this byte. */ + kFLEXCAN_NonCorrectableErrors /*!< Non-correctable error in this byte. */ +} flexcan_byte_error_syndrome_t; + +/*! + * @brief FlexCAN memory error register status structure + * + * This structure contains the memory access properties that caused a memory error access. + * It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can + * use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access. + */ +typedef struct _flexcan_memory_error_report_status +{ + flexcan_memory_error_type_t errorType; /*!< The type of memory error that giving rise to the report. */ + flexcan_memory_access_type_t accessType; /*!< The type of memory access that giving rise to the memory error. */ + uint16_t accessAddress; /*!< The address where memory error detected. */ + uint32_t errorData; /*!< The raw data word read from memory with error. */ + struct + { + bool byteIsRead; /*!< The byte n (0~3) was read or not. */ + /*!< The type of error and which bit in byte (n) is affected by the error. */ + flexcan_byte_error_syndrome_t bitAffected; + } byteStatus[4]; +} flexcan_memory_error_report_status_t; +#endif + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief FlexCAN message frame structure. */ +typedef struct _flexcan_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame data length in bytes (Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t : 1; /*!< Reserved. */ + uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord0; /*!< CAN Frame payload word0. */ + uint32_t dataWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_frame_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! @brief CAN FD message frame structure. + * + * The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length + * selected for the message buffers. The length should be a enumeration member, see @ref _flexcan_fd_frame_length. + */ +typedef struct _flexcan_fd_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t srr : 1; /*!< Substitute Remote request. */ + uint32_t : 6; + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ + }; + /* Note: the maximum databyte* below is actually 64, user can add them if needed, + or just use dataWord[*] instead. */ + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /*! @note ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be + * located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is + * correct.*/ + uint32_t idhit; /*!< CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive + mode). */ +#endif +} flexcan_fd_frame_t; +#endif + +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint16_t preDivider; /*!< Classic CAN or CAN FD nominal phase bit rate prescaler. */ + uint8_t rJumpwidth; /*!< Classic CAN or CAN FD nominal phase Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Classic CAN or CAN FD nominal phase Segment 1. */ + uint8_t phaseSeg2; /*!< Classic CAN or CAN FD nominal phase Segment 2. */ + uint8_t propSeg; /*!< Classic CAN or CAN FD nominal phase Propagation Segment. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint16_t fpreDivider; /*!< CAN FD data phase bit rate prescaler. */ + uint8_t frJumpwidth; /*!< CAN FD data phase Re-sync Jump Width. */ + uint8_t fphaseSeg1; /*!< CAN FD data phase Phase Segment 1. */ + uint8_t fphaseSeg2; /*!< CAN FD data phase Phase Segment 2. */ + uint8_t fpropSeg; /*!< CAN FD data phase Propagation Segment. */ +#endif +} flexcan_timing_config_t; + +/*! @brief FlexCAN module configuration structure. + * @deprecated Do not use the baudRate. It has been superceded bitRate + * @deprecated Do not use the baudRateFD. It has been superceded bitRateFD + */ +typedef struct _flexcan_config +{ + union + { + struct + { + uint32_t baudRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t baudRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */ +#endif + }; + struct + { + uint32_t bitRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t bitRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */ +#endif + }; + }; + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ + flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask and Queue feature. */ + bool disableSelfReception; /*!< Enable or Disable Self Reflection. */ + bool enableListenOnlyMode; /*!< Enable or Disable Listen Only Mode. */ +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + bool enableSupervisorMode; /*!< Enable or Disable Supervisor Mode, enable this mode will make registers allow only + Supervisor access. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + bool enablePretendedeNetworking; /*!< Enable or Disable the Pretended Networking mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + bool enableMemoryErrorControl; /*!< Enable or Disable the memory errors detection and correction mechanism. */ + bool enableNonCorrectableErrorEnterFreeze; /*!< Enable or Disable Non-Correctable Errors In FlexCAN Access Put + Device In Freeze Mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + bool enableTransceiverDelayMeasure; /*!< Enable or Disable the transceiver delay measurement, when it is enabled, + then the secondary sample point position is determined by the sum of the + transceiver delay measurement plus the enhanced TDC offset. */ +#endif + flexcan_timing_config_t timingConfig; /* Protocol timing . */ +} flexcan_config_t; + +/*! + * @brief FlexCAN Receive Message Buffer configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. + * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive + * Message Buffer. The function abort previous receiving process, clean the + * Message Buffer and activate the Rx Message Buffer using given Message Buffer + * setting. + */ +typedef struct _flexcan_rx_mb_config +{ + uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using + FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ + flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ +} flexcan_rx_mb_config_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! @brief FlexCAN Pretended Networking match source selection. */ +typedef enum _flexcan_pn_match_source +{ + kFLEXCAN_PNMatSrcID = 0U, /*!< Message match with ID filtering. */ + kFLEXCAN_PNMatSrcIDAndData, /*!< Message match with ID filtering and payload filtering. */ +} flexcan_pn_match_source_t; + +/*! @brief FlexCAN Pretended Networking mode match type. */ +typedef enum _flexcan_pn_match_mode +{ + kFLEXCAN_PNMatModeEqual = 0x0U, /*!< Match upon ID/Payload contents against an exact target value. */ + kFLEXCAN_PNMatModeGreater, /*!< Match upon an ID/Payload value greater than or equal to a specified target value. + */ + kFLEXCAN_PNMatModeSmaller, /*!< Match upon an ID/Payload value smaller than or equal to a specified target value. + */ + kFLEXCAN_PNMatModeRange, /*!< Match upon an ID/Payload value inside a range, greater than or equal to a specified + lower limit, and smaller than or equal to a specified upper limit */ +} flexcan_pn_match_mode_t; + +/*! + * @brief FlexCAN Pretended Networking configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetPNConfig() function. + * The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode. + */ +typedef struct _flexcan_pn_config +{ + bool enableTimeout; /*!< Enable or Disable timeout event trigger wakeup.*/ + uint16_t timeoutValue; /*!< The timeout value that generates a wakeup event, the counter timer is incremented based + on 64 times the CAN Bit Time unit. */ + bool enableMatch; /*!< Enable or Disable match event trigger wakeup.*/ + flexcan_pn_match_source_t matchSrc; /*!< Selects the match source (ID and/or data match) to trigger wakeup. */ + uint8_t matchNum; /*!< The number of times a given message must match the predefined ID and/or data before + generating a wakeup event, range in 0x1 ~ 0xFF. */ + flexcan_pn_match_mode_t idMatchMode; /*!< The ID match type. */ + flexcan_pn_match_mode_t dataMatchMode; /*!< The data match type. */ + uint32_t idLower; /*!< The ID target values 1 which used either for ID match "equal to", "smaller than", + "greater than" comparisons, or as the lower limit value in ID match "range detection". */ + uint32_t idUpper; /*!< The ID target values 2 which used only as the upper limit value in ID match "range + detection" or used to store the ID mask in "equal to". */ + uint8_t lengthLower; /*!< The lower limit for length of data bytes which used only in data match "range + detection". Range in 0x0 ~ 0x8.*/ + uint8_t lengthUpper; /*!< The upper limit for length of data bytes which used only in data match "range + detection". Range in 0x0 ~ 0x8.*/ + union + { + /*!< The data target values 1 which used either for data match "equal to", "smaller than", + "greater than" comparisons, or as the lower limit value in data match "range + detection". */ + struct + { + uint32_t lowerWord0; /*!< CAN Frame payload word0. */ + uint32_t lowerWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t lowerByte3; /*!< CAN Frame payload byte3. */ + uint8_t lowerByte2; /*!< CAN Frame payload byte2. */ + uint8_t lowerByte1; /*!< CAN Frame payload byte1. */ + uint8_t lowerByte0; /*!< CAN Frame payload byte0. */ + uint8_t lowerByte7; /*!< CAN Frame payload byte7. */ + uint8_t lowerByte6; /*!< CAN Frame payload byte6. */ + uint8_t lowerByte5; /*!< CAN Frame payload byte5. */ + uint8_t lowerByte4; /*!< CAN Frame payload byte4. */ + }; + }; + union + { + /*!< The data target values 2 which used only as the upper limit value in data match "range + detection" or used to store the data mask in "equal to". */ + struct + { + uint32_t upperWord0; /*!< CAN Frame payload word0. */ + uint32_t upperWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t upperByte3; /*!< CAN Frame payload byte3. */ + uint8_t upperByte2; /*!< CAN Frame payload byte2. */ + uint8_t upperByte1; /*!< CAN Frame payload byte1. */ + uint8_t upperByte0; /*!< CAN Frame payload byte0. */ + uint8_t upperByte7; /*!< CAN Frame payload byte7. */ + uint8_t upperByte6; /*!< CAN Frame payload byte6. */ + uint8_t upperByte5; /*!< CAN Frame payload byte5. */ + uint8_t upperByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_pn_config_t; +#endif + +/*! @brief FlexCAN Legacy Rx FIFO configuration structure. */ +typedef struct _flexcan_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Legacy Rx FIFO identifier filter table. */ + uint8_t idFilterNum; /*!< The FlexCAN Legacy Rx FIFO Filter elements quantity. */ + flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Legacy Rx FIFO Filter type. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Legacy Rx FIFO receive priority. */ +} flexcan_rx_fifo_config_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx FIFO Standard ID filter element structure. */ +typedef struct _flexcan_enhanced_rx_fifo_std_id_filter +{ + uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t : 2; + uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t std1 : 11; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t : 4; + uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t std2 : 11; /*!< Substitute Remote request. */ +} flexcan_enhanced_rx_fifo_std_id_filter_t; + +/*! @brief FlexCAN Enhanced Rx FIFO Extended ID filter element structure. */ +typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter +{ + uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t std1 : 29; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t : 2; + uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t std2 : 29; /*!< Substitute Remote request. */ +} flexcan_enhanced_rx_fifo_ext_id_filter_t; +/*! @brief FlexCAN Enhanced Rx FIFO configuration structure. */ +typedef struct _flexcan_enhanced_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member + occupies 32 bit word, table size should be equal to idFilterNum. There are two types of + Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element + (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table + members), the extended-ID filter element needs to be placed in front of the table. */ + uint8_t idFilterPairNum; /*!< idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, + each pair of filter elements occupies 2 words and can consist of one extended ID filter + element or two standard ID filter elements. */ + uint8_t extendIdFilterNum; /*!< The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO + identifier filter table, each extended-ID filter element occupies 2 words, + extendIdFilterNum need less than or equal to idFilterPairNum. */ + uint8_t fifoWatermark; /*!< (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO + which can trigger FIFO watermark interrupt or a DMA request. */ + flexcan_efifo_dma_per_read_length_t dmaPerReadLength; /*!< Define the length of each read of the Enhanced RX FIFO + element by the DAM, see @ref _flexcan_fd_frame_length. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Enhanced Rx FIFO receive priority. */ +} flexcan_enhanced_rx_fifo_config_t; +#endif + +/*! @brief FlexCAN Message Buffer transfer. */ +typedef struct _flexcan_mb_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t *framefd; +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ +} flexcan_mb_transfer_t; + +/*! @brief FlexCAN Rx FIFO transfer. */ +typedef struct _flexcan_fifo_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *framefd; /*!< The buffer of CAN Message to be received from Enhanced Rx FIFO. */ +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Legacy Rx FIFO. */ + size_t frameNum; /*!< Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO. */ +} flexcan_fifo_transfer_t; + +/*! @brief FlexCAN handle structure definition. */ +typedef struct _flexcan_handle flexcan_handle_t; + +/*! @brief FlexCAN transfer callback function. + * + * The FlexCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of + * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_CALLBACK(x) \ + void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint64_t result, void *userData) +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData); +#else +#define FLEXCAN_CALLBACK(x) \ + void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint32_t result, void *userData) +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); +#endif + +/*! @brief FlexCAN handle structure. */ +struct _flexcan_handle +{ + flexcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + flexcan_frame_t + *volatile mbFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN data from Message Buffers. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t + *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN FD data from Message Buffers. */ +#endif + flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received CAN data from Legacy Rx FIFO. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *volatile rxFifoFDFrameBuf; /*!< The buffer for received CAN FD data from Ehanced Rx FIFO. */ +#endif + size_t rxFifoFrameNum; /*!< The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO. */ + size_t rxFifoTransferTotalNum; /*!< Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO. */ + volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ + volatile uint32_t timestamp[CAN_WORD1_COUNT]; /*!< Mailbox transfer timestamp. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Determine whether the FlexCAN instance support CAN FD mode at run time. + * + * @note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part + * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. + * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be + * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, + * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode. + * + * @param base FlexCAN peripheral base address. + * @return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode. + */ +bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base); +#endif + +/*! + * @brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_EnterFreezeMode(CAN_Type *base); + +/*! + * @brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_ExitFreezeMode(CAN_Type *base); + +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Calculates the improved timing values by specific bit Rates for classical CAN. + * + * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated + * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 + * v4.2.0 and previous version document. + * + * @param base FlexCAN peripheral base address. + * @param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); + +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Calculates the improved timing values by specific bit rates for CANFD. + * + * This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase + * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based + * on the recommendation of the CiA 1301 v1.0.0 document. + * + * @param base FlexCAN peripheral base address. + * @param bitRate The CANFD bus control speed in bps defined by user. + * @param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate + * switching. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t bitRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * @param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs + * to be less than or equal to this value. + * @param brs True if bit rate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs); +#endif + +/*! + * @brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig->bitRate = 1000000U; + * flexcanConfig->bitRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->disableSelfReception = false; + * flexcanConfig->enableListenOnlyMode = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig->enableMemoryErrorControl = true; + * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; + * flexcanConfig.timingConfig = timingConfig; + * + * @param pConfig Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig); + +/* @} */ + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the FlexCAN classical CAN protocol timing characteristic. + * + * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead. + * + * @note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate(). + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig); + +/*! + * @brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase. + * + * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on + * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * @note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRate_Bps Bit rate in Bps. + * @return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully. + */ +status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Sets the FlexCAN CANFD data phase timing characteristic. + * + * This function gives user settings to CANFD data phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() + * to set both Nominal/Data bit Rate instead. + * + * @note Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in + * FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate(). + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig); + +/*! + * @brief Set bit rate of FlexCAN FD frame. + * + * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing + * values. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRateN_Bps Nominal bit Rate in Bps. + * @param bitRateD_Bps Data bit Rate in Bps. + * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully. + */ +status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps); +#endif + +/*! + * @brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * @param base FlexCAN peripheral base address. + * @param maskIdx The Index of individual Mask. + * @param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); + +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); +#endif + +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable); +#endif + +/*! + * @brief Configures the FlexCAN Legacy Rx FIFO. + * + * This function configures the FlexCAN Rx FIFO with given configuration. + * @note Legacy Rx FIFO only can receive classic CAN message. + * + * @param base FlexCAN peripheral base address. + * @param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * @param enable Enable/disable Legacy Rx FIFO. + * - true: Enable Legacy Rx FIFO. + * - false: Disable Legacy Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Configures the FlexCAN Enhanced Rx FIFO. + * + * This function configures the Enhanced Rx FIFO with given configuration. + * @note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO + * cannot be enabled at the same time. + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * @param enable Enable/disable Enhanced Rx FIFO. + * - true: Enable Enhanced Rx FIFO. + * - false: Disable Enhanced Rx FIFO. + */ +void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Configures the FlexCAN Pretended Networking mode. + * + * This function configures the FlexCAN Pretended Networking mode with given configuration. + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the FlexCAN Rx FIFO configuration structure. + */ +void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig); +#endif +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexCAN module interrupt flags. + * + * This function gets all FlexCAN status flags. The flags are returned as the logical + * OR value of the enumerators @ref _flexcan_flags. To check the specific status, + * compare the return value with enumerators in @ref _flexcan_flags. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + uint64_t tempflag = (uint64_t)base->ESR1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Get PN Wake Up status. */ + tempflag |= FLEXCAN_PN_STATUS_MASK(base->WU_MTC); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Get Enhanced Rx FIFO status. */ + tempflag |= FLEXCAN_EFIFO_STATUS_MASK(base->ERFSR); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Get Memory Error status. */ + tempflag |= FLEXCAN_MECR_STATUS_MASK(base->ERRSR); +#endif + return tempflag; +} +#else +static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + return base->ESR1; +} +#endif +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * + * @param base FlexCAN peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask) +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Clear PN Wake Up status. */ + base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Clear Enhanced Rx FIFO status. */ + base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Clear Memory Error status. */ + base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask); +#endif + base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU); +} +#else +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag. */ + base->ESR1 = mask; +} +#endif +/*! + * @brief Gets the FlexCAN Bus Error Counter value. + * + * This function gets the FlexCAN Bus Error Counter value for both Tx and + * Rx direction. These values may be needed in the upper layer error handling. + * + * @param base FlexCAN peripheral base address. + * @param txErrBuf Buffer to store Tx Error Counter value. + * @param rxErrBuf Buffer to store Rx Error Counter value. + */ +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +{ + if (NULL != txErrBuf) + { + *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); + } + + if (NULL != rxErrBuf) + { + *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); + } +} + +/*! + * @brief Gets the FlexCAN Message Buffer interrupt flags. + * + * This function gets the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t tempflag = (uint64_t)base->IFLAG1; + return (tempflag | (((uint64_t)base->IFLAG2) << 32)) & mask; +#else + return (base->IFLAG1 & mask); +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Gets the FlexCAN High 64 Message Buffer interrupt flags. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) +{ + uint64_t tempflag = 0U; +#if defined(CAN_IFLAG3_BUF95TO64_MASK) + tempflag |= (uint64_t)base->IFLAG3; +#endif +#if defined(CAN_IFLAG4_BUF127TO96_MASK) + tempflag |= (uint64_t)base->IFLAG4; +#endif + return (tempflag & mask); +} +#endif + +/*! + * @brief Clears the FlexCAN Message Buffer interrupt flags. + * + * This function clears the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); + base->IFLAG2 = (uint32_t)(mask >> 32); +#else + base->IFLAG1 = mask; +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Clears the FlexCAN High 64 Message Buffer interrupt flags. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) +{ +#if defined(CAN_IFLAG3_BUF95TO64_MASK) + base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU); +#endif +#if defined(CAN_IFLAG4_BUF127TO96_MASK) + base->IFLAG4 = (uint32_t)(mask >> 32U); +#endif +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * @brief Gets the FlexCAN Memory Error Report registers status. + * + * This function gets the FlexCAN Memory Error Report registers status. + * + * @param base FlexCAN peripheral base address. + * @param errorStatus Pointer to FlexCAN Memory Error Report registers status structure. + */ +void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Gets the FlexCAN Number of Matches when in Pretended Networking. + * + * This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL + * before a wakeup event. + * + * @param base FlexCAN peripheral base address. + * @return The number of received wake up msessages. + */ +static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base) +{ + return (uint8_t)((base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK) >> CAN_WU_MTC_MCOUNTER_SHIFT); +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Gets the number of FlexCAN Enhanced Rx FIFO available frames. + * + * This function gets the number of CAN messages stored in the Enhanced Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @return The number of available CAN messages stored in the Enhanced Rx FIFO. + */ +static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base) +{ + return (base->ERFSR & CAN_ERFSR_ERFEL_MASK); +} +#endif +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables FlexCAN interrupts according to the provided mask. + * + * This function enables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + + /* Solve Self Wake Up interrupt. */ + base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Solve CAN FD frames data phase error interrupt. */ + base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); + } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Solve PN Wake Up interrupt. */ + base->CTRL1_PN |= FLEXCAN_PN_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Solve Enhanced Rx FIFO interrupt. */ + base->ERFIER |= FLEXCAN_EFIFO_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Solve Memory Error interrupt. */ + base->MECR |= FLEXCAN_MECR_INT_UNMASK(mask); +#endif + + /* Solve interrupt enable bits in CTRL1 register. */ + base->CTRL1 |= + (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); + + EnableGlobalIRQ(primask); +} + +/*! + * @brief Disables FlexCAN interrupts according to the provided mask. + * + * This function disables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + + /* Solve Wake Up Interrupt. */ + base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Solve CAN FD frames data phase error interrupt. */ + base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); + } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Solve PN Wake Up Interrupt. */ + base->CTRL1_PN &= ~FLEXCAN_PN_STATUS_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Solve Enhanced Rx FIFO interrupt. */ + base->ERFIER &= ~FLEXCAN_EFIFO_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Solve Memory Error Interrupt. */ + base->MECR &= ~FLEXCAN_MECR_STATUS_UNMASK(mask); +#endif + + /* Solve interrupt enable bits in CTRL1 register. */ + base->CTRL1 &= + ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); + + EnableGlobalIRQ(primask); +} + +/*! + * @brief Enables FlexCAN Message Buffer interrupts. + * + * This function enables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); + base->IMASK2 |= (uint32_t)(mask >> 32); +#else + base->IMASK1 |= mask; +#endif + EnableGlobalIRQ(primask); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Enables FlexCAN high 64 Message Buffer interrupts. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) +{ + uint32_t primask = DisableGlobalIRQ(); + +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU); +#endif +#if defined(CAN_IMASK4_BUF127TO96_MASK) + base->IMASK4 |= (uint32_t)(mask >> 32U); +#endif + EnableGlobalIRQ(primask); +} +#endif + +/*! + * @brief Disables FlexCAN Message Buffer interrupts. + * + * This function disables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); + base->IMASK2 &= ~((uint32_t)(mask >> 32)); +#else + base->IMASK1 &= ~mask; +#endif + EnableGlobalIRQ(primask); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Disables FlexCAN high 64 Message Buffer interrupts. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) +{ + uint32_t primask = DisableGlobalIRQ(); + +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); +#endif +#if defined(CAN_IMASK4_BUF127TO96_MASK) + base->IMASK4 &= ~((uint32_t)(mask >> 32U)); +#endif + EnableGlobalIRQ(primask); +} +#endif + +/* @} */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); + +/*! + * @brief Gets the Rx FIFO Head address. + * + * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN Rx FIFO Head address. + */ +static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +{ + return (uintptr_t) & (base->MB[0].CS); +} + +/* @} */ +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN module operation. + * + * This function enables or disables the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param enable true to enable, false to disable. + */ +static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN exit from low-power mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } + else + { + base->MCR |= CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN enter low-power mode. */ + while (0U == (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } +} + +/*! + * @brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame); + +/*! + * @brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pTxFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame); + +/*! + * @brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); +#endif + +/*! + * @brief Reads a FlexCAN Message from Legacy Rx FIFO. + * + * This function reads a CAN message from the FlexCAN Legacy Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Reads a FlexCAN Message from Enhanced Rx FIFO. + * + * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Reads a FlexCAN Message from Wake Up MB. + * + * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers + * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The + * last message is stored in WMB3. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3. + * @retval kStatus_Success - Read Message from Wake up Message Buffer successfully. + * @retval kStatus_Fail - Wake up Message Buffer has no valid content. + */ +status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); +#endif +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pTxFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); +#endif + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); + +/*! + * @brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame); +#endif + +/*! + * @brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); + +/*! + * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Receives a message from Enhanced Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@ + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); + +/*! + * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, + flexcan_handle_t *handle, + size_t *count) +{ + return FLEXCAN_TransferGetReceiveFifoCount(base, handle, count); +} +#endif + +/*! + * @brief Gets the detail index of Mailbox's Timestamp by handle. + * + * Then function can only be used when calling non-blocking Data transfer (TX/RX) API, + * After TX/RX data transfer done (User can get the status by handler's callback function), + * we can get the detail index of Mailbox's timestamp by handle, + * Detail non-blocking data transfer API (TX/RX) contain. + * -FLEXCAN_TransferSendNonBlocking + * -FLEXCAN_TransferFDSendNonBlocking + * -FLEXCAN_TransferReceiveNonBlocking + * -FLEXCAN_TransferFDReceiveNonBlocking + * -FLEXCAN_TransferReceiveFifoNonBlocking + * + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @retval the index of mailbox 's timestamp stored in the handle. + * + */ +uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle); +#endif + +/*! + * @brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FLEXCAN_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan_edma.c new file mode 100644 index 0000000000..a5f68487f3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan_edma.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexcan_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan_edma" +#endif + +/*base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + framefd = flexcanPrivateHandle->handle->framefd; + for (uint32_t i = 0; i < flexcanPrivateHandle->handle->frameNum; i++) + { + /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */ + idHitIndex = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U; + framefd->idhit = framefd->dataWord[idHitIndex]; + /* Clear the unused frame data. */ + for (uint32_t j = idHitIndex; j < 16U; j++) + { + framefd->dataWord[j] = 0x0U; + } + framefd++; + } + } +#endif + /* Disable transfer. */ + FLEXCAN_TransferAbortReceiveFifoEDMA(flexcanPrivateHandle->base, flexcanPrivateHandle->handle); + + if (NULL != flexcanPrivateHandle->handle->callback) + { + flexcanPrivateHandle->handle->callback(flexcanPrivateHandle->base, flexcanPrivateHandle->handle, + kStatus_FLEXCAN_RxFifoIdle, flexcanPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param callback The callback function. + * param userData The parameter of the callback function. + * param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = FLEXCAN_GetInstance(base); + s_flexcanEdmaPrivateHandle[instance].base = base; + s_flexcanEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(flexcan_edma_handle_t)); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle; + handle->rxFifoEdmaHandle = rxFifoEdmaHandle; + + /* Register Callback. */ + handle->callback = callback; + handle->userData = userData; + + /* Configure Legacy/Enhanced Rx FIFO DMA callback. */ + EDMA_SetCallback(handle->rxFifoEdmaHandle, FLEXCAN_ReceiveFifoEDMACallback, &s_flexcanEdmaPrivateHandle[instance]); +} + +/*! + * brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO. + * + * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO. + * + * param base FlexCAN peripheral base address. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * param pEdmaConfig The user configuration structure of type edma_transfer_t. + * + */ +void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, + flexcan_fifo_transfer_t *pFifoXfer, + edma_transfer_config_t *pEdmaConfig) +{ + assert(NULL != pFifoXfer); + assert(NULL != pFifoXfer->frame); + assert(NULL != pEdmaConfig); + + flexcan_frame_t *fifoAddr = (flexcan_frame_t *)FLEXCAN_GetRxFifoHeadAddr(base); + +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, sizeof(flexcan_frame_t), (void *)pFifoXfer->frame, + sizeof(uint32_t), sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, + kEDMA_PeripheralToMemory); +#else + /* The Data Size of FLEXCAN Legacy RX FIFO output port is 16 Bytes, but lots of chips not support 16Bytes width DMA + * transfer. These chips always support 4Byte width memory transfer, so we need prepare Memory to Memory mode by 4 + * Bytes width mode. + */ + EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, 4U, (void *)pFifoXfer->frame, sizeof(uint32_t), + sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, kEDMA_MemoryToMemory); +#endif +} + +/*! + * brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA. + * + * This function to Update edma transfer confiugration and Start eDMA transfer + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pEdmaConfig The user configuration structure of type edma_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, + flexcan_edma_handle_t *handle, + edma_transfer_config_t *pEdmaConfig) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pEdmaConfig); + status_t status; + + /* If previous Rx FIFO receive not finished. */ + if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState) + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy; + + /* Enable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, true); + + /* Submit configuration. */ + (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, (const edma_transfer_config_t *)pEdmaConfig); + EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo16bytes, + kEDMA_ModuloDisable); + /* Start transfer. */ + EDMA_StartTransfer(handle->rxFifoEdmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives the CAN Messages from the Legacy Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pFifoXfer->frame); + + edma_transfer_config_t dmaXferConfig = {0}; + status_t status; + + handle->frameNum = pFifoXfer->frameNum; + /* Prepare transfer. */ + FLEXCAN_PrepareTransfConfiguration(base, pFifoXfer, &dmaXferConfig); + + /* Submit configuration and start edma transfer. */ + status = FLEXCAN_StartTransferDatafromRxFIFO(base, handle, &dmaXferConfig); + + return status; +} + +/*! + * brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param count Number of CAN messages receive so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + status_t result = kStatus_Success; + + if (handle->rxFifoState == (uint32_t)KFLEXCAN_RxFifoIdle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->frameNum - + EDMA_GetRemainingMajorLoopCount(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel); + } + + return result; +} + +/*! + * brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle) +{ + assert(NULL != handle->rxFifoEdmaHandle); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxFifoEdmaHandle); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + handle->framefd = NULL; +#endif + handle->frameNum = 0U; + /* Disable FlexCAN Legacy/Enhanced Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, false); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA. + * + * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark need be set to + 1 to do successfully EDMA transfer with this API. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pFifoXfer->framefd); + + edma_transfer_config_t dmaXferConfig; + edma_minor_offset_config_t dmaMinorOffsetConfig; + status_t status; + flexcan_fd_frame_t *fifoAddr = (flexcan_fd_frame_t *)E_RX_FIFO(base); + uint32_t perReadWords = ((base->ERFCR & CAN_ERFCR_DMALW_MASK) >> CAN_ERFCR_DMALW_SHIFT) + 1U; + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + + /* If previous Rx FIFO receive not finished. */ + if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState) + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + handle->frameNum = pFifoXfer->frameNum; + handle->framefd = pFifoXfer->framefd; + /*!< To reduce the complexity of DMA software configuration, need to set watermark to 1 to make that each DMA + request read once Rx FIFO. Because a DMA transfer cannot be dynamically changed, Number of words read per + transfer (ERFCR[DMALW] + 1) should be programmed so that the Enhanced Rx FIFO element can store the largest + CAN message present on the CAN bus. */ + if ((watermark != 1U) || ((sizeof(uint32_t) * perReadWords) != sizeof(flexcan_fd_frame_t))) + { + return kStatus_InvalidArgument; + } + + /* Prepare transfer. */ + EDMA_PrepareTransfer( + &dmaXferConfig, (void *)fifoAddr, sizeof(uint32_t), (void *)pFifoXfer->framefd, sizeof(uint32_t), + sizeof(uint32_t) * perReadWords, /* minor loop bytes : 4* perReadWords */ + sizeof(uint32_t) * perReadWords * handle->frameNum, /* major loop counts : handle->frameNum */ + kEDMA_MemoryToMemory); + /* Submit configuration. */ + (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, &dmaXferConfig); + + dmaMinorOffsetConfig.enableDestMinorOffset = false; + dmaMinorOffsetConfig.enableSrcMinorOffset = true; + dmaMinorOffsetConfig.minorOffset = 128U - sizeof(uint32_t) * perReadWords; + EDMA_SetMinorOffsetConfig(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, + &dmaMinorOffsetConfig); + + EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo128bytes, + kEDMA_ModuloDisable); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy; + + /* Enable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, true); + /* Start transfer. */ + EDMA_StartTransfer(handle->rxFifoEdmaHandle); + + status = kStatus_Success; + } + + return status; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan_edma.h new file mode 100644 index 0000000000..98f1f803be --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexcan_edma.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXCAN_EDMA_H_ +#define FSL_FLEXCAN_EDMA_H_ + +#include "fsl_flexcan.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexcan_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN EDMA driver version. */ +#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 3)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexcan_edma_handle flexcan_edma_handle_t; + +/*! @brief FlexCAN transfer callback function. */ +typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, + flexcan_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief FlexCAN eDMA handle + */ +struct _flexcan_edma_handle +{ + flexcan_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + edma_handle_t *rxFifoEdmaHandle; /*!< The EDMA handler for Rx FIFO. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ + size_t frameNum; /*!< The number of messages that need to be received. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *framefd; /*!< Point to the buffer of CAN Message to be received from Enhanced Rx FIFO. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle); + +/*! + * @brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO. + * + * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * + */ +void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, + flexcan_fifo_transfer_t *pFifoXfer, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA. + * + * This function to Update edma transfer confiugration and Start eDMA transfer + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, + flexcan_edma_handle_t *handle, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Receives the CAN Message from the Legacy Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count); +/*! + * @brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA. + * + * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, + flexcan_edma_handle_t *handle, + size_t *count) +{ + return FLEXCAN_TransferGetReceiveFifoCountEMDA(base, handle, count); +} +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FLEXCAN_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio.c new file mode 100644 index 0000000000..52741f2a4d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio.c @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio" +#endif + +/*< @brief user configurable flexio handle count. */ +#define FLEXIO_HANDLE_COUNT 2 + +#if defined(FLEXIO_RSTS) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS +#elif defined(FLEXIO_RSTS_N) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*< @brief pointer to array of FLEXIO handle. */ +static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO IP types. */ +static void *s_flexioType[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO Isr. */ +static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; + +/* FlexIO common IRQ Handler. */ +static void FLEXIO_CommonIRQHandler(void); + +#if defined(FLEXIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Codes + ******************************************************************************/ + +/*! + * brief Get instance number for FLEXIO module. + * + * param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++) + { + if (s_flexioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexioBases)); + + return instance; +} + +/*! + * brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) +{ + uint32_t ctrlReg = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]); +#endif + + FLEXIO_Reset(base); + + ctrlReg = base->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->CTRL = ctrlReg; +} + +/*! + * brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base) +{ + FLEXIO_Enable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + endcode + * + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) +{ + assert(userConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(userConfig, 0, sizeof(*userConfig)); + + userConfig->enableFlexio = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; +} + +/*! + * brief Resets the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base) +{ + /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ + base->CTRL |= FLEXIO_CTRL_SWRST_MASK; + base->CTRL = 0; +} + +/*! + * brief Gets the shifter buffer address for the DMA transfer usage. + * + * param base FlexIO peripheral base address + * param type Shifter type of flexio_shifter_buffer_type_t + * param index Shifter index + * return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) +{ + assert(index < FLEXIO_SHIFTBUF_COUNT); + + uint32_t address = 0; + + switch (type) + { + case kFLEXIO_ShifterBuffer: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + + case kFLEXIO_ShifterBufferBitSwapped: + address = (uint32_t) & (base->SHIFTBUFBIS[index]); + break; + + case kFLEXIO_ShifterBufferByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBYS[index]); + break; + + case kFLEXIO_ShifterBufferBitByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBBS[index]); + break; + +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + case kFLEXIO_ShifterBufferNibbleByteSwapped: + address = (uint32_t) & (base->SHIFTBUFNBS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + case kFLEXIO_ShifterBufferHalfWordSwapped: + address = (uint32_t) & (base->SHIFTBUFHWS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + case kFLEXIO_ShifterBufferNibbleSwapped: + address = (uint32_t) & (base->SHIFTBUFNIS[index]); + break; + +#endif + default: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + } + return address; +} + +/*! + * brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Shifter index + * param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) +{ + base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | + FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); + + base->SHIFTCTL[index] = + FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | + FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | + FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); +} + +/*! + * brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Timer index + * param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) +{ + base->TIMCFG[index] = + FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | + FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | + FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | + FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); + + base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); + + base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | + FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | + FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | + FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | + FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); +} + +/*! + * brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * param handle Pointer to the handler for FlexIO simulated peripheral. + * param isr FlexIO simulated peripheral interrupt handler. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) +{ + assert(base != NULL); + assert(handle != NULL); + assert(isr != NULL); + + uint8_t index; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] == NULL) + { + /* Register FLEXIO simulated driver base, handle and isr. */ + s_flexioType[index] = base; + s_flexioHandle[index] = handle; + s_flexioIsr[index] = isr; + break; + } + } + + if (index == (uint8_t)FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +/*! + * brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base) +{ + assert(base != NULL); + + uint8_t index; + + /* Find the index from base address mappings. */ + for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioType[index] == base) + { + /* Unregister FLEXIO simulated driver handle and isr. */ + s_flexioType[index] = NULL; + s_flexioHandle[index] = NULL; + s_flexioIsr[index] = NULL; + break; + } + } + + if (index == (uint8_t)FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +static void FLEXIO_CommonIRQHandler(void) +{ + uint8_t index; + + for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] != NULL) + { + s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); + } + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER +/*! + * brief Configure a FLEXIO pin used by the board. + * + * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. + * Then, call the FLEXIO_SetPinConfig() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalInput, + * 0U, + * kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable, + * } + * Define a digital output pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalOutput, + * 0U, + * 0U + * } + * endcode + * param base FlexIO peripheral base address + * param pin FLEXIO pin number. + * param config FLEXIO pin configuration pointer. + */ +void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config) +{ + assert(NULL != config); + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + if (config->pinDirection == kFLEXIO_DigitalInput) + { + base->PINOUTE &= ~(1UL << pin); + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_InputInterruptEnable)) + { + base->PINIEN = 1UL << pin; + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base)]); + } + + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagRisingEdgeEnable)) + { + base->PINREN = 1UL << pin; + } + + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagFallingEdgeEnable)) + { + base->PINFEN = 1UL << pin; + } + } + else + { + FLEXIO_EnablePinOutput(base, pin); + FLEXIO_PinWrite(base, pin, config->outputLogic); + } +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + +void FLEXIO_DriverIRQHandler(void); +void FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO0_DriverIRQHandler(void); +void FLEXIO0_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO1_DriverIRQHandler(void); +void FLEXIO1_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void UART2_FLEXIO_DriverIRQHandler(void); +void UART2_FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO2_DriverIRQHandler(void); +void FLEXIO2_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO3_DriverIRQHandler(void); +void FLEXIO3_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio.h new file mode 100644 index 0000000000..86f6553570 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio.h @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_H_ +#define FSL_FLEXIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO driver version. */ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*@}*/ + +/*! @brief Calculate FlexIO timer trigger.*/ +#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) +#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) +#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) + +/*! @brief Define time of timer trigger polarity.*/ +typedef enum _flexio_timer_trigger_polarity +{ + kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ +} flexio_timer_trigger_polarity_t; + +/*! @brief Define type of timer trigger source.*/ +typedef enum _flexio_timer_trigger_source +{ + kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ + kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ +} flexio_timer_trigger_source_t; + +/*! @brief Define type of timer/shifter pin configuration.*/ +typedef enum _flexio_pin_config +{ + kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ + kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ + kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ + kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ +} flexio_pin_config_t; + +/*! @brief Definition of pin polarity.*/ +typedef enum _flexio_pin_polarity +{ + kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ +} flexio_pin_polarity_t; + +/*! @brief Define type of timer work mode.*/ +typedef enum _flexio_timer_mode +{ + kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ + kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ + kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ + kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ +} flexio_timer_mode_t; + +/*! @brief Define type of timer initial output or timer reset condition.*/ +typedef enum _flexio_timer_output +{ + kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ + kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ +} flexio_timer_output_t; + +/*! @brief Define type of timer decrement.*/ +typedef enum _flexio_timer_decrement_source +{ + kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock + equals Timer output. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcOnPinInputShiftPinInput, /*!< Decrement counter on Pin input (both edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Trigger input. */ +#if (defined(FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH) && (FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH == 3)) + , + kFLEXIO_TimerDecSrcDiv16OnFlexIOClockShiftTimerOutput, /*!< Decrement counter on FlexIO clock divided by 16, + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcDiv256OnFlexIOClockShiftTimerOutput, /*!< Decrement counter on FlexIO clock divided by 256, + Shift clock equals Timer output. */ + kFLEXIO_TimerRisSrcOnPinInputShiftPinInput, /*!< Decrement counter on Pin input (rising edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerRisSrcOnTriggerInputShiftTriggerInput /*!< Decrement counter on Trigger input (rising edges), Shift + clock equals Trigger input. */ +#endif /* FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH */ +} flexio_timer_decrement_source_t; + +/*! @brief Define type of timer reset condition.*/ +typedef enum _flexio_timer_reset_condition +{ + kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ + kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to + Timer Output. */ + kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ +} flexio_timer_reset_condition_t; + +/*! @brief Define type of timer disable condition.*/ +typedef enum _flexio_timer_disable_condition +{ + kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ + kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ + kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ + kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ + kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided + Trigger is high. */ + kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ +} flexio_timer_disable_condition_t; + +/*! @brief Define type of timer enable condition.*/ +typedef enum _flexio_timer_enable_condition +{ + kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ + kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ + kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ + kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ + kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ + kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ + kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ +} flexio_timer_enable_condition_t; + +/*! @brief Define type of timer stop bit generate condition.*/ +typedef enum _flexio_timer_stop_bit_condition +{ + kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ + kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ + kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ + kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer + disable. */ +} flexio_timer_stop_bit_condition_t; + +/*! @brief Define type of timer start bit generate condition.*/ +typedef enum _flexio_timer_start_bit_condition +{ + kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ + kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ +} flexio_timer_start_bit_condition_t; + +/*! @brief FlexIO as PWM channel output state */ +typedef enum _flexio_timer_output_state +{ + kFLEXIO_PwmLow = 0, /*!< The output state of PWM channel is low */ + kFLEXIO_PwmHigh, /*!< The output state of PWM channel is high */ +} flexio_timer_output_state_t; + +/*! @brief Define type of timer polarity for shifter control. */ +typedef enum _flexio_shifter_timer_polarity +{ + kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */ +} flexio_shifter_timer_polarity_t; + +/*! @brief Define type of shifter working mode.*/ +typedef enum _flexio_shifter_mode +{ + kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ + kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ + kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ + kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ + kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ +#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE + kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing + programmable state attributes. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ +#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE + kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing + programmable logic look up table. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ +} flexio_shifter_mode_t; + +/*! @brief Define type of shifter input source.*/ +typedef enum _flexio_shifter_input_source +{ + kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ + kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ +} flexio_shifter_input_source_t; + +/*! @brief Define of STOP bit configuration.*/ +typedef enum _flexio_shifter_stop_bit +{ + kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ + kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ + kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ +} flexio_shifter_stop_bit_t; + +/*! @brief Define type of START bit configuration.*/ +typedef enum _flexio_shifter_start_bit +{ + kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads + data on enable. */ + kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads + data on first shift. */ + kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ + kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ +} flexio_shifter_start_bit_t; + +/*! @brief Define FlexIO shifter buffer type*/ +typedef enum _flexio_shifter_buffer_type +{ + kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ + kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ + kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ + kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ +#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ +#endif +} flexio_shifter_buffer_type_t; + +/*! @brief Define FlexIO user configuration structure. */ +typedef struct _flexio_config_ +{ + bool enableFlexio; /*!< Enable/disable FlexIO module */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ +} flexio_config_t; + +/*! @brief Define FlexIO timer configuration structure. */ +typedef struct _flexio_timer_config +{ + /* Trigger. */ + uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ + flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ + flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ + uint32_t pinSelect; /*!< Timer Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ + /* Timer. */ + flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ + flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and + whether it is affected by the Timer reset. */ + flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the + source of the Shift clock. */ + flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter + (and optionally the timer output) to be reset. */ + flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be + disabled and stop decrementing. */ + flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be + enabled and start decrementing. */ + flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ + flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ + uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ +} flexio_timer_config_t; + +/*! @brief Define FlexIO shifter configuration structure. */ +typedef struct _flexio_shifter_config +{ + /* Timer. */ + uint32_t timerSelect; /*!< Selects which Timer is used for controlling the + logic/shift register and generating the Shift clock. */ + flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ + uint32_t pinSelect; /*!< Shifter Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ + /* Shifter. */ + flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ + flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ + flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ +} flexio_shifter_config_t; + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER +/*! @brief FLEXIO gpio direction definition */ +typedef enum _flexio_gpio_direction +{ + kFLEXIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kFLEXIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} flexio_gpio_direction_t; + +/*! @brief FLEXIO gpio input config */ +typedef enum _flexio_pin_input_config +{ + kFLEXIO_InputInterruptDisabled = 0x0U, /*!< Interrupt request is disabled. */ + kFLEXIO_InputInterruptEnable = 0x1U, /*!< Interrupt request is enable. */ + kFLEXIO_FlagRisingEdgeEnable = 0x2U, /*!< Input pin flag on rising edge. */ + kFLEXIO_FlagFallingEdgeEnable = 0x4U, /*!< Input pin flag on falling edge. */ +} flexio_pin_input_config_t; + +/*! + * @brief The FLEXIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, use inputConfig param. + * If configured as an output pin, use outputLogic. + */ +typedef struct _flexio_gpio_config +{ + flexio_gpio_direction_t pinDirection; /*!< FLEXIO pin direction, input or output */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + uint8_t inputConfig; /*!< Set an input config */ +} flexio_gpio_config_t; +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + +/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ +typedef void (*flexio_isr_t)(void *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +extern FLEXIO_Type *const s_flexioBases[]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +extern const clock_ip_name_t s_flexioClocks[]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + @code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + @endcode + * + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); + +/*! + * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + @code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); + +/*! + * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * @note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base); + +/*! + * @brief Get instance number for FLEXIO module. + * + * @param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); + +/* @} */ + +/*! + * @name FlexIO Basic Operation + * @{ + */ + +/*! + * @brief Resets the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base); + +/*! + * @brief Enables the FlexIO module operation. + * + * @param base FlexIO peripheral base address + * @param enable true to enable, false to disable. + */ +static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Reads the input data on each of the FlexIO pins. + * + * @param base FlexIO peripheral base address + * @return FlexIO pin input data + */ +static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) +{ + return base->PIN; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE +/*! + * @brief Gets the current state pointer for state mode use. + * + * @param base FlexIO peripheral base address + * @return current State pointer + */ +static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) +{ + return ((uint8_t)(base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); +} +#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ + +/*! + * @brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + @code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Shifter index + * @param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); +/*! + * @brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + @code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Timer index + * @param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); + +/*! + * @brief This function set the value of the prescaler on flexio channels + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @param index Timer index + * @param clocksource Set clock value + */ +static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource) +{ + uint32_t reg = base->TIMCFG[index]; + + reg &= ~FLEXIO_TIMCFG_TIMDEC_MASK; + + reg |= FLEXIO_TIMCFG_TIMDEC(clocksource); + + base->TIMCFG[index] = reg; +} + +/* @} */ + +/*! + * @name FlexIO Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN |= mask; +} + +/*! + * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN &= ~mask; +} + +/*! + * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN |= mask; +} + +/*! + * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN &= ~mask; +} + +/*! + * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN |= mask; +} + +/*! + * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN &= ~mask; +} + +/* @} */ + +/*! + * @name FlexIO Status Operation + * @{ + */ + +/*! + * @brief Gets the shifter status flags. + * + * @param base FlexIO peripheral base address + * @return Shifter status flags + */ +static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); +} + +/*! + * @brief Clears the shifter status flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSTAT = mask; +} + +/*! + * @brief Gets the shifter error flags. + * + * @param base FlexIO peripheral base address + * @return Shifter error flags + */ +static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); +} + +/*! + * @brief Clears the shifter error flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTERR = mask; +} + +/*! + * @brief Gets the timer status flags. + * + * @param base FlexIO peripheral base address + * @return Timer status flags + */ +static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) +{ + return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); +} + +/*! + * @brief Clears the timer status flags. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMSTAT = mask; +} + +/* @} */ + +/*! + * @name FlexIO DMA Operation + * @{ + */ + +/*! + * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. + * + * @note For multiple shifter status DMA enables, for example, calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SHIFTSDEN |= mask; + } + else + { + base->SHIFTSDEN &= ~mask; + } +} + +/*! + * @brief Gets the shifter buffer address for the DMA transfer usage. + * + * @param base FlexIO peripheral base address + * @param type Shifter type of flexio_shifter_buffer_type_t + * @param index Shifter index + * @return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); + +/*! + * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @param handle Pointer to the handler for FlexIO simulated peripheral. + * @param isr FlexIO simulated peripheral interrupt handler. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); + +/*! + * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base); +/* @} */ + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER + +/*! + * @brief Configure a FLEXIO pin used by the board. + * + * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. + * Then, call the FLEXIO_SetPinConfig() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalInput, + * 0U, + * kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable, + * } + * Define a digital output pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalOutput, + * 0U, + * 0U + * } + * @endcode + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @param config FLEXIO pin configuration pointer. + */ +void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config); + +/*! + * @name GPIO Output Operations + * @{ + */ + +/*! + * @brief Sets the output level of the multiple FLEXIO pins to the logic 0. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTCLR = mask; +} + +/*! + * @brief Sets the output level of the multiple FLEXIO pins to the logic 1. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTSET = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FLEXIO pins. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTTOG = mask; +} + +/*! + * @brief Sets the output level of the FLEXIO pins to the logic 1 or 0. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @param output FLEXIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + FLEXIO_ClearPortOutput(base, 1UL << pin); + } + else + { + FLEXIO_SetPortOutput(base, 1UL << pin); + } +} + +/*! + * @brief Enables the FLEXIO output pin function. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + */ +static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin) +{ + base->PINOUTE |= (1UL << pin); +} +/*@}*/ + +/*! + * @name FLEXIO PIN Input Operations + * @{ + */ + +/*! + * @brief Reads the current input value of the FLEXIO pin. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @retval FLEXIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin) +{ + return (((base->PIN) >> pin) & 0x01U); +} + +/*! + * @brief Gets the FLEXIO input pin status. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @retval FLEXIO port input status + * - 0: corresponding pin input capture no status. + * - 1: corresponding pin input capture rising or falling edge. + */ +static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin) +{ + return (((base->PINSTAT) >> pin) & 0x01U); +} + +/*! + * @brief Clears the multiple FLEXIO input pins status. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask) +{ + base->PINSTAT = mask; +} +/*@}*/ + +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*FSL_FLEXIO_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_i2c_master.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_i2c_master.c new file mode 100644 index 0000000000..9239527c6f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_i2c_master.c @@ -0,0 +1,1377 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_i2c_master.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master" +#endif + +/*! @brief FLEXIO I2C transfer state */ +enum _flexio_i2c_master_transfer_states +{ + kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ + kFLEXIO_I2C_Start = 0x1U, /*!< I2C start phase */ + kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ + kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ + kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ + kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param transfer pointer to flexio_i2c_master_transfer_t structure + */ +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * @retval kStatus_Success Successfully run state machine + * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer + */ +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief Complete transfer, disable interrupt and call callback. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param status flexio transfer status + */ +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineStart. + * This function was deal with Initial state, i2c start state. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +static void FLEXIO_I2C_MasterTransferStateMachineStart(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineSendCommand. + * This function was deal with Check address only needed for transfer with subaddress . + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is true when No abnormality. + * @return false when time out. + */ +static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineSendData. + * This function was deal with Send command byte. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is true when No abnormality. + * @return false when time out. + */ +static bool FLEXIO_I2C_MasterTransferStateMachineSendData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin. + * This function was deal with Receive Data Begin. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is true when No abnormality. + * @return false when time out. + */ +static bool FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief introduce function Case_kFLEXIO_I2C_ReceiveDataBegin. + * This function was deal with Receive Data. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is kStatus_Success when No abnormality. + * @return kStatus_FLEXIO_I2C_Nak when ReceiveNakFlag is not set. + * @return kStatus_FLEXIO_I2C_Timeout when time out. + */ +static status_t FLEXIO_I2C_MasterTransferStateMachineReceiveData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + bool needRestart; + uint32_t byteCount; + + /* Init the handle member. */ + handle->transfer.slaveAddress = xfer->slaveAddress; + handle->transfer.direction = xfer->direction; + handle->transfer.subaddress = xfer->subaddress; + handle->transfer.subaddressSize = xfer->subaddressSize; + handle->transfer.data = xfer->data; + handle->transfer.dataSize = xfer->dataSize; + handle->transfer.flags = xfer->flags; + handle->transferSize = xfer->dataSize; + + /* Initial state, i2c start state. */ + handle->state = (uint8_t)kFLEXIO_I2C_Start; + + /* Clear all status before transfer. */ + FLEXIO_I2C_MasterClearStatusFlags(base, (uint32_t)kFLEXIO_I2C_ReceiveNakFlag); + + /* Calculate whether need to send re-start. */ + needRestart = (handle->transfer.subaddressSize != 0U) && (handle->transfer.direction == kFLEXIO_I2C_Read); + handle->needRestart = needRestart; + + /* Calculate total byte count in a frame. */ + byteCount = 1U; + + if (!needRestart) + { + byteCount += handle->transfer.dataSize; + } + + if (handle->transfer.subaddressSize != 0U) + { + byteCount += handle->transfer.subaddressSize; + } + + /* Configure data count. */ + if (FLEXIO_I2C_MasterSetTransferCount(base, (uint16_t)byteCount) != kStatus_Success) + { + return kStatus_InvalidArgument; + } + + /* Configure timer1 disable condition. */ + uint32_t tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[1]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPreTimerDisable); + base->flexioBase->TIMCFG[base->timerIndex[1]] = tmpConfig; + +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + + return kStatus_Success; +} + +static void FLEXIO_I2C_MasterTransferStateMachineStart(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) +{ + if (handle->needRestart) + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write); + } + else + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction); + } + if (handle->transfer.subaddressSize == 0U) + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kFLEXIO_I2C_SendData; + } + else + { + /* Next state, receive data begin. */ + handle->state = (uint8_t)kFLEXIO_I2C_ReceiveDataBegin; + } + } + else + { + /* Next state, send command byte. */ + handle->state = (uint8_t)kFLEXIO_I2C_SendCommand; + } +} + +static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + if (handle->transfer.subaddressSize > 0U) + { + handle->transfer.subaddressSize--; + FLEXIO_I2C_MasterWriteByte(base, ((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize))); + + if (handle->transfer.subaddressSize == 0U) + { + /* Load re-start in advance. */ + if (handle->transfer.direction == kFLEXIO_I2C_Read) + { +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + FLEXIO_I2C_MasterRepeatedStart(base); + } + } + } + else + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0U) + { + /* Next state, send data. */ + handle->state = (uint8_t)kFLEXIO_I2C_SendData; + + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + (void)FLEXIO_I2C_MasterReadByte(base); + + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + } + } + else + { + (void)FLEXIO_I2C_MasterSetTransferCount(base, (uint16_t)(handle->transfer.dataSize + 1U)); + /* Delay at least one clock cycle so that the restart setup time is up to spec standard. */ + SDK_DelayAtLeastUs(1000000UL / base->baudrate, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read); + + /* Next state, receive data begin. */ + handle->state = (uint8_t)kFLEXIO_I2C_ReceiveDataBegin; + } + } + } + return true; +} + +static bool FLEXIO_I2C_MasterTransferStateMachineSendData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0U) + { + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + (void)FLEXIO_I2C_MasterReadByte(base); + + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + } + } + return true; +} + +static bool FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U) + { + handle->state = (uint8_t)kFLEXIO_I2C_ReceiveData; + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1U) + { + FLEXIO_I2C_MasterEnableAck(base, false); +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + FLEXIO_I2C_MasterStop(base); + } + else + { + FLEXIO_I2C_MasterEnableAck(base, true); + } + } + else if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + /* Read one byte of data. */ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + else + { + ; /* Avoid MISRA 2012 rule 15.7 */ + } + return true; +} + +static status_t FLEXIO_I2C_MasterTransferStateMachineReceiveData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U) + { + *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base); + handle->transfer.data++; + if (0U != handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0U) + { + FLEXIO_I2C_MasterDisableInterrupts(base, (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + /* Return nak if ReceiveNakFlag is not set */ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) == 0U) + { + return kStatus_FLEXIO_I2C_Nak; + } + } + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1U) + { + FLEXIO_I2C_MasterEnableAck(base, false); +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + FLEXIO_I2C_MasterStop(base); + } + } + } + else if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + if (handle->transfer.dataSize > 1U) + { + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + } + else + { + ; /* Avoid MISRA 2012 rule 15.7 */ + } + return kStatus_Success; +} + +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + status_t status; +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + if ((statusFlags & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U) + { + /* Clear receive nak flag. */ + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + + if ((!((handle->state == (uint8_t)kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) && + (!(((handle->state == (uint8_t)kFLEXIO_I2C_ReceiveData) || + (handle->state == (uint8_t)kFLEXIO_I2C_ReceiveDataBegin)) && + (handle->transfer.dataSize == 1U)))) + { + (void)FLEXIO_I2C_MasterReadByte(base); + + FLEXIO_I2C_MasterAbortStop(base); + + /* Delay one clk cycle to ensure the bus is idle. */ + SDK_DelayAtLeastUs(1000000UL / base->baudrate, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + + return kStatus_FLEXIO_I2C_Nak; + } + } + + if (((statusFlags & (uint8_t)kFLEXIO_I2C_RxFullFlag) != 0U) && (handle->state != (uint8_t)kFLEXIO_I2C_ReceiveData)) + { + (void)FLEXIO_I2C_MasterReadByte(base); + } + + switch (handle->state) + { + /* Initial state, i2c start state. */ + case (uint8_t)kFLEXIO_I2C_Start: + /* Send address byte first. */ + FLEXIO_I2C_MasterTransferStateMachineStart(base, handle); + break; + + /* Check address only needed for transfer with subaddress */ + case (uint8_t)kFLEXIO_I2C_SendCommand: + if (false == FLEXIO_I2C_MasterTransferStateMachineSendCommand(base, handle, statusFlags)) + { + return kStatus_FLEXIO_I2C_Timeout; + } + break; + + /* Send command byte. */ + case (uint8_t)kFLEXIO_I2C_SendData: + if (false == FLEXIO_I2C_MasterTransferStateMachineSendData(base, handle, statusFlags)) + { + return kStatus_FLEXIO_I2C_Timeout; + } + break; + + case (uint8_t)kFLEXIO_I2C_ReceiveDataBegin: + if (false == FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(base, handle, statusFlags)) + { + return kStatus_FLEXIO_I2C_Timeout; + } + break; + + case (uint8_t)kFLEXIO_I2C_ReceiveData: + status = FLEXIO_I2C_MasterTransferStateMachineReceiveData(base, handle, statusFlags); + if (kStatus_Success != status) + { + return status; + } + break; + + default: + /* Add comment to avoid MISRA violation */ + break; + } + + return kStatus_Success; +} + +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status) +{ + FLEXIO_I2C_MasterDisableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, status, handle->userData); + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * brief Make sure the bus isn't already pulled down. + * + * Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * retval kStatus_Success + * retval kStatus_FLEXIO_I2C_Busy + */ +status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base) +{ + uint32_t mask; + /* If in certain loops the SDA/SCL is continuously pulled down, then return bus busy status. */ + /* The loop count is determined by maximum CPU clock frequency */ + for (uint32_t i = 0U; i < SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 600000U; ++i) + { + mask = 1UL << base->SDAPinIndex | 1UL << base->SCLPinIndex; + if ((FLEXIO_ReadPinInput(base->flexioBase) & mask) == mask) + { + return kStatus_Success; + } + } + return kStatus_FLEXIO_I2C_Busy; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + endcode + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param masterConfig Pointer to flexio_i2c_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Initialization successful + * retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert((base != NULL) && (masterConfig != NULL)); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t controlVal = 0; + uint16_t timerDiv = 0; + status_t result = kStatus_Success; + + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[2]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[2]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 and timer 1 for generating bit clock. */ + /* timer 1 is used to config baudrate */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + /* Set TIMCMP = (baud rate divider / 2) - 1. */ + timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps) / 2U - 1U; + /* Calculate and assign the actual baudrate. */ + base->baudrate = srcClock_Hz / (2U * ((uint32_t)timerDiv + 1U)); + + timerConfig.timerCompare = timerDiv; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + /* timer 0 is used to config total shift clock edges */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + /* Set TIMCMP when confinguring transfer bytes. */ + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 2 for controlling shifters. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ + timerConfig.timerCompare = 8U * 2U - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[2], &timerConfig); + + /* Configure FLEXIO I2C Master. */ + controlVal = base->flexioBase->CTRL; + controlVal &= + ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + controlVal |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = controlVal; + /* Disable internal IRQs. */ + FLEXIO_I2C_MasterDisableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + return result; +} + +/*! + * brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[2]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[2]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[2]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[1]); + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[2]); +} + +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + endcode + * param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; +} + +/*! + * brief Gets the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure + * return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. + */ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) +{ + uint32_t status = 0; + + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + + return status; +} + +/*! + * brief Clears the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_I2C_RxFullFlag + * arg kFLEXIO_I2C_ReceiveNakFlag + */ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]); + } + + if ((mask & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } + + if ((mask & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Enables the FlexIO i2c master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + * Currently only one interrupt request source: + * arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO I2C master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Sets the FlexIO I2C master transfer baudrate. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param baudRate_Bps the baud rate value in HZ + * param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t timerDiv = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP = (baud rate divider / 2) - 1.*/ + timerDiv = (uint16_t)((srcClock_Hz / baudRate_Bps) / 2U - 1U); + + flexioBase->TIMCMP[base->timerIndex[1]] = timerDiv; + + /* Calculate and assign the actual baudrate. */ + base->baudrate = srcClock_Hz / (2U * ((uint32_t)timerDiv + 1U)); +} + +/*! + * brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * retval kStatus_Success Successfully configured the count. + * retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count) +{ + /* Calculate whether the transfer count is larger than the max value compare register can achieve */ + if (count > ((0xFFFFUL - 1UL) / (16UL + 1UL + 1UL))) + { + return kStatus_InvalidArgument; + } + + uint32_t timerConfig = 0U; + FLEXIO_Type *flexioBase = base->flexioBase; + + flexioBase->TIMCMP[base->timerIndex[0]] = (uint32_t)count * 18U + 1U; + timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; + timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; + + return kStatus_Success; +} + +/*! + * brief Sends START + 7-bit address to the bus. + * + * note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * param base Pointer to FLEXIO_I2C_Type structure. + * param address 7-bit address. + * param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * arg kFLEXIO_I2C_Write: Transmit + * arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) +{ + uint32_t data; + + data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U); + + FLEXIO_I2C_MasterWriteByte(base, data); +} + +/*! + * brief Sends the repeated start signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) +{ + /* Prepare for RESTART condition, no stop.*/ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); +} + +/*! + * brief Sends the stop signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) +{ + /* Prepare normal stop. */ + (void)FLEXIO_I2C_MasterSetTransferCount(base, 0x0U); + FLEXIO_I2C_MasterWriteByte(base, 0x0U); +} + +/*! + * brief Sends the stop signal when transfer is still on-going. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) +{ + uint32_t tmpConfig; + + /* Prepare abort stop. */ + /* Disable timer 0. */ + tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); + base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; + + /* Disable timer 1. */ + tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[1]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); + base->flexioBase->TIMCFG[base->timerIndex[1]] = tmpConfig; +} + +/*! + * brief Configures the sent ACK/NAK for the following byte. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param enable True to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) +{ + uint32_t tmpConfig = 0; + + tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; + tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK; + if (enable) + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow); + } + else + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh); + } + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; +} + +/*! + * brief Sends a buffer of data in bytes. + * + * note This function blocks via polling until all bytes have been sent. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param txBuff The data bytes to send. + * param txSize The number of data bytes to send. + * retval kStatus_Success Successfully write data. + * retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) +{ + assert(txBuff != NULL); + assert(txSize != 0U); + + uint32_t status; +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + while (0U != txSize--) + { + FLEXIO_I2C_MasterWriteByte(base, *txBuff++); + + /* Wait until data transfer complete. */ +#if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; + while ((0U == ((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == ((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + + if ((status & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + return kStatus_FLEXIO_I2C_Nak; + } + } + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param rxBuff The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + * retval kStatus_Success Successfully read data. + * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) +{ + assert(rxBuff != NULL); + assert(rxSize != 0U); + +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + while (0U != rxSize--) + { + /* Wait until data transfer complete. */ +#if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; + while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + *rxBuff++ = FLEXIO_I2C_MasterReadByte(base); + } + return kStatus_Success; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * param base pointer to FLEXIO_I2C_Type structure. + * param xfer pointer to flexio_i2c_master_transfer_t structure. + * return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer) +{ + assert(xfer != NULL); + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS + /* Return an error if the bus is already in use not by us.*/ + status_t status = FLEXIO_I2C_CheckForBusyBus(base); + if (status != kStatus_Success) + { + return status; + } +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + + flexio_i2c_master_handle_t tmpHandle; + uint32_t statusFlags; + status_t result = kStatus_Success; +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Zero the handle. */ + (void)memset(&tmpHandle, 0, sizeof(tmpHandle)); + + /* Set up transfer machine. */ + result = FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer); + if (result != kStatus_Success) + { + return result; + } + + do + { + /* Wait either tx empty or rx full flag is asserted. */ +#if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; + while ((0U == ((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & + ((uint32_t)kFLEXIO_I2C_TxEmptyFlag | (uint32_t)kFLEXIO_I2C_RxFullFlag))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == ((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & + ((uint32_t)kFLEXIO_I2C_TxEmptyFlag | (uint32_t)kFLEXIO_I2C_RxFullFlag))) + { + } +#endif + FLEXIO_ClearTimerStatusFlags(base->flexioBase, ((1UL << base->timerIndex[0]) | (1UL << base->timerIndex[1]))); + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags); + + } while ((tmpHandle.state != (uint8_t)kFLEXIO_I2C_Idle) && (result == kStatus_Success)); + + /* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent. + */ + while (0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1UL << base->timerIndex[1]))) + { + } + + return result; +} + +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * param callback Pointer to user callback function. + * param userData User param passed to the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); + (void)EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); +} + +/*! + * brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * param xfer pointer to flexio_i2c_master_transfer_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + status_t result = kStatus_Success; + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS + /* Return an error if the bus is already in use not by us.*/ + result = FLEXIO_I2C_CheckForBusyBus(base); + if (result != kStatus_Success) + { + return result; + } +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + + if (handle->state != (uint8_t)kFLEXIO_I2C_Idle) + { + return kStatus_FLEXIO_I2C_Busy; + } + else + { + /* Set up transfer machine. */ + result = FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer); + if (result != kStatus_Success) + { + return result; + } + + /* Enable both tx empty and rxfull interrupt. */ + FLEXIO_I2C_MasterEnableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + + return kStatus_Success; + } +} + +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupts. */ + FLEXIO_I2C_MasterDisableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + + /* Reset to idle state. */ + handle->state = (uint8_t)kFLEXIO_I2C_Idle; +} + +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) +{ + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kFLEXIO_I2C_Idle) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +/*! + * brief Master interrupt handler. + * + * param i2cType Pointer to FLEXIO_I2C_Type structure + * param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) +{ + FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; + flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; + uint32_t statusFlags; + status_t result; + + statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base); + + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags); + + if (handle->state == (uint8_t)kFLEXIO_I2C_Idle) + { + FLEXIO_I2C_MasterTransferComplete(base, handle, result); + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_i2c_master.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_i2c_master.h new file mode 100644 index 0000000000..02dd10a48b --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_i2c_master.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_I2C_MASTER_H_ +#define FSL_FLEXIO_I2C_MASTER_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2c_master + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief FlexIO I2C transfer status*/ +enum +{ + kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ + kStatus_FLEXIO_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 3), /*!< Timeout polling status flags. */ +}; + +/*! @brief Define FlexIO I2C master interrupt mask. */ +enum _flexio_i2c_master_interrupt +{ + kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ + kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO I2C master status mask. */ +enum _flexio_i2c_master_status_flags +{ + kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ + kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ + kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ +}; + +/*! @brief Direction of master transfer.*/ +typedef enum _flexio_i2c_direction +{ + kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ + kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ +} flexio_i2c_direction_t; + +/*! @brief Define FlexIO I2C master access structure typedef. */ +typedef struct _flexio_i2c_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDAPinIndex; /*!< Pin select for I2C SDA. */ + uint8_t SCLPinIndex; /*!< Pin select for I2C SCL. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */ + uint8_t timerIndex[3]; /*!< Timer index used in FlexIO I2C. */ + uint32_t baudrate; /*!< Master transfer baudrate, used to calculate delay time. */ +} FLEXIO_I2C_Type; + +/*! @brief Define FlexIO I2C master user configuration structure. */ +typedef struct _flexio_i2c_master_config +{ + bool enableMaster; /*!< Enables the FlexIO I2C peripheral at initialization time. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ +} flexio_i2c_master_config_t; + +/*! @brief Define FlexIO I2C master transfer structure. */ +typedef struct _flexio_i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t volatile *data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} flexio_i2c_master_transfer_t; + +/*! @brief FlexIO I2C master handle typedef. */ +typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t; + +/*! @brief FlexIO I2C master transfer callback typedef. */ +typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2C master handle structure. */ +struct _flexio_i2c_master_handle +{ + flexio_i2c_master_transfer_t transfer; /*!< FlexIO I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */ + /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback function. */ + bool needRestart; /*!< Whether master needs to send re-start signal. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Make sure the bus isn't already pulled down. + * + * Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down. + * + * @param base Pointer to FLEXIO_I2C_Type structure.. + * @retval kStatus_Success + * @retval kStatus_FLEXIO_I2C_Busy + */ +status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base); +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + @code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Initialization successful + * @retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + @code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + @endcode + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig); + +/*! + * @brief Enables/disables the FlexIO module operation. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable Pass true to enable module, false does not have any effect. + */ +static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. + */ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); + +/*! + * @brief Clears the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_I2C_RxFullFlag + * @arg kFLEXIO_I2C_ReceiveNakFlag + */ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO i2c master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + * Currently only one interrupt request source: + * @arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2C master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the FlexIO I2C master transfer baudrate. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param baudRate_Bps the baud rate value in HZ + * @param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends START + 7-bit address to the bus. + * + * @note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param address 7-bit address. + * @param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * @arg kFLEXIO_I2C_Write: Transmit + * @arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction); + +/*! + * @brief Sends the stop signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the repeated start signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the stop signal when transfer is still on-going. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Configures the sent ACK/NAK for the following byte. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable True to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); + +/*! + * @brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * @note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * @retval kStatus_Success Successfully configured the count. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count); + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param data a byte of data. + */ +static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; +} + +/*! + * @brief Reads one byte of data from the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the data is ready in the register. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @return data byte read. + */ +static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base) +{ + return (uint8_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]); +} + +/*! + * @brief Sends a buffer of data in bytes. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param txBuff The data bytes to send. + * @param txSize The number of data bytes to send. + * @retval kStatus_Success Successfully write data. + * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param rxBuff The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + * @retval kStatus_Success Successfully read data. + * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param xfer pointer to flexio_i2c_master_transfer_t structure. + * @return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer); +/*@}*/ + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * @param callback Pointer to user callback function. + * @param userData User param passed to the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param xfer pointer to flexio_i2c_master_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param i2cType Pointer to FLEXIO_I2C_Type structure + * @param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd.c new file mode 100644 index 0000000000..217b6595a3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd.c @@ -0,0 +1,1334 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +enum _mculcd_transfer_state +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. */ +}; + +/* The TIMCFG[0:7] is used for baud rate divider in dual 8-bit counters baud/bit mode. */ +#define FLEXIO_BAUDRATE_DIV_MASK 0xFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the + * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD + * configuration. + * The configuration structure can be filled by the user, or be set with default + * values + * by the ref FLEXIO_MCULCD_GetDefaultConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param config Pointer to the flexio_mculcd_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Initialization success. + * retval kStatus_InvalidArgument Initialization failed because of invalid + * argument. + */ +status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + status_t status; + + flexio_config_t flexioConfig = {config->enable, config->enableInDoze, config->enableInDebug, + config->enableFastAccess}; + + FLEXIO_Init(base->flexioBase, &flexioConfig); + + status = FLEXIO_MCULCD_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + + if (kStatus_Success == status) + { + base->setCSPin(true); + base->setRSPin(true); + } + + return status; +} + +/*! + * brief Resets the FLEXIO_MCULCD timer and shifter configuration. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + */ +void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base) +{ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); +} + +/*! + * brief Gets the default configuration to configure the FlexIO MCULCD. + * + * The default configuration value is: + * code + * config->enable = true; + * config->enableInDoze = false; + * config->enableInDebug = true; + * config->enableFastAccess = true; + * config->baudRate_Bps = 96000000U; + * endcode + * param Config Pointer to the flexio_mculcd_config_t structure. + */ +void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enable = true; + config->enableInDoze = false; + config->enableInDebug = true; + config->enableFastAccess = true; + config->baudRate_Bps = 96000000U; +} + +/*! + * brief Set desired baud rate. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined. + * param srcClock_Hz FLEXIO clock frequency in Hz. + * retval kStatus_Success Set successfully. + * retval kStatus_InvalidArgument Could not set the baud rate. + */ +status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t baudRateDiv; + uint32_t baudRatePerDataLine; + uint32_t timerCompare; + status_t status; + + baudRatePerDataLine = baudRate_Bps / (uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH; + + baudRateDiv = (srcClock_Hz + baudRatePerDataLine) / (baudRatePerDataLine * 2U); + + if ((0U == baudRateDiv) || (baudRateDiv > (FLEXIO_BAUDRATE_DIV_MASK + 1U))) + { + status = kStatus_InvalidArgument; + } + else + { + baudRateDiv--; + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex]; + + timerCompare = (timerCompare & ~FLEXIO_BAUDRATE_DIV_MASK) | baudRateDiv; + + base->flexioBase->TIMCMP[base->timerIndex] = timerCompare; + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Gets FlexIO MCULCD status flags. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * return status flag; OR'ed value or the ref _flexio_mculcd_status_flags. + * + * note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base) +{ + uint32_t ret = 0U; + uint32_t flags; + + /* Get shifter status. */ + flags = FLEXIO_GetShifterStatusFlags(base->flexioBase); + + if (0U != (flags & (1UL << base->rxShifterEndIndex))) + { + ret |= (uint32_t)kFLEXIO_MCULCD_RxFullFlag; + } + + if (0U != (flags & (1UL << base->txShifterStartIndex))) + { + ret |= (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag; + } + + return ret; +} + +/*! + * brief Clears FlexIO MCULCD status flags. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Status to clear, it is the OR'ed value of ref + * _flexio_mculcd_status_flags. + * + * note Don't use this function with DMA APIs. + */ +void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t flags = 0U; + + /* Clear the shifter flags. */ + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_RxFullFlag)) + { + flags |= (1UL << base->rxShifterEndIndex); + } + + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag)) + { + flags |= (1UL << base->txShifterStartIndex); + } + + FLEXIO_ClearShifterStatusFlags(base->flexioBase, flags); +} + +/*! + * brief Enables the FlexIO MCULCD interrupt. + * + * This function enables the FlexIO MCULCD interrupt. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Interrupts to enable, it is the OR'ed value of ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t interrupts = 0U; + + /* Enable shifter interrupts. */ + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_RxFullFlag)) + { + interrupts |= (1UL << base->rxShifterEndIndex); + } + + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag)) + { + interrupts |= (1UL << base->txShifterStartIndex); + } + + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, interrupts); +} + +/*! + * brief Disables the FlexIO MCULCD interrupt. + * + * This function disables the FlexIO MCULCD interrupt. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Interrupts to disable, it is the OR'ed value of ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t interrupts = 0U; + + /* Disable shifter interrupts. */ + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_RxFullFlag)) + { + interrupts |= (1UL << base->rxShifterEndIndex); + } + + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag)) + { + interrupts |= (1UL << base->txShifterStartIndex); + } + + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, interrupts); +} + +/*! + * brief Read data from the FLEXIO MCULCD RX shifter buffer. + * + * Read data from the RX shift buffer directly, it does no check whether the + * buffer is empty or not. + * + * If the data bus width is 8-bit: + * code + * uint8_t value; + * value = (uint8_t)FLEXIO_MCULCD_ReadData(base); + * endcode + * + * If the data bus width is 16-bit: + * code + * uint16_t value; + * value = (uint16_t)FLEXIO_MCULCD_ReadData(base); + * endcode + * + * note This function returns the RX shifter buffer value (32-bit) directly. + * The return value should be converted according to data bus width. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * return The data read out. + * + * note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base) +{ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + return base->flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; +#else + return base->flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; +#endif +} + +/*! + * brief Configures the FLEXIO MCULCD to single beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data writing. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint32_t timerCompare; + uint32_t timerControl; + + /* Enable the TX Shifter output. */ + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1, + * so the TIMCMP[15:8] is 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = (1UL << 8U) | timerCompare; + + /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus. + Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the + issue. */ + timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); + + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; + timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput); + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; +} + +/*! + * brief Clear the FLEXIO MCULCD single beats write mode configuration. + * + * Clear the write configuration set by ref FLEXIO_MCULCD_SetSingleBeatWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + /* Stop the TX shifter. */ + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = 0U; + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = 0U; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->txShifterStartIndex); +} + +/*! + * brief Configures the FLEXIO MCULCD to single beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data reading. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint8_t timerPin; + uint32_t timerCompare; + flexio_pin_polarity_t timerPinPolarity; + + /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */ + if (kFLEXIO_MCULCD_8080 == base->busType) + { + timerPin = base->RDPinIndex; + timerPinPolarity = kFLEXIO_PinActiveLow; + } + else + { + timerPin = base->ENWRPinIndex; + timerPinPolarity = kFLEXIO_PinActiveHigh; + } + + /* Enable the RX Shifter input. */ + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U); + + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + + /* Use RX shifter flag as the inverted timer trigger. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1, + * so the TIMCMP[15:8] is 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = (1UL << 8U) | timerCompare; + + base->flexioBase->TIMCTL[base->timerIndex] |= + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD single beats read mode configuration. + * + * Clear the read configuration set by ref FLEXIO_MCULCD_SetSingleBeatReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + /* Stop the RX shifter. */ + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = 0U; + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = 0U; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->rxShifterEndIndex); +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data writing. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint32_t timerCompare; + uint32_t timerControl; + uint8_t beats; + uint8_t i; + + /* Enable the TX Shifter output. */ + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + + for (i = base->txShifterStartIndex + 1U; i <= base->txShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[i] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(0) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + } + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + beats = 4U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U); +#else + beats = 2U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U); +#endif + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2UL - 1UL) << 8U) | timerCompare; + + /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus. + Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the + issue. */ + timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); + + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; + timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput); + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by ref FLEXIO_MCULCD_SetMultBeatsWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) +{ + uint8_t i; + uint32_t statusFlags = 0U; + + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + + /* Stop the TX shifter. */ + for (i = base->txShifterStartIndex; i <= base->txShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = 0U; + base->flexioBase->SHIFTCTL[i] = 0U; + statusFlags |= (1UL << i); + } + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = statusFlags; +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data reading. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint8_t timerPin; + uint8_t beats; + uint8_t i; + uint32_t timerCompare; + flexio_pin_polarity_t timerPinPolarity; + + /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */ + if (kFLEXIO_MCULCD_8080 == base->busType) + { + timerPin = base->RDPinIndex; + timerPinPolarity = kFLEXIO_PinActiveLow; + } + else + { + timerPin = base->ENWRPinIndex; + timerPinPolarity = kFLEXIO_PinActiveHigh; + } + + /* Enable the RX Shifter input. */ + for (i = base->rxShifterStartIndex; i < base->rxShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[i] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + } + + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U); + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + beats = 4U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U); +#else + beats = 2U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U); +#endif + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2UL - 1UL) << 8U) | timerCompare; + + /* Use RX shifter flag as the inverted timer trigger. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + base->flexioBase->TIMCTL[base->timerIndex] |= + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by ref FLEXIO_MCULCD_SetMultBeatsReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) +{ + uint8_t i; + uint32_t statusFlags = 0U; + + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + /* Stop the RX shifter. */ + for (i = base->rxShifterStartIndex; i <= base->rxShifterEndIndex; i++) + { + base->flexioBase->SHIFTCTL[i] = 0U; + base->flexioBase->SHIFTCFG[i] = 0U; + statusFlags |= (1UL << i); + } + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = statusFlags; +} + +/*! + * brief Wait for transmit data send out finished. + * + * Currently there is no effective method to wait for the data send out + * from the shiter, so here use a while loop to wait. + * + * note This is an internal used function. + */ +void FLEXIO_MCULCD_WaitTransmitComplete(void) +{ + uint32_t i = FLEXIO_MCULCD_WAIT_COMPLETE_TIME; + + while (0U != (i--)) + { + __NOP(); + } +} + +/*! + * brief Send command in blocking way. + * + * This function sends the command and returns when the command has been sent + * out. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param command The command to send. + */ +void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command) +{ + FLEXIO_Type *flexioBase = base->flexioBase; + + /* De-assert the RS pin. */ + base->setRSPin(false); + + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + + /* Write command to shifter buffer. */ + flexioBase->SHIFTBUF[base->txShifterStartIndex] = command; + + /* Wait for command send out. */ + while (0U == ((1UL << base->timerIndex) & FLEXIO_GetTimerStatusFlags(flexioBase))) + { + } + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } +} + +/*! + * brief Send data array in blocking way. + * + * This function sends the data array and returns when the data sent out. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param data The data array to send. + * param size How many bytes to write. + */ +void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, const void *data, size_t size) +{ + assert(size > 0U); + + uint32_t i; +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + const uint8_t *data8Bit; +#else + const uint16_t *data16Bit; +#endif + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + +/* If data bus width is 8. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data8Bit = (const uint8_t *)data; + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = data8Bit[i]; + + /* Wait for the data send out. */ + while (0U == ((1UL << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1UL << base->timerIndex; + } +#else + data16Bit = (const uint16_t *)data; + size /= 2U; + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = data16Bit[i]; + + /* Wait for the data send out. */ + while (0U == ((1UL << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1UL << base->timerIndex; + } +#endif + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); +} + +/*! + * brief Read data into array in blocking way. + * + * This function reads the data into array and returns when the data read + * finished. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param data The array to save the data. + * param size How many bytes to read. + */ +void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size) +{ + assert(size > 0U); + + uint32_t i; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + uint8_t *data8Bit = (uint8_t *)data; +#else + uint16_t *data16Bit = (uint16_t *)data; +#endif + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Enable the timer and RX shifter. */ + FLEXIO_MCULCD_SetSingleBeatReadConfig(base); + +/* If data bus width is 8. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + for (i = 0; i < (size - 1U); i++) + { + /* Wait for shifter buffer full. */ + while (0U == ((1UL << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; + } +#else + /* Data bus width is 16. */ + size /= 2U; + + for (i = 0; i < (size - 1U); i++) + { + /* Wait for shifter buffer full. */ + while (0U == ((1UL << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; + } +#endif + + /* Wait for shifter buffer full. */ + while (0U == ((1UL << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + /* Stop the timer and disable the RX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); + +/* Read out the last data. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; +#else + data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; +#endif +} + +/*! + * brief Send the same value many times in blocking way. + * + * This function sends the same value many times. It could be used to clear the + * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of + * p sameValue for p size times. If the data bus is 16, this function will send + * LSB 16 bits of p sameValue for p size / 2 times. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param sameValue The same value to send. + * param size How many bytes to send. + */ +void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size) +{ + assert(size > 0U); + + uint32_t i; + FLEXIO_Type *flexioBase = base->flexioBase; + +#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + size /= 2U; +#endif + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = sameValue; + + /* Wait for the data send out. */ + while (0U == ((1UL << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1UL << base->timerIndex; + } + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); +} + +/*! + * brief Performs a polling transfer. + * + * note The API does not return until the transfer finished. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param xfer pointer to flexio_mculcd_transfer_t structure. + */ +void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer) +{ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + if (xfer->dataSize > 0U) + { + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + FLEXIO_MCULCD_ReadDataArrayBlocking(base, (uint8_t *)(xfer->dataAddrOrSameValue), xfer->dataSize); + } + else if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + FLEXIO_MCULCD_WriteDataArrayBlocking(base, (uint8_t *)(xfer->dataAddrOrSameValue), xfer->dataSize); + } + else + { + FLEXIO_MCULCD_WriteSameValueBlocking(base, xfer->dataAddrOrSameValue, xfer->dataSize); + } + } + + FLEXIO_MCULCD_StopTransfer(base); +} + +/*! + * brief Initializes the FlexIO MCULCD handle, which is used in transactional + * functions. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base->flexioBase)]); + + /* Save the context in global variables to support the double weak mechanism. + */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_MCULCD_TransferHandleIRQ); +} + +/*! + * brief Transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which + * returns right away. When all data is sent out/received, the callback + * function is called. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer. + */ +status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + /* If previous transfer is in progress. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Set the state in handle. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateReadArray; + } + else if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray; + } + else + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteSameValue; + } + + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + /* If transfer count is 0 (only to send command), return directly. */ + if (0U == xfer->dataSize) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* De-assert the nCS. */ + FLEXIO_MCULCD_StopTransfer(base); + + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + handle->dataCount = xfer->dataSize; +#else + handle->dataCount = xfer->dataSize / 2U; +#endif + + handle->remainingCount = handle->dataCount; + + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Enable interrupt. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } + FLEXIO_MCULCD_SetSingleBeatReadConfig(base); + FLEXIO_MCULCD_EnableInterrupts(base, (uint32_t)kFLEXIO_MCULCD_RxFullInterruptEnable); + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + FLEXIO_MCULCD_EnableInterrupts(base, (uint32_t)kFLEXIO_MCULCD_TxEmptyInterruptEnable); + } + } + + return kStatus_Success; +} + +/*! + * brief Aborts the data transfer, which used IRQ. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle) +{ + /* If no transfer in process, return directly. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == handle->state) + { + return; + } + + /* Disable the interrupt. */ + FLEXIO_MCULCD_DisableInterrupts( + base, (uint32_t)kFLEXIO_MCULCD_RxFullInterruptEnable | (uint32_t)kFLEXIO_MCULCD_TxEmptyInterruptEnable); + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == handle->state) + { + /* Stop the timer and disable the RX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); + } + else + { + /* Stop the timer and disable the TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + } + + /* Clean the flags. */ + FLEXIO_MCULCD_ClearStatusFlags(base, (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag | (uint32_t)kFLEXIO_MCULCD_RxFullFlag); + + /* De-assert the nCS. */ + FLEXIO_MCULCD_StopTransfer(base); + + handle->dataCount = 0; + handle->remainingCount = 0; + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; +} + +/*! + * brief Gets the data transfer status which used IRQ. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param count How many bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count) +{ + assert(NULL != count); + + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == handle->state) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->dataCount - handle->remainingCount; + +#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + *count *= 2U; +#endif + + return kStatus_Success; +} + +/*! + * brief FlexIO MCULCD IRQ handler function. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle) +{ + FLEXIO_MCULCD_Type *flexioLcdMcuBase = (FLEXIO_MCULCD_Type *)base; + flexio_mculcd_handle_t *flexioLcdMcuHandle = (flexio_mculcd_handle_t *)handle; + uint32_t statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + uint32_t data; + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == flexioLcdMcuHandle->state) + { + /* Handle the reading process. */ + while ((0U != ((uint32_t)kFLEXIO_MCULCD_RxFullFlag & statusFlags)) && (flexioLcdMcuHandle->remainingCount > 0U)) + { + if (1U == flexioLcdMcuHandle->remainingCount) + { + /* If this is the last data, stop the RX shifter and timer. */ + FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, (uint32_t)kFLEXIO_MCULCD_RxFullInterruptEnable); + FLEXIO_MCULCD_ClearSingleBeatReadConfig(flexioLcdMcuBase); + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + } + + /* Read out the data. */ + data = FLEXIO_MCULCD_ReadData(flexioLcdMcuBase); + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint8_t)data; + flexioLcdMcuHandle->dataAddrOrSameValue++; +#else + *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint16_t)data; + flexioLcdMcuHandle->dataAddrOrSameValue += 2U; +#endif + + flexioLcdMcuHandle->remainingCount--; + + /* Transfer finished, call the callback. */ + if (0U == flexioLcdMcuHandle->remainingCount) + { + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, + kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData); + } + } + + /* Is the shifter buffer ready to send the next data? */ + statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + } + } + else + { + /* Handle the writing process. */ + while ((0U != ((uint32_t)kFLEXIO_MCULCD_TxEmptyFlag & statusFlags)) && + (flexioLcdMcuHandle->remainingCount > 0U)) + { + /* Send the data. */ + if ((uint32_t)kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state) + { + data = flexioLcdMcuHandle->dataAddrOrSameValue; + } + else + { +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data = *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue); + flexioLcdMcuHandle->dataAddrOrSameValue++; +#else + data = *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue); + flexioLcdMcuHandle->dataAddrOrSameValue += 2U; +#endif + } + + /* If this is the last data to send, delay to wait for the data shift out. */ + if (1U == flexioLcdMcuHandle->remainingCount) + { + FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, (uint32_t)kFLEXIO_MCULCD_TxEmptyInterruptEnable); + + /* Write the last data. */ + FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data); + + /* Wait for the last data send finished. */ + FLEXIO_MCULCD_WaitTransmitComplete(); + flexioLcdMcuHandle->remainingCount = 0; + + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(flexioLcdMcuBase); + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, + kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData); + } + } + else + { + FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data); + flexioLcdMcuHandle->remainingCount--; + } + /* Is the shifter buffer ready to send the next data? */ + statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + } + } +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd.h new file mode 100644 index 0000000000..d998b1d39f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd.h @@ -0,0 +1,686 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_MCULCD_H_ +#define FSL_FLEXIO_MCULCD_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO MCULCD driver version. */ +#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +#ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME +/*! + * @brief The delay time to wait for FLEXIO transmit complete. + * + * Currently there is no method to detect whether the data has been + * sent out from the shifter, so the driver use a software delay for this. When + * the data is written to shifter buffer, the driver call the delay + * function to wait for the data shift out. + * If this value is too small, then the last few bytes might be lost when writing + * data using interrupt method or DMA method. + */ +#define FLEXIO_MCULCD_WAIT_COMPLETE_TIME 512 +#endif + +#ifndef FLEXIO_MCULCD_DATA_BUS_WIDTH +/*! + * @brief The data bus width, must be 8 or 16. + */ +#define FLEXIO_MCULCD_DATA_BUS_WIDTH 16UL +#endif + +#if (16UL != FLEXIO_MCULCD_DATA_BUS_WIDTH) && (8UL != FLEXIO_MCULCD_DATA_BUS_WIDTH) +#error Only support data bus 8-bit or 16-bit +#endif + +/*! @brief FlexIO LCD transfer status */ +enum +{ + kStatus_FLEXIO_MCULCD_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 0), /*!< FlexIO LCD is idle. */ + kStatus_FLEXIO_MCULCD_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 1), /*!< FlexIO LCD is busy */ + kStatus_FLEXIO_MCULCD_Error = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 2), /*!< FlexIO LCD error occurred */ +}; + +/*! @brief Define FlexIO MCULCD pixel format. */ +typedef enum _flexio_mculcd_pixel_format +{ + kFLEXIO_MCULCD_RGB565 = 0, /*!< RGB565, 16-bit. */ + kFLEXIO_MCULCD_BGR565, /*!< BGR565, 16-bit. */ + kFLEXIO_MCULCD_RGB888, /*!< RGB888, 24-bit. */ + kFLEXIO_MCULCD_BGR888, /*!< BGR888, 24-bit. */ +} flexio_mculcd_pixel_format_t; + +/*! @brief Define FlexIO MCULCD bus type. */ +typedef enum _flexio_mculcd_bus +{ + kFLEXIO_MCULCD_8080, /*!< Using Intel 8080 bus. */ + kFLEXIO_MCULCD_6800, /*!< Using Motorola 6800 bus. */ +} flexio_mculcd_bus_t; + +/*! @brief Define FlexIO MCULCD interrupt mask. */ +enum _flexio_mculcd_interrupt_enable +{ + kFLEXIO_MCULCD_TxEmptyInterruptEnable = (1U << 0U), /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_MCULCD_RxFullInterruptEnable = (1U << 1U), /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO MCULCD status mask. */ +enum _flexio_mculcd_status_flags +{ + kFLEXIO_MCULCD_TxEmptyFlag = (1U << 0U), /*!< Transmit buffer empty flag. */ + kFLEXIO_MCULCD_RxFullFlag = (1U << 1U), /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO MCULCD DMA mask. */ +enum _flexio_mculcd_dma_enable +{ + kFLEXIO_MCULCD_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_MCULCD_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ +}; + +/*! @brief Function to set or clear the CS and RS pin. */ +typedef void (*flexio_mculcd_pin_func_t)(bool set); + +/*! @brief Define FlexIO MCULCD access structure typedef. */ +typedef struct _flexio_mculcd_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + flexio_mculcd_bus_t busType; /*!< The bus type, 8080 or 6800. */ + uint8_t dataPinStartIndex; /*!< Start index of the data pin, the FlexIO pin dataPinStartIndex + to (dataPinStartIndex + FLEXIO_MCULCD_DATA_BUS_WIDTH -1) + will be used for data transfer. Only support data bus width 8 and 16. */ + uint8_t ENWRPinIndex; /*!< Pin select for WR(8080 mode), EN(6800 mode). */ + uint8_t RDPinIndex; /*!< Pin select for RD(8080 mode), not used in 6800 mode. */ + uint8_t txShifterStartIndex; /*!< Start index of shifters used for data write, it must be 0 or 4. */ + uint8_t txShifterEndIndex; /*!< End index of shifters used for data write. */ + uint8_t rxShifterStartIndex; /*!< Start index of shifters used for data read. */ + uint8_t rxShifterEndIndex; /*!< End index of shifters used for data read, it must be 3 or 7. */ + uint8_t timerIndex; /*!< Timer index used in FlexIO MCULCD. */ + flexio_mculcd_pin_func_t setCSPin; /*!< Function to set or clear the CS pin. */ + flexio_mculcd_pin_func_t setRSPin; /*!< Function to set or clear the RS pin. */ + flexio_mculcd_pin_func_t setRDWRPin; /*!< Function to set or clear the RD/WR pin, only used in 6800 mode. */ +} FLEXIO_MCULCD_Type; + +/*! @brief Define FlexIO MCULCD configuration structure. */ +typedef struct _flexio_mculcd_config +{ + bool enable; /*!< Enable/disable FlexIO MCULCD after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in bit-per-second for all data lines combined. */ +} flexio_mculcd_config_t; + +/*! @brief Transfer mode.*/ +typedef enum _flexio_mculcd_transfer_mode +{ + kFLEXIO_MCULCD_ReadArray, /*!< Read data into an array. */ + kFLEXIO_MCULCD_WriteArray, /*!< Write data from an array. */ + kFLEXIO_MCULCD_WriteSameValue, /*!< Write the same value many times. */ +} flexio_mculcd_transfer_mode_t; + +/*! @brief Define FlexIO MCULCD transfer structure. */ +typedef struct _flexio_mculcd_transfer +{ + uint32_t command; /*!< Command to send. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataSize; /*!< How many bytes to transfer. */ + flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */ + bool dataOnly; /*!< Send data only when tx without the command. */ +} flexio_mculcd_transfer_t; + +/*! @brief typedef for flexio_mculcd_handle_t in advance. */ +typedef struct _flexio_mculcd_handle flexio_mculcd_handle_t; + +/*! @brief FlexIO MCULCD callback for finished transfer. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO MCULCD handle structure. */ +struct _flexio_mculcd_handle +{ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataCount; /*!< Total count to be transferred. */ + volatile size_t remainingCount; /*!< Remaining count to transfer. */ + volatile uint32_t state; /*!< FlexIO MCULCD internal state. */ + flexio_mculcd_transfer_callback_t completionCallback; /*!< FlexIO MCULCD transfer completed callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO MCULCD Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the + * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD + * configuration. + * The configuration structure can be filled by the user, or be set with default + * values + * by the @ref FLEXIO_MCULCD_GetDefaultConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param config Pointer to the flexio_mculcd_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Initialization success. + * @retval kStatus_InvalidArgument Initialization failed because of invalid + * argument. + */ +status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FLEXIO_MCULCD timer and shifter configuration. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + */ +void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO MCULCD. + * + * The default configuration value is: + * @code + * config->enable = true; + * config->enableInDoze = false; + * config->enableInDebug = true; + * config->enableFastAccess = true; + * config->baudRate_Bps = 96000000U; + * @endcode + * @param config Pointer to the flexio_mculcd_config_t structure. + */ +void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config); + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO MCULCD status flags. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return status flag; OR'ed value or the @ref _flexio_mculcd_status_flags. + * + * @note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clears FlexIO MCULCD status flags. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Status to clear, it is the OR'ed value of @ref + * _flexio_mculcd_status_flags. + * + * @note Don't use this function with DMA APIs. + */ +void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO MCULCD interrupt. + * + * This function enables the FlexIO MCULCD interrupt. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Interrupts to enable, it is the OR'ed value of @ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO MCULCD interrupt. + * + * This function disables the FlexIO MCULCD interrupt. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Interrupts to disable, it is the OR'ed value of @ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO MCULCD transmit DMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_MCULCD_EnableTxDMA(FLEXIO_MCULCD_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1UL << base->txShifterStartIndex), enable); +} + +/*! + * @brief Enables/disables the FlexIO MCULCD receive DMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_MCULCD_EnableRxDMA(FLEXIO_MCULCD_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1UL << base->rxShifterEndIndex), enable); +} + +/*! + * @brief Gets the FlexIO MCULCD transmit data register address. + * + * This function returns the MCULCD data register address, which is mainly used + * by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return FlexIO MCULCD transmit data register address. + */ +static inline uint32_t FLEXIO_MCULCD_GetTxDataRegisterAddress(FLEXIO_MCULCD_Type *base) +{ + return (uint32_t) & (base->flexioBase->SHIFTBUF[base->txShifterStartIndex]); +} + +/*! + * @brief Gets the FlexIO MCULCD receive data register address. + * + * This function returns the MCULCD data register address, which is mainly used + * by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return FlexIO MCULCD receive data register address. + */ +static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type *base) +{ + return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]); +} + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Set desired baud rate. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined. + * @param srcClock_Hz FLEXIO clock frequency in Hz. + * @retval kStatus_Success Set successfully. + * @retval kStatus_InvalidArgument Could not set the baud rate. + */ +status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by @ref FLEXIO_MCULCD_SetSingleBeatWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by @ref FLEXIO_MCULCD_SetSingleBeatReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by FLEXIO_MCULCD_ClearMultBeatsWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by FLEXIO_MCULCD_SetMultBeatsWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by FLEXIO_MCULCD_ClearMultBeatsReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by FLEXIO_MCULCD_SetMultBeatsReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Enables/disables the FlexIO MCULCD module operation. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_MCULCD_Enable(FLEXIO_MCULCD_Type *base, bool enable) +{ + if (enable) + { + FLEXIO_Enable(base->flexioBase, enable); + } +} + +/*! + * @brief Read data from the FLEXIO MCULCD RX shifter buffer. + * + * Read data from the RX shift buffer directly, it does no check whether the + * buffer is empty or not. + * + * If the data bus width is 8-bit: + * @code + * uint8_t value; + * value = (uint8_t)FLEXIO_MCULCD_ReadData(base); + * @endcode + * + * If the data bus width is 16-bit: + * @code + * uint16_t value; + * value = (uint16_t)FLEXIO_MCULCD_ReadData(base); + * @endcode + * + * @note This function returns the RX shifter buffer value (32-bit) directly. + * The return value should be converted according to data bus width. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return The data read out. + * + * @note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Write data into the FLEXIO MCULCD TX shifter buffer. + * + * Write data into the TX shift buffer directly, it does no check whether the + * buffer is full or not. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The data to write. + * + * @note Don't use this function with DMA APIs. + */ +static inline void FLEXIO_MCULCD_WriteData(FLEXIO_MCULCD_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUF[base->txShifterStartIndex] = data; +} + +/*! + * @brief Assert the nCS to start transfer. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + */ +static inline void FLEXIO_MCULCD_StartTransfer(FLEXIO_MCULCD_Type *base) +{ + base->setCSPin(false); +} + +/*! + * @brief De-assert the nCS to stop transfer. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + */ +static inline void FLEXIO_MCULCD_StopTransfer(FLEXIO_MCULCD_Type *base) +{ + base->setCSPin(true); +} + +/*! + * @brief Wait for transmit data send out finished. + * + * Currently there is no effective method to wait for the data send out + * from the shiter, so here use a while loop to wait. + * + * @note This is an internal used function. + */ +void FLEXIO_MCULCD_WaitTransmitComplete(void); + +/*! + * @brief Send command in blocking way. + * + * This function sends the command and returns when the command has been sent + * out. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param command The command to send. + */ +void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command); + +/*! + * @brief Send data array in blocking way. + * + * This function sends the data array and returns when the data sent out. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The data array to send. + * @param size How many bytes to write. + */ +void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, const void *data, size_t size); + +/*! + * @brief Read data into array in blocking way. + * + * This function reads the data into array and returns when the data read + * finished. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The array to save the data. + * @param size How many bytes to read. + */ +void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size); + +/*! + * @brief Send the same value many times in blocking way. + * + * This function sends the same value many times. It could be used to clear the + * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of + * @p sameValue for @p size times. If the data bus is 16, this function will send + * LSB 16 bits of @p sameValue for @p size / 2 times. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param sameValue The same value to send. + * @param size How many bytes to send. + */ +void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size); + +/*! + * @brief Performs a polling transfer. + * + * @note The API does not return until the transfer finished. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param xfer pointer to flexio_mculcd_transfer_t structure. + */ +void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer); +/*@}*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO MCULCD handle, which is used in transactional + * functions. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which + * returns right away. When all data is sent out/received, the callback + * function is called. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer. + */ +status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts the data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param count How many bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO MCULCD IRQ handler function. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*FSL_FLEXIO_MCULCD_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_edma.c new file mode 100644 index 0000000000..0c52c4e8c0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_edma.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_edma" +#endif + +#define EDMA_MAX_MAJOR_COUNT (DMA_CITER_ELINKNO_CITER_MASK >> DMA_CITER_ELINKNO_CITER_SHIFT) + +enum +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. + */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief EDMA callback function for FLEXIO MCULCD TX. + * + * For details, see @ref edma_callback. + */ +static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds); + +/*! + * @brief EDMA callback function for FLEXIO MCULCD RX. + * + * For details, see @ref edma_callback. + */ +static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds); + +/*! + * @brief Set EDMA config for FLEXIO MCULCD transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + */ +static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle); + +/*! + * @brief Convert the FlexIO shifter number to eDMA modulo. + * + * @param shifterNum The FlexIO shifter number. + * @param modulo The modulo number. + * @retval Get the modulo successfully. + * @retval Could not get the modulo for the shifter number. + */ +static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param; + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base; + + if (transferDone) + { + if (flexioLcdMcuHandle->remainingCount >= flexioLcdMcuHandle->minorLoopBytes) + { + FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle); + EDMA_StartTransfer(flexioLcdMcuHandle->txDmaHandle); + } + else + { + FLEXIO_MCULCD_EnableTxDMA(flexioLcdMcuBase, false); + + /* Now the data are in shifter, wait for the data send out from the shifter. */ + FLEXIO_MCULCD_WaitTransmitComplete(); + + /* Disable the TX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase); + + /* Send the remaining data. */ + if (0U != flexioLcdMcuHandle->remainingCount) + { + if ((uint32_t)kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state) + { + FLEXIO_MCULCD_WriteSameValueBlocking(flexioLcdMcuBase, flexioLcdMcuHandle->dataAddrOrSameValue, + flexioLcdMcuHandle->remainingCount); + } + else + { + FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, + (uint8_t *)flexioLcdMcuHandle->dataAddrOrSameValue, + flexioLcdMcuHandle->remainingCount); + } + } + + /* De-assert nCS. */ + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + + /* Change the state. */ + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + flexioLcdMcuHandle->dataCount = 0; + flexioLcdMcuHandle->remainingCount = 0; + + /* Callback to inform upper layer. */ + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle, + flexioLcdMcuHandle->userData); + } + } + } +} + +static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + uint32_t i; + uint32_t rxBufAddr; + flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param; + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base; + FLEXIO_Type *flexioBase = flexioLcdMcuBase->flexioBase; + + if (transferDone) + { + if (flexioLcdMcuHandle->remainingCount >= (2U * flexioLcdMcuHandle->minorLoopBytes)) + { + FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle); + EDMA_StartTransfer(flexioLcdMcuHandle->rxDmaHandle); + } + else + { + FLEXIO_MCULCD_EnableRxDMA(flexioLcdMcuBase, false); + + /* Wait the data saved to the shifter buffer. */ + while (0U == ((1UL << flexioLcdMcuBase->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + /* Disable the RX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsReadConfig(flexioLcdMcuBase); + + rxBufAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(flexioLcdMcuBase); + +/* Read out the data. */ +#if (defined(__CORTEX_M) && (__CORTEX_M == 0)) + /* Cortex M0 and M0+ only support aligned access. */ + for (i = 0; i < flexioLcdMcuHandle->rxShifterNum * 4; i++) + { + ((uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint8_t *)rxBufAddr)[i]; + } +#else + for (i = 0; i < flexioLcdMcuHandle->rxShifterNum; i++) + { + ((uint32_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint32_t *)rxBufAddr)[i]; + } +#endif + flexioLcdMcuHandle->remainingCount -= flexioLcdMcuHandle->minorLoopBytes; + + if (0U != flexioLcdMcuHandle->remainingCount) + { + FLEXIO_MCULCD_ReadDataArrayBlocking( + flexioLcdMcuBase, + (uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue + flexioLcdMcuHandle->minorLoopBytes), + flexioLcdMcuHandle->remainingCount); + } + + /* De-assert nCS. */ + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + + /* Change the state. */ + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + flexioLcdMcuHandle->dataCount = 0; + flexioLcdMcuHandle->remainingCount = 0; + + /* Callback to inform upper layer. */ + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle, + flexioLcdMcuHandle->userData); + } + } + } +} + +static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle) +{ + edma_transfer_config_t xferConfig = {0}; + edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes; + int16_t offset; + uint32_t majorLoopCounts; + uint32_t transferCount; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + transferSize = kEDMA_TransferSize1Bytes; + offset = 1; +#else + transferSize = kEDMA_TransferSize2Bytes; + offset = 2; +#endif + + majorLoopCounts = handle->remainingCount / handle->minorLoopBytes; + + /* For reading, the last minor loop data is not tranfered by DMA. */ + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == handle->state) + { + majorLoopCounts--; + } + + if (majorLoopCounts > EDMA_MAX_MAJOR_COUNT) + { + majorLoopCounts = EDMA_MAX_MAJOR_COUNT; + } + + transferCount = majorLoopCounts * handle->minorLoopBytes; + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == handle->state) + { + xferConfig.srcAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(base); + xferConfig.destAddr = handle->dataAddrOrSameValue; + xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destTransferSize = transferSize; + xferConfig.srcOffset = 4; + xferConfig.destOffset = offset; + xferConfig.minorLoopBytes = handle->minorLoopBytes; + xferConfig.majorLoopCounts = majorLoopCounts; + handle->remainingCount -= transferCount; + handle->dataAddrOrSameValue += transferCount; + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, handle->rxEdmaModulo, + kEDMA_ModuloDisable); + } + else + { + if ((uint32_t)kFLEXIO_MCULCD_StateWriteArray == handle->state) + { + xferConfig.srcAddr = handle->dataAddrOrSameValue; + xferConfig.srcOffset = offset; + handle->dataAddrOrSameValue += transferCount; + } + else + { + xferConfig.srcAddr = (uint32_t)(&(handle->dataAddrOrSameValue)); + xferConfig.srcOffset = 0; + } + xferConfig.destAddr = FLEXIO_MCULCD_GetTxDataRegisterAddress(base); + xferConfig.srcTransferSize = transferSize; + xferConfig.destTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destOffset = 4; + xferConfig.minorLoopBytes = handle->minorLoopBytes; + xferConfig.majorLoopCounts = majorLoopCounts; + handle->remainingCount -= transferCount; + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, kEDMA_ModuloDisable, + handle->txEdmaModulo); + } +} + +static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo) +{ + bool ret = true; + + switch (shifterNum) + { + case 1U: + *modulo = kEDMA_Modulo4bytes; + break; + case 2U: + *modulo = kEDMA_Modulo8bytes; + break; + case 4U: + *modulo = kEDMA_Modulo16bytes; + break; + case 8U: + *modulo = kEDMA_Modulo32bytes; + break; + default: + ret = false; + break; + } + + return ret; +} + +/*! + * brief Initializes the FLEXO MCULCD master eDMA handle. + * + * This function initializes the FLEXO MCULCD master eDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_MCULCD_Type structure. + * param handle Pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * param callback MCULCD transfer complete callback, NULL means no callback. + * param userData callback function parameter. + * param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX, + * the DMA request source of this handle should be the first of TX shifters. + * param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX, + * the DMA request source of this handle should be the last of RX shifters. + * retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txDmaHandle, + edma_handle_t *rxDmaHandle) +{ + assert(NULL != handle); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Initialize the state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + handle->base = base; + handle->txShifterNum = base->txShifterEndIndex - base->txShifterStartIndex + 1U; + handle->rxShifterNum = base->rxShifterEndIndex - base->rxShifterStartIndex + 1U; + + if (NULL != rxDmaHandle) + { + if (!FLEXIO_MCULCD_GetEDMAModulo(handle->rxShifterNum, &handle->rxEdmaModulo)) + { + return kStatus_InvalidArgument; + } + + handle->rxDmaHandle = rxDmaHandle; + EDMA_SetCallback(rxDmaHandle, FLEXIO_MCULCD_RxEDMACallback, handle); + } + + if (NULL != txDmaHandle) + { + if (!FLEXIO_MCULCD_GetEDMAModulo(handle->txShifterNum, &handle->txEdmaModulo)) + { + return kStatus_InvalidArgument; + } + + handle->txDmaHandle = txDmaHandle; + EDMA_SetCallback(txDmaHandle, FLEXIO_MCULCD_TxEDMACallback, handle); + } + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO MCULCD transfer using eDMA. + * + * This function returns immediately after transfer initiates. To check whether + * the transfer is completed, user could: + * 1. Use the transfer completed callback; + * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * param xfer Pointer to FlexIO MCULCD transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + + /* + * The data transfer mechanism: + * + * Read: + * Assume the data length is Lr = (n1 * minorLoopBytes + n2), where + * n2 < minorLoopBytes. + * If (n1 <= 1), then all data are sent using blocking method. + * If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read + * using DMA, the left (minorLoopBytes + n2) are read using blocking method. + * + * Write: + * Assume the data length is Lw = (n1 * minorLoopBytes + n2), where + * n2 < minorLoopBytes. + * If (n1 = 0), then all data are sent using blocking method. + * If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent + * using DMA, the left n2 are sent using blocking method. + */ + + /* Check if the device is busy. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Set the state in handle. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateReadArray; + handle->minorLoopBytes = handle->rxShifterNum * 4UL; + } + else + { + handle->minorLoopBytes = handle->txShifterNum * 4UL; + + if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray; + } + else + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteSameValue; + } + } + + /* + * For TX, if data is less than one minor loop, then use polling method. + * For RX, if data is less than two minor loop, then use polling method. + */ + if ((xfer->dataSize < handle->minorLoopBytes) || + ((kFLEXIO_MCULCD_ReadArray == xfer->mode) && (xfer->dataSize < 2U * (handle->minorLoopBytes)))) + { + FLEXIO_MCULCD_TransferBlocking(base, xfer); + + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Callback to inform upper layer. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { + handle->dataCount = xfer->dataSize; + handle->remainingCount = xfer->dataSize; + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Setup DMA to transfer data. */ + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + /* Setup the DMA configuration. */ + FLEXIO_MCULCD_EDMAConfig(base, handle); + + /* Start the transfer. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } + FLEXIO_MCULCD_SetMultiBeatsReadConfig(base); + FLEXIO_MCULCD_EnableRxDMA(base, true); + EDMA_StartTransfer(handle->rxDmaHandle); + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base); + FLEXIO_MCULCD_EnableTxDMA(base, true); + EDMA_StartTransfer(handle->txDmaHandle); + } + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO MCULCD transfer using eDMA. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD eDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable dma. */ + if (NULL != handle->txDmaHandle) + { + EDMA_AbortTransfer(handle->txDmaHandle); + } + if (NULL != handle->rxDmaHandle) + { + EDMA_AbortTransfer(handle->rxDmaHandle); + } + + /* Disable DMA enable bit. */ + FLEXIO_MCULCD_EnableTxDMA(handle->base, false); + FLEXIO_MCULCD_EnableRxDMA(handle->base, false); + + /* Set the handle state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + handle->dataCount = 0; +} + +/*! + * brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD eDMA handle pointer. + * param count Number of count transferred so far by the eDMA transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + size_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + uint32_t state = handle->state; + + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == state) + { + return kStatus_NoTransferInProgress; + } + else + { + *count = handle->dataCount - handle->remainingCount; + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == state) + { + *count -= handle->minorLoopBytes * + EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + } + else + { + *count -= handle->minorLoopBytes * + EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel); + } + } + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_edma.h new file mode 100644 index 0000000000..eb2a4ce42e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_edma.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_MCULCD_EDMA_H_ +#define FSL_FLEXIO_MCULCD_EDMA_H_ + +#include "fsl_edma.h" +#include "fsl_flexio_mculcd.h" + +/*! + * @addtogroup flexio_edma_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*@{*/ +/*! @brief FlexIO MCULCD EDMA driver version. */ +#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */ +typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t; + +/*! @brief FlexIO MCULCD master callback for transfer complete. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_edma_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO MCULCD eDMA transfer handle, users should not touch the + * content of the handle.*/ +struct _flexio_mculcd_edma_handle +{ + FLEXIO_MCULCD_Type *base; /*!< Pointer to the FLEXIO_MCULCD_Type. */ + uint8_t txShifterNum; /*!< Number of shifters used for TX. */ + uint8_t rxShifterNum; /*!< Number of shifters used for RX. */ + uint32_t minorLoopBytes; /*!< eDMA transfer minor loop bytes. */ + edma_modulo_t txEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */ + edma_modulo_t rxEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or + reading array, this is the address of the + data array. */ + size_t dataCount; /*!< Total count to be transferred. */ + volatile size_t remainingCount; /*!< Remaining count still not transfered. */ + volatile uint32_t state; /*!< FlexIO MCULCD driver internal state. */ + edma_handle_t *txDmaHandle; /*!< DMA handle for MCULCD TX */ + edma_handle_t *rxDmaHandle; /*!< DMA handle for MCULCD RX */ + flexio_mculcd_edma_transfer_callback_t completionCallback; /*!< Callback for MCULCD DMA transfer */ + void *userData; /*!< User Data for MCULCD DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXO MCULCD master eDMA handle. + * + * This function initializes the FLEXO MCULCD master eDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_MCULCD_Type structure. + * @param handle Pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * @param callback MCULCD transfer complete callback, NULL means no callback. + * @param userData callback function parameter. + * @param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX, + * the DMA request source of this handle should be the first of TX shifters. + * @param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX, + * the DMA request source of this handle should be the last of RX shifters. + * @retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txDmaHandle, + edma_handle_t *rxDmaHandle); + +/*! + * @brief Performs a non-blocking FlexIO MCULCD transfer using eDMA. + * + * This function returns immediately after transfer initiates. To check whether + * the transfer is completed, user could: + * 1. Use the transfer completed callback; + * 2. Polling function FLEXIO_MCULCD_GetTransferCountEDMA + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * @param xfer Pointer to FlexIO MCULCD transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO MCULCD transfer using eDMA. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD eDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD eDMA handle pointer. + * @param count Number of count transferred so far by the eDMA transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_FLEXIO_MCULCD_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_smartdma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_smartdma.c new file mode 100644 index 0000000000..3ca5315052 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_smartdma.c @@ -0,0 +1,407 @@ +/* + * Copyright 2019-2021,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd_smartdma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_smartdma" +#endif + +#define FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER 0U +#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER 7U +#define FLEXIO_MCULCD_SMARTDMA_TX_SHIFTER_NUM \ + (FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER - FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER + 1) + +enum _MCULCD_transfer_state +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. + */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the TX chunk size. + * + * The SMARTDMA TX transfer memory must be 4Byte aligned, the transfer size must + * be multiple of 64Byte. So the transfer data is devided in to three part: + * part1 + part2 + part3. + * The part2 is transfered using SMARTDMA, it should be 4Byte aligned, multiple + * of 64Byte. + * The part1 and part3 are transfered using blocking method, each of them is + * less than 64Byte, and total of them is less than (64 + 4) bytes. + * + * This function gets the size of each part. + * + * @param totalLen The total TX size in byte. + * @param startAddr The start address of the TX data. + * @param part1Len Length of the part 1 in byte. + * @param part2Len Length of the part 2 in byte. + * @param part3Len Length of the part 3 in byte. + */ +static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen( + uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len); + +/*! + * @brief Convert RGB565 to RGB888. + * + * @param rgb565 Input RGB565. + * @param pixelCount Pixel count. + * @param rgb888 Output RGB888. + */ +static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888); + +/*! + * @brief Callback function registered to SMARTDMA driver. + */ +static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen( + uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len) +{ + if (totalLen < FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN) + { + *part1Len = totalLen; + *part2Len = 0; + *part3Len = 0; + } + else + { + *part3Len = (startAddr + totalLen) & (FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN - 1U); + *part2Len = ((uint32_t)(totalLen - *part3Len)) & (~(FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN - 1U)); + + if (FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN > *part2Len) + { + *part1Len = totalLen; + *part2Len = 0; + *part3Len = 0; + } + else + { + *part1Len = totalLen - *part2Len - *part3Len; + } + } +} + +static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888) +{ + while ((pixelCount--) != 0U) + { + *rgb888 = (uint8_t)(((*rgb565) & 0x001FU) << 3U); + rgb888++; + *rgb888 = (uint8_t)(((*rgb565) & 0x07E0U) >> 3U); + rgb888++; + *rgb888 = (uint8_t)(((*rgb565) & 0xF800U) >> 8U); + rgb888++; + + rgb565++; + } +} + +/*! + * brief Initializes the FLEXO MCULCD master SMARTDMA handle. + * + * This function initializes the FLEXO MCULCD master SMARTDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_MCULCD_Type structure. + * param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * param config Pointer to the configuration. + * param callback MCULCD transfer complete callback, NULL means no callback. + * param userData callback function parameter. + * retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + const flexio_mculcd_smartdma_config_t *config, + flexio_mculcd_smartdma_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + /* The SMARTDMA firmware only support TX using shifter 0 to shifter 7 */ + if (base->txShifterStartIndex != FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER) + { + return kStatus_InvalidArgument; + } + + if (base->txShifterEndIndex != FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER) + { + return kStatus_InvalidArgument; + } + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + if (NULL == config) + { + handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA; + } + else + { + if (config->inputPixelFormat == config->outputPixelFormat) + { + handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA; + } + else if (((config->inputPixelFormat == kFLEXIO_MCULCD_RGB565) && + (config->outputPixelFormat == kFLEXIO_MCULCD_RGB888)) || + ((config->inputPixelFormat == kFLEXIO_MCULCD_BGR565) && + (config->outputPixelFormat == kFLEXIO_MCULCD_BGR888))) + { + handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA_RGB565To888; + handle->needColorConvert = true; + } + else + { + return kStatus_InvalidArgument; + } + } + + /* Initialize the state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + handle->base = base; + + SMARTDMA_InstallFirmware(SMARTDMA_DISPLAY_MEM_ADDR, s_smartdmaDisplayFirmware, SMARTDMA_DISPLAY_FIRMWARE_SIZE); + + SMARTDMA_InstallCallback(FLEXIO_MCULCD_SMARTDMA_Callback, handle); + + /* The shifter interrupt is used by the SMARTDMA. */ + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, (1UL << FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER)); + +#if (defined(SMARTDMA_USE_FLEXIO_SHIFTER_DMA) && SMARTDMA_USE_FLEXIO_SHIFTER_DMA) + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL, true); +#endif + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA. + * + * This function returns immediately after transfer initiates. Use the callback + * function to check whether the transfer is completed. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * param xfer Pointer to FlexIO MCULCD transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t part1Len, part2Len, part3Len; + + /* Check if the device is busy. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Only support write array. */ + if (kFLEXIO_MCULCD_WriteArray != xfer->mode) + { + return kStatus_InvalidArgument; + } + + FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(xfer->dataSize, xfer->dataAddrOrSameValue, &part1Len, &part2Len, &part3Len); + + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray; + + /* Start transfer. */ + handle->remainingCount = xfer->dataSize; + handle->dataCount = xfer->dataSize; + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + if (part1Len > 0U) + { + if (handle->needColorConvert) + { + FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part1Len >> 1U, + handle->blockingXferBuffer); + FLEXIO_MCULCD_WriteDataArrayBlocking(base, handle->blockingXferBuffer, (part1Len >> 1U) * 3U); + } + else + { + FLEXIO_MCULCD_WriteDataArrayBlocking(base, (void *)(uint8_t *)xfer->dataAddrOrSameValue, (size_t)part1Len); + } + handle->remainingCount -= part1Len; + handle->dataAddrOrSameValue += part1Len; + } + + if (0U == part2Len) + { + /* In this case, all data are sent out as part 1. Only notify upper layer here. */ + FLEXIO_MCULCD_StopTransfer(base); + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Callback to inform upper layer. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base); + + /* Save the part 3 information. */ + handle->dataCountUsingEzh = part2Len; + handle->dataAddrOrSameValue += part2Len; + + /* The part 3 is transfered using blocking method in ISR, convert the color + to save time in ISR. */ + if ((0U != part3Len) && (handle->needColorConvert)) + { + FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part3Len >> 1U, + handle->blockingXferBuffer); + } + + handle->smartdmaParam.p_buffer = (uint32_t *)(xfer->dataAddrOrSameValue + part1Len); + handle->smartdmaParam.buffersize = part2Len; + handle->smartdmaParam.smartdma_stack = handle->smartdmaStack; + + SMARTDMA_Reset(); + SMARTDMA_Boot(handle->smartdmaApi, &(handle->smartdmaParam), 0); + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO MCULCD transfer using SMARTDMA. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD SMARTDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle) +{ + assert(handle != NULL); + + SMARTDMA_Reset(); + + /* Set the handle state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + handle->dataCount = 0; +} + +/*! + * brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD SMARTDMA handle pointer. + * param count Number of count transferred so far by the SMARTDMA transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + uint32_t state = handle->state; + + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == state) + { + return kStatus_NoTransferInProgress; + } + else + { + *count = handle->dataCount - handle->remainingCount; + } + + return kStatus_Success; +} + +static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param) +{ + flexio_mculcd_smartdma_handle_t *flexioMculcdSmartDmaHandle = (flexio_mculcd_smartdma_handle_t *)param; + + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioMculcdSmartDmaHandle->base; + + FLEXIO_MCULCD_WaitTransmitComplete(); + + /* Disable the TX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase); + + flexioMculcdSmartDmaHandle->remainingCount -= flexioMculcdSmartDmaHandle->dataCountUsingEzh; + + /* Send the part 3 */ + if (0U != flexioMculcdSmartDmaHandle->remainingCount) + { + if (flexioMculcdSmartDmaHandle->needColorConvert) + { + FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, flexioMculcdSmartDmaHandle->blockingXferBuffer, + (flexioMculcdSmartDmaHandle->remainingCount >> 1U) * 3U); + } + else + { + FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, + (void *)(uint8_t *)flexioMculcdSmartDmaHandle->dataAddrOrSameValue, + flexioMculcdSmartDmaHandle->remainingCount); + } + } + + flexioMculcdSmartDmaHandle->remainingCount = 0; + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + flexioMculcdSmartDmaHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Callback to inform upper layer. */ + if (NULL != flexioMculcdSmartDmaHandle->completionCallback) + { + flexioMculcdSmartDmaHandle->completionCallback(flexioLcdMcuBase, flexioMculcdSmartDmaHandle, + kStatus_FLEXIO_MCULCD_Idle, + flexioMculcdSmartDmaHandle->userData); + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_smartdma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_smartdma.h new file mode 100644 index 0000000000..3500aaaed0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_mculcd_smartdma.h @@ -0,0 +1,158 @@ +/* + * Copyright 2019,2021,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_MCULCD_SMARTDMA_H_ +#define FSL_FLEXIO_MCULCD_SMARTDMA_H_ + +#include "fsl_smartdma.h" +#include "fsl_flexio_mculcd.h" + +/*! + * @addtogroup flexio_smartdma_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*@{*/ +/*! @brief FlexIO MCULCD SMARTDMA driver version. */ +#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief SMARTDMA transfer size should be multiple of 64 bytes. */ +#define FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN 64U + +/*! @brief SMARTDMA transfer memory address should be 4 byte aligned. */ +#define FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN 4U + +/*! @brief typedef for flexio_mculcd_smartdma_handle_t in advance. */ +typedef struct _flexio_mculcd_smartdma_handle flexio_mculcd_smartdma_handle_t; + +/*! @brief FlexIO MCULCD master callback for transfer complete. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_smartdma_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO MCULCD SMARTDMA transfer handle, users should not touch the + * content of the handle.*/ +struct _flexio_mculcd_smartdma_handle +{ + FLEXIO_MCULCD_Type *base; /*!< Pointer to the FLEXIO_MCULCD_Type. */ + size_t dataCount; /*!< Total count to be transferred. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataCountUsingEzh; /*!< Data transfered using SMARTDMA. */ + volatile size_t remainingCount; /*!< Remaining count to transfer. */ + volatile uint32_t state; /*!< FlexIO MCULCD driver internal state. */ + uint8_t smartdmaApi; /*!< The SMARTDMA API used during transfer. */ + bool needColorConvert; /*!< Need color convert or not. */ + uint8_t blockingXferBuffer[FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN * 3 / + 2]; /*!< Used for blocking method color space convet. */ + flexio_mculcd_smartdma_transfer_callback_t completionCallback; /*!< Callback for MCULCD SMARTDMA transfer */ + void *userData; /*!< User Data for MCULCD SMARTDMA callback */ + smartdma_flexio_mculcd_param_t smartdmaParam; /*!< SMARTDMA function parameters. */ + uint32_t smartdmaStack[1]; /*!< SMARTDMA function stack. */ +}; + +/*! @brief FlexIO MCULCD SMARTDMA configuration. */ +typedef struct _flexio_mculcd_smartdma_config +{ + flexio_mculcd_pixel_format_t inputPixelFormat; /*!< The pixel format in the frame buffer. */ + flexio_mculcd_pixel_format_t outputPixelFormat; /*!< The pixel format on the 8080/68k bus. */ +} flexio_mculcd_smartdma_config_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SMARTDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXO MCULCD master SMARTDMA handle. + * + * This function initializes the FLEXO MCULCD master SMARTDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_MCULCD_Type structure. + * @param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * @param config Pointer to the configuration. + * @param callback MCULCD transfer complete callback, NULL means no callback. + * @param userData callback function parameter. + * @retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + const flexio_mculcd_smartdma_config_t *config, + flexio_mculcd_smartdma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA. + * + * This function returns immediately after transfer initiates. Use the callback + * function to check whether the transfer is completed. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the + * transfer state. + * @param xfer Pointer to FlexIO MCULCD transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO MCULCD transfer using SMARTDMA. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD SMARTDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD SMARTDMA handle pointer. + * @param count Number of count transferred so far by the SMARTDMA transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_smartdma_handle_t *handle, + size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_FLEXIO_MCULCD_SMARTDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi.c new file mode 100644 index 0000000000..96c9a7c0ac --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi.c @@ -0,0 +1,1565 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_spi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi" +#endif + +/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ +enum _flexio_spi_transfer_states +{ + kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */ + kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Send a piece of data for SPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for SPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = (uint32_t) * (handle->txData); + handle->txData++; + } + else if (handle->bytePerFrame == 2U) + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += (uint32_t)handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 2U; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 24U; + tmpData += (uint32_t)(handle->txData[1]) << 16U; + tmpData += (uint32_t)(handle->txData[2]) << 8U; + tmpData += (uint32_t)handle->txData[3]; + } + else + { + tmpData = (uint32_t)(handle->txData[3]) << 24U; + tmpData += (uint32_t)(handle->txData[2]) << 16U; + tmpData += (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 4U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes -= handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + if (0U == handle->txRemainingBytes) + { + FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + } +} + +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint32_t tmpData; + + tmpData = FLEXIO_SPI_ReadData(base, handle->direction); + + if (handle->rxData != NULL) + { + if (handle->bytePerFrame == 1U) + { + *handle->rxData = (uint8_t)tmpData; + } + else if (handle->bytePerFrame == 2U) + { + if (handle->direction == kFLEXIO_SPI_LsbFirst) + { + *handle->rxData = (uint8_t)(tmpData >> 8); + handle->rxData++; + *handle->rxData = (uint8_t)tmpData; + } + else + { + *handle->rxData = (uint8_t)tmpData; + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8); + } + } + else + { + if (handle->direction == kFLEXIO_SPI_LsbFirst) + { + *handle->rxData = (uint8_t)(tmpData >> 24U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 16U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8U); + handle->rxData++; + *handle->rxData = (uint8_t)tmpData; + } + else + { + *handle->rxData = (uint8_t)tmpData; + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 16U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 24U); + } + } + handle->rxData++; + } + handle->rxRemainingBytes -= handle->bytePerFrame; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO + * SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + endcode + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param masterConfig Pointer to the flexio_spi_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base != NULL); + assert(masterConfig != NULL); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Master */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for SCK. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + /* Low 8-bits are used to configure baudrate. */ + timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps); + timerDiv = timerDiv / 2U - 1U; + /* High 8-bits are used to configure shift clock edges(transfer width). */ + timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for CSn. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->CSnPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + timerConfig.timerCompare = 0xFFFFU; /* Never compare. */ + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); +} + +/*! + * brief Resets the FlexIO SPI timer and shifter config. + * + * param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; +} + +/*! + * brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + endcode + * param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + /* Default baud rate 500kbps. */ + masterConfig->baudRate_Bps = 500000U; + /* Default CPHA = 0. */ + masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + masterConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO + * SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + endcode + * param base Pointer to the FLEXIO_SPI_Type structure. + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) +{ + assert((base != NULL) && (slaveConfig != NULL)); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Slave */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave)); + if (!slaveConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for shift clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + } + else + { + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + } + + timerConfig.timerCompare = (uint32_t)slaveConfig->dataMode * 2U - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); +} + +/*! + * brief Gates the FlexIO clock. + * + * param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) +{ + FLEXIO_SPI_MasterDeinit(base); +} + +/*! + * brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + endcode + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->enableInDoze = false; + slaveConfig->enableInDebug = true; + slaveConfig->enableFastAccess = false; + /* Default CPHA = 0. */ + slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +/*! + * brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source. The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask SPI DMA source. + * param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxDmaEnable) != 0U) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable); + } + + if ((mask & (uint32_t)kFLEXIO_SPI_RxDmaEnable) != 0U) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable); + } +} + +/*! + * brief Gets FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * return status flag; Use the status flag to AND the following flag mask and get the status. + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag + */ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) +{ + uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); + uint32_t status = 0; + + status = ((shifterStatus & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= (((shifterStatus & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); + + return status; +} + +/*! + * brief Clears FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask status flag + * The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag + */ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param baudRate_Bps Baud Rate needed in Hz. + * param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = (uint16_t)(srcClockHz / baudRate_Bps); + timerDiv = timerDiv / 2U - 1U; + + timerCmp = (uint16_t)(flexioBase->TIMCMP[base->timerIndex[0]]); + timerCmp &= 0xFF00U; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The data bytes to send. + * param size The number of data bytes to send. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size) +{ + assert(buffer != NULL); + assert(size != 0U); + +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != size--) + { + /* Wait until data transfer complete. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + FLEXIO_SPI_WriteData(base, direction, *buffer++); + } + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The buffer to store the received bytes. + * param size The number of data bytes to be received. + * param direction Shift direction of MSB first or LSB first. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size) +{ + assert(buffer != NULL); + assert(size != 0U); + +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != size--) + { + /* Wait until data transfer complete. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + *buffer++ = (uint8_t)FLEXIO_SPI_ReadData(base, direction); + } + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base pointer to FLEXIO_SPI_Type structure + * param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) +{ + flexio_spi_shift_direction_t direction; + uint8_t bytesPerFrame; + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]); + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + timerCmp &= 0x00FFU; + + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + + /* Configure the values in handle. */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_8bitLsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_LsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_16bitMsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_16bitLsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_LsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_LsbFirst; + break; + + default: + dataMode = (8UL * 2UL - 1UL) << 8U; + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % bytesPerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + while (xfer->dataSize != 0U) + { + /* Wait until data transfer complete. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + if (xfer->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (bytesPerFrame == 1U) + { + tmpData = (uint32_t) * (xfer->txData); + xfer->txData++; + } + else if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(xfer->txData[0]) << 8U; + tmpData += (uint32_t)xfer->txData[1]; + } + else + { + tmpData = (uint32_t)(xfer->txData[1]) << 8U; + tmpData += (uint32_t)xfer->txData[0]; + } + xfer->txData += 2U; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(xfer->txData[0]) << 24U; + tmpData += (uint32_t)(xfer->txData[1]) << 16U; + tmpData += (uint32_t)(xfer->txData[2]) << 8U; + tmpData += (uint32_t)xfer->txData[3]; + } + else + { + tmpData = (uint32_t)(xfer->txData[3]) << 24U; + tmpData += (uint32_t)(xfer->txData[2]) << 16U; + tmpData += (uint32_t)(xfer->txData[1]) << 8U; + tmpData += (uint32_t)xfer->txData[0]; + } + xfer->txData += 4U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + xfer->dataSize -= bytesPerFrame; + + FLEXIO_SPI_WriteData(base, direction, tmpData); + +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + tmpData = FLEXIO_SPI_ReadData(base, direction); + + if (xfer->rxData != NULL) + { + if (bytesPerFrame == 1U) + { + *xfer->rxData = (uint8_t)tmpData; + } + else if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + *xfer->rxData = (uint8_t)(tmpData >> 8); + xfer->rxData++; + *xfer->rxData = (uint8_t)tmpData; + } + else + { + *xfer->rxData = (uint8_t)tmpData; + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8); + } + } + else + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + *xfer->rxData = (uint8_t)(tmpData >> 24U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 16U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8U); + xfer->rxData++; + *xfer->rxData = (uint8_t)tmpData; + } + else + { + *xfer->rxData = (uint8_t)tmpData; + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 16U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 24U); + } + } + xfer->rxData++; + } + } + + return kStatus_Success; +} + +/*! + * brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); +} + +/*! + * brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + timerCmp &= 0x00FFU; + + /* Check if SPI is busy. */ + if (handle->state == (uint32_t)kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0 + enables when tx shifter is written and disables when timer compare. The timer compare event causes the + transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is + disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if + software writes the tx register upon the detection of tx register empty event, the timer enable condition + is triggered again, then the CS signal can remain low until software no longer writes the tx register. */ + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + + /* Configure the values in handle */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_8bitLsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitMsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitLsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = (8UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % handle->bytePerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = (uint32_t)kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Send first byte of data to trigger the rx interrupt. */ + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = (uint32_t) * (handle->txData); + handle->txData++; + } + else if (handle->bytePerFrame == 2U) + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += (uint32_t)handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 2U; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 24U; + tmpData += (uint32_t)(handle->txData[1]) << 16U; + tmpData += (uint32_t)(handle->txData[2]) << 8U; + tmpData += (uint32_t)handle->txData[3]; + } + else + { + tmpData = (uint32_t)(handle->txData[3]) << 24U; + tmpData += (uint32_t)(handle->txData[2]) << 16U; + tmpData += (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 4U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + /* Enable transmit and receive interrupt to handle rx. */ + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); + + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + } + + return kStatus_Success; +} + +/*! + * brief Gets the data transfer status which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Return remaing bytes in different cases. */ + if (handle->rxData != NULL) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + + return kStatus_Success; +} + +/*! + * brief Aborts the master data transfer, which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + assert(handle != NULL); + + FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); + FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + + /* Transfer finished, set the state to idle. */ + handle->state = (uint32_t)kFLEXIO_SPI_Idle; + + /* Clear the internal state. */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +/*! + * brief FlexIO SPI master IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle != NULL); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == (uint32_t)kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Receive interrupt. */ + if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + return; + } + + /* Handle rx. */ + if (handle->rxRemainingBytes != 0U) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* Handle tx. */ + if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_MasterTransferAbort(base, handle); + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} + +/*! + * brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); +} + +/*! + * brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + /* Check if SPI is busy. */ + if (handle->state == (uint32_t)kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */ + /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and + before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode, + timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode, + tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */ + FLEXIO_SPI_FlushShifters(base); + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + else + { + if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) == + FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive)) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + } + + /* Configure the values in handle */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + dataMode = 8U * 2U - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_8bitLsb: + dataMode = 8U * 2U - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitMsb: + dataMode = 16U * 2U - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitLsb: + dataMode = 16U * 2U - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = 32UL * 2UL - 1UL; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = 32UL * 2UL - 1UL; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = 8UL * 2UL - 1UL; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % handle->bytePerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = (uint32_t)kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Enable transmit and receive interrupt to handle tx and rx. */ + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +/*! + * brief FlexIO SPI slave IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle != NULL); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == (uint32_t)kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle tx. */ + if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* Handle rx. */ + if (((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) && (handle->rxRemainingBytes != 0U)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_SlaveTransferAbort(base, handle); + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} + +/*! + * brief Flush tx/rx shifters. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + */ +void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base) +{ + /* Disable then re-enable to flush the tx shifter. */ + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + /* Read to flush the rx shifter. */ + (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]]; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi.h new file mode 100644 index 0000000000..338cf43ab3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi.h @@ -0,0 +1,719 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_SPI_H_ +#define FSL_FLEXIO_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO SPI driver version. */ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) +/*@}*/ + +#ifndef FLEXIO_SPI_DUMMYDATA +/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ +#define FLEXIO_SPI_DUMMYDATA (0x00U) +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Get the transfer data format of width and bit order. */ +#define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U)) + +/*! @brief Error codes for the FlexIO SPI driver. */ +enum +{ + kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ + kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ + kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ + kStatus_FLEXIO_SPI_Timeout = + MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 4), /*!< FlexIO SPI timeout polling status flags. */ +}; + +/*! @brief FlexIO SPI clock phase configuration. */ +typedef enum _flexio_spi_clock_phase +{ + kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first + * cycle of a data transfer. */ + kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the + * first cycle of a data transfer. */ +} flexio_spi_clock_phase_t; + +/*! @brief FlexIO SPI data shifter direction options. */ +typedef enum _flexio_spi_shift_direction +{ + kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */ + kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */ +} flexio_spi_shift_direction_t; + +/*! @brief FlexIO SPI data length mode options. */ +typedef enum _flexio_spi_data_bitcount_mode +{ + kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ + kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ + kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */ +} flexio_spi_data_bitcount_mode_t; + +/*! @brief Define FlexIO SPI interrupt mask. */ +enum _flexio_spi_interrupt_enable +{ + kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO SPI status mask. */ +enum _flexio_spi_status_flags +{ + kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO SPI DMA mask. */ +enum _flexio_spi_dma_enable +{ + kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ + kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ +}; + +/*! @brief Define FlexIO SPI transfer flags. + * @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */ +enum _flexio_spi_transfer_flags +{ + kFLEXIO_SPI_8bitMsb = 0x0U, /*!< FlexIO SPI 8-bit MSB first */ + kFLEXIO_SPI_8bitLsb = 0x1U, /*!< FlexIO SPI 8-bit LSB first */ + kFLEXIO_SPI_16bitMsb = 0x2U, /*!< FlexIO SPI 16-bit MSB first */ + kFLEXIO_SPI_16bitLsb = 0x3U, /*!< FlexIO SPI 16-bit LSB first */ + kFLEXIO_SPI_32bitMsb = 0x4U, /*!< FlexIO SPI 32-bit MSB first */ + kFLEXIO_SPI_32bitLsb = 0x5U, /*!< FlexIO SPI 32-bit LSB first */ + kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */ +}; + +/*! @brief Define FlexIO SPI access structure typedef. */ +typedef struct _flexio_spi_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDOPinIndex; /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as + GPIO input and disable all pull up/down in application. */ + uint8_t SDIPinIndex; /*!< Pin select for data input. */ + uint8_t SCKPinIndex; /*!< Pin select for clock. */ + uint8_t CSnPinIndex; /*!< Pin select for enable. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */ +} FLEXIO_SPI_Type; + +/*! @brief Define FlexIO SPI master configuration structure. */ +typedef struct _flexio_spi_master_config +{ + bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_master_config_t; + +/*! @brief Define FlexIO SPI slave configuration structure. */ +typedef struct _flexio_spi_slave_config +{ + bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_slave_config_t; + +/*! @brief Define FlexIO SPI transfer structure. */ +typedef struct _flexio_spi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t dataSize; /*!< Transfer bytes. */ + uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ +} flexio_spi_transfer_t; + +/*! @brief typedef for flexio_spi_master_handle_t in advance. */ +typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO SPI handle structure. */ +struct _flexio_spi_master_handle +{ + uint8_t *txData; /*!< Transfer buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */ + volatile uint32_t state; /*!< FlexIO SPI internal state. */ + uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ + flexio_spi_shift_direction_t direction; /*!< Shift direction. */ + flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO SPI Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * @note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO + * SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO SPI timer and shifter config. + * + * @param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + @code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + @endcode + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig); + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * @note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO + * SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + @endcode + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig); + +/*! + * @brief Gates the FlexIO clock. + * + * @param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + @code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + @endcode + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @return status flag; Use the status flag to AND the following flag mask and get the status. + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag + */ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); + +/*! + * @brief Clears FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask status flag + * The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag + */ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source. The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask SPI DMA source. + * @param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable); + +/*! + * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI transmit data register address. + */ +static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, + base->shifterIndex[0]) + + 3U; + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); + } +} + +/*! + * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI receive data register address. + */ +static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]); + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U; + } +} + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI module operation. + * + * @param base Pointer to the FLEXIO_SPI_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param baudRate_Bps Baud Rate needed in Hz. + * @param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz); + +/*! + * @brief Writes one byte of data, which is sent using the MSB method. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param data 8/16/32 bit data. + */ +static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; + } + else + { + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data; + } +} + +/*! + * @brief Reads 8 bit/16 bit data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return 8 bit/16 bit data received. + */ +static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]); + } + else + { + return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); + } +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The data bytes to send. + * @param size The number of data bytes to send. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The buffer to store the received bytes. + * @param size The number of data bytes to be received. + * @param direction Shift direction of MSB first or LSB first. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); + +/*! + * @brief Flush tx/rx shifters. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + */ +void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base); +/*@}*/ + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the master data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO SPI master IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle); + +/*! + * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the slave data transfer which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbort(base, handle); +} +/*! + * @brief Gets the data transfer status which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief FlexIO SPI slave IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*FSL_FLEXIO_SPI_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi_edma.c new file mode 100644 index 0000000000..c1feba0f00 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi_edma.c @@ -0,0 +1,565 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_spi_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma" +#endif + +/*base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback != NULL) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; + + if (transferDone) + { + /* Disable Rx dma */ + FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback != NULL) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + edma_transfer_config_t xferConfig = {0}; + flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst; + uint8_t bytesPerFrame; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + /* Configure the values in handle. */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_8bitLsb: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitMsb: + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitLsb: + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_LsbFirst; + break; + default: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % bytesPerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Configure tx transfer EDMA. */ + xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); + xferConfig.destOffset = 0; + if (bytesPerFrame == 1U) + { + xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.minorLoopBytes = 1U; + } + else if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 1U; + } + xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.minorLoopBytes = 2U; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 3U; + } + xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.minorLoopBytes = 4U; + } + + /* Configure DMA channel. */ + if (xfer->txData != NULL) + { + xferConfig.srcOffset = (int16_t)bytesPerFrame; + xferConfig.srcAddr = (uint32_t)(xfer->txData); + } + else + { + /* Disable the source increasement and source set to dummyData. */ + xferConfig.srcOffset = 0; + xferConfig.srcAddr = (uint32_t)(&s_dummyData); + } + + xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */ + handle->nbytes = (uint8_t)xferConfig.minorLoopBytes; + + if (handle->txHandle != NULL) + { + (void)EDMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + + /* Configure rx transfer EDMA. */ + if (xfer->rxData != NULL) + { + xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction); + if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + xferConfig.srcAddr -= 1U; + } + } + else if (bytesPerFrame == 4U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + xferConfig.srcAddr -= 3U; + } + } + else + { + } + xferConfig.srcOffset = 0; + xferConfig.destAddr = (uint32_t)(xfer->rxData); + xferConfig.destOffset = (int16_t)bytesPerFrame; + (void)EDMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, true); + EDMA_StartTransfer(handle->rxHandle); + } + + /* Always start tx transfer. */ + if (handle->txHandle != NULL) + { + handle->txInProgress = true; + FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, true); + EDMA_StartTransfer(handle->txHandle); + } + + return kStatus_Success; +} + +/*! + * brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param callback SPI callback, NULL means no callback. + * param userData callback function parameter. + * param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + assert(handle != NULL); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0U; index < (uint8_t)FLEXIO_SPI_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == (uint16_t)FLEXIO_SPI_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + /* Set spi base to handle. */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle. */ + handle->txInProgress = false; + handle->rxInProgress = false; + + /* Install callback for Tx/Rx dma channel. */ + if (handle->txHandle != NULL) + { + EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]); + } + if (handle->rxHandle != NULL) + { + EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]); + } + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + timerCmp &= 0x00FFU; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0 + enables when tx shifter is written and disables when timer compare. The timer compare event causes the + transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is + disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if + software writes the tx register upon the detection of tx register empty event, the timer enable condition + is triggered again, then the CS signal can remain low until software no longer writes the tx register. */ + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + + /* configure data mode. */ + if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb)) + { + dataMode = (8UL * 2UL - 1UL) << 8U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb)) + { + dataMode = (16UL * 2UL - 1UL) << 8U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb)) + { + dataMode = (32UL * 2UL - 1UL) << 8U; + } + else + { + dataMode = (8UL * 2UL - 1UL) << 8U; + } + + dataMode |= timerCmp; + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + return FLEXIO_SPI_EDMAConfig(base, handle, xfer); +} + +/*! + * brief Gets the remaining bytes for FlexIO SPI eDMA transfer. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + if (handle->rxInProgress) + { + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->rxHandle->base, handle->rxHandle->channel)); + } + else + { + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->txHandle->base, handle->txHandle->channel)); + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO SPI transfer using eDMA. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable dma. */ + EDMA_AbortTransfer(handle->txHandle); + EDMA_AbortTransfer(handle->rxHandle); + + /* Disable DMA enable bit. */ + FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_DmaAllEnable, false); + + /* Set the handle state. */ + handle->txInProgress = false; + handle->rxInProgress = false; +} + +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0U; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */ + /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and + before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode, + timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode, + tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */ + FLEXIO_SPI_FlushShifters(base); + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + else + { + if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) == + FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive)) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb)) + { + dataMode = 8U * 2U - 1U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb)) + { + dataMode = 16U * 2U - 1U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb)) + { + dataMode = 32UL * 2UL - 1UL; + } + else + { + dataMode = 8U * 2U - 1U; + } + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + return FLEXIO_SPI_EDMAConfig(base, handle, xfer); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi_edma.h new file mode 100644 index 0000000000..6700548986 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_spi_edma.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_SPI_EDMA_H_ +#define FSL_FLEXIO_SPI_EDMA_H_ + +#include "fsl_flexio_spi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO SPI EDMA driver version. */ +#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ +typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_spi_master_edma_handle +{ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + bool txInProgress; /*!< Send transfer in progress */ + bool rxInProgress; /*!< Receive transfer in progress */ + edma_handle_t *txHandle; /*!< DMA handler for SPI send */ + edma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + flexio_spi_master_edma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle); + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes transferred so far using FlexIO SPI master eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count); + +/*! + * @brief Initializes the FlexIO SPI slave eDMA handle. + * + * This function initializes the FlexIO SPI slave eDMA handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + */ +static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + (void)FLEXIO_SPI_MasterTransferCreateHandleEDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbortEDMA(base, handle); +} + +/*! + * @brief Gets the number of bytes transferred so far using FlexIO SPI slave eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCountEDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart.c new file mode 100644 index 0000000000..13890caee7 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart.c @@ -0,0 +1,1023 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart" +#endif + +/*flexioBase); +} + +static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle) +{ + size_t size; + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; + + if (rxRingBufferTail > rxRingBufferHead) + { + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; + } + else + { + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; + } + + return size; +} + +static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle) +{ + bool full; + + if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + endcode + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param userConfig Pointer to the flexio_uart_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Configuration success. + * retval kStatus_FLEXIO_UART_BaudrateNotSupport Baudrate is not supported for current clock source frequency. +*/ +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz) +{ + assert((base != NULL) && (userConfig != NULL)); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + uint32_t calculatedBaud; + uint32_t diff; + status_t result = kStatus_Success; + + /* Clear the shifterConfig & timerConfig struct. */ + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO UART */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableUart)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->TxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /*2. Configure the timer 0 for tx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->TxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = (uint16_t)(srcClock_Hz / userConfig->baudRate_Bps); + timerDiv = timerDiv / 2U - 1U; + + if (timerDiv > 0xFFU) + { + /* Check whether the calculated timerDiv is within allowed range. */ + return kStatus_FLEXIO_UART_BaudrateNotSupport; + } + else + { + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculated timerDiv value */ + calculatedBaud = srcClock_Hz / (((uint32_t)timerDiv + 1U) * 2U); + /* timerDiv cannot be larger than the ideal divider, so calculatedBaud is definitely larger + than configured baud */ + diff = calculatedBaud - userConfig->baudRate_Bps; + if (diff > ((userConfig->baudRate_Bps / 100U) * 3U)) + { + return kStatus_FLEXIO_UART_BaudrateNotSupport; + } + } + + timerCmp = ((uint16_t)userConfig->bitCountPerChar * 2U - 1U) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 3. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->RxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /* 4. Configure the timer 1 for rx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->RxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + return result; +} + +/*! + * brief Resets the FlexIO UART shifter and timer config. + * + * note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * param base Pointer to FLEXIO_UART_Type structure + */ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[1]); +} + +/*! + * brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + endcode + * param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) +{ + assert(userConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(userConfig, 0, sizeof(*userConfig)); + + userConfig->enableUart = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; + /* Default baud rate 115200. */ + userConfig->baudRate_Bps = 115200U; + /* Default bit count at 8. */ + userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; +} + +/*! + * brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * return FlexIO UART status flags. + */ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) +{ + uint32_t status = 0U; + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + return status; +} + +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_UART_TxDataRegEmptyFlag + * arg kFLEXIO_UART_RxEmptyFlag + * arg kFLEXIO_UART_RxOverRunFlag + */ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxOverRunFlag) != 0U) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param txData The data bytes to send. + * param txSize The number of data bytes to send. + * retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) +{ + assert(txData != NULL); + assert(txSize != 0U); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != txSize--) + { + /* Wait until data transfer complete. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_FLEXIO_UART_Timeout; + } +#endif + + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++; + } + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param rxData The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + * retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) +{ + assert(rxData != NULL); + assert(rxSize != 0U); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != rxSize--) + { + /* Wait until data transfer complete. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (FLEXIO_UART_GetStatusFlags(base) & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_UART_GetStatusFlags(base) & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_FLEXIO_UART_Timeout; + } +#endif + + *rxData++ = (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); + } + return kStatus_Success; +} + +/*! + * brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base to FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle != NULL); + + /* Setup the ringbuffer address */ + if (ringBuffer != NULL) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->rxState == (uint8_t)kFLEXIO_UART_RxIdle) + { + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * retval kStatus_Success Successfully starts the data transmission. + * retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->txData)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if ((uint8_t)kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kFLEXIO_UART_TxBusy; + + /* Enable transmiter interrupt. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Disable the transmitter and disable the interrupt. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + handle->txDataSize = 0U; + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; +} + +/*! + * brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer UART transfer structure. See #flexio_uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* Disable FLEXIO_UART RX IRQ, protect ring buffer. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if ((uint32_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kFLEXIO_UART_RxBusy; + } + + /* Enable FLEXIO_UART RX IRQ if previously enabled. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kFLEXIO_UART_RxBusy; + + /* Enable RX interrupt. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; +} + +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * param uartType Pointer to the FLEXIO_UART_Type structure. + * param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) +{ + uint8_t count = 1; + FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; + flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; + uint16_t rxRingBufferHead; + + /* Read the status back. */ + uint32_t status = FLEXIO_UART_GetStatusFlags(base); + + /* If RX overrun. */ + if (((uint32_t)kFLEXIO_UART_RxOverRunFlag & status) != 0U) + { + /* Clear Overrun flag. */ + FLEXIO_UART_ClearStatusFlags(base, (uint32_t)kFLEXIO_UART_RxOverRunFlag); + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((((uint32_t)kFLEXIO_UART_RxDataRegFullFlag & status) != 0U) && + ((base->flexioBase->SHIFTSIEN & (1UL << base->shifterIndex[1])) != 0U)) + { + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + if (handle->rxDataSize != 0U) + { + /* Using non block API to read the data from the registers. */ + FLEXIO_UART_ReadByte(base, handle->rxData); + handle->rxDataSize--; + handle->rxData++; + count--; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + + if (handle->rxRingBuffer != NULL) + { + if (count != 0U) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if ((uint32_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + rxRingBufferHead = handle->rxRingBufferHead; + handle->rxRingBuffer[rxRingBufferHead] = + (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); + + /* Increase handle->rxRingBufferHead. */ + if ((uint32_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((((uint32_t)kFLEXIO_UART_TxDataRegEmptyFlag & status) != 0U) && + ((base->flexioBase->SHIFTSIEN & (1UL << base->shifterIndex[0])) != 0U)) + { + if (handle->txDataSize != 0U) + { + /* Using non block API to write the data to the registers. */ + FLEXIO_UART_WriteByte(base, handle->txData); + handle->txData++; + handle->txDataSize--; + + /* If all the data are written to data register, TX finished. */ + if (0U == handle->txDataSize) + { + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; + + /* Disable TX register empty interrupt. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData); + } + } + } + } +} + +/*! + * brief Flush tx/rx shifters. + * + * param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base) +{ + /* Disable then re-enable to flush the tx shifter. */ + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + /* Read to flush the rx shifter. */ + (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]]; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart.h new file mode 100644 index 0000000000..bc82a0aee6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart.h @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_UART_H_ +#define FSL_FLEXIO_UART_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO UART driver version. */ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the UART driver. */ +enum +{ + kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */ + kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ + kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ + kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ + kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ + kStatus_FLEXIO_UART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ + kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6), /*!< UART RX receiver overrun. */ + kStatus_FLEXIO_UART_Timeout = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 7), /*!< UART times out. */ + kStatus_FLEXIO_UART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_FLEXIO_UART, 8) /*!< Baudrate is not supported in current clock source */ +}; + +/*! @brief FlexIO UART bit count per char. */ +typedef enum _flexio_uart_bit_count_per_char +{ + kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */ + kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */ + kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */ +} flexio_uart_bit_count_per_char_t; + +/*! @brief Define FlexIO UART interrupt mask. */ +enum _flexio_uart_interrupt_enable +{ + kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO UART status mask. */ +enum _flexio_uart_status_flags +{ + kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ +}; + +/*! @brief Define FlexIO UART access structure typedef. */ +typedef struct _flexio_uart_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t TxPinIndex; /*!< Pin select for UART_Tx. */ + uint8_t RxPinIndex; /*!< Pin select for UART_Rx. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO UART. */ +} FLEXIO_UART_Type; + +/*! @brief Define FlexIO UART user configuration structure. */ +typedef struct _flexio_uart_config +{ + bool enableUart; /*!< Enable/disable FlexIO UART TX & RX. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */ +} flexio_uart_config_t; + +/*! @brief Define FlexIO UART transfer structure. */ +typedef struct _flexio_uart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< Transfer size*/ +} flexio_uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_handle flexio_uart_handle_t; + +/*! @brief FlexIO UART transfer callback function. */ +typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FLEXIO UART handle structure*/ +struct _flexio_uart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + flexio_uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + @code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param userConfig Pointer to the flexio_uart_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Configuration success. + * @retval kStatus_FLEXIO_UART_BaudrateNotSupport Baudrate is not supported for current clock source frequency. +*/ +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO UART shifter and timer config. + * + * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * @param base Pointer to FLEXIO_UART_Type structure + */ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + @code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + @endcode + * @param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART status flags. + */ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_UART_TxDataRegEmptyFlag + * @arg kFLEXIO_UART_RxEmptyFlag + * @arg kFLEXIO_UART_RxOverRunFlag + */ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the FlexIO UARt transmit data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART transmit data register address. + */ +static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); +} + +/*! + * @brief Gets the FlexIO UART receive data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART receive data register address. + */ +static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]); +} + +/*! + * @brief Enables/disables the FlexIO UART transmit DMA. + * This function enables/disables the FlexIO UART Tx DMA, + * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable); +} + +/*! + * @brief Enables/disables the FlexIO UART receive DMA. + * This function enables/disables the FlexIO UART Rx DMA, + * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable); +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO UART module operation. + * + * @param base Pointer to the FLEXIO_UART_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Writes one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register. Ensure that the TxEmptyFlag is asserted before calling + * this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The data bytes to send. + */ +static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer) +{ + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer; +} + +/*! + * @brief Reads one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The buffer to store the received bytes. + */ +static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer) +{ + *buffer = (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param txData The data bytes to send. + * @param txSize The number of data bytes to send. + * @retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param rxData The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + * @retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base to FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * @retval kStatus_Success Successfully starts the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer UART transfer structure. See #flexio_uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * @param uartType Pointer to the FLEXIO_UART_Type structure. + * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); + +/*! + * @brief Flush tx/rx shifters. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*FSL_FLEXIO_UART_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart_edma.c new file mode 100644 index 0000000000..f2502c9df2 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart_edma.c @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_uart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma" +#endif + +/*handle != NULL); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + FLEXIO_UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback != NULL) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData); + } + } +} + +static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle, + void *param, + bool transferDone, + uint32_t tcds) +{ + flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param; + + assert(uartPrivateHandle->handle != NULL); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + FLEXIO_UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback != NULL) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the UART handle which is used in transactional functions. + * + * param base Pointer to FLEXIO_UART_Type. + * param handle Pointer to flexio_uart_edma_handle_t structure. + * param callback The callback function. + * param userData The parameter of the callback function. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle != NULL); + + uint8_t index = 0U; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0U; index < (uint8_t)FLEXIO_UART_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == (uint8_t)FLEXIO_UART_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + + /* Configure TX. */ + if (txEdmaHandle != NULL) + { + EDMA_SetCallback(handle->txEdmaHandle, FLEXIO_UART_TransferSendEDMACallback, &s_edmaPrivateHandle); + } + + /* Configure RX. */ + if (rxEdmaHandle != NULL) + { + EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_UART_TransferReceiveEDMACallback, &s_edmaPrivateHandle); + } + + return kStatus_Success; +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent out, the send callback function is called. + * + * param base Pointer to FLEXIO_UART_Type + * param handle UART handle pointer. + * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->txEdmaHandle != NULL); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if ((uint8_t)kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txState = (uint8_t)kFLEXIO_UART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (uint32_t *)FLEXIO_UART_GetTxDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = 1U; + + /* Submit transfer. */ + (void)EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle != NULL); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if ((uint8_t)kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kFLEXIO_UART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (uint32_t *)FLEXIO_UART_GetRxDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + (void)EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data which using eDMA. + * + * This function aborts sent data which using eDMA. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->txEdmaHandle != NULL); + + /* Disable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; +} + +/*! + * brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle != NULL); + + /* Disable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; +} + +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count) +{ + assert(handle != NULL); + assert(handle->rxEdmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(handle->txEdmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart_edma.h new file mode 100644 index 0000000000..3809ad98ae --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_flexio_uart_edma.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_UART_EDMA_H_ +#define FSL_FLEXIO_UART_EDMA_H_ + +#include "fsl_flexio_uart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO UART EDMA driver version. */ +#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief UART eDMA handle + */ +struct _flexio_uart_edma_handle +{ + flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_UART_Type. + * @param handle Pointer to flexio_uart_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent out, the send callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle UART handle pointer. + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data which using eDMA. + * + * This function aborts sent data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_UART_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_freqme.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_freqme.c new file mode 100644 index 0000000000..459bbb6f3a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_freqme.c @@ -0,0 +1,155 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_freqme.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_freqme" +#endif + +#if defined(FREQME_RSTS_N) +#define FREQME_RESETS_ARRAY FREQME_RSTS_N +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t FREQME_GetInstance(FREQME_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map freqme instance number to base address. */ +static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to FREQME clocks for each instance. */ +static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FREQME_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_freqmeResets[] = FREQME_RESETS_ARRAY; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FREQME_GetInstance(FREQME_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_freqmeBases); instance++) + { + if (s_freqmeBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_freqmeBases)); + + return instance; +} + +/*! + * brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. + * + * param base FREQME peripheral base address. + * param config The pointer to module basic configuration, please refer to freq_measure_config_t. + */ +void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config) +{ + assert(config); + + uint32_t tmp32 = 0UL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable FREQME clock. */ + CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FREQME_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_freqmeResets[FREQME_GetInstance(base)]); +#endif + + if (config->startMeasurement) + { + tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; + } + tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | + FREQME_CTRL_W_PULSE_MODE(config->operateMode); + if (config->operateMode == kFREQME_FreqMeasurementMode) + { + tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor); + } + else + { + tmp32 |= FREQME_CTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity); + } + + base->CTRL_W = tmp32; +} + +/*! + * brief Get default configuration. + * + * code + * config->operateMode = kFREQME_FreqMeasurementMode; + * config->operateModeAttribute.refClkScaleFactor = 0U; + * config->enableContinuousMode = false; + * config->startMeasurement = false; + * endcode + * + * param config The pointer to module basic configuration, please refer to freq_measure_config_t. + */ +void FREQME_GetDefaultConfig(freq_measure_config_t *config) +{ + assert(config); + + (void)memset(config, 0, sizeof(*config)); + + config->operateMode = kFREQME_FreqMeasurementMode; + config->operateModeAttribute.refClkScaleFactor = 0U; + config->enableContinuousMode = false; + config->startMeasurement = false; +} + +/*! + * brief Calculate the frequency of selected target clock. + * + * note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. + * + * note This function only useful when the operate mode is selected as frequency measurement mode. + * + * param base FREQME peripheral base address. + * param refClkFrequency The frequency of reference clock. + * return The frequency of target clock, if the output result is 0, please check the module's operate mode. + */ +uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency) +{ + uint32_t measureResult = 0UL; + uint32_t targetFreq = 0UL; + uint64_t tmp64 = 0ULL; + + while ((base->CTRL_R & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL) + { + } + + if (!FREQME_CheckOperateMode(base)) + { + measureResult = base->CTRL_R & FREQME_CTRL_R_RESULT_MASK; + tmp64 = ((uint64_t)measureResult - 2ULL) * (uint64_t)refClkFrequency; + targetFreq = (uint32_t)(tmp64 / (1ULL << (uint64_t)FREQME_GetReferenceClkScaleValue(base))); + } + + return targetFreq; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_freqme.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_freqme.h new file mode 100644 index 0000000000..72e281051f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_freqme.h @@ -0,0 +1,441 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FREQME_H_ +#define FSL_FREQME_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_freqme + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FREQME driver version 2.1.2. */ +#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*@}*/ + +/*! + * @brief The enumeration of interrupt status flags. + * @anchor _freqme_interrupt_status_flags + */ +enum _freqme_interrupt_status_flags +{ + kFREQME_UnderflowInterruptStatusFlag = FREQME_CTRLSTAT_LT_MIN_STAT_MASK, /*!< Indicate the measurement is + just done and the result is less + than minimun value. */ + kFREQME_OverflowInterruptStatusFlag = FREQME_CTRLSTAT_GT_MAX_STAT_MASK, /*!< Indicate the measurement is + just done and the result is greater + than maximum value. */ + kFREQME_ReadyInterruptStatusFlag = FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< Indicate the measurement is + just done and the result is ready to + read. */ + kFREQME_AllInterruptStatusFlags = FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | + FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< All interrupt + status flags. */ +}; + +/*! + * @brief The enumeration of interrupts, including underflow interrupt, overflow interrupt, + * and result ready interrupt. + * @anchor _freqme_interrupt_enable + */ +enum _freqme_interrupt_enable +{ + kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is + less than minimum value. */ + kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is + greater than maximum value. */ + kFREQME_ReadyInterruptEnable = FREQME_CTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a + measurement completes and the result + is ready. */ +}; + +/*! + * @brief FREQME module operate mode enumeration, including frequency measurement mode + * and pulse width measurement mode. + */ +typedef enum _freqme_operate_mode +{ + kFREQME_FreqMeasurementMode = 0U, /*!< The module works in the frequency measurement mode. */ + kFREOME_PulseWidthMeasurementMode, /*!< The module works in the pulse width measurement mode. */ +} freqme_operate_mode_t; + +/*! + * @brief The enumeration of pulse polarity. + */ +typedef enum _freqme_pulse_polarity +{ + kFREQME_PulseHighPeriod = 0U, /*!< Select high period of the reference clock. */ + kFREQME_PulseLowPeriod, /*!< Select low period of the reference clock. */ +} freqme_pulse_polarity_t; + +/*! + * @brief The union of operate mode attribute. + * @note If the operate mode is selected as frequency measurement mode the member \b refClkScaleFactor should be used, + * if the operate mode is selected as pulse width measurement mode the member \b pulsePolarity should be used. + */ +typedef union _freqme_mode_attribute +{ + uint8_t refClkScaleFactor; /*!< Only useful in frequency measurement operate mode, + used to set the reference clock counter scaling factor. */ + freqme_pulse_polarity_t pulsePolarity; /*!< Only Useful in pulse width measurement operate mode, + used to set period polarity. */ +} freqme_mode_attribute_t; + +/*! + * @brief The structure of freqme module basic configuration, + * including operate mode, operate mode attribute and so on. + */ +typedef struct _freq_measure_config +{ + freqme_operate_mode_t operateMode; /*!< Select operate mode, please refer to @ref freqme_operate_mode_t. */ + freqme_mode_attribute_t operateModeAttribute; /*!< Used to set the attribute of the selected operate mode, if + the operate mode is selected as @ref kFREQME_FreqMeasurementMode + set freqme_mode_attribute_t::refClkScaleFactor, if operate mode is + selected as @ref kFREOME_PulseWidthMeasurementMode, please set + freqme_mode_attribute_t::pulsePolarity. */ + + bool enableContinuousMode; /*!< Enable/disable continuous mode, if continuous mode is enable, + the measurement is performed continuously and the result for the + last completed measurement is available in the result register. */ + bool startMeasurement; +} freq_measure_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Basic Control APIs + * @{ + */ +/*! + * @brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. + * + * @param base FREQME peripheral base address. + * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. + */ +void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config); + +/*! + * @brief Get default configuration. + * + * @code + * config->operateMode = kFREQME_FreqMeasurementMode; + * config->operateModeAttribute.refClkScaleFactor = 0U; + * config->enableContinuousMode = false; + * config->startMeasurement = false; + * @endcode + * + * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. + */ +void FREQME_GetDefaultConfig(freq_measure_config_t *config); + +/*! + * @brief Start frequency or pulse width measurement process. + * + * @param base FREQME peripheral base address. + */ +static inline void FREQME_StartMeasurementCycle(FREQME_Type *base) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; + base->CTRL_W = tmp32; +} + +/*! + * @brief Force the termination of any measurement cycle currently in progress and resets RESULT or just reset + * RESULT if the module in idle state. + * + * @param base FREQME peripheral base address. + */ +static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + base->CTRL_W = tmp32; +} + +/*! + * @brief Enable/disable Continuous mode. + * + * @param base FREQME peripheral base address. + * @param enable Used to enable/disable continuous mode, + * - \b true Enable Continuous mode. + * - \b false Disable Continuous mode. + */ +static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + if (enable) + { + tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK; + } + + base->CTRL_W = tmp32; +} + +/*! + * @brief Check whether continuous mode is enabled. + * + * @param base FREQME peripheral base address. + * @retval True Continuous mode is enabled, the measurement is performed continuously. + * @retval False Continuous mode is disabled. + */ +static inline bool FREQME_CheckContinuousMode(FREQME_Type *base) +{ + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) != 0UL); +} + +/*! + * @brief Set operate mode of freqme module. + * + * @param base FREQME peripheral base address. + * @param operateMode The operate mode to be set, please refer to @ref freqme_operate_mode_t. + */ +static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_t operateMode) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + if (operateMode == kFREOME_PulseWidthMeasurementMode) + { + tmp32 |= FREQME_CTRL_W_PULSE_MODE_MASK; + } + + base->CTRL_W = tmp32; +} + +/*! + * @brief Check module's operate mode. + * + * @param base FREQME peripheral base address. + * @retval True Pulse width measurement mode. + * @retval False Frequency measurement mode. + */ +static inline bool FREQME_CheckOperateMode(FREQME_Type *base) +{ + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_MODE_MASK) != 0UL); + +} + +/*! + * @brief Set the minimum expected value for the measurement result. + * + * @param base FREQME peripheral base address. + * @param minValue The minimum value to set, please note that this value is 31 bits width. + */ +static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue) +{ + base->MIN = minValue; +} + +/*! + * @brief Set the maximum expected value for the measurement result. + * + * @param base FREQME peripheral base address. + * @param maxValue The maximum value to set, please note that this value is 31 bits width. + */ +static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue) +{ + base->MAX = maxValue; +} + +/*! @} */ + +/*! + * @name Frequency Measurement Mode Control APIs + * @{ + */ + +/*! + * @brief Calculate the frequency of selected target clock。 + * + * @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. + * + * @note This function only useful when the operate mode is selected as frequency measurement mode. + * + * @param base FREQME peripheral base address. + * @param refClkFrequency The frequency of reference clock. + * @return The frequency of target clock the unit is Hz, if the output result is 0, please check the module's + * operate mode. + */ +uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency); + +/*! + * @brief Get reference clock scaling factor. + * + * @param base FREQME peripheral base address. + * @return Reference clock scaling factor, the reference count cycle is 2 ^ ref_scale. + */ +static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base) +{ + return (uint8_t)(base->CTRLSTAT & FREQME_CTRLSTAT_REF_SCALE_MASK); +} + +/*! @} */ + +/*! + * @name Pulse Width Measurement Mode Control APIs + * @{ + */ + +/*! + * @brief Set pulse polarity when operate mode is selected as Pulse Width Measurement mode. + * + * @param base FREQME peripheral base address. + * @param pulsePolarity The pulse polarity to be set, please refer to @ref freqme_pulse_polarity_t. + */ +static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polarity_t pulsePolarity) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + + if (pulsePolarity != kFREQME_PulseHighPeriod) + { + tmp32 |= FREQME_CTRL_W_PULSE_POL_MASK; + } + + base->CTRL_W = tmp32; +} + +/*! + * @brief Check pulse polarity when the operate mode is selected as pulse width measurement mode. + * + * @param base FREQME peripheral base address. + * @retval True Low period. + * @retval False High period. + */ +static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base) +{ + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_POL_MASK) != 0UL); +} + +/*! + * @brief Get measurement result, if operate mode is selected as pulse width measurement mode this function can + * be used to calculate pulse width. + * + * @note Pulse width = counter result / Frequency of target clock. + * + * @param base FREQME peripheral base address. + * @return Measurement result. + */ +static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base) +{ + return base->CTRL_R & FREQME_CTRL_R_RESULT_MASK; +} + +/*! @} */ + +/*! + * @name Status Control APIs + * @{ + */ + +/*! + * @brief Get interrupt status flags, such as overflow interrupt status flag, + * underflow interrupt status flag, and so on. + * + * @param base FREQME peripheral base address. + * @return Current interrupt status flags, should be the OR'ed value of @ref _freqme_interrupt_status_flags. + */ +static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base) +{ + return (base->CTRLSTAT & (uint32_t)kFREQME_AllInterruptStatusFlags); +} + +/*! + * @brief Clear interrupt status flags. + * + * @param base FREQME peripheral base address. + * @param statusFlags The combination of interrupt status flags to clear, + * should be the OR'ed value of @ref _freqme_interrupt_status_flags. + */ +static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags) +{ + base->CTRLSTAT |= statusFlags; +} + +/*! @} */ + +/*! + * @name Interrupt Control APIs + * @{ + */ + +/*! + * @brief Enable interrupts, such as result ready interrupt, overflow interrupt and so on. + * + * @param base FREQME peripheral base address. + * @param masks The mask of interrupts to enable, should be the OR'ed value of @ref _freqme_interrupt_enable. + */ +static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK | + FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + + tmp32 |= masks; + base->CTRL_W = tmp32; +} + +/*! + * @brief Disable interrupts, such as result ready interrupt, overflow interrupt and so on. + * + * @param base FREQME peripheral base address. + * @param masks The mask of interrupts to disable, should be the OR'ed value of @ref _freqme_interrupt_enable. + */ +static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | + FREQME_CTRLSTAT_RESULT_READY_STAT_MASK | masks); + + base->CTRL_W = tmp32; +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_FREQME_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_gpio.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_gpio.c new file mode 100644 index 0000000000..0f3b4020c2 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_gpio.c @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpio" +#endif + +#if defined(GPIO_RSTS) +#define GPIO_RESETS_ARRAY GPIO_RSTS +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(GPIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * @brief Gets the GPIO instance according to the GPIO base + * + * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval GPIO instance + */ +static uint32_t GPIO_GetInstance(GPIO_Type *base); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY) +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} +#endif +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param pin GPIO port pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(NULL != config); + +#if defined(GPIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]); +#endif + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= GPIO_FIT_REG(~(1UL << pin)); + } + else + { + GPIO_PinWrite(base, pin, config->outputLogic); + base->PDDR |= GPIO_FIT_REG((1UL << pin)); + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER +void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info) +{ + info->feature = (uint16_t)base->VERID; + info->minor = (uint8_t)(base->VERID >> GPIO_VERID_MINOR_SHIFT); + info->major = (uint8_t)(base->VERID >> GPIO_VERID_MAJOR_SHIFT); +} +#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = (uint8_t)GPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} +#else +/*! + * brief Read the GPIO interrupt status flags. + * + * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * return The current GPIO's interrupt status flag. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base) +{ + return base->ISFR[0]; +} +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS). + * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + * + * return The current GPIO's interrupt status flag based on the selected interrupt channel. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel) +{ + assert(channel < 2U); + return base->ISFR[channel]; +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */ +/*! + * brief Read individual pin's interrupt status flag. + * + * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on) + * param pin GPIO specific pin number. + * return The current selected pin's interrupt status flag. + */ +uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin) +{ + return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT); +} +#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * brief Clears multiple GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = (uint8_t)GPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#else +/*! + * brief Clears GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISFR[0] = GPIO_FIT_REG(mask); +} +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS). + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + */ +void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel) +{ + assert(channel < 2U); + base->ISFR[channel] = GPIO_FIT_REG(mask); +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */ +/*! + * brief Clear GPIO individual pin's interrupt status flag. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on). + * param pin GPIO specific pin number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin) +{ + base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U)); +} +#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register + * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little + * endian data convention. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param attribute GPIO checker attribute + */ +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) +{ +#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U) + base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT); +#else + base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT); +#endif /* FSL_FEATURE_GPIO_REGISTERS_WIDTH */ +} +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * @brief Gets the FGPIO instance according to the GPIO base + * + * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval FGPIO instance + */ +static uint32_t FGPIO_GetInstance(FGPIO_Type *base); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +static uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++) + { + if (s_fgpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_fgpioBases)); + + return instance; +} +#endif +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param pin FGPIO port pin number + * param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(NULL != config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1UL << pin); + } + else + { + FGPIO_PinWrite(base, pin, config->outputLogic); + base->PDDR |= (1UL << pin); + } +} +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = (uint8_t)FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +/*! + * brief Clears the multiple FGPIO pin interrupt status flag. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = (uint8_t)FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#endif +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param attribute FGPIO checker attribute + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) +{ + base->GACR = ((uint32_t)attribute << FGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << FGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB3_SHIFT); +} +#endif + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_gpio.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_gpio.h new file mode 100644 index 0000000000..ce943c5b69 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_gpio.h @@ -0,0 +1,799 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_GPIO_H_ +#define FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3)) +/*@}*/ + +#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U) +#define GPIO_FIT_REG(value) \ + ((uint8_t)(value)) /*!< For some platforms with 8-bit register width, cast the type to uint8_t */ +#else +#define GPIO_FIT_REG(value) ((uint32_t)(value)) +#endif /*FSL_FEATURE_GPIO_REGISTERS_WIDTH*/ + +/*! @brief GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! @brief GPIO checker attribute */ +typedef enum _gpio_checker_attribute +{ + kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = + 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = + 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = + 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = + 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = + 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = + 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = + 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = + 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ + kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ +} gpio_checker_attribute_t; +#endif + +/*! + * @brief The GPIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, leave the outputConfig unused. + * Note that in some use cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig(). + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations; ignore if configured as an input pin */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \ + !(defined(FSL_FEATURE_SOC_PORT_COUNT)) +/*! @brief Configures the interrupt generation condition. */ +typedef enum _gpio_interrupt_config +{ + kGPIO_InterruptStatusFlagDisabled = 0x0U, /*!< Interrupt status flag is disabled. */ + kGPIO_DMARisingEdge = 0x1U, /*!< ISF flag and DMA request on rising edge. */ + kGPIO_DMAFallingEdge = 0x2U, /*!< ISF flag and DMA request on falling edge. */ + kGPIO_DMAEitherEdge = 0x3U, /*!< ISF flag and DMA request on either edge. */ + kGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ + kGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ + kGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +} gpio_interrupt_config_t; +#endif + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! @brief Configures the selection of interrupt/DMA request/trigger output. */ +typedef enum _gpio_interrupt_selection +{ + kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */ + kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */ +} gpio_interrupt_selection_t; +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */ + +#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER +/*! @brief GPIO version information. */ +typedef struct _gpio_version_info +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor Version Number. */ + uint8_t major; /*!< Major Version Number. */ +} gpio_version_info_t; +#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL +/*! @brief GPIO pin and interrupt control. */ +typedef enum +{ + kGPIO_PinControlNonSecure = 0x01U, /*!< Pin Control Non-Secure. */ + kGPIO_InterruptControlNonSecure = 0x02U, /*!< Interrupt Control Non-Secure. */ + kGPIO_PinControlNonPrivilege = 0x04U, /*!< Pin Control Non-Privilege. */ + kGPIO_InterruptControlNonPrivilege = 0x08U, /*!< Interrupt Control Non-Privilege. */ +} gpio_pin_interrupt_control_t; +#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */ + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO port pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER +/*! + * @brief Get GPIO version information. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param info GPIO version information + */ +void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info); +#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL +/*! + * @brief lock or unlock secure privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask pin or interrupt macro + */ +static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask) +{ + base->LOCK |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Enable Pin Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->PCNS |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Pin Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->PCNS &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Enable Pin Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->PCNP |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Pin Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->PCNP &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Enable Interrupt Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->ICNS |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Interrupt Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->ICNS &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Enable Interrupt Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->ICNP |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Interrupt Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->ICNP &= GPIO_FIT_REG(~mask); +} +#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */ + +#if defined(FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL +/*! + * @brief Enable port input. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask) +{ + base->PIDR &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Disable port input. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask) +{ + base->PIDR |= GPIO_FIT_REG(mask); +} +#endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */ + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + if (output == 0U) + { + base->PCOR = GPIO_FIT_REG(1UL << pin); + } + else + { + base->PSOR = GPIO_FIT_REG(1UL << pin); + } +#else + if (output == 0U) + { + base->PDOR |= GPIO_FIT_REG(1UL << pin); + } + else + { + base->PDOR &= ~GPIO_FIT_REG(1UL << pin); + } +#endif +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + base->PSOR = GPIO_FIT_REG(mask); +#else + base->PDOR |= GPIO_FIT_REG(mask); +#endif +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + base->PCOR = GPIO_FIT_REG(mask); +#else + base->PDOR &= ~GPIO_FIT_REG(mask); +#endif +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + base->PTOR = GPIO_FIT_REG(mask); +#else + base->PDOR ^= GPIO_FIT_REG(mask); +#endif +} + +/*@}*/ + +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + return (((uint32_t)(base->PDIR) >> pin) & 0x01UL); +} + +/*@}*/ + +/*! @name GPIO Interrupt */ +/*@{*/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * @brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base); + +/*! + * @brief Clears multiple GPIO pin interrupt status flags. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask); +#else +/*! + * @brief Configures the gpio pin interrupt/DMA request. + * + * @param base GPIO peripheral base pointer. + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config) +{ + assert(base); + + base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config)); +} + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * @brief Configures the gpio pin interrupt/DMA request/trigger output channel selection. + * + * @param base GPIO peripheral base pointer. + * @param pin GPIO pin number. + * @param selection GPIO pin interrupt output selection. + * - #kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0. + * - #kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1. + */ +static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection) +{ + assert(base); + + base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQS_MASK) | GPIO_ICR_IRQS(selection)); +} +#endif +/*! + * @brief Read the GPIO interrupt status flags. + * + * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * @return The current GPIO's interrupt status flag. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base); +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * @brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS). + * + * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + * @return The current GPIO's interrupt status flag based on the selected interrupt channel. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel); +#endif +/*! + * @brief Read individual pin's interrupt status flag. + * + * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on) + * @param pin GPIO specific pin number. + * @return The current selected pin's interrupt status flag. + */ +uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin); + +/*! + * @brief Clears GPIO pin interrupt status flags. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask); +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * @brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS). + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + */ +void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel); +#endif +/*! + * @brief Clear GPIO individual pin's interrupt status flag. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on). + * @param pin GPIO specific pin number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin); + +/*! + * @brief Reads the GPIO DMA request flags. + * The corresponding flag will be cleared automatically at the completion of the requested + * DMA transfer + */ +static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base) +{ + assert(base); + return (base->ISFR[1]); +} + +/*! + * @brief Sets the GPIO interrupt configuration in PCR register for multiple pins. + * + * @param base GPIO peripheral base pointer. + * @param mask GPIO pin number macro. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config) +{ + assert(base); + + if (0UL != (mask & 0xffffUL)) + { + base->GICLR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU)); + } + mask = mask >> 16U; + if (mask != 0UL) + { + base->GICHR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU)); + } +} +#endif + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register + * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little + * endian data convention. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param attribute GPIO checker attribute + */ +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); +#endif + +/*@}*/ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduces the FGPIO feature. + * + * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT + * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*@{*/ + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * @brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base); +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name FGPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*@}*/ + +/*! @name FGPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the FGPIO port. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @retval FGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*@}*/ + +/*! @name FGPIO Interrupt */ +/*@{*/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); +#endif +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param attribute FGPIO checker attribute + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); +#endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */ + +/*@}*/ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_GPIO_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c.c new file mode 100644 index 0000000000..5862a142ac --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c.c @@ -0,0 +1,3493 @@ +/* + * Copyright 2018-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i3c.h" +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) +#include "fsl_reset.h" +#endif +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i3c" +#endif + +#define I3C_BROADCASE_ADDR (0x7EU) + +#define NSEC_PER_SEC (1000000000UL) +#define FSL_I3C_ERROR_RATE_MAX (10U) +#define FSL_I3C_PPBAUD_DIV_MAX ((I3C_MCONFIG_PPBAUD_MASK >> I3C_MCONFIG_PPBAUD_SHIFT) + 1U) +#define FSL_I3C_ODBAUD_DIV_MAX ((I3C_MCONFIG_ODBAUD_MASK >> I3C_MCONFIG_ODBAUD_SHIFT) + 1U) +#define FSL_I3C_I2CBAUD_DIV_MAX (((I3C_MCONFIG_I2CBAUD_MASK >> I3C_MCONFIG_I2CBAUD_SHIFT) + 1U) / 2U) + +/*! @brief Common sets of flags used by the driver. */ +enum _i3c_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterRxReadyFlag /* | kI3C_MasterTxReadyFlag */ | kI3C_MasterArbitrationWonFlag | + kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag | kI3C_SlaveRxReadyFlag | + kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | + kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | + kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | + kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | + kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i3c_transfer_states +{ + kIdleState = 0, + kIBIWonState, + kSlaveStartState, + kSendCommandState, + kWaitRepeatedStartCompleteState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! + * @brief Used for conversion between `uint8_t*` and `uint32_t`. + */ +typedef union i3c_puint8_to_u32 +{ + uint8_t *puint8; + uint32_t u32; + const uint8_t *cpuint8; +} i3c_puint8_to_u32_t; + +/* + * MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + } + + return result; +} + +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) +{ + status_t result = kStatus_Success; + uint32_t status, errStatus; +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + +#if I3C_RETRY_TIMES + while ((result == kStatus_Success) && (--waitTimes)) +#else + while (result == kStatus_Success) +#endif + { + status = I3C_MasterGetStatusFlags(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + /* Check for error flags. */ + result = I3C_MasterCheckAndClearError(base, errStatus); + /* Check if the control finishes. */ + if (0UL != (status & (uint32_t)kI3C_MasterControlDoneFlag)) + { + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + if (!waitIdle) + { + break; + } + } + /* kI3C_MasterControlDoneFlag only indicates ACK got, need to wait for SDA high. */ + if (waitIdle && I3C_MasterGetState(base) == kI3C_MasterStateIdle) + { + break; + } + } + +#if I3C_RETRY_TIMES + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + + return result; +} + +static status_t I3C_MasterWaitForTxReady(I3C_Type *base, uint8_t byteCounts) +{ + uint32_t errStatus; + status_t result; + size_t txCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + I3C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } +#if I3C_RETRY_TIMES + } while ((txCount < byteCounts) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#else + } while (txCount < byteCounts); +#endif + + return kStatus_Success; +} + +static status_t I3C_MasterWaitForComplete(I3C_Type *base, bool waitIdle) +{ + uint32_t status, errStatus; + status_t result = kStatus_Success; +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + status = I3C_MasterGetStatusFlags(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); +#if I3C_RETRY_TIMES + } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && + (result == kStatus_Success) && --waitTimes); +#else + } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && + (result == kStatus_Success)); +#endif + + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); + +#if I3C_RETRY_TIMES + if (waitTimes == 0UL) + { + return kStatus_I3C_Timeout; + } +#endif + + if (waitIdle) + { +#if I3C_RETRY_TIMES + while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) +#else + while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) +#endif + { + } + } + + return result; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The I3C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_I3C_OverrunError + * @retval #kStatus_I3C_UnderrunError + * @retval #kStatus_I3C_UnderrunNak + * @retval #kStatus_I3C_Term + * @retval #kStatus_I3C_InvalidStart + * @retval #kStatus_I3C_SdrParityError + * @retval #kStatus_I3C_HdrParityError + * @retval #kStatus_I3C_CrcError + * @retval #kStatus_I3C_S0S1Error + * @retval #kStatus_I3C_ReadFifoError + * @retval #kStatus_I3C_WriteFifoError + */ +status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kSlaveErrorFlags; + +#if defined(I3C_DMA_IGNORE_FIFO_ERROR) + status &= ~((uint32_t)kI3C_SlaveErrorUnderrunFlag | (uint32_t)kI3C_SlaveErrorOverwriteFlag); + I3C_SlaveClearErrorStatusFlags(base, + ((uint32_t)kI3C_SlaveErrorUnderrunFlag | (uint32_t)kI3C_SlaveErrorOverwriteFlag)); +#endif + + if (0UL != status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverrunFlag)) + { + result = kStatus_I3C_OverrunError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunFlag)) + { + result = kStatus_I3C_UnderrunError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunNakFlag)) + { + result = kStatus_I3C_UnderrunNak; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorTermFlag)) + { + result = kStatus_I3C_Term; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorInvalidStartFlag)) + { + result = kStatus_I3C_InvalidStart; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorSdrParityFlag)) + { + result = kStatus_I3C_SdrParityError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrParityFlag)) + { + result = kStatus_I3C_HdrParityError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrCRCFlag)) + { + result = kStatus_I3C_CrcError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorS0S1Flag)) + { + result = kStatus_I3C_S0S1Error; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverreadFlag)) + { + result = kStatus_I3C_ReadFifoError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverwriteFlag)) + { + result = kStatus_I3C_WriteFifoError; + } + else + { + assert(false); + } + + /* Clear the flags. */ + I3C_SlaveClearErrorStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + } + + return result; +} + +static status_t I3C_SlaveWaitForTxReady(I3C_Type *base) +{ + uint32_t errStatus; + status_t result; + size_t txCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + I3C_SlaveGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + errStatus = I3C_SlaveGetErrorStatusFlags(base); + result = I3C_SlaveCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } +#if I3C_RETRY_TIMES + } while ((txCount == 0UL) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#else + } while (txCount == 0UL); +#endif + + return kStatus_Success; +} + +static status_t I3C_MasterEmitStop(I3C_Type *base, bool waitIdle) +{ + status_t result = kStatus_Success; + + /* Return an error if the bus is not in transaction. */ + if (I3C_MasterGetState(base) != kI3C_MasterStateNormAct) + { + return kStatus_I3C_InvalidReq; + } + + /* Send the STOP signal */ + base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) | + I3C_MCTRL_REQUEST(kI3C_RequestEmitStop); + + /* Wait for the stop operation finishes. */ + /* Also check for errors while waiting. */ + result = I3C_MasterWaitForCtrlDone(base, waitIdle); + + return result; +} + +/*! + * brief I3C master get IBI Type. + * + * param base The I3C peripheral base address. + * param i3c_ibi_type_t Type of #i3c_ibi_type_t. + */ +i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base) +{ + uint32_t ibiValue = (base->MSTATUS & I3C_MSTATUS_IBITYPE_MASK) >> I3C_MSTATUS_IBITYPE_SHIFT; + i3c_ibi_type_t ibiType = kI3C_IbiNormal; + + switch (ibiValue) + { + case 3L: + ibiType = kI3C_IbiHotJoin; + break; + case 2L: + ibiType = kI3C_IbiMasterRequest; + break; + default: + ibiType = kI3C_IbiNormal; + break; + } + + return ibiType; +} + +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The I3C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_I3C_Busy + */ +/* Not static so it can be used from fsl_i3c_edma.c. */ +status_t I3C_CheckForBusyBus(I3C_Type *base) +{ + return (I3C_MasterGetBusIdleState(base) == true) ? kStatus_Success : kStatus_I3C_Busy; +} + +/* brief Provides a default configuration for the I3C peripheral. + * + */ +void I3C_GetDefaultConfig(i3c_config_t *config) +{ + assert(NULL != config); + + (void)memset(config, 0, sizeof(*config)); + + config->enableMaster = kI3C_MasterCapable; + config->disableTimeout = false; + config->hKeep = kI3C_MasterHighKeeperNone; + config->enableOpenDrainStop = true; + config->enableOpenDrainHigh = true; + config->baudRate_Hz.i2cBaud = 400000U; + config->baudRate_Hz.i3cPushPullBaud = 12500000U; + config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; + config->masterDynamicAddress = 0x0AU; /* Default master dynamic address. */ + config->slowClock_Hz = 1000000U; /* Default slow timer clock 1MHz. */ + config->enableSlave = true; + config->vendorID = 0x11BU; +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + config->enableRandomPart = false; +#endif + config->partNumber = 0; + config->dcr = 0; /* Generic device. */ + config->bcr = 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR + Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, + device is offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI + Request Capable, capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ + config->hdrMode = (uint8_t)kI3C_HDRModeDDR; + config->nakAllRequest = false; + config->ignoreS0S1Error = false; + config->offline = false; + config->matchSlaveStartStop = false; + config->maxWriteLength = 256U; + config->maxReadLength = 256U; +} + +/*! + * @brief Initializes the I3C peripheral. + * + */ +void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz) +{ + uint32_t instance = I3C_GetInstance(base); + uint32_t configValue; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + + if ((config->masterDynamicAddress != 0U) && (config->enableMaster == kI3C_MasterOn)) + { + base->MDYNADDR &= ~I3C_MDYNADDR_DADDR_MASK; + base->MDYNADDR |= I3C_MDYNADDR_DADDR(config->masterDynamicAddress) | I3C_MDYNADDR_DAVALID_MASK; + } + + base->MCONFIG = I3C_MCONFIG_MSTENA(config->enableMaster) | I3C_MCONFIG_DISTO(config->disableTimeout) | + I3C_MCONFIG_HKEEP(config->hKeep) | I3C_MCONFIG_ODSTOP(config->enableOpenDrainStop) | + I3C_MCONFIG_ODHPP(config->enableOpenDrainHigh); + + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); + + I3C_MasterSetBaudRate(base, &config->baudRate_Hz, sourceClock_Hz); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + uint8_t matchCount; + /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ + matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL); +#endif + + configValue = base->SCONFIG; + + configValue &= + ~(I3C_SCONFIG_SADDR_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH_MASK | +#endif + I3C_SCONFIG_OFFLINE_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND_MASK | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK_MASK | +#else + I3C_SCONFIG_DDROK_MASK | +#endif + I3C_SCONFIG_S0IGNORE_MASK | I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); + + configValue |= I3C_SCONFIG_SADDR(config->staticAddr) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH(matchCount) | +#endif + I3C_SCONFIG_OFFLINE(config->offline) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND(config->enableRandomPart) | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK((0U != (config->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#else + I3C_SCONFIG_DDROK((0U != (config->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#endif + I3C_SCONFIG_S0IGNORE(config->ignoreS0S1Error) | I3C_SCONFIG_MATCHSS(config->matchSlaveStartStop) | + I3C_SCONFIG_NACK(config->nakAllRequest) | I3C_SCONFIG_SLVENA(config->enableSlave); + + base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; + base->SVENDORID |= I3C_SVENDORID_VID(config->vendorID); + +#if defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND + base->SIDPARTNO = config->partNumber; +#else + if (!config->enableRandomPart) + { + base->SIDPARTNO = config->partNumber; + } +#endif + + base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); + base->SIDEXT |= I3C_SIDEXT_BCR(config->bcr) | I3C_SIDEXT_DCR(config->dcr); + + base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); + base->SMAXLIMITS |= (I3C_SMAXLIMITS_MAXRD(config->maxReadLength) | I3C_SMAXLIMITS_MAXWR(config->maxWriteLength)); + + base->SCONFIG = configValue; +} + +/*! + * brief Provides a default configuration for the I3C master peripheral. + * + * This function provides the following default configuration for the I3C master peripheral: + * code + * masterConfig->enableMaster = kI3C_MasterOn; + * masterConfig->disableTimeout = false; + * masterConfig->hKeep = kI3C_MasterHighKeeperNone; + * masterConfig->enableOpenDrainStop = true; + * masterConfig->enableOpenDrainHigh = true; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busType = kI3C_TypeI2C; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I3C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. + */ +void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig) +{ + masterConfig->enableMaster = kI3C_MasterOn; + masterConfig->disableTimeout = false; + masterConfig->hKeep = kI3C_MasterHighKeeperNone; + masterConfig->enableOpenDrainStop = true; + masterConfig->enableOpenDrainHigh = true; + masterConfig->baudRate_Hz.i2cBaud = 400000U; + masterConfig->baudRate_Hz.i3cPushPullBaud = 12500000U; + masterConfig->baudRate_Hz.i3cOpenDrainBaud = 2500000U; +} + +/*! + * brief Initializes the I3C master peripheral. + * + * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I3C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of + * defaults that you can override. + * param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ + uint32_t instance = I3C_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + base->MCONFIG = I3C_MCONFIG_MSTENA(masterConfig->enableMaster) | I3C_MCONFIG_DISTO(masterConfig->disableTimeout) | + I3C_MCONFIG_HKEEP(masterConfig->hKeep) | I3C_MCONFIG_ODSTOP(masterConfig->enableOpenDrainStop) | + I3C_MCONFIG_ODHPP(masterConfig->enableOpenDrainHigh); + + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); + + I3C_MasterSetBaudRate(base, &masterConfig->baudRate_Hz, sourceClock_Hz); +} + +/*! + * @brief Gets the I3C master state. + * + * @param base The I3C peripheral base address. + * @return I3C master state. + */ +i3c_master_state_t I3C_MasterGetState(I3C_Type *base) +{ + uint32_t masterState = (base->MSTATUS & I3C_MSTATUS_STATE_MASK) >> I3C_MSTATUS_STATE_SHIFT; + i3c_master_state_t returnCode; + + switch (masterState) + { + case (uint32_t)kI3C_MasterStateIdle: + returnCode = kI3C_MasterStateIdle; + break; + case (uint32_t)kI3C_MasterStateSlvReq: + returnCode = kI3C_MasterStateSlvReq; + break; + case (uint32_t)kI3C_MasterStateMsgSdr: + returnCode = kI3C_MasterStateMsgSdr; + break; + case (uint32_t)kI3C_MasterStateNormAct: + returnCode = kI3C_MasterStateNormAct; + break; + case (uint32_t)kI3C_MasterStateDdr: + returnCode = kI3C_MasterStateDdr; + break; + case (uint32_t)kI3C_MasterStateDaa: + returnCode = kI3C_MasterStateDaa; + break; + case (uint32_t)kI3C_MasterStateIbiAck: + returnCode = kI3C_MasterStateIbiAck; + break; + case (uint32_t)kI3C_MasterStateIbiRcv: + returnCode = kI3C_MasterStateIbiRcv; + break; + default: + returnCode = kI3C_MasterStateIdle; + break; + } + + return returnCode; +} + +/*! + * brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I3C peripheral base address. + */ +void I3C_MasterDeinit(I3C_Type *base) +{ + uint32_t idx = I3C_GetInstance(base); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[idx]); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + CLOCK_DisableClock(kI3cClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset handle pointer. */ + s_i3cMasterHandle[idx] = NULL; +} + +static uint32_t I3C_CalcErrorRatio(uint32_t curFreq, uint32_t desiredFreq) +{ + if (curFreq > desiredFreq) + { + return (curFreq - desiredFreq) * 100UL / desiredFreq; + } + else + { + return (desiredFreq - curFreq) * 100UL / desiredFreq; + } +} + +/*! + * brief Sets the I3C bus frequency for master transactions. + * + * The I3C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I3C peripheral base address. + * param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. + * param sourceClock_Hz I3C functional clock frequency in Hertz. + */ +void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz) +{ + uint32_t div, freq; + uint32_t divEven, divOdd; + uint32_t ppBaud, odBaud, i2cBaud; + uint32_t errRate0, errRate1; + uint32_t i3cPPBaud_HZ = baudRate_Hz->i3cPushPullBaud; + uint32_t i3cPPBaudMax_HZ = i3cPPBaud_HZ / 10U + i3cPPBaud_HZ; /* max is 1.1*i3cPPBaud_HZ */ + uint32_t i3cODBaud_HZ = baudRate_Hz->i3cOpenDrainBaud; + uint32_t i3cODBaudMax_HZ = i3cODBaud_HZ / 10U + i3cODBaud_HZ; /* max is 1.1*i3cODBaud_HZ */ + uint32_t i2cBaud_HZ = baudRate_Hz->i2cBaud; + uint32_t i3cPPLow_Ns, i3cOdLow_Ns; + bool isODHigh = (0U != (base->MCONFIG & I3C_MCONFIG_ODHPP_MASK)) ? true : false; + + /* Find out the div to generate target freq */ + freq = sourceClock_Hz / 2UL; + /* ppFreq = FCLK / 2 / (PPBAUD + 1)), 0 <= PPBAUD <= 15 */ + /* We need PPBAUD generate 12.5MHz or so. */ + div = freq / i3cPPBaud_HZ; + div = (div == 0UL) ? 1UL : div; + if (freq / div > i3cPPBaudMax_HZ) + { + div++; + } + assert(div <= FSL_I3C_PPBAUD_DIV_MAX); + ppBaud = div - 1UL; + freq /= div; + + i3cPPLow_Ns = (uint32_t)(NSEC_PER_SEC / (2UL * freq)); + + /* We need ODBAUD generate 2.5MHz or so. */ + if (isODHigh) + { + /* odFreq = (2*freq) / (ODBAUD + 2), 1 <= ODBAUD <= 255 */ + div = (2UL * freq) / i3cODBaud_HZ; + div = div < 2UL ? 2UL : div; + if ((2UL * freq / div) > i3cODBaudMax_HZ) + { + div++; + } + odBaud = div - 2UL; + freq = (2UL * freq) / div; + } + else + { + /* odFreq = ppFreq / (ODBAUD + 1), 1 <= ODBAUD <= 255 */ + div = freq / i3cODBaud_HZ; + div = div < 1UL ? 1UL : div; + if (freq / div > i3cODBaudMax_HZ) + { + div++; + } + odBaud = div - 1UL; + freq /= div; + } + + i3cOdLow_Ns = (odBaud + 1UL) * i3cPPLow_Ns; + + /* i2cFreq = odFreq / (I2CBAUD + 1), 0 <= I2CBAUD <= 7 (I2CBAUD need << 1 in register) */ + /* i2cFreq = NSEC_PER_SEC / (I2CBAUD + 1)*i3cOdLow_Ns */ + divEven = (sourceClock_Hz / i2cBaud_HZ) / (2UL * (ppBaud + 1UL) * (odBaud + 1UL)); + divEven = divEven == 0UL ? 1UL : divEven; + errRate0 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / (2UL * divEven * i3cOdLow_Ns)), i2cBaud_HZ); + + divOdd = ((sourceClock_Hz / i2cBaud_HZ) / ((ppBaud + 1UL) * (odBaud + 1UL) - 1UL)) / 2UL; + divOdd = divOdd == 0UL ? 1UL : divOdd; + errRate1 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / ((2UL * divOdd + 1UL) * i3cOdLow_Ns)), i2cBaud_HZ); + + if (errRate0 < FSL_I3C_ERROR_RATE_MAX || errRate1 < FSL_I3C_ERROR_RATE_MAX) + { + /* Use this div */ + i2cBaud = errRate0 < errRate1 ? (divEven - 1UL) * 2UL : (divOdd - 1UL) * 2UL + 1UL; + } + else + { + /* Use div + 1, unless current freq is already lower than desired. */ + i2cBaud = freq / divEven < i2cBaud_HZ ? (divEven - 1UL) * 2UL : divEven * 2UL; + } + + base->MCONFIG = (base->MCONFIG & ~(I3C_MCONFIG_PPBAUD_MASK | I3C_MCONFIG_PPLOW_MASK | I3C_MCONFIG_ODBAUD_MASK | + I3C_MCONFIG_I2CBAUD_MASK)) | + I3C_MCONFIG_PPBAUD(ppBaud) | I3C_MCONFIG_ODBAUD(odBaud) | I3C_MCONFIG_I2CBAUD(i2cBaud); +} + +/*! + * brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize) +{ + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, rxSize); +} + +/*! + * brief Sends a START signal and slave address on the I2C/I3C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir) +{ + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + return I3C_MasterStartWithRxSize(base, type, address, dir, 0); +} + +/*! + * brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read + * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer + * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize + * configuration. + * + * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize) +{ + uint32_t mctrlVal; + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_051617) && (FSL_FEATURE_I3C_HAS_ERRATA_051617) + /* ERRATA051617: When used as I2C controller generates repeated START randomly before the STOP under PVT condition. + This issue is caused by a glitch at the output of an internal clock MUX. The glitch when generates acts as a clock + pulse which causes the SDA line to fall early during SCL high period and creates the unintended Repeated START before + actual STOP. */ + if (type == kI3C_TypeI2C) + { + base->MCONFIG |= I3C_MCONFIG_SKEW(1); + } + else + { + base->MCONFIG &= ~I3C_MCONFIG_SKEW_MASK; + } +#endif + + /* Issue start command. */ + mctrlVal = base->MCTRL; + mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | + I3C_MCTRL_RDTERM_MASK); + mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) | + I3C_MCTRL_ADDR(address) | I3C_MCTRL_RDTERM(rxSize); + + base->MCTRL = mctrlVal; + + return kStatus_Success; +} +/*! + * brief Sends a STOP signal on the I2C/I3C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The I3C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterStop(I3C_Type *base) +{ + return I3C_MasterEmitStop(base, true); +} + +/*! + * brief I3C master emit request. + * + * param base The I3C peripheral base address. + * param masterReq I3C master request of type #i3c_bus_request_t + */ +void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq) +{ + uint32_t mctrlReg = base->MCTRL; + + mctrlReg &= ~I3C_MCTRL_REQUEST_MASK; + + if (masterReq == kI3C_RequestProcessDAA) + { + mctrlReg &= ~I3C_MCTRL_TYPE_MASK; + } + + mctrlReg |= I3C_MCTRL_REQUEST(masterReq); + + base->MCTRL = mctrlReg; +} + +/*! + * brief I3C master register IBI rule. + * + * param base The I3C peripheral base address. + * param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t + */ +void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) +{ + assert(NULL != ibiRule); + uint32_t ruleValue = I3C_MIBIRULES_MSB0_MASK; + + for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) + { + ruleValue |= ((uint32_t)ibiRule->address[count]) << (count * I3C_MIBIRULES_ADDR1_SHIFT); + } + + ruleValue &= ~I3C_MIBIRULES_NOBYTE_MASK; + + if (!ibiRule->ibiHasPayload) + { + ruleValue |= I3C_MIBIRULES_NOBYTE_MASK; + } + + base->MIBIRULES = ruleValue; +} + +/*! + * brief I3C master get IBI rule. + * + * param base The I3C peripheral base address. + * param ibiRule Pointer to store the read out ibi rule description. + */ +void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) +{ + assert(NULL != ibiRule); + + uint32_t ruleValue = base->MIBIRULES; + + for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) + { + ibiRule->address[count] = + (uint8_t)(ruleValue >> (count * I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK; + } + + ibiRule->ibiHasPayload = (0U == (ruleValue & I3C_MIBIRULES_NOBYTE_MASK)); +} + +/*! + * brief Performs a polling receive transfer on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + bool isRxAutoTerm = ((flags & (uint32_t)kI3C_TransferRxAutoTermFlag) != 0UL); + bool completed = false; + uint32_t status; + uint8_t *buf; + + assert(NULL != rxBuff); + + /* Handle empty read. */ + if (rxSize == 0UL) + { + return kStatus_Success; + } + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + + while ((rxSize != 0UL) || !completed) + { +#if I3C_RETRY_TIMES + if (--waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + /* Check for errors. */ + result = I3C_MasterCheckAndClearError(base, I3C_MasterGetErrorStatusFlags(base)); + if (kStatus_Success != result) + { + return result; + } + + /* Check complete flag */ + if (!completed) + { + status = I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterCompleteFlag; + if (0UL != status) + { + completed = true; + /* Clear complete flag */ + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); + /* Send stop if needed */ + if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { + if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); + } + else + { + result = I3C_MasterEmitStop(base, false); + } + if (kStatus_Success != result) + { + return result; + } + } + } + } + + /* Check RX data */ + if ((0UL != rxSize) && (0UL != (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK))) + { + *buf++ = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); + rxSize--; + if ((flags & (uint32_t)kI3C_TransferDisableRxTermFlag) == 0UL) + { + if ((!isRxAutoTerm) && (rxSize == 1U)) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1U); + } + } + } + } + + /* Wait idle if stop is sent. */ + if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { +#if I3C_RETRY_TIMES + while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) +#else + while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) +#endif + { + } + } + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C/I3C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I3C_Nak. + * + * param base The I3C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or over run. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + i3c_puint8_to_u32_t buf; + buf.cpuint8 = (const uint8_t *)((const void *)txBuff); + status_t result = kStatus_Success; + bool enableWord = ((flags & (uint32_t)kI3C_TransferWordsFlag) == (uint32_t)kI3C_TransferWordsFlag) ? true : false; + uint8_t byteCounts = enableWord ? 2U : 1U; + + assert(NULL != txBuff); + if (enableWord) + { + assert(txSize % 2UL == 0UL); + } + + /* Send data buffer */ + while (0UL != txSize) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = I3C_MasterWaitForTxReady(base, byteCounts); + if (kStatus_Success != result) + { + return result; + } + + /* Write byte into I3C master data register. */ + if (txSize > byteCounts) + { + if (enableWord) + { + base->MWDATAH = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; + } + else + { + base->MWDATAB = *buf.cpuint8; + } + } + else + { + if (enableWord) + { + base->MWDATAHE = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; + } + else + { + base->MWDATABE = *buf.cpuint8; + } + } + + buf.u32 = buf.u32 + byteCounts; + txSize = txSize - byteCounts; + } + + result = I3C_MasterWaitForComplete(base, false); + if ((result == kStatus_Success) && ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL)) + { + if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); + } + else + { + result = I3C_MasterEmitStop(base, true); + } + } + + return result; +} + +/*! + * brief Performs a DAA in the i3c bus with specified temporary baud rate. + * + * param base The I3C peripheral base address. + * param addressList The pointer for address list which is used to do DAA. + * param count The address count in the address list. + * param daaBaudRate The temporary baud rate in DAA process, NULL for using initial setting. + * The initial setting is set back between the completion of the DAA and the return of this function. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + * retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. + */ +status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, + uint8_t *addressList, + uint32_t count, + i3c_master_daa_baudrate_t *daaBaudRate) +{ + assert(addressList != NULL); + assert(count != 0U); + + status_t result = kStatus_Success; + uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; + uint32_t masterConfig = 0; + uint32_t devCount = 0; + uint8_t rxSize = 0; + bool mctrlDone = false; + i3c_baudrate_hz_t baudRate_Hz; + uint32_t errStatus; + uint32_t status; + size_t rxCount; + + /* Return an error if the bus is already in use not by us. */ + result = I3C_CheckForBusyBus(base); + if (kStatus_Success != result) + { + return result; + } + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Disable I3C IRQ sources while we configure stuff. */ + uint32_t enabledInts = I3C_MasterGetEnabledInterrupts(base); + I3C_MasterDisableInterrupts(base, enabledInts); + + /* Temporarily adjust baud rate before DAA. */ + if (daaBaudRate != NULL) + { + masterConfig = base->MCONFIG; + /* Set non-zero value for I2C baud rate which is useless here. */ + baudRate_Hz.i2cBaud = 1; + baudRate_Hz.i3cOpenDrainBaud = daaBaudRate->i3cOpenDrainBaud; + baudRate_Hz.i3cPushPullBaud = daaBaudRate->i3cPushPullBaud; + I3C_MasterSetBaudRate(base, &baudRate_Hz, daaBaudRate->sourceClock_Hz); + } + + /* Emit process DAA */ + I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + + do + { + status = I3C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + break; + } + + if ((!mctrlDone) || (rxSize < 8U)) + { + I3C_MasterGetFifoCounts(base, &rxCount, NULL); + + if ((0UL != (status & (uint32_t)kI3C_MasterRxReadyFlag)) && (rxCount != 0U)) + { + rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); + } + + if ((status & (uint32_t)kI3C_MasterControlDoneFlag) != 0U) + { + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + mctrlDone = true; + } + } + else if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && + (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag))) + { + if (((devCount + 1UL) > count) || ((devCount + 1UL) > I3C_MAX_DEVCNT)) + { + result = kStatus_I3C_SlaveCountExceed; + break; + } + + /* Assign the dynamic address from address list. */ + devList[devCount].dynamicAddr = *addressList++; + base->MWDATAB = devList[devCount].dynamicAddr; + + /* Emit process DAA again. */ + I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + + devList[devCount].vendorID = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U; + devList[devCount].partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U | + (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]); + devList[devCount].bcr = rxBuffer[6]; + devList[devCount].dcr = rxBuffer[7]; + devCount++; + usedDevCount++; + + /* Ready to handle next device. */ + mctrlDone = false; + rxSize = 0; + } + else + { + /* Intentional empty */ + } + } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag); + + /* Master stops DAA if slave device number exceeds the prepared address number. */ + if (result == kStatus_I3C_SlaveCountExceed) + { + /* Send the STOP signal */ + base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) | + I3C_MCTRL_REQUEST(kI3C_RequestEmitStop); + } + + /* Set back initial baud rate after DAA is over. */ + if (daaBaudRate != NULL) + { + base->MCONFIG = masterConfig; + } + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Enable I3C IRQ sources while we configure stuff. */ + I3C_MasterEnableInterrupts(base, enabledInts); + + return result; +} + +/*! + * brief Get device information list after DAA process is done. + * + * param base The I3C peripheral base address. + * param[out] count The pointer to store the available device count. + * return Pointer to the i3c_device_info_t array. + */ +i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count) +{ + assert(NULL != count); + + *count = usedDevCount; + + return devList; +} + +/*! + * @brief introduce function I3C_MasterClearFlagsAndEnableIRQ. + * + * This function was used of Clear all flags and Enable I3C IRQ sources for @param *base. + * + * @param base The I3C peripheral base address. + */ +static void I3C_MasterClearFlagsAndEnableIRQ(I3C_Type *base) +{ + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Enable I3C IRQ sources. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); +} + +/*! + * @brief introduce function I3C_MasterTransferNoStartFlag. + * + * This function was used of Check if device request wins arbitration. + * + * @param base The I3C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #true if the device wins arbitration. + * @retval #false if the device not wins arbitration. + */ +static bool I3C_MasterTransferNoStartFlag(I3C_Type *base, i3c_master_transfer_t *transfer) +{ + /* Wait tx fifo empty. */ + size_t txCount = 0xFFUL; + + while (txCount != 0U) + { + I3C_MasterGetFifoCounts(base, NULL, &txCount); + } + + /* Check if device request wins arbitration. */ + if (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterArbitrationWonFlag)) + { + I3C_MasterClearFlagsAndEnableIRQ(base); + return true; + } + return false; +} + +/*! + * brief Performs a master polling transfer on the I2C/I3C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The I3C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer) +{ + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result = kStatus_Success; + i3c_direction_t direction = transfer->direction; + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + i3c_rx_term_ops_t rxTermOps; + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + if (transfer->busType != kI3C_TypeI3CDdr) + { + direction = (0UL != transfer->subaddressSize) ? kI3C_Write : transfer->direction; + } + + /* True: Set Rx termination bytes at start point, False: Set Rx termination one bytes in advance. */ + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + rxTermOps = kI3C_RxAutoTerm; + } + else + { + rxTermOps = kI3C_RxTermLastByte; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, transfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + if ((direction == kI3C_Read) && (rxTermOps == kI3C_RxAutoTerm)) + { + result = I3C_MasterStartWithRxSize(base, transfer->busType, transfer->slaveAddress, direction, + (uint8_t)transfer->dataSize); + } + else + { + result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction); + } + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + + if (true == I3C_MasterTransferNoStartFlag(base, transfer)) + { + return kStatus_I3C_IBIWon; + } + } + else + { + if ((direction == kI3C_Read) && (rxTermOps != kI3C_RxTermDisable)) + { + /* Can't set Rx termination more than one bytes in advance without START. */ + rxTermOps = kI3C_RxTermLastByte; + } + } + + /* Subaddress, MSB first. */ + if (0U != transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (0UL != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8UL * subaddressRemaining)) & 0xFFUL); + + result = I3C_MasterWaitForTxReady(base, 1U); + + if ((0UL == subaddressRemaining) && ((transfer->direction == kI3C_Read) || (0UL == transfer->dataSize)) && + (transfer->busType != kI3C_TypeI3CDdr)) + { + base->MWDATABE = subaddressByte; + result = I3C_MasterWaitForComplete(base, false); + if (kStatus_Success != result) + { + if (result == kStatus_I3C_Nak) + { + (void)I3C_MasterEmitStop(base, true); + } + I3C_MasterClearFlagsAndEnableIRQ(base); + return result; + } + } + else + { + base->MWDATAB = subaddressByte; + } + } + /* Need to send repeated start if switching directions to read. */ + if ((transfer->busType != kI3C_TypeI3CDdr) && (0UL != transfer->dataSize) && (transfer->direction == kI3C_Read)) + { + if (rxTermOps == kI3C_RxAutoTerm) + { + result = I3C_MasterRepeatedStartWithRxSize(base, transfer->busType, transfer->slaveAddress, kI3C_Read, + (uint8_t)transfer->dataSize); + } + else + { + result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read); + } + + if (kStatus_Success != result) + { + I3C_MasterClearFlagsAndEnableIRQ(base); + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + } + + if (rxTermOps == kI3C_RxAutoTerm) + { + transfer->flags |= (uint32_t)kI3C_TransferRxAutoTermFlag; + } + else + { + transfer->flags &= ~(uint32_t)kI3C_TransferRxAutoTermFlag; + } + + /* Transmit data. */ + if ((transfer->direction == kI3C_Write) && (transfer->dataSize > 0UL)) + { + /* Send Data. */ + result = I3C_MasterSend(base, transfer->data, transfer->dataSize, transfer->flags); + } + /* Receive Data. */ + else if ((transfer->direction == kI3C_Read) && (transfer->dataSize > 0UL)) + { + result = I3C_MasterReceive(base, transfer->data, transfer->dataSize, transfer->flags); + } + else + { + if ((transfer->flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { + result = I3C_MasterEmitStop(base, true); + } + } + + if (result == kStatus_I3C_Nak) + { + (void)I3C_MasterEmitStop(base, true); + } + + I3C_MasterClearFlagsAndEnableIRQ(base); + + return result; +} + +/*! + * brief Creates a new handle for the I3C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The I3C peripheral base address. + * param[out] handle Pointer to the I3C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I3C_MasterTransferCreateHandle(I3C_Type *base, + i3c_master_handle_t *handle, + const i3c_master_transfer_callback_t *callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = *callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cMasterIsr = I3C_MasterTransferHandleIRQ; + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); +} + +static void I3C_TransferStateMachineIBIWonState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + if (stateParams->masterState == kI3C_MasterStateIbiAck) + { + handle->ibiType = I3C_GetIBIType(base); + if (handle->callback.ibiCallback != NULL) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); + } + else + { + I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); + } + } + + /* Make sure there is data in the rx fifo. */ + if (0UL != stateParams->rxCount) + { + if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); + } + uint8_t tempData = (uint8_t)base->MRDATAB; + if (handle->ibiBuff != NULL) + { + handle->ibiBuff[handle->ibiPayloadSize++] = tempData; + } + (stateParams->rxCount)--; + return; + } + else if (0UL != (stateParams->status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->ibiType = I3C_GetIBIType(base); + handle->ibiAddress = I3C_GetIBIAddress(base); + stateParams->state_complete = true; + stateParams->result = kStatus_I3C_IBIWon; + } + else + { + stateParams->state_complete = true; + } +} + +static void I3C_TransferStateMachineSendCommandState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + /* Make sure there is room in the tx fifo for the next command. */ + if (0UL == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + if (handle->transfer.subaddressSize > 1U) + { + handle->transfer.subaddressSize--; + base->MWDATAB = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + } + else if (handle->transfer.subaddressSize == 1U) + { + handle->transfer.subaddressSize--; + + if ((handle->transfer.direction == kI3C_Read) || (0UL == handle->transfer.dataSize)) + { + base->MWDATABE = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + + if (handle->transfer.busType != kI3C_TypeI3CDdr) + { + if (0UL == handle->transfer.dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } + } + else + { + handle->state = (uint8_t)kTransferDataState; + } + } + else + { + /* Next state, transfer data. */ + handle->state = (uint8_t)kTransferDataState; + base->MWDATAB = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + } + } + else + { + /* Eliminate misra 15.7*/ + } +} + +static void I3C_TransferStateMachineWaitRepeatedStartCompleteState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + /* We stay in this state until the master complete. */ + if (0UL != (stateParams->status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kTransferDataState; + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + + if (handle->remainingBytes < 256U) + { + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; + stateParams->result = + I3C_MasterRepeatedStartWithRxSize(base, handle->transfer.busType, handle->transfer.slaveAddress, + kI3C_Read, (uint8_t)handle->remainingBytes); + } + else + { + stateParams->result = + I3C_MasterRepeatedStart(base, handle->transfer.busType, handle->transfer.slaveAddress, kI3C_Read); + } + } + + stateParams->state_complete = true; +} + +static void I3C_TransferStateMachineTransferDataState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + + i3c_puint8_to_u32_t dataBuff; + if (handle->transfer.direction == kI3C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (0UL == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + + /* Put byte to send in fifo. */ + dataBuff.puint8 = (uint8_t *)handle->transfer.data; + if (handle->transfer.dataSize > 1U) + { + base->MWDATAB = *dataBuff.puint8; + } + else + { + base->MWDATABE = *dataBuff.puint8; + } + dataBuff.u32 = dataBuff.u32 + 1U; + (handle->transfer.dataSize)--; + handle->transfer.data = (void *)(dataBuff.puint8); + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0UL) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + } + else + { + /* Make sure there is data in the rx fifo. */ + if (0UL == (stateParams->rxCount)--) + { + stateParams->state_complete = true; + return; + } + + /* Read byte from fifo. */ + dataBuff.puint8 = (uint8_t *)handle->transfer.data; + *dataBuff.puint8 = (uint8_t)base->MRDATAB; + dataBuff.u32 = dataBuff.u32 + 1U; + handle->transfer.data = (void *)(dataBuff.puint8); + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0UL) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + + if ((handle->rxTermOps == kI3C_RxTermLastByte) && (handle->remainingBytes == 1UL)) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1UL); + } + } +} + +static void I3C_TransferStateMachineWaitForCompletionState(i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + /* We stay in this state until the maste complete. */ + if (0UL != (stateParams->status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kStopState; + } + else + { + stateParams->state_complete = true; + } +} + +static void I3C_TransferStateMachineStopState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + /* Only issue a stop transition if the caller requested it. */ + if (0UL == (handle->transfer.flags & (uint32_t)kI3C_TransferNoStopFlag)) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (0UL == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + if (handle->transfer.busType == kI3C_TypeI3CDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + (void)I3C_MasterEmitStop(base, false); + } + } + stateParams->state_complete = true; +} + +static status_t I3C_RunTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle, bool *isDone) +{ + i3c_master_state_machine_param_t stateParams; + (void)memset(&stateParams, 0, sizeof(stateParams)); + + stateParams.result = kStatus_Success; + stateParams.state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + uint32_t errStatus; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + + /* Check for errors. */ + stateParams.status = (uint32_t)I3C_MasterGetPendingInterrupts(base); + I3C_MasterClearStatusFlags(base, stateParams.status); + + stateParams.masterState = I3C_MasterGetState(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + stateParams.result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != stateParams.result) + { + return stateParams.result; + } + + if (0UL != (stateParams.status & (uint32_t)kI3C_MasterSlave2MasterFlag)) + { + if (handle->callback.slave2Master != NULL) + { + handle->callback.slave2Master(base, handle->userData); + } + } + + if ((0UL != (stateParams.status & (uint32_t)kI3C_MasterSlaveStartFlag)) && + (handle->transfer.busType != kI3C_TypeI2C)) + { + handle->state = (uint8_t)kSlaveStartState; + } + + if ((stateParams.masterState == kI3C_MasterStateIbiRcv) || (stateParams.masterState == kI3C_MasterStateIbiAck)) + { + handle->state = (uint8_t)kIBIWonState; + } + + if (handle->state == (uint8_t)kIdleState) + { + return stateParams.result; + } + + /* Get fifo counts and compute room in tx fifo. */ + I3C_MasterGetFifoCounts(base, &stateParams.rxCount, &stateParams.txCount); + stateParams.txCount = txFifoSize - stateParams.txCount; + + while (!stateParams.state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSlaveStartState: + /* Emit start + 0x7E */ + I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); + handle->state = (uint8_t)kIBIWonState; + stateParams.state_complete = true; + break; + + case (uint8_t)kIBIWonState: + I3C_TransferStateMachineIBIWonState(base, handle, &stateParams); + break; + + case (uint8_t)kSendCommandState: + I3C_TransferStateMachineSendCommandState(base, handle, &stateParams); + break; + + case (uint8_t)kWaitRepeatedStartCompleteState: + I3C_TransferStateMachineWaitRepeatedStartCompleteState(base, handle, &stateParams); + break; + + case (uint8_t)kTransferDataState: + I3C_TransferStateMachineTransferDataState(base, handle, &stateParams); + break; + + case (uint8_t)kWaitForCompletionState: + I3C_TransferStateMachineWaitForCompletionState(handle, &stateParams); + break; + + case (uint8_t)kStopState: + I3C_TransferStateMachineStopState(base, handle, &stateParams); + *isDone = true; + break; + + default: + assert(false); + break; + } + } + return stateParams.result; +} + +static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle) +{ + i3c_master_transfer_t *xfer = &handle->transfer; + status_t result = kStatus_Success; + i3c_direction_t direction = xfer->direction; + + if (xfer->busType != kI3C_TypeI3CDdr) + { + direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (xfer->subaddressSize > 0UL) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI3C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kTransferDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + I3C_MasterTransferHandleIRQ(base, handle); + return result; + } + /* If repeated start is requested, send repeated start. */ + else if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); + } + + if (xfer->subaddressSize > 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + handle->state = (uint8_t)kTransferDataState; + } + + if ((handle->remainingBytes < 256U) && (direction == kI3C_Read)) + { + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; + base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); + } + + return result; +} + +/*! + * brief Performs a non-blocking transaction on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I3C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + handle->remainingBytes = transfer->dataSize; + + /* Configure IBI response type. */ + base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; + base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + handle->rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + handle->rxTermOps = kI3C_RxAutoTerm; + } + else + { + handle->rxTermOps = kI3C_RxTermLastByte; + } + + /* Generate commands to send. */ + (void)I3C_InitTransferStateMachine(base, handle); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + + if (transfer->direction == kI3C_Write) + { + I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + } + + return kStatus_Success; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint8_t state; + uint32_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = I3C_MasterGetEnabledInterrupts(base); + I3C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + I3C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case (uint8_t)kIdleState: + case (uint8_t)kSendCommandState: + *count = 0; + break; + + case (uint8_t)kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case (uint8_t)kStopState: + case (uint8_t)kWaitForCompletionState: + default: + *count = dataSize; + break; + } + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking I3C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I3C peripheral's IRQ priority. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. + */ +void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Send a stop command to finalize the transfer. */ + (void)I3C_MasterStop(base); + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle) +{ + bool isDone; + status_t result; + + i3c_master_handle_t *handle = (i3c_master_handle_t *)intHandle; + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I3C_RunTransferStateMachine(base, handle, &isDone); + + if (handle->state == (uint8_t)kIdleState) + { + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + return; + } + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) + { + (void)I3C_MasterEmitStop(base, false); + } + + /* Disable internal IRQ enables. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke IBI user callback. */ + if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); + handle->ibiPayloadSize = 0; + } + + /* Invoke callback. */ + if (NULL != handle->callback.transferComplete) + { + handle->callback.transferComplete(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Provides a default configuration for the I3C slave peripheral. + * + * This function provides the following default configuration for the I3C slave peripheral: + * code + * slaveConfig->enableslave = true; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the slave driver with I3C_SlaveInit(). + * + * param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. + */ +void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig) +{ + assert(NULL != slaveConfig); + + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) + slaveConfig->isHotJoin = false; +#endif + slaveConfig->vendorID = 0x11BU; +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + slaveConfig->enableRandomPart = false; +#endif + slaveConfig->partNumber = 0; + slaveConfig->dcr = 0; /* Generic device. */ + slaveConfig->bcr = + 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR + Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, device is + offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI Request Capable, + capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ + slaveConfig->hdrMode = (uint8_t)kI3C_HDRModeDDR; + slaveConfig->nakAllRequest = false; + slaveConfig->ignoreS0S1Error = true; + slaveConfig->offline = false; + slaveConfig->matchSlaveStartStop = false; + slaveConfig->maxWriteLength = 256U; + slaveConfig->maxReadLength = 256U; +} + +/*! + * brief Initializes the I3C slave peripheral. + * + * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user + * provided configuration. + * + * param base The I3C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of + * defaults that you can override. + * param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + */ +void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz) +{ + assert(NULL != slaveConfig); + assert(0UL != slowClock_Hz); + + uint32_t configValue; + uint32_t instance = I3C_GetInstance(base); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + uint8_t matchCount; + /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/ + matchCount = (uint8_t)(slowClock_Hz / 1000000UL); +#endif + + configValue = base->SCONFIG; + configValue &= + ~(I3C_SCONFIG_SADDR_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH_MASK | +#endif + I3C_SCONFIG_OFFLINE_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND_MASK | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK_MASK | +#else + I3C_SCONFIG_DDROK_MASK | +#endif + I3C_SCONFIG_S0IGNORE_MASK | I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); + configValue |= I3C_SCONFIG_SADDR(slaveConfig->staticAddr) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH(matchCount) | +#endif + I3C_SCONFIG_OFFLINE(slaveConfig->offline) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND(slaveConfig->enableRandomPart) | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK((0U != (slaveConfig->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#else + I3C_SCONFIG_DDROK((0U != (slaveConfig->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#endif + I3C_SCONFIG_S0IGNORE(slaveConfig->ignoreS0S1Error) | + I3C_SCONFIG_MATCHSS(slaveConfig->matchSlaveStartStop) | + I3C_SCONFIG_NACK(slaveConfig->nakAllRequest) | I3C_SCONFIG_SLVENA(slaveConfig->enableSlave); + + base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; + base->SVENDORID |= I3C_SVENDORID_VID(slaveConfig->vendorID); + +#if defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND + base->SIDPARTNO = slaveConfig->partNumber; +#else + if (!slaveConfig->enableRandomPart) + { + base->SIDPARTNO = slaveConfig->partNumber; + } +#endif + + base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); + base->SIDEXT |= I3C_SIDEXT_BCR(slaveConfig->bcr) | I3C_SIDEXT_DCR(slaveConfig->dcr); + + base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); + base->SMAXLIMITS |= + (I3C_SMAXLIMITS_MAXRD(slaveConfig->maxReadLength) | I3C_SMAXLIMITS_MAXWR(slaveConfig->maxWriteLength)); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) + if (slaveConfig->isHotJoin) + { + I3C_SlaveRequestEvent(base, kI3C_SlaveEventHotJoinReq); + } +#endif + base->SCONFIG = configValue; +} + +/*! + * brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I3C peripheral base address. + */ +void I3C_SlaveDeinit(I3C_Type *base) +{ + uint32_t idx = I3C_GetInstance(base); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[idx]); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + CLOCK_DisableClock(kI3cClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset handle pointer */ + s_i3cSlaveHandle[idx] = NULL; +} + +/*! + * @brief Gets the I3C slave state. + * + * @param base The I3C peripheral base address. + * @return I3C slave activity state, refer #i3c_slave_activity_state_t. + */ +i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base) +{ + uint8_t activeState = (uint8_t)((base->SSTATUS & I3C_SSTATUS_ACTSTATE_MASK) >> I3C_SSTATUS_ACTSTATE_SHIFT); + i3c_slave_activity_state_t returnCode; + switch (activeState) + { + case (uint8_t)kI3C_SlaveNoLatency: + returnCode = kI3C_SlaveNoLatency; + break; + case (uint8_t)kI3C_SlaveLatency1Ms: + returnCode = kI3C_SlaveLatency1Ms; + break; + case (uint8_t)kI3C_SlaveLatency100Ms: + returnCode = kI3C_SlaveLatency100Ms; + break; + case (uint8_t)kI3C_SlaveLatency10S: + returnCode = kI3C_SlaveLatency10S; + break; + default: + returnCode = kI3C_SlaveNoLatency; + break; + } + + return returnCode; +} + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) +/*! + * brief I3C slave request event. + * + * param base The I3C peripheral base address. + * param event I3C slave event of type #i3c_slave_event_t + * param data IBI data if In-band interrupt has data, only applicable for event type #kI3C_SlaveEventIBI + */ +void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event) +{ + uint32_t ctrlValue = base->SCTRL; + + ctrlValue &= ~I3C_SCTRL_EVENT_MASK; + ctrlValue |= I3C_SCTRL_EVENT(event); + + base->SCTRL = ctrlValue; +} + +/*! + * brief I3C slave request event. + * deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData. + * + * param base The I3C peripheral base address. + * param data IBI data + * param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize) +{ + uint32_t ctrlValue = base->SCTRL; + + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data); + + base->SCTRL = ctrlValue; +} + +/*! + * brief I3C slave request IBI event with data payload(mandatory and extended). + * + * param base The I3C peripheral base address. + * param data Pointer to IBI data to be sent in the request. + * param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize) +{ + assert((dataSize > 0U) && (dataSize <= 8U)); + + uint32_t ctrlValue; + +#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK) + if (dataSize > 1U) + { + ctrlValue = I3C_IBIEXT1_EXT1(data[1]); + if (dataSize > 2U) + { + ctrlValue |= I3C_IBIEXT1_EXT2(data[2]); + } + if (dataSize > 3U) + { + ctrlValue |= I3C_IBIEXT1_EXT3(data[3]); + } + ctrlValue |= I3C_IBIEXT1_CNT(dataSize - 1U); + base->IBIEXT1 = ctrlValue; + } + + if (dataSize > 4U) + { + ctrlValue = I3C_IBIEXT2_EXT4(data[4]); + if (dataSize > 5U) + { + ctrlValue |= I3C_IBIEXT2_EXT5(data[5]); + } + if (dataSize > 6U) + { + ctrlValue |= I3C_IBIEXT2_EXT6(data[6]); + } + if (dataSize > 7U) + { + ctrlValue |= I3C_IBIEXT2_EXT7(data[7]); + } + base->IBIEXT2 = ctrlValue; + } +#endif + + ctrlValue = base->SCTRL; +#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK) + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK | I3C_SCTRL_EXTDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]) | I3C_SCTRL_EXTDATA(dataSize > 1U); +#else + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]); +#endif + base->SCTRL = ctrlValue; +} +#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */ + +/*! + * brief Performs a polling send transfer on the I3C bus. + * + * param base The I3C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return Error or success status returned by API. + */ +status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize) +{ + const uint8_t *buf = (const uint8_t *)((const void *)txBuff); + status_t result = kStatus_Success; + + assert(NULL != txBuff); + + /* Send data buffer */ + while (0UL != txSize--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = I3C_SlaveWaitForTxReady(base); + if (kStatus_Success != result) + { + return result; + } + + /* Write byte into I3C slave data register. */ + if (0UL != txSize) + { + base->SWDATAB = *buf++; + } + else + { + base->SWDATABE = *buf++; + } + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I3C bus. + * + * param base The I3C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return Error or success status returned by API. + */ +status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf; + + assert(NULL != rxBuff); + + /* Handle empty read. */ + if (0UL == rxSize) + { + return kStatus_Success; + } + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (0UL != rxSize) + { +#if I3C_RETRY_TIMES + if (--waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + /* Check for errors. */ + result = I3C_SlaveCheckAndClearError(base, I3C_SlaveGetErrorStatusFlags(base)); + if (kStatus_Success != result) + { + return result; + } + + /* Check RX data */ + if (0UL != (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK)) + { + *buf++ = (uint8_t)(base->SRDATAB & I3C_SRDATAB_DATA0_MASK); + rxSize--; + } + } + + return result; +} + +/*! + * brief Creates a new handle for the I3C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The I3C peripheral base address. + * param[out] handle Pointer to the I3C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I3C_SlaveTransferCreateHandle(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* Save Tx FIFO Size. */ + handle->txFifoSize = + 2U << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + + /* Save this handle for IRQ use. */ + s_i3cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cSlaveIsr = I3C_SlaveTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + (void)EnableIRQ(kI3cIrqs[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. + */ +status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(NULL != handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kI3C_SlaveTransmitEvent | (uint32_t)kI3C_SlaveReceiveEvent; + + /* Clear all flags. */ + I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + return kStatus_Success; +} + +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The I3C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ +status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + * retval #kStatus_Success + * retval #kStatus_I3C_Idle + */ +void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle) +{ + assert(NULL != handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable I3C IRQ sources. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +static bool I3C_SlaveTransferHandleGetStatusFlags(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + /* Check for a valid handle in case of a spurious interrupt. */ + uint32_t errFlags; + stateParams->flags = I3C_SlaveGetStatusFlags(base); + errFlags = I3C_SlaveGetErrorStatusFlags(base); + + stateParams->pendingInts = I3C_SlaveGetPendingInterrupts(base); + stateParams->enabledInts = I3C_SlaveGetEnabledInterrupts(base); + + if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) + { + handle->transfer.event = (uint32_t)kI3C_SlaveCompletionEvent; + handle->transfer.completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); + + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, &handle->transfer, handle->userData); + } + return false; + } + return true; +} + +static void I3C_SlaveTransferHandleBusStart(I3C_Type *base, i3c_slave_transfer_t *xfer, uint32_t *pendingInts) +{ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK; + xfer->txDataSize = 0; + I3C_SlaveEnableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + (*pendingInts) |= (uint32_t)kI3C_SlaveTxReadyFlag; +} + +static void I3C_SlaveTransferHandleEventSent(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer) +{ + xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +} + +static void I3C_SlaveTransferHandleReceivedCCC(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer) +{ + handle->isBusy = true; + xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +} + +static void I3C_SlaveTransferHandleBusStop(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + stateParams->pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + if (handle->isBusy) + { + handle->transfer.event = (uint32_t)kI3C_SlaveCompletionEvent; + handle->transfer.completionStatus = kStatus_Success; + handle->transfer.transferredCount = handle->transferredCount; + handle->isBusy = false; + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that I3C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --handle->transfer.transferredCount; + handle->wasTransmit = false; + } + + if ((0UL != (handle->eventMask & handle->transfer.event)) && (NULL != handle->callback)) + { + handle->callback(base, &handle->transfer, handle->userData); + } + + /* Clean up transfer info on completion, after the callback has been invoked. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + } +} + +static void I3C_SlaveTransferHandleMatched(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer) +{ + assert(NULL != base && NULL != handle && NULL != xfer); + xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; + handle->isBusy = true; + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +} + +static void I3C_SlaveTransferHandleTxReady(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((NULL == handle->transfer.txData) || (0UL == handle->transfer.txDataSize)) + { + handle->transfer.event = (uint32_t)kI3C_SlaveTransmitEvent; + if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) + { + handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; + } + if (NULL != handle->callback) + { + handle->callback(base, &handle->transfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0; + } + + if ((NULL == handle->transfer.txData) || (0UL == handle->transfer.txDataSize)) + { + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + (stateParams->pendingInts) &= ~(uint32_t)kI3C_SlaveTxReadyFlag; + } + + /* Transmit a byte. */ + while ((handle->transfer.txDataSize != 0UL) && ((stateParams->txCount) != 0U)) + { + if (handle->transfer.txDataSize > 1UL) + { + base->SWDATAB = *handle->transfer.txData++; + } + else + { + base->SWDATABE = *handle->transfer.txData++; + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + } + --(handle->transfer.txDataSize); + ++(handle->transferredCount); + (stateParams->txCount)--; + } +} + +static void I3C_SlaveTransferHandleRxReady(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((NULL == handle->transfer.rxData) || (0UL == handle->transfer.rxDataSize)) + { + handle->transfer.event = (uint32_t)kI3C_SlaveReceiveEvent; + if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) + { + handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; + } + if (NULL != handle->callback) + { + handle->callback(base, &handle->transfer, handle->userData); + } + handle->transferredCount = 0; + } + /* Receive a byte. */ + while ((stateParams->rxCount != 0U) && ((handle->transfer.rxData != NULL) && (handle->transfer.rxDataSize != 0UL))) + { + *(handle->transfer.rxData++) = (uint8_t)base->SRDATAB; + --(handle->transfer.rxDataSize); + ++(handle->transferredCount); + (stateParams->rxCount)--; + } +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + */ +void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle) +{ + i3c_slave_handleIrq_param_t stateParams; + + (void)memset(&stateParams, 0, sizeof(stateParams)); + i3c_slave_handle_t *handle = (i3c_slave_handle_t *)intHandle; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL == handle) + { + return; + } + + /* Get status flags. */ + if (false == I3C_SlaveTransferHandleGetStatusFlags(base, handle, &stateParams)) + { + return; + } + + /* Clear status flags. */ + I3C_SlaveClearStatusFlags(base, stateParams.flags); + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveBusStartFlag)) + { + I3C_SlaveTransferHandleBusStart(base, &handle->transfer, &stateParams.pendingInts); + } + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveEventSentFlag)) + { + I3C_SlaveTransferHandleEventSent(base, handle, &handle->transfer); + } + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) + { + I3C_SlaveTransferHandleReceivedCCC(base, handle, &handle->transfer); + } + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveMatchedFlag)) + { + I3C_SlaveTransferHandleMatched(base, handle, &handle->transfer); + } + + /* Get fifo counts and compute room in tx fifo. */ + I3C_SlaveGetFifoCounts(base, &stateParams.rxCount, &stateParams.txCount); + stateParams.txCount = handle->txFifoSize - stateParams.txCount; + + /* Handle transmit and receive. */ + if ((0UL != (stateParams.flags & (uint32_t)kI3C_SlaveTxReadyFlag)) && + (0UL != (stateParams.pendingInts & (uint32_t)kI3C_SlaveTxReadyFlag))) + { + I3C_SlaveTransferHandleTxReady(base, handle, &stateParams); + } + + if ((0UL != (stateParams.flags & (uint32_t)kI3C_SlaveRxReadyFlag)) && + (0UL != (stateParams.enabledInts & (uint32_t)kI3C_SlaveRxReadyFlag))) + { + I3C_SlaveTransferHandleRxReady(base, handle, &stateParams); + } + + /* Handle stop event. */ + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveBusStopFlag)) + { + I3C_SlaveTransferHandleBusStop(base, handle, &stateParams); + } +} + +static void I3C_CommonIRQHandler(I3C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if (((uint32_t)kI3C_MasterOn == (base->MCONFIG & I3C_MCONFIG_MSTENA_MASK)) && (NULL != s_i3cMasterIsr)) + { + /* Master mode. */ + s_i3cMasterIsr(base, s_i3cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((I3C_SCONFIG_SLVENA_MASK == (base->SCONFIG & I3C_SCONFIG_SLVENA_MASK)) && (NULL != s_i3cSlaveIsr)) + { + /* Slave mode. */ + s_i3cSlaveIsr(base, s_i3cSlaveHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(I3C) +/* Implementation of I3C handler named in startup code. */ +void I3C0_DriverIRQHandler(void); +void I3C0_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C, 0); +} +#endif + +#if defined(I3C0) +/* Implementation of I3C0 handler named in startup code. */ +void I3C0_DriverIRQHandler(void); +void I3C0_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C0, 0); +} +#endif + +#if defined(I3C1) +/* Implementation of I3C1 handler named in startup code. */ +void I3C1_DriverIRQHandler(void); +void I3C1_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C1, 1); +} +#endif + +#if defined(I3C2) +/* Implementation of I3C2 handler named in startup code. */ +void I3C2_DriverIRQHandler(void); +void I3C2_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C2, 2); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c.h new file mode 100644 index 0000000000..f6a2d7fc4d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c.h @@ -0,0 +1,1876 @@ +/* + * Copyright 2018-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_I3C_H_ +#define FSL_I3C_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i3c + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I3C driver version */ +#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 10, 6)) +/*@}*/ + +/*! @brief Timeout times for waiting flag. */ +#ifndef I3C_RETRY_TIMES +#define I3C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define I3C_MAX_DEVCNT 10U + +#ifndef I3C_IBI_BUFF_SIZE +#define I3C_IBI_BUFF_SIZE 10U +#endif + +/*! @brief I3C status return codes. */ +enum +{ + kStatus_I3C_Busy = MAKE_STATUS(kStatusGroup_I3C, 0), /*!< The master is already performing a transfer. */ + kStatus_I3C_Idle = MAKE_STATUS(kStatusGroup_I3C, 1), /*!< The slave driver is idle. */ + kStatus_I3C_Nak = MAKE_STATUS(kStatusGroup_I3C, 2), /*!< The slave device sent a NAK in response to an address. */ + kStatus_I3C_WriteAbort = + MAKE_STATUS(kStatusGroup_I3C, 3), /*!< The slave device sent a NAK in response to a write. */ + kStatus_I3C_Term = MAKE_STATUS(kStatusGroup_I3C, 4), /*!< The master terminates slave read. */ + kStatus_I3C_HdrParityError = MAKE_STATUS(kStatusGroup_I3C, 5), /*!< Parity error from DDR read. */ + kStatus_I3C_CrcError = MAKE_STATUS(kStatusGroup_I3C, 6), /*!< CRC error from DDR read. */ + kStatus_I3C_ReadFifoError = MAKE_STATUS(kStatusGroup_I3C, 7), /*!< Read from M/SRDATAB register when FIFO empty. */ + kStatus_I3C_WriteFifoError = MAKE_STATUS(kStatusGroup_I3C, 8), /*!< Write to M/SWDATAB register when FIFO full. */ + kStatus_I3C_MsgError = + MAKE_STATUS(kStatusGroup_I3C, 9), /*!< Message SDR/DDR mismatch or read/write message in wrong state */ + kStatus_I3C_InvalidReq = MAKE_STATUS(kStatusGroup_I3C, 10), /*!< Invalid use of request. */ + kStatus_I3C_Timeout = MAKE_STATUS(kStatusGroup_I3C, 11), /*!< The module has stalled too long in a frame. */ + kStatus_I3C_SlaveCountExceed = + MAKE_STATUS(kStatusGroup_I3C, 12), /*!< The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. */ + kStatus_I3C_IBIWon = MAKE_STATUS( + kStatusGroup_I3C, 13), /*!< The I3C slave event IBI or MR or HJ won the arbitration on a header address. */ + kStatus_I3C_OverrunError = MAKE_STATUS(kStatusGroup_I3C, 14), /*!< Slave internal from-bus buffer/FIFO overrun. */ + kStatus_I3C_UnderrunError = MAKE_STATUS(kStatusGroup_I3C, 15), /*!< Slave internal to-bus buffer/FIFO underrun */ + kStatus_I3C_UnderrunNak = + MAKE_STATUS(kStatusGroup_I3C, 16), /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */ + kStatus_I3C_InvalidStart = MAKE_STATUS(kStatusGroup_I3C, 17), /*!< Slave invalid start flag */ + kStatus_I3C_SdrParityError = MAKE_STATUS(kStatusGroup_I3C, 18), /*!< SDR parity error */ + kStatus_I3C_S0S1Error = MAKE_STATUS(kStatusGroup_I3C, 19), /*!< S0 or S1 error */ +}; + +/*! @brief I3C HDR modes. */ +typedef enum _i3c_hdr_mode +{ + kI3C_HDRModeNone = 0x00U, /* Do not support HDR mode. */ + kI3C_HDRModeDDR = 0x01U, /* HDR-DDR Mode. */ + kI3C_HDRModeTSP = 0x02U, /* HDR-TSP Mode. */ + kI3C_HDRModeTSL = 0x04U, /* HDR-TSL Mode. */ +} i3c_hdr_mode_t; + +/*! @brief I3C device information. */ +typedef struct _i3c_device_info +{ + uint8_t dynamicAddr; /*!< Device dynamic address. */ + uint8_t staticAddr; /*!< Static address. */ + uint8_t dcr; /*!< Device characteristics register information. */ + uint8_t bcr; /*!< Bus characteristics register information. */ + uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */ + uint32_t partNumber; /*!< Device part number info */ + uint16_t maxReadLength; /*!< Maximum read length. */ + uint16_t maxWriteLength; /*!< Maximum write length. */ + uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in i3c_hdr_mode. */ +} i3c_device_info_t; + +/*! @} */ + +/*! + * @addtogroup i3c_master_driver + * @{ + */ + +/*! + * @brief I3C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kI3C_MasterSlaveStartFlag + * - #kI3C_MasterControlDoneFlag + * - #kI3C_MasterCompleteFlag + * - #kI3C_MasterArbitrationWonFlag + * - #kI3C_MasterSlave2MasterFlag + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_master_flags +{ + kI3C_MasterBetweenFlag = I3C_MSTATUS_BETWEEN_MASK, /*!< Between messages/DAAs flag */ + kI3C_MasterNackDetectFlag = I3C_MSTATUS_NACKED_MASK, /*!< NACK detected flag */ + kI3C_MasterSlaveStartFlag = I3C_MSTATUS_SLVSTART_MASK, /*!< Slave request start flag */ + kI3C_MasterControlDoneFlag = I3C_MSTATUS_MCTRLDONE_MASK, /*!< Master request complete flag */ + kI3C_MasterCompleteFlag = I3C_MSTATUS_COMPLETE_MASK, /*!< Transfer complete flag */ + kI3C_MasterRxReadyFlag = I3C_MSTATUS_RXPEND_MASK, /*!< Rx data ready in Rx buffer flag */ + kI3C_MasterTxReadyFlag = I3C_MSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */ + kI3C_MasterArbitrationWonFlag = I3C_MSTATUS_IBIWON_MASK, /*!< Header address won arbitration flag */ + kI3C_MasterErrorFlag = I3C_MSTATUS_ERRWARN_MASK, /*!< Error occurred flag */ + kI3C_MasterSlave2MasterFlag = I3C_MSTATUS_NOWMASTER_MASK, /*!< Switch from slave to master flag */ + kI3C_MasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, +}; + +/*! + * @brief I3C master error flags to indicate the causes. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_master_error_flags +{ + kI3C_MasterErrorNackFlag = I3C_MERRWARN_NACK_MASK, /*!< Slave NACKed the last address */ + kI3C_MasterErrorWriteAbortFlag = I3C_MERRWARN_WRABT_MASK, /*!< Slave NACKed the write data */ +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag = I3C_MERRWARN_TERM_MASK, /*!< Master terminates slave read */ +#endif + kI3C_MasterErrorParityFlag = I3C_MERRWARN_HPAR_MASK, /*!< Parity error from DDR read */ + kI3C_MasterErrorCrcFlag = I3C_MERRWARN_HCRC_MASK, /*!< CRC error from DDR read */ + kI3C_MasterErrorReadFlag = I3C_MERRWARN_OREAD_MASK, /*!< Read from MRDATAB register when FIFO empty */ + kI3C_MasterErrorWriteFlag = I3C_MERRWARN_OWRITE_MASK, /*!< Write to MWDATAB register when FIFO full */ + kI3C_MasterErrorMsgFlag = I3C_MERRWARN_MSGERR_MASK, /*!< Message SDR/DDR mismatch or + read/write message in wrong state */ + kI3C_MasterErrorInvalidReqFlag = I3C_MERRWARN_INVREQ_MASK, /*!< Invalid use of request */ + kI3C_MasterErrorTimeoutFlag = I3C_MERRWARN_TIMEOUT_MASK, /*!< The module has stalled too long in a frame */ + kI3C_MasterAllErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, /*!< All error flags */ +}; + +/*! @brief I3C working master state. */ +typedef enum _i3c_master_state +{ + kI3C_MasterStateIdle = 0U, /*!< Bus stopped. */ + kI3C_MasterStateSlvReq = 1U, /*!< Bus stopped but slave holding SDA low. */ + kI3C_MasterStateMsgSdr = 2U, /*!< In SDR Message mode from using MWMSG_SDR. */ + kI3C_MasterStateNormAct = 3U, /*!< In normal active SDR mode. */ + kI3C_MasterStateDdr = 4U, /*!< In DDR Message mode. */ + kI3C_MasterStateDaa = 5U, /*!< In ENTDAA mode. */ + kI3C_MasterStateIbiAck = 6U, /*!< Waiting on IBI ACK/NACK decision. */ + kI3C_MasterStateIbiRcv = 7U, /*!< receiving IBI. */ +} i3c_master_state_t; + +/*! @brief I3C master enable configuration. */ +typedef enum _i3c_master_enable +{ + kI3C_MasterOff = 0U, /*!< Master off. */ + kI3C_MasterOn = 1U, /*!< Master on. */ + kI3C_MasterCapable = 2U /*!< Master capable. */ +} i3c_master_enable_t; + +/*! @brief I3C high keeper configuration. */ +typedef enum _i3c_master_hkeep +{ + kI3C_MasterHighKeeperNone = 0U, /*!< Use PUR to hold SCL high. */ + kI3C_MasterHighKeeperWiredIn = 1U, /*!< Use pin_HK controls. */ + kI3C_MasterPassiveSDA = 2U, /*!< Hi-Z for Bus Free and hold SDA. */ + kI3C_MasterPassiveSDASCL = 3U /*!< Hi-Z both for Bus Free, and can Hi-Z SDA for hold. */ +} i3c_master_hkeep_t; + +/*! @brief Emits the requested operation when doing in pieces vs. by message. */ +typedef enum _i3c_bus_request +{ + kI3C_RequestNone = 0U, /*!< No request. */ + kI3C_RequestEmitStartAddr = 1U, /*!< Request to emit start and address on bus. */ + kI3C_RequestEmitStop = 2U, /*!< Request to emit stop on bus. */ + kI3C_RequestIbiAckNack = 3U, /*!< Manual IBI ACK or NACK. */ + kI3C_RequestProcessDAA = 4U, /*!< Process DAA. */ + kI3C_RequestForceExit = 6U, /*!< Request to force exit. */ + kI3C_RequestAutoIbi = 7U, /*!< Hold in stopped state, but Auto-emit START,7E. */ +} i3c_bus_request_t; + +/*! @brief Bus type with EmitStartAddr. */ +typedef enum _i3c_bus_type +{ + kI3C_TypeI3CSdr = 0U, /*!< SDR mode of I3C. */ + kI3C_TypeI2C = 1U, /*!< Standard i2c protocol. */ + kI3C_TypeI3CDdr = 2U, /*!< HDR-DDR mode of I3C. */ +} i3c_bus_type_t; + +/*! @brief IBI response. */ +typedef enum _i3c_ibi_response +{ + kI3C_IbiRespAck = 0U, /*!< ACK with no mandatory byte. */ + kI3C_IbiRespNack = 1U, /*!< NACK. */ + kI3C_IbiRespAckMandatory = 2U, /*!< ACK with mandatory byte. */ + kI3C_IbiRespManual = 3U, /*!< Reserved. */ +} i3c_ibi_response_t; + +/*! @brief IBI type. */ +typedef enum _i3c_ibi_type +{ + kI3C_IbiNormal = 0U, /*!< In-band interrupt. */ + kI3C_IbiHotJoin = 1U, /*!< slave hot join. */ + kI3C_IbiMasterRequest = 2U, /*!< slave master ship request. */ +} i3c_ibi_type_t; + +/*! @brief IBI state. */ +typedef enum _i3c_ibi_state +{ + kI3C_IbiReady = 0U, /*!< In-band interrupt ready state, ready for user to handle. */ + kI3C_IbiDataBuffNeed = 1U, /*!< In-band interrupt need data buffer for data receive. */ + kI3C_IbiAckNackPending = 2U, /*!< In-band interrupt Ack/Nack pending for decision. */ +} i3c_ibi_state_t; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i3c_direction +{ + kI3C_Write = 0U, /*!< Master transmit. */ + kI3C_Read = 1U /*!< Master receive. */ +} i3c_direction_t; + +/*! @brief Watermark of TX int/dma trigger level. */ +typedef enum _i3c_tx_trigger_level +{ + kI3C_TxTriggerOnEmpty = 0U, /*!< Trigger on empty. */ + kI3C_TxTriggerUntilOneQuarterOrLess = 1U, /*!< Trigger on 1/4 full or less. */ + kI3C_TxTriggerUntilOneHalfOrLess = 2U, /*!< Trigger on 1/2 full or less. */ + kI3C_TxTriggerUntilOneLessThanFull = 3U, /*!< Trigger on 1 less than full or less. */ +} i3c_tx_trigger_level_t; + +/*! @brief Watermark of RX int/dma trigger level. */ +typedef enum _i3c_rx_trigger_level +{ + kI3C_RxTriggerOnNotEmpty = 0U, /*!< Trigger on not empty. */ + kI3C_RxTriggerUntilOneQuarterOrMore = 1U, /*!< Trigger on 1/4 full or more. */ + kI3C_RxTriggerUntilOneHalfOrMore = 2U, /*!< Trigger on 1/2 full or more. */ + kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */ +} i3c_rx_trigger_level_t; + +/*! @brief I3C master read termination operations. */ +typedef enum _i3c_rx_term_ops +{ + kI3C_RxTermDisable = 0U, /*!< Master doesn't terminate read, used for CCC transfer. */ + kI3C_RxAutoTerm = 1U, /*!< Master auto terminate read after receiving specified bytes(<=255). */ + kI3C_RxTermLastByte = 2U, /*!< Master terminates read at any time after START, no length limitation. */ +} i3c_rx_term_ops_t; + +/*! @brief Structure with setting master IBI rules and slave registry. */ +typedef struct _i3c_register_ibi_addr +{ + uint8_t address[5]; /*!< Address array for registry. */ + bool ibiHasPayload; /*!< Whether the address array has mandatory IBI byte. */ +} i3c_register_ibi_addr_t; + +/*! @brief Structure with I3C baudrate settings. */ +typedef struct _i3c_baudrate +{ + uint32_t i2cBaud; /*!< Desired I2C baud rate in Hertz. */ + uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */ + uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */ +} i3c_baudrate_hz_t; + +/*! @brief I3C DAA baud rate configuration. */ +typedef struct _i3c_master_daa_baudrate +{ + uint32_t sourceClock_Hz; /*!< FCLK, function clock in Hertz. */ + uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */ + uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */ +} i3c_master_daa_baudrate_t; + +/*! + * @brief Structure with settings to initialize the I3C master module. + * + * This structure holds configuration settings for the I3C peripheral. To initialize this + * structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i3c_master_config +{ + i3c_master_enable_t enableMaster; /*!< Enable master mode. */ + bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */ + i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */ + bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */ + bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */ + i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */ +} i3c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_master_transfer i3c_master_transfer_t; +typedef struct _i3c_master_handle i3c_master_handle_t; + +/*! @brief i3c master callback functions. */ +typedef struct _i3c_master_transfer_callback +{ + void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ + void (*ibiCallback)(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_ibi_type_t ibiType, + i3c_ibi_state_t ibiState); /*!< IBI event callback */ + void (*transferComplete)(I3C_Type *base, + i3c_master_handle_t *handle, + status_t completionStatus, + void *userData); /*!< Transfer complete callback */ +} i3c_master_transfer_callback_t; +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i3c_master_transfer::flags field. + */ +enum _i3c_master_transfer_flags +{ + kI3C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI3C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ + kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */ + kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */ + kI3C_TransferRxAutoTermFlag = + 0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */ + kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API. + */ +struct _i3c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available + options. Set to 0 or #kI3C_TransferDefaultFlag for normal transfers. */ + uint8_t slaveAddress; /*!< The 7-bit slave address. */ + i3c_direction_t direction; /*!< Either #kI3C_Read or #kI3C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ + i3c_bus_type_t busType; /*!< bus type. */ + i3c_ibi_response_t ibiResponse; /*!< ibi response during transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + i3c_rx_term_ops_t rxTermOps; /*!< Read termination operation. */ + i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + uint8_t ibiAddress; /*!< Slave address which request IBI. */ + uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ + size_t ibiPayloadSize; /*!< IBI payload size. */ + i3c_ibi_type_t ibiType; /*!< IBI type. */ + i3c_master_transfer_callback_t callback; /*!< Callback functions pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle); + +/*! @} */ + +/*! + * @addtogroup i3c_slave_driver + * @{ + */ + +/*! + * @brief I3C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * + * Only below flags can be enabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_slave_flags +{ + kI3C_SlaveNotStopFlag = I3C_SSTATUS_STNOTSTOP_MASK, /*!< Slave status not stop flag */ + kI3C_SlaveMessageFlag = I3C_SSTATUS_STMSG_MASK, /*!< Slave status message, indicating slave is + listening to the bus traffic or responding */ + kI3C_SlaveRequiredReadFlag = I3C_SSTATUS_STREQRD_MASK, /*!< Slave status required, either is master doing SDR + read from slave, or is IBI pushing out. */ + kI3C_SlaveRequiredWriteFlag = I3C_SSTATUS_STREQWR_MASK, /*!< Slave status request write, master is doing SDR + write to slave, except slave in ENTDAA mode */ + kI3C_SlaveBusDAAFlag = I3C_SSTATUS_STDAA_MASK, /*!< I3C bus is in ENTDAA mode */ + kI3C_SlaveBusHDRModeFlag = I3C_SSTATUS_STHDR_MASK, /*!< I3C bus is in HDR mode */ + kI3C_SlaveBusStartFlag = I3C_SSTATUS_START_MASK, /*!< Start/Re-start event is seen since the bus was last cleared */ + kI3C_SlaveMatchedFlag = I3C_SSTATUS_MATCHED_MASK, /*!< Slave address(dynamic/static) matched since last cleared */ + kI3C_SlaveBusStopFlag = I3C_SSTATUS_STOP_MASK, /*!enableMaster = kI3C_MasterCapable; + * config->disableTimeout = false; + * config->hKeep = kI3C_MasterHighKeeperNone; + * config->enableOpenDrainStop = true; + * config->enableOpenDrainHigh = true; + * config->baudRate_Hz.i2cBaud = 400000U; + * config->baudRate_Hz.i3cPushPullBaud = 12500000U; + * config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; + * config->masterDynamicAddress = 0x0AU; + * config->slowClock_Hz = 1000000U; + * config->enableSlave = true; + * config->vendorID = 0x11BU; + * config->enableRandomPart = false; + * config->partNumber = 0; + * config->dcr = 0; + * config->bcr = 0; + * config->hdrMode = (uint8_t)kI3C_HDRModeDDR; + * config->nakAllRequest = false; + * config->ignoreS0S1Error = false; + * config->offline = false; + * config->matchSlaveStartStop = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the common I3C driver with I3C_Init(). + * + * @param[out] config User provided configuration structure for default values. Refer to #i3c_config_t. + */ +void I3C_GetDefaultConfig(i3c_config_t *config); + +/*! + * @brief Initializes the I3C peripheral. + * This function enables the peripheral clock and initializes the I3C peripheral as described by the user + * provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C + * module could work as pure master, pure slave or secondary master, etc. + * A software reset is performed prior to configuration. + * + * @param base The I3C peripheral base address. + * @param config User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of + * defaults that you can override. + * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz); + +/*! @} */ + +/*! + * @addtogroup i3c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I3C master peripheral. + * + * This function provides the following default configuration for the I3C master peripheral: + * @code + * masterConfig->enableMaster = kI3C_MasterOn; + * masterConfig->disableTimeout = false; + * masterConfig->hKeep = kI3C_MasterHighKeeperNone; + * masterConfig->enableOpenDrainStop = true; + * masterConfig->enableOpenDrainHigh = true; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busType = kI3C_TypeI2C; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I3C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. + */ +void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I3C master peripheral. + * + * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I3C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of + * defaults that you can override. + * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I3C peripheral base address. + */ +void I3C_MasterDeinit(I3C_Type *base); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_CheckForBusyBus(I3C_Type *base); + +/*! + * @brief Set I3C module master mode. + * + * @param base The I3C peripheral base address. + * @param enable Enable master mode. + */ +static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable) +{ + base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the I3C master status flags. + * + * A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_master_flags + */ +static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base) +{ + return base->MSTATUS & ~(I3C_MSTATUS_STATE_MASK | I3C_MSTATUS_IBITYPE_MASK); +} + +/*! + * @brief Clears the I3C master status flag state. + * + * The following status register flags can be cleared: + * - #kI3C_MasterSlaveStartFlag + * - #kI3C_MasterControlDoneFlag + * - #kI3C_MasterCompleteFlag + * - #kI3C_MasterArbitrationWonFlag + * - #kI3C_MasterSlave2MasterFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i3c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_MasterGetStatusFlags(). + * @see _i3c_master_flags. + */ +static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->MSTATUS = statusMask; +} + +/*! + * @brief Gets the I3C master error status flags. + * + * A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the error status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_master_error_flags + */ +static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base) +{ + return base->MERRWARN; +} + +/*! + * @brief Clears the I3C master error status flag state. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of + * #_i3c_master_error_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_MasterGetStatusFlags(). + * @see _i3c_master_error_flags. + */ +static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + while ((base->MERRWARN & statusMask) != 0U) + { + base->MERRWARN = statusMask; + } +} + +/*! + * @brief Gets the I3C master state. + * + * @param base The I3C peripheral base address. + * @return I3C master state. + */ +i3c_master_state_t I3C_MasterGetState(I3C_Type *base); + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I3C master interrupt requests. + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i3c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->MINTSET |= interruptMask; +} + +/*! + * @brief Disables the I3C master interrupt requests. + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i3c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->MINTCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I3C master interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base) +{ + return base->MINTSET; +} + +/*! + * @brief Returns the set of pending I3C master interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the + * set of pending interrupts. + */ +static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base) +{ + return base->MINTMASKED; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables I3C master DMA requests. + * + * @param base The I3C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + * @param width DMA read/write unit in bytes. + */ +static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) +{ + assert(width <= 2U); + base->MDMACTRL = + I3C_MDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_MDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_MDMACTRL_DMAWIDTH(width); +} + +/*! + * @brief Gets I3C master transmit data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Master Transmit Data Register address. + */ +static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->MWDATAH : &base->MWDATAB); +} + +/*! + * @brief Gets I3C master receive data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Master Receive Data Register address. + */ +static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB); +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for I3C master FIFOs. + * + * @param base The I3C peripheral base address. + * @param txLvl Transmit FIFO watermark level. The #kI3C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO reaches @a txLvl. + * @param rxLvl Receive FIFO watermark level. The #kI3C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO reaches @a rxLvl. + * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. + * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. + */ +static inline void I3C_MasterSetWatermarks( + I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) +{ + base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(rxLvl) | + (flushTx ? I3C_MDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_MDATACTRL_FLUSHFB_MASK : 0U); +} + +/*! + * @brief Gets the current number of bytes in the I3C master FIFOs. + * + * @param base The I3C peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I3C bus frequency for master transactions. + * + * The I3C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I3C peripheral base address. + * @param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. + * @param sourceClock_Hz I3C functional clock frequency in Hertz. + */ +void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I3C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I3C_MasterGetBusIdleState(I3C_Type *base) +{ + return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false); +} + +/*! + * @brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); + +/*! + * @brief Sends a START signal and slave address on the I2C/I3C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read + * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer + * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize + * configuration. + * + * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C/I3C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, + i3c_bus_type_t type, + uint8_t address, + i3c_direction_t dir) +{ + return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, 0); +} + +/*! + * @brief Performs a polling send transfer on the I2C/I3C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I3C_Nak. + * + * @param base The I3C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * @retval #kStatus_Success Data was sent successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. + * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C/I3C bus. + * + * @param base The I3C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Term The master terminates slave read. + * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. + * @retval #kStatus_I3C_CrcError CRC error from DDR read. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Sends a STOP signal on the I2C/I3C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The I3C peripheral base address. + * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterStop(I3C_Type *base); + +/*! + * @brief I3C master emit request. + * + * @param base The I3C peripheral base address. + * @param masterReq I3C master request of type #i3c_bus_request_t + */ +void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq); + +/*! + * @brief I3C master emit request. + * + * @param base The I3C peripheral base address. + * @param ibiResponse I3C master emit IBI response of type #i3c_ibi_response_t + */ +static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse) +{ + uint32_t ctrlVal = base->MCTRL; + ctrlVal &= ~(I3C_MCTRL_IBIRESP_MASK | I3C_MCTRL_REQUEST_MASK); + ctrlVal |= I3C_MCTRL_IBIRESP((uint32_t)ibiResponse) | I3C_MCTRL_REQUEST(kI3C_RequestIbiAckNack); + base->MCTRL = ctrlVal; +} + +/*! + * @brief I3C master register IBI rule. + * + * @param base The I3C peripheral base address. + * @param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t + */ +void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); + +/*! + * @brief I3C master get IBI rule. + * + * @param base The I3C peripheral base address. + * @param ibiRule Pointer to store the read out ibi rule description. + */ +void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); + +/*! + * @brief I3C master get IBI Type. + * + * @param base The I3C peripheral base address. + * @retval i3c_ibi_type_t Type of #i3c_ibi_type_t. + */ +i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base); + +/*! + * @brief I3C master get IBI Address. + * + * @param base The I3C peripheral base address. + * @retval The 8-bit IBI address. + */ +static inline uint8_t I3C_GetIBIAddress(I3C_Type *base) +{ + return (uint8_t)((base->MSTATUS & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT); +} + +/*! + * @brief Performs a DAA in the i3c bus with specified temporary baud rate. + * + * @param base The I3C peripheral base address. + * @param addressList The pointer for address list which is used to do DAA. + * @param count The address count in the address list. + * @param daaBaudRate The temporary baud rate in DAA process, NULL for using initial setting. + * The initial setting is set back between the completion of the DAA and the return of this function. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. + */ +status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, + uint8_t *addressList, + uint32_t count, + i3c_master_daa_baudrate_t *daaBaudRate); + +/*! + * @brief Performs a DAA in the i3c bus. + * + * @param base The I3C peripheral base address. + * @param addressList The pointer for address list which is used to do DAA. + * @param count The address count in the address list. + * The initial setting is set back between the completion of the DAA and the return of this function. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. + */ +static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count) +{ + return I3C_MasterProcessDAASpecifiedBaudrate(base, addressList, count, NULL); +} + +/*! + * @brief Get device information list after DAA process is done. + * + * @param base The I3C peripheral base address. + * @param[out] count The pointer to store the available device count. + * @return Pointer to the i3c_device_info_t array. + */ +i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count); +/*! + * @brief Performs a master polling transfer on the I2C/I3C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The I3C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_IBIWon The I3C slave event IBI or MR or HJ won the arbitration on a header address. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. + * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. + * @retval #kStatus_I3C_Term The master terminates slave read. + * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. + * @retval #kStatus_I3C_CrcError CRC error from DDR read. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. + * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I3C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The I3C peripheral base address. + * @param[out] handle Pointer to the I3C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I3C_MasterTransferCreateHandle(I3C_Type *base, + i3c_master_handle_t *handle, + const i3c_master_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C/I3C bus. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I3C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I3C peripheral's IRQ priority. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. + */ +void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup i3c_slave_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the I3C slave peripheral. + * + * This function provides the following default configuration for the I3C slave peripheral: + * @code + * slaveConfig->enableslave = true; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the slave driver with I3C_SlaveInit(). + * + * @param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. + */ +void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I3C slave peripheral. + * + * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user + * provided configuration. + * + * @param base The I3C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of + * defaults that you can override. + * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + */ +void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz); + +/*! + * @brief Deinitializes the I3C slave peripheral. + * + * This function disables the I3C slave peripheral and gates the clock. + * + * @param base The I3C peripheral base address. + */ +void I3C_SlaveDeinit(I3C_Type *base); + +/*! + * @brief Enable/Disable Slave. + * + * @param base The I3C peripheral base address. + * @param isEnable Enable or disable. + */ +static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable) +{ + base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the I3C slave status flags. + * + * A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_slave_flags + */ +static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base) +{ + return base->SSTATUS & ~(I3C_SSTATUS_EVDET_MASK | I3C_SSTATUS_ACTSTATE_MASK | I3C_SSTATUS_TIMECTRL_MASK); +} + +/*! + * @brief Clears the I3C slave status flag state. + * + * The following status register flags can be cleared: + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i3c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_SlaveGetStatusFlags(). + * @see _i3c_slave_flags. + */ +static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->SSTATUS = statusMask; +} + +/*! + * @brief Gets the I3C slave error status flags. + * + * A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the error status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_slave_error_flags + */ +static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base) +{ + return base->SERRWARN; +} + +/*! + * @brief Clears the I3C slave error status flag state. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of + * #_i3c_slave_error_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_SlaveGetErrorStatusFlags(). + * @see _i3c_slave_error_flags. + */ +static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->SERRWARN = statusMask; +} + +/*! + * @brief Gets the I3C slave state. + * + * @param base The I3C peripheral base address. + * @return I3C slave activity state, refer #i3c_slave_activity_state_t. + */ +i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status); +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the I3C slave interrupt requests. + * + * Only below flags can be enabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i3c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->SINTSET |= interruptMask; +} + +/*! + * @brief Disables the I3C slave interrupt requests. + * + * Only below flags can be disabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i3c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->SINTCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I3C slave interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base) +{ + return base->SINTSET; +} + +/*! + * @brief Returns the set of pending I3C slave interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the + * set of pending interrupts. + */ +static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base) +{ + return base->SINTMASKED; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables I3C slave DMA requests. + * + * @param base The I3C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + * @param width DMA read/write unit in bytes. + */ +static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) +{ + assert(width <= 2U); + base->SDMACTRL = + I3C_SDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_SDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_SDMACTRL_DMAWIDTH(width); +} + +/*! + * @brief Gets I3C slave transmit data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Slave Transmit Data Register address. + */ +static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->SWDATAH : &base->SWDATAB); +} + +/*! + * @brief Gets I3C slave receive data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Slave Receive Data Register address. + */ +static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB); +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for I3C slave FIFOs. + * + * @param base The I3C peripheral base address. + * @param txLvl Transmit FIFO watermark level. The #kI3C_SlaveTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO reaches @a txLvl. + * @param rxLvl Receive FIFO watermark level. The #kI3C_SlaveRxReadyFlag flag is set whenever + * the number of words in the receive FIFO reaches @a rxLvl. + * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. + * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. + */ +static inline void I3C_SlaveSetWatermarks( + I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) +{ + base->SDATACTRL = I3C_SDATACTRL_UNLOCK_MASK | I3C_SDATACTRL_TXTRIG(txLvl) | I3C_SDATACTRL_RXTRIG(rxLvl) | + (flushTx ? I3C_SDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_SDATACTRL_FLUSHFB_MASK : 0U); +} + +/*! + * @brief Gets the current number of bytes in the I3C slave FIFOs. + * + * @param base The I3C peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->SDATACTRL & I3C_SDATACTRL_TXCOUNT_MASK) >> I3C_SDATACTRL_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK) >> I3C_SDATACTRL_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) +/*! + * @brief I3C slave request event. + * + * @param base The I3C peripheral base address. + * @param event I3C slave event of type #i3c_slave_event_t + */ +void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event); +#endif + +/*! + * @brief Performs a polling send transfer on the I3C bus. + * + * @param base The I3C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I3C bus. + * + * @param base The I3C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the I3C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The I3C peripheral base address. + * @param[out] handle Pointer to the I3C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I3C_SlaveTransferCreateHandle(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. + */ +status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The I3C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress + */ +status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @retval #kStatus_Success + * @retval #kStatus_I3C_Idle + */ +void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + */ +void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) +/*! + * @brief I3C slave request IBI event with data payload(mandatory and extended). + * + * @param base The I3C peripheral base address. + * @param data Pointer to IBI data to be sent in the request. + * @param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize); + +/*! + * @brief I3C slave request IBI event with single data. + * @deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData. + * + * @param base The I3C peripheral base address. + * @param data IBI data to be sent in the request. + * @param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize); +#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */ + +/*@}*/ +/*! @} */ +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_I3C_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c_edma.c new file mode 100644 index 0000000000..7601d3c7c0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c_edma.c @@ -0,0 +1,1055 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i3c_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i3c_edma" +#endif + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i3c_edma_transfer_states +{ + kIdleState = 0, + kIBIWonState, + kSlaveStartState, + kSendCommandState, + kWaitRepeatedStartCompleteState, + kTransmitDataState, + kReceiveDataState, + kStopState, + kWaitForCompletionState, + kAddressMatchState, +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i3c_edma_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterDMAIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveDMAIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | + kI3C_SlaveBusStopFlag | /*kI3C_SlaveRxReadyFlag |*/ + kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | + kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | + kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | + kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | + kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, +}; +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map I3C instance number to base pointer. */ +static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS; + +/*! @brief Array to store the END byte of I3C teransfer. */ +static uint8_t i3cEndByte[ARRAY_SIZE(kI3cBases)] = {0}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void I3C_MasterTransferEDMACallbackRx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + + if (transferDone) + { + /* Terminate following data if present. */ + i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U); + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.dataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_MasterGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.data + i3cHandle->transfer.dataSize - 1U) = + (uint8_t)i3cHandle->base->MRDATAB; + } +#endif + + /* Disable I3C Rx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMAFB_MASK; + } +} + +static void I3C_MasterTransferEDMACallbackTx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + uint32_t instance; + + if (transferDone) + { + /* Disable I3C Tx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMATB_MASK; + + if (i3cHandle->transferCount != 1U) + { + instance = I3C_GetInstance(i3cHandle->base); + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->MDATACTRL & I3C_MDATACTRL_TXFULL_MASK) != 0U) + { + } + i3cHandle->base->MWDATABE = i3cEndByte[instance]; + } + } +} +/*! + * brief Prepares the transfer state machine and fills in the command buffer. + * param handle Master nonblocking driver handle. + */ +static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + i3c_master_transfer_t *xfer = &handle->transfer; + status_t result = kStatus_Success; + i3c_direction_t direction = xfer->direction; + + /* Calculate command count and put into command buffer. */ + handle->subaddressCount = 0U; + if (xfer->subaddressSize != 0U) + { + for (uint32_t i = xfer->subaddressSize; i > 0U; i--) + { + handle->subaddressBuffer[handle->subaddressCount++] = (uint8_t)((xfer->subaddress) >> (8U * (i - 1U))); + } + } + + /* Start condition shall be ommited, switch directly to next phase */ + if (xfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (xfer->subaddressSize > 0UL) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI3C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kTransmitDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + } + else + { + if (xfer->subaddressSize != 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (handle->transfer.direction == kI3C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI3C_Read) + { + handle->state = (uint8_t)kReceiveDataState; + } + else + { + return kStatus_InvalidArgument; + } + } + + if (handle->transfer.direction == kI3C_Read) + { + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Read); + } + + if (handle->state != (uint8_t)kStopState) + { + /* If repeated start is requested, send repeated start. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); + } + } + } + + I3C_MasterTransferEDMAHandleIRQ(base, handle); + return result; +} + +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction) +{ + bool isEnableTxDMA = false; + bool isEnableRxDMA = false; + edma_transfer_config_t xferConfig; + uint32_t instance; + uint32_t address; + uint32_t width; + + handle->transferCount = dataSize; + + switch (direction) + { + case kI3C_Write: + if (dataSize != 1U) + { + address = (uint32_t)&base->MWDATAB1; + /* Cause controller sends command and data with same interface, need special buffer to store the END byte. */ + instance = I3C_GetInstance(base); + i3cEndByte[instance] = *(uint8_t *)((uint32_t)(uint32_t *)data + dataSize - 1U); + dataSize--; + } + else + { + address = (uint32_t)&base->MWDATABE; + } + EDMA_PrepareTransfer(&xferConfig, data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), 1, dataSize, + kEDMA_MemoryToPeripheral); + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txDmaHandle); + isEnableTxDMA = true; + width = 1U; + break; + + case kI3C_Read: +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + address = (uint32_t)&base->MRDATAB; + EDMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), data, sizeof(uint8_t), 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxDmaHandle); + isEnableRxDMA = true; + width = 1U; + break; + + default: + /* This should never happen */ + assert(false); + break; + } + + I3C_MasterEnableDMA(base, isEnableTxDMA, isEnableRxDMA, width); +} + +static status_t I3C_MasterRunTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t errStatus; + status_t result = kStatus_Success; + i3c_master_transfer_t *xfer; + size_t rxCount = 0; + bool state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = (uint32_t)I3C_MasterGetPendingInterrupts(base); + I3C_MasterClearStatusFlags(base, status); + + i3c_master_state_t masterState = I3C_MasterGetState(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } + + if (0UL != (status & (uint32_t)kI3C_MasterSlave2MasterFlag)) + { + if (handle->callback.slave2Master != NULL) + { + handle->callback.slave2Master(base, handle->userData); + } + } + + if ((0UL != (status & (uint32_t)kI3C_MasterSlaveStartFlag)) && (handle->transfer.busType != kI3C_TypeI2C)) + { + handle->state = (uint8_t)kSlaveStartState; + } + + if ((masterState == kI3C_MasterStateIbiRcv) || (masterState == kI3C_MasterStateIbiAck)) + { + handle->state = (uint8_t)kIBIWonState; + } + + if (handle->state == (uint8_t)kIdleState) + { + return result; + } + + if (handle->state == (uint8_t)kIBIWonState) + { + /* Get fifo counts and compute room in tx fifo. */ + rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; + } + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSlaveStartState: + /* Emit start + 0x7E */ + I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); + handle->state = (uint8_t)kIBIWonState; + state_complete = true; + break; + + case (uint8_t)kIBIWonState: + if (masterState == kI3C_MasterStateIbiAck) + { + handle->ibiType = I3C_GetIBIType(base); + if (handle->callback.ibiCallback != NULL) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); + } + else + { + I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); + } + } + + /* Make sure there is data in the rx fifo. */ + if (0UL != rxCount) + { + if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); + } + uint8_t tempData = (uint8_t)base->MRDATAB; + if (handle->ibiBuff != NULL) + { + handle->ibiBuff[handle->ibiPayloadSize++] = tempData; + } + rxCount--; + break; + } + else if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->ibiType = I3C_GetIBIType(base); + handle->ibiAddress = I3C_GetIBIAddress(base); + state_complete = true; + result = kStatus_I3C_IBIWon; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kSendCommandState: + I3C_MasterRunEDMATransfer(base, handle, handle->subaddressBuffer, handle->subaddressCount, kI3C_Write); + + if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize)) + { + if (0UL == xfer->dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } + } + else + { + /* Next state, transfer data. */ + handle->state = (uint8_t)kTransmitDataState; + } + + state_complete = true; + break; + + case (uint8_t)kWaitRepeatedStartCompleteState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kReceiveDataState; + /* Send repeated start and slave address. */ + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, kI3C_Read); + } + + state_complete = true; + break; + + case (uint8_t)kTransmitDataState: + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Write); + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kReceiveDataState: + /* Do DMA read. */ + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kWaitForCompletionState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kStopState; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if (0UL == (xfer->flags & (uint32_t)kI3C_TransferNoStopFlag)) + { + if (xfer->busType == kI3C_TypeI3CDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + } + } + *isDone = true; + state_complete = true; + break; + + default: + assert(false); + break; + } + } + return result; +} + +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = *callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cMasterIsr = I3C_MasterTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_MasterTransferEDMACallbackRx, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_MasterTransferEDMACallbackTx, handle); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterDMAIrqFlags); +} + +/*! + * brief Performs a non-blocking DMA transaction on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I3C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts( + base, ((uint32_t)kMasterDMAIrqFlags | (uint32_t)kI3C_MasterRxReadyFlag | (uint32_t)kI3C_MasterTxReadyFlag)); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Configure IBI response type. */ + base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; + base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Generate commands to send. */ + (void)I3C_MasterInitTransferStateMachineEDMA(base, handle); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_MasterEnableInterrupts(base, (uint32_t)(kMasterDMAIrqFlags)); + + if (transfer->busType == kI3C_TypeI2C) + { + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterSlaveStartFlag); + } + + return kStatus_Success; +} + +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + i3c_master_edma_handle_t *handle = (i3c_master_edma_handle_t *)i3cHandle; + + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I3C_MasterRunTransferStateMachineEDMA(base, handle, &isDone); + + if (handle->state == (uint8_t)kIdleState) + { + return; + } + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + } + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke IBI user callback. */ + if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); + handle->ibiPayloadSize = 0; + } + + /* Invoke callback. */ + if (NULL != handle->callback.transferComplete) + { + handle->callback.transferComplete(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + i3c_direction_t dir = handle->transfer.direction; + + if (dir == kI3C_Read) + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + } + else + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel); + } + + return kStatus_Success; +} + +/*! + * brief Abort a master edma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_MasterEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Send a stop command to finalize the transfer. */ + (void)I3C_MasterStop(base); + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +static void I3C_SlaveTransferEDMACallback(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_slave_edma_handle_t *i3cHandle = (i3c_slave_edma_handle_t *)param; + + if (transferDone) + { + /* Simply disable dma enablement */ + if (i3cHandle->txDmaHandle == dmaHandle) + { + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMATB_MASK; + + if (i3cHandle->transfer.txDataSize > 1U) + { + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->SDATACTRL & I3C_SDATACTRL_TXFULL_MASK) != 0U) + { + } + /* Send the last byte. */ + i3cHandle->base->SWDATABE = *(uint8_t *)((uintptr_t)i3cHandle->transfer.txData + i3cHandle->transfer.txDataSize - 1U); + } + } + else + { +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.rxDataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_SlaveGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.rxData + i3cHandle->transfer.rxDataSize - 1U) = + (uint8_t)i3cHandle->base->SRDATAB; + } +#endif + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMAFB_MASK; + } + } +} + +/*! + * brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + * param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cSlaveIsr = I3C_SlaveTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_SlaveTransferEDMACallback, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_SlaveTransferEDMACallback, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Enable IRQ. */ + I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); +} + +static void I3C_SlavePrepareTxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + edma_transfer_config_t txConfig; + uint32_t *txFifoBase; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + + if (xfer->txDataSize == 1U) + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATABE; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize, + kEDMA_MemoryToPeripheral); + } + else + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATAB1; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize - 1U, + kEDMA_MemoryToPeripheral); + } + + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &txConfig); + EDMA_StartTransfer(handle->txDmaHandle); +} + +static void I3C_SlavePrepareRxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + uint32_t *rxFifoBase = (uint32_t *)(uintptr_t)&base->SRDATAB; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + size_t dataSize = xfer->rxDataSize; + edma_transfer_config_t rxConfig; + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + + EDMA_PrepareTransfer(&rxConfig, (void *)rxFifoBase, 1, xfer->rxData, 1, 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &rxConfig); + EDMA_StartTransfer(handle->rxDmaHandle); +} + +/*! + * brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param transfer The pointer to the transfer descriptor. + * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask) +{ + assert(NULL != handle); + assert(NULL != transfer); + + bool txDmaEn = false, rxDmaEn = false; + uint32_t width; + + if (handle->isBusy) + { + return kStatus_I3C_Busy; + } + /* Clear all flags. */ + I3C_SlaveClearErrorStatusFlags(base, (uint32_t)kSlaveErrorFlags); + I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + + handle->transfer = *transfer; + + /* Set up event mask. */ + handle->eventMask = eventMask; + + if ((transfer->txData != NULL) && (transfer->txDataSize != 0U)) + { + I3C_SlavePrepareTxEDMA(base, handle); + txDmaEn = true; + width = 1U; + } + + if ((transfer->rxData != NULL) && (transfer->rxDataSize != 0U)) + { + I3C_SlavePrepareRxEDMA(base, handle); + rxDmaEn = true; + width = 1U; + } + + if (txDmaEn || rxDmaEn) + { + I3C_SlaveEnableDMA(base, txDmaEn, rxDmaEn, width); + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + uint32_t flags; + uint32_t errFlags; + i3c_slave_edma_transfer_t *xfer; + + i3c_slave_edma_handle_t *handle = (i3c_slave_edma_handle_t *)i3cHandle; + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL == handle) + { + return; + } + + xfer = &handle->transfer; + + /* Get status flags. */ + flags = I3C_SlaveGetStatusFlags(base); + errFlags = I3C_SlaveGetErrorStatusFlags(base); + + /* Clear status flags. */ + I3C_SlaveClearStatusFlags(base, flags); + + if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); + + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + return; + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveEventSentFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) + { + handle->isBusy = true; + xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveBusStopFlag)) + { + if (handle->isBusy == true) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + I3C_SlaveTransferAbortEDMA(base, handle); + } + else + { + return; + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveMatchedFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; + handle->isBusy = true; + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } +} + +/*! + * brief Abort a slave dma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + if (handle->isBusy != false) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_SlaveEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + } +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c_edma.h new file mode 100644 index 0000000000..1e896e8de6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_i3c_edma.h @@ -0,0 +1,279 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_I3C_EDMA_H_ +#define FSL_I3C_EDMA_H_ + +#include "fsl_i3c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I3C EDMA driver version. */ +#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 8)) +/*@}*/ + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t; + +/*! @brief i3c master callback functions. */ +typedef struct _i3c_master_edma_callback +{ + void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ + void (*ibiCallback)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + i3c_ibi_type_t ibiType, + i3c_ibi_state_t ibiState); /*!< IBI event callback */ + void (*transferComplete)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ +} i3c_master_edma_callback_t; +/*! + * @brief Driver handle for master EDMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_master_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint8_t subaddressBuffer[4]; /*!< Saving subaddress command. */ + uint8_t subaddressCount; /*!< Saving command count. */ + i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i3c_master_edma_callback_t callback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + uint8_t ibiAddress; /*!< Slave address which request IBI. */ + uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ + size_t ibiPayloadSize; /*!< IBI payload size. */ + i3c_ibi_type_t ibiType; /*!< IBI type. */ +}; + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t; + +/*! @brief I3C slave transfer structure */ +typedef struct _i3c_slave_edma_transfer +{ + uint32_t event; /*!< Reason the callback is being invoked. */ + uint8_t *txData; /*!< Transfer buffer */ + size_t txDataSize; /*!< Transfer size */ + uint8_t *rxData; /*!< Transfer buffer */ + size_t rxDataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI3C_SlaveCompletionEvent. */ +} i3c_slave_edma_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave DMA transfer API. + * + * @param base Base address for the I3C instance on which the event occurred. + * @param handle Pointer to slave DMA transfer handle. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData); +/*! + * @brief I3C slave edma handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_slave_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + i3c_slave_edma_transfer_t transfer; /*!< I3C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + i3c_slave_edma_callback_t callback; /*!< Callback function called at transfer event. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; +/*! @} */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*@{*/ + +/*! + * @brief Create a new handle for the I3C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I3C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I3C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * DMA peripheral's IRQ priority. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master DMA driver handle. + */ +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ + +/*! @name Slave DMA */ +/*@{*/ +/*! + * @brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param transfer The pointer to the transfer descriptor. + * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * @retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask); +/*! + * @brief Abort a slave edma non-blocking transfer in a early time + * + * @param base I3C peripheral base address + * @param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave DMA driver handle. + */ +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*@}*/ + +/*! @} */ +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_I3C_EDMA_H_ */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux.c new file mode 100644 index 0000000000..1f2ce0bcd2 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + +#if defined(INPUTMUX_RSTS) +#define INPUTMUX_RESETS_ARRAY INPUTMUX_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! + * @brief Get instance number for INPUTMUX module. + * + * @param base INPUTMUX peripheral base address + */ +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! @brief Pointers to INPUTMUX bases for each instance. */ +static INPUTMUX_Type *const s_inputmuxBases[] = INPUTMUX_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_inputmuxResets[] = INPUTMUX_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_inputmuxBases); instance++) + { + if (s_inputmuxBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_inputmuxBases)); + + return instance; +} +#endif + +/*! + * brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE +#if (defined(FSL_FEATURE_SOC_SCT_COUNT) && (FSL_FEATURE_SOC_SCT_COUNT > 0)) + CLOCK_EnableClock(kCLOCK_Sct); +#endif /* FSL_FEATURE_SOC_SCT_COUNT */ + CLOCK_EnableClock(kCLOCK_Dma); +#else + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(INPUTMUX_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_inputmuxResets[INPUTMUX_GetInstance(base)]); +#endif +} + +/*! + * brief Attaches a signal + * + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter p index specified as 2, this function configures register PINT_SEL2. + * + * param base Base address of the INPUTMUX peripheral. + * param index The serial number of destination register in the group of INPUTMUX registers with same name. + * param connection Applies signal from source signals collection to target signal. + * + * retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; +} + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param signal Enable signal register id and bit offset. + * param enable Selects enable or disable. + * + * retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; + uint32_t bit_offset; + +#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX + uint32_t chmux_offset; + uint32_t chmux_value; + + /* Only enable need to update channel mux */ + if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) + { + chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); + chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); + *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; + } + ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; +#endif + /* extract enable register to be used */ + ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; + /* extract enable bit offset */ + bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); + } +} +#endif + +/*! + * brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE +#if (defined(FSL_FEATURE_SOC_SCT_COUNT) && (FSL_FEATURE_SOC_SCT_COUNT > 0)) + CLOCK_DisableClock(kCLOCK_Sct); +#endif /* FSL_FEATURE_SOC_SCT_COUNT */ + CLOCK_DisableClock(kCLOCK_Dma); +#else + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux.h new file mode 100644 index 0000000000..c3cf9ccdd0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_INPUTMUX_H_ +#define FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * @code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * @endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter @p index specified as 2, this function configures register PINT_SEL2. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index The serial number of destination register in the group of INPUTMUX registers with same name. + * @param connection Applies signal from source signals collection to target signal. + * + * @retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux_connections.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux_connections.h new file mode 100644 index 0000000000..629a6aa25e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_inputmux_connections.h @@ -0,0 +1,3664 @@ +/* + * Copyright 2022 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define TIMER0CAPTSEL0 0x20U +#define TIMER0TRIGIN 0x30U +#define TIMER1CAPTSEL0 0x40U +#define TIMER1TRIGIN 0x50U +#define TIMER2CAPTSEL0 0x60U +#define TIMER2TRIGIN 0x70U +#define SMARTDMAARCHB_INMUX0 0xA0U +#define PINTSEL0 0xC0U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TAR_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER3TRIGIN 0x1B0U +#define TIMER4CAPTSEL0 0x1C0U +#define TIMER4TRIGIN 0x1D0U +#define CMP0_TRIG_REG 0x260U +#define ADC0_TRIG0 0x280U +#define ADC1_TRIG0 0x2C0U +#define QDC0_TRIG_REG 0x360U +#define QDC0_HOME_REG 0x364U +#define QDC0_INDEX_REG 0x368U +#define QDC0_PHASEB_REG 0x36CU +#define QDC0_PHASEA_REG 0x370U +#define QDC1_TRIG_REG 0x380U +#define QDC1_HOME_REG 0x384U +#define QDC1_INDEX_REG 0x388U +#define QDC1_PHASEB_REG 0x38CU +#define QDC1_PHASEA_REG 0x390U +#define FlexPWM0_SM0_EXTSYNC_REG 0x3A0U +#define FlexPWM0_SM1_EXTSYNC_REG 0x3A4U +#define FlexPWM0_SM2_EXTSYNC_REG 0x3A8U +#define FlexPWM0_SM3_EXTSYNC_REG 0x3ACU +#define FlexPWM0_SM0_EXTA_REG 0x3B0U +#define FlexPWM0_SM1_EXTA_REG 0x3B4U +#define FlexPWM0_SM2_EXTA_REG 0x3B8U +#define FlexPWM0_SM3_EXTA_REG 0x3BCU +#define FlexPWM0_EXTFORCE_REG 0x3C0U +#define FlexPWM0_FAULT0_REG 0x3C4U +#define FlexPWM0_FAULT1_REG 0x3C8U +#define FlexPWM0_FAULT2_REG 0x3CCU +#define FlexPWM0_FAULT3_REG 0x3D0U +#define FlexPWM1_SM0_EXTSYNC_REG 0x3E0U +#define FlexPWM1_SM1_EXTSYNC_REG 0x3E4U +#define FlexPWM1_SM2_EXTSYNC_REG 0x3E8U +#define FlexPWM1_SM3_EXTSYNC_REG 0x3ECU +#define FlexPWM1_SM0_EXTA_REG 0x3F0U +#define FlexPWM1_SM1_EXTA_REG 0x3F4U +#define FlexPWM1_SM2_EXTA_REG 0x3F8U +#define FlexPWM1_SM3_EXTA_REG 0x3FCU +#define FlexPWM1_EXTFORCE_REG 0x400U +#define FlexPWM1_FAULT0_REG 0x404U +#define FlexPWM1_FAULT1_REG 0x408U +#define FlexPWM1_FAULT2_REG 0x40CU +#define FlexPWM1_FAULT3_REG 0x410U +#define PWM0_EXT_CLK_REG 0x420U +#define PWM1_EXT_CLK_REG 0x424U +#define EVTG_TRIG0_REG 0x440U +#define EXT_TRIG0_REG 0x4C0U +#define CMP1_TRIG_REG 0x4E0U +#define FLEXCOMM0_TRIG_REG 0x5A0U +#define FLEXCOMM1_TRIG_REG 0x5C0U +#define FLEXCOMM2_TRIG_REG 0x5E0U +#define FLEXCOMM3_TRIG_REG 0x600U +#define FLEXCOMM4_TRIG_REG 0x620U +#define FLEXCOMM5_TRIG_REG 0x640U +#define FLEXCOMM6_TRIG_REG 0x660U +#define FLEXCOMM7_TRIG_REG 0x680U +#define FLEXIO_TRIG0_REG 0x6E0U + +#define DMA0_REQ_ENABLE0_REG 0x700U +#define DMA0_REQ_ENABLE1_REG 0x710U +#define DMA0_REQ_ENABLE2_REG 0x720U +#define DMA0_REQ_ENABLE3_REG 0x730U +#define DMA1_REQ_ENABLE0_REG 0x780U +#define DMA1_REQ_ENABLE1_REG 0x790U +#define DMA1_REQ_ENABLE2_REG 0x7A0U +#define DMA1_REQ_ENABLE3_REG 0x7B0U + +#define ENA_SHIFT 8U +#define PMUX_SHIFT 20U + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer0Captsel = 32U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer0Captsel = 47U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer0Captsel = 50U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer0Captsel = 51U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer0Captsel = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer0Captsel = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer0Captsel = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer0Captsel = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer0Captsel = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer0Captsel = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer0Captsel = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer0Captsel = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer0Captsel = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer0Captsel = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer1Captsel = 32U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer1Captsel = 47U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer1Captsel = 50U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer1Captsel = 51U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer1Captsel = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer1Captsel = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer1Captsel = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer1Captsel = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer1Captsel = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer1Captsel = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer1Captsel = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer1Captsel = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer1Captsel = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer1Captsel = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer2Captsel = 32U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer2Captsel = 47U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer2Captsel = 50U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer2Captsel = 51U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer2Captsel = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer2Captsel = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer2Captsel = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer2Captsel = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer2Captsel = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer2Captsel = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer2Captsel = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer2Captsel = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer2Captsel = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer2Captsel = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer3Captsel = 32U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer3Captsel = 47U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer3Captsel = 50U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer3Captsel = 51U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer3Captsel = 52U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer3Captsel = 53U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer3Captsel = 54U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer3Captsel = 55U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer3Captsel = 56U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer3Captsel = 57U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer3Captsel = 58U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer3Captsel = 59U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer3Captsel = 60U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer3Captsel = 61U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer3Captsel = 62U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer3Captsel = 63U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer3Captsel = 64U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer4Captsel = 32U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer4Captsel = 47U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer4Captsel = 50U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer4Captsel = 51U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer4Captsel = 52U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer4Captsel = 53U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer4Captsel = 54U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer4Captsel = 55U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer4Captsel = 56U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer4Captsel = 57U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer4Captsel = 58U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer4Captsel = 59U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer4Captsel = 60U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer4Captsel = 61U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer4Captsel = 62U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer4Captsel = 63U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer4Captsel = 64U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER0 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer0Trigger = 0U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer0Trigger = 21U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer0Trigger = 32U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer0Trigger = 47U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer0Trigger = 50U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer0Trigger = 51U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer0Trigger = 52U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer0Trigger = 53U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer0Trigger = 54U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer0Trigger = 55U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer0Trigger = 56U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer0Trigger = 58U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer0Trigger = 59U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer0Trigger = 61U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer0Trigger = 62U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer0Trigger = 64U + (TIMER0TRIGIN << PMUX_SHIFT), + + /*!< TIMER1 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer1Trigger = 0U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer1Trigger = 21U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer1Trigger = 32U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer1Trigger = 47U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer1Trigger = 50U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer1Trigger = 51U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer1Trigger = 52U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer1Trigger = 53U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer1Trigger = 54U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer1Trigger = 55U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer1Trigger = 56U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer1Trigger = 58U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer1Trigger = 59U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer1Trigger = 61U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer1Trigger = 62U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer1Trigger = 64U + (TIMER1TRIGIN << PMUX_SHIFT), + + /*!< TIMER2 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer2Trigger = 0U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer2Trigger = 21U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer2Trigger = 32U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer2Trigger = 47U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer2Trigger = 50U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer2Trigger = 51U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer2Trigger = 52U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer2Trigger = 53U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer2Trigger = 54U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer2Trigger = 55U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer2Trigger = 56U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer2Trigger = 58U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer2Trigger = 59U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer2Trigger = 61U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer2Trigger = 62U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer2Trigger = 64U + (TIMER2TRIGIN << PMUX_SHIFT), + + /*!< TIMER3 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer3Trigger = 0U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer3Trigger = 21U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer3Trigger = 32U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer3Trigger = 47U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer3Trigger = 50U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer3Trigger = 51U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer3Trigger = 52U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer3Trigger = 53U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer3Trigger = 54U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer3Trigger = 55U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer3Trigger = 56U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer3Trigger = 57U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer3Trigger = 58U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer3Trigger = 59U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer3Trigger = 60U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer3Trigger = 61U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer3Trigger = 62U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer3Trigger = 63U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer3Trigger = 64U + (TIMER3TRIGIN << PMUX_SHIFT), + + /*!< TIMER4 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer4Trigger = 0U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameToTimer4Trigger = 21U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_DcdcBurstActiveToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0TxSyncOutToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai0RxSyncOutToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToTimer4Trigger = 32U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToTimer4Trigger = 47U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig0ToTimer4Trigger = 50U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig1ToTimer4Trigger = 51U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0Trig2ToTimer4Trigger = 52U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig0ToTimer4Trigger = 53U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig1ToTimer4Trigger = 54U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1Trig2ToTimer4Trigger = 55U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig0ToTimer4Trigger = 56U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig1ToTimer4Trigger = 57U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2Trig2ToTimer4Trigger = 58U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig0ToTimer4Trigger = 59U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig1ToTimer4Trigger = 60U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig2ToTimer4Trigger = 61U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3Trig3ToTimer4Trigger = 62U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1TxSyncOutToTimer4Trigger = 63U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Sai1RxSyncOutToTimer4Trigger = 64U + (TIMER4TRIGIN << PMUX_SHIFT), + + /*!< SMARTDMA arch B inputs. */ + kINPUTMUX_GpioPort0Pin0ToSmartDma = 0U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToSmartDma = 1U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToSmartDma = 2U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToSmartDma = 3U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToSmartDma = 4U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToSmartDma = 5U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToSmartDma = 6U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToSmartDma = 7U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToSmartDma = 12U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToSmartDma = 13U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToSmartDma = 14U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToSmartDma = 15U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_MrtCh0IrqToSmartDma = 20U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_MrtCh1IrqToSmartDma = 21U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToSmartDma = 22U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToSmartDma = 23U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToSmartDma = 24U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToSmartDma = 25U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToSmartDma = 26U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToSmartDma = 27U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_UtickIrqToSmartDma = 28U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Wdt0IrqToSmartDma = 29U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToSmartDma = 30U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp0IrqToSmartDma = 31U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm7IrqToSmartDma = 33U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm6IrqToSmartDma = 34U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm5IrqToSmartDma = 35U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm4IrqToSmartDma = 36U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm3IrqToSmartDma = 37U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm2IrqToSmartDma = 38U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm1IrqToSmartDma = 39U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_LpFlexcomm0IrqToSmartDma = 40U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0IrqToSmartDma = 41U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1IrqToSmartDma = 42U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SysIrqToSmartDma = 43U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_RtcComboIrqToSmartDma = 44U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSmartDma = 45U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToSmartDma = 46U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToSmartDma = 49U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameIrqToSmartDma = 50U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Usb1StartOfFrameIrqToSmartDma = 51U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_OsEventTimerIrqToSmartDma = 52U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToSmartDma = 53U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Cmp01IrqToSmartDma = 54U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm0IrqToSmartDma = 57U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Pwm1IrqToSmartDma = 58U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc0IrqToSmartDma = 59U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Qdc1IrqToSmartDma = 60U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToSmartDma = 61U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToSmartDma = 62U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToSmartDma = 65U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig1ToSmartDma = 66U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToSmartDma = 67U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToSmartDma = 68U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToSmartDma = 69U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToSmartDma = 70U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest0ToSmartDma = 71U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest1ToSmartDma = 72U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest2ToSmartDma = 73U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest3ToSmartDma = 74U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest4ToSmartDma = 75U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest5ToSmartDma = 76U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest6ToSmartDma = 77U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + kINPUTMUX_FlexioShifterDmaRequest7ToSmartDma = 78U + (SMARTDMAARCHB_INMUX0 << PMUX_SHIFT), + + /*!< Pin interrupt select. */ + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ClkInToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro144MToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_CpuAhbClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ClkInToFreqmeasTar = 0U + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MToFreqmeasTar = 1u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Fro144MToFreqmeasTar = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToFreqmeasTar = 4u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_CpuAhbClkToFreqmeasTar = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasTar = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasTar = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFreqmeasTar = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFreqmeasTar = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + + /*!< Cmp0 Trigger. */ + kINPUTMUX_PinInt0ToCmp0Trigger = 0U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToCmp0Trigger = 1U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToCmp0Trigger = 5U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToCmp0Trigger = 6U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToCmp0Trigger = 7U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp0Trigger = 8U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp0Trigger = 9U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToCmp0Trigger = 11U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToCmp0Trigger = 12U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToCmp0Trigger = 13U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToCmp0Trigger = 14U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToCmp0Trigger = 17U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToCmp0Trigger = 18U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToCmp0Trigger = 19U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToCmp0Trigger = 20U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToCmp0Trigger = 21U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToCmp0Trigger = 22U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToCmp0Trigger = 23U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToCmp0Trigger = 24U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToCmp0Trigger = 30U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToCmp0Trigger = 31U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToCmp0Trigger = 32U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToCmp0Trigger = 33U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToCmp0Trigger = 34U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp0Trigger = 35U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToCmp0Trigger = 36U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 37U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToCmp0Trigger = 38U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 39U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToCmp0Trigger = 40U + (CMP0_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp1 Trigger. */ + kINPUTMUX_PinInt0ToCmp1Trigger = 0U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToCmp1Trigger = 1U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToCmp1Trigger = 5U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToCmp1Trigger = 6U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToCmp1Trigger = 7U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp1Trigger = 8U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp1Trigger = 9U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToCmp1Trigger = 11U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToCmp1Trigger = 12U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToCmp1Trigger = 13U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToCmp1Trigger = 14U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToCmp1Trigger = 17U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToCmp1Trigger = 18U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToCmp1Trigger = 19U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToCmp1Trigger = 20U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToCmp1Trigger = 21U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToCmp1Trigger = 22U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToCmp1Trigger = 23U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToCmp1Trigger = 24U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToCmp1Trigger = 30U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToCmp1Trigger = 31U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToCmp1Trigger = 32U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToCmp1Trigger = 33U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToCmp1Trigger = 34U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp1Trigger = 35U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToCmp1Trigger = 36U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 37U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToCmp1Trigger = 38U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 39U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToCmp1Trigger = 40U + (CMP1_TRIG_REG << PMUX_SHIFT), + + + /*!< Adc0 Trigger. */ + kINPUTMUX_PinInt0ToAdc0Trigger = 0U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToAdc0Trigger = 1U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc0Trigger = 5U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc0Trigger = 6U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc0Trigger = 7U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAdc0Trigger = 8U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAdc0Trigger = 9U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstDoneTrigToAdc0Trigger = 10U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc0Trigger = 11U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToAdc0Trigger = 12U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc0Trigger = 13U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc0Trigger = 14U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc0Trigger = 15U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc0Trigger = 16U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 17U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 18U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 19U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 20U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc0Trigger = 21U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc0Trigger = 22U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToAdc0Trigger = 24U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToAdc0Trigger = 25U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToAdc0Trigger = 26U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToAdc0Trigger = 27U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToAdc0Trigger = 28U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToAdc0Trigger = 29U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToAdc0Trigger = 30U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToAdc0Trigger = 31U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToAdc0Trigger = 32U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToAdc0Trigger = 33U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToAdc0Trigger = 34U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToAdc0Trigger = 35U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToAdc0Trigger = 36U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToAdc0Trigger = 37U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToAdc0Trigger = 38U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToAdc0Trigger = 39U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc0Trigger = 40U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc0Trigger = 41U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToAdc0Trigger = 42U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToAdc0Trigger = 43U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToAdc0Trigger = 44U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToAdc0Trigger = 45U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToAdc0Trigger = 46U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToAdc0Trigger = 47U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToAdc0Trigger = 48U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToAdc0Trigger = 49U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc0Trigger = 50U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToAdc0Trigger = 51U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc0Trigger = 52U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc0Trigger = 53U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc0Trigger = 54U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc0Trigger = 55U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 61U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToAdc0Trigger = 62U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 63U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToAdc0Trigger = 64U + (ADC0_TRIG0 << PMUX_SHIFT), + kINPUTMUX_WuuToAdc0Trigger = 65U + (ADC0_TRIG0 << PMUX_SHIFT), + + /*!< Adc1 Trigger. */ + kINPUTMUX_PinInt0ToAdc1Trigger = 0U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToAdc1Trigger = 1U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAdc1Trigger = 5U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAdc1Trigger = 6U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAdc1Trigger = 7U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAdc1Trigger = 8U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc1Trigger = 9U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_DcdcBurstDoneTrigToAdc1Trigger = 10U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToAdc1Trigger = 11U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToAdc1Trigger = 12U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 13U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 14U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 15U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 16U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc1Trigger = 17U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc1Trigger = 18U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc1Trigger = 19U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc1Trigger = 20U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc1Trigger = 21U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc1Trigger = 22U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToAdc1Trigger = 24U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToAdc1Trigger = 25U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToAdc1Trigger = 26U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToAdc1Trigger = 27U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToAdc1Trigger = 28U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToAdc1Trigger = 29U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToAdc1Trigger = 30U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToAdc1Trigger = 31U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToAdc1Trigger = 32U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToAdc1Trigger = 33U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToAdc1Trigger = 34U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToAdc1Trigger = 35U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToAdc1Trigger = 36U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToAdc1Trigger = 37U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToAdc1Trigger = 38U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToAdc1Trigger = 39U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToAdc1Trigger = 40U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToAdc1Trigger = 41U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToAdc1Trigger = 42U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToAdc1Trigger = 43U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToAdc1Trigger = 44U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToAdc1Trigger = 45U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToAdc1Trigger = 46U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToAdc1Trigger = 47U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToAdc1Trigger = 48U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToAdc1Trigger = 49U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc1Trigger = 50U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToAdc1Trigger = 51U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc1Trigger = 52U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc1Trigger = 53U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc1Trigger = 54U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc1Trigger = 55U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger = 61U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToAdc1Trigger = 62U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger = 63U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToAdc1Trigger = 64U + (ADC1_TRIG0 << PMUX_SHIFT), + kINPUTMUX_WuuToAdc1Trigger = 65U + (ADC1_TRIG0 << PMUX_SHIFT), + + /*!< QDC0 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Trigger = 0U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Trigger = 1U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Trigger = 5U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Trigger = 6U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Trigger = 7U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Trigger = 8U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Trigger = 9U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Trigger = 11U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Trigger = 12U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Trigger = 13U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Trigger = 14U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Trigger = 15U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Trigger = 16U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Trigger = 17U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Trigger = 18U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Trigger = 19U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Trigger = 20U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Trigger = 21U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Trigger = 22U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Trigger = 24U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Trigger = 25U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Trigger = 26U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Trigger = 27U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Trigger = 28U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Trigger = 29U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Trigger = 30U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Trigger = 31U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Trigger = 32U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Trigger = 33U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Trigger = 34U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Trigger = 35U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Trigger = 41U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Trigger = 42U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Trigger = 43U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Trigger = 44U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Trigger = 45U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Trigger = 46U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Trigger = 47U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Trigger = 48U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Trigger = 49U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Trigger = 50U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Trigger = 51U + (QDC0_TRIG_REG << PMUX_SHIFT), + + /*!< QDC0 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Home = 0U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Home = 1U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Home = 5U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Home = 6U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Home = 7U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Home = 8U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Home = 9U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Home = 11U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Home = 12U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Home = 13U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Home = 14U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Home = 15U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Home = 16U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Home = 17U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Home = 18U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Home = 19U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Home = 20U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Home = 21U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Home = 22U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Home = 24U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Home = 25U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Home = 26U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Home = 27U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Home = 28U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Home = 29U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Home = 30U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Home = 31U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Home = 32U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Home = 33U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Home = 34U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Home = 35U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Home = 41U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Home = 42U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Home = 43U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Home = 44U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Home = 45U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Home = 46U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Home = 47U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Home = 48U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Home = 49U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Home = 50U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Home = 51U + (QDC0_HOME_REG << PMUX_SHIFT), + + /*!< QDC0 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Index = 0U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Index = 1U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Index = 5U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Index = 6U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Index = 7U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Index = 8U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Index = 9U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Index = 11U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Index = 12U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Index = 13U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Index = 14U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Index = 15U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Index = 16U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Index = 17U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Index = 18U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Index = 19U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Index = 20U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Index = 21U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Index = 22U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Index = 24U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Index = 25U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Index = 26U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Index = 27U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Index = 28U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Index = 29U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Index = 30U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Index = 31U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Index = 32U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Index = 33U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Index = 34U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Index = 35U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Index = 41U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Index = 42U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Index = 43U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Index = 44U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Index = 45U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Index = 46U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Index = 47U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Index = 48U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Index = 49U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Index = 50U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Index = 51U + (QDC0_INDEX_REG << PMUX_SHIFT), + + /*!< QDC0 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phaseb = 0U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phaseb = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phaseb = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phaseb = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phaseb = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phaseb = 8U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phaseb = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phaseb = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phaseb = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phaseb = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phaseb = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phaseb = 15U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phaseb = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phaseb = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phaseb = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phaseb = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phaseb = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phaseb = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phaseb = 22U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phaseb = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phaseb = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phaseb = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phaseb = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phaseb = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phaseb = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phaseb = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phaseb = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phaseb = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phaseb = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phaseb = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phaseb = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phaseb = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phaseb = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phaseb = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phaseb = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phaseb = 45U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phaseb = 46U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phaseb = 47U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phaseb = 48U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phaseb = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phaseb = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phaseb = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT), + + /*!< QDC0 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc0Phasea = 0U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc0Phasea = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phasea = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phasea = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phasea = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc0Phasea = 8U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc0Phasea = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc0Phasea = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc0Phasea = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc0Phasea = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc0Phasea = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc0Phasea = 15U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc0Phasea = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc0Phasea = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc0Phasea = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc0Phasea = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc0Phasea = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phasea = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phasea = 22U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc0Phasea = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc0Phasea = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc0Phasea = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc0Phasea = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc0Phasea = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc0Phasea = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc0Phasea = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc0Phasea = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc0Phasea = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc0Phasea = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc0Phasea = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc0Phasea = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc0Phasea = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phasea = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phasea = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phasea = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phasea = 45U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phasea = 46U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phasea = 47U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phasea = 48U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phasea = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phasea = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phasea = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT), + + /*!< QDC1 Trigger Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Trigger = 0U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Trigger = 1U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Trigger = 5U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Trigger = 6U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Trigger = 7U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Trigger = 8U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Trigger = 9U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Trigger = 11U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Trigger = 12U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Trigger = 13U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Trigger = 14U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Trigger = 15U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Trigger = 16U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Trigger = 17U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Trigger = 18U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Trigger = 19U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Trigger = 20U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Trigger = 21U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Trigger = 22U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Trigger = 24U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Trigger = 25U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Trigger = 26U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Trigger = 27U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Trigger = 28U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Trigger = 29U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Trigger = 30U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Trigger = 31U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Trigger = 32U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Trigger = 33U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Trigger = 34U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Trigger = 35U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Trigger = 41U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Trigger = 42U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Trigger = 43U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Trigger = 44U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Trigger = 45U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Trigger = 46U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Trigger = 47U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Trigger = 48U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Trigger = 49U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Trigger = 50U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Trigger = 51U + (QDC1_TRIG_REG << PMUX_SHIFT), + + /*!< QDC1 Home Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Home = 0U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Home = 1U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Home = 5U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Home = 6U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Home = 7U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Home = 8U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Home = 9U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Home = 11U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Home = 12U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Home = 13U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Home = 14U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Home = 15U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Home = 16U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Home = 17U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Home = 18U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Home = 19U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Home = 20U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Home = 21U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Home = 22U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Home = 24U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Home = 25U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Home = 26U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Home = 27U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Home = 28U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Home = 29U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Home = 30U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Home = 31U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Home = 32U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Home = 33U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Home = 34U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Home = 35U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Home = 41U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Home = 42U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Home = 43U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Home = 44U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Home = 45U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Home = 46U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Home = 47U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Home = 48U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Home = 49U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Home = 50U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Home = 51U + (QDC1_HOME_REG << PMUX_SHIFT), + + /*!< QDC1 Index Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Index = 0U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Index = 1U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Index = 5U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Index = 6U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Index = 7U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Index = 8U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Index = 9U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Index = 11U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Index = 12U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Index = 13U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Index = 14U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Index = 15U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Index = 16U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Index = 17U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Index = 18U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Index = 19U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Index = 20U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Index = 21U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Index = 22U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Index = 24U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Index = 25U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Index = 26U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Index = 27U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Index = 28U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Index = 29U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Index = 30U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Index = 31U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Index = 32U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Index = 33U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Index = 34U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Index = 35U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Index = 41U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Index = 42U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Index = 43U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Index = 44U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Index = 45U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Index = 46U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Index = 47U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Index = 48U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Index = 49U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Index = 50U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Index = 51U + (QDC1_INDEX_REG << PMUX_SHIFT), + + /*!< QDC1 Phaseb Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phaseb = 0U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phaseb = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phaseb = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phaseb = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phaseb = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phaseb = 8U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phaseb = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phaseb = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phaseb = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phaseb = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phaseb = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phaseb = 15U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phaseb = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phaseb = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phaseb = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phaseb = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phaseb = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phaseb = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phaseb = 22U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phaseb = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phaseb = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phaseb = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phaseb = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phaseb = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phaseb = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phaseb = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phaseb = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phaseb = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phaseb = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phaseb = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phaseb = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phaseb = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phaseb = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phaseb = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phaseb = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phaseb = 45U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phaseb = 46U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phaseb = 47U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phaseb = 48U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phaseb = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phaseb = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phaseb = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT), + + /*!< QDC1 Phasea Input Connections. */ + kINPUTMUX_PinInt0ToQdc1Phasea = 0U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt4ToQdc1Phasea = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phasea = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phasea = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phasea = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToQdc1Phasea = 8U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToQdc1Phasea = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToQdc1Phasea = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToQdc1Phasea = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToQdc1Phasea = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToQdc1Phasea = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToQdc1Phasea = 15U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToQdc1Phasea = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToQdc1Phasea = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToQdc1Phasea = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToQdc1Phasea = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToQdc1Phasea = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phasea = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phasea = 22U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToQdc1Phasea = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToQdc1Phasea = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToQdc1Phasea = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToQdc1Phasea = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToQdc1Phasea = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToQdc1Phasea = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToQdc1Phasea = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToQdc1Phasea = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToQdc1Phasea = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToQdc1Phasea = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToQdc1Phasea = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToQdc1Phasea = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToQdc1Phasea = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phasea = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phasea = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phasea = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phasea = 45U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phasea = 46U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phasea = 47U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phasea = 48U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phasea = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phasea = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phasea = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm0ExtSync = 0U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm0ExtSync = 1U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0ExtSync = 5U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0ExtSync = 6U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0ExtSync = 7U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm0ExtSync = 8U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm0ExtSync = 9U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm0ExtSync = 11U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm0ExtSync = 12U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm0ExtSync = 13U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm0ExtSync = 14U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm0ExtSync = 15U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm0ExtSync = 16U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm0ExtSync = 17U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm0ExtSync = 18U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm0ExtSync = 19U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm0ExtSync = 20U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0ExtSync = 21U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0ExtSync = 22U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm0ExtSync = 24U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm0ExtSync = 25U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm0ExtSync = 26U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm0ExtSync = 27U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm0ExtSync = 28U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0ExtSync = 29U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0ExtSync = 30U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0ExtSync = 31U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0ExtSync = 32U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0ExtSync = 33U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm0ExtSync = 34U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm0ExtSync = 35U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm0ExtSync = 36U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm0ExtSync = 37U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm0ExtSync = 38U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm0ExtSync = 39U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm0ExtSync = 40U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm0ExtSync = 41U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0ExtSync = 42U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0ExtSync = 43U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0ExtSync = 44U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0ExtSync = 45U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0ExtSync = 46U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0ExtSync = 47U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0ExtSync = 48U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0ExtSync = 49U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0ExtSync = 50U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0ExtSync = 51U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0ExtSync = 57U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm0ExtSync = 58U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0ExtSync = 59U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm0ExtSync = 60U + (FlexPWM0_SM0_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm1ExtSync = 0U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm1ExtSync = 1U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1ExtSync = 5U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1ExtSync = 6U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1ExtSync = 7U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm1ExtSync = 8U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm1ExtSync = 9U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm1ExtSync = 11U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm1ExtSync = 12U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm1ExtSync = 13U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm1ExtSync = 14U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm1ExtSync = 15U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm1ExtSync = 16U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm1ExtSync = 17U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm1ExtSync = 18U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm1ExtSync = 19U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm1ExtSync = 20U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1ExtSync = 21U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1ExtSync = 22U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm1ExtSync = 24U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm1ExtSync = 25U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm1ExtSync = 26U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm1ExtSync = 27U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm1ExtSync = 28U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1ExtSync = 29U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1ExtSync = 30U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1ExtSync = 31U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1ExtSync = 32U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1ExtSync = 33U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm1ExtSync = 34U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm1ExtSync = 35U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm1ExtSync = 36U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm1ExtSync = 37U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm1ExtSync = 38U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm1ExtSync = 39U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm1ExtSync = 40U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm1ExtSync = 41U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1ExtSync = 42U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1ExtSync = 43U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1ExtSync = 44U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1ExtSync = 45U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1ExtSync = 46U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1ExtSync = 47U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1ExtSync = 48U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1ExtSync = 49U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1ExtSync = 50U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1ExtSync = 51U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1ExtSync = 57U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm1ExtSync = 58U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1ExtSync = 59U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm1ExtSync = 60U + (FlexPWM0_SM1_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm2ExtSync = 0U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm2ExtSync = 1U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2ExtSync = 5U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2ExtSync = 6U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2ExtSync = 7U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm2ExtSync = 8U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm2ExtSync = 9U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm2ExtSync = 11U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm2ExtSync = 12U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm2ExtSync = 13U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm2ExtSync = 14U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm2ExtSync = 15U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm2ExtSync = 16U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm2ExtSync = 17U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm2ExtSync = 18U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm2ExtSync = 19U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm2ExtSync = 20U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2ExtSync = 21U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2ExtSync = 22U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm2ExtSync = 24U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm2ExtSync = 25U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm2ExtSync = 26U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm2ExtSync = 27U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm2ExtSync = 28U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2ExtSync = 29U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2ExtSync = 30U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2ExtSync = 31U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2ExtSync = 32U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2ExtSync = 33U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm2ExtSync = 34U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm2ExtSync = 35U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm2ExtSync = 36U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm2ExtSync = 37U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm2ExtSync = 38U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm2ExtSync = 39U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm2ExtSync = 40U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm2ExtSync = 41U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2ExtSync = 42U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2ExtSync = 43U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2ExtSync = 44U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2ExtSync = 45U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2ExtSync = 46U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2ExtSync = 47U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2ExtSync = 48U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2ExtSync = 49U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2ExtSync = 50U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2ExtSync = 51U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2ExtSync = 57U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm2ExtSync = 58U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2ExtSync = 59U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm2ExtSync = 60U + (FlexPWM0_SM2_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm3ExtSync = 0U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm3ExtSync = 1U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3ExtSync = 5U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3ExtSync = 6U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3ExtSync = 7U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm3ExtSync = 8U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm3ExtSync = 9U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm3ExtSync = 11U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm3ExtSync = 12U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm3ExtSync = 13U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm3ExtSync = 14U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm3ExtSync = 15U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm3ExtSync = 16U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm3ExtSync = 17U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm3ExtSync = 18U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm3ExtSync = 19U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm3ExtSync = 20U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3ExtSync = 21U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3ExtSync = 22U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm3ExtSync = 24U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm3ExtSync = 25U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm3ExtSync = 26U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm3ExtSync = 27U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm3ExtSync = 28U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3ExtSync = 29U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3ExtSync = 30U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3ExtSync = 31U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3ExtSync = 32U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3ExtSync = 33U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm3ExtSync = 34U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm3ExtSync = 35U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm3ExtSync = 36U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm3ExtSync = 37U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm3ExtSync = 38U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm3ExtSync = 39U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm3ExtSync = 40U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm3ExtSync = 41U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3ExtSync = 42U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3ExtSync = 43U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3ExtSync = 44U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3ExtSync = 45U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3ExtSync = 46U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3ExtSync = 47U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3ExtSync = 48U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3ExtSync = 49U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3ExtSync = 50U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3ExtSync = 51U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3ExtSync = 57U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm3ExtSync = 58U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3ExtSync = 59U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm3ExtSync = 60U + (FlexPWM0_SM3_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm0Exta = 0U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm0Exta = 1U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta = 5U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta = 6U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta = 7U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm0Exta = 8U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm0Exta = 9U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta = 11U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm0Exta = 12U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm0Exta = 13U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm0Exta = 14U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm0Exta = 15U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm0Exta = 16U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm0Exta = 17U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm0Exta = 18U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm0Exta = 19U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm0Exta = 20U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta = 21U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta = 22U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm0Exta = 24U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm0Exta = 25U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm0Exta = 26U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm0Exta = 27U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm0Exta = 28U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm0Exta = 29U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm0Exta = 30U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm0Exta = 31U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm0Exta = 32U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm0Exta = 33U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm0Exta = 34U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm0Exta = 35U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm0Exta = 36U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm0Exta = 37U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm0Exta = 38U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm0Exta = 39U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm0Exta = 40U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm0Exta = 41U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta = 42U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta = 43U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta = 44U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta = 45U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta = 46U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta = 47U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta = 48U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta = 49U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta = 50U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta = 51U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta = 57U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm0Exta = 58U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta = 59U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm0Exta = 60U + (FlexPWM0_SM0_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm1Exta = 0U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm1Exta = 1U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta = 5U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta = 6U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta = 7U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm1Exta = 8U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm1Exta = 9U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta = 11U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm1Exta = 12U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm1Exta = 13U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm1Exta = 14U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm1Exta = 15U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm1Exta = 16U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm1Exta = 17U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm1Exta = 18U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm1Exta = 19U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm1Exta = 20U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta = 21U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta = 22U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm1Exta = 24U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm1Exta = 25U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm1Exta = 26U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm1Exta = 27U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm1Exta = 28U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm1Exta = 29U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm1Exta = 30U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm1Exta = 31U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm1Exta = 32U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm1Exta = 33U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm1Exta = 34U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm1Exta = 35U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm1Exta = 36U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm1Exta = 37U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm1Exta = 38U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm1Exta = 39U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm1Exta = 40U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm1Exta = 41U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta = 42U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta = 43U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta = 44U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta = 45U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta = 46U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta = 47U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta = 48U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta = 49U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta = 50U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta = 51U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta = 57U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm1Exta = 58U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta = 59U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm1Exta = 60U + (FlexPWM0_SM1_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm2Exta = 0U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm2Exta = 1U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta = 5U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta = 6U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta = 7U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm2Exta = 8U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm2Exta = 9U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta = 11U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm2Exta = 12U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm2Exta = 13U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm2Exta = 14U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm2Exta = 15U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm2Exta = 16U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm2Exta = 17U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm2Exta = 18U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm2Exta = 19U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm2Exta = 20U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta = 21U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta = 22U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm2Exta = 24U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm2Exta = 25U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm2Exta = 26U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm2Exta = 27U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm2Exta = 28U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm2Exta = 29U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm2Exta = 30U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm2Exta = 31U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm2Exta = 32U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm2Exta = 33U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm2Exta = 34U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm2Exta = 35U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm2Exta = 36U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm2Exta = 37U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm2Exta = 38U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm2Exta = 39U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm2Exta = 40U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm2Exta = 41U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta = 42U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta = 43U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta = 44U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta = 45U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta = 46U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta = 47U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta = 48U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta = 49U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta = 50U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta = 51U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta = 57U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm2Exta = 58U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta = 59U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm2Exta = 60U + (FlexPWM0_SM2_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM3_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Sm3Exta = 0U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Sm3Exta = 1U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm3Exta = 5U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm3Exta = 6U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm3Exta = 7U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Sm3Exta = 8U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Sm3Exta = 9U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Sm3Exta = 11U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Sm3Exta = 12U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Sm3Exta = 13U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Sm3Exta = 14U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Sm3Exta = 15U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Sm3Exta = 16U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Sm3Exta = 17U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Sm3Exta = 18U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Sm3Exta = 19U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Sm3Exta = 20U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm3Exta = 21U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm3Exta = 22U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Sm3Exta = 24U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Sm3Exta = 25U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Sm3Exta = 26U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Sm3Exta = 27U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Sm3Exta = 28U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Sm3Exta = 29U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Sm3Exta = 30U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Sm3Exta = 31U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Sm3Exta = 32U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Sm3Exta = 33U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Sm3Exta = 34U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Sm3Exta = 35U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Sm3Exta = 36U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Sm3Exta = 37U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Sm3Exta = 38U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Sm3Exta = 39U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Sm3Exta = 40U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Sm3Exta = 41U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm3Exta = 42U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm3Exta = 43U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm3Exta = 44U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm3Exta = 45U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm3Exta = 46U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm3Exta = 47U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm3Exta = 48U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm3Exta = 49U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm3Exta = 50U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm3Exta = 51U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm3Exta = 57U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Sm3Exta = 58U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm3Exta = 59U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Sm3Exta = 60U + (FlexPWM0_SM3_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM0_EXTFORCE input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0ExtForce = 0U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0ExtForce = 1U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0ExtForce = 5U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0ExtForce = 6U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0ExtForce = 7U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0ExtForce = 8U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0ExtForce = 9U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0ExtForce = 11U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0ExtForce = 12U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0ExtForce = 13U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0ExtForce = 14U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0ExtForce = 15U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0ExtForce = 16U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0ExtForce = 17U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0ExtForce = 18U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0ExtForce = 19U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0ExtForce = 20U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0ExtForce = 21U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0ExtForce = 22U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0ExtForce = 24U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0ExtForce = 25U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0ExtForce = 26U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0ExtForce = 27U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0ExtForce = 28U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0ExtForce = 29U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0ExtForce = 30U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0ExtForce = 31U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0ExtForce = 32U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0ExtForce = 33U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0ExtForce = 34U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0ExtForce = 35U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0ExtForce = 36U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0ExtForce = 37U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0ExtForce = 38U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0ExtForce = 39U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0ExtForce = 40U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0ExtForce = 41U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0ExtForce = 42U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0ExtForce = 43U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0ExtForce = 44U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0ExtForce = 45U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0ExtForce = 46U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0ExtForce = 47U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0ExtForce = 48U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0ExtForce = 49U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0ExtForce = 50U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0ExtForce = 51U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0ExtForce = 57U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0ExtForce = 58U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0ExtForce = 59U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0ExtForce = 60U + (FlexPWM0_EXTFORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT0 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault0 = 0U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault0 = 1U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault0 = 5U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault0 = 6U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault0 = 7U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault0 = 8U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault0 = 9U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault0 = 11U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault0 = 12U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault0 = 13U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault0 = 14U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault0 = 15U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault0 = 16U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault0 = 17U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault0 = 18U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault0 = 19U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault0 = 20U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault0 = 21U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault0 = 22U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault0 = 24U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault0 = 25U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault0 = 26U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault0 = 27U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault0 = 28U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault0 = 29U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault0 = 30U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault0 = 31U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault0 = 32U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault0 = 33U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault0 = 34U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault0 = 35U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault0 = 36U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault0 = 37U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault0 = 38U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault0 = 39U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault0 = 40U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault0 = 41U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault0 = 42U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault0 = 43U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault0 = 44U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault0 = 45U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault0 = 46U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault0 = 47U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault0 = 48U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault0 = 49U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault0 = 50U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault0 = 51U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault0 = 57U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault0 = 58U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault0 = 59U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault0 = 60U + (FlexPWM0_FAULT0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT1 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault1 = 0U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault1 = 1U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault1 = 5U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault1 = 6U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault1 = 7U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault1 = 8U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault1 = 9U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault1 = 11U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault1 = 12U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault1 = 13U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault1 = 14U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault1 = 15U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault1 = 16U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault1 = 17U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault1 = 18U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault1 = 19U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault1 = 20U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault1 = 21U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault1 = 22U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault1 = 24U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault1 = 25U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault1 = 26U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault1 = 27U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault1 = 28U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault1 = 29U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault1 = 30U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault1 = 31U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault1 = 32U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault1 = 33U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault1 = 34U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault1 = 35U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault1 = 36U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault1 = 37U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault1 = 38U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault1 = 39U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault1 = 40U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault1 = 41U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault1 = 42U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault1 = 43U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault1 = 44U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault1 = 45U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault1 = 46U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault1 = 47U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault1 = 48U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault1 = 49U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault1 = 50U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault1 = 51U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault1 = 57U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault1 = 58U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault1 = 59U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault1 = 60U + (FlexPWM0_FAULT1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault2 = 0U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault2 = 1U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault2 = 5U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault2 = 6U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault2 = 7U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault2 = 8U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault2 = 9U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault2 = 11U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault2 = 12U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault2 = 13U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault2 = 14U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault2 = 15U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault2 = 16U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault2 = 17U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault2 = 18U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault2 = 19U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault2 = 20U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault2 = 21U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault2 = 22U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault2 = 24U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault2 = 25U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault2 = 26U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault2 = 27U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault2 = 28U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault2 = 29U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault2 = 30U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault2 = 31U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault2 = 32U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault2 = 33U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault2 = 34U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault2 = 35U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault2 = 36U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault2 = 37U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault2 = 38U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault2 = 39U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault2 = 40U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault2 = 41U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault2 = 42U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault2 = 43U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault2 = 44U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault2 = 45U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault2 = 46U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault2 = 47U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault2 = 48U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault2 = 49U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault2 = 50U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault2 = 51U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault2 = 57U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault2 = 58U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault2 = 59U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault2 = 60U + (FlexPWM0_FAULT2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT3 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm0Fault3 = 0U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexPwm0Fault3 = 1U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault3 = 5U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault3 = 6U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault3 = 7U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexPwm0Fault3 = 8U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexPwm0Fault3 = 9U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm0Fault3 = 11U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm0Fault3 = 12U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm0Fault3 = 13U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm0Fault3 = 14U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm0Fault3 = 15U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm0Fault3 = 16U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm0Fault3 = 17U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm0Fault3 = 18U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm0Fault3 = 19U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm0Fault3 = 20U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault3 = 21U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault3 = 22U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexPwm0Fault3 = 24U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexPwm0Fault3 = 25U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexPwm0Fault3 = 26U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexPwm0Fault3 = 27U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexPwm0Fault3 = 28U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexPwm0Fault3 = 29U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexPwm0Fault3 = 30U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexPwm0Fault3 = 31U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm0Fault3 = 32U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm0Fault3 = 33U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm0Fault3 = 34U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm0Fault3 = 35U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm0Fault3 = 36U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm0Fault3 = 37U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm0Fault3 = 38U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm0Fault3 = 39U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm0Fault3 = 40U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm0Fault3 = 41U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault3 = 42U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault3 = 43U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault3 = 44U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault3 = 45U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault3 = 46U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault3 = 47U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault3 = 48U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault3 = 49U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault3 = 50U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault3 = 51U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault3 = 57U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm0Fault3 = 58U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault3 = 59U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm0Fault3 = 60U + (FlexPWM0_FAULT3_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm0ExtSync = 0U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm0ExtSync = 1U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0ExtSync = 5U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0ExtSync = 6U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0ExtSync = 7U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm0ExtSync = 8U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm0ExtSync = 9U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm0ExtSync = 11U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm0ExtSync = 12U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm0ExtSync = 13U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm0ExtSync = 14U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm0ExtSync = 15U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm0ExtSync = 16U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm0ExtSync = 17U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm0ExtSync = 18U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm0ExtSync = 19U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm0ExtSync = 20U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0ExtSync = 21U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0ExtSync = 22U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0ExtSync = 24U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0ExtSync = 25U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0ExtSync = 26U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0ExtSync = 27U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0ExtSync = 28U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0ExtSync = 29U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0ExtSync = 30U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0ExtSync = 31U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0ExtSync = 32U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0ExtSync = 33U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm0ExtSync = 34U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm0ExtSync = 35U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm0ExtSync = 36U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm0ExtSync = 37U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm0ExtSync = 38U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm0ExtSync = 39U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm0ExtSync = 40U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm0ExtSync = 41U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0ExtSync = 42U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0ExtSync = 43U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0ExtSync = 44U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0ExtSync = 45U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0ExtSync = 46U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0ExtSync = 47U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0ExtSync = 48U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0ExtSync = 49U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0ExtSync = 50U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0ExtSync = 51U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0ExtSync = 57U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm0ExtSync = 58U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0ExtSync = 59U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm0ExtSync = 60U + (FlexPWM1_SM0_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm1ExtSync = 0U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm1ExtSync = 1U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1ExtSync = 5U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1ExtSync = 6U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1ExtSync = 7U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm1ExtSync = 8U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm1ExtSync = 9U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm1ExtSync = 11U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm1ExtSync = 12U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm1ExtSync = 13U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm1ExtSync = 14U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm1ExtSync = 15U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm1ExtSync = 16U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm1ExtSync = 17U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm1ExtSync = 18U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm1ExtSync = 19U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm1ExtSync = 20U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1ExtSync = 21U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1ExtSync = 22U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1ExtSync = 24U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1ExtSync = 25U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1ExtSync = 26U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1ExtSync = 27U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1ExtSync = 28U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1ExtSync = 29U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1ExtSync = 30U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1ExtSync = 31U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1ExtSync = 32U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1ExtSync = 33U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm1ExtSync = 34U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm1ExtSync = 35U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm1ExtSync = 36U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm1ExtSync = 37U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm1ExtSync = 38U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm1ExtSync = 39U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm1ExtSync = 40U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm1ExtSync = 41U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1ExtSync = 42U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1ExtSync = 43U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1ExtSync = 44U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1ExtSync = 45U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1ExtSync = 46U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1ExtSync = 47U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1ExtSync = 48U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1ExtSync = 49U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1ExtSync = 50U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1ExtSync = 51U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1ExtSync = 57U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm1ExtSync = 58U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1ExtSync = 59U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm1ExtSync = 60U + (FlexPWM1_SM1_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm2ExtSync = 0U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm2ExtSync = 1U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2ExtSync = 5U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2ExtSync = 6U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2ExtSync = 7U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm2ExtSync = 8U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm2ExtSync = 9U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm2ExtSync = 11U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm2ExtSync = 12U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm2ExtSync = 13U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm2ExtSync = 14U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm2ExtSync = 15U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm2ExtSync = 16U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm2ExtSync = 17U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm2ExtSync = 18U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm2ExtSync = 19U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm2ExtSync = 20U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2ExtSync = 21U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2ExtSync = 22U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2ExtSync = 24U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2ExtSync = 25U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2ExtSync = 26U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2ExtSync = 27U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2ExtSync = 28U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2ExtSync = 29U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2ExtSync = 30U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2ExtSync = 31U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2ExtSync = 32U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2ExtSync = 33U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm2ExtSync = 34U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm2ExtSync = 35U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm2ExtSync = 36U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm2ExtSync = 37U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm2ExtSync = 38U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm2ExtSync = 39U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm2ExtSync = 40U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm2ExtSync = 41U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2ExtSync = 42U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2ExtSync = 43U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2ExtSync = 44U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2ExtSync = 45U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2ExtSync = 46U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2ExtSync = 47U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2ExtSync = 48U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2ExtSync = 49U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2ExtSync = 50U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2ExtSync = 51U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2ExtSync = 57U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm2ExtSync = 58U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2ExtSync = 59U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm2ExtSync = 60U + (FlexPWM1_SM2_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTSYNC input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm3ExtSync = 0U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm3ExtSync = 1U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3ExtSync = 5U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3ExtSync = 6U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3ExtSync = 7U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm3ExtSync = 8U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm3ExtSync = 9U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm3ExtSync = 11U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm3ExtSync = 12U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm3ExtSync = 13U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm3ExtSync = 14U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm3ExtSync = 15U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm3ExtSync = 16U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm3ExtSync = 17U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm3ExtSync = 18U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm3ExtSync = 19U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm3ExtSync = 20U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3ExtSync = 21U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3ExtSync = 22U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3ExtSync = 24U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3ExtSync = 25U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3ExtSync = 26U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3ExtSync = 27U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3ExtSync = 28U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3ExtSync = 29U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3ExtSync = 30U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3ExtSync = 31U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3ExtSync = 32U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3ExtSync = 33U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm3ExtSync = 34U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm3ExtSync = 35U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm3ExtSync = 36U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm3ExtSync = 37U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm3ExtSync = 38U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm3ExtSync = 39U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm3ExtSync = 40U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm3ExtSync = 41U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3ExtSync = 42U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3ExtSync = 43U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3ExtSync = 44U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3ExtSync = 45U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3ExtSync = 46U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3ExtSync = 47U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3ExtSync = 48U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3ExtSync = 49U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3ExtSync = 50U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3ExtSync = 51U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3ExtSync = 57U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm3ExtSync = 58U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3ExtSync = 59U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm3ExtSync = 60U + (FlexPWM1_SM3_EXTSYNC_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm0Exta = 0U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm0Exta = 1U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta = 5U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta = 6U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta = 7U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm0Exta = 8U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm0Exta = 9U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta = 11U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm0Exta = 12U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm0Exta = 13U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm0Exta = 14U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm0Exta = 15U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm0Exta = 16U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm0Exta = 17U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm0Exta = 18U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm0Exta = 19U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm0Exta = 20U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta = 21U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta = 22U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm0Exta = 24U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm0Exta = 25U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm0Exta = 26U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm0Exta = 27U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm0Exta = 28U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm0Exta = 29U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm0Exta = 30U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm0Exta = 31U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm0Exta = 32U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm0Exta = 33U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm0Exta = 34U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm0Exta = 35U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm0Exta = 36U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm0Exta = 37U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm0Exta = 38U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm0Exta = 39U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm0Exta = 40U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm0Exta = 41U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta = 42U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta = 43U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta = 44U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta = 45U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta = 46U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta = 47U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta = 48U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta = 49U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta = 50U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta = 51U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta = 57U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm0Exta = 58U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta = 59U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm0Exta = 60U + (FlexPWM1_SM0_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm1Exta = 0U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm1Exta = 1U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta = 5U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta = 6U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta = 7U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm1Exta = 8U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm1Exta = 9U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta = 11U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm1Exta = 12U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm1Exta = 13U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm1Exta = 14U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm1Exta = 15U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm1Exta = 16U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm1Exta = 17U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm1Exta = 18U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm1Exta = 19U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm1Exta = 20U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta = 21U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta = 22U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm1Exta = 24U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm1Exta = 25U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm1Exta = 26U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm1Exta = 27U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm1Exta = 28U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm1Exta = 29U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm1Exta = 30U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm1Exta = 31U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm1Exta = 32U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm1Exta = 33U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm1Exta = 34U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm1Exta = 35U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm1Exta = 36U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm1Exta = 37U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm1Exta = 38U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm1Exta = 39U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm1Exta = 40U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm1Exta = 41U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta = 42U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta = 43U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta = 44U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta = 45U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta = 46U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta = 47U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta = 48U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta = 49U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta = 50U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Exta = 51U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Exta = 57U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm1Exta = 58U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Exta = 59U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm1Exta = 60U + (FlexPWM1_SM1_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm2Exta = 0U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm2Exta = 1U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta = 5U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta = 6U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta = 7U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm2Exta = 8U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm2Exta = 9U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm2Exta = 11U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm2Exta = 12U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm2Exta = 13U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm2Exta = 14U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm2Exta = 15U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm2Exta = 16U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm2Exta = 17U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm2Exta = 18U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm2Exta = 19U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm2Exta = 20U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta = 21U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta = 22U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm2Exta = 24U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm2Exta = 25U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm2Exta = 26U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm2Exta = 27U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm2Exta = 28U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm2Exta = 29U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm2Exta = 30U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm2Exta = 31U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm2Exta = 32U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm2Exta = 33U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm2Exta = 34U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm2Exta = 35U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm2Exta = 36U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm2Exta = 37U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm2Exta = 38U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm2Exta = 39U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm2Exta = 40U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm2Exta = 41U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Exta = 42U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Exta = 43U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Exta = 44U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Exta = 45U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Exta = 46U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Exta = 47U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Exta = 48U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Exta = 49U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Exta = 50U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Exta = 51U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Exta = 57U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm2Exta = 58U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Exta = 59U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm2Exta = 60U + (FlexPWM1_SM2_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM3_EXTA input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Sm3Exta = 0U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Sm3Exta = 1U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm3Exta = 5U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm3Exta = 6U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm3Exta = 7U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Sm3Exta = 8U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Sm3Exta = 9U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Sm3Exta = 11U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Sm3Exta = 12U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Sm3Exta = 13U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Sm3Exta = 14U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Sm3Exta = 15U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Sm3Exta = 16U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Sm3Exta = 17U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Sm3Exta = 18U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Sm3Exta = 19U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Sm3Exta = 20U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm3Exta = 21U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm3Exta = 22U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Sm3Exta = 24U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Sm3Exta = 25U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Sm3Exta = 26U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Sm3Exta = 27U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Sm3Exta = 28U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Sm3Exta = 29U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Sm3Exta = 30U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Sm3Exta = 31U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Sm3Exta = 32U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Sm3Exta = 33U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Sm3Exta = 34U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Sm3Exta = 35U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Sm3Exta = 36U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Sm3Exta = 37U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Sm3Exta = 38U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Sm3Exta = 39U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Sm3Exta = 40U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Sm3Exta = 41U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm3Exta = 42U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm3Exta = 43U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm3Exta = 44U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm3Exta = 45U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm3Exta = 46U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm3Exta = 47U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm3Exta = 48U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm3Exta = 49U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm3Exta = 50U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm3Exta = 51U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm3Exta = 57U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Sm3Exta = 58U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm3Exta = 59U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Sm3Exta = 60U + (FlexPWM1_SM3_EXTA_REG << PMUX_SHIFT), + + /*!< FlexPWM1_EXTFORCE input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1ExtForce = 0U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1ExtForce = 1U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1ExtForce = 5U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1ExtForce = 6U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1ExtForce = 7U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1ExtForce = 8U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1ExtForce = 9U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1ExtForce = 11U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1ExtForce = 12U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1ExtForce = 13U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1ExtForce = 14U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1ExtForce = 15U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1ExtForce = 16U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1ExtForce = 17U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1ExtForce = 18U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1ExtForce = 19U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1ExtForce = 20U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1ExtForce = 21U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1ExtForce = 22U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1ExtForce = 24U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1ExtForce = 25U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1ExtForce = 26U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1ExtForce = 27U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1ExtForce = 28U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1ExtForce = 29U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1ExtForce = 30U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1ExtForce = 31U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1ExtForce = 32U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1ExtForce = 33U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1ExtForce = 34U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1ExtForce = 35U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1ExtForce = 36U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1ExtForce = 37U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1ExtForce = 38U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1ExtForce = 39U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1ExtForce = 40U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1ExtForce = 41U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1ExtForce = 42U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1ExtForce = 43U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1ExtForce = 44U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1ExtForce = 45U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1ExtForce = 46U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1ExtForce = 47U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1ExtForce = 48U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1ExtForce = 49U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1ExtForce = 50U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1ExtForce = 51U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1ExtForce = 57U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1ExtForce = 58U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1ExtForce = 59U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1ExtForce = 60U + (FlexPWM1_EXTFORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT0 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault0 = 0U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault0 = 1U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault0 = 5U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault0 = 6U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault0 = 7U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault0 = 8U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault0 = 9U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault0 = 11U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault0 = 12U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault0 = 13U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault0 = 14U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault0 = 15U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault0 = 16U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault0 = 17U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault0 = 18U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault0 = 19U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault0 = 20U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault0 = 21U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault0 = 22U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault0 = 24U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault0 = 25U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault0 = 26U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault0 = 27U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault0 = 28U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault0 = 29U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault0 = 30U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault0 = 31U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault0 = 32U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault0 = 33U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault0 = 34U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault0 = 35U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault0 = 36U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault0 = 37U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault0 = 38U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault0 = 39U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault0 = 40U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault0 = 41U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault0 = 42U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault0 = 43U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault0 = 44U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault0 = 45U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault0 = 46U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault0 = 47U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault0 = 48U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault0 = 49U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault0 = 50U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault0 = 51U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault0 = 57U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault0 = 58U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault0 = 59U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault0 = 60U + (FlexPWM1_FAULT0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT1 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault1 = 0U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault1 = 1U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault1 = 5U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault1 = 6U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault1 = 7U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault1 = 8U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault1 = 9U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault1 = 11U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault1 = 12U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault1 = 13U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault1 = 14U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault1 = 15U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault1 = 16U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault1 = 17U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault1 = 18U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault1 = 19U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault1 = 20U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault1 = 21U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault1 = 22U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault1 = 24U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault1 = 25U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault1 = 26U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault1 = 27U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault1 = 28U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault1 = 29U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault1 = 30U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault1 = 31U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault1 = 32U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault1 = 33U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault1 = 34U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault1 = 35U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault1 = 36U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault1 = 37U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault1 = 38U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault1 = 39U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault1 = 40U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault1 = 41U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault1 = 42U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault1 = 43U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault1 = 44U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault1 = 45U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault1 = 46U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault1 = 47U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault1 = 48U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault1 = 49U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault1 = 50U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault1 = 51U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault1 = 57U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault1 = 58U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault1 = 59U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault1 = 60U + (FlexPWM1_FAULT1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT2 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault2 = 0U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault2 = 1U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault2 = 5U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault2 = 6U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault2 = 7U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault2 = 8U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault2 = 9U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault2 = 11U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault2 = 12U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault2 = 13U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault2 = 14U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault2 = 15U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault2 = 16U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault2 = 17U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault2 = 18U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault2 = 19U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault2 = 20U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault2 = 21U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault2 = 22U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault2 = 24U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault2 = 25U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault2 = 26U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault2 = 27U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault2 = 28U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault2 = 29U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault2 = 30U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault2 = 31U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault2 = 32U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault2 = 33U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault2 = 34U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault2 = 35U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault2 = 36U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault2 = 37U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault2 = 38U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault2 = 39U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault2 = 40U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault2 = 41U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault2 = 42U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault2 = 43U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault2 = 44U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault2 = 45U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault2 = 46U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault2 = 47U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault2 = 48U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault2 = 49U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault2 = 50U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault2 = 51U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault2 = 57U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault2 = 58U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault2 = 59U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault2 = 60U + (FlexPWM1_FAULT2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT3 input trigger connections. */ + kINPUTMUX_PinInt0ToFlexPwm1Fault3 = 0U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_PinInt2ToFlexPwm1Fault3 = 1U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault3 = 5U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault3 = 6U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault3 = 7U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexPwm1Fault3 = 8U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexPwm1Fault3 = 9U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexPwm1Fault3 = 11U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexPwm1Fault3 = 12U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexPwm1Fault3 = 13U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexPwm1Fault3 = 14U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexPwm1Fault3 = 15U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexPwm1Fault3 = 16U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexPwm1Fault3 = 17U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexPwm1Fault3 = 18U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexPwm1Fault3 = 19U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexPwm1Fault3 = 20U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault3 = 21U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault3 = 22U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexPwm1Fault3 = 24U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexPwm1Fault3 = 25U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexPwm1Fault3 = 26U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexPwm1Fault3 = 27U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexPwm1Fault3 = 28U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexPwm1Fault3 = 29U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexPwm1Fault3 = 30U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexPwm1Fault3 = 31U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToFlexPwm1Fault3 = 32U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToFlexPwm1Fault3 = 33U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexPwm1Fault3 = 34U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexPwm1Fault3 = 35U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexPwm1Fault3 = 36U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexPwm1Fault3 = 37U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexPwm1Fault3 = 38U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexPwm1Fault3 = 39U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexPwm1Fault3 = 40U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexPwm1Fault3 = 41U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault3 = 42U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault3 = 43U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault3 = 44U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault3 = 45U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault3 = 46U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault3 = 47U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault3 = 48U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault3 = 49U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault3 = 50U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault3 = 51U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault3 = 57U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexPwm1Fault3 = 58U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault3 = 59U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexPwm1Fault3 = 60U + (FlexPWM1_FAULT3_REG << PMUX_SHIFT), + + /*!< PWM0 external clock trigger. */ + kINPUTMUX_Fro16KToPwm0ExtClk = 0U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToPwm0ExtClk = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToPwm0ExtClk = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToPwm0ExtClk = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn1ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + + /*!< PWM1 external clock trigger. */ + kINPUTMUX_Fro16KToPwm1ExtClk = 0U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Osc32KToPwm1ExtClk = 1U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToPwm1ExtClk = 2U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToPwm1ExtClk = 3U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm1ExtClk = 4U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn1ToPwm1ExtClk = 5U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + + /*!< EVTG trigger input connections. */ + kINPUTMUX_PinInt0ToEvtgTrigger = 0U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt1ToEvtgTrigger = 1U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToEvtgTrigger = 6U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToEvtgTrigger = 7U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToEvtgTrigger = 8U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToEvtgTrigger = 9U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToEvtgTrigger = 10U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToEvtgTrigger = 11U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToEvtgTrigger = 13U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToEvtgTrigger = 14U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToEvtgTrigger = 15U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToEvtgTrigger = 16U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToEvtgTrigger = 17U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToEvtgTrigger = 18U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToEvtgTrigger = 19U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToEvtgTrigger = 20U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToEvtgTrigger = 21U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToEvtgTrigger = 22U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToEvtgTrigger = 23U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToEvtgTrigger = 24U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToEvtgTrigger = 25U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToEvtgTrigger = 27U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToEvtgTrigger = 28U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToEvtgTrigger = 29U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToEvtgTrigger = 30U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToEvtgTrigger = 31U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToEvtgTrigger = 32U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToEvtgTrigger = 33U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToEvtgTrigger = 34U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToEvtgTrigger = 35U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToEvtgTrigger = 36U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToEvtgTrigger = 37U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToEvtgTrigger = 38U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToEvtgTrigger = 39U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToEvtgTrigger = 40U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToEvtgTrigger = 41U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToEvtgTrigger = 42U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToEvtgTrigger = 43U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToEvtgTrigger = 44U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToEvtgTrigger = 45U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToEvtgTrigger = 46U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToEvtgTrigger = 47U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToEvtgTrigger = 48U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToEvtgTrigger = 49U + (EVTG_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToEvtgTrigger = 50U + (EVTG_TRIG0_REG << PMUX_SHIFT), + + /*!< EXT trigger connections. */ + kINPUTMUX_PinInt0ToExtTrigger = 0U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt1ToExtTrigger = 1U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0IrqToExtTrigger = 2U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1IrqToExtTrigger = 3U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToExtTrigger = 4U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToExtTrigger = 5U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig01ToExtTrigger = 6U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig01ToExtTrigger = 7U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig01ToExtTrigger = 8U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig01ToExtTrigger = 9U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig01ToExtTrigger = 10U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig01ToExtTrigger = 11U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig01ToExtTrigger = 12U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig01ToExtTrigger = 13U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpPosMatchToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpPosMatchToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToExtTrigger = 16U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToExtTrigger = 17U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToExtTrigger = 18U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToExtTrigger = 19U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToExtTrigger = 20U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToExtTrigger = 21U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToExtTrigger = 22U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToExtTrigger = 23U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToExtTrigger = 26U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToExtTrigger = 27U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig3ToExtTrigger = 34U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig3ToExtTrigger = 35U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig3ToExtTrigger = 36U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig3ToExtTrigger = 37U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm4Trig3ToExtTrigger = 38U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm5Trig3ToExtTrigger = 39U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm6Trig3ToExtTrigger = 40U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm7Trig3ToExtTrigger = 41U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToExtTrigger = 44U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToExtTrigger = 45U + (EXT_TRIG0_REG << PMUX_SHIFT), + + /*!< FLEXCOMM0 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm0Trigger = 0U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm0Trigger = 1U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm0Trigger = 2U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm0Trigger = 6U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm0Trigger = 7U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexcomm0Trigger = 8U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToFlexcomm0Trigger = 9U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexcomm0Trigger = 10U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm0Trigger = 11U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm0Trigger = 12U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm0Trigger = 13U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm0Trigger = 14U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm0Trigger = 15U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm0Trigger = 16U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm0Trigger = 18U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm0Trigger = 19U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm0Trigger = 20U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm0Trigger = 21U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm0Trigger = 22U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm0Trigger = 23U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm0Trigger = 24U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm0Trigger = 25U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm0Trigger = 26U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm0Trigger = 27U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm0Trigger = 28U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm0Trigger = 29U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm0Trigger = 30U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm0Trigger = 31U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm0Trigger = 32U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm0Trigger = 33U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm0Trigger = 34U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm0Trigger = 35U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm0Trigger = 36U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm0Trigger = 37U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm0Trigger = 38U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm0Trigger = 39U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm0Trigger = 40U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm0Trigger = 41U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm0Trigger = 42U + (FLEXCOMM0_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM1 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm1Trigger = 0U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm1Trigger = 1U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm1Trigger = 2U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm1Trigger = 6U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm1Trigger = 7U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToFlexcomm1Trigger = 8U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToFlexcomm1Trigger = 9U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToFlexcomm1Trigger = 10U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm1Trigger = 11U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm1Trigger = 12U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm1Trigger = 13U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm1Trigger = 14U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm1Trigger = 15U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm1Trigger = 16U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm1Trigger = 18U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm1Trigger = 19U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm1Trigger = 20U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm1Trigger = 21U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm1Trigger = 22U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm1Trigger = 23U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm1Trigger = 24U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm1Trigger = 25U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm1Trigger = 26U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm1Trigger = 27U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm1Trigger = 28U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm1Trigger = 29U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm1Trigger = 30U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm1Trigger = 31U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm1Trigger = 32U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm1Trigger = 33U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm1Trigger = 34U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm1Trigger = 35U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm1Trigger = 36U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm1Trigger = 37U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm1Trigger = 38U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm1Trigger = 39U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm1Trigger = 40U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm1Trigger = 41U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm1Trigger = 42U + (FLEXCOMM1_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM2 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm2Trigger = 0U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexcomm2Trigger = 1U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm2Trigger = 2U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm2Trigger = 6U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm2Trigger = 7U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexcomm2Trigger = 8U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexcomm2Trigger = 9U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexcomm2Trigger = 10U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm2Trigger = 11U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm2Trigger = 12U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm2Trigger = 13U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm2Trigger = 14U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm2Trigger = 15U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm2Trigger = 16U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm2Trigger = 18U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm2Trigger = 19U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm2Trigger = 20U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm2Trigger = 21U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm2Trigger = 22U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm2Trigger = 23U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm2Trigger = 24U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm2Trigger = 25U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm2Trigger = 26U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm2Trigger = 27U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm2Trigger = 28U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm2Trigger = 29U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm2Trigger = 30U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm2Trigger = 31U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm2Trigger = 32U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm2Trigger = 33U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm2Trigger = 34U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm2Trigger = 35U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm2Trigger = 36U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm2Trigger = 37U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm2Trigger = 38U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm2Trigger = 39U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm2Trigger = 40U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm2Trigger = 41U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm2Trigger = 42U + (FLEXCOMM2_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM3 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm3Trigger = 0U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm3Trigger = 1U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm3Trigger = 2U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm3Trigger = 6U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm3Trigger = 7U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexcomm3Trigger = 8U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexcomm3Trigger = 9U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexcomm3Trigger = 10U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm3Trigger = 11U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm3Trigger = 12U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm3Trigger = 13U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm3Trigger = 14U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm3Trigger = 15U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm3Trigger = 16U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm3Trigger = 18U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm3Trigger = 19U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm3Trigger = 20U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm3Trigger = 21U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm3Trigger = 22U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm3Trigger = 23U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm3Trigger = 24U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm3Trigger = 25U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm3Trigger = 26U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm3Trigger = 27U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm3Trigger = 28U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm3Trigger = 29U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm3Trigger = 30U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm3Trigger = 31U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm3Trigger = 32U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm3Trigger = 33U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm3Trigger = 34U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm3Trigger = 35U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm3Trigger = 36U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm3Trigger = 37U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm3Trigger = 38U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm3Trigger = 39U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm3Trigger = 40U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm3Trigger = 41U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm3Trigger = 42U + (FLEXCOMM3_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM4 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm4Trigger = 0U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm4Trigger = 1U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm4Trigger = 2U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm4Trigger = 6U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm4Trigger = 7U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexcomm4Trigger = 8U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexcomm4Trigger = 9U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexcomm4Trigger = 10U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm4Trigger = 11U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm4Trigger = 12U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm4Trigger = 13U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm4Trigger = 14U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm4Trigger = 15U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm4Trigger = 16U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm4Trigger = 18U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm4Trigger = 19U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm4Trigger = 20U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm4Trigger = 21U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm4Trigger = 22U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm4Trigger = 23U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm4Trigger = 24U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm4Trigger = 25U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm4Trigger = 26U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm4Trigger = 27U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm4Trigger = 28U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm4Trigger = 29U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm4Trigger = 30U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm4Trigger = 31U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm4Trigger = 32U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm4Trigger = 33U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm4Trigger = 34U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm4Trigger = 35U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm4Trigger = 36U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm4Trigger = 37U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm4Trigger = 38U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm4Trigger = 39U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm4Trigger = 40U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm4Trigger = 41U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm4Trigger = 42U + (FLEXCOMM4_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM5 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm5Trigger = 0U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm5Trigger = 1U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm5Trigger = 2U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm5Trigger = 6U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm5Trigger = 7U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexcomm5Trigger = 8U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexcomm5Trigger = 9U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexcomm5Trigger = 10U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm5Trigger = 11U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm5Trigger = 12U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm5Trigger = 13U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm5Trigger = 14U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm5Trigger = 15U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm5Trigger = 16U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm5Trigger = 18U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm5Trigger = 19U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm5Trigger = 20U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm5Trigger = 21U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm5Trigger = 22U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm5Trigger = 23U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm5Trigger = 24U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm5Trigger = 25U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm5Trigger = 26U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm5Trigger = 27U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm5Trigger = 28U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm5Trigger = 29U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm5Trigger = 30U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm5Trigger = 31U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm5Trigger = 32U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm5Trigger = 33U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm5Trigger = 34U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm5Trigger = 35U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm5Trigger = 36U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm5Trigger = 37U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm5Trigger = 38U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm5Trigger = 39U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm5Trigger = 40U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm5Trigger = 41U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm5Trigger = 42U + (FLEXCOMM5_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM6 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm6Trigger = 0U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm6Trigger = 1U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm6Trigger = 2U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm6Trigger = 6U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm6Trigger = 7U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexcomm6Trigger = 8U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexcomm6Trigger = 9U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexcomm6Trigger = 10U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm6Trigger = 11U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm6Trigger = 12U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm6Trigger = 13U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm6Trigger = 14U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm6Trigger = 15U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm6Trigger = 16U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm6Trigger = 18U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm6Trigger = 19U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm6Trigger = 20U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm6Trigger = 21U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm6Trigger = 22U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm6Trigger = 23U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm6Trigger = 24U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm6Trigger = 25U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm6Trigger = 26U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm6Trigger = 27U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm6Trigger = 28U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm6Trigger = 29U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm6Trigger = 30U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm6Trigger = 31U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm6Trigger = 32U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm6Trigger = 33U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm6Trigger = 34U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm6Trigger = 35U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm6Trigger = 36U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm6Trigger = 37U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm6Trigger = 38U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm6Trigger = 39U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm6Trigger = 40U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm6Trigger = 41U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm6Trigger = 42U + (FLEXCOMM6_TRIG_REG << PMUX_SHIFT), + + /*!< FLEXCOMM7 trigger input connections. */ + kINPUTMUX_PinInt4ToFlexcomm7Trigger = 0U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexcomm7Trigger = 1U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexcomm7Trigger = 2U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexcomm7Trigger = 6U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexcomm7Trigger = 7U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexcomm7Trigger = 8U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexcomm7Trigger = 9U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexcomm7Trigger = 10U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexcomm7Trigger = 11U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexcomm7Trigger = 12U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexcomm7Trigger = 13U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexcomm7Trigger = 14U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexcomm7Trigger = 15U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexcomm7Trigger = 16U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexcomm7Trigger = 18U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexcomm7Trigger = 19U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexcomm7Trigger = 20U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexcomm7Trigger = 21U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexcomm7Trigger = 22U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexcomm7Trigger = 23U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexcomm7Trigger = 24U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexcomm7Trigger = 25U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexcomm7Trigger = 26U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexcomm7Trigger = 27U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexcomm7Trigger = 28U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexcomm7Trigger = 29U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexcomm7Trigger = 30U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexcomm7Trigger = 31U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexcomm7Trigger = 32U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh4ToFlexcomm7Trigger = 33U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh5ToFlexcomm7Trigger = 34U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh6ToFlexcomm7Trigger = 35U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh7ToFlexcomm7Trigger = 36U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToFlexcomm7Trigger = 37U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexcomm7Trigger = 38U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig1ToFlexcomm7Trigger = 39U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexcomm7Trigger = 40U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig1ToFlexcomm7Trigger = 41U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexcomm7Trigger = 42U + (FLEXCOMM7_TRIG_REG << PMUX_SHIFT), + + /*!< FlexIO trigger input connections. */ + kINPUTMUX_PinInt4ToFlexioTrigger = 0U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt5ToFlexioTrigger = 1U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt6ToFlexioTrigger = 2U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_PinInt7ToFlexioTrigger = 3U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexioTrigger = 9U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexioTrigger = 10U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexioTrigger = 11U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToFlexioTrigger = 12U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToFlexioTrigger = 13U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexioTrigger = 14U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr1ToFlexioTrigger = 15U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_ArmTxevToFlexioTrigger = 16U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_GpioIntBmatchToFlexioTrigger = 17U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexioTrigger = 18U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexioTrigger = 19U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexioTrigger = 20U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexioTrigger = 21U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexioTrigger = 22U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexioTrigger = 23U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexioTrigger = 24U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexioTrigger = 25U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexioTrigger = 26U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexioTrigger = 27U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig0ToFlexioTrigger = 29U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A0Trig1ToFlexioTrigger = 30U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig0ToFlexioTrigger = 31U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A1Trig1ToFlexioTrigger = 32U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig0ToFlexioTrigger = 33U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A2Trig1ToFlexioTrigger = 34U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig0ToFlexioTrigger = 35U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0A3Trig1ToFlexioTrigger = 36U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexioTrigger = 37U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig1ToFlexioTrigger = 38U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig0ToFlexioTrigger = 39U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A1Trig1ToFlexioTrigger = 40U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig0ToFlexioTrigger = 41U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A2Trig1ToFlexioTrigger = 42U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig0ToFlexioTrigger = 43U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A3Trig1ToFlexioTrigger = 44U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0AToFlexioTrigger = 45U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut0BToFlexioTrigger = 46U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1AToFlexioTrigger = 47U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut1BToFlexioTrigger = 48U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2AToFlexioTrigger = 49U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut2BToFlexioTrigger = 50U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3AToFlexioTrigger = 51U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_EvtgOut3BToFlexioTrigger = 52U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexioTrigger = 53U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexioTrigger = 54U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexioTrigger = 55U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexioTrigger = 56U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexioTrigger = 57U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig0ToFlexioTrigger = 63U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig1ToFlexioTrigger = 64U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm0Trig2ToFlexioTrigger = 65U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig0ToFlexioTrigger = 66U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig1ToFlexioTrigger = 67U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm1Trig2ToFlexioTrigger = 68U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig0ToFlexioTrigger = 69U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig1ToFlexioTrigger = 70U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm2Trig2ToFlexioTrigger = 71U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig0ToFlexioTrigger = 72U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig1ToFlexioTrigger = 73U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig2ToFlexioTrigger = 74U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpflexcomm3Trig3ToFlexioTrigger = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexioTrigger = 76U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), +} inputmux_connection_t; + +/*! @brief INPUTMUX signal enable/disable type */ +typedef enum _inputmux_signal_t +{ + /*!< DMA0 REQ ENABLE0 signal. */ + kINPUTMUX_PinInt0ToDma0Ch3Ena = 3U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt1ToDma0Ch4Ena = 4U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt2ToDma0Ch5Ena = 5U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt3ToDma0Ch6Ena = 6U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0Ch7Ena = 7U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0Ch8Ena = 8U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0Ch9Ena = 9U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0Ch10Ena = 10U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0Ch11Ena = 11U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0Ch12Ena = 12U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0Ch13Ena = 13U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0Ch14Ena = 14U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0Ch15Ena = 15U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0Ch16Ena = 16U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Wuu0ToDma0Ch17Ena = 17U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Micfil0FifoRequestToDma0Ch18Ena = 18U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoARequestToDma0Ch21Ena = 21U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoBRequestToDma0Ch22Ena = 22U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoARequestToDma0Ch23Ena = 23U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoBRequestoDma0Ch24Ena = 24U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp0DmaRequestToDma0Ch28Ena = 28U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp1DmaRequestToDma0Ch29Ena = 29U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out0AToDma0Ch31Ena = 31U + (DMA0_REQ_ENABLE0_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE1 signal. */ + kINPUTMUX_Evtg0Out0BToDma0Ch32Ena = 0U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1AToDma0Ch33Ena = 1U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1BToDma0Ch34Ena = 2U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2AToDma0Ch35Ena = 3U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2BToDma0Ch36Ena = 4U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3AToDma0Ch37Ena = 5U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3BToDma0Ch38Ena = 6U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDma0Ch39Ena = 7U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDma0Ch40Ena = 8U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDma0Ch41Ena = 9U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDma0Ch42Ena = 10U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDma0Ch43Ena = 11U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDma0Ch44Ena = 12U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDma0Ch45Ena = 13U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDma0Ch46Ena = 14U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDma0Ch47Ena = 15U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDma0Ch48Ena = 16U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDma0Ch49Ena = 17U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDma0Ch50Ena = 18U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDma0Ch51Ena = 19U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDma0Ch52Ena = 20U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDma0Ch53Ena = 21U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDma0Ch54Ena = 22U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr0ToDma0Ch57Ena = 25U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr1ToDma0Ch58Ena = 26U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan0DmaRequestToDma0Ch59Ena = 27U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan1DmaRequestToDma0Ch60Ena = 28U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister0RequestToDma0Ch61Ena = 29U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister1RequestToDma0Ch62Ena = 30U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister2RequestToDma0Ch63Ena = 31U + (DMA0_REQ_ENABLE1_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE2 signal. */ + kINPUTMUX_FlexIO0ShiftRegister3RequestToDma0Ch64Ena = 0U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister4RequestToDma0Ch65Ena = 1U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister5RequestToDma0Ch66Ena = 2U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister6RequestToDma0Ch67Ena = 3U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister7RequestToDma0Ch68Ena = 4U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0RxToDma0Ch69Ena = 5U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0TxToDma0Ch70Ena = 6U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1RxToDma0Ch71Ena = 7U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1TxToDma0Ch72Ena = 8U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2RxToDma0Ch73Ena = 9U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2TxToDma0Ch74Ena = 10U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3RxToDma0Ch75Ena = 11U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3TxToDma0Ch76Ena = 12U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4RxToDma0Ch77Ena = 13U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4TxToDma0Ch78Ena = 14U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5RxToDma0Ch79Ena = 15U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5TxToDma0Ch80Ena = 16U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6RxToDma0Ch81Ena = 17U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6TxToDma0Ch82Ena = 18U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7RxToDma0Ch83Ena = 19U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7TxToDma0Ch84Ena = 20U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_I3c0RxToDma0Ch95Ena = 31U + (DMA0_REQ_ENABLE2_REG << ENA_SHIFT), + + /*!< DMA0 REQ ENABLE3 signal. */ + kINPUTMUX_I3c0TxToDma0Ch96Ena = 0U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1RxToDma0Ch97Ena = 1U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1TxToDma0Ch98Ena = 2U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0RxToDma0Ch99Ena = 3U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0TxToDma0Ch100Ena = 4U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1RxToDma0Ch101Ena = 5U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1TxToDma0Ch102Ena = 6U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest0ToDma0Ch108Ena = 12U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest1ToDma0Ch109Ena = 13U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest0ToDma0Ch110Ena = 14U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest1ToDma0Ch111Ena = 15U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest0ToDma0Ch112Ena = 16U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest1ToDma0Ch113Ena = 17U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest0ToDma0Ch114Ena = 18U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest1ToDma0Ch115Ena = 19U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest0ToDma0Ch116Ena = 20U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest1ToDma0Ch117Ena = 21U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest0ToDma0Ch118Ena = 22U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest1ToDma0Ch119Ena = 23U + (DMA0_REQ_ENABLE3_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE0 signal. */ + kINPUTMUX_PinInt0ToDma1Ch3Ena = 3U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt1ToDma1Ch4Ena = 4U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt2ToDma1Ch5Ena = 5U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_PinInt3ToDma1Ch6Ena = 6U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1Ch7Ena = 7U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1Ch8Ena = 8U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M0ToDma1Ch9Ena = 9U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer1M1ToDma1Ch10Ena = 10U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1Ch11Ena = 11U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer2M1ToDma1Ch12Ena = 12U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M0ToDma1Ch13Ena = 13U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer3M1ToDma1Ch14Ena = 14U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M0ToDma1Ch15Ena = 15U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Ctimer4M1ToDma1Ch16Ena = 16U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Wuu0ToDma1Ch17Ena = 17U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Micfil0FifoRequestToDma1Ch18Ena = 18U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoARequestToDma1Ch21Ena = 21U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc0FifoBRequestToDma1Ch22Ena = 22U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoARequestToDma1Ch23Ena = 23U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Adc1FifoBRequestToDma1Ch24Ena = 24U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp0DmaRequestToDma1Ch28Ena = 28U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_HsCmp1DmaRequestToDma1Ch29Ena = 29U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out0AToDma1Ch31Ena = 31U + (DMA1_REQ_ENABLE0_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE1 signal. */ + kINPUTMUX_Evtg0Out0BToDma1Ch32Ena = 0U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1AToDma1Ch33Ena = 1U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out1BToDma1Ch34Ena = 2U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2AToDma1Ch35Ena = 3U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out2BToDma1Ch36Ena = 4U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3AToDma1Ch37Ena = 5U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Evtg0Out3BToDma1Ch38Ena = 6U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt0ToDma1Ch39Ena = 7U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt1ToDma1Ch40Ena = 8U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt2ToDma1Ch41Ena = 9U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqCapt3ToDma1Ch42Ena = 10U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal0ToDma1Ch43Ena = 11U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal1ToDma1Ch44Ena = 12U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal2ToDma1Ch45Ena = 13U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm0ReqVal3ToDma1Ch46Ena = 14U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt0ToDma1Ch47Ena = 15U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt1ToDma1Ch48Ena = 16U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt2ToDma1Ch49Ena = 17U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqCapt3ToDma1Ch50Ena = 18U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal0ToDma1Ch51Ena = 19U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal1ToDma1Ch52Ena = 20U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal2ToDma1Ch53Ena = 21U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexPwm1ReqVal3ToDma1Ch54Ena = 22U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr0ToDma1Ch57Ena = 25U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_Lptmr1ToDma1Ch58Ena = 26U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan0DmaRequestToDma1Ch59Ena = 27U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexCan1DmaRequestToDma1Ch60Ena = 28U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister0RequestToDma1Ch61Ena = 29U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister1RequestToDma1Ch62Ena = 30U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister2RequestToDma1Ch63Ena = 31U + (DMA1_REQ_ENABLE1_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE2 signal. */ + kINPUTMUX_FlexIO0ShiftRegister3RequestToDma1Ch64Ena = 0U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister4RequestToDma1Ch65Ena = 1U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister5RequestToDma1Ch66Ena = 2U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister6RequestToDma1Ch67Ena = 3U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_FlexIO0ShiftRegister7RequestToDma1Ch68Ena = 4U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0RxToDma1Ch69Ena = 5U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm0TxToDma1Ch70Ena = 6U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1RxToDma1Ch71Ena = 7U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm1TxToDma1Ch72Ena = 8U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2RxToDma1Ch73Ena = 9U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm2TxToDma1Ch74Ena = 10U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3RxToDma1Ch75Ena = 11U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm3TxToDma1Ch76Ena = 12U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4RxToDma1Ch77Ena = 13U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm4TxToDma1Ch78Ena = 14U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5RxToDma1Ch79Ena = 15U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm5TxToDma1Ch80Ena = 16U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6RxToDma1Ch81Ena = 17U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm6TxToDma1Ch82Ena = 18U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7RxToDma1Ch83Ena = 19U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_LpFlexcomm7TxToDma1Ch84Ena = 20U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_ESpi0Ch0ToDma1Ch89Ena = 25U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_ESpi0Ch1ToDma1Ch90Ena = 26U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + kINPUTMUX_I3c0RxToDma1Ch95Ena = 31U + (DMA1_REQ_ENABLE2_REG << ENA_SHIFT), + + /*!< DMA1 REQ ENABLE3 signal. */ + kINPUTMUX_I3c0TxToDma1Ch96Ena = 0U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1RxToDma1Ch97Ena = 1U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_I3c1TxToDma1Ch98Ena = 2U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0RxToDma1Ch99Ena = 3U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai0TxToDma1Ch100Ena = 4U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1RxToDma1Ch101Ena = 5U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Sai1TxToDma1Ch102Ena = 6U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest0ToDma1Ch108Ena = 12U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio0PinEventRequest1ToDma1Ch109Ena = 13U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest0ToDma1Ch110Ena = 14U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio1PinEventRequest1ToDma1Ch111Ena = 15U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest0ToDma1Ch112Ena = 16U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio2PinEventRequest1ToDma1Ch113Ena = 17U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest0ToDma1Ch114Ena = 18U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio3PinEventRequest1ToDma1Ch115Ena = 19U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest0ToDma1Ch116Ena = 20U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio4PinEventRequest1ToDma1Ch117Ena = 21U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest0ToDma1Ch118Ena = 22U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), + kINPUTMUX_Gpio5PinEventRequest1ToDma1Ch119Ena = 23U + (DMA1_REQ_ENABLE3_REG << ENA_SHIFT), +} inputmux_signal_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_intm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_intm.c new file mode 100644 index 0000000000..b62eb585b3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_intm.c @@ -0,0 +1,86 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_intm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.intm" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Fill in the INTM config struct with the default settings + * + * The default values are: + * code + * config[0].irqnumber = NotAvail_IRQn; + * config[0].maxtimer = 1000U; + * config[1].irqnumber = NotAvail_IRQn; + * config[1].maxtimer = 1000U; + * config[2].irqnumber = NotAvail_IRQn; + * config[2].maxtimer = 1000U; + * config[3].irqnumber = NotAvail_IRQn; + * config[3].maxtimer = 1000U; + * config->enable = false; + * endcode + * param config Pointer to user's INTM config structure. + */ +void INTM_GetDefaultConfig(intm_config_t *config) +{ + assert(config); + + for (uint32_t i = 0; i < (uint32_t)FSL_FEATURE_INTM_MONITOR_COUNT; i++) + { + config->intm[i].irqnumber = NotAvail_IRQn; + config->intm[i].maxtimer = 1000U; + } + + /* INTM cycle count timer mode disable*/ + config->enable = false; +} + +/*! + * brief Ungates the INTM clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the INTM driver. + * + * param base INTM peripheral base address + * param config Pointer to user's INTM config structure. + */ +void INTM_Init(INTM_Type *base, const intm_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Intm); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_INTM_MONITOR_COUNT; i++) + { + base->MON[i].INTM_IRQSEL = INTM_MON_INTM_IRQSEL_IRQ(config->intm[i].irqnumber); + base->MON[i].INTM_LATENCY = INTM_MON_INTM_LATENCY_LAT(config->intm[i].maxtimer); + } + + INTM_EnableCycleCount(base, config->enable); +} + +/*! + * brief Disables the INTM module. + * + * param base INTM peripheral base address + */ +void INTM_Deinit(INTM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the INTM clock*/ + CLOCK_DisableClock(kCLOCK_Intm); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_intm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_intm.h new file mode 100644 index 0000000000..7e0410b3cb --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_intm.h @@ -0,0 +1,207 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_INTM_H_ +#define FSL_INTM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup intm + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief INTM driver version. */ +#define FSL_INTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Interrupt monitors. */ +typedef enum _intm_monitor +{ + kINTM_Monitor1 = 0U, + kINTM_Monitor2, + kINTM_Monitor3, + kINTM_Monitor4 +} intm_monitor_t; + +/*! @brief INTM interrupt source configuration structure. */ +typedef struct _intm_monitor_config +{ + uint32_t maxtimer; /*!< Set the maximum timer */ + IRQn_Type irqnumber; /*!< Select the interrupt request number to monitor. */ +} intm_monitor_config_t; + +/*! @brief INTM configuration structure. */ +typedef struct _intm_config +{ + intm_monitor_config_t intm[FSL_FEATURE_INTM_MONITOR_COUNT]; /*! Interrupt source monitor config.*/ + bool enable; /*!< enables the cycle count timer on a monitored interrupt request for comparison to the latency + register. */ +} intm_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief Fill in the INTM config struct with the default settings + * + * The default values are: + * @code + * config[0].irqnumber = NotAvail_IRQn; + * config[0].maxtimer = 1000U; + * config[1].irqnumber = NotAvail_IRQn; + * config[1].maxtimer = 1000U; + * config[2].irqnumber = NotAvail_IRQn; + * config[2].maxtimer = 1000U; + * config[3].irqnumber = NotAvail_IRQn; + * config[3].maxtimer = 1000U; + * config->enable = false; + * @endcode + * @param config Pointer to user's INTM config structure. + */ +void INTM_GetDefaultConfig(intm_config_t *config); + +/*! + * @brief Ungates the INTM clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the INTM driver. + * + * @param base INTM peripheral base address + * @param config Pointer to user's INTM config structure. + */ +void INTM_Init(INTM_Type *base, const intm_config_t *config); + +/*! + * @brief Disables the INTM module. + * + * @param base INTM peripheral base address + */ +void INTM_Deinit(INTM_Type *base); + +/*! + * @brief Enable the cycle count timer mode. + * + * Monitor mode enables the cycle count timer on a monitored interrupt request for comparison to the latency register. + * + * @param base INTM peripheral base address. + * @param enable Enable the cycle count or not. + */ +static inline void INTM_EnableCycleCount(INTM_Type *base, bool enable) +{ + if (enable) + { + base->INTM_MM |= INTM_INTM_MM_MM_MASK; + } + else + { + base->INTM_MM &= ~INTM_INTM_MM_MM_MASK; + } +} + +/*! + * @brief Interrupt Acknowledge. + * + * Call this function in ISR to acknowledge interrupt. + * + * @param base INTM peripheral base address. + * @param irq Handle interrupt number. + */ +static inline void INTM_AckIrq(INTM_Type *base, IRQn_Type irq) +{ + assert(((uint32_t)irq) < (uint32_t)NUMBER_OF_INT_VECTORS); + + base->INTM_IACK = (uint32_t)irq; +} + +/*! + * @brief Interrupt Request Select. + * + * This function is used to set the interrupt request number to monitor or check. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + * @param irq Interrupt request number to monitor. + * + * @return Select the interrupt request number to monitor. + */ +static inline void INTM_SetInterruptRequestNumber(INTM_Type *base, intm_monitor_t intms, IRQn_Type irq) +{ + assert(((uint32_t)irq) < (uint32_t)NUMBER_OF_INT_VECTORS); + + base->MON[intms].INTM_IRQSEL = INTM_MON_INTM_IRQSEL_IRQ(irq); +} + +/*! + * @brief Set the maximum count time. + * + * This function is to set the maximum time from interrupt generation to confirmation. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + * @param count Timer maximum count. + */ +static inline void INTM_SetMaxTime(INTM_Type *base, intm_monitor_t intms, uint32_t count) +{ + assert((count < 0xFFFFFDU) && (count > 0U)); + + base->MON[intms].INTM_LATENCY = INTM_MON_INTM_LATENCY_LAT(count); +} + +/*! + * @brief Clear the timer period in units of count. + * + * This function is used to clear the INTM_TIMERa register. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + */ +static inline void INTM_ClearTimeCount(INTM_Type *base, intm_monitor_t intms) +{ + base->MON[intms].INTM_TIMER &= ~INTM_MON_INTM_TIMER_TIMER_MASK; +} + +/*! + * @brief Gets the timer period in units of count. + * + * This function is used to get the number of INTM clock cycles from interrupt request to confirmation interrupt + * processing. If this number exceeds the set maximum time, will be an error signal. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + */ +static inline uint32_t INTM_GetTimeCount(INTM_Type *base, intm_monitor_t intms) +{ + return base->MON[intms].INTM_TIMER; +} + +/*! + * @brief Interrupt monitor status. + * + * This function indicates whether the INTM_TIMERa value has exceeded the INTM_LATENCYa value. + * If any interrupt source in INTM_TIMERa exceeds the programmed delay value, the monitor state + * can be cleared by calling the INTM_ClearTimeCount() API to clear the corresponding INTM_TIMERa register. + * + * @param base INTM peripheral base address. + * @param intms Programmable interrupt monitors. + * + * @return Whether INTM_TIMER value has exceeded INTM_LATENCY value. + * false:INTM_TIMER value has not exceeded the INTM_LATENCY value; + * true:INTM_TIMER value has exceeded the INTM_LATENCY value. + */ +static inline bool INTM_GetStatusFlags(INTM_Type *base, intm_monitor_t intms) +{ + return ((base->MON[intms].INTM_STATUS & INTM_MON_INTM_STATUS_STATUS_MASK) != 0U); +} + +/*! @} */ +#endif /* FSL_INTM_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_irtc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_irtc.c new file mode 100644 index 0000000000..f1d15df922 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_irtc.c @@ -0,0 +1,717 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_irtc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.irtc" +#endif + +#define IRTC_BASE_YEAR (2112U) +#define YEAR_RANGE_START (1984U) /* Valid values for year range from -128 to 127; 2112 - 128 */ +#define YEAR_RANGE_END (2239U) /* Valid values for year range from -128 to 127; 2112 + 127 */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime); + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + bool fgRet = true; + + /* Table of days in a month for a non leap year */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->weekDay >= 7U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || + (datetime->second >= 60U)) + { + /* If not correct then error*/ + fgRet = false; + } + else + { + /* Adjust the days in February for a leap year */ + if (((0U == (datetime->year & 3U)) && (0U != (datetime->year % 100U))) || (0U == (datetime->year % 400U))) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + fgRet = false; + } + } + return fgRet; +} + +/*! + * brief Ungates the IRTC clock and configures the peripheral for basic operation. + * + * This function initiates a soft-reset of the IRTC module, this has not effect on DST, + * calendaring, standby time and tamper detect registers. + * + * note This API should be called at the beginning of the application using the IRTC driver. + * + * param base IRTC peripheral base address + * param config Pointer to user's IRTC config structure. + * + * return kStatus_Fail if we cannot disable register write protection + */ +status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config) +{ + assert(NULL != config); + + uint16_t reg; + status_t status = kStatus_Success; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Rtc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET + RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn); +#endif + + /* Unlock to allow register write operation */ + if (kStatus_Success == IRTC_SetWriteProtection(base, false)) + { + /* Issue a software reset */ + IRTC_Reset(base); + +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + /* Setup the wakeup pin select */ + if (config->wakeupSelect) + { + base->CTRL2 |= RTC_CTRL2_WAKEUP_MODE_MASK; + } + else + { + base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; + } +#endif + /* Setup alarm match operation, sampling clock operation in standby mode, 16.384kHz RTC clock and selected clock outout to other peripherals */ + reg = base->CTRL; + reg &= ~( +#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) + (uint16_t)RTC_CTRL_TIMER_STB_MASK_MASK | +#endif +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT + (uint16_t)RTC_CTRL_CLK_SEL_MASK | +#endif +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE + (uint16_t)RTC_CTRL_CLKO_DIS_MASK | +#endif + (uint16_t)RTC_CTRL_ALM_MATCH_MASK); + reg |= ( +#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) + RTC_CTRL_TIMER_STB_MASK(config->timerStdMask) | +#endif +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT + RTC_CTRL_CLK_SEL(config->clockSelect) | +#endif +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE + RTC_CTRL_CLKO_DIS(config->disableClockOutput) | +#endif + RTC_CTRL_ALM_MATCH(config->alrmMatch)); + base->CTRL = reg; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Fill in the IRTC config struct with the default settings + * + * The default values are: + * code + * config->wakeupSelect = true; + * config->timerStdMask = false; + * config->alrmMatch = kRTC_MatchSecMinHr; + * endcode + * param config Pointer to user's IRTC config structure. + */ +void IRTC_GetDefaultConfig(irtc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + /* Tamper pin 0 is used as a wakeup/hibernation pin */ + config->wakeupSelect = true; +#endif + +#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) + /* Sampling clock are not gated when in standby mode */ + config->timerStdMask = false; +#endif + + /* Only seconds, minutes and hours are matched when generating an alarm */ + config->alrmMatch = kRTC_MatchSecMinHr; + +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT + /* 16.384kHz clock is selected */ + config->clockSelect = kIRTC_Clk16K; +#endif + +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE + /* The selected clock is not output to other peripherals */ + config->disableClockOutput = true; +#endif +} + +/*! + * brief Sets the IRTC date and time according to the given time structure. + * + * The IRTC counter is started after the time is set. + * + * param base IRTC peripheral base address + * param datetime Pointer to structure where the date and time details to set are stored + * + * return kStatus_Success: success in setting the time and starting the IRTC + * kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect. + */ +status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + status_t status = kStatus_Success; + + /* Return error if the time provided is not valid */ + if (IRTC_CheckDatetimeFormat(datetime)) + { + /* The register stores the offset in years from the base year of 2112 */ + if (datetime->year < IRTC_BASE_YEAR) + { + /* Values for years less than the base year range from -128 to 1 */ + base->YEARMON = + RTC_YEARMON_YROFST(0x100U + datetime->year - IRTC_BASE_YEAR) | RTC_YEARMON_MON_CNT(datetime->month); + } + else + { + /* Values for years greater or equal to the base year range from 0 to 127 */ + base->YEARMON = RTC_YEARMON_YROFST(datetime->year - IRTC_BASE_YEAR) | RTC_YEARMON_MON_CNT(datetime->month); + } + /* Update the Day Count and Day of the week field */ + base->DAYS = RTC_DAYS_DOW(datetime->weekDay) | RTC_DAYS_DAY_CNT(datetime->day); + + /* Update hour and minute field */ + base->HOURMIN = RTC_HOURMIN_HOUR_CNT(datetime->hour) | RTC_HOURMIN_MIN_CNT(datetime->minute); + + /* Update the seconds register */ + base->SECONDS = RTC_SECONDS_SEC_CNT(datetime->second); + } + else + { + status = kStatus_InvalidArgument; + } + + return status; +} + +/*! + * brief Gets the IRTC time and stores it in the given time structure. + * + * param base IRTC peripheral base address + * param datetime Pointer to structure where the date and time details are stored. + */ +void IRTC_GetDatetime(RTC_Type *base, irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + uint16_t temp = base->YEARMON; + + datetime->year = + (uint16_t)IRTC_BASE_YEAR + (uint16_t)((int8_t)(uint8_t)((temp >> RTC_YEARMON_YROFST_SHIFT) & 0xFFU)); + datetime->month = (uint8_t)temp & RTC_YEARMON_MON_CNT_MASK; + + temp = base->DAYS; + datetime->weekDay = (uint8_t)((temp & RTC_DAYS_DOW_MASK) >> RTC_DAYS_DOW_SHIFT); + datetime->day = (uint8_t)temp & RTC_DAYS_DAY_CNT_MASK; + + temp = base->HOURMIN; + datetime->hour = (uint8_t)((temp & RTC_HOURMIN_HOUR_CNT_MASK) >> RTC_HOURMIN_HOUR_CNT_SHIFT); + datetime->minute = (uint8_t)temp & RTC_HOURMIN_MIN_CNT_MASK; + + datetime->second = (uint8_t)(base->SECONDS) & RTC_SECONDS_SEC_CNT_MASK; +} + +/*! + * brief Sets the IRTC alarm time + * + * param base RTC peripheral base address + * param alarmTime Pointer to structure where the alarm time is stored. + * + * note weekDay field of alarmTime is not used during alarm match and should be set to 0 + * + * return kStatus_Success: success in setting the alarm + * kStatus_InvalidArgument: error in setting the alarm. Error occurs because the alarm + * datetime format is incorrect. + */ +status_t IRTC_SetAlarm(RTC_Type *base, const irtc_datetime_t *alarmTime) +{ + assert(NULL != alarmTime); + + status_t status = kStatus_Success; + + /* Return error if the alarm time provided is not valid */ + if (IRTC_CheckDatetimeFormat(alarmTime)) + { + /* Set the alarm year */ + if (alarmTime->year < IRTC_BASE_YEAR) + { + base->ALM_YEARMON = RTC_ALM_YEARMON_ALM_YEAR(0x100U + alarmTime->year - IRTC_BASE_YEAR) | + RTC_ALM_YEARMON_ALM_MON(alarmTime->month); + } + else + { + base->ALM_YEARMON = + RTC_ALM_YEARMON_ALM_YEAR(alarmTime->year - IRTC_BASE_YEAR) | RTC_ALM_YEARMON_ALM_MON(alarmTime->month); + } + + /* Set the alarm day */ + base->ALM_DAYS = RTC_ALM_DAYS_ALM_DAY(alarmTime->day); + + /* Set the alarm hour and minute */ + base->ALM_HOURMIN = RTC_ALM_HOURMIN_ALM_HOUR(alarmTime->hour) | RTC_ALM_HOURMIN_ALM_MIN(alarmTime->minute); + + /* Set the alarm seconds */ + base->ALM_SECONDS = RTC_ALM_SECONDS_ALM_SEC(alarmTime->second); + } + else + { + status = kStatus_InvalidArgument; + } + + return status; +} + +/*! + * brief Returns the IRTC alarm time. + * + * param base RTC peripheral base address + * param datetime Pointer to structure where the alarm date and time details are stored. + */ +void IRTC_GetAlarm(RTC_Type *base, irtc_datetime_t *datetime) +{ + assert(NULL != datetime); + + uint16_t temp = base->ALM_YEARMON; + + datetime->year = + (uint16_t)IRTC_BASE_YEAR + (uint16_t)((int8_t)(uint8_t)((temp >> RTC_ALM_YEARMON_ALM_YEAR_SHIFT) & 0xFFU)); + datetime->month = (uint8_t)temp & RTC_ALM_YEARMON_ALM_MON_MASK; + + datetime->day = (uint8_t)(base->ALM_DAYS) & RTC_ALM_DAYS_ALM_DAY_MASK; + + temp = base->ALM_HOURMIN; + datetime->hour = (uint8_t)((temp & RTC_ALM_HOURMIN_ALM_HOUR_MASK) >> RTC_ALM_HOURMIN_ALM_HOUR_SHIFT); + datetime->minute = (uint8_t)temp & RTC_ALM_HOURMIN_ALM_MIN_MASK; + + datetime->second = (uint8_t)(base->ALM_SECONDS) & RTC_ALM_SECONDS_ALM_SEC_MASK; +} + +/*! + * brief Locks or unlocks IRTC registers for write access. + * + * note When the registers are unlocked, they remain in unlocked state for + * 2 seconds, after which they are locked automatically. After + * power-on-reset, the registers come out unlocked and they are locked + * automatically 15 seconds after power on. + * + * param base IRTC peripheral base address + * param lock true: Lock IRTC registers; false: Unlock IRTC registers. + * + * return kStatus_Success: if lock or unlock operation is successful + * kStatus_Fail: if lock or unlock operation fails even after multiple retry attempts + */ +status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock) +{ + /* Retry before giving up */ + uint8_t repeatProtectSequence = 0xFFU; + status_t status = kStatus_Success; + + if (!lock) + { + /* Unlock IRTC registers */ + while ((0U != (base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK)) && (0U != repeatProtectSequence)) + { + /* Access in 8-bit mode while storing the value */ + *(__IO uint8_t *)(&base->STATUS) = 0U; + *(__IO uint8_t *)(&base->STATUS) = 0x40U; + *(__IO uint8_t *)(&base->STATUS) = 0xC0U; + *(__IO uint8_t *)(&base->STATUS) = 0x80U; + repeatProtectSequence--; + } + } + else + { + /* Lock IRTC registers */ + while ((0U == ((base->STATUS & (uint16_t)RTC_STATUS_WRITE_PROT_EN_MASK) >> RTC_STATUS_WRITE_PROT_EN_SHIFT)) && + (0U != repeatProtectSequence)) + { + *(__IO uint8_t *)(&base->STATUS) = 0x80U; + repeatProtectSequence--; + } + } + + /* Lock/unlock was not successful even after trying 256 times */ + if (0U == repeatProtectSequence) + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Sets the IRTC daylight savings start and stop date and time. + * + * It also enables the daylight saving bit in the IRTC control register + * + * param base IRTC peripheral base address + * param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime) +{ + assert(NULL != datetime); + + /* Disable daylight saving time */ + base->CTRL &= ~(uint16_t)RTC_CTRL_DST_EN_MASK; + + /* Set the daylight saving time start month and end month value */ + base->DST_MONTH = + RTC_DST_MONTH_DST_START_MONTH(datetime->startMonth) | RTC_DST_MONTH_DST_END_MONTH(datetime->endMonth); + + /* Set the daylight saving time start day and end day value */ + base->DST_DAY = RTC_DST_DAY_DST_START_DAY(datetime->startDay) | RTC_DST_DAY_DST_END_DAY(datetime->endDay); + + /* Set the daylight saving time start hour and end hour value */ + base->DST_HOUR = RTC_DST_HOUR_DST_START_HOUR(datetime->startHour) | RTC_DST_HOUR_DST_END_HOUR(datetime->endHour); + + /* Enable daylight saving time */ + base->CTRL |= RTC_CTRL_DST_EN_MASK; +} + +/*! + * brief Gets the IRTC daylight savings time and stores it in the given time structure. + * + * param base IRTC peripheral base address + * param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime) +{ + assert(NULL != datetime); + + uint16_t temp = base->DST_MONTH; + + /* Get the daylight savings time start and end month value */ + datetime->startMonth = + (uint8_t)((temp & RTC_DST_MONTH_DST_START_MONTH_MASK) >> RTC_DST_MONTH_DST_START_MONTH_SHIFT); + datetime->endMonth = (uint8_t)((temp & RTC_DST_MONTH_DST_END_MONTH_MASK) >> RTC_DST_MONTH_DST_END_MONTH_SHIFT); + + /* Get the daylight savings time start and end day value */ + temp = base->DST_DAY; + datetime->startDay = (uint8_t)((temp & RTC_DST_DAY_DST_START_DAY_MASK) >> RTC_DST_DAY_DST_START_DAY_SHIFT); + datetime->endDay = (uint8_t)((temp & RTC_DST_DAY_DST_END_DAY_MASK) >> RTC_DST_DAY_DST_END_DAY_SHIFT); + + /* Get the daylight savings time start and end hour value */ + temp = base->DST_HOUR; + datetime->startHour = (uint8_t)((temp & RTC_DST_HOUR_DST_START_HOUR_MASK) >> RTC_DST_HOUR_DST_START_HOUR_SHIFT); + datetime->endHour = (uint8_t)((temp & RTC_DST_HOUR_DST_END_HOUR_MASK) >> RTC_DST_HOUR_DST_END_HOUR_SHIFT); +} + +/*! + * brief Enables the coarse compensation and sets the value in the IRTC compensation register. + * + * param base IRTC peripheral base address + * param compensationValue Compensation value is a 2's complement value. + * param compensationInterval Compensation interval. + */ +void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8_t compensationInterval) +{ + uint16_t reg; + + /* Set the compensation value and interval */ + base->COMPEN = (uint16_t)compensationValue | ((uint16_t)compensationInterval << 8U); + + /* Disable fine and enable coarse compensation */ + reg = base->CTRL; + reg &= ~(uint16_t)RTC_CTRL_FINEEN_MASK; + reg |= RTC_CTRL_COMP_EN_MASK; + base->CTRL = reg; +} + +/*! + * brief Enables the fine compensation and sets the value in the IRTC compensation register. + * + * param base The IRTC peripheral base address + * param integralValue Compensation integral value; twos complement value of the integer part + * param fractionValue Compensation fraction value expressed as number of clock cycles of a + * fixed 4.194304Mhz clock that have to be added. + * param accumulateFractional Flag indicating if we want to add to previous fractional part; + * true: Add to previously accumulated fractional part, + * false: Start afresh and overwrite current value + */ +void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional) +{ + if (!accumulateFractional) + { + /* Disable compensation to clear previous accumulated fractional part */ + base->CTRL &= ~(((uint16_t)1U << RTC_CTRL_COMP_EN_SHIFT) | ((uint16_t)1U << RTC_CTRL_FINEEN_SHIFT)); + } + + /* Set the compensation fractional and integral parts */ + base->COMPEN = ((uint16_t)fractionValue & 0x7FU) | (((uint16_t)integralValue & 0xFU) << 12U); + /* Enable fine compensation */ + base->CTRL |= (RTC_CTRL_COMP_EN_MASK | RTC_CTRL_FINEEN_MASK); +} + +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) + +/*! + * brief This function allows configuring the four tamper inputs. + * + * The function configures the filter properties for the three external tampers. + * It also sets up active/passive and direction of the tamper bits, which are not available + * on all platforms. + * note This function programs the tamper filter parameters. The user must gate the 32K clock to + * the RTC before calling this function. It is assumed that the time and date are set after this + * and the tamper parameters do not require to be changed again later. + * + * param base The IRTC peripheral base address + * param tamperNumber The IRTC tamper input to configure + * param tamperConfig The IRTC tamper properties + */ +void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const irtc_tamper_config_t *tamperConfig) +{ + assert(NULL != tamperConfig); + + uint16_t reg = 0; + +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION) && (FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION) + reg = base->TAMPER_DIRECTION; + /* Set whether tamper pin is active or passive */ + if (tamperConfig->activePassive) + { + /* In case of active tamper, set the direction */ + reg |= (1U << tamperNumber); + if (tamperConfig->direction) + { + /* Tamper direction is output */ + reg |= (1U << (RTC_TAMPER_DIRECTION_I_O_TAMP_SHIFT + tamperNumber)); + } + else + { + /* Tamper direction is input */ + reg &= ~(1U << (RTC_TAMPER_DIRECTION_I_O_TAMP_SHIFT + tamperNumber)); + } + } + else + { + /* Passive tampers are input only and the direction bit is read only in this case */ + reg &= ~(1U << tamperNumber); + } + base->TAMPER_DIRECTION = reg; +#endif /* FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION */ + + /* Set the filter properties for the external tamper pins */ + switch (tamperNumber) + { + case kIRTC_Tamper_0: + /* Set the pin for Tamper 0 */ +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + base->CTRL2 &= ~(uint16_t)RTC_CTRL2_WAKEUP_MODE_MASK; +#endif + reg = base->FILTER01_CFG; + reg &= ~((uint16_t)RTC_FILTER01_CFG_POL0_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR0_MASK | + (uint16_t)RTC_FILTER01_CFG_CLK_SEL0_MASK); + reg |= (RTC_FILTER01_CFG_POL0(tamperConfig->pinPolarity) | + RTC_FILTER01_CFG_FIL_DUR0(tamperConfig->filterDuration) | + RTC_FILTER01_CFG_CLK_SEL0(tamperConfig->filterClk)); + base->FILTER01_CFG = reg; + break; + case kIRTC_Tamper_1: + reg = base->FILTER01_CFG; + reg &= ~((uint16_t)RTC_FILTER01_CFG_POL1_MASK | (uint16_t)RTC_FILTER01_CFG_FIL_DUR1_MASK | + (uint16_t)RTC_FILTER01_CFG_CLK_SEL1_MASK); + reg |= (RTC_FILTER01_CFG_POL1(tamperConfig->pinPolarity) | + RTC_FILTER01_CFG_FIL_DUR1(tamperConfig->filterDuration) | + RTC_FILTER01_CFG_CLK_SEL1(tamperConfig->filterClk)); + base->FILTER01_CFG = reg; + break; +#if defined(FSL_FEATURE_RTC_HAS_FILTER23_CFG) && FSL_FEATURE_RTC_HAS_FILTER23_CFG + case kIRTC_Tamper_2: + reg = base->FILTER23_CFG; + reg &= ~((uint16_t)RTC_FILTER23_CFG_POL2_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR2_MASK | + (uint16_t)RTC_FILTER23_CFG_CLK_SEL2_MASK); + reg |= (RTC_FILTER23_CFG_POL2(tamperConfig->pinPolarity) | + RTC_FILTER23_CFG_FIL_DUR2(tamperConfig->filterDuration) | + RTC_FILTER23_CFG_CLK_SEL2(tamperConfig->filterClk)); + base->FILTER23_CFG = reg; + break; + case kIRTC_Tamper_3: + reg = base->FILTER23_CFG; + reg &= ~((uint16_t)RTC_FILTER23_CFG_POL3_MASK | (uint16_t)RTC_FILTER23_CFG_FIL_DUR3_MASK | + (uint16_t)RTC_FILTER23_CFG_CLK_SEL3_MASK); + reg |= (RTC_FILTER23_CFG_POL3(tamperConfig->pinPolarity) | + RTC_FILTER23_CFG_FIL_DUR3(tamperConfig->filterDuration) | + RTC_FILTER23_CFG_CLK_SEL3(tamperConfig->filterClk)); + base->FILTER23_CFG = reg; + break; +#else + case kIRTC_Tamper_2: + reg = base->FILTER2_CFG; + reg &= ~((uint16_t)RTC_FILTER2_CFG_POL2_MASK | (uint16_t)RTC_FILTER2_CFG_FIL_DUR2_MASK | + (uint16_t)RTC_FILTER2_CFG_CLK_SEL2_MASK); + reg |= (RTC_FILTER2_CFG_POL2(tamperConfig->pinPolarity) | + RTC_FILTER2_CFG_FIL_DUR2(tamperConfig->filterDuration) | + RTC_FILTER2_CFG_CLK_SEL2(tamperConfig->filterClk)); + base->FILTER2_CFG = reg; + break; +#endif + + default: + /* Internal tamper, does not have filter configuration. */ + break; + } +} + +#endif + +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) + +/*! + * brief This function reads the tamper timestamp and returns the associated tamper pin. + * + * The tamper timestamp has month, day, hour, minutes, and seconds. Ignore the year field as this + * information is not available in the tamper queue. The user should look at the RTC_YEARMON register + * for this because the expectation is that the queue is read at least once a year. + * Return the tamper pin number associated with the timestamp. + * + * param base The IRTC peripheral base address + * param tamperTimestamp The tamper timestamp + * + * return The tamper pin number + */ +uint8_t IRTC_ReadTamperQueue(RTC_Type *base, irtc_datetime_t *tamperTimestamp) +{ + assert(NULL != tamperTimestamp); + + /* Read the register 2 times to get a entry*/ + uint16_t temp1 = base->TAMPER_QUEUE; + uint16_t temp2 = base->TAMPER_QUEUE; + uint8_t tamperNum; + + /* + * Tamper queue does not store the year field as this value can be read from RTC_YEARMON. + * It is expected that the queue will be read at least once in a year. + */ + tamperTimestamp->year = 0; + /* From the first read; TAMPER_DATA[4:0] is the hour field */ + tamperTimestamp->hour = (uint8_t)temp1 & 0x1FU; + /* From the first read; TAMPER_DATA[9:5] is the day field */ + tamperTimestamp->day = (uint8_t)(temp1 >> 5U) & 0x1FU; + /* From the first read; TAMPER_DATA[13:10] is the month field */ + tamperTimestamp->month = (uint8_t)(temp1 >> 10U) & 0xFU; + + /* From the second read; TAMPER_DATA[5:0] is the seconds field */ + tamperTimestamp->second = (uint8_t)temp2 & 0x3FU; + /* From the second read; TAMPER_DATA[11:6] is the minutes field */ + tamperTimestamp->minute = (uint8_t)(temp2 >> 6U) & 0x3FU; + /* From the second read; TAMPER_DATA[14:12] is the tamper index */ + tamperNum = (uint8_t)(temp2 >> 12U) & 0x7U; + + return tamperNum; +} + +#endif /* FSL_FEATURE_RTC_HAS_TAMPER_QUEUE */ +#endif /* FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE */ + +/*! + * brief Select which clock to output from RTC. + * + * Select which clock to output from RTC for other modules to use inside SoC, for example, + * RTC subsystem needs RTC to output 1HZ clock for sub-second counter. + * + * param base IRTC peripheral base address + * param cloOut select clock to use for output + */ +void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut) +{ + uint16_t ctrlVal = base->CTRL; + + ctrlVal &= (uint16_t)(~RTC_CTRL_CLKOUT_MASK); + + ctrlVal |= RTC_CTRL_CLKOUT((uint16_t)clkOut); + if (clkOut == kIRTC_ClkoutCoarse1Hz) + { + ctrlVal |= RTC_CTRL_COMP_EN_MASK; + } + else if (clkOut == kIRTC_ClkoutFine1Hz) + { + ctrlVal |= RTC_CTRL_FINEEN_MASK; + } + else + { + /* empty else */ + } + + base->CTRL = ctrlVal; +} + +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT + +/*! + * brief Select which clock is used by RTC. + * + * Select which clock is used by RTC to output to the peripheral + * and divided to generate a 512 Hz clock and a 1 Hz clock. + * + * param base IRTC peripheral base address + * param clkSelect select clock used by RTC + */ +void IRTC_ConfigClockSelect(RTC_Type *base, irtc_clock_select_t clkSelect) +{ + uint16_t ctrlVal = base->CTRL; + + ctrlVal &= (uint16_t)(~RTC_CTRL_CLK_SEL_MASK); + + ctrlVal |= RTC_CTRL_CLK_SEL((uint16_t)clkSelect); + + base->CTRL = ctrlVal; +} + +#endif /* FSL_FEATURE_RTC_HAS_CLOCK_SELECT */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_irtc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_irtc.h new file mode 100644 index 0000000000..98f78be185 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_irtc.h @@ -0,0 +1,852 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_IRTC_H_ +#define FSL_IRTC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup irtc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*!< Version. */ +/*@}*/ + +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT +/*! @brief IRTC clock select. */ +typedef enum _irtc_clock_select +{ + kIRTC_Clk16K = 0x0U, /*!< 16.384 kHz clock is selected.*/ + kIRTC_Clk32K = 0x1U, /*!< 32.768 kHz clock is selected.*/ +} irtc_clock_select_t; +#endif + +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) +/*! @brief IRTC filter clock source options. */ +typedef enum _irtc_filter_clock_source +{ + kIRTC_32K = 0x0U, /*!< Use 32 kHz clock source for the tamper filter.*/ + kIRTC_512 = 0x1U, /*!< Use 512 Hz clock source for the tamper filter.*/ + kIRTC_128 = 0x2U, /*!< Use 128 Hz clock source for the tamper filter.*/ + kIRTC_64 = 0x3U, /*!< Use 64 Hz clock source for the tamper filter.*/ + kIRTC_16 = 0x4U, /*!< Use 16 Hz clock source for the tamper filter.*/ + kIRTC_8 = 0x5U, /*!< Use 8 Hz clock source for the tamper filter.*/ + kIRTC_4 = 0x6U, /*!< Use 4 Hz clock source for the tamper filter.*/ + kIRTC_2 = 0x7U /*!< Use 2 Hz clock source for the tamper filter.*/ +} irtc_filter_clock_source_t; + +/*! @brief IRTC Tamper pins. */ +typedef enum _irtc_tamper_pins +{ + kIRTC_Tamper_0 = 0U, /*!< External Tamper 0 */ + kIRTC_Tamper_1, /*!< External Tamper 1 */ + kIRTC_Tamper_2, /*!< External Tamper 2 */ + kIRTC_Tamper_3 /*!< Internal tamper, does not have filter configuration */ +} irtc_tamper_pins_t; +#endif + +/*! @brief List of IRTC interrupts */ +typedef enum _irtc_interrupt_enable +{ +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) + kIRTC_TamperInterruptEnable = RTC_IER_TAMPER_IE_MASK, /*!< Tamper Interrupt Enable */ +#endif + kIRTC_AlarmInterruptEnable = RTC_IER_ALM_IE_MASK, /*!< Alarm Interrupt Enable */ + kIRTC_DayInterruptEnable = RTC_IER_DAY_IE_MASK, /*!< Days Interrupt Enable */ + kIRTC_HourInterruptEnable = RTC_IER_HOUR_IE_MASK, /*!< Hours Interrupt Enable */ + kIRTC_MinInterruptEnable = RTC_IER_MIN_IE_MASK, /*!< Minutes Interrupt Enable */ + kIRTC_1hzInterruptEnable = RTC_IER_IE_1HZ_MASK, /*!< 1 Hz interval Interrupt Enable */ + kIRTC_2hzInterruptEnable = RTC_IER_IE_2HZ_MASK, /*!< 2 Hz interval Interrupt Enable */ + kIRTC_4hzInterruptEnable = RTC_IER_IE_4HZ_MASK, /*!< 4 Hz interval Interrupt Enable */ + kIRTC_8hzInterruptEnable = RTC_IER_IE_8HZ_MASK, /*!< 8 Hz interval Interrupt Enable */ + kIRTC_16hzInterruptEnable = RTC_IER_IE_16HZ_MASK, /*!< 16 Hz interval Interrupt Enable */ + kIRTC_32hzInterruptEnable = RTC_IER_IE_32HZ_MASK, /*!< 32 Hz interval Interrupt Enable */ + kIRTC_64hzInterruptEnable = RTC_IER_IE_64HZ_MASK, /*!< 64 Hz interval Interrupt Enable */ + kIRTC_128hzInterruptEnable = RTC_IER_IE_128HZ_MASK, /*!< 128 Hz interval Interrupt Enable */ + kIRTC_256hzInterruptEnable = RTC_IER_IE_256HZ_MASK, /*!< 256 Hz interval Interrupt Enable */ + kIRTC_512hzInterruptEnable = RTC_IER_IE_512HZ_MASK, /*!< 512 Hz interval Interrupt Enable */ +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + kIRTC_WakeTimerInterruptEnable = (RTC_WAKE_TIMER_CTRL_INTR_EN_MASK << 16U), /*!< Wake timer Interrupt Enable */ +#endif +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && FSL_FEATURE_RTC_HAS_TAMPER_QUEUE + kIRTC_TamperQueueFullInterruptEnable = + (RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK << 24U), /*!< Tamper queue full Interrupt Enable */ +#endif +} irtc_interrupt_enable_t; + +/*! @brief List of IRTC flags */ +typedef enum _irtc_status_flags +{ +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) + kIRTC_TamperFlag = RTC_ISR_TAMPER_IS_MASK, /*!< Tamper Status flag*/ +#endif + kIRTC_AlarmFlag = RTC_ISR_ALM_IS_MASK, /*!< Alarm Status flag */ + kIRTC_DayFlag = RTC_ISR_DAY_IS_MASK, /*!< Days Status flag */ + kIRTC_HourFlag = RTC_ISR_HOUR_IS_MASK, /*!< Hour Status flag */ + kIRTC_MinFlag = RTC_ISR_MIN_IS_MASK, /*!< Minutes Status flag */ + kIRTC_1hzFlag = RTC_ISR_IS_1HZ_MASK, /*!< 1 Hz interval status flag */ + kIRTC_2hzFlag = RTC_ISR_IS_2HZ_MASK, /*!< 2 Hz interval status flag*/ + kIRTC_4hzFlag = RTC_ISR_IS_4HZ_MASK, /*!< 4 Hz interval status flag*/ + kIRTC_8hzFlag = RTC_ISR_IS_8HZ_MASK, /*!< 8 Hz interval status flag*/ + kIRTC_16hzFlag = RTC_ISR_IS_16HZ_MASK, /*!< 16 Hz interval status flag*/ + kIRTC_32hzFlag = RTC_ISR_IS_32HZ_MASK, /*!< 32 Hz interval status flag*/ + kIRTC_64hzFlag = RTC_ISR_IS_64HZ_MASK, /*!< 64 Hz interval status flag*/ + kIRTC_128hzFlag = RTC_ISR_IS_128HZ_MASK, /*!< 128 Hz interval status flag*/ + kIRTC_256hzFlag = RTC_ISR_IS_256HZ_MASK, /*!< 256 Hz interval status flag*/ + kIRTC_512hzFlag = RTC_ISR_IS_512HZ_MASK, /*!< 512 Hz interval status flag*/ + kIRTC_InvalidFlag = (RTC_STATUS_INVAL_BIT_MASK << 16U), /*!< Indicates if time/date counters are invalid */ + kIRTC_WriteProtFlag = (RTC_STATUS_WRITE_PROT_EN_MASK << 16U), /*!< Write protect enable status flag */ +#if !defined(FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG) || (!FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG) + kIRTC_CpuLowVoltFlag = (RTC_STATUS_CPU_LOW_VOLT_MASK << 16U), /*!< CPU low voltage warning flag */ +#endif +#if !defined(FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG) || (!FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG) + kIRTC_ResetSrcFlag = (RTC_STATUS_RST_SRC_MASK << 16U), /*!< Reset source flag */ +#endif + kIRTC_CmpIntFlag = (RTC_STATUS_CMP_INT_MASK << 16U), /*!< Compensation interval status flag */ + kIRTC_BusErrFlag = (RTC_STATUS_BUS_ERR_MASK << 16U), /*!< Bus error flag */ + kIRTC_CmpDoneFlag = (RTC_STATUS_CMP_DONE_MASK << 16U), /*!< Compensation done flag */ +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + kIRTC_WakeTimerFlag = (RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK << 28U) /*!< Wake timer status flag */ +#endif +} irtc_status_flags_t; + +/*! @brief IRTC alarm match options */ +typedef enum _irtc_alarm_match +{ + kRTC_MatchSecMinHr = 0U, /*!< Only match second, minute and hour */ + kRTC_MatchSecMinHrDay = 1U, /*!< Only match second, minute, hour and day */ + kRTC_MatchSecMinHrDayMnth = 2U, /*!< Only match second, minute, hour, day and month */ + kRTC_MatchSecMinHrDayMnthYr = 3U /*!< Only match second, minute, hour, day, month and year */ +} irtc_alarm_match_t; + +#if !defined(FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) || (!FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) +/*! @brief List of RTC Oscillator capacitor load settings */ +typedef enum _irtc_osc_cap_load +{ + kIRTC_Capacitor2p = (1U << 1U), /*!< 2pF capacitor load */ + kIRTC_Capacitor4p = (1U << 2U), /*!< 4pF capacitor load */ + kIRTC_Capacitor8p = (1U << 3U), /*!< 8pF capacitor load */ + kIRTC_Capacitor16p = (1U << 4U) /*!< 16pF capacitor load */ +} irtc_osc_cap_load_t; +#endif + +/*! @brief IRTC clockout select. */ +typedef enum _irtc_clockout_sel +{ + kIRTC_ClkoutNo = 0U, /*!< No clock out */ + kIRTC_ClkoutFine1Hz, /*!< clock out fine 1Hz */ + kIRTC_Clkout32kHz, /*!< clock out 32.768kHz */ + kIRTC_ClkoutCoarse1Hz /*!< clock out coarse 1Hz */ +} irtc_clockout_sel_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _irtc_datetime +{ + uint16_t year; /*!< Range from 1984 to 2239.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t weekDay; /*!< Range from 0(Sunday) to 6(Saturday). */ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} irtc_datetime_t; + +/*! @brief Structure is used to hold the daylight saving time */ +typedef struct _irtc_daylight_time +{ + uint8_t startMonth; /*!< Range from 1 to 12 */ + uint8_t endMonth; /*!< Range from 1 to 12 */ + uint8_t startDay; /*!< Range from 1 to 31 (depending on month) */ + uint8_t endDay; /*!< Range from 1 to 31 (depending on month) */ + uint8_t startHour; /*!< Range from 0 to 23 */ + uint8_t endHour; /*!< Range from 0 to 23 */ +} irtc_daylight_time_t; + +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) +/*! @brief Structure is used to define the parameters to configure a RTC tamper event. */ +typedef struct _irtc_tamper_config +{ +#if FSL_FEATURE_RTC_HAS_TAMPER_DIRECTION + bool activePassive; /*!< true: configure tamper as active; false: passive tamper */ + bool direction; /*!< true: configure tamper direction as output; false: configure as input; + this is only used if a tamper pin is defined as active */ +#endif + bool pinPolarity; /*!< true: tamper has active low polarity; + false: active high polarity */ + irtc_filter_clock_source_t filterClk; /*!< Clock source for the tamper filter */ + uint8_t filterDuration; /*!< Tamper filter duration.*/ +} irtc_tamper_config_t; +#endif + +/*! + * @brief RTC config structure + * + * This structure holds the configuration settings for the RTC peripheral. To initialize this + * structure to reasonable defaults, call the IRTC_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _irtc_config +{ +#if !defined(FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) || (!FSL_FEATURE_RTC_HAS_NO_CTRL2_WAKEUP_MODE) + bool wakeupSelect; /*!< true: Tamper pin 0 is used to wakeup the chip; + false: Tamper pin 0 is used as the tamper pin */ +#endif +#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) + bool timerStdMask; /*!< true: Sampling clocks gated in standby mode; + false: Sampling clocks not gated */ +#endif + irtc_alarm_match_t alrmMatch; /*!< Pick one option from enumeration :: irtc_alarm_match_t */ +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT + irtc_clock_select_t clockSelect; /*!< Pick one option from enumeration :: irtc_clock_select_t */ +#endif +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE + bool disableClockOutput; /*!< true: The selected clock is not output to other peripherals; + false: The selected clock is output to other peripherals */ +#endif +} irtc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the IRTC clock and configures the peripheral for basic operation. + * + * This function initiates a soft-reset of the IRTC module, this has not effect on DST, + * calendaring, standby time and tamper detect registers. + * + * @note This API should be called at the beginning of the application using the IRTC driver. + * + * @param base IRTC peripheral base address + * @param config Pointer to user's IRTC config structure. + * + * @return kStatus_Fail if we cannot disable register write protection + */ +status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config); + +/*! + * @brief Gate the IRTC clock + * + * @param base IRTC peripheral base address + */ +static inline void IRTC_Deinit(RTC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Rtc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Fill in the IRTC config struct with the default settings + * + * The default values are: + * @code + * config->wakeupSelect = true; + * config->timerStdMask = false; + * config->alrmMatch = kRTC_MatchSecMinHr; + * @endcode + * @param config Pointer to user's IRTC config structure. + */ +void IRTC_GetDefaultConfig(irtc_config_t *config); + +/*! @}*/ + +/*! + * @name Current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the IRTC date and time according to the given time structure. + * + * The IRTC counter is started after the time is set. + * + * @param base IRTC peripheral base address + * @param datetime Pointer to structure where the date and time details to set are stored + * + * @return kStatus_Success: success in setting the time and starting the IRTC + * kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect. + */ +status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime); + +/*! + * @brief Gets the IRTC time and stores it in the given time structure. + * + * @param base IRTC peripheral base address + * @param datetime Pointer to structure where the date and time details are stored. + */ +void IRTC_GetDatetime(RTC_Type *base, irtc_datetime_t *datetime); + +/*! + * @brief Sets the IRTC alarm time + * + * @param base RTC peripheral base address + * @param alarmTime Pointer to structure where the alarm time is stored. + * + * @note weekDay field of alarmTime is not used during alarm match and should be set to 0 + * + * @return kStatus_Success: success in setting the alarm + * kStatus_InvalidArgument: error in setting the alarm. Error occurs because the alarm + * datetime format is incorrect. + */ +status_t IRTC_SetAlarm(RTC_Type *base, const irtc_datetime_t *alarmTime); + +/*! + * @brief Returns the IRTC alarm time. + * + * @param base RTC peripheral base address + * @param datetime Pointer to structure where the alarm date and time details are stored. + */ +void IRTC_GetAlarm(RTC_Type *base, irtc_datetime_t *datetime); +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected IRTC interrupts. + * + * @param base IRTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::irtc_interrupt_enable_t + */ +static inline void IRTC_EnableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER |= (uint16_t)mask; +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + if (0U != (mask & (uint32_t)kIRTC_WakeTimerInterruptEnable)) + { + base->WAKE_TIMER_CTRL |= RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; + } +#endif +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) + if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable)) + { + base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; + } +#endif +#endif +} + +/*! + * @brief Disables the selected IRTC interrupts. + * + * @param base IRTC peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::irtc_interrupt_enable_t + */ +static inline void IRTC_DisableInterrupts(RTC_Type *base, uint32_t mask) +{ + base->IER &= ~(uint16_t)mask; +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + if (0U != (mask & (uint32_t)kIRTC_WakeTimerInterruptEnable)) + { + base->WAKE_TIMER_CTRL &= ~(uint16_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK; + } +#endif +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) + if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable)) + { + base->TAMPER_QSCR &= ~(uint16_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK; + } +#endif +#endif +} + +/*! + * @brief Gets the enabled IRTC interrupts. + * + * @param base IRTC peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::irtc_interrupt_enable_t + */ +static inline uint32_t IRTC_GetEnabledInterrupts(RTC_Type *base) +{ + uint32_t intsEnabled = base->IER; +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + intsEnabled |= (base->WAKE_TIMER_CTRL & (uint32_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U; +#endif +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) + intsEnabled |= (base->TAMPER_QSCR & (uint32_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U; +#endif +#endif + + return intsEnabled; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the IRTC status flags + * + * @param base IRTC peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::irtc_status_flags_t + */ +static inline uint32_t IRTC_GetStatusFlags(RTC_Type *base) +{ +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + return (base->ISR | ((uint32_t)base->STATUS << 16U) | ((uint32_t)base->WAKE_TIMER_CTRL << 28U)); +#else + return (base->ISR | ((uint32_t)base->STATUS << 16U)); +#endif +} + +/*! + * @brief Clears the IRTC status flags. + * + * @param base IRTC peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::irtc_status_flags_t + */ +static inline void IRTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) +{ + base->ISR = (uint16_t)mask; + base->STATUS = (base->STATUS & ~((uint16_t)RTC_STATUS_BUS_ERR_MASK | (uint16_t)RTC_STATUS_CMP_DONE_MASK)) | + ((uint16_t)(mask >> 16U)); +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) + /* TAMPER flag need clear TAMPER_SCR[TMPR_STS] filed */ + if (0U != (mask & (uint32_t)kIRTC_TamperFlag)) + { + base->TAMPER_SCR |= RTC_TAMPER_SCR_TMPR_STS_MASK; + } +#endif +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM + if (0U != (mask & (uint32_t)kIRTC_WakeTimerFlag)) + { + base->WAKE_TIMER_CTRL |= RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK; + } +#endif +} + +/*! @}*/ + +#if !defined(FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) || (!FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) + +/*! + * @brief This function sets the specified capacitor configuration for the RTC oscillator. + * + * @param base IRTC peripheral base address + * @param capLoad Oscillator loads to enable. This is a logical OR of members of the + * enumeration ::irtc_osc_cap_load_t + */ +static inline void IRTC_SetOscCapLoad(RTC_Type *base, uint16_t capLoad) +{ + uint16_t reg = base->GP_DATA_REG; + + reg &= ~((uint16_t)kIRTC_Capacitor2p | (uint16_t)kIRTC_Capacitor4p | (uint16_t)kIRTC_Capacitor8p | + (uint16_t)kIRTC_Capacitor16p); + reg |= capLoad; + + base->GP_DATA_REG = reg; +} + +#endif + +/*! + * @brief Locks or unlocks IRTC registers for write access. + * + * @note When the registers are unlocked, they remain in unlocked state for + * 2 seconds, after which they are locked automatically. After + * power-on-reset, the registers come out unlocked and they are locked + * automatically 15 seconds after power on. + * + * @param base IRTC peripheral base address + * @param lock true: Lock IRTC registers; false: Unlock IRTC registers. + * + * @return kStatus_Success: if lock or unlock operation is successful + * kStatus_Fail: if lock or unlock operation fails even after multiple retry attempts + */ +status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock); + +/*! + * @brief Performs a software reset on the IRTC module. + * + * Clears contents of alarm, interrupt (status and enable except tamper interrupt enable bit) + * registers, STATUS[CMP_DONE] and STATUS[BUS_ERR]. This has no effect on DST, calendaring, standby time + * and tamper detect registers. + * + * @param base IRTC peripheral base address + */ +static inline void IRTC_Reset(RTC_Type *base) +{ + base->CTRL |= RTC_CTRL_SWR_MASK; +} + +#if !defined(FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) || (!FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) + +/*! + * @brief Enable/disable 32 kHz RTC OSC clock during RTC register write + * + * @param base IRTC peripheral base address + * @param enable Enable/disable 32 kHz RTC OSC clock. + * - true: Enables the oscillator. + * - false: Disables the oscillator. + * + */ +static inline void IRTC_Enable32kClkDuringRegisterWrite(RTC_Type *base, bool enable) +{ + uint16_t mask = RTC_GP_DATA_REG_CFG0_MASK; + if (enable) + { + base->GP_DATA_REG &= ~mask; + } + else + { + base->GP_DATA_REG |= mask; + } +} + +#endif + +/*! + * @brief Select which clock to output from RTC. + * + * Select which clock to output from RTC for other modules to use inside SoC, for example, + * RTC subsystem needs RTC to output 1HZ clock for sub-second counter. + * + * @param base IRTC peripheral base address + * @param cloOut select clock to use for output, + */ +void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut); + +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT + +/*! + * @brief Select which clock is used by RTC. + * + * Select which clock is used by RTC to output to the peripheral + * and divided to generate a 512 Hz clock and a 1 Hz clock. + * + * @param base IRTC peripheral base address + * @param clkSelect select clock used by RTC + */ +void IRTC_ConfigClockSelect(RTC_Type *base, irtc_clock_select_t clkSelect); + +#endif /* FSL_FEATURE_RTC_HAS_CLOCK_SELECT */ + +#if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE + +/*! + * @brief Determines whether the selected clock is output to other peripherals. + * + * Determines whether the selected clock is output to other peripherals. + * + * @param base IRTC peripheral base address + * @param enable determine whether the selected clock is output to other peripherals + */ +static inline void IRTC_EnableClockOutputToPeripheral(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL &= ~(uint16_t)RTC_CTRL_CLKO_DIS_MASK; + } + else + { + base->CTRL |= RTC_CTRL_CLKO_DIS_MASK; + } +} + +#endif /* FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE */ + +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) + +/*! + * @brief Gets the IRTC Tamper status flags + * + * @param base IRTC peripheral base address + * + * @return The Tamper status value. + */ +static inline uint8_t IRTC_GetTamperStatusFlag(RTC_Type *base) +{ + return (uint8_t)((base->TAMPER_SCR & RTC_TAMPER_SCR_TMPR_STS_MASK) >> RTC_TAMPER_SCR_TMPR_STS_SHIFT); +} + +/*! + * @brief Gets the IRTC Tamper status flags + * + * @param base IRTC peripheral base address + * + */ +static inline void IRTC_ClearTamperStatusFlag(RTC_Type *base) +{ + /* Writing '1' to this field clears the tamper status.*/ + base->TAMPER_SCR |= RTC_TAMPER_SCR_TMPR_STS_MASK; +} + +/*! + * @brief Set tamper configuration over + * + * Note that this API is neeeded after call IRTC_SetTamperParams to configure tamper events to + * notify IRTC module that tamper configuration process is over. + * + * @param base IRTC peripheral base address + * + */ +static inline void IRTC_SetTamperConfigurationOver(RTC_Type *base) +{ + /* Set tamper configuration over.*/ + base->CTRL2 |= RTC_CTRL2_TAMP_CFG_OVER_MASK; +} + +#endif + +/*! + * @name Daylight Savings Interface + * @{ + */ + +/*! + * @brief Sets the IRTC daylight savings start and stop date and time. + * + * It also enables the daylight saving bit in the IRTC control register + * + * @param base IRTC peripheral base address + * @param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime); + +/*! + * @brief Gets the IRTC daylight savings time and stores it in the given time structure. + * + * @param base IRTC peripheral base address + * @param datetime Pointer to a structure where the date and time details are stored. + */ +void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime); + +/*! @}*/ + +/*! + * @name Time Compensation Interface + * @{ + */ + +/*! + * @brief Enables the coarse compensation and sets the value in the IRTC compensation register. + * + * @param base IRTC peripheral base address + * @param compensationValue Compensation value is a 2's complement value. + * @param compensationInterval Compensation interval. + */ +void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8_t compensationInterval); + +/*! + * @brief Enables the fine compensation and sets the value in the IRTC compensation register. + * + * @param base The IRTC peripheral base address + * @param integralValue Compensation integral value; twos complement value of the integer part + * @param fractionValue Compensation fraction value expressed as number of clock cycles of a + * fixed 4.194304Mhz clock that have to be added. + * @param accumulateFractional Flag indicating if we want to add to previous fractional part; + * true: Add to previously accumulated fractional part, + * false: Start afresh and overwrite current value + */ +void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional); + +/*! @}*/ + +#if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) + +/*! + * @name Tamper Interface + * @{ + */ + +/*! + * @brief This function allows configuring the four tamper inputs. + * + * The function configures the filter properties for the three external tampers. + * It also sets up active/passive and direction of the tamper bits, which are not available + * on all platforms. + * @note This function programs the tamper filter parameters. The user must gate the 32K clock to + * the RTC before calling this function. It is assumed that the time and date are set after this + * and the tamper parameters do not require to be changed again later. + * + * @param base The IRTC peripheral base address + * @param tamperNumber The IRTC tamper input to configure + * @param tamperConfig The IRTC tamper properties + */ +void IRTC_SetTamperParams(RTC_Type *base, irtc_tamper_pins_t tamperNumber, const irtc_tamper_config_t *tamperConfig); + +#if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) + +/*! + * @brief This function reads the tamper timestamp and returns the associated tamper pin. + * + * The tamper timestamp has month, day, hour, minutes, and seconds. Ignore the year field as this + * information is not available in the tamper queue. The user should look at the RTC_YEARMON register + * for this because the expectation is that the queue is read at least once a year. + * Return the tamper pin number associated with the timestamp. + * + * @param base The IRTC peripheral base address + * @param tamperTimestamp The tamper timestamp + * + * @return The tamper pin number + */ +uint8_t IRTC_ReadTamperQueue(RTC_Type *base, irtc_datetime_t *tamperTimestamp); + +/*! + * @brief Gets the IRTC Tamper queue full status + * + * @param base IRTC peripheral base address + * + * @retval true Tamper queue is full. + * @retval false Tamper queue is not full. + */ +static inline bool IRTC_GetTamperQueueFullStatus(RTC_Type *base) +{ + return ((0U != (base->TAMPER_SCR & RTC_TAMPER_QSCR_Q_FULL_MASK)) ? true : false); +} + +/*! + * @brief Clear the IRTC Tamper queue full status + * + * @param base IRTC peripheral base address + * + */ +static inline void IRTC_ClearTamperQueueFullStatus(RTC_Type *base) +{ + base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_CLEAR_MASK; +} +#endif /* FSL_FEATURE_RTC_HAS_TAMPER_QUEUE */ + +/*! @}*/ + +#endif + +#if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM +/*! + * @name RTC subsystem Interface + * @{ + */ + +/*! + * @brief Enable the RTC wake-up timer. + * + * 1HZ clock out selected via call to API IRTC_ConfigClockOut in order for the subsecond + * counter to synchronize with the RTC_SECONDS counter. + * + * @param base RTC peripheral base address + * @param enable Use/Un-use the sub-second counter. + * - true: Use RTC wake-up timer at the same time. + * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. + */ +static inline void IRTC_EnableSubsecondCounter(RTC_Type *base, bool enable) +{ + if (enable) + { + base->SUBSECOND_CTRL |= RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK; + } + else + { + base->SUBSECOND_CTRL &= ~RTC_SUBSECOND_CTRL_SUB_SECOND_CNT_EN_MASK; + } +} + +/*! + * @brief Read the actual RTC sub-second COUNT value. + * + * @param base RTC peripheral base address + * + * @return The actual RTC sub-second COUNT value. + */ +static inline uint32_t IRTC_GetSubsecondCount(RTC_Type *base) +{ + uint32_t a, b; + + /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ + do + { + a = base->SUBSECOND_CNT; + b = base->SUBSECOND_CNT; + } while (a != b); + + return b; +} +/*! + * @brief Set countdown value to the RTC wake timer counter register. + * + * @param base RTC peripheral base address + * @param enable1kHzClk Enable 1kHz clock source for the wake timer, else use the 32kHz clock. + * @param wakeupValue The value to be loaded into the WAKE register in wake timer counter. + */ +static inline void IRTC_SetWakeupCount(RTC_Type *base, bool enable1kHzClk, uint32_t wakeupValue) +{ + /* Config whether enable the wakeup counter */ + uint32_t writeVal; + writeVal = base->WAKE_TIMER_CTRL; + base->WAKE_TIMER_CTRL = RTC_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK; + + if (enable1kHzClk) + { + writeVal |= RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; + } + else + { + writeVal &= ~RTC_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; + } + + base->WAKE_TIMER_CTRL = writeVal; + /* Set the start countdown value into the RTC WAKE register */ + base->WAKE_TIMER_CNT = wakeupValue; +} + +/*! + * @brief Read the actual value from the WAKE register value in RTC wake timer. + * + * @param base RTC peripheral base address + * + * @return The actual value of the WAKE register value in wake timer counter. + */ +static inline uint32_t IRTC_GetWakeupCount(RTC_Type *base) +{ + /* Read current wake-up countdown value */ + return base->WAKE_TIMER_CNT; +} + +/*! @}*/ +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_IRTC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_itrc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_itrc.c new file mode 100644 index 0000000000..27120e076a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_itrc.c @@ -0,0 +1,293 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_itrc.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.itrc" +#endif + +#define b11 0x3UL +#define b10 0x2u +#define b01 0x1u + +#define OUT_SEL_0_COUNT (16u) +#define OUT_SEL_1_COUNT (32u) +#define OUT_SEL_2_COUNT (48u) + +/* Value used to trigger SW Events */ +#define SW_EVENT_VAL 0x5AA55AA5u + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * Weak implementation of ITRC IRQ, should be re-defined by user when using ITRC IRQ + */ +__WEAK void ITRC0_DriverIRQHandler(void) +{ + /* ITRC generates IRQ until corresponding bit in STATUS is cleared by calling + * ITRC_ClearStatus(ITRC,((uint32_t)kITRC_Irq) + */ +} + +/*! + * brief Clear ITRC status + * + * This function clears corresponding ITRC event or action in STATUS register. + * + * param base ITRC peripheral base address + * param word 32bit word represent corresponding event/action in STATUS register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word) +{ + /* If reserved/unused bits in STATUS register are set in 'word' parameter, return kStatus_InvalidArgument */ + if ((word & ~(IN_0_15_EVENTS_MASK | OUT_ACTIONS_MASK)) != 0u) + { + return kStatus_InvalidArgument; + } + + base->STATUS |= word; + + return kStatus_Success; +} + +/*! + * brief Get ITRC Status + * + * This function returns ITRC STATUS1 register value. + * + * param base ITRC peripheral base address + * return Value of ITRC STATUS register + */ +uint32_t ITRC_GetStatus(ITRC_Type *base) +{ + return base->STATUS; +} + +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) +/*! + * brief Clear ITRC status 1 + * + * This function clears corresponding ITRC event or action in STATUS1 register. + * + * param base ITRC peripheral base address + * param word 32bit word represent corresponding event/action in STATUS1 register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus1(ITRC_Type *base, uint32_t word) +{ + /* If reserved/unused bits in STATUS register are set in 'word' parameter, return kStatus_InvalidArgument */ + if ((word & ~(IN_16_47_EVENTS_MASK)) != 0u) + { + return kStatus_InvalidArgument; + } + + base->STATUS1 |= word; + + return kStatus_Success; +} + +/*! + * brief Get ITRC Status 1 + * + * This function returns ITRC STATUS1 register value. + * + * param base ITRC peripheral base address + * return Value of ITRC STATUS1 register + */ +uint32_t ITRC_GetStatus1(ITRC_Type *base) +{ + return base->STATUS1; +} + +#endif /* defined(ITRC_STATUS1_IN16_STATUS_MASK) */ + +/*! + * brief Clear all ITRC status + * + * This clears all event and action in STATUS and STATUS1 registers. + * + * param base ITRC peripheral base address + * return kStatus_Success + */ +status_t ITRC_ClearAllStatus(ITRC_Type *base) +{ + base->STATUS |= (IN_0_15_EVENTS_MASK | OUT_ACTIONS_MASK); +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) + base->STATUS1 |= (IN_16_47_EVENTS_MASK); +#endif /* defined(ITRC_STATUS1_IN16_STATUS_MASK) */ + + return kStatus_Success; +} + +/*! + * brief Trigger ITRC SW Event 0 + * + * This funciton set SW_EVENT0 register with value !=0 which triggers ITRC SW Event 0. + * + * param base ITRC peripheral base address + */ +void ITRC_SetSWEvent0(ITRC_Type *base) +{ + base->SW_EVENT0 = SW_EVENT_VAL; +} + +/*! + * brief Trigger ITRC SW Event 1 + * + * This funciton set SW_EVENT1 register with value !=0 which triggers ITRC SW Event 1. + * + * param base ITRC peripheral base address + */ +void ITRC_SetSWEvent1(ITRC_Type *base) +{ + base->SW_EVENT1 = SW_EVENT_VAL; +} + +/*! + * brief Set ITRC Action to Event + * + * This function sets input Event signal to corresponding output Action response signal. + * + * param base ITRC peripheral base address + * param out ITRC OUT signal action + * param in ITRC IN signal event + * param lock if set locks INx_SEL configuration. This can be cleared only by PMC Core reset. + * param enable if set input Event will be selected for output Action, otherwise disable (if not already locked). + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_SetActionToEvent( + ITRC_Type *base, itrc_out_signals_t out, itrc_input_signals_t in, itrc_lock_t lock, itrc_enable_t enable) +{ + uint32_t sel0, sel1, index, select_AND_mask; + + /* prepare values for INx_SEL0/1 bit-field according to secure techniques and register behavior + * +------------+------------+------------------+---------------------------+ + * | INx_SEL0 | INx_SEL1 | Signal selected? | Writable field? | + * +------------+------------+------------------+---------------------------+ + * | 10 | 10 | No | Yes (default after reset) | + * | 01 | 10 | Yes | Yes | + * | don't care | !="10" | Yes | No | + * | 00 or 11 | don't care | Yes | No | + * +------------+------------+------------------+---------------------------+ + */ + if ((lock == kITRC_Unlock) && (enable == kITRC_Disable)) + { + sel0 = b10; + sel1 = b10; + } + else if ((lock == kITRC_Unlock) && (enable == kITRC_Enable)) + { + sel0 = b01; + sel1 = b10; + } + else + { + sel0 = b11; + sel1 = b11; + } + + /* Compute index for INx_SEL0/1 bit-field within OUTy_SEL0/1 registers */ + if ((uint32_t)in < OUT_SEL_0_COUNT) + { + index = 2u * (uint32_t)in; + } + else if (OUT_SEL_0_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_1_COUNT) + { + index = 2u * ((uint32_t)in - OUT_SEL_0_COUNT); + } + else if (OUT_SEL_1_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_2_COUNT) + { + index = 2u * ((uint32_t)in - OUT_SEL_1_COUNT); + } + else + { + return kStatus_InvalidArgument; + } + + /* Prepare AND mask to set INx_SEL0 accordingly */ + select_AND_mask = ~(uint32_t)(b11 << index); + + /* Configure OUT action for IN event */ + for (uint8_t i = (uint8_t)kITRC_Irq; i < ITRC_OUT_COUNT; i++) + { + /* Loop over all OUT actions, set only requested one */ + if (i == (uint8_t)out) + { + if ((uint32_t)in < OUT_SEL_0_COUNT) + { + base->OUT_SEL[i][0] = (base->OUT_SEL[i][0] & select_AND_mask) | (sel0 << index); + base->OUT_SEL[i][1] |= sel1 << index; + break; + } +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_COUNT) + else if (OUT_SEL_0_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_1_COUNT) + { + base->OUT_SEL_1[i][0] = (base->OUT_SEL[i][0] & select_AND_mask) | (sel0 << index); + base->OUT_SEL_1[i][1] |= sel1 << index; + break; + } +#endif /* defined(OUT_SEL_1) */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_COUNT) + else if (OUT_SEL_1_COUNT <= (uint32_t)in && (uint32_t)in < OUT_SEL_2_COUNT) + { + base->OUT_SEL_2[i][0] = (base->OUT_SEL[i][0] & select_AND_mask) | (sel0 << index); + base->OUT_SEL_2[i][1] |= sel1 << index; + break; + } + else + { + /* All the cases have been listed above, this branch should not be reached. */ + return kStatus_InvalidArgument; + } +#endif /* defined(OUT_SEL_2) */ + } + } + + return kStatus_Success; +} + +/*! + * brief Initialize ITRC + * + * This function initializes ITRC by enabling IRQ. + * + * param base ITRC peripheral base address + * return Status of the init operation + */ +status_t ITRC_Init(ITRC_Type *base) +{ + NVIC_EnableIRQ(ITRC0_IRQn); + + return kStatus_Success; +} + +/*! + * brief Deinitialize ITRC + * + * This function just disable ITRC IRQ. + * + * param base ITRC peripheral base address + */ +void ITRC_Deinit(ITRC_Type *base) +{ + NVIC_DisableIRQ(ITRC0_IRQn); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_itrc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_itrc.h new file mode 100644 index 0000000000..6e0817da6c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_itrc.h @@ -0,0 +1,322 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_ITRC_H_ +#define FSL_ITRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ITRC + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines ITRC driver version 2.3.0. + * + * Change log: + * - Version 2.3.0 + * - Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM + * - Version 2.2.0 + * - Update driver to new version and input events + * - Version 2.1.0 + * - Make SYSCON glitch platform dependent + * - Version 2.0.0 + * - initial version + */ +#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +typedef enum _itrc_input_signals +{ + kITRC_Glitch = 0U, + kITRC_Tamper = 1U, + kITRC_Cdog = 2U, + kITRC_BodVbat = 3u, + kITRC_BodVdd = 4u, + kITRC_Watchdog = 5u, + kITRC_FlashEcc = 6u, + kITRC_Ahb = 7u, + kITRC_ElsErr = 8u, +#if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) + kITRC_SysconGlitch = 9u, +#endif + kITRC_Pkc = 10u, +#if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK) + kITRC_Cdog1 = 11u, +#endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN11_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK) + kITRC_Watchdog1 = 12u, +#endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN12_SELn_MASK*/ +#if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK) + kITRC_Freqme = 13u, +#endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK */ + kITRC_SwEvent0 = 14u, + kITRC_SwEvent1 = 15u, +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK) + kITRC_VddSysLow = 16u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK) + kITRC_VddIoLow = 17u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN17_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK) + kITRC_VddTemp = 19u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN19_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK) + kITRC_VddClock = 20u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN20_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK) + kITRC_INTM0 = 21u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN21_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK) + kITRC_INTM1 = 22u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN22_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK) + kITRC_INTM2 = 23u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN23_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK) + kITRC_INTM3 = 24u, +#endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN24_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN25_SELn_MASK) && \ + defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN32_SELn_MASK) + kITRC_SoCTrim0 = 25u, + kITRC_SoCTrim1 = 26u, + kITRC_SoCTrim2 = 27u, + kITRC_SoCTrim3 = 28u, + kITRC_SoCTrim4 = 29u, + kITRC_SoCTrim5 = 30u, + kITRC_SoCTrim6 = 31u, + kITRC_SoCTrim7 = 32u, +#endif /* ITRC_OUTX_SEL_x_OUTX_SELY_OUT_SEL_INxx_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN33_SELn_MASK) + kITRC_GdetSfr = 33u, +#endif /* ITRC_OUTX_SEL_x_OUTX_SELY_OUT_SEL_INxx_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK) + kITRC_VddCore = 34u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN34_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK) + kITRC_VddSys = 35u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN35_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK) + kITRC_VddIo = 36u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN36_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK) + kITRC_FlexspiGcm = 37u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN37_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK) + kITRC_Sm3Err = 46u, +#endif /* ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN46_SELn_MASK */ +#if defined(ITRC_OUTX_SEL_2_OUTX_SELY_OUT_SEL_2_IN47_SELn_MASK) + kITRC_TrngErr = 47u, +#endif /* */ +} itrc_input_signals_t; + +typedef enum _itrc_lock +{ + kITRC_Unlock = 0U, + kITRC_Lock = 1U, +} itrc_lock_t; + +typedef enum _itrc_enable +{ + kITRC_Enable = 0U, + kITRC_Disable = 1U, +} itrc_enable_t; + +typedef enum _itrc_out_signals +{ + kITRC_Irq = 0U, + kITRC_ElsReset = 1U, + kITRC_PufZeroize = 2U, + kITRC_RamZeroize = 3u, + kITRC_ChipReset = 4u, + kITRC_TamperOut = 5u, + kITRC_TamperOut1 = 6u, +} itrc_out_signals_t; + +/* Inputs 0 to 15 events mask */ +#if defined(FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH) && (FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH > 0) +#define IN_0_15_EVENTS_MASK \ + (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ + ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ + ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ + ITRC_STATUS_IN9_STATUS_MASK | ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | \ + ITRC_STATUS_IN15_STATUS_MASK) +#else +#define IN_0_15_EVENTS_MASK \ + (ITRC_STATUS_IN0_STATUS_MASK | ITRC_STATUS_IN1_STATUS_MASK | ITRC_STATUS_IN2_STATUS_MASK | \ + ITRC_STATUS_IN3_STATUS_MASK | ITRC_STATUS_IN4_STATUS_MASK | ITRC_STATUS_IN5_STATUS_MASK | \ + ITRC_STATUS_IN6_STATUS_MASK | ITRC_STATUS_IN7_STATUS_MASK | ITRC_STATUS_IN8_STATUS_MASK | \ + ITRC_STATUS_IN10_STATUS_MASK | ITRC_STATUS_IN14_STATUS_MASK | ITRC_STATUS_IN15_STATUS_MASK) +#endif /* FSL_FEATURE_ITRC_HAS_SYSCON_GLITCH */ + +/* Inputs 15 to 47 events mask */ +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) && defined(ITRC_STATUS1_IN47_STATUS) +#define IN_16_47_EVENTS_MASK \ + (ITRC_STATUS1_IN16_STATUS_MASK | ITRC_STATUS1_IN17_STATUS_MASK | ITRC_STATUS1_IN18_STATUS_MASK | \ + ITRC_STATUS1_IN19_STATUS_MASK | ITRC_STATUS1_IN20_STATUS_MASK | ITRC_STATUS1_IN24_21_STATUS_MASK | \ + ITRC_STATUS1_IN24_21_STATUS_MASK | ITRC_STATUS1_IN32_25_STATUS_MASK | ITRC_STATUS1_IN33_STATUS_MASK | \ + ITRC_STATUS1_IN34_STATUS_MASK | ITRC_STATUS1_IN35_STATUS_MASK | ITRC_STATUS1_IN36_STATUS_MASK | \ + ITRC_STATUS1_IN37_STATUS_MASK | ITRC_STATUS1_IN46_STATUS_MASK | ITRC_STATUS1_IN47_STATUS_MASK) +#endif /* ITRC_STATUS1_IN16_STATUS_MASK && ITRC_STATUS1_IN47_STATUS */ + +/* Output actions mask */ +#if defined(ITRC_STATUS_OUT6_STATUS) +#define OUT_ACTIONS_MASK \ + (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ + ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK | \ + ITRC_STATUS_OUT6_STATUS_MASK) +#else +#define OUT_ACTIONS_MASK \ + (ITRC_STATUS_OUT0_STATUS_MASK | ITRC_STATUS_OUT1_STATUS_MASK | ITRC_STATUS_OUT2_STATUS_MASK | \ + ITRC_STATUS_OUT3_STATUS_MASK | ITRC_STATUS_OUT4_STATUS_MASK | ITRC_STATUS_OUT5_STATUS_MASK) +#endif /* ITRC_STATUS_OUT6_STATUS */ + +#define ITRC_OUT_COUNT (7u) +#ifndef ITRC +#define ITRC ITRC0 +#endif + +/******************************************************************************* + * API + *******************************************************************************/ + +extern void ITRC0_DriverIRQHandler(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name ITRC Functional Operation + * @{ + */ + +/*! + * @brief Set ITRC Action to Event + * + * This function sets input Event signal to corresponding output Action response signal. + * + * @param base ITRC peripheral base address + * @param out ITRC OUT signal action + * @param in ITRC IN signal event + * @param lock if set locks INx_SEL configuration. This can be cleared only by PMC Core reset. + * @param enable if set input Event will be selected for output Action, otherwise disable (if not already locked). + * @return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_SetActionToEvent( + ITRC_Type *base, itrc_out_signals_t out, itrc_input_signals_t in, itrc_lock_t lock, itrc_enable_t enable); + +/*! + * @brief Trigger ITRC SW Event 0 + * + * This funciton set SW_EVENT0 register with value !=0 which triggers ITRC SW Event 0. + * + * @param base ITRC peripheral base address + */ +void ITRC_SetSWEvent0(ITRC_Type *base); + +/*! + * @brief Trigger ITRC SW Event 1 + * + * This funciton set SW_EVENT1 register with value !=0 which triggers ITRC SW Event 1. + * + * @param base ITRC peripheral base address + */ +void ITRC_SetSWEvent1(ITRC_Type *base); + +/*! + * @brief Get ITRC Status + * + * This function returns ITRC register status. + * + * @param base ITRC peripheral base address + * @return Value of ITRC STATUS register + */ +uint32_t ITRC_GetStatus(ITRC_Type *base); + +/*! + * @brief Clear ITRC status + * + * This function clears corresponding ITRC event or action in STATUS register. + * + * @param base ITRC peripheral base address + * @param word 32bit word represent corresponding event/action in STATUS register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * @return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus(ITRC_Type *base, uint32_t word); + +#if defined(ITRC_STATUS1_IN16_STATUS_MASK) +/*! + * @brief Get ITRC Status 1 + * + * This function returns ITRC STATUS1 register value. + * + * @param base ITRC peripheral base address + * @return Value of ITRC STATUS1 register + */ +uint32_t ITRC_GetStatus1(ITRC_Type *base); + +/*! + * brief Clear ITRC status 1 + * + * This function clears corresponding ITRC event or action in STATUS1 register. + * + * param base ITRC peripheral base address + * param word 32bit word represent corresponding event/action in STATUS1 register to be cleared (see + * ITRC_STATUS_INx/OUTx_STATUS) + * return kStatus_Success if success, kStatus_InvalidArgument otherwise + */ +status_t ITRC_ClearStatus1(ITRC_Type *base, uint32_t word); +#endif /* defined(ITRC_STATUS1_IN16_STATUS_MASK) */ + +/*! + * @brief Clear All ITRC status + * + * This function clears all event and action status. + * + * @param base ITRC peripheral base address + * @return kStatus_Success if success + */ +status_t ITRC_ClearAllStatus(ITRC_Type *base); + +/*! + * @brief Initialize ITRC + * + * This function initializes ITRC by enabling IRQ. + * + * @param base ITRC peripheral base address + * @param conf ITRC configuration structure + * @return Status of the init operation + */ +status_t ITRC_Init(ITRC_Type *base); + +/*! + * @brief Deinitialize ITRC + * + * This function deinitializes ITRC by disabling IRQ. + * + * @param base ITRC peripheral base address + */ +void ITRC_Deinit(ITRC_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group itrc */ + +#endif /* FSL_ITRC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpadc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpadc.c new file mode 100644 index 0000000000..c22741c4f5 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpadc.c @@ -0,0 +1,977 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpadc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpadc" +#endif + +#ifndef ADC_VERID_DIFFEN_MASK +#define ADC_VERID_DIFFEN_MASK (0x2U) +#endif /* ADC_VERID_DIFFEN_MASK */ + +#ifndef ADC_VERID_NUM_SEC_MASK +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#endif /* ADC_VERID_NUM_SEC_MASK */ + +#define ADC_CMDL_CHANNEL_MODE_MASK (0x60U) +#define ADC_CMDL_CHANNEL_MODE_SHIFT (5U) +#define ADC_CMDL_CHANNEL_MODE(x) \ + (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CHANNEL_MODE_SHIFT)) & ADC_CMDL_CHANNEL_MODE_MASK) + +#define GET_ADC_CFG_TPRICTRL_VALUE(val) (((uint32_t)val) & 0x3U) + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES +#define GET_ADC_CFG_TRES_VALUE(val) ((((uint32_t)val) & 0x4U) >> 2U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES +#define GET_ADC_CFG_TCMDRES_VALUE(val) ((((uint32_t)val) & 0x8U) >> 3U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI +#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((((uint32_t)val) & 0x10U) >> 4U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ + +#if defined(LPADC_RSTS) +#define LPADC_RESETS_ARRAY LPADC_RSTS +#elif defined(ADC_RSTS) +#define LPADC_RESETS_ARRAY ADC_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for LPADC module. + * + * @param base LPADC peripheral base address + */ +static uint32_t LPADC_GetInstance(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * @brief Get gain conversion result . + * + * @param gainAdjustment gain adjustment value. + */ +static uint32_t LPADC_GetGainConvResult(float gainAdjustment); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPADC bases for each instance. */ +static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPADC clocks for each instance. */ +static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(LPADC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpadcResets[] = LPADC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpadcBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_lpadcBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (s_lpadcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpadcBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) +/*! + * brief Get gain conversion Result . + * + * param gainAdjustment gain adjustment value. + */ +static uint32_t LPADC_GetGainConvResult(float gainAdjustment) +{ + uint16_t i = 0U; + uint32_t tmp32 = 0U; + uint32_t GCRa[17] = {0}; + uint32_t GCALR = 0U; + + for (i = 0x11U; i > 0U; i--) + { + tmp32 = (uint32_t)((gainAdjustment) / ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)))))); + GCRa[i - 1U] = tmp32; + gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (double)(1U << (0x10U - (i - 1U))))); + } + /* Get GCALR value calculated */ + for (i = 0x11U; i > 0U; i--) + { + GCALR += GCRa[i - 1U] * ((uint32_t)(1UL << (uint32_t)(i - 1UL))); + } + + /* to return GCALR value calculated */ + return GCALR; +} +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * brief Initializes the LPADC module. + * + * param base LPADC peripheral base address. + * param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) +{ + /* Check if the pointer is available. */ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for LPADC instance. */ + (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPADC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpadcResets[LPADC_GetInstance(base)]); +#endif + + /* Reset the module. */ + LPADC_DoResetConfig(base); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + LPADC_DoResetFIFO0(base); + LPADC_DoResetFIFO1(base); +#else + LPADC_DoResetFIFO(base); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Disable the module before setting configuration. */ + LPADC_Enable(base, false); + + /* Configure the module generally. */ + if (config->enableInDozeMode) + { + base->CTRL &= ~ADC_CTRL_DOZEN_MASK; + } + else + { + base->CTRL |= ADC_CTRL_DOZEN_MASK; + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/* ADCx_CFG. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + if (config->enableInternalClock) + { + tmp32 |= ADC_CFG_ADCKEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + if (config->enableVref1LowVoltage) + { + tmp32 |= ADC_CFG_VREF1RNG_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + if (config->enableAnalogPreliminary) + { + tmp32 |= ADC_CFG_PWREN_MASK; + } + tmp32 |= (ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ + | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + ); + + tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy)); + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES) + tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) + tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) + tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ + + base->CFG = tmp32; + + /* ADCx_PAUSE. */ + if (config->enableConvPause) + { + base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); + } + else + { + base->PAUSE = 0U; + } + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* ADCx_FCTRL0. */ + base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); + /* ADCx_FCTRL1. */ + base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); +#else + /* ADCx_FCTRL. */ + base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Enable the module after setting configuration. */ + LPADC_Enable(base, true); +} + +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * code + * config->enableInDozeMode = true; + * config->conversionAverageMode = kLPADC_ConversionAverage1; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFO0Watermark = 0U; + * config->FIFO1Watermark = 0U; + * config->FIFOWatermark = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + config->enableInternalClock = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + config->enableVref1LowVoltage = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + config->enableInDozeMode = true; +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + config->conversionAverageMode = kLPADC_ConversionAverage1; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + config->enableAnalogPreliminary = false; + config->powerUpDelay = 0x80; + config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + config->powerLevelMode = kLPADC_PowerLevelAlt1; +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + config->enableConvPause = false; + config->convPauseDelay = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->FIFO0Watermark = 0U; + config->FIFO1Watermark = 0U; +#else + config->FIFOWatermark = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} + +/*! + * brief De-initializes the LPADC module. + * + * param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base) +{ + /* Disable the module. */ + LPADC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO[index]; + + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +/*! + * brief Get the result in conversion FIFOn using blocking method. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO[index]; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO[index]; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} +#else +/*! + * brief Get the result in conversion FIFO. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO; + + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * param base LPADC peripheral base address. + * param triggerId ID for each trigger. Typically, the available value range is from 0 to 3. + * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) +{ + assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ + | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ + | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) +#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) + | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) +#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + ; + if (config->enableHardwareTrigger) + { + tmp32 |= ADC_TCTRL_HTEN_MASK; + } + + base->TCTRL[triggerId] = tmp32; +} + +/*! + * brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * code + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->targetCommandId = 0U; + config->delayPower = 0U; + config->priority = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->channelAFIFOSelect = 0U; + config->channelBFIFOSelect = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + config->enableHardwareTrigger = false; +} + +/*! + * brief Configure conversion command. + * + * note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. + * + * param base LPADC peripheral base address. + * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) +{ + assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0; + + commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ + + /* ADCx_CMDL. */ + tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + tmp32 |= ADC_CMDL_ALTB_ADCH(config->channelBNumber); /* Alternate channel B number. */ +#endif +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + tmp32 |= ADC_CMDL_ALTB_CSCALE(config->channelBScaleMode); /* Alternate channel B full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + assert(((config->sampleChannelMode >= kLPADC_SampleChannelDiffBothSideAB) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSideAB)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + assert(((config->sampleChannelMode == kLPADC_SampleChannelDiffBothSide) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + ((config->sampleChannelMode == kLPADC_SampleChannelDualSingleEndBothSide) && + (((base->VERID) & ADC_VERID_NUM_SEC_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDualSingleEndBothSide)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + + tmp32 |= ADC_CMDL_CHANNEL_MODE(config->sampleChannelMode); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + /* Enable alternate channel B.*/ + if (config->enableChannelB) + { + tmp32 |= ADC_CMDL_ALTBEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ + + base->CMD[commandId].CMDL = tmp32; + + /* ADCx_CMDH. */ + tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ + | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ + | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ + | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ + | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ +#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) + if (config->enableWaitTrigger) + { + tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ + + if (config->enableAutoChannelIncrement) + { + tmp32 |= ADC_CMDH_LWI_MASK; + } + base->CMD[commandId].CMDH = tmp32; + + /* Hardware compare settings. + * Not all Command Buffers have an associated Compare Value register. The compare function is only available on + * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be + * made before setting the CV register. + */ + + if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT)) + { + /* Set CV register. */ + base->CV[commandId] = (ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ + | ADC_CV_CVL(config->hardwareCompareValueLow)); /* Compare value low. */ + } +} + +/*! + * brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelBScaleMode = kLPADC_SampleFullScale; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * config->enableChannelB = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + config->sampleScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + config->channelBScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + config->channelNumber = 0U; +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + config->channelBNumber = 0U; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + config->chainedNextCommandNumber = 0U; /* No next command defined. */ + config->enableAutoChannelIncrement = false; + config->loopCount = 0U; + config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + config->sampleTimeMode = kLPADC_SampleTimeADCK3; + config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + config->hardwareCompareValueHigh = 0U; /* No used. */ + config->hardwareCompareValueLow = 0U; /* No used. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + config->enableWaitTrigger = false; +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + config->enableChannelB = false; /* Enable alternate channel B.*/ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ +} + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * param base LPADC peripheral base address. + * param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable) +{ + LPADC_Enable(base, false); + if (enable) + { + base->CFG |= ADC_CFG_CALOFS_MASK; + } + else + { + base->CFG &= ~ADC_CFG_CALOFS_MASK; + } + LPADC_Enable(base, true); +} + +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert(0u == LPADC_GetConvResultCount(base)); + + uint32_t mLpadcCMDL; + uint32_t mLpadcCMDH; + uint32_t mLpadcTrigger; + lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; + lpadc_conv_command_config_t mLpadcCommandConfigStruct; + lpadc_conv_result_t mLpadcResultConfigStruct; + + /* Enable the calibration function. */ + LPADC_EnableCalibration(base, true); + + /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ + mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ + mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ + mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ + + /* Set trigger0 configuration - for software trigger. */ + LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); + mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ + LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + + /* Set conversion CMD configuration. */ + LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); + mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; + LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ + + /* Do calibration. */ + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) + { + } + /* The valid bits of data are bits 14:3 in the RESFIFO register. */ + LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); + /* Disable the calibration function. */ + LPADC_EnableCalibration(base, false); + + /* restore CMD and TRG registers. */ + base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ + base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ + base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * brief Do offset calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base) +{ + LPADC_EnableOffsetCalibration(base, true); + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + LPADC_PrepareAutoCalibration(base); + LPADC_FinishAutoCalibration(base); +} + +/*! + * brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. + * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. + * + * param base LPADC peripheral base address. + */ +void LPADC_PrepareAutoCalibration(ADC_Type *base) +{ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + assert((0U == LPADC_GetConvResultCount(base, 0)) && (0U == LPADC_GetConvResultCount(base, 1))); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ + assert(LPADC_GetConvResultCount(base) == 0U); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ + + /* Request gain calibration. */ + base->CTRL |= ADC_CTRL_CAL_REQ_MASK; +} + +/*! + * brief Finish auto calibration start with LPADC_PrepareAutoCalibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_FinishAutoCalibration(ADC_Type *base) +{ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE + int32_t GCCa; + int32_t GCCb; + float GCRa; + float GCRb; +#else + uint32_t GCCa; + float GCRa; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + uint32_t GCCb; + float GCRb; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + + while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + || (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK)) +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + ) + { + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE + GCCa = (int32_t)(base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCCb = (int32_t)(base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + if (0U != ((base->GCC[0]) & 0x8000U)) + { + GCCa = GCCa - 0x10000; + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ + } + + if (0U != ((base->GCC[1]) & 0x8000U)) + { + GCCb = GCCb - 0x10000; + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ + } +#else + /* Calculate gain offset. */ + GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + /* Indicate the values are valid. */ + base->GCR[0] |= ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + base->GCR[1] |= ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * brief Get calibration value into the memory which is defined by invoker. + * + * note Please note the ADC will be disabled temporary. + * note This function should be used after finish calibration. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure, this memory block should be always powered + * on even in low power modes. + */ +void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + uint32_t i; + for (i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR0))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR0))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#else + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + ptrCalibrationValue->gainCalibrationResultA = (uint16_t)(base->GCR[0] & ADC_GCR_GCALR_MASK); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + ptrCalibrationValue->gainCalibrationResultB = (uint16_t)(base->GCR[1] & ADC_GCR_GCALR_MASK); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +/*! + * brief Set calibration value into ADC calibration registers. + * + * note Please note the ADC will be disabled temporary. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure which contains ADC's calibration value. + */ +void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + for (uint32_t i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + *(((volatile uint32_t *)(&(base->CAL_GAR0))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR0))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#else + *(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + base->GCR[0] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultA) | ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + base->GCR[1] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultB) | ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + /* + * $Branch Coverage Justification$ + * while ((base->STAT & ADC_STAT_CAL_RDY_MASK) == ADC_STAT_CAL_RDY_MASK) not covered. Test unfeasible, + * the calibration ready state is too short not to catch. + */ + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpadc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpadc.h new file mode 100644 index 0000000000..5da0019687 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpadc.h @@ -0,0 +1,1529 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPADC_H_ +#define FSL_LPADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpadc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPADC driver version 2.8.4. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) +/*! @} */ + +#if (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1)) +#define ADC_OFSTRIM_OFSTRIM_MAX (ADC_OFSTRIM_OFSTRIM_MASK >> ADC_OFSTRIM_OFSTRIM_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_SIGN ((ADC_OFSTRIM_OFSTRIM_MAX + 1U) >> 1U) + +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2)) +#define ADC_OFSTRIM_OFSTRIM_A_MAX (ADC_OFSTRIM_OFSTRIM_A_MASK >> ADC_OFSTRIM_OFSTRIM_A_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_B_MAX (ADC_OFSTRIM_OFSTRIM_B_MASK >> ADC_OFSTRIM_OFSTRIM_B_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_A_SIGN ((ADC_OFSTRIM_OFSTRIM_A_MAX + 1U) >> 1U) +#define ADC_OFSTRIM_OFSTRIM_B_SIGN ((ADC_OFSTRIM_OFSTRIM_B_MAX + 1U) >> 1U) +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ + +/*! + * @brief Define the MACRO function to get command status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) + +/*! + * @brief Define the MACRO function to get trigger status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) + +/* Map macros to the unified name. */ +#if !defined(ADC_STAT_FOF0_MASK) +#ifdef ADC_STAT_FOF_MASK +#define ADC_STAT_FOF0_MASK ADC_STAT_FOF_MASK +#else +#error "ADC_STAT_FOF0_MASK not defined" +#endif /* ifdef(ADC_STAT_FOF_MASK) */ +#endif /* !defined(ADC_STAT_FOF0_MASK) */ + +#if !defined(ADC_STAT_RDY0_MASK) +#ifdef ADC_STAT_RDY_MASK +#define ADC_STAT_RDY0_MASK ADC_STAT_RDY_MASK +#else +#error "ADC_STAT_RDY0_MASK not defined" +#endif /* ifdef ADC_STAT_RDY_MASK */ +#endif /* !defined(ADC_STAT_RDY0_MASK) */ + +#if !defined(ADC_IE_FOFIE0_MASK) +#ifdef ADC_IE_FOFIE_MASK +#define ADC_IE_FOFIE0_MASK ADC_IE_FOFIE_MASK +#else +#error "ADC_IE_FOFIE0_MASK not defined" +#endif /* ifdef ADC_IE_FOFIE_MASK */ +#endif /* !defined(ADC_IE_FOFIE0_MASK) */ + +#if !defined(ADC_IE_FWMIE0_MASK) +#ifdef ADC_IE_FWMIE_MASK +#define ADC_IE_FWMIE0_MASK ADC_IE_FWMIE_MASK +#else +#error "ADC_IE_FWMIE0_MASK not defined" +#endif /* ifdef ADC_IE_FWMIE_MASK */ +#endif /* !defined(ADC_IE_FWMIE0_MASK) */ + +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result + FIFO 0 than it can hold. */ + kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 0 is greater than the setting watermark level. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result + FIFO 1 than it can hold. */ + kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 1 is greater than the setting watermark level. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) + kLPADC_TriggerExceptionFlag = ADC_STAT_TEXC_INT_MASK, /*!< Indicates that a trigger exception event has occurred. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) + kLPADC_TriggerCompletionFlag = ADC_STAT_TCOMP_INT_MASK, /*!< Indicates that a trigger completion event has occurred. + */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) + kLPADC_CalibrationReadyFlag = ADC_STAT_CAL_RDY_MASK, /*!< Indicates that the calibration process is done. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) + kLPADC_ActiveFlag = ADC_STAT_ADC_ACTIVE_MASK, /*!< Indicates that the ADC is in active state. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) */ + + kLPADC_ResultFIFOOverflowFlag = kLPADC_ResultFIFO0OverflowFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0OverflowFlag as instead. */ + + kLPADC_ResultFIFOReadyFlag = kLPADC_ResultFIFO0ReadyFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0ReadyFlag as instead. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF0 flag is asserted. */ + kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFOOverflowInterruptEnable = kLPADC_ResultFIFO0OverflowInterruptEnable, /*!< To compilitable with old + version, do not recommend using this, + please use + #kLPADC_ResultFIFO0OverflowInterruptEnable + as instead. */ + kLPADC_FIFOWatermarkInterruptEnable = kLPADC_FIFO0WatermarkInterruptEnable, /*!< To compilitable with old version, + do not recommend using this, please + use + #kLPADC_FIFO0WatermarkInterruptEnable + as instead. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF1 flag is asserted. */ + kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY1 flag is asserted. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) + kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception + interrupt. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt + when trigger 0 completion. */ + kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt + when trigger 1 completion. */ + kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt + when trigger 2 completion. */ + kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt + when trigger 3 completion. */ + kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt + when trigger 4 completion. */ + kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt + when trigger 5 completion. */ + kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt + when trigger 6 completion. */ + kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt + when trigger 7 completion. */ + kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt + when trigger 8 completion. */ + kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt + when trigger 9 completion. */ + kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt + when trigger 10 completion. */ + kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt + when trigger 11 completion. */ + kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt + when trigger 12 completion. */ + kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt + when trigger 13 completion. */ + kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt + when trigger 14 completion. */ + kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt + when trigger 15 completion. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ +}; + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) +/*! + * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. + */ +enum _lpadc_trigger_status_flags +{ + kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ + kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ + kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ + kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ + kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ + kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ + kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ + kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ + kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ + kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ + kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ + kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ + kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ + kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ + kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ + kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ + + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ +}; +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) */ + +/*! + * @brief Define enumeration of sample scale mode. + * + * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum + * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the + * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows + * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. + */ +typedef enum _lpadc_sample_scale_mode +{ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. + (For scale select,please refer to the reference manual). */ + kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ +} lpadc_sample_scale_mode_t; + +/*! + * @brief Define enumeration of channel sample mode. + * + * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. + */ +typedef enum _lpadc_sample_channel_mode +{ + kLPADC_SampleChannelSingleEndSideA = 0x0U, /*!< Single-end mode, only A-side channel is converted. */ +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + kLPADC_SampleChannelSingleEndSideB = 0x1U, /*!< Single-end mode, only B-side channel is converted. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + kLPADC_SampleChannelDiffBothSideAB = 0x2U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDiffBothSideBA = 0x3U, /*!< Differential mode, the ADC result is (CHnB-CHnA). */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDualSingleEndBothSide = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side + channels are converted independently. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +} lpadc_sample_channel_mode_t; + +/*! + * @brief Define enumeration of hardware average selection. + * + * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to + * capture temporary results while the averaging iterations are executed. + * + * @note Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH + * register. + */ +typedef enum _lpadc_hardware_average_mode +{ + kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ + kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ +#if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) + kLPADC_HardwareAverageCount256 = 8U, /*!< 256 conversions averaged. */ + kLPADC_HardwareAverageCount512 = 9U, /*!< 512 conversions averaged. */ + kLPADC_HardwareAverageCount1024 = 10U, /*!< 1024 conversions averaged. */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ +} lpadc_hardware_average_mode_t; + +/*! + * @brief Define enumeration of sample time selection. + * + * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher + * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption + * when command looping and sequencing is configured and high conversion rates are not required. + */ +typedef enum _lpadc_sample_time_mode +{ + kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ +} lpadc_sample_time_mode_t; + +/*! + * @brief Define enumeration of hardware compare mode. + * + * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting + * guides operation of the automatic compare function to optionally only store when the compare operation is true. + * When compare is enabled, the conversion result is compared to the compare values. + */ +typedef enum _lpadc_hardware_compare_mode +{ + kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ + kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ + kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ +} lpadc_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE +/*! + * @brief Define enumeration of conversion resolution mode. + * + * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to + * #lpadc_sample_channel_mode_t + */ +typedef enum _lpadc_conversion_resolution_mode +{ + kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential + 13-bit conversion with 2's complement output. */ + kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit + conversion with 2's complement output. */ +} lpadc_conversion_resolution_mode_t; +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS +/*! + * @brief Define enumeration of conversion averages mode. + * + * Configure the converion average number for auto-calibration. + * @note Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL + * register. + */ +typedef enum _lpadc_conversion_average_mode +{ + kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ + kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ +#if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) + kLPADC_ConversionAverage256 = 8U, /*!< 256 conversions averaged. */ + kLPADC_ConversionAverage512 = 9U, /*!< 512 conversions averaged. */ + kLPADC_ConversionAverage1024 = 10U, /*!< 1024 conversions averaged. */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ +} lpadc_conversion_average_mode_t; +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/*! + * @brief Define enumeration of reference voltage source. + * + * For detail information, need to check the SoC's specification. + */ +typedef enum _lpadc_reference_voltage_mode +{ + kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ + kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ + kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ +} lpadc_reference_voltage_source_t; + +/*! + * @brief Define enumeration of power configuration. + * + * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be + * possible. Refer to the device data sheet for power and performance capabilities for each setting. + */ +typedef enum _lpadc_power_level_mode +{ + kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ + kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ + kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ + kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ +} lpadc_power_level_mode_t; + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) +/*! + * @brief Define enumeration of offset calibration mode. + * + */ +typedef enum _lpadc_offset_calibration_mode +{ + kLPADC_OffsetCalibration12bitMode = 0U, /*!< 12 bit offset calibration mode. */ + kLPADC_OffsetCalibration16bitMode = 1U, /*!< 16 bit offset calibration mode. */ +} lpadc_offset_calibration_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + +/*! + * @brief Define enumeration of trigger priority policy. + * + * This selection controls how higher priority triggers are handled. + * @note \b kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of + * TPRICTRL field in CFG register. + */ +typedef enum _lpadc_trigger_priority_policy +{ + kLPADC_ConvPreemptImmediatelyNotAutoResumed = 0x0U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion is not + automatically resumed or restarted. */ + kLPADC_ConvPreemptSoftlyNotAutoResumed = 0x1U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion is not + resumed or restarted. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptImmediatelyAutoRestarted = 0x4U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be restarted. */ + kLPADC_ConvPreemptSoftlyAutoRestarted = 0x5U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + automatically be restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptImmediatelyAutoResumed = 0xCU, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be resumed. */ + kLPADC_ConvPreemptSoftlyAutoResumed = 0xDU, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + be automatically be resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptImmediately = + kLPADC_ConvPreemptImmediatelyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ + kLPADC_TriggerPriorityPreemptSoftly = + kLPADC_ConvPreemptSoftlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures compatibility + with older versions. */ + +#if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) + kLPADC_ConvPreemptSubsequentlyNotAutoResumed = 0x2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + not automatically be restarted or resumed. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptSubsequentlyAutoRestarted = 0x6U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptSubsequentlyAutoResumed = 0xEU, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptSubsequently = + kLPADC_ConvPreemptSubsequentlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI + kLPADC_TriggerPriorityExceptionDisabled = 0x10U, /*!< High priority trigger exception disabled. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ +} lpadc_trigger_priority_policy_t; + +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Define enumeration of tune value. + */ +typedef enum _lpadc_tune_value +{ + kLPADC_TuneValue0 = 0U, /*!< Tune value 0. */ + kLPADC_TuneValue1 = 1U, /*!< Tune value 1. */ + kLPADC_TuneValue2 = 2U, /*!< Tune value 2. */ + kLPADC_TuneValue3 = 3U, /*!< Tune value 3. */ +} lpadc_tune_value_t; +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + +/*! + * @brief LPADC global configuration. + * + * This structure would used to keep the settings for initialization. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". + If voltage reference option1 input is above 1.8V, it should be "false". */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When + enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the + ADC will wait for the current averaging iteration/FIFO storage to complete before + acknowledging stop or wait mode entry. */ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without + startup delays(at the cost of higher DC current consumption). */ + uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered + while the ADC is active and there is a counted delay defined by this field after an + initial trigger transitions the ADC from its Idle state to allow time for the analog + circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must + result in a longer delay than the analog startup time. */ + lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for + conversions.*/ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to + lpadc_trigger_priority_policy_t. */ + bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during + command execution sequencing between LOOP iterations, between commands in a sequence, and + between conversions when command is executing in "Compare Until True" configuration. */ + uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay + is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing + function is enabled. The available value range is in 9-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* for FIFO0. */ + uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ + /* for FIFO1. */ + uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ +#else + /* for FIFO. */ + uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored + in the ADC Result FIFO is greater than the value in this field, the ready flag would be + asserted to indicate stored data has reached the programmable threshold. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) + +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +} lpadc_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion command. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + lpadc_sample_scale_mode_t channelBScaleMode; /*!< Alternate channe B Scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ + uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */ +#endif + uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. + 1-15 is available, 0 is to terminate the chain after this command. */ + bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number + of times the selected channel is converted consecutively; when enabled, the + "loopCount" field defines how many consecutive channels are converted as part + of the command execution. */ + uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next + command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ + lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ + lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ + + lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ + uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ + uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be + automatically executed; when enabled, the active trigger must be asserted again before + executing this command. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + bool enableChannelB; /*! Enable alternate Channel B */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ +} lpadc_conv_command_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion trigger. + */ +typedef struct +{ + uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated + trigger event. */ + uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. + When this field is clear, then no delay is incurred. When this field is set to a non-zero + value, the duration for the delay is 2^delayPower ADCK cycles. The available value range + is 4-bit. */ + uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same + priority level setting, the lower order trigger event has the higher priority. The lower + value for this field is for the higher priority, the available value range is 1-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ + uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the + input trigger source or not. THe software trigger is always available. */ +} lpadc_conv_trigger_config_t; + +/*! + * @brief Define the structure to keep the conversion result. + */ +typedef struct +{ + uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ + uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ + uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ + uint16_t convValue; /*!< Data result. */ +} lpadc_conv_result_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * @brief A structure of calibration value. + */ +typedef struct _lpadc_calibration_value +{ + /* gain calibration result. */ + uint16_t gainCalibrationResultA; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + uint16_t gainCalibrationResultB; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + /* general calibration value. */ + uint16_t generalCalibrationValueA[33U]; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + uint16_t generalCalibrationValueB[33U]; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +} lpadc_calibration_value_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization & de-initialization. + * @{ + */ + +/*! + * @brief Initializes the LPADC module. + * + * @param base LPADC peripheral base address. + * @param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->enableInDozeMode = true; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFOWatermark = 0U; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config); + +/*! + * @brief De-initializes the LPADC module. + * + * @param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base); + +/*! + * @brief Switch on/off the LPADC module. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the module. + */ +static inline void LPADC_Enable(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_ADCEN_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_ADCEN_MASK; + } +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Do reset the conversion FIFO0. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO0(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; +} + +/*! + * @brief Do reset the conversion FIFO1. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO1(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; +} +#else + +#if defined(ADC_CTRL_RSTFIFO0_MASK) +#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK +#endif /* defined(ADC_CTRL_RSTFIFO0_MASK) */ +/*! + * @brief Do reset the conversion FIFO. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO_MASK; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Do reset the module's configuration. + * + * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetConfig(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RST_MASK; + base->CTRL &= ~ADC_CTRL_RST_MASK; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get status flags. + * + * @param base LPADC peripheral base address. + * @return status flags' mask. See to #_lpadc_status_flags. + */ +static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clear status flags. + * + * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. + */ +static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high + * priority trigger exception. + * + * @param base LPADC peripheral base address. + * @return The OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) +{ + return base->TSTAT; +} + +/*! + * @brief Clear trigger status flags. + * + * @param base LPADC peripheral base address. + * @param mask The mask of trigger status flags to be cleared, should be the + * OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) +{ + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert(((mask & 0xFFFFU) == (mask & ADC_TSTAT_TEXC_NUM_MASK)) && + ((mask & 0xFFFF0000U) == (mask & ADC_TSTAT_TCOMP_FLAG_MASK))); + base->TSTAT = mask; +} +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) */ + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ + base->IE |= mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ + base->IE &= ~mask; +} + +/*! + * @name DMA Control + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Switch on/off the DMA trigger for FIFO0 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE0_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE0_MASK; + } +} + +/*! + * @brief Switch on/off the DMA trigger for FIFO1 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE1_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE1_MASK; + } +} +#else +#if defined(ADC_DE_FWMDE0_MASK) +#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK +#endif /* defined(ADC_DE_FWMDE0_MASK) */ +/*! + * @brief Switch on/off the DMA trigger for FIFO watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE_MASK; + } +} +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ +/* @} */ + +/*! + * @name Trigger and conversion with FIFO. + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Get the count of result kept in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param index Result FIFO index. + * @return The count of result kept in conversion FIFOn. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. + * + * @return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); + +/*! + * @brief Get the result in conversion FIFOn using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ +/*! + * @brief Get the count of result kept in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @return The count of result kept in conversion FIFO. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * @return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); + +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ + +/*! + * @brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * @code + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); + +/*! + * @brief Do software trigger to conversion command. + * + * @param base LPADC peripheral base address. + * @param triggerIdMask Mask value for software trigger indexes, which count from zero. + */ +static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) +{ + /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ + base->SWTRIG = triggerIdMask; +} + +#if defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL +/*! + * @brief Enable hardware trigger command selection. + * + * This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined + * by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL]. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param enable True to enable or flase to disable. + */ +static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable) +{ + if (enable) + { + base->TCTRL[triggerId] |= ADC_TCTRL_CMD_SEL_MASK; + } + else + { + base->TCTRL[triggerId] &= ~ADC_TCTRL_CMD_SEL_MASK; + } +} +#endif /* defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/ + +/*! + * @brief Configure conversion command. + + * @note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. + * + * @param base LPADC peripheral base address. + * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * @code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelBScaleMode = kLPADC_SampleFullScale; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * config->enableChannelB = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * @brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable); +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * To minimize the offset during normal operation, software should read the conversion result from + * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. + * + * @param base LPADC peripheral base address. + * @param value Setting offset value. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) +{ + base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; +} + +/*! + * @brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +#if defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1U) +/*! + * @brief Set trim value for offset. + * + * @note For 16-bit conversions, each increment is 1/2 LSB resulting in a programmable offset range of -256 LSB to 255.5 + * LSB; For 12-bit conversions, each increment is 1/32 LSB resulting in a programmable offset range of -16 LSB to + * 15.96875 LSB. + * + * @param base LPADC peripheral base address. + * @param value Offset trim value, is a 10-bit signed value between -512 and 511. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM(value); +} + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValue Pointer to the variable in type of int16_t to store offset value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue) +{ + assert(pValue != NULL); + + uint16_t ofstrim = (uint16_t)((base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_MASK)) >> ADC_OFSTRIM_OFSTRIM_SHIFT); + + if ((ofstrim & ADC_OFSTRIM_OFSTRIM_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrim |= (uint16_t)(~ADC_OFSTRIM_OFSTRIM_MAX); + } + + *pValue = (int16_t)ofstrim; +} +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2U)) +/*! + * @brief Set proper offset value to trim ADC. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, int32_t valueA, int32_t valueB) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); +} + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValueA Pointer to the variable in type of int32_t to store offset A value. + * @param pValueB Pointer to the variable in type of int32_t to store offset B value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int32_t *pValueA, int32_t *pValueB) +{ + assert(pValueA != NULL); + assert(pValueB != NULL); + + uint32_t ofstrimA = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_A_MASK)) >> ADC_OFSTRIM_OFSTRIM_A_SHIFT; + uint32_t ofstrimB = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_B_MASK)) >> ADC_OFSTRIM_OFSTRIM_B_SHIFT; + + if ((ofstrimA & ADC_OFSTRIM_OFSTRIM_A_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimA |= (~ADC_OFSTRIM_OFSTRIM_A_MAX); + } + if ((ofstrimB & ADC_OFSTRIM_OFSTRIM_B_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimB |= (~ADC_OFSTRIM_OFSTRIM_B_MAX); + } + + *pValueA = (int32_t)ofstrimA; + *pValueB = (int32_t)ofstrimB; +} +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ +#else /* !(defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM) */ +/*! + * @brief Set proper offset value to trim 12 bit ADC conversion. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffset12BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM12 = ADC_OFSTRIM12_OFSTRIM_A(valueA) | ADC_OFSTRIM12_OFSTRIM_A(valueB); +} + +/*! + * @brief Set proper offset value to trim 16 bit ADC conversion. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffset16BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM16 = ADC_OFSTRIM16_OFSTRIM_A(valueA) | ADC_OFSTRIM16_OFSTRIM_B(valueB); +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ + +/*! + * @brief Enable the offset calibration function. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_CALOFS_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_CALOFS_MASK; + } +} +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE +/*! + * @brief Set offset calibration mode. + * + * @param base LPADC peripheral base address. + * @param mode set offset calibration mode.see to #lpadc_offset_calibration_mode_t . + */ +static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode) +{ + base->CTRL = (base->CTRL & ~ADC_CTRL_CALOFSMODE_MASK) | ADC_CTRL_CALOFSMODE(mode); +} + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + +/*! + * @brief Do offset calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * @brief Do auto calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); + +/*! + * @brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. + * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. + * + * @param base LPADC peripheral base address. + */ +void LPADC_PrepareAutoCalibration(ADC_Type *base); + +/*! + * @brief Finish auto calibration start with LPADC_PrepareAutoCalibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_FinishAutoCalibration(ADC_Type *base); + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * @brief Get calibration value into the memory which is defined by invoker. + * + * @note Please note the ADC will be disabled temporary. + * @note This function should be used after finish calibration. + * + * @param base LPADC peripheral base address. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure, this memory block should be always + * powered on even in low power modes. + */ +void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue); + +/*! + * @brief Set calibration value into ADC calibration registers. + * + * @note Please note the ADC will be disabled temporary. + * + * @param base LPADC peripheral base address. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure which contains ADC's calibration + * value. + */ +void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue); + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Request high speed mode trim calculation. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_RequestHighSpeedModeTrim(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_CALHS_MASK; +} + +/*! + * @brief Get high speed mode trim value, the result is a 5-bit signed value between -16 and 15. + * + * @note The high speed mode trim value is used to minimize offset for high speed conversion. + * + * @param base LPADC peripheral base address. + * @return The calculated high speed mode trim value. + */ +static inline int8_t LPADC_GetHighSpeedTrimValue(ADC_Type *base) +{ + return (int8_t)(base->HSTRIM); +} + +/*! + * @brief Set high speed mode trim value. + * + * @note If is possible to set the trim value manually, but it is recommended to use the LPADC_RequestHighSpeedModeTrim. + * + * @param base LPADC peripheral base address. + * @param trimValue The trim value to be set. + */ +static inline void LPADC_SetHighSpeedTrimValue(ADC_Type *base, int8_t trimValue) +{ + base->HSTRIM = ADC_HSTRIM_HSTRIM(trimValue); +} + +/*! + * @brief Enable/disable high speed conversion mode, if enabled conversions complete 2 or 3 ADCK cycles sooner compared + * to conversion cycle counts when high speed mode is disabled. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable high speed conversion mode: + * - \b true Enable high speed conversion mode; + * - \b false Disable high speed conversion mode. + */ +static inline void LPADC_EnableHighSpeedConversionMode(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HS_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HS_MASK; + } +} + +/*! + * @brief Enable/disable an additional ADCK cycle to conversion. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable an additional ADCK cycle to conversion: + * - \b true Enable an additional ADCK cycle to conversion; + * - \b false Disable an additional ADCK cycle to conversion. + */ +static inline void LPADC_EnableExtraCycle(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HSEXTRA_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HSEXTRA_MASK; + } +} + +/*! + * @brief Set tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @param tuneValue The tune value to be set, please refer to @ref lpadc_tune_value_t. + */ +static inline void LPADC_SetTuneValue(ADC_Type *base, lpadc_tune_value_t tuneValue) +{ + base->CFG2 = (base->CFG2 & ~ADC_CFG2_TUNE_MASK) | ADC_CFG2_TUNE(tuneValue); +} + +/*! + * @brief Get tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @return The tune value, please refer to @ref lpadc_tune_value_t. + */ +static inline lpadc_tune_value_t LPADC_GetTuneValue(ADC_Type *base) +{ + return (lpadc_tune_value_t)((base->CFG2 & ADC_CFG2_TUNE_MASK) >> ADC_CFG2_TUNE_SHIFT); +} +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) +/*! + * @brief Enable/disable left-justify format in 12-bit single-end mode. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable left-justify format in 12-bit single-end mode: + * - \b true Enable left-justify format in 12-bit single-end mode; + * - \b false Disable left-justify format in 12-bit single-end mode. + */ +static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_JLEFT_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_JLEFT_MASK; + } +} +#endif /* (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* FSL_LPADC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpcmp.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpcmp.c new file mode 100644 index 0000000000..23b2da790e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpcmp.c @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpcmp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpcmp" +#endif + +#if defined(LPCMP_RSTS) +#define LPCMP_RESETS_ARRAY LPCMP_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(LPCMP_CLOCKS) +/*! + * @brief Get instance number for LPCMP module. + * + * @param base LPCMP peripheral base address + */ +static uint32_t LPCMP_GetInstance(LPCMP_Type *base); +#endif /* LPCMP_CLOCKS */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(LPCMP_CLOCKS) +/*! @brief Pointers to LPCMP bases for each instance. */ +static LPCMP_Type *const s_lpcmpBases[] = LPCMP_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPCMP clocks for each instance. */ +static const clock_ip_name_t s_lpcmpClocks[] = LPCMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPCMP_CLOCKS */ + +#if defined(LPCMP_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpcmpResets[] = LPCMP_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Codes + ******************************************************************************/ +#if defined(LPCMP_CLOCKS) +static uint32_t LPCMP_GetInstance(LPCMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpcmpBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_lpcmpBases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_lpcmpBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (s_lpcmpBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpcmpBases)); + + return instance; +} +#endif /* LPCMP_CLOCKS */ + +/*! + * brief Initialize the LPCMP + * + * This function initializes the LPCMP module. The operations included are: + * - Enabling the clock for LPCMP module. + * - Configuring the comparator. + * - Enabling the LPCMP module. + * Note: For some devices, multiple LPCMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the LPCMPs. Check the chip reference manual for the clock assignment of the LPCMP. + * + * param base LPCMP peripheral base address. + * param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + +#if defined(LPCMP_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_lpcmpClocks[LPCMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPCMP_CLOCKS */ + +#if defined(LPCMP_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpcmpResets[LPCMP_GetInstance(base)]); +#endif + + /* Configure. */ + LPCMP_Enable(base, false); + +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + /* CCR0 register. */ + if (config->enableStopMode) + { + base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK; + } + else + { + base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; + } +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + + /* CCR1 register. */ + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + | LPCMP_CCR1_FUNC_CLK_SEL_MASK +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + ))); + + if (config->enableOutputPin) + { + tmp32 |= LPCMP_CCR1_COUT_PEN_MASK; + } + if (config->useUnfilteredOutput) + { + tmp32 |= LPCMP_CCR1_COUT_SEL_MASK; + } + if (config->enableInvertOutput) + { + tmp32 |= LPCMP_CCR1_COUT_INV_MASK; + } +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + tmp32 |= LPCMP_CCR1_FUNC_CLK_SEL(config->functionalSourceClock); +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + base->CCR1 = tmp32; + /* CCR2 register. */ + tmp32 = base->CCR2 & ~(LPCMP_CCR2_HYSTCTR_MASK | LPCMP_CCR2_CMP_NPMD_MASK | LPCMP_CCR2_CMP_HPMD_MASK); + tmp32 |= LPCMP_CCR2_HYSTCTR(config->hysteresisMode); + tmp32 |= ((uint32_t)(config->powerMode) << LPCMP_CCR2_CMP_HPMD_SHIFT); + base->CCR2 = tmp32; + + LPCMP_Enable(base, true); /* Enable the LPCMP module. */ +} + +/*! + * brief De-initializes the LPCMP module. + * + * This function de-initializes the LPCMP module. The operations included are: + * - Disabling the LPCMP module. + * - Disabling the clock for LPCMP module. + * + * This function disables the clock for the LPCMP. + * Note: For some devices, multiple LPCMP instance shares the same clock gate. In this case, before disabling the + * clock for the LPCMP, ensure that all the LPCMP instances are not used. + * + * param base LPCMP peripheral base address. + */ +void LPCMP_Deinit(LPCMP_Type *base) +{ + /* Disable the LPCMP module. */ + LPCMP_Enable(base, false); +#if defined(LPCMP_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_lpcmpClocks[LPCMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPCMP_CLOCKS */ +} + +/*! + * brief Gets an available pre-defined settings for the comparator's configuration. + * + * This function initializes the comparator configuration structure to these default values: + * code + * config->enableStopMode = false; + * config->enableOutputPin = false; + * config->useUnfilteredOutput = false; + * config->enableInvertOutput = false; + * config->hysteresisMode = kLPCMP_HysteresisLevel0; + * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; + * endcode + * param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_GetDefaultConfig(lpcmp_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + config->enableStopMode = false; +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + config->enableOutputPin = false; + config->useUnfilteredOutput = false; + config->enableInvertOutput = false; + config->hysteresisMode = kLPCMP_HysteresisLevel0; + config->powerMode = kLPCMP_LowSpeedPowerMode; +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + config->functionalSourceClock = kLPCMP_FunctionalClockSource0; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ +} + +/*! + * brief Select the input channels for LPCMP. This function determines which input + * is selected for the negative and positive mux. + * + * param base LPCMP peripheral base address. + * param positiveChannel Positive side input channel number. + * param negativeChannel Negative side input channel number. + */ +void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel) +{ + uint32_t tmp32; + + tmp32 = base->CCR2 & ~(LPCMP_CCR2_PSEL_MASK | LPCMP_CCR2_MSEL_MASK); + tmp32 |= LPCMP_CCR2_PSEL(positiveChannel) | LPCMP_CCR2_MSEL(negativeChannel); + base->CCR2 = tmp32; +} + +/*! + * brief Configures the filter. + * + * param base LPCMP peripheral base address. + * param config Pointer to "lpcmp_filter_config_t" structure. + */ +void LPCMP_SetFilterConfig(LPCMP_Type *base, const lpcmp_filter_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + + tmp32 = base->CCR1 & ~(LPCMP_CCR1_FILT_PER_MASK | LPCMP_CCR1_FILT_CNT_MASK | LPCMP_CCR1_SAMPLE_EN_MASK); + if (config->enableSample) + { + tmp32 |= LPCMP_CCR1_SAMPLE_EN_MASK; + } + tmp32 |= LPCMP_CCR1_FILT_PER(config->filterSamplePeriod) | LPCMP_CCR1_FILT_CNT(config->filterSampleCount); + base->CCR1 = tmp32; +} + +/*! + * brief Configure the internal DAC module. + * + * param base LPCMP peripheral base address. + * param config Pointer to "lpcmp_dac_config_t" structure. If config is "NULL", disable internal DAC. + */ +void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config) +{ + uint32_t tmp32; + if (config == NULL) + { + tmp32 = 0U; /* Disable internal DAC. */ + } + else + { + tmp32 = LPCMP_DCR_VRSEL(config->referenceVoltageSource) | LPCMP_DCR_DAC_DATA(config->DACValue); + if (config->enableLowPowerMode) + { + tmp32 |= LPCMP_DCR_DAC_HPMD_MASK; + } + tmp32 |= LPCMP_DCR_DAC_EN_MASK; + } + base->DCR = tmp32; +} + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUTA_CFG_MASK | LPCMP_CCR1_EVT_SEL_CFG_MASK | LPCMP_CCR1_WINDOW_INV_MASK))); + + if (config->enableInvertWindowSignal) + { + tmp32 |= LPCMP_CCR1_WINDOW_INV_MASK; + } + + /* Set COUT event, which can close the active window in window mode. */ + tmp32 |= LPCMP_CCR1_EVT_SEL_CFG(config->closeWindowEvent); + + /* Set the COUTA signal value when the window is closed. */ + tmp32 |= LPCMP_CCR1_COUTA_CFG(config->COUTASignal); + + base->CCR1 = tmp32; +} +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + /* LPCMPx_RRCR0 register, Configuration options for the round-robin operation. */ + tmp32 = (base->RRCR0 & + (~(LPCMP_RRCR0_RR_TRG_SEL_MASK | LPCMP_RRCR0_RR_NSAM_MASK | LPCMP_RRCR0_RR_CLK_SEL_MASK | + LPCMP_RRCR0_RR_INITMOD_MASK | LPCMP_RRCR0_RR_SAMPLE_CNT_MASK | LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK))); + + tmp32 |= + (LPCMP_RRCR0_RR_TRG_SEL(config->roundrobinTriggerSource) | LPCMP_RRCR0_RR_NSAM(config->sampleClockNumbers) | + LPCMP_RRCR0_RR_CLK_SEL(config->roundrobinClockSource) | LPCMP_RRCR0_RR_INITMOD(config->initDelayModules) | + LPCMP_RRCR0_RR_SAMPLE_CNT(config->channelSampleNumbers) | + LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(config->sampleTimeThreshhold)); + + base->RRCR0 = tmp32; + + /* LPCMPx_RRCR1 register, Configure the fix port, fix channel and checker channel. */ + tmp32 = + (base->RRCR1 & (~(LPCMP_RRCR1_FIXP_MASK | LPCMP_RRCR1_FIXCH_MASK | (0xFFUL << LPCMP_RRCR1_RR_CH0EN_SHIFT)))); + tmp32 |= (LPCMP_RRCR1_FIXP(config->fixedMuxPort) | LPCMP_RRCR1_FIXCH(config->fixedChannel) | + ((uint32_t)(config->checkerChannelMask) << LPCMP_RRCR1_RR_CH0EN_SHIFT)); + + base->RRCR1 = tmp32; +} + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value) +{ + uint32_t tmp32 = 0UL; + + tmp32 = (base->RRCR2 & (~LPCMP_RRCR2_RR_TIMER_RELOAD_MASK)); + tmp32 |= LPCMP_RRCR2_RR_TIMER_RELOAD(value); + + base->RRCR2 = tmp32; +} + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpcmp.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpcmp.h new file mode 100644 index 0000000000..737738acd4 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpcmp.h @@ -0,0 +1,585 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPCMP_H_ +#define FSL_LPCMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpcmp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPCMP driver version 2.1.2. */ +#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @} */ + +#define LPCMP_CCR1_COUTA_CFG_MASK (LPCMP_CCR1_COUTA_OWEN_MASK | LPCMP_CCR1_COUTA_OW_MASK) +#define LPCMP_CCR1_COUTA_CFG_SHIFT LPCMP_CCR1_COUTA_OWEN_SHIFT +#define LPCMP_CCR1_COUTA_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_CFG_SHIFT)) & LPCMP_CCR1_COUTA_CFG_MASK) + +#define LPCMP_CCR1_EVT_SEL_CFG_MASK (LPCMP_CCR1_EVT_SEL_MASK | LPCMP_CCR1_WINDOW_CLS_MASK) +#define LPCMP_CCR1_EVT_SEL_CFG_SHIFT LPCMP_CCR1_WINDOW_CLS_SHIFT +#define LPCMP_CCR1_EVT_SEL_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_CFG_SHIFT)) & LPCMP_CCR1_EVT_SEL_CFG_MASK) + +/*! + * @brief LPCMP status falgs mask. + */ +enum _lpcmp_status_flags +{ + kLPCMP_OutputRisingEventFlag = LPCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CSR_RRF) && FSL_FEATURE_LPCMP_HAS_CSR_RRF + kLPCMP_OutputRoundRobinEventFlag = LPCMP_CSR_RRF_MASK, /*!< Detects when any channel's last comparison result is + different from the pre-set value in trigger mode. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CSR_RRF */ + kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. + The flag does not support W1C. */ +}; + +/*! + * @brief LPCMP interrupt enable/disable mask. + */ +enum _lpcmp_interrupt_enable +{ + kLPCMP_OutputRisingInterruptEnable = LPCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */ + kLPCMP_OutputFallingInterruptEnable = LPCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */ +#if defined(FSL_FEATURE_LPCMP_HAS_IER_RRF_IE) && FSL_FEATURE_LPCMP_HAS_IER_RRF_IE + kLPCMP_RoundRobinInterruptEnable = LPCMP_IER_RRF_IE_MASK, /*!< Comparator round robin mode interrupt + occurred when the comparison result changes for a given channel. */ +#endif /* FSL_FEATURE_LPCMP_HAS_IER_RRF_IE */ +}; + +/*! + * @brief LPCMP hysteresis mode. See chip data sheet to get the actual hystersis + * value with each level + */ +typedef enum _lpcmp_hysteresis_mode +{ + kLPCMP_HysteresisLevel0 = 0U, /*!< The hard block output has level 0 hysteresis internally. */ + kLPCMP_HysteresisLevel1 = 1U, /*!< The hard block output has level 1 hysteresis internally. */ + kLPCMP_HysteresisLevel2 = 2U, /*!< The hard block output has level 2 hysteresis internally. */ + kLPCMP_HysteresisLevel3 = 3U, /*!< The hard block output has level 3 hysteresis internally. */ +} lpcmp_hysteresis_mode_t; + +/*! + * @brief LPCMP nano mode. + */ +typedef enum _lpcmp_power_mode +{ + kLPCMP_LowSpeedPowerMode = 0U, /*!< Low speed comparison mode is selected. */ + kLPCMP_HighSpeedPowerMode = 1U, /*!< High speed comparison mode is selected. */ + kLPCMP_NanoPowerMode = 2U, /*!< Nano power comparator is enabled. */ +} lpcmp_power_mode_t; + +/*! + * @brief Internal DAC reference voltage source. + */ +typedef enum _lpcmp_dac_reference_voltage_source +{ + kLPCMP_VrefSourceVin1 = 0U, /*!< vrefh_int is selected as resistor ladder network supply reference Vin. */ + kLPCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */ +} lpcmp_dac_reference_voltage_source_t; + +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL +/*! + * @brief LPCMP functional mode clock source selection. + * + * Note: In different devices, the functional mode clock source selection is different, + * please refer to specific device Reference Manual for details. + */ +typedef enum _lpcmp_functional_source_clock +{ + kLPCMP_FunctionalClockSource0 = 0U, /*!< Select functional mode clock source0. */ + kLPCMP_FunctionalClockSource1 = 1U, /*!< Select functional mode clock source1. */ + kLPCMP_FunctionalClockSource2 = 2U, /*!< Select functional mode clock source2. */ + kLPCMP_FunctionalClockSource3 = 3U, /*!< Select functional mode clock source3. */ +} lpcmp_functional_source_clock_t; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Set the COUTA signal value when the window is closed. + */ +typedef enum _lpcmp_couta_signal +{ + kLPCMP_COUTASignalNoSet = 0U, /*!< NO set the COUTA signal value when the window is closed. */ + kLPCMP_COUTASignalLow = 1U, /*!< Set COUTA signal low(0) when the window is closed. */ + kLPCMP_COUTASignalHigh = 3U, /*!< Set COUTA signal high(1) when the window is closed. */ +} lpcmp_couta_signal_t; + +/*! + * @brief Set COUT event, which can close the active window in window mode. + */ +typedef enum _lpcmp_close_window_event +{ + kLPCMP_CLoseWindowEventNoSet = 0U, /*!< No Set COUT event, which can close the active window in window mode. */ + kLPCMP_CloseWindowEventRisingEdge = 1U, /*!< Set rising edge COUT signal as COUT event. */ + kLPCMP_CloseWindowEventFallingEdge = 3U, /*!< Set falling edge COUT signal as COUT event. */ + kLPCMP_CLoseWindowEventBothEdge = 5U, /*!< Set both rising and falling edge COUT signal as COUT event. */ +} lpcmp_close_window_event_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief LPCMP round robin mode fixed mux port. + */ +typedef enum _lpcmp_roundrobin_fixedmuxport +{ + kLPCMP_FixedPlusMuxPort = 0U, /*!< Fixed plus mux port. */ + kLPCMP_FixedMinusMuxPort = 1U, /*!< Fixed minus mux port. */ +} lpcmp_roundrobin_fixedmuxport_t; + +/*! + * @brief LPCMP round robin mode clock source selection. + * + * Note: In different devices,the round robin mode clock source selection is different, + * please refer to the specific device Reference Manual for details. + */ +typedef enum _lpcmp_roundrobin_clock_source +{ + kLPCMP_RoundRobinClockSource0 = 0U, /*!< Select roundrobin mode clock source0. */ + kLPCMP_RoundRobinClockSource1 = 1U, /*!< Select roundrobin mode clock source1. */ + kLPCMP_RoundRobinClockSource2 = 2U, /*!< Select roundrobin mode clock source2. */ + kLPCMP_RoundRobinClockSource3 = 3U, /*!< Select roundrobin mode clock source3. */ +} lpcmp_roundrobin_clock_source_t; + +/*! + * @brief LPCMP round robin mode trigger source. + */ +typedef enum _lpcmp_roundrobin_trigger_source +{ + kLPCMP_TriggerSourceExternally = 0U, /*!< Select external trigger source. */ + kLPCMP_TriggerSourceInternally = 1U, /*!< Select internal trigger source. */ +} lpcmp_roundrobin_trigger_source_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +/*! + * @brief Configure the filter. + */ +typedef struct _lpcmp_filter_config +{ + bool enableSample; /*!< Decide whether to use the external SAMPLE as a sampling clock input. */ + uint8_t filterSampleCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */ + uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The + sampling clock must be at least 4 times slower than the system clock to the comparator. + So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ +} lpcmp_filter_config_t; + +/*! + * @brief configure the internal DAC. + */ +typedef struct _lpcmp_dac_config +{ + bool enableLowPowerMode; /*!< Decide whether to enable DAC low power mode. */ + lpcmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Different devices has different available range, + for specific values, please refer to the reference manual.*/ +} lpcmp_dac_config_t; + +/*! + * @brief Configures the comparator. + */ +typedef struct _lpcmp_config +{ +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + + bool enableOutputPin; /*!< Decide whether to enable the comparator is available in selected pin. */ + bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */ + bool enableInvertOutput; /*!< Decide whether to inverts the comparator output. */ + lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */ + lpcmp_power_mode_t powerMode; /*!< LPCMP power mode. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + lpcmp_functional_source_clock_t functionalSourceClock; /*!< Select LPCMP functional mode clock source. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ +} lpcmp_config_t; + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window mode control. + */ +typedef struct _lpcmp_window_control_config +{ + bool enableInvertWindowSignal; /*!< True: enable invert window signal, False: disable invert window signal. */ + lpcmp_couta_signal_t COUTASignal; /*!< Decide whether to define the COUTA signal value when the window is closed. */ + lpcmp_close_window_event_t closeWindowEvent; /*!< Decide whether to select COUT event signal edge defines + a COUT event to close window. */ +} lpcmp_window_control_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the round robin mode. + */ +typedef struct _lpcmp_roundrobin_config +{ + uint8_t initDelayModules; /*!< Comparator and DAC initialization delay modulus, See Reference Manual and DataSheet + for specific value. */ + uint8_t sampleClockNumbers; /*!< Specify the number of the round robin clock cycles(0~3) to wait after scanning the + active channel before sampling the channel's comparison result. */ + uint8_t channelSampleNumbers; /*!< Specify the number of samples for one channel, note that channelSampleNumbers + must not smaller than sampleTimeThreshhold. */ + uint8_t sampleTimeThreshhold; /*!< Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are + "1",the final result is "1", otherwise the final result is "0", note that the + sampleTimeThreshhold must not be larger than channelSampleNumbers. */ + lpcmp_roundrobin_clock_source_t roundrobinClockSource; /*!< Decide which clock source to + choose in round robin mode. */ + lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource; /*!< Decide which trigger source to + choose in round robin mode. */ + lpcmp_roundrobin_fixedmuxport_t fixedMuxPort; /*!< Decide which mux port to choose as + fixed channel in round robin mode. */ + uint8_t fixedChannel; /*!< Indicate which channel of the fixed mux port is used in round robin mode. */ + uint8_t checkerChannelMask; /*!< Indicate which channel of the non-fixed mux port to check its voltage value in + round robin mode, for example, if checkerChannelMask set to 0x11U means select + channel 0 and channel 4 as checker channel.*/ +} lpcmp_roundrobin_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and configuration + * @{ + */ + +/*! + * @brief Initialize the LPCMP + * + * This function initializes the LPCMP module. The operations included are: + * - Enabling the clock for LPCMP module. + * - Configuring the comparator. + * - Enabling the LPCMP module. + * Note: For some devices, multiple LPCMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the LPCMPs. Check the chip reference manual for the clock assignment of the LPCMP. + * + * @param base LPCMP peripheral base address. + * @param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config); + +/*! + * @brief De-initializes the LPCMP module. + * + * This function de-initializes the LPCMP module. The operations included are: + * - Disabling the LPCMP module. + * - Disabling the clock for LPCMP module. + * + * This function disables the clock for the LPCMP. + * Note: For some devices, multiple LPCMP instance shares the same clock gate. In this case, before disabling the + * clock for the LPCMP, ensure that all the LPCMP instances are not used. + * + * @param base LPCMP peripheral base address. + */ +void LPCMP_Deinit(LPCMP_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the comparator's configuration. + * + * This function initializes the comparator configuration structure to these default values: + * @code + * config->enableStopMode = false; + * config->enableOutputPin = false; + * config->useUnfilteredOutput = false; + * config->enableInvertOutput = false; + * config->hysteresisMode = kLPCMP_HysteresisLevel0; + * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; + * @endcode + * @param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_GetDefaultConfig(lpcmp_config_t *config); + +/*! + * @brief Enable/Disable LPCMP module. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable the module, and "false" means disable the module. + */ +static inline void LPCMP_Enable(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR0 |= LPCMP_CCR0_CMP_EN_MASK; + } + else + { + base->CCR0 &= ~LPCMP_CCR0_CMP_EN_MASK; + } +} + +/*! + * @brief Select the input channels for LPCMP. This function determines which input + * is selected for the negative and positive mux. + * + * @param base LPCMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel); + +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * Normally, the LPCMP generates a CPU interrupt if there is a rising/falling event. When + * DMA support is enabled and the rising/falling interrupt is enabled , the rising/falling + * event forces a DMA transfer request rather than a CPU interrupt instead. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable DMA support, and "false" means disable DMA support. + */ +static inline void LPCMP_EnableDMA(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= LPCMP_CCR1_DMA_EN_MASK; + } + else + { + base->CCR1 &= ~LPCMP_CCR1_DMA_EN_MASK; + } +} + +/*! + * @brief Configures the filter. + * + * @param base LPCMP peripheral base address. + * @param config Pointer to "lpcmp_filter_config_t" structure. + */ +void LPCMP_SetFilterConfig(LPCMP_Type *base, const lpcmp_filter_config_t *config); + +/*! + * @brief Configure the internal DAC module. + * + * @param base LPCMP peripheral base address. + * @param config Pointer to "lpcmp_dac_config_t" structure. If config is "NULL", disable internal DAC. + */ +void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config); + +/*! + * @brief Enable the interrupts. + * + * @param base LPCMP peripheral base address. + * @param mask Mask value for interrupts. See "_lpcmp_interrupt_enable". + */ +static inline void LPCMP_EnableInterrupts(LPCMP_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disable the interrupts. + * + * @param base LPCMP peripheral base address. + * @param mask Mask value for interrupts. See "_lpcmp_interrupt_enable". + */ +static inline void LPCMP_DisableInterrupts(LPCMP_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + * @brief Get the LPCMP status flags. + * + * @param base LPCMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_lpcmp_status_flags". + */ +static inline uint32_t LPCMP_GetStatusFlags(LPCMP_Type *base) +{ + return base->CSR; +} + +/*! + * @brief Clear the LPCMP status flags + * + * @param base LPCMP peripheral base address. + * @param mask Mask value for the flags. See "_lpcmp_status_flags". + */ +static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask) +{ + base->CSR = mask; +} + +/*! @} */ + +/*! + * @name Window mode + * @{ + */ + +/*! + * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by + * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. + * The optionally inverted comparator output COUT_RAW is sampled on every bus clock + * when WINDOW=1 to generate COUTA. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable window mode, and "false" means disable window mode. + */ +static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; + } + else + { + base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; + } +} + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config); +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +/*! @} */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @name RoundRobin mode + * @{ + */ + +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config); + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value); + +/*! + * @brief Enable/Disable roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin mode, and "false" means disable roundrobin mode. + */ +static inline void LPCMP_EnableRoundRobinMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR0 |= LPCMP_RRCR0_RR_EN_MASK; + } + else + { + base->RRCR0 &= ~LPCMP_RRCR0_RR_EN_MASK; + } +} + +/*! + * @brief Enable/Disable roundrobin internal timer, note that this function is only valid + * when using the internal trigger source. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin internal timer, and "false" means disable roundrobin internal timer. + */ +static inline void LPCMP_EnableRoundRobinInternalTimer(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR2 |= LPCMP_RRCR2_RR_TIMER_EN_MASK; + } + else + { + base->RRCR2 &= ~LPCMP_RRCR2_RR_TIMER_EN_MASK; + } +} + +/*! + * @brief Set preset value for all channels, users can set all channels' preset vaule through this API, + * for example, if the mask set to 0x03U means channel0 and channel2's preset value set to 1U and other + * channels' preset value set to 0U. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_SetPreSetValue(LPCMP_Type *base, uint8_t mask) +{ + base->RRCSR = (uint32_t)mask; +} + +/*! + * @brief Get comparison results for all channels, users can get all channels' comparison + * results through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' comparison result. + */ +static inline uint8_t LPCMP_GetComparisonResult(LPCMP_Type *base) +{ + return (uint8_t)base->RRCSR; +} + +/*! + * @brief Clear input changed flags for single channel or multiple channels, users can clear + * input changed flag of a single channel or multiple channels through this API, for example, + * if the mask set to 0x03U means clear channel0 and channel2's input changed flags. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_ClearInputChangedFlags(LPCMP_Type *base, uint8_t mask) +{ + base->RRSR = (uint32_t)mask; +} + +/*! + * @brief Get input changed flags for all channels, Users can get all channels' input changed + * flags through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' changed flag. + */ +static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base) +{ + return (uint8_t)base->RRSR; +} + +/*! @} */ + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_LPCMP_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpflexcomm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpflexcomm.c new file mode 100644 index 0000000000..b494aa8d96 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpflexcomm.c @@ -0,0 +1,380 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm" +#endif + +/*! + * @brief Used for conversion between `void*` and `uint32_t`. + */ +typedef union pvoid_to_u32 +{ + void *pvoid; + uint32_t u32; +} pvoid_to_u32_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief check whether lpflexcomm supports peripheral type */ +static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph); + +/*! @brief Changes LP_FLEXCOMM mode. */ +static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief Common LPFLEXCOMM IRQhandle. */ +static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LP_FLEXCOMM instance number to base address. */ +static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS; + +/*! @brief Array to map LP_FLEXCOMM instance PTRS. */ +static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS; + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)]; + +/*! @brief Array to map LP_FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = LP_FLEXCOMM_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each LP_FLEXCOMM module */ +static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to LP_FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether lpflexcomm supports peripheral type */ +static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph) +{ + if (periph == LP_FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= LP_FLEXCOMM_PERIPH_LPI2C) + { + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; + } + else if (periph == LP_FLEXCOMM_PERIPH_LPI2CAndLPUART) + { + return true; + } + else + { + return false; + } +} + +/*! @brief Returns for LP_FLEXCOMM base address. */ +uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance) +{ + if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)) + { + return s_lpflexcommBaseAddrs[instance]; + } + return 0U; +} + +/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */ +uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance) +{ + LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance]; + return base->ISTAT; +} + +/* Get the index corresponding to the LP_FLEXCOMM */ +/*! brief Returns instance number for LP_FLEXCOMM module with given base address. */ +uint32_t LP_FLEXCOMM_GetInstance(void *base) +{ + uint32_t i; + pvoid_to_u32_t BaseAddr; + BaseAddr.pvoid = base; + + for (i = 0U; i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs); i++) + { + if (BaseAddr.u32 == s_lpflexcommBaseAddrs[i]) + { + break; + } + } + + assert(i < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs)); + return i; +} + +/* Changes LP_FLEXCOMM mode */ +static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock) +{ + assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART); + LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance]; + + /* Check whether peripheral type is present */ + if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if (((base->PSELID & LP_FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & LP_FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock != 0) + { + base->PSELID = (uint32_t)periph | LP_FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph) +{ + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_lpflexcommClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) + /* Reset the LP_FLEXCOMM module before configuring it.*/ + RESET_ClearPeripheralReset(s_lpflexcommResets[instance]); +#endif + /* Set the LP_FLEXCOMM to given peripheral */ + return LP_FLEXCOMM_SetPeriph(instance, periph, 0); +} + +/*! brief Deinitializes LP_FLEXCOMM. */ +void LP_FLEXCOMM_Deinit(uint32_t instance) +{ + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the peripheral clock */ + CLOCK_DisableClock(s_lpflexcommClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + RESET_SetPeripheralReset(s_lpflexcommResets[instance]); +} + +/*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to + * LP_FLEXCOMM mode */ +void LP_FLEXCOMM_SetIRQHandler(uint32_t instance, + lpflexcomm_irq_handler_t handler, + void *lpflexcommHandle, + LP_FLEXCOMM_PERIPH_T periph) +{ + assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase)); + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_lpflexcommIrqHandler[periph][instance] = NULL; + s_lpflexcommHandle[periph][instance] = lpflexcommHandle; + s_lpflexcommIrqHandler[periph][instance] = handler; +} + +static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance) +{ + uint32_t interruptStat; + + interruptStat = LP_FLEXCOMM_GetInterruptStatus(instance); + if ((interruptStat & + ((uint32_t)kLPFLEXCOMM_I2cSlaveInterruptFlag | (uint32_t)kLPFLEXCOMM_I2cMasterInterruptFlag)) != 0U) + { + if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance] != NULL) + { + s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C][instance]( + instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPI2C][instance]); + } + } + if ((interruptStat & ((uint32_t)kLPFLEXCOMM_UartRxInterruptFlag | (uint32_t)kLPFLEXCOMM_UartTxInterruptFlag)) != 0U) + { + if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance] != NULL) + { + s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPUART][instance]( + instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPUART][instance]); + } + } + if (((interruptStat & (uint32_t)kLPFLEXCOMM_SpiInterruptFlag)) != 0U) + { + if (s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance] != NULL) + { + s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPSPI][instance]( + instance, s_lpflexcommHandle[LP_FLEXCOMM_PERIPH_LPSPI][instance]); + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(LP_FLEXCOMM0) +void LP_FLEXCOMM0_DriverIRQHandler(void); +void LP_FLEXCOMM0_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(0U); +} +#endif + +#if defined(LP_FLEXCOMM1) +void LP_FLEXCOMM1_DriverIRQHandler(void); +void LP_FLEXCOMM1_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(1U); +} +#endif + +#if defined(LP_FLEXCOMM2) +void LP_FLEXCOMM2_DriverIRQHandler(void); +void LP_FLEXCOMM2_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(2U); +} +#endif + +#if defined(LP_FLEXCOMM3) +void LP_FLEXCOMM3_DriverIRQHandler(void); +void LP_FLEXCOMM3_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(3U); +} +#endif + +#if defined(LP_FLEXCOMM4) +void LP_FLEXCOMM4_DriverIRQHandler(void); +void LP_FLEXCOMM4_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(4U); +} +#endif + +#if defined(LP_FLEXCOMM5) +void LP_FLEXCOMM5_DriverIRQHandler(void); +void LP_FLEXCOMM5_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(5U); +} +#endif + +#if defined(LP_FLEXCOMM6) +void LP_FLEXCOMM6_DriverIRQHandler(void); +void LP_FLEXCOMM6_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(6U); +} +#endif + +#if defined(LP_FLEXCOMM7) +void LP_FLEXCOMM7_DriverIRQHandler(void); +void LP_FLEXCOMM7_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(7U); +} +#endif + +#if defined(LP_FLEXCOMM8) +void LP_FLEXCOMM8_DriverIRQHandler(void); +void LP_FLEXCOMM8_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(8U); +} +#endif + +#if defined(LP_FLEXCOMM9) +void LP_FLEXCOMM9_DriverIRQHandler(void); +void LP_FLEXCOMM9_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(9U); +} +#endif + +#if defined(LP_FLEXCOMM10) +void LP_FLEXCOMM10_DriverIRQHandler(void); +void LP_FLEXCOMM10_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(10U); +} +#endif + +#if defined(LP_FLEXCOMM11) +void LP_FLEXCOMM11_DriverIRQHandler(void); +void LP_FLEXCOMM11_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(11U); +} +#endif + +#if defined(LP_FLEXCOMM12) +void LP_FLEXCOMM12_DriverIRQHandler(void); +void LP_FLEXCOMM12_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(12U); +} +#endif + +#if defined(LP_FLEXCOMM13) +void LP_FLEXCOMM13_DriverIRQHandler(void); +void LP_FLEXCOMM13_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(13U); +} +#endif + +#if defined(LP_FLEXCOMM17) +void LP_FLEXCOMM17_DriverIRQHandler(void); +void LP_FLEXCOMM17_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(17U); +} +#endif + +#if defined(LP_FLEXCOMM18) +void LP_FLEXCOMM18_DriverIRQHandler(void); +void LP_FLEXCOMM18_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(18U); +} +#endif + +#if defined(LP_FLEXCOMM19) +void LP_FLEXCOMM19_DriverIRQHandler(void); +void LP_FLEXCOMM19_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(19U); +} +#endif + +#if defined(LP_FLEXCOMM20) +void LP_FLEXCOMM20_DriverIRQHandler(void); +void LP_FLEXCOMM20_DriverIRQHandler(void) +{ + LP_FLEXCOMM_CommonIRQHandler(20U); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpflexcomm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpflexcomm.h new file mode 100644 index 0000000000..3dc449b653 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpflexcomm.h @@ -0,0 +1,88 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LP_FLEXCOMM_H_ +#define FSL_LP_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpflexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version. */ +#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +/*! @brief LP_FLEXCOMM peripheral modes. */ +typedef enum +{ + LP_FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + LP_FLEXCOMM_PERIPH_LPUART, /*!< LPUART peripheral */ + LP_FLEXCOMM_PERIPH_LPSPI, /*!< LPSPI Peripheral */ + LP_FLEXCOMM_PERIPH_LPI2C, /*!< LPI2C Peripheral */ + LP_FLEXCOMM_PERIPH_LPI2CAndLPUART = 7, /*!< LPI2C and LPUART Peripheral */ +} LP_FLEXCOMM_PERIPH_T; + +/*! @brief LP_FLEXCOMM interrupt source flags. */ +enum _lpflexcomm_interrupt_flag +{ + kLPFLEXCOMM_I2cSlaveInterruptFlag = LP_FLEXCOMM_ISTAT_I2CS_MASK, /* LPI2C slave interrupt. */ + kLPFLEXCOMM_I2cMasterInterruptFlag = LP_FLEXCOMM_ISTAT_I2CM_MASK, /* LPI2C master interrupt. */ + kLPFLEXCOMM_SpiInterruptFlag = LP_FLEXCOMM_ISTAT_SPI_MASK, /* LPSPI interrupt. */ + kLPFLEXCOMM_UartRxInterruptFlag = LP_FLEXCOMM_ISTAT_UARTRX_MASK, /* LPUART RX interrupt. */ + kLPFLEXCOMM_UartTxInterruptFlag = LP_FLEXCOMM_ISTAT_UARTTX_MASK, /* LPUART TX interrupt. */ + + kLPFLEXCOMM_AllInterruptFlag = kLPFLEXCOMM_I2cSlaveInterruptFlag | kLPFLEXCOMM_I2cMasterInterruptFlag | + kLPFLEXCOMM_SpiInterruptFlag | kLPFLEXCOMM_UartRxInterruptFlag | + kLPFLEXCOMM_UartTxInterruptFlag, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*lpflexcomm_irq_handler_t)(uint32_t instance, void *handle); + +/*! @brief Array with IRQ number for each LP_FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */ +uint32_t LP_FLEXCOMM_GetInstance(void *base); + +/*! @brief Returns for LP_FLEXCOMM base address. */ +uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance); + +/*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */ +uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance); + +/*! @brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph); + +/*! @brief Deinitializes LP_FLEXCOMM. */ +void LP_FLEXCOMM_Deinit(uint32_t instance); + +/*! @brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to + * LP_FLEXCOMM mode */ +void LP_FLEXCOMM_SetIRQHandler(uint32_t instance, + lpflexcomm_irq_handler_t handler, + void *lpflexcommHandle, + LP_FLEXCOMM_PERIPH_T periph); + +#if defined(__cplusplus) +} +#endif + +/*@}*/ + +#endif /* FSL_LP_FLEXCOMM_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c.c new file mode 100644 index 0000000000..43e081a0fe --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c.c @@ -0,0 +1,2423 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpi2c" +#endif + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpi2c_slave_isr_t)(uint32_t instance, void *handle); + +/*! + * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpi2c_master_isr_t` + */ +typedef union lpi2c_to_lpflexcomm +{ + lpi2c_master_isr_t lpi2c_master_handler; + lpi2c_slave_isr_t lpi2c_slave_handler; + lpflexcomm_irq_handler_t lpflexcomm_handler; +} lpi2c_to_lpflexcomm_t; + +/* ! @brief LPI2C master fifo commands. */ +enum +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum +{ + kDefaultTxWatermark = 0, + kDefaultRxWatermark = 0, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t LPI2C_GetCyclesForWidth( + uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler); + +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); + +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); + +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); + +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/*! @brief Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map LPI2C instance number to clock gate enum. */ +static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; + +#if defined(LPI2C_PERIPH_CLOCKS) +/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ +static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpi2c_slave_isr_t s_lpi2cSlaveIsr; + +/*! @brief Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +void *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; + +/*! @brief Pointers to slave handles for each instance. */ +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The LPI2C peripheral base address. + * return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base) +{ + uint32_t instance; + for (instance = 0U; instance < ARRAY_SIZE(kLpi2cBases); ++instance) + { + if (kLpi2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(kLpi2cBases)); + return instance; +} + +/*! + * @brief Computes a cycle count for a given time in nanoseconds. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param width_ns Desired with in nanoseconds. + * @param minCycles Minimum cycle count. + * @param maxCycles Maximum cycle count. + * @param prescaler LPI2C prescaler setting. If the cycle period is not affected by the prescaler value, set it to 0. + */ +static uint32_t LPI2C_GetCyclesForWidth( + uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler) +{ + assert(sourceClock_Hz > 0U); + + uint32_t divider = 1U; + + while (prescaler != 0U) + { + divider *= 2U; + prescaler--; + } + + uint32_t busCycle_ns = 1000000U / (sourceClock_Hz / divider / 1000U); + /* Calculate the cycle count, round up the calculated value. */ + uint32_t cycles = (width_ns * 10U / busCycle_ns + 5U) / 10U; + + /* If the calculated value is smaller than the minimum value, use the minimum value */ + if (cycles < minCycles) + { + cycles = minCycles; + } + /* If the calculated value is larger than the maximum value, use the maxmum value */ + if (cycles > maxCycles) + { + cycles = maxCycles; + } + + return cycles; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kLPI2C_MasterErrorFlags; + if (0U != status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0U != (status & (uint32_t)kLPI2C_MasterPinLowTimeoutFlag)) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterArbitrationLostFlag)) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterNackDetectFlag)) + { + result = kStatus_LPI2C_Nak; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the flags. */ + LPI2C_MasterClearStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/*! + * @brief Wait until there is room in the tx fifo. + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) +{ + status_t result = kStatus_Success; + uint32_t status; + size_t txCount; + size_t txFifoSize = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheckAndClearError(base, status); + if (kStatus_Success != result) + { + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == txCount) && (0U != waitTimes)); + + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == txCount); +#endif + + return result; +} + +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Busy + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) +{ + status_t ret = kStatus_Success; + + uint32_t status = LPI2C_MasterGetStatusFlags(base); + if ((0U != (status & (uint32_t)kLPI2C_MasterBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_MasterBusyFlag))) + { + ret = kStatus_LPI2C_Busy; + } + + return ret; +} + +/*! + * brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0U; + * masterConfig->pinLowTimeout_ns = 0U; + * masterConfig->sdaGlitchFilterWidth_ns = 0U; + * masterConfig->sclGlitchFilterWidth_ns = 0U; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->debugEnable = false; + masterConfig->enableDoze = true; + masterConfig->ignoreAck = false; + masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + masterConfig->baudRate_Hz = 100000U; + masterConfig->busIdleTimeout_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->pinLowTimeout_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->sdaGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->sclGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->hostRequest.enable = false; + masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; +} + +/*! + * brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The LPI2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ + uint32_t prescaler; + uint32_t cycles; + uint32_t cfgr2; + uint32_t value; + uint32_t instance = LPI2C_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPI2C mode */ + status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + /* Reset peripheral before configuring it. */ + LPI2C_MasterReset(base); + + /* Doze bit: 0 is enable, 1 is disable */ + base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze)); + + /* host request */ + value = base->MCFGR0; + value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); + value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | + LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) | + LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source); + base->MCFGR0 = value; + + /* pin config and ignore ack */ + value = base->MCFGR1; + value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); + value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); + value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); + base->MCFGR1 = value; + + LPI2C_MasterSetWatermarks(base, (size_t)kDefaultTxWatermark, (size_t)kDefaultRxWatermark); + + /* Configure glitch filters. */ + cfgr2 = base->MCFGR2; + if (0U != (masterConfig->sdaGlitchFilterWidth_ns)) + { + /* Calculate SDA filter width. The width is equal to FILTSDA cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns, 1U, + (LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 0U); + cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles); + } + if (0U != masterConfig->sclGlitchFilterWidth_ns) + { + /* Calculate SDL filter width. The width is equal to FILTSCL cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns, 1U, + (LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 0U); + cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); + } + base->MCFGR2 = cfgr2; + + /* Configure baudrate after the SDA/SCL glitch filter setting, + since the baudrate calculation needs them as parameter. */ + LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); + + /* Configure bus idle and pin low timeouts after baudrate setting, + since the timeout calculation needs prescaler as parameter. */ + prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; + + if (0U != (masterConfig->busIdleTimeout_ns)) + { + /* Calculate bus idle timeout value. The value is equal to BUSIDLE cycles of functional clock divided by + prescaler. And set BUSIDLE to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, 1U, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + cfgr2 &= ~LPI2C_MCFGR2_BUSIDLE_MASK; + cfgr2 |= LPI2C_MCFGR2_BUSIDLE(cycles); + } + base->MCFGR2 = cfgr2; + if (0U != masterConfig->pinLowTimeout_ns) + { + /* Calculate bus pin low timeout value. The value is equal to PINLOW cycles of functional clock divided by + prescaler. And set PINLOW to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256U, 1U, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); + } + + LPI2C_MasterEnable(base, masterConfig->enableMaster); +} + +/*! + * brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base) +{ + uint32_t instance = LPI2C_GetInstance(base); + + /* Restore to reset state. */ + LPI2C_MasterReset(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + LP_FLEXCOMM_Deinit(instance); + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base)); +#endif +} + +/*! + * brief Configures LPI2C master data match feature. + * + * param base The LPI2C peripheral base address. + * param matchConfig Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig) +{ + /* Disable master mode. */ + bool wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); + LPI2C_MasterEnable(base, false); + + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(matchConfig->matchMode); + base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(matchConfig->rxDataMatchOnly); + base->MDMR = LPI2C_MDMR_MATCH0(matchConfig->match0) | LPI2C_MDMR_MATCH1(matchConfig->match1); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * param base The LPI2C peripheral base address. + * param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) +{ + bool wasEnabled; + uint8_t filtScl = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSCL_MASK) >> LPI2C_MCFGR2_FILTSCL_SHIFT); + + uint8_t divider = 1U; + uint8_t bestDivider = 1U; + uint8_t prescale = 0U; + uint8_t bestPre = 0U; + + uint8_t clkCycle; + uint8_t bestclkCycle = 0U; + + uint32_t absError = 0U; + uint32_t bestError = 0xffffffffu; + uint32_t computedRate; + + uint32_t tmpReg = 0U; + + /* Disable master mode. */ + wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); + LPI2C_MasterEnable(base, false); + + /* Baud rate = (sourceClock_Hz / 2 ^ prescale) / (CLKLO + 1 + CLKHI + 1 + SCL_LATENCY) + * SCL_LATENCY = ROUNDDOWN((2 + FILTSCL) / (2 ^ prescale)) + */ + for (prescale = 0U; prescale <= 7U; prescale++) + { + /* Calculate the clkCycle, clkCycle = CLKLO + CLKHI, divider = 2 ^ prescale */ + clkCycle = (uint8_t)((10U * sourceClock_Hz / divider / baudRate_Hz + 5U) / 10U - (2U + filtScl) / divider - 2U); + /* According to register description, The max value for CLKLO and CLKHI is 63. + however to meet the I2C specification of tBUF, CLKHI should be less than + clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U. Refer to the comment of the tmpHigh's + calculation for details. So we have: + CLKHI < clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U, + clkCycle = CLKHI + CLKLO and + sourceClock_Hz / baudRate_Hz / divider = clkCycle + 2 + ROUNDDOWN((2 + FILTSCL) / divider), + we can come up with: CLKHI < 0.92 x CLKLO - ROUNDDOWN(2 + FILTSCL) / divider + so the max boundary of CLKHI should be 0.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider, + and the max boundary of clkCycle is 1.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider. */ + if (clkCycle > (120U - (2U + filtScl) / divider)) + { + divider *= 2U; + continue; + } + /* Calculate the computed baudrate and compare it with the desired baudrate */ + computedRate = (sourceClock_Hz / (uint32_t)divider) / + ((uint32_t)clkCycle + 2U + (2U + (uint32_t)filtScl) / (uint32_t)divider); + absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + if (absError < bestError) + { + bestPre = prescale; + bestDivider = divider; + bestclkCycle = clkCycle; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0U) + { + break; + } + } + divider *= 2U; + } + + /* SCL low time tLO should be larger than or equal to SCL high time tHI: + tLO = ((CLKLO + 1) x (2 ^ PRESCALE)) >= tHI = ((CLKHI + 1 + SCL_LATENCY) x (2 ^ PRESCALE)), + which is CLKLO >= CLKHI + (2U + filtScl) / bestDivider. + Also since bestclkCycle = CLKLO + CLKHI, bestDivider = 2 ^ PRESCALE + which makes CLKHI <= (bestclkCycle - (2U + filtScl) / bestDivider) / 2U. + + The max tBUF should be at least 0.52 times of the SCL clock cycle: + tBUF = ((CLKLO + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.52 / baudRate_Hz), + plus bestDivider = 2 ^ PRESCALE, bestclkCycle = CLKLO + CLKHI we can come up with + CLKHI <= (bestclkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / bestDivider + 1U). + In this case to get a safe CLKHI calculation, we can assume: + */ + uint8_t tmpHigh = (bestclkCycle - (2U + filtScl) / bestDivider) / 2U; + while (tmpHigh > (bestclkCycle - 52U * sourceClock_Hz / baudRate_Hz / bestDivider / 100U + 1U)) + { + tmpHigh = tmpHigh - 1U; + } + + /* Calculate DATAVD and SETHOLD. + To meet the timing requirement of I2C spec for standard mode, fast mode and fast mode plus: */ + /* The min tHD:STA/tSU:STA/tSU:STO should be at least 0.4 times of the SCL clock cycle, use 0.5 to be safe: + tHD:STA = ((SETHOLD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.5 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpHold = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 2U) - 1U; + + /* The max tVD:DAT/tVD:ACK/tHD:DAT should be at most 0.345 times of the SCL clock cycle, use 0.25 to be safe: + tVD:DAT = ((DATAVD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) < (0.25 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpDataVd = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 4U) - 1U; + + /* The min tSU:DAT should be at least 0.05 times of the SCL clock cycle: + tSU:DAT = ((2 + FILTSDA + 2 ^ PRESCALE) / sourceClock_Hz) >= (0.05 / baud), + plus bestDivider = 2 ^ PRESCALE, we can come up with: + FILTSDA >= (0.05 x sourceClock_Hz / baudRate_Hz - bestDivider - 2) */ + if ((sourceClock_Hz / baudRate_Hz / 20U) > (bestDivider + 2U)) + { + /* Read out the FILTSDA configuration, if it is smaller than expected, change the setting. */ + uint8_t filtSda = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSDA_MASK) >> LPI2C_MCFGR2_FILTSDA_SHIFT); + if (filtSda < (sourceClock_Hz / baudRate_Hz / 20U - bestDivider - 2U)) + { + filtSda = (uint8_t)(sourceClock_Hz / baudRate_Hz / 20U) - bestDivider - 2U; + } + base->MCFGR2 = (base->MCFGR2 & ~LPI2C_MCFGR2_FILTSDA_MASK) | LPI2C_MCFGR2_FILTSDA(filtSda); + } + + /* Set CLKHI, CLKLO, SETHOLD, DATAVD value. */ + tmpReg = LPI2C_MCCR0_CLKHI((uint32_t)tmpHigh) | + LPI2C_MCCR0_CLKLO((uint32_t)((uint32_t)bestclkCycle - (uint32_t)tmpHigh)) | + LPI2C_MCCR0_SETHOLD((uint32_t)tmpHold) | LPI2C_MCCR0_DATAVD((uint32_t)tmpDataVd); + base->MCCR0 = tmpReg; + + /* Set PRESCALE value. */ + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The LPI2C peripheral base address. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + /* Return an error if the bus is already in use not by us. */ + status_t result = LPI2C_CheckForBusyBus(base); + if (kStatus_Success == result) + { + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Wait until there is room in the fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Issue start command. */ + base->MTDR = (uint32_t)kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir); + } + } + + return result; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The LPI2C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base) +{ + /* Wait until there is room in the fifo. */ + status_t result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Send the STOP signal */ + base->MTDR = (uint32_t)kStopCmd; + + /* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ + /* Also check for errors while waiting. */ +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + +#if I2C_RETRY_TIMES != 0U + while ((result == kStatus_Success) && (0U != waitTimes)) + { + waitTimes--; +#else + while (result == kStatus_Success) + { +#endif + uint32_t status = LPI2C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + result = LPI2C_MasterCheckAndClearError(base, status); + + /* Check if the stop was sent successfully. */ + if ((0U != (status & (uint32_t)kLPI2C_MasterStopDetectFlag)) && + (0U != (status & (uint32_t)kLPI2C_MasterTxReadyFlag))) + { + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterStopDetectFlag); + break; + } + } + +#if I2C_RETRY_TIMES != 0U + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#endif + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) +{ + assert(NULL != rxBuff); + + status_t result = kStatus_Success; + uint8_t *buf; + size_t tmpRxSize = rxSize; +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes; +#endif + + /* Check transfer data size. */ + if (rxSize > (256UL * (uint32_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base))) + { + return kStatus_InvalidArgument; + } + + /* Handle empty read. */ + if (rxSize != 0U) + { + /* Wait until there is room in the command fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Issue command to receive data. A single write to MTDR can issue read operation of 0xFFU + 1 byte of data + at most, so when the rxSize is larger than 0x100U, push multiple read commands to MTDR until rxSize is + reached. */ + while (tmpRxSize != 0U) + { + if (tmpRxSize > 256U) + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (0U != (rxSize--)) + { +#if I2C_RETRY_TIMES != 0U + waitTimes = I2C_RETRY_TIMES; +#endif + /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ + /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ + /* using a single register read. */ + uint32_t value = 0U; + do + { + /* Check for errors. */ + result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base)); + if (kStatus_Success != result) + { + break; + } + + value = base->MRDR; +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U != (value & LPI2C_MRDR_RXEMPTY_MASK)) && (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U != (value & LPI2C_MRDR_RXEMPTY_MASK)); +#endif + if ((status_t)kStatus_Success != result) + { + break; + } + + *buf++ = (uint8_t)(value & LPI2C_MRDR_DATA_MASK); + } + } + } + + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + + assert(NULL != txBuff); + + /* Send data buffer */ + while (0U != (txSize--)) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = *buf++; + } + + return result; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The LPI2C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer) +{ + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result = kStatus_Success; + status_t ret = kStatus_Success; + uint16_t commandBuffer[7]; + uint32_t cmdCount = 0U; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == kLPI2C_Read) && + (transfer->dataSize > (256UL * (uint32_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base)))) + { + return kStatus_InvalidArgument; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (kStatus_Success == result) + { + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + lpi2c_direction_t direction = (0U != transfer->subaddressSize) ? kLPI2C_Write : transfer->direction; + if (0U == (transfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction); + } + + /* Subaddress, MSB first. */ + if (0U != transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (0U != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + commandBuffer[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != transfer->dataSize) && (transfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Send command buffer */ + uint32_t index = 0U; + while (0U != cmdCount--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = commandBuffer[index]; + index++; + } + + if (kStatus_Success == result) + { + /* Transmit data. */ + if ((transfer->direction == kLPI2C_Write) && (transfer->dataSize > 0U)) + { + /* Send Data. */ + result = LPI2C_MasterSend(base, transfer->data, transfer->dataSize); + } + + /* Receive Data. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > 0U)) + { + result = LPI2C_MasterReceive(base, transfer->data, transfer->dataSize); + } + + if (kStatus_Success == result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + result = LPI2C_MasterStop(base); + } + } + } + /* Transmit fail */ + if (kStatus_Success != result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + ret = LPI2C_MasterStop(base); + if(kStatus_Success != ret) + { + result = ret; + } + } + } + } + + return result; +} + +/*! + * brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_t handler; + (void)memset(&handler, 0, sizeof(handler)); + + /* Save the handle in global variables to support the double weak mechanism. */ + handler.lpi2c_master_handler = LPI2C_MasterTransferHandleIRQ; + LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save this handle for IRQ use. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; + } + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kLpi2cIrqs[instance]); +} + +/*! + * @brief Execute states until FIFOs are exhausted. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + status_t result = kStatus_Success; + lpi2c_master_transfer_t *xfer; + size_t txCount; + size_t rxCount; + size_t txFifoSize = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + bool state_complete = false; + uint16_t sendval; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = LPI2C_MasterGetStatusFlags(base); + + /* Get fifo counts. */ + LPI2C_MasterGetFifoCounts(base, &rxCount, &txCount); + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + /* For the last byte, nack flag is expected. + Do not check and clear kLPI2C_MasterNackDetectFlag for the last byte, + in case FIFO is emptied when stop command has not been sent. */ + if (handle->remainingBytes == 0U) + { + /* When data size is not zero which means it is not only one byte of address is sent, and */ + /* when the txfifo is empty, or have one byte which is the stop command, then the nack status can be ignored. */ + if ((xfer->dataSize != 0U) && + ((txCount == 0U) || ((txCount == 1U) && (handle->state == (uint8_t)kWaitForCompletionState) && + ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U)))) + { + status &= ~(uint32_t)kLPI2C_MasterNackDetectFlag; + } + } + + result = LPI2C_MasterCheckAndClearError(base, status); + + if (kStatus_Success == result) + { + /* Compute room in tx fifo */ + txCount = txFifoSize - txCount; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSendCommandState: + /* Make sure there is room in the tx fifo for the next command. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ + sendval = ((uint16_t)handle->buf[0]) | (((uint16_t)handle->buf[1]) << 8U); + base->MTDR = sendval; + handle->buf++; + handle->buf++; + + /* Count down until all commands are sent. */ + if (--handle->remainingBytes == 0U) + { + /* Choose next state and set up buffer pointer and count. */ + if (0U != xfer->dataSize) + { + /* Either a send or receive transfer is next. */ + handle->state = (uint8_t)kTransferDataState; + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = (uint16_t)xfer->dataSize; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterTxReadyFlag); + /* Issue command to receive data. A single write to MTDR can issue read operation of + 0xFFU + 1 byte of data at most, so when the dataSize is larger than 0x100U, push + multiple read commands to MTDR until dataSize is reached. */ + size_t tmpRxSize = xfer->dataSize; + while (tmpRxSize != 0U) + { + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + while (txFifoSize == txCount) + { + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + } + + if (tmpRxSize > 256U) + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + } + } + else + { + /* No transfer, so move to stop state. */ + handle->state = (uint8_t)kStopState; + } + } + break; + + case (uint8_t)kIssueReadCommandState: + /* Make sure there is room in the tx fifo for the read command. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + base->MTDR = (uint32_t)kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1U); + + /* Move to transfer state. */ + handle->state = (uint8_t)kTransferDataState; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterTxReadyFlag); + } + break; + + case (uint8_t)kTransferDataState: + if (xfer->direction == kLPI2C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + /* Put byte to send in fifo. */ + base->MTDR = *(handle->buf)++; + } + else + { + /* XXX handle receive sizes > 256, use kIssueReadCommandState */ + /* Make sure there is data in the rx fifo. */ + if (0U == rxCount--) + { + state_complete = true; + break; + } + + /* Read byte from fifo. */ + *(handle->buf)++ = (uint8_t)(base->MRDR & LPI2C_MRDR_DATA_MASK); + } + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0U) + { + if (xfer->direction == kLPI2C_Write) + { + state_complete = true; + } + handle->state = (uint8_t)kStopState; + } + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (0U == txCount--) + { + state_complete = true; + break; + } + + base->MTDR = (uint32_t)kStopCmd; + } + else + { + /* If all data is read and no stop flag is required to send, we are done. */ + if (xfer->direction == kLPI2C_Read) + { + *isDone = true; + } + state_complete = true; + } + handle->state = (uint8_t)kWaitForCompletionState; + break; + + case (uint8_t)kWaitForCompletionState: + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* We stay in this state until the stop state is detected. */ + if (0U != (status & (uint32_t)kLPI2C_MasterStopDetectFlag)) + { + *isDone = true; + } + } + else + { + /* If all data is pushed to FIFO and no stop flag is required to send, we need to make sure they + are all send out to bus. */ + if ((xfer->direction == kLPI2C_Write) && ((base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) == 0U)) + { + /* We stay in this state until the data is sent out to bus. */ + *isDone = true; + } + } + state_complete = true; + break; + default: + assert(false); + break; + } + } + } + return result; +} + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param handle Master nonblocking driver handle. + */ +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + handle->state = (uint8_t)kIssueReadCommandState; + } + else + { + /* Start immediately in the data transfer state. */ + handle->state = (uint8_t)kTransferDataState; + } + + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = (uint16_t)xfer->dataSize; + } + else + { + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0U; + + /* Initial direction depends on whether a subaddress was provided, and of course the actual */ + /* data transfer direction. */ + lpi2c_direction_t direction = (0U != xfer->subaddressSize) ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (0U != xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (0U != (subaddressRemaining--)) + { + uint8_t subaddressByte = (uint8_t)((xfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != xfer->dataSize) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Set up state machine for transferring the commands. */ + handle->state = (uint8_t)kSendCommandState; + handle->remainingBytes = (uint16_t)cmdCount; + handle->buf = (uint8_t *)&handle->commandBuffer; + } +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == kLPI2C_Read) && + (transfer->dataSize > (256U * (uint32_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base)))) + { + return kStatus_InvalidArgument; + } + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + result = kStatus_LPI2C_Busy; + } + else + { + result = LPI2C_CheckForBusyBus(base); + } + + if ((status_t)kStatus_Success == result) + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset FIFO in case there are data. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + LPI2C_InitTransferStateMachine(handle); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_MasterEnableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + } + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) +{ + status_t result = kStatus_Success; + + assert(NULL != handle); + + if (NULL == count) + { + result = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + result = kStatus_NoTransferInProgress; + } + else + { + uint8_t state; + uint16_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); + LPI2C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + LPI2C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case (uint8_t)kIdleState: + case (uint8_t)kSendCommandState: + case (uint8_t) + kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ + *count = 0; + break; + + case (uint8_t)kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case (uint8_t)kStopState: + case (uint8_t)kWaitForCompletionState: + default: + *count = dataSize; + break; + } + } + + return result; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* If master is still busy and has not send out stop signal yet. */ + if ((LPI2C_MasterGetStatusFlags(base) & ((uint32_t)kLPI2C_MasterStopDetectFlag | + (uint32_t)kLPI2C_MasterBusyFlag)) == (uint32_t)kLPI2C_MasterBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + base->MTDR = (uint32_t)kStopCmd; + } + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param instance The LPI2C instance. + * param lpi2cMasterHandle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle) +{ + assert(lpi2cMasterHandle != NULL); + assert(instance < ARRAY_SIZE(kLpi2cBases)); + LPI2C_Type *base = kLpi2cBases[instance]; + lpi2c_master_handle_t *handle = (lpi2c_master_handle_t *)lpi2cMasterHandle; + bool isDone = false; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL != handle) + { + if (handle->state != (uint8_t)kIdleState) + { + result = LPI2C_RunTransferStateMachine(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Handle error, terminate xfer */ + if (result != kStatus_Success) + { + LPI2C_MasterTransferAbort(base, handle); + } + + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke callback. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } + } + } +} + +/*! + * brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the a + * address0 member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->address0 = 0U; + slaveConfig->address1 = 0U; + slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + slaveConfig->filterDozeEnable = true; + slaveConfig->filterEnable = true; + slaveConfig->enableGeneralCall = false; + slaveConfig->sclStall.enableAck = false; + slaveConfig->sclStall.enableTx = true; + slaveConfig->sclStall.enableRx = true; + slaveConfig->sclStall.enableAddress = false; + slaveConfig->ignoreAck = false; + slaveConfig->enableReceivedAddressRead = false; + slaveConfig->sdaGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + slaveConfig->sclGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + slaveConfig->dataValidDelay_ns = 0U; + /* When enabling the slave tx SCL stall, set the default clock hold time to 250ns according + to I2C spec for standard mode baudrate(100k). User can manually change it to 100ns or 50ns + for fast-mode(400k) or fast-mode+(1m). */ + slaveConfig->clockHoldTime_ns = 250U; +} + +/*! + * brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * param base The LPI2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) +{ + uint32_t tmpReg; + uint32_t tmpCycle; + uint32_t instance = LPI2C_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPI2C mode */ + status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + /* Restore to reset conditions. */ + LPI2C_SlaveReset(base); + + /* Configure peripheral. */ + base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1); + + base->SCFGR1 = + LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) | + LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) | + LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) | + LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) | + LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress); + + /* Calculate SDA filter width. The width is equal to FILTSDA+3 cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 4. */ + tmpReg = LPI2C_SCFGR2_FILTSDA( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns, 4U, + (LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT) + 3U, 0U) - + 3U); + + /* Calculate SDL filter width. The width is equal to FILTSCL+3 cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 4. */ + tmpCycle = LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns, 4U, + (LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT) + 3U, 0U); + tmpReg |= LPI2C_SCFGR2_FILTSCL(tmpCycle - 3U); + + /* Calculate data valid time. The time is equal to FILTSCL+DATAVD+3 cycles of functional clock. + So the min value is FILTSCL+3. */ + tmpReg |= LPI2C_SCFGR2_DATAVD( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns, tmpCycle, + tmpCycle + (LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 0U) - + tmpCycle); + + /* Calculate clock hold time. The time is equal to CLKHOLD+3 cycles of functional clock. + So the min value is 3. */ + base->SCFGR2 = + tmpReg | LPI2C_SCFGR2_CLKHOLD( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns, 3U, + (LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT) + 3U, 0U) - + 3U); + + /* Save SCR to last so we don't enable slave until it is configured */ + base->SCR = LPI2C_SCR_FILTDZ(!slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) | + LPI2C_SCR_SEN(slaveConfig->enableSlave); +} + +/*! + * brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base) +{ + uint32_t instance = LPI2C_GetInstance(base); + + /* Restore to reset state. */ + LPI2C_SlaveReset(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + LP_FLEXCOMM_Deinit(instance); + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base)); +#endif +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_BitError + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) +{ + status_t result = kStatus_Success; + + flags &= (uint32_t)kLPI2C_SlaveErrorFlags; + if (0U != flags) + { + if (0U != (flags & (uint32_t)kLPI2C_SlaveBitErrFlag)) + { + result = kStatus_LPI2C_BitError; + } + else if (0U != (flags & (uint32_t)kLPI2C_SlaveFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the errors. */ + LPI2C_SlaveClearStatusFlags(base, flags); + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param[out] actualTxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + size_t remaining = txSize; + + assert(NULL != txBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can transmit. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (kStatus_Success != result) + { + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if (kStatus_Success != result) + { + break; + } + + /* Send a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + base->STDR = *buf++; + --remaining; + } + + /* Exit loop if we see a stop or restart in transfer*/ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags( + base, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param[out] actualRxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)rxBuff; + size_t remaining = rxSize; + + assert(NULL != rxBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can receive. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (kStatus_Success != result) + { + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if ((status_t)kStatus_Success != result) + { + break; + } + + /* Receive a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + *buf++ = (uint8_t)(base->SRDR & LPI2C_SRDR_DATA_MASK); + --remaining; + } + + /* Exit loop if we see a stop or restart */ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags( + base, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + + return result; +} + +/*! + * brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_t handler; + (void)memset(&handler, 0, sizeof(handler)); + + /* Save the handle in global variables to support the double weak mechanism. */ + handler.lpi2c_slave_handler = LPI2C_SlaveTransferHandleIRQ; + LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save this handle for IRQ use. */ + s_lpi2cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; + } + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + (void)EnableIRQ(kLpi2cIrqs[instance]); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) +{ + status_t result = kStatus_Success; + + assert(NULL != handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + result = kStatus_LPI2C_Busy; + } + else + { + /* Return an error if the bus is already in use not by us. */ + uint32_t status = LPI2C_SlaveGetStatusFlags(base); + if ((0U != (status & (uint32_t)kLPI2C_SlaveBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_SlaveBusyFlag))) + { + result = kStatus_LPI2C_Busy; + } + } + + if ((status_t)kStatus_Success == result) + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kLPI2C_SlaveTransmitEvent | (uint32_t)kLPI2C_SlaveReceiveEvent; + + /* Ack by default. */ + base->STAR = 0U; + + /* Clear all flags. */ + LPI2C_SlaveClearStatusFlags(base, (uint32_t)kLPI2C_SlaveClearFlags); + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_SlaveEnableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + } + + return result; +} + +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The LPI2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) +{ + status_t status = kStatus_Success; + + assert(NULL != handle); + + if (count == NULL) + { + status = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (!handle->isBusy) + { + *count = 0; + status = kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + else + { + *count = handle->transferredCount; + } + + return status; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * retval #kStatus_Success + * retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + assert(NULL != handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable LPI2C IRQ sources. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param instance The LPI2C instance. + * param lpi2cSlaveHandle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle) +{ + assert(instance < ARRAY_SIZE(kLpi2cBases)); + uint32_t flags; + lpi2c_slave_transfer_t *xfer; + LPI2C_Type *base = kLpi2cBases[instance]; + lpi2c_slave_handle_t *handle = (lpi2c_slave_handle_t *)lpi2cSlaveHandle; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL != handle) + { + xfer = &handle->transfer; + + /* Get status flags. */ + flags = LPI2C_SlaveGetStatusFlags(base); + + if (0U != (flags & ((uint32_t)kLPI2C_SlaveBitErrFlag | (uint32_t)kLPI2C_SlaveFifoErrFlag))) + { + xfer->event = kLPI2C_SlaveCompletionEvent; + xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { + if (0U != + (flags & (((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag) | ((uint32_t)kLPI2C_SlaveStopDetectFlag)))) + { + xfer->event = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ? + kLPI2C_SlaveRepeatedStartEvent : + kLPI2C_SlaveCompletionEvent; + xfer->receivedAddress = 0U; + xfer->completionStatus = kStatus_Success; + xfer->transferredCount = handle->transferredCount; + + if (xfer->event == kLPI2C_SlaveCompletionEvent) + { + handle->isBusy = false; + } + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --xfer->transferredCount; + handle->wasTransmit = false; + } + + /* Clear the flag. */ + LPI2C_SlaveClearStatusFlags(base, flags & ((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag | + (uint32_t)kLPI2C_SlaveStopDetectFlag)); + + /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ + base->STAR = 0U; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (0U != (flags & (uint32_t)kLPI2C_SlaveStopDetectFlag)) + { + /* Clean up transfer info on completion, after the callback has been invoked. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveAddressValidFlag)) + { + xfer->event = kLPI2C_SlaveAddressMatchEvent; + xfer->receivedAddress = (uint8_t)(base->SASR & LPI2C_SASR_RADDR_MASK); + + /* Update handle status to busy because slave is addressed. */ + handle->isBusy = true; + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveTransmitAckFlag)) + { + xfer->event = kLPI2C_SlaveTransmitAckEvent; + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + else + { + LPI2C_SlaveTransmitAck(base, true); + } + } + + /* Handle transmit and receive. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveTransmitEvent; + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Transmit a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + base->STDR = *xfer->data++; + --xfer->dataSize; + ++handle->transferredCount; + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveReceiveEvent; + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Receive a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + *xfer->data++ = (uint8_t)base->SRDR; + --xfer->dataSize; + ++handle->transferredCount; + if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK)) + { + if (((0U == (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) || + (NULL == handle->callback))) + { + LPI2C_SlaveTransmitAck(base, true); + } + } + } + else + { + /* We don't have any room to receive more data, so send a nack. */ + if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK)) + { + if (((0U == (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) || + (NULL == handle->callback))) + { + LPI2C_SlaveTransmitAck(base, false); + } + } + } + } + } + } +} + +#if !(defined(FSL_FEATURE_I2C_HAS_NO_IRQ) && FSL_FEATURE_I2C_HAS_NO_IRQ) +/*! + * @brief Shared IRQ handler that can call both master and slave ISRs. + * + * The master and slave ISRs are called through function pointers in order to decouple + * this code from the ISR functions. Without this, the linker would always pull in both + * ISRs and every function they call, even if only the functional API was used. + * + * @param base The LPI2C peripheral base address. + * @param instance The LPI2C peripheral instance number. + */ +void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); +void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if ((0U != (base->MCR & LPI2C_MCR_MEN_MASK)) && (NULL != s_lpi2cMasterIsr)) + { + /* Master mode. */ + s_lpi2cMasterIsr(instance, s_lpi2cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((0U != (base->SCR & LPI2C_SCR_SEN_MASK)) && (NULL != s_lpi2cSlaveIsr)) + { + /* Slave mode. */ + s_lpi2cSlaveIsr(instance, s_lpi2cSlaveHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(LPI2C15) +/* Implementation of LPI2C15 handler named in startup code. */ +void LPI2C15_DriverIRQHandler(void); +void LPI2C15_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C15, 15U); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c.h new file mode 100644 index 0000000000..cd7cba0335 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c.h @@ -0,0 +1,1342 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPI2C_H_ +#define FSL_LPI2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C driver version. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief LPI2C status return codes. */ +enum +{ + kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = + MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout polling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_master_flags +{ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK, /*!< Bus busy flag */ + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_MasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag | kLPI2C_MasterDataMatchFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_MasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + /*! Errors to check for. */ + kLPI2C_MasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | + kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _lpi2c_direction +{ + kLPI2C_Write = 0U, /*!< Master transmit. */ + kLPI2C_Read = 1U /*!< Master receive. */ +} lpi2c_direction_t; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = + 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = + 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = + 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/*! + * @brief Structure with settings to initialize the LPI2C master module. + * + * This structure holds configuration settings for the LPI2C peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + bool enableDoze; /*!< Whether master is enabled in doze mode. */ + bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ + bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ + lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ + uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + struct + { + bool enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; /*!< Host request options. */ +} lpi2c_master_config_t; + +/*! @brief LPI2C master data match configuration modes. */ +typedef enum _lpi2c_data_match_config_mode +{ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ + kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ + kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = + 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ + kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = + 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ + kLPI2C_1stWordAndM1EqualsM0AndM1 = + 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ + kLPI2C_AnyWordAndM1EqualsM0AndM1 = + 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ +} lpi2c_data_match_config_mode_t; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ + bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param base The LPI2C peripheral base address. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[6]; /*!< LPI2C command sequence. When all 6 command words are used: + Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs. + */ +typedef void (*lpi2c_master_isr_t)(uint32_t instance, void *handle); + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_SlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_SlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + /*! Errors to check for. */ + kLPI2C_SlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag +}; + +/*! @brief LPI2C slave address match options. */ +typedef enum _lpi2c_slave_address_match +{ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ +} lpi2c_slave_address_match_t; + +/*! + * @brief Structure with settings to initialize the LPI2C slave module. + * + * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_slave_config +{ + bool enableSlave; /*!< Enable slave mode. */ + uint8_t address0; /*!< Slave's 7-bit address. */ + uint8_t address1; /*!< Alternate slave 7-bit address. */ + lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ + bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ + bool filterEnable; /*!< Enable digital glitch filter. */ + bool enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; + bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ + bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to + disable. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to + disable. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ +} lpi2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. + When this event is set, the driver will no longer decide to reply to ack/nack. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the LPI2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern IRQn_Type const kLpi2cIrqs[]; + +/*! Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern void *s_lpi2cMasterHandle[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The LPI2C peripheral base address. + * @return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base); + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The LPI2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base); + +/*! + * @brief Configures LPI2C master data match feature. + * + * @param base The LPI2C peripheral base address. + * @param matchConfig Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the LPI2C master peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_MasterReset(LPI2C_Type *base) +{ + base->MCR = LPI2C_MCR_RST_MASK; + base->MCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as master. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as master. + */ +static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) +{ + base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C master status flags. + * + * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_master_flags + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPI2C master status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * _lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_MasterGetStatusFlags(). + * @see _lpi2c_master_flags. + */ +static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C master interrupt requests. + * + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of _lpi2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->MIER; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables LPI2C master DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) +{ + base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); +} + +/*! + * @brief Gets LPI2C master transmit data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Transmit Data Register address. + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MTDR; +} + +/*! + * @brief Gets LPI2C master receive data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Receive Data Register address. + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MRDR; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or + * greater than the FIFO size is truncated. + * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater + * than the FIFO size is truncated. + */ +static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) +{ + base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); +} + +/*! + * @brief Gets the current number of words in the LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * @param base The LPI2C peripheral base address. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) +{ + return ((base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * LPI2C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + return LPI2C_MasterStart(base, address, dir); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The LPI2C peripheral base address. + * @retval kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The LPI2C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param instance The LPI2C instance. + * @param lpi2cMasterHandle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a + * address0 member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * @param base The LPI2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base); + +/*! + * @brief Performs a software reset of the LPI2C slave peripheral. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_SlaveReset(LPI2C_Type *base) +{ + base->SCR = LPI2C_SCR_RST_MASK; + base->SCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as slave. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as slave. + */ +static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) +{ + base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); +} + +/*@}*/ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C slave status flags. + * + * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_slave_flags + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) +{ + return base->SSR; +} + +/*! + * @brief Clears the LPI2C status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_SlaveGetStatusFlags(). + * @see _lpi2c_slave_flags. + */ +static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->SSR = statusMask; +} + +/*@}*/ + +/*! @name Slave interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C slave interrupt requests. + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->SIER; +} + +/*@}*/ + +/*! @name Slave DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables the LPI2C slave peripheral DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. + * The address valid DMA request is shared with the receive data DMA request. + * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. + * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) +{ + base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | + LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); +} + +/*@}*/ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the slave mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) +{ + return ((base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. + * + * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This + * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration + * structure used to initialize the slave peripheral. + * + * @param base The LPI2C peripheral base address. + * @param ackOrNack Pass true for an ACK or false for a NAK. + */ +static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) +{ + base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); +} + +/*! + * @brief Enables or disables ACKSTALL. + * + * When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to + * a byte from the master. + * + * @param base The LPI2C peripheral base address. + * @param enable True will enable ACKSTALL,false will disable ACKSTALL. + */ +static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable) +{ + if (enable) + { + base->SCFGR1 |= LPI2C_SCFGR1_ACKSTALL_MASK; + } + else + { + base->SCFGR1 &= ~LPI2C_SCFGR1_ACKSTALL_MASK; + } +} + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) +{ + return base->SASR & LPI2C_SASR_RADDR_MASK; +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param[out] actualTxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param[out] actualRxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @retval kStatus_Success + * @retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param instance The LPI2C instance. + * @param lpi2cSlaveHandle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_LPI2C_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_edma.c new file mode 100644 index 0000000000..a49cf9fb19 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_edma.c @@ -0,0 +1,636 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c_edma.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpi2c_edma" +#endif + +/* @brief Mask to align an address to 32 bytes. */ +#define ALIGN_32_MASK (0x1fU) + +/* ! @brief LPI2C master fifo commands. */ +enum _lpi2c_master_fifo_cmd +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _lpi2c_transfer_states +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! + * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpi2c_master_isr_t` + */ +typedef union lpi2c_to_lpflexcomm_edma +{ + lpi2c_master_isr_t lpi2c_master_handler; + lpflexcomm_irq_handler_t lpflexcomm_handler; +} lpi2c_to_lpflexcomm_edma_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Prepares the command buffer with the sequence of commands needed to send the requested transaction. + * @param handle Master DMA driver handle. + * @return Number of command words. + */ +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); + +/*! + * @brief DMA completion callback. + * @param dmaHandle DMA channel handle for the channel that completed. + * @param userData User data associated with the channel handle. For this callback, the user data is the + * LPI2C DMA driver handle. + * @param isTransferDone Whether the DMA transfer has completed. + * @param tcds Number of TCDs that completed. + */ +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); + +/*! + * @brief LPI2C master edma transfer IRQ handle routine. + * + * This API handles the LPI2C bus error status and invoke callback if needed. + * + * @param base The LPI2C peripheral base address. + * @param lpi2cMasterEdmaHandle Pointer to the LPI2C master edma handle. + */ +static void LPI2C_MasterTransferEdmaHandleIRQ(uint32_t instance, void *lpi2cMasterEdmaHandle); +/******************************************************************************* + * Variables + ******************************************************************************/ + +static uint32_t lpi2c_edma_RecSetting = 0x02; + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + assert(rxDmaHandle != NULL); + assert(txDmaHandle != NULL); + + /* Look up instance number */ + uint32_t instance = LPI2C_GetInstance(base); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ + /* in order to make the transfer API code simpler. */ + handle->base = base; + handle->completionCallback = callback; + handle->userData = userData; + handle->rx = rxDmaHandle; + handle->tx = (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) > 0) ? txDmaHandle : rxDmaHandle; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpi2c_to_lpflexcomm_edma_t handler; + handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ; + + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C); + } + else + { + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set LPI2C_MasterTransferEdmaHandleIRQ as LPI2C DMA IRQ handler */ + s_lpi2cMasterIsr = LPI2C_MasterTransferEdmaHandleIRQ; + } + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(kLpi2cIrqs[instance]); + + /* Set DMA channel completion callbacks. */ + EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_SetCallback(handle->tx, LPI2C_MasterEDMACallback, handle); + } +} + +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; + + /* Handle no start option. */ + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag) != 0U) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(xfer->dataSize - 1U); + } + } + else + { + /* + * Initial direction depends on whether a subaddress was provided, and of course the actual + * data transfer direction. + */ + lpi2c_direction_t direction = (xfer->subaddressSize != 0U) ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (xfer->subaddressSize != 0U) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (0U != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)(xfer->subaddress >> (8U * subaddressRemaining)) & 0xffU; + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling because we have to issue a read command and maybe a repeated start. */ + if ((xfer->dataSize != 0U) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + + /* Read command. A single write to MTDR can issue read operation of 0xFFU + 1 byte of data at most, so when + the dataSize is larger than 0x100U, push multiple read commands to MTDR until dataSize is reached. */ + size_t tmpRxSize = xfer->dataSize; + while (tmpRxSize != 0U) + { + if (tmpRxSize > 256U) + { + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + } + } + + return cmdCount; +} + +/*! + * brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the a handle was created is invoked when the transaction has + * completed. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + status_t result; + + assert(handle != NULL); + assert(transfer != NULL); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Check transfer data size in read operation. */ + /* A single write to MTDR can issue read operation of 0xFFU + 1 byte of data at most, so when the dataSize is larger + than 0x100U, push multiple read commands to MTDR until dataSize is reached. LPI2C edma transfer uses linked + descriptor to transfer command and data, the command buffer is stored in handle. Allocate 4 command words to + carry read command which can cover nearly all use cases. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > (256U * 4U))) + { + return kStatus_InvalidArgument; + } + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result != kStatus_Success) + { + return result; + } + + /* We're now busy. */ + handle->isBusy = true; + + /* Disable LPI2C IRQ and DMA sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + LPI2C_MasterEnableDMA(base, false, false); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + uint32_t commandCount = LPI2C_GenerateCommands(handle); + + /* If the user is transmitting no data with no start or stop, then just go ahead and invoke the callback. */ + if ((0U == commandCount) && (transfer->dataSize == 0U)) + { + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + return kStatus_Success; + } + + /* Reset DMA channels. */ + EDMA_ResetChannel(handle->rx->base, handle->rx->channel); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_ResetChannel(handle->tx->base, handle->tx->channel); + } + + /* Get a 32-byte aligned TCD pointer. */ + edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); + + bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize != 0U); + bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize != 0U); + + edma_transfer_config_t transferConfig = {0}; + edma_tcd_t *linkTcd = NULL; + + /* Set up data transmit. */ + if (hasSendData) + { + uint32_t *srcAddr = (uint32_t *)transfer->data; + transferConfig.srcAddr = (uint32_t)srcAddr; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = (int16_t)sizeof(uint8_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = (uint8_t)transferConfig.minorLoopBytes; + + if (commandCount != 0U) + { + /* Create a software TCD, which will be chained after the commands. */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); + linkTcd = tcd; + } + else + { + /* User is only transmitting data with no required commands, so this transfer can stand alone. */ + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, (uint32_t)kEDMA_MajorInterruptEnable); + } + } + else if (hasReceiveData) + { + uint32_t *srcAddr = (uint32_t *)transfer->data; + /* Set up data receive. */ + transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); + transferConfig.destAddr = (uint32_t)srcAddr; + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = (int16_t)sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = (uint8_t)transferConfig.minorLoopBytes; + + if ((FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) || (0U == commandCount)) + { + /* We can put this receive transfer on its own DMA channel. */ + EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, (uint32_t)kEDMA_MajorInterruptEnable); + } + else + { + /* For shared rx/tx DMA requests, when there are commands, create a software TCD of + enabling rx dma and disabling tx dma, which will be chained onto the commands transfer, + and create another software TCD of transfering data and chain it onto the last TCD. + Notice that in this situation assume tx/rx uses same channel */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); + + transferConfig.srcAddr = (uint32_t)&lpi2c_edma_RecSetting; + transferConfig.destAddr = (uint32_t) & (base->MDER); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = (int16_t)sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); + transferConfig.majorLoopCounts = 1; + + edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_32_MASK)); + + EDMA_TcdReset(tcdSetRxClearTxDMA); + EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd); + linkTcd = tcdSetRxClearTxDMA; + } + } + else + { + /* No data to send */ + } + + if (hasSendData) + { + } + + /* Set up commands transfer. */ + if (commandCount != 0U) + { + transferConfig.srcAddr = (uint32_t)handle->commandBuffer; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.srcOffset = (int16_t)sizeof(uint16_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = commandCount; + + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); + } + + /* Start DMA transfer. */ + if (hasReceiveData || (0 == FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base))) + { + EDMA_StartTransfer(handle->rx); + } + + if ((hasSendData || (commandCount != 0U)) && (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0)) + { + EDMA_StartTransfer(handle->tx); + } + + /* Enable DMA in both directions. This actually kicks of the transfer. */ + LPI2C_MasterEnableDMA(base, true, true); + + /* Enable all LPI2C master interrupts */ + LPI2C_MasterEnableInterrupts(base, + (uint32_t)kLPI2C_MasterArbitrationLostFlag | (uint32_t)kLPI2C_MasterNackDetectFlag | + (uint32_t)kLPI2C_MasterPinLowTimeoutFlag | (uint32_t)kLPI2C_MasterFifoErrFlag); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint32_t remaining = handle->transfer.dataSize; + + /* If the DMA is still on a commands transfer that chains to the actual data transfer, */ + /* we do nothing and return the number of transferred bytes as zero. */ + if (EDMA_GetNextTCDAddress(handle->tx) == 0U) + { + if (handle->transfer.direction == kLPI2C_Write) + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); + } + else + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); + } + } + + *count = handle->transfer.dataSize - remaining; + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) +{ + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + return kStatus_LPI2C_Idle; + } + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Disable LPI2C interrupts. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* If master is still busy and has not send out stop signal yet. */ + if ((LPI2C_MasterGetStatusFlags(base) & + ((uint32_t)kLPI2C_MasterStopDetectFlag | (uint32_t)kLPI2C_MasterBusyFlag)) == (uint32_t)kLPI2C_MasterBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + base->MTDR = (uint32_t)kStopCmd; + } + + /* Reset handle. */ + handle->isBusy = false; + + return kStatus_Success; +} + +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) +{ + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; + + if (NULL == handle) + { + return; + } + + /* Check for errors. */ + status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); + + /* Done with this transaction. */ + handle->isBusy = false; + + if (0U == (handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag)) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = (uint32_t)kStopCmd; + } + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(handle->base, handle, result, handle->userData); + } +} + +static void LPI2C_MasterTransferEdmaHandleIRQ(uint32_t instance, void *lpi2cMasterEdmaHandle) +{ + assert(lpi2cMasterEdmaHandle != NULL); + assert(instance < ARRAY_SIZE(kLpi2cBases)); + LPI2C_Type *base = kLpi2cBases[instance]; + + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)lpi2cMasterEdmaHandle; + uint32_t status = LPI2C_MasterGetStatusFlags(base); + status_t result = kStatus_Success; + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Done with this transaction. */ + handle->isBusy = false; + + /* Disable LPI2C interrupts. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Check error status */ + if (0U != (status & (uint32_t)kLPI2C_MasterPinLowTimeoutFlag)) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterArbitrationLostFlag)) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterNackDetectFlag)) + { + result = kStatus_LPI2C_Nak; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear error status. */ + (void)LPI2C_MasterCheckAndClearError(base, status); + + /* Send stop flag if needed */ + if (0U == (handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag)) + { + status = LPI2C_MasterGetStatusFlags(base); + /* If bus is still busy and the master has not generate stop flag */ + if ((status & ((uint32_t)kLPI2C_MasterBusBusyFlag | (uint32_t)kLPI2C_MasterStopDetectFlag)) == + (uint32_t)kLPI2C_MasterBusBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = (uint32_t)kStopCmd; + } + } + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_edma.h new file mode 100644 index 0000000000..e17be77997 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_edma.h @@ -0,0 +1,158 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPI2C_EDMA_H_ +#define FSL_LPI2C_EDMA_H_ + +#include "fsl_lpi2c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C EDMA driver version. */ +#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t; + +/*! + * @brief Master DMA completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterCreateEDMAHandle(). + * + * @param base The LPI2C peripheral base address. + * @param handle Handle associated with the completed transfer. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Driver handle for master DMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_edma_handle +{ + LPI2C_Type *base; /*!< LPI2C base pointer. */ + bool isBusy; /*!< Transfer state machine current state. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint16_t commandBuffer[10]; /*!< LPI2C command sequence. When all 10 command words are used: + Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words] */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_edma_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rx; /*!< Handle for receive DMA channel. */ + edma_handle_t *tx; /*!< Handle for transmit DMA channel. */ + edma_tcd_t tcds[3]; /*!< Software TCD. Three are allocated to provide enough room to align to 32-bytes. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*@{*/ + +/*! + * @brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_LPI2C_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_freertos.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_freertos.c new file mode 100644 index 0000000000..818c23801b --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_freertos.c @@ -0,0 +1,122 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpi2c_freertos" +#endif + +static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData) +{ + lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData; + BaseType_t reschedule = pdFALSE; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes LPI2C. + * + * This function initializes the LPI2C module and the related RTOS context. + * + * param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the LPI2C instance to initialize. + * param masterConfig Configuration structure to set-up LPI2C in master mode. + * param srcClock_Hz Frequency of input clock of the LPI2C module. + * return status of the operation. + */ +status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle, + LPI2C_Type *base, + const lpi2c_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(lpi2c_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->semaphore = xSemaphoreCreateBinary(); + if (handle->semaphore == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + LPI2C_MasterInit(handle->base, masterConfig, srcClock_Hz); + LPI2C_MasterTransferCreateHandle(base, &handle->drv_handle, LPI2C_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the LPI2C. + * + * This function deinitializes the LPI2C module and the related RTOS context. + * + * param handle The RTOS LPI2C handle. + */ +status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle) +{ + LPI2C_MasterDeinit(handle->base); + vSemaphoreDelete(handle->semaphore); + vSemaphoreDelete(handle->mutex); + return kStatus_Success; +} + +/*! + * brief Performs LPI2C transfer. + * + * This function performs an LPI2C transfer according to data given in the transfer structure. + * + * param handle The RTOS LPI2C handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPI2C_Busy; + } + + status = LPI2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY); + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Return status captured by callback function */ + return handle->async_status; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_freertos.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_freertos.h new file mode 100644 index 0000000000..ea4e77d3c8 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpi2c_freertos.h @@ -0,0 +1,107 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPI2C_FREERTOS_H__ +#define FSL_LPI2C_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_lpi2c.h" + +/*! + * @addtogroup lpi2c_freertos_driver LPI2C FreeRTOS Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C FreeRTOS driver version 2.0.0. */ +#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief LPI2C FreeRTOS handle */ +typedef struct _lpi2c_rtos_handle +{ + LPI2C_Type *base; /*!< LPI2C base address */ + lpi2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; /*!< Transactional state of the underlying driver */ + SemaphoreHandle_t mutex; /*!< A mutex to lock the handle during a transfer */ + SemaphoreHandle_t semaphore; /*!< A semaphore to notify and unblock task when the transfer ends */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ + StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */ +#endif +} lpi2c_rtos_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPI2C RTOS Operation + * @{ + */ + +/*! + * @brief Initializes LPI2C. + * + * This function initializes the LPI2C module and the related RTOS context. + * + * @param handle The RTOS LPI2C handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the LPI2C instance to initialize. + * @param masterConfig Configuration structure to set-up LPI2C in master mode. + * @param srcClock_Hz Frequency of input clock of the LPI2C module. + * @return status of the operation. + */ +status_t LPI2C_RTOS_Init(lpi2c_rtos_handle_t *handle, + LPI2C_Type *base, + const lpi2c_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the LPI2C. + * + * This function deinitializes the LPI2C module and the related RTOS context. + * + * @param handle The RTOS LPI2C handle. + */ +status_t LPI2C_RTOS_Deinit(lpi2c_rtos_handle_t *handle); + +/*! + * @brief Performs LPI2C transfer. + * + * This function performs an LPI2C transfer according to data given in the transfer structure. + * + * @param handle The RTOS LPI2C handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t LPI2C_RTOS_Transfer(lpi2c_rtos_handle_t *handle, lpi2c_master_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_LPI2C_FREERTOS_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi.c new file mode 100644 index 0000000000..09ef87cba6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi.c @@ -0,0 +1,2297 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpspi" +#endif + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum _lpspi_default_watermarks +{ + kLpspiDefaultTxWatermark = 0, + kLpspiDefaultRxWatermark = 0, +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*lpspi_master_isr_t)(uint32_t instance, lpspi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpspi_slave_isr_t)(uint32_t instance, lpspi_slave_handle_t *handle); + +/*! + * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpuart_irq_handler_t` + */ +typedef union lpspi_to_lpflexcomm +{ + lpspi_master_isr_t lpspi_master_handler; + lpspi_slave_isr_t lpspi_slave_handler; + lpflexcomm_irq_handler_t lpflexcomm_handler; +} lpspi_to_lpflexcomm_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Configures the LPSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and + * configures the Pcs signal to operate with the desired characteristic. + * + * @param base LPSPI peripheral address. + * @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to + * apply the active high or active low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of + * type lpspi_pcs_polarity_config_t. + */ +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh); + +/*! + * @brief Combine the write data for 1 byte to 4 bytes. + * This is not a public API. + */ +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap); + +/*! + * @brief Separate the read data for 1 byte to 4 bytes. + * This is not a public API. + */ +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint8_t bytesEachRead, bool isByteSwap); + +/*! + * @brief Wait for tx FIFO to be empty. + * This is not a public API. + * @param base LPSPI peripheral address. + * @return true for the tx FIFO is ready, false is not. + */ +static bool LPSPI_TxFifoReady(LPSPI_Type *base); + +/*! + * @brief Master fill up the TX FIFO with data. + * This is not a public API. + */ +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Master finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Slave fill up the TX FIFO with data. + * This is not a public API. + */ +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief Slave finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128}; + +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi IRQ number for each instance. */ +static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to lpspi clocks for each instance. */ +static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS; + +#if defined(LPSPI_PERIPH_CLOCKS) +static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to lpspi handles for each instance. */ +static void *s_lpspiHandle[ARRAY_SIZE(s_lpspiBases)]; + +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static lpspi_master_isr_t s_lpspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpspi_slave_isr_t s_lpspiSlaveIsr; + +/********************************************************************************************************************** + * Code + *********************************************************************************************************************/ + +/*! + * brief Get the LPSPI instance from peripheral base address. + * + * param base LPSPI peripheral base address. + * return LPSPI instance. + */ +uint32_t LPSPI_GetInstance(LPSPI_Type *base) +{ + uint8_t instance = 0; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) + { + if (s_lpspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpspiBases)); + + return instance; +} + +/*! + * brief Set up the dummy data. + * + * param base LPSPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = LPSPI_GetInstance(base); + g_lpspiDummyData[instance] = dummyData; +} + +/*! + * brief Initializes the LPSPI master. + * + * param base LPSPI peripheral address. + * param masterConfig Pointer to structure lpspi_master_config_t. + * param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig != NULL); + + uint32_t tcrPrescaleValue = 0; + uint32_t instance = LPSPI_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPSPI mode */ + status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + /* Enable LPSPI clock */ + (void)CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + /* Disable LPSPI first */ + LPSPI_Enable(base, false); + + /* Set LPSPI to master */ + LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); + + /* Set specific PCS to active high or low */ + LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + /* Set Configuration Register 1 related setting.*/ + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK | + LPSPI_CFGR1_SAMPLE_MASK | LPSPI_CFGR1_PCSCFG_MASK )) | + LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | + LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay )| + LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc); + + /* Set baudrate and delay times*/ + (void)LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue); + + /* Set default watermarks */ + LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark); + + /* Set Transmit Command Register*/ + base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | + LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1U) | + LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs); + + LPSPI_Enable(base, true); + + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz); + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz); + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, + srcClock_Hz); + + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); +} + +/*! + * brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * endcode + * param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->baudRate = 500000; + masterConfig->bitsPerFrame = 8; + masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; + masterConfig->direction = kLPSPI_MsbFirst; + + masterConfig->pcsToSckDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->lastSckToPcsDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->betweenTransferDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + + masterConfig->whichPcs = kLPSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + masterConfig->pcsFunc = kLPSPI_PcsAsCs; + + masterConfig->pinCfg = kLPSPI_SdiInSdoOut; + masterConfig->dataOutConfig = kLpspiDataOutRetained; + + masterConfig->enableInputDelay = false; +} + +/*! + * brief LPSPI slave configuration. + * + * param base LPSPI peripheral address. + * param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + uint32_t instance = LPSPI_GetInstance(base); + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPSPI mode */ + status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI); + if (kStatus_Success != status) + { + assert(false); + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + + } + else + { + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + /* Enable LPSPI clock */ + (void)CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + } + + LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); + + LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); + + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | + LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); + + LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark); + + base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | + LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1U); + + /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */ + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); + + LPSPI_Enable(base, true); +} + +/*! + * brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * endcode + * param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ + slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ + slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ + slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ + + slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ + slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ + + slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; + slaveConfig->dataOutConfig = kLpspiDataOutRetained; +} + +/*! + * brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base) +{ + /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ + base->CR |= LPSPI_CR_RST_MASK; + + /* Software reset doesn't reset the CR, so manual reset the FIFOs */ + base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; + + /* Master logic is not reset and module is disabled.*/ + base->CR = 0x00U; +} + +/*! + * brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base) +{ + + uint32_t instance = LPSPI_GetInstance(base); + + /* Reset to default value */ + LPSPI_Reset(base); + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + LP_FLEXCOMM_Deinit(instance); + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable LPSPI clock */ + (void)CLOCK_DisableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPSPI_GetInstance(base)); +#endif +} + +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t cfgr1Value = 0; + /* Clear the PCS polarity bit */ + cfgr1Value = base->CFGR1 & ~(1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); + + /* Configure the PCS polarity bit according to the activeLowOrHigh setting */ + base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); +} + +/*! + * brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param baudRate_Bps The desired baud rate in bits per second. + * param srcClock_Hz Module source input clock in Hertz. + * param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue) +{ + assert(tcrPrescaleValue != NULL); + + /* For master mode configuration only, if slave mode detected, return 0. + * Also, the LPSPI module needs to be disabled first, if enabled, return 0 + */ + if ((!LPSPI_IsMaster(base)) || ((base->CR & LPSPI_CR_MEN_MASK) != 0U)) + { + return 0U; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t desiredBaudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + + /* Set to maximum divisor value bit settings so that if baud rate passed in is less + * than the minimum possible baud rate, then the SPI will be configured to the lowest + * possible baud rate + */ + bestPrescaler = 7; + bestScaler = 255; + + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0U; prescaler < 8U; prescaler++) + { + if (min_diff == 0U) + { + break; + } + for (scaler = 0U; scaler < 256U; scaler++) + { + if (min_diff == 0U) + { + break; + } + realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); + + /* calculate the baud rate difference based on the conditional statement + * that states that the calculated baud rate must not exceed the desired baud rate + */ + if (desiredBaudrate >= realBaudrate) + { + diff = desiredBaudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + } + } + } + } + + /* Write the best baud rate scalar to the CCR. + * Note, no need to check for error since we've already checked to make sure the module is + * disabled and in master mode. Also, there is a limit on the maximum divider so we will not + * exceed this. + */ +#if defined(FSL_FEATURE_LPSPI_HAS_CCR1) && FSL_FEATURE_LPSPI_HAS_CCR1 + /* When CCR1 is present, the CCR[DBT] and CCR[SCKDIV] is write only, all read will return 0 + The real DBT and SCKDIV can be obtained in CCR1, CCR[DBT]=CCR1[SCKSCK] and CCR[SCKDIV]=CCR1[SCKHLD]+CCR1[SCKSET] + So when changing either CCR[DBT] or CCR[SCKDIV] make sure the other value is not overwritten by 0 */ + base->CCR = base->CCR | LPSPI_CCR_DBT((base->CCR1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT) | + LPSPI_CCR_SCKDIV(bestScaler); +#else + base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); +#endif /* FSL_FEATURE_LPSPI_HAS_CCR1 */ + + /* return the best prescaler value for user to use later */ + *tcrPrescaleValue = bestPrescaler; + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +/*! + * brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param scaler The 8-bit delay value 0x00 to 0xFF (255). + * param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) +{ + /*These settings are only relevant in master mode */ +#if defined(FSL_FEATURE_LPSPI_HAS_CCR1) && FSL_FEATURE_LPSPI_HAS_CCR1 + /* When CCR1 is present, the CCR[DBT] and CCR[SCKDIV] is write only, all read will return 0 + The real DBT and SCKDIV can be obtained in CCR1, CCR[DBT]=CCR1[SCKSCK] and CCR[SCKDIV]=CCR1[SCKHLD]+CCR1[SCKSET] + So when changing either CCR[DBT] or CCR[SCKDIV] make sure the other value is not overwritten by 0 */ + uint32_t dbt = (base->CCR1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT; + uint32_t sckdiv = (base->CCR1 & LPSPI_CCR1_SCKHLD_MASK) >> LPSPI_CCR1_SCKHLD_SHIFT; + sckdiv += (base->CCR1 & LPSPI_CCR1_SCKSET_MASK) >> LPSPI_CCR1_SCKSET_SHIFT; + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler) | LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_SCKDIV(sckdiv); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler) | LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_SCKDIV(sckdiv); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = base->CCR | LPSPI_CCR_DBT(scaler) | LPSPI_CCR_SCKDIV(sckdiv); +#else + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); +#endif /* FSL_FEATURE_LPSPI_HAS_CCR1 */ + break; + default: + assert(false); + break; + } +} + +/*! + * brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * param base LPSPI peripheral address. + * param delayTimeInNanoSec The desired delay value in nano-seconds. + * param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * param srcClock_Hz Module source input clock in Hertz. + * return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz) +{ + uint64_t realDelay, bestDelay; + uint32_t scaler, bestScaler; + uint32_t diff, min_diff; + uint64_t initialDelayNanoSec; + uint32_t clockDividedPrescaler; + + /* For delay between transfer, an additional scaler value is needed */ + uint32_t additionalScaler = 0; + + /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between + * transfers.*/ + clockDividedPrescaler = + srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT]; + + /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/ + min_diff = 0xFFFFFFFFU; + + /* Initialize scaler to max value to generate the max delay */ + bestScaler = 0xFFU; + + /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as + * the delay divisors are slightly different based on which delay we are configuring. + */ + if (whichDelay == kLPSPI_BetweenTransfer) + { + /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of + calculated values (uint64_t), we need to break up the calculation into several steps to ensure + accurate calculated results + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec *= 2U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 1U; + } + else + { + /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated + values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated + results. + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 0U; + } + + /* If the initial, default delay is already greater than the desired delay, then + * set the delay to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + LPSPI_MasterSetDelayScaler(base, 0, whichDelay); + return (uint32_t)initialDelayNanoSec; + } + + /* If min_diff = 0, the exit for loop */ + for (scaler = 0U; scaler < 256U; scaler++) + { + if (min_diff == 0U) + { + break; + } + /* Calculate the real delay value as we cycle through the scaler values. + Due to large size of calculated values (uint64_t), we need to break up the + calculation into several steps to ensure accurate calculated results + */ + realDelay = 1000000000U; + realDelay *= ((uint64_t)scaler + 1UL + (uint64_t)additionalScaler); + realDelay /= clockDividedPrescaler; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = (uint32_t)(realDelay - (uint64_t)delayTimeInNanoSec); + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + + /* write the best scaler value for the delay */ + LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); + + /* return the actual calculated delay value (in ns) */ + return (uint32_t)bestDelay; +} + +/*Transactional APIs -- Master*/ + +/*! + * brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_master_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + uint32_t instance = LPSPI_GetInstance(base); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->callback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpspi_to_lpflexcomm_t handler; + handler.lpspi_master_handler = LPSPI_MasterTransferHandleIRQ; + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + } + else + { + s_lpspiHandle[instance] = handle; + + /* Set irq handler. */ + s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; + } +} + +/*! + * brief Check the argument for transfer . + * + * param base LPSPI peripheral address. + * param transfer the transfer struct to be used. + * param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer + * return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma) +{ + assert(transfer != NULL); + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U; + uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0U) + { + return false; + } + + /* If both send buffer and receive buffer is null */ + if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData))) + { + return false; + } + + /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 . + *For bytesPerFrame greater than 4 situation: + *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 , + *otherwise , the transfer data size can be integer multiples of bytesPerFrame. + */ + if (bytesPerFrame <= 4U) + { + if ((transfer->dataSize % bytesPerFrame) != 0U) + { + return false; + } + } + else + { + if ((bytesPerFrame % 4U) != 0U) + { + if (transfer->dataSize != bytesPerFrame) + { + return false; + } + } + else + { + if ((transfer->dataSize % bytesPerFrame) != 0U) + { + return false; + } + } + } + + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + /* The 3-wire mode can't send and receive data at the same time. */ + if ((transfer->txData != NULL) && (transfer->rxData != NULL)) + { + return false; + } + if (NULL == transfer->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + } + + if (isEdma && ((bytesPerFrame % 4U) == 3U)) + { + return false; + } + + return true; +} + +/*! + * brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) +{ + assert(transfer != NULL); + + /* Check that LPSPI is not busy.*/ + if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ModuleBusyFlag) != 0U) + { + return kStatus_LPSPI_Busy; + } + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + + /* Variables */ + bool isTxMask = false; + bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + uint8_t bytesEachWrite; + uint8_t bytesEachRead; + uint8_t *txData = transfer->txData; + uint8_t *rxData = transfer->rxData; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t readData = 0U; + uint32_t txRemainingByteCount = transfer->dataSize; + uint32_t rxRemainingByteCount = transfer->dataSize; + uint32_t wordToSend = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + uint32_t fifoSize = LPSPI_GetRxFifoSize(base); + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + /* No need to configure PCS continous if the transfer byte count is smaller than frame size */ + bool isPcsContinuous = (((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U) && + (bytesPerFrame < transfer->dataSize)); + uint32_t rxFifoMaxBytes = MIN(bytesPerFrame, 4U) * fifoSize; + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t width = (transfer->configFlags & LPSPI_MASTER_WIDTH_MASK) >> LPSPI_MASTER_WIDTH_SHIFT; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + /* Mask tx data in half duplex mode */ + if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) && + (txData == NULL)) + { + isTxMask = true; + } + + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + LPSPI_Enable(base, true); + + /* Configure transfer control register. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_PCS(whichPcs) | LPSPI_TCR_WIDTH(width); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* PCS should be configured separately from the other bits, otherwise it will not take effect. */ + base->TCR |= LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(isPcsContinuous) | LPSPI_TCR_RXMSK(NULL == rxData); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + if (bytesPerFrame <= 4U) + { + bytesEachWrite = (uint8_t)bytesPerFrame; + bytesEachRead = (uint8_t)bytesPerFrame; + } + else + { + bytesEachWrite = 4U; + bytesEachRead = 4U; + } + + /*Write the TX data until txRemainingByteCount is equal to 0 */ + while (txRemainingByteCount > 0U) + { + if (txRemainingByteCount < bytesEachWrite) + { + bytesEachWrite = (uint8_t)txRemainingByteCount; + } + + /*Wait until TX FIFO is not full*/ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetTxFifoCount(base) == fifoSize) && (--waitTimes != 0U)) +#else + while (LPSPI_GetTxFifoCount(base) == fifoSize) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + + /* To prevent rxfifo overflow, ensure transmitting and receiving are executed in parallel */ + if (((NULL == rxData) || (rxRemainingByteCount - txRemainingByteCount) < rxFifoMaxBytes)) + { + if (isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared + by hardware every time when TCR[FRAMESZ] bit of data is transfered. + In this case TCR[TXMSK] should be set to initiate each transfer. */ + base->TCR |= LPSPI_TCR_TXMSK_MASK; + if (isPcsContinuous && (txRemainingByteCount == bytesPerFrame)) + { + /* For the last piece of frame size of data, if is PCS continous mode(TCR[CONT]), TCR[CONTC] should + * be cleared to de-assert the PCS. Be sure to clear the TXMSK as well otherwise another FRAMESZ + * of data will be received. */ + base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK); + } + txRemainingByteCount -= bytesPerFrame; + } + else + { + if (txData != NULL) + { + wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); + txData += bytesEachWrite; + } + /* Otherwise push data to tx FIFO to initiate transfer */ + LPSPI_WriteData(base, wordToSend); + txRemainingByteCount -= bytesEachWrite; + } + } + + /* Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun. */ + if ((rxData != NULL) && (rxRemainingByteCount != 0U)) + { + /* To ensure parallel execution in 3-wire mode, after writting 1 to TXMSK to generate clock of + bytesPerFrame's data wait until bytesPerFrame's data is received. */ + while (isTxMask && (LPSPI_GetRxFifoCount(base) == 0U)) + { + } +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetRxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while (LPSPI_GetRxFifoCount(base) != 0U) +#endif + { + readData = LPSPI_ReadData(base); + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = (uint8_t)rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + } + } + + if (isPcsContinuous && !isTxMask) + { + /* In PCS continous mode(TCR[CONT]), after write all the data in TX FIFO, TCR[CONTC] and TCR[CONT] should be + cleared to de-assert the PCS. Note that TCR register also use the TX FIFO. Also CONTC should be cleared when + tx is not masked, otherwise written to TCR register with TXMSK bit wet will initiate a new transfer. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetTxFifoCount(base) == fifoSize) && (--waitTimes != 0U)) +#else + while (LPSPI_GetTxFifoCount(base) == fifoSize) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK)); + } + + /*Read out the RX data in FIFO*/ + if (rxData != NULL) + { + while (rxRemainingByteCount > 0U) + { +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetRxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while (LPSPI_GetRxFifoCount(base) != 0U) +#endif + { + readData = LPSPI_ReadData(base); + + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = (uint8_t)rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + } + } + + /* Wait for transfer complete flag, that is the PCS is re-asserted. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) == 0U) && (--waitTimes != 0U)) +#else + while ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) == 0U) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_LPSPI_Timeout; + } +#endif + + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + /* Flush FIFO, clear status, disable all the interrupts. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + /* Variables */ + bool isRxMask = false; + handle->isTxMask = false; + uint8_t txWatermark; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t tmpTimes; + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeTcrInIsr = false; + handle->bytesPerFrame = (uint16_t)((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + /* No need to configure PCS continous if the transfer byte count is smaller than frame size */ + bool isPcsContinuous = (((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U) && + (transfer->dataSize > handle->bytesPerFrame)); + handle->writeRegRemainingTimes = + (transfer->dataSize / (uint32_t)handle->bytesPerFrame) * (((uint32_t)handle->bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isPcsContinuous = isPcsContinuous; + handle->isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (handle->bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)handle->bytesPerFrame; + handle->bytesEachRead = (uint8_t)handle->bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + } + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + if (handle->fifoSize > 1U) + { + txWatermark = 1U; + handle->rxWatermark = handle->fifoSize - 2U; + } + else + { + txWatermark = 0U; + handle->rxWatermark = 0U; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* If there is no rxData, mask the receive data so that receive data is not stored in receive FIFO. */ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0; + } + + /* Mask tx data in half duplex mode since the tx/rx share the same pin, so that the data received from slave is not + * interfered. */ + if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) && + (handle->txData == NULL)) + { + handle->isTxMask = true; + } + + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* Configure transfer control register. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_PCS(whichPcs); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* PCS should be configured separately from the other bits, otherwise it will not take effect. */ + base->TCR |= LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(isPcsContinuous) | LPSPI_TCR_RXMSK(isRxMask); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + (void)EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + if (handle->isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared by + hardware every time when TCR[FRAMESZ] bit of data is transfered. In this case TCR[TXMSK] should be set to + initiate each transfer. */ + + base->TCR |= LPSPI_TCR_TXMSK_MASK; + handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame; + } + else + { + /* Fill up the TX data in FIFO to initiate transfer */ + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData != NULL) + { + if (handle->isTxMask) + { + /* if tx data is masked, transfer is initiated by writing 1 to TCR[TXMSK] and TCR[FRMESZ] bits of data is + read. If rx water mark is set larger than TCR[FRMESZ], rx interrupt will not be generated. Lower the rx + water mark setting */ + if ((handle->bytesPerFrame / 4U) < (uint16_t)handle->rxWatermark) + { + handle->rxWatermark = + (uint8_t)(handle->bytesPerFrame / 4U) > 0U ? (uint8_t)(handle->bytesPerFrame / 4U - 1U) : 0U; + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->rxWatermark); + } + } + else + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise + *there is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + tmpTimes = handle->readRegRemainingTimes; + if (tmpTimes <= handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(tmpTimes - 1U); + } + } + + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t wordToSend = 0; + uint8_t fifoSize = handle->fifoSize; + uint32_t writeRegRemainingTimes = handle->writeRegRemainingTimes; + uint32_t readRegRemainingTimes = handle->readRegRemainingTimes; + size_t txRemainingByteCount = handle->txRemainingByteCount; + uint8_t bytesEachWrite = handle->bytesEachWrite; + bool isByteSwap = handle->isByteSwap; + + /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth + * and that the number of TX FIFO entries does not exceed the FIFO depth. + * But no need to make the protection if there is no rxData. + */ + while ((LPSPI_GetTxFifoCount(base) < fifoSize) && + (((readRegRemainingTimes - writeRegRemainingTimes) < (uint32_t)fifoSize) || (handle->rxData == NULL))) + { + if (txRemainingByteCount < (size_t)bytesEachWrite) + { + handle->bytesEachWrite = (uint8_t)txRemainingByteCount; + bytesEachWrite = handle->bytesEachWrite; + } + + if (handle->txData != NULL) + { + wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap); + handle->txData += bytesEachWrite; + } + else + { + wordToSend = handle->txBuffIfNull; + } + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + /*Decrease the write TX register times.*/ + --handle->writeRegRemainingTimes; + writeRegRemainingTimes = handle->writeRegRemainingTimes; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= (size_t)bytesEachWrite; + txRemainingByteCount = handle->txRemainingByteCount; + + if (handle->txRemainingByteCount == 0U) + { + /* If PCS is continuous, update TCR to de-assert PCS */ + if (handle->isPcsContinuous) + { + /* Only write to the TCR if the FIFO has room */ + if (LPSPI_GetTxFifoCount(base) < fifoSize) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + /* Else, set a global flag to tell the ISR to do write to the TCR */ + else + { + handle->writeTcrInIsr = true; + } + } + break; + } + } +} + +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + handle->state = (uint8_t)kLPSPI_Idle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_Success, handle->userData); + } +} + +/*! + * brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData != NULL) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + LPSPI_Reset(base); + + handle->state = (uint8_t)kLPSPI_Idle; + handle->txRemainingByteCount = 0; + handle->rxRemainingByteCount = 0; +} + +/*! + * brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * param instance LPSPI instance. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(uint32_t instance, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + assert(instance < ARRAY_SIZE(s_lpspiBases)); + LPSPI_Type *base = s_lpspiBases[instance]; + uint32_t readData; + uint8_t bytesEachRead = handle->bytesEachRead; + bool isByteSwap = handle->isByteSwap; + uint32_t readRegRemainingTimes = handle->readRegRemainingTimes; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount != 0U) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts based on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + + while ((LPSPI_GetRxFifoCount(base) != 0U) && (handle->rxRemainingByteCount != 0U)) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + readRegRemainingTimes = handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < (size_t)bytesEachRead) + { + handle->bytesEachRead = (uint8_t)(handle->rxRemainingByteCount); + bytesEachRead = handle->bytesEachRead; + } + + LPSPI_SeparateReadData(handle->rxData, readData, bytesEachRead, isByteSwap); + handle->rxData += bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= (size_t)bytesEachRead; + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (handle->rxRemainingByteCount != 0U) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((readRegRemainingTimes > 1U) ? (readRegRemainingTimes - 1U) : (0U)); + } + } + + if (handle->txRemainingByteCount != 0U) + { + if (handle->isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared by + hardware every time when TCR[FRAMESZ] bit of data is transfered. + In this case TCR[TXMSK] should be set to initiate each transfer. */ + base->TCR |= LPSPI_TCR_TXMSK_MASK; + if ((handle->txRemainingByteCount == (uint32_t)handle->bytesPerFrame) && (handle->isPcsContinuous)) + { + /* For the last piece of frame size of data, if is PCS continous mode(TCR[CONT]), TCR[CONTC] should + * be cleared to de-assert the PCS. Be sure to clear the TXMSK as well otherwise another FRAMESZ + * of data will be received. */ + base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK); + } + handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame; + } + else + { + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + } + else + { + if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) + { + if ((handle->isPcsContinuous) && (handle->writeTcrInIsr) && (!handle->isTxMask)) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + } + } + + if ((handle->txRemainingByteCount == 0U) && (handle->rxRemainingByteCount == 0U) && (!handle->writeTcrInIsr)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + if (handle->rxData == NULL) + { + if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) != 0U) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_TransferCompleteFlag); + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TransferCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + } +} + +/*Transactional APIs -- Slave*/ +/*! + * brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_slave_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + /* Get instance from peripheral base address. */ + uint32_t instance = LPSPI_GetInstance(base); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->callback = callback; + handle->userData = userData; + + if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U) + { + lpspi_to_lpflexcomm_t handler; + handler.lpspi_slave_handler = LPSPI_SlaveTransferHandleIRQ; + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI); + } + else + { + s_lpspiHandle[instance] = handle; + + /* Set irq handler. */ + s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; + } +} + +/*! + * brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + /* Flush FIFO, clear status, disable all the inerrupts. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + /* Variables */ + bool isRxMask = false; + bool isTxMask = false; + uint8_t txWatermark; + uint32_t readRegRemainingTimes; + uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_SlaveByteSwap) != 0U); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + } + /* Set proper RX and TX watermarks to reduce the ISR response times. */ + if (handle->fifoSize > 1U) + { + txWatermark = 1U; + handle->rxWatermark = handle->fifoSize - 2U; + } + else + { + txWatermark = 0U; + handle->rxWatermark = 0U; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* If there is no rxData, mask the receive data so that receive data is not stored in receive FIFO. */ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0U; + } + /* If there is no txData, mask the transmit data so that no data is loaded from transmit FIFO and output pin + * is tristated. */ + if (handle->txData == NULL) + { + isTxMask = true; + handle->txRemainingByteCount = 0U; + } + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + (void)EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + if (!LPSPI_TxFifoReady(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* Fill up the TX data in FIFO */ + if (handle->txData != NULL) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData != NULL) + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + readRegRemainingTimes = handle->readRegRemainingTimes; + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(readRegRemainingTimes - 1U); + } + + /* RX request and FIFO overflow request enable */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable | (uint32_t)kLPSPI_ReceiveErrorInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable); + } + + if (handle->txData != NULL) + { + /* TX FIFO underflow request enable */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TransmitErrorInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t wordToSend = 0U; + uint8_t bytesEachWrite = handle->bytesEachWrite; + bool isByteSwap = handle->isByteSwap; + + while (LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) + { + if (handle->txRemainingByteCount < (size_t)bytesEachWrite) + { + handle->bytesEachWrite = (uint8_t)handle->txRemainingByteCount; + bytesEachWrite = handle->bytesEachWrite; + } + + wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap); + handle->txData += bytesEachWrite; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= (size_t)bytesEachWrite; + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + if (handle->txRemainingByteCount == 0U) + { + break; + } + } +} + +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + if (handle->state == (uint8_t)kLPSPI_Error) + { + status = kStatus_LPSPI_Error; + } + else + { + status = kStatus_Success; + } + + handle->state = (uint8_t)kLPSPI_Idle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, status, handle->userData); + } +} + +/*! + * brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData != NULL) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + + LPSPI_Reset(base); + + handle->state = (uint8_t)kLPSPI_Idle; + handle->txRemainingByteCount = 0U; + handle->rxRemainingByteCount = 0U; +} + +/*! + * brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * param instance LPSPI instance index. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + assert(instance < ARRAY_SIZE(s_lpspiBases)); + LPSPI_Type *base = s_lpspiBases[instance]; + uint32_t readData; /* variable to store word read from RX FIFO */ + uint8_t bytesEachRead = handle->bytesEachRead; + bool isByteSwap = handle->isByteSwap; + uint32_t readRegRemainingTimes; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount > 0U) + { + while (LPSPI_GetRxFifoCount(base) != 0U) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < (size_t)bytesEachRead) + { + handle->bytesEachRead = (uint8_t)handle->rxRemainingByteCount; + bytesEachRead = handle->bytesEachRead; + } + + LPSPI_SeparateReadData(handle->rxData, readData, bytesEachRead, isByteSwap); + handle->rxData += bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= (size_t)bytesEachRead; + + if ((handle->txRemainingByteCount > 0U) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + if (handle->rxRemainingByteCount == 0U) + { + break; + } + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + readRegRemainingTimes = handle->readRegRemainingTimes; + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((readRegRemainingTimes > 1U) ? (readRegRemainingTimes - 1U) : (0U)); + } + } + if ((handle->rxData == NULL) && (handle->txRemainingByteCount != 0U) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + if ((handle->txRemainingByteCount == 0U) && (handle->rxRemainingByteCount == 0U)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/ + if (handle->rxData == NULL) + { + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_FrameCompleteFlag) != 0U) && + (LPSPI_GetTxFifoCount(base) == 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_FrameCompleteFlag); + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + else + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_FrameCompleteFlag); + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_FrameCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransmitErrorFlag) != 0U) && + ((base->IER & LPSPI_IER_TEIE_MASK) != 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_TransmitErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData != NULL) + { + handle->state = (uint8_t)kLPSPI_Error; + } + handle->errorCount++; + /* ERR051588: Clear FIFO after underrun occurs */ + LPSPI_FlushFifo(base, true, false); + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ReceiveErrorFlag) != 0U) && + ((base->IER & LPSPI_IER_REIE_MASK) != 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_ReceiveErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData != NULL) + { + handle->state = (uint8_t)kLPSPI_Error; + } + handle->errorCount++; + } +} + +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap) +{ + assert(txData != NULL); + + uint32_t wordToSend = 0U; + + switch (bytesEachWrite) + { + case 1: + wordToSend = *txData; + ++txData; + break; + + case 2: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + + break; + + case 3: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + case 4: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 24U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 24U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + default: + assert(false); + break; + } + return wordToSend; +} + +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint8_t bytesEachRead, bool isByteSwap) +{ + assert(rxData != NULL); + + switch (bytesEachRead) + { + case 1: + *rxData = (uint8_t)readData; + ++rxData; + break; + + case 2: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + case 3: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + case 4: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 24); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + default: + assert(false); + break; + } +} + +static bool LPSPI_TxFifoReady(LPSPI_Type *base) +{ +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while (((uint8_t)LPSPI_GetTxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while ((uint8_t)LPSPI_GetTxFifoCount(base) != 0U) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + return true; +} + +void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance); +void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance) +{ + assert(s_lpspiHandle[instance] != NULL); + if (LPSPI_IsMaster(base)) + { + s_lpspiMasterIsr(instance, (lpspi_master_handle_t *)s_lpspiHandle[instance]); + } + else + { + s_lpspiSlaveIsr(instance, (lpspi_slave_handle_t *)s_lpspiHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(LPSPI14) +void LPSPI14_DriverIRQHandler(void); +void LPSPI14_DriverIRQHandler(void) +{ + LPSPI_CommonIRQHandler(LPSPI14, 14); +} +#endif + +#if defined(LPSPI16) +void LPSPI16_DriverIRQHandler(void); +void LPSPI16_DriverIRQHandler(void) +{ + LPSPI_CommonIRQHandler(LPSPI16, 16); +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi.h new file mode 100644 index 0000000000..2b016e983c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi.h @@ -0,0 +1,1175 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPSPI_H_ +#define FSL_LPSPI_H_ + +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/*! + * @addtogroup lpspi_driver + * @{ + */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI driver version. */ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) +/*@}*/ + +#ifndef LPSPI_DUMMY_DATA +/*! @brief LPSPI dummy data if no Tx data.*/ +#define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t g_lpspiDummyData[]; + +/*! @brief Status for the LPSPI driver.*/ +enum +{ + kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ + kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ + kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ + kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3), /*!< LPSPI transfer out Of range. */ + kStatus_LPSPI_Timeout = MAKE_STATUS(kStatusGroup_LPSPI, 4) /*!< LPSPI timeout polling status flags. */ +}; + +/*! @brief LPSPI status flags in SPIx_SR register.*/ +enum _lpspi_flags +{ + kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ + kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ + kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ + kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ + kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ + kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ + kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ + kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ + kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ + kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | + LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | + LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ +}; + +/*! @brief LPSPI interrupt source.*/ +enum _lpspi_interrupt_enable +{ + kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ + kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ + kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ + kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ + kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ + kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ + kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ + kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ + kLPSPI_AllInterruptEnable = + (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | + LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ +}; + +/*! @brief LPSPI DMA source.*/ +enum _lpspi_dma_enable +{ + kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ + kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ +}; + +/*! @brief LPSPI master or slave mode configuration.*/ +typedef enum _lpspi_master_slave_mode +{ + kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ + kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ +} lpspi_master_slave_mode_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ +typedef enum _lpspi_which_pcs_config +{ + kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ + kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ + kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ + kLPSPI_Pcs3 = 3U /*!< PCS[3] */ +} lpspi_which_pcs_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ +typedef enum _lpspi_pcs_polarity_config +{ + kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ + kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ +} lpspi_pcs_polarity_config_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ +enum _lpspi_pcs_polarity +{ + kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief LPSPI clock polarity configuration.*/ +typedef enum _lpspi_clock_polarity +{ + kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ + kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ +} lpspi_clock_polarity_t; + +/*! @brief LPSPI clock phase configuration.*/ +typedef enum _lpspi_clock_phase +{ + kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} lpspi_clock_phase_t; + +/*! @brief LPSPI data shifter direction options.*/ +typedef enum _lpspi_shift_direction +{ + kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ +} lpspi_shift_direction_t; + +/*! @brief LPSPI Host Request select configuration. */ +typedef enum _lpspi_host_request_select +{ + kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ + kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ +} lpspi_host_request_select_t; + +/*! @brief LPSPI Match configuration options. */ +typedef enum _lpspi_match_config +{ + kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ + kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ +} lpspi_match_config_t; + +/*! @brief LPSPI pin (SDO and SDI) configuration. */ +typedef enum _lpspi_pin_config +{ + kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ + kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */ + kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */ + kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ +} lpspi_pin_config_t; + +/*! @brief LPSPI data output configuration. */ +typedef enum _lpspi_data_out_config +{ + kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ + kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ +} lpspi_data_out_config_t; + +/*! @brief LPSPI cs function configuration. */ +typedef enum _lpspi_pcs_function_config +{ + kLPSPI_PcsAsCs = 0U, /*!< PCS pin select as cs function */ + kLPSPI_PcsAsData = 1U, /*!< PCS pin select as date function */ +} lpspi_pcs_function_config_t; + +/*! @brief LPSPI transfer width configuration. */ +typedef enum _lpspi_transfer_width +{ + kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ + kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ + kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ +} lpspi_transfer_width_t; + +/*! @brief LPSPI delay type selection.*/ +typedef enum _lpspi_delay_type +{ + kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ + kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ + kLPSPI_BetweenTransfer /*!< Delay between transfers. */ +} lpspi_delay_type_t; + +#define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ +#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ + +#define LPSPI_MASTER_WIDTH_SHIFT (16U) /*!< LPSPI master width shift macro, internal used */ +#define LPSPI_MASTER_WIDTH_MASK (0x30000U) /*!< LPSPI master width shift mask, internal used */ + +/*! @brief Use this enumeration for LPSPI master transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_master +{ + kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ + kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ + kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ + kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ + + kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */ + kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */ + kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */ + + kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ + + kLPSPI_MasterByteSwap = + 1U << 22 /*!< Is master swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ +}; + +#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ +#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ + +/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_slave +{ + kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ + kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ + kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ + kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ + + kLPSPI_SlaveByteSwap = + 1U << 22 /*!< Is slave swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ +}; + +/*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ +enum _lpspi_transfer_state +{ + kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kLPSPI_Busy, /*!< Transfer queue is not finished. */ + kLPSPI_Error /*!< Transfer error. */ +}; + +/*! @brief LPSPI master configuration structure.*/ +typedef struct _lpspi_master_config +{ + uint32_t baudRate; /*!< Baud Rate for LPSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. + It sets the boundary value if out of range.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum + delay. It sets the boundary value if out of range.*/ + uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the + minimum delay. It sets the boundary value if out of range.*/ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ + bool enableInputDelay; /*!< Enable master to sample the input data on a delayed SCK. This can help improve slave + setup time. Refer to device data sheet for specific time length. */ +} lpspi_master_config_t; + +/*! @brief LPSPI slave configuration structure.*/ +typedef struct _lpspi_slave_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ +} lpspi_slave_config_t; + +/*! + * @brief Forward declaration of the _lpspi_master_handle typedefs. + */ +typedef struct _lpspi_master_handle lpspi_master_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_handle typedefs. + */ +typedef struct _lpspi_slave_handle lpspi_slave_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief Slave completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master/slave transfer structure.*/ +typedef struct _lpspi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if + the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the + transfer is used for slave.*/ +} lpspi_transfer_t; + +/*! @brief LPSPI master transfer handle structure used for transactional API. */ +struct _lpspi_master_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + volatile bool isTxMask; /*!< A flag that whether TCR[TXMSK] is set. */ + volatile uint16_t bytesPerFrame; /*!< Number of bytes in each frame */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief LPSPI slave transfer handle structure used for transactional API. */ +struct _lpspi_slave_handle +{ + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the LPSPI master. + * + * @param base LPSPI peripheral address. + * @param masterConfig Pointer to structure lpspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * @code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); + +/*! + * @brief LPSPI slave configuration. + * + * @param base LPSPI peripheral address. + * @param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * @code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * @param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base); + +/*! + * @brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * @param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base); + +/*! + * @brief Get the LPSPI instance from peripheral base address. + * + * @param base LPSPI peripheral base address. + * @return LPSPI instance. + */ +uint32_t LPSPI_GetInstance(LPSPI_Type *base); + +/*! + * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. + * + * @param base LPSPI peripheral address. + * @param enable Pass true to enable module, false to disable module. + */ +static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) +{ + if (enable) + { + base->CR |= LPSPI_CR_MEN_MASK; + } + else + { + base->CR &= ~LPSPI_CR_MEN_MASK; + } +} + +/*! + *@} + */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the LPSPI status flag state. + * @param base LPSPI peripheral address. + * @return The LPSPI status(in SR register). + */ +static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Gets the LPSPI Tx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Tx FIFO size. + */ +static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Rx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Rx FIFO size. + */ +static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Tx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the transmit FIFO. + */ +static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); +} + +/*! + * @brief Gets the LPSPI Rx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the receive FIFO. + */ +static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); +} + +/*! + * @brief Clears the LPSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. + * Example usage: + * @code + * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); + * @endcode + * + * @param base LPSPI peripheral address. + * @param statusFlags The status flag used from type _lpspi_flags. + */ +static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} + */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the LPSPI interrupts. + * + * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. + * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. + * + * @code + * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the LPSPI interrupts. + * + * @code + * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + *@} + */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER |= mask; +} + +/*! + * @brief Disables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER &= ~mask; +} + +/*! + * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. + * + * This function gets the LPSPI Transmit Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Transmit Data Register address. + */ +static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->TDR); +} + +/*! + * @brief Gets the LPSPI Receive Data Register address for a DMA operation. + * + * This function gets the LPSPI Receive Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Receive Data Register address. + */ +static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->RDR); +} + +/*! + *@} + */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Check the argument for transfer . + * + * @param base LPSPI peripheral address. + * @param transfer the transfer struct to be used. + * @param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer + * @return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma); + +/*! + * @brief Configures the LPSPI for either master or slave. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * @param base LPSPI peripheral address. + * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. + */ +static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) +{ + base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); +} + +/*! + * @brief Configures the peripheral chip select used for the transfer. + * + * @param base LPSPI peripheral address. + * @param select LPSPI Peripheral Chip Select (PCS) configuration. + */ +static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select) +{ + base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select); +} + +/*! + * @brief Set the PCS signal to continuous or uncontinuous mode. + * + * @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command + * word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. + * In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after + * that the LPSPI will transmit received data back (assuming a 32-bit shift register). + * + * @param base LPSPI peripheral address. + * @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode. + */ +static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous) +{ + if (IsContinous) + { + base->TCR |= LPSPI_TCR_CONT_MASK; + } + else + { + base->TCR &= ~LPSPI_TCR_CONT_MASK; + } +} + +/*! + * @brief Returns whether the LPSPI module is in master mode. + * + * @param base LPSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool LPSPI_IsMaster(LPSPI_Type *base) +{ + return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); +} + +/*! + * @brief Flushes the LPSPI FIFOs. + * + * @param base LPSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. + * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. + */ +static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ + base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); +} + +/*! + * @brief Sets the transmit and receive FIFO watermark values. + * + * This function allows the user to set the receive and transmit FIFO watermarks. The function + * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be + * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. + * + * @param base LPSPI peripheral address. + * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + */ +static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) +{ + base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); +} + +/*! + * @brief Configures all LPSPI peripheral chip select polarities simultaneously. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of + * PCS is device-specific. + * @code + * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. + */ +static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) +{ + base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); +} + +/*! + * @brief Configures the frame size. + * + * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal + * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word + * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not + * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. + * + * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although + * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command + * register + * should only be changed if the LPSPI is idle. + * + * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That + * means the TCR register should be written to when the Tx FIFO is not full. + * + * @param base LPSPI peripheral address. + * @param frameSize The frame size in number of bits. + */ +static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) +{ + base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U); +} + +/*! + * @brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param baudRate_Bps The desired baud rate in bits per second. + * @param srcClock_Hz Module source input clock in Hertz. + * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * @return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue); + +/*! + * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param scaler The 8-bit delay value 0x00 to 0xFF (255). + * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * @param base LPSPI peripheral address. + * @param delayTimeInNanoSec The desired delay value in nano-seconds. + * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * @param srcClock_Hz Module source input clock in Hertz. + * @return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz); + +/*! + * @brief Writes data into the transmit data buffer. + * + * This function writes data passed in by the user to the Transmit Data Register (TDR). + * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, + * the user has to manage sending the data one 32-bit word at a time. + * Any writes to the TDR result in an immediate push to the transmit FIFO. + * This function can be used for either master or slave modes. + * + * @param base LPSPI peripheral address. + * @param data The data word to be sent. + */ +static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) +{ + base->TDR = data; +} + +/*! + * @brief Reads data from the data buffer. + * + * This function reads the data from the Receive Data Register (RDR). + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The data read from the data buffer. + */ +static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) +{ + return (base->RDR); +} + +/*! + * @brief Set up the dummy data. + * + * @param base LPSPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); + +/*! + *@} + */ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_master_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been + * completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); + +/*! + * @brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * @param instance LPSPI instance. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(uint32_t instance, lpspi_master_handle_t *handle); + +/*! + * @brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_slave_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * @param instance LPSPI instance index. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle); + +/*! + *@} + */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /*FSL_LPSPI_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_edma.c new file mode 100644 index 0000000000..bfba766d33 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_edma.c @@ -0,0 +1,1118 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi_edma.h" + +/*********************************************************************************************************************** + * Definitions + ***********************************************************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpspi_edma" +#endif + +/*! + * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_master_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_master_edma_handle_t *handle; /*!< lpspi_master_edma_handle_t handle */ +} lpspi_master_edma_private_handle_t; + +/*! + * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_slave_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_slave_edma_handle_t *handle; /*!< lpspi_slave_edma_handle_t handle */ +} lpspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** + * Prototypes + ***********************************************************************************************************************/ + +/*! + * @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! + * @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); + +/*********************************************************************************************************************** + * Variables + ***********************************************************************************************************************/ +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi edma handles for each instance. */ +static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; +static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; + +/*********************************************************************************************************************** + * Code + ***********************************************************************************************************************/ +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) +{ + assert(rxData != NULL); + + switch (bytesEachRead) + { + case 1: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + break; + + case 2: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + break; + + case 4: + + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + + break; + + default: + assert(false); + break; + } +} + +/*! + * brief Initializes the LPSPI master eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx and Tx are the same source) DMA + * request source. + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaIntermediaryToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle. + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_master_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + lpspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle != NULL); + assert(edmaRxRegToRxDataHandle != NULL); + assert(edmaTxDataToTxRegHandle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiMasterEdmaPrivateHandle[instance].base = base; + s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +static void LPSPI_PrepareTransferEDMA(LPSPI_Type *base) +{ + /* Flush FIFO, clear status, disable all the inerrupts and DMA requests. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); +} + +/*! + * brief LPSPI master config transfer parameter using eDMA. + * + * This function is preparing to transfers data using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param configFlags transfer configuration flags. ref _lpspi_transfer_config_flag_for_master. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. + */ +status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags) +{ + assert(handle != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + /* Disable module before configuration */ + LPSPI_Enable(base, false); + + LPSPI_PrepareTransferEDMA(base); + + bool isByteSwap = ((configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + bool isPcsContinuous = ((configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U); + uint32_t instance = LPSPI_GetInstance(base); + uint8_t dummyData = g_lpspiDummyData[instance]; + /*Used for byte swap*/ + uint32_t whichPcs = (configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isPcsContinuous = isPcsContinuous; + handle->isByteSwap = isByteSwap; + handle->isThereExtraRxBytes = false; + + /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ + LPSPI_SetFifoWatermarks(base, 0U, 0U); + + /* Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is + * hard to controlled by software. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + handle->bytesLastRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + + handle->bytesLastRead = 4U; + } + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using eDMA without configs. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * This API is only for transfer through DMA without configuration. + * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure, config field is not working. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. + * retval kStatus_InvalidArgument The transfer structure is invalid. + */ +status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, true)) + { + return kStatus_InvalidArgument; + } + + /* Variables */ + bool isThereExtraTxBytes = false; + uint8_t bytesLastWrite = 0; + uint32_t instance = LPSPI_GetInstance(base); + /*Used for byte swap*/ + uint32_t addrOffset = 0; + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + edma_transfer_config_t transferConfigRx = {0}; + edma_transfer_config_t transferConfigTx = {0}; + edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame > 4U) + { + if ((transfer->dataSize % 4U) != 0U) + { + bytesLastWrite = (uint8_t)(transfer->dataSize % 4U); + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + + --handle->writeRegRemainingTimes; + + --handle->readRegRemainingTimes; + handle->isThereExtraRxBytes = true; + } + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiMasterCallback, + &s_lpspiMasterEdmaPrivateHandle[instance]); + + /* Configure rx EDMA transfer */ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData != NULL) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + addrOffset; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ + handle->nbytes = (uint8_t)transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + (uint32_t)kEDMA_MajorInterruptEnable); + + /* Configure tx EDMA transfer */ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + if (isThereExtraTxBytes) + { + if (handle->txData != NULL) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + + if (handle->isPcsContinuous) + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + } + + if (handle->isPcsContinuous) + { + handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); + + transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); + transferConfigTx.srcOffset = 0; + + transferConfigTx.destAddr = (uint32_t) & (base->TCR); + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_pcsContinuous); + EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); + } + + if (handle->txData != NULL) + { + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0U; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else if (handle->isPcsContinuous) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + LPSPI_EnableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + status_t status = kStatus_Fail; + status = LPSPI_MasterTransferPrepareEDMALite(base, handle, transfer->configFlags); + if(kStatus_Success != status) + { + return status; + } + return LPSPI_MasterTransferEDMALite(base,handle,transfer); +} + +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle != NULL); + assert(g_lpspiEdmaPrivateHandle != NULL); + + uint32_t readData; + + lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + size_t rxRemainingByteCount = lpspiEdmaPrivateHandle->handle->rxRemainingByteCount; + uint8_t bytesLastRead = lpspiEdmaPrivateHandle->handle->bytesLastRead; + bool isByteSwap = lpspiEdmaPrivateHandle->handle->isByteSwap; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData != NULL) + { + LPSPI_SeparateEdmaReadData(&(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]), + readData, bytesLastRead, isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = (uint8_t)kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback != NULL) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI master aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) +{ + assert(handle != NULL); + + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = (uint8_t)kLPSPI_Idle; +} + +/*! + * brief Gets the master eDMA transfer remaining bytes. + * + * This function gets the master eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the EDMA transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief Initializes the LPSPI slave eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request + * source. + * + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaTxDataToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle . + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_slave_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + lpspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle != NULL); + assert(edmaRxRegToRxDataHandle != NULL); + assert(edmaTxDataToTxRegHandle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiSlaveEdmaPrivateHandle[instance].base = base; + s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +/*! + * brief LPSPI slave transfers data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + /* Disable module before configuration. */ + LPSPI_Enable(base, false); + /* Check arguements, also dma transfer can not support 3 bytes */ + if (!LPSPI_CheckTransferArgument(base, transfer, true)) + { + return kStatus_InvalidArgument; + } + + LPSPI_PrepareTransferEDMA(base); + + /* Variables */ + bool isThereExtraTxBytes = false; + bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + uint8_t bytesLastWrite = 0; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t mask = (uint32_t)kLPSPI_RxDmaEnable; + + /* Used for byte swap */ + uint32_t addrOffset = 0; + uint32_t instance = LPSPI_GetInstance(base); + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + edma_transfer_config_t transferConfigRx = {0}; + edma_transfer_config_t transferConfigTx = {0}; + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isByteSwap = isByteSwap; + handle->isThereExtraRxBytes = false; + + /* Because DMA is fast enough, set the RX and TX watermarks to 0. */ + LPSPI_SetFifoWatermarks(base, 0U, 0U); + + /* Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* For DMA transfer, mask the transmit data if the tx data is null, for rx the receive data should not be masked at + any time since we use rx dma transfer finish cllback to indicate transfer finish. */ + base->TCR = + (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_MASK)) | + LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + + handle->bytesLastRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + + handle->bytesLastRead = 4U; + + if ((transfer->dataSize % 4U) != 0U) + { + bytesLastWrite = (uint8_t)(transfer->dataSize % 4U); + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + --handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = true; + --handle->readRegRemainingTimes; + } + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiSlaveCallback, + &s_lpspiSlaveEdmaPrivateHandle[instance]); + + /*Rx*/ + if (handle->readRegRemainingTimes > 0U) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData != NULL) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + addrOffset; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + handle->nbytes = (uint8_t)transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + } + + /*Tx*/ + if (handle->txData != NULL) + { + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + if (isThereExtraTxBytes) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + transferConfigTx.destOffset = 0; + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + addrOffset = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + transferConfigTx.destOffset = 0; + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + addrOffset = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + mask |= (uint32_t)kLPSPI_TxDmaEnable; + } + + LPSPI_EnableDMA(base, mask); + + return kStatus_Success; +} + +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle != NULL); + assert(g_lpspiEdmaPrivateHandle != NULL); + + uint32_t readData; + + lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_slave_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + size_t rxRemainingByteCount = lpspiEdmaPrivateHandle->handle->rxRemainingByteCount; + uint8_t bytesLastRead = lpspiEdmaPrivateHandle->handle->bytesLastRead; + bool isByteSwap = lpspiEdmaPrivateHandle->handle->isByteSwap; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData != NULL) + { + LPSPI_SeparateEdmaReadData(&(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]), + readData, bytesLastRead, isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = (uint8_t)kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback != NULL) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI slave aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) +{ + assert(handle != NULL); + + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = (uint8_t)kLPSPI_Idle; +} + +/*! + * brief Gets the slave eDMA transfer remaining bytes. + * + * This function gets the slave eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the eDMA transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_edma.h new file mode 100644 index 0000000000..d5ed08989f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_edma.h @@ -0,0 +1,339 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPSPI_EDMA_H_ +#define FSL_LPSPI_EDMA_H_ + +#include "fsl_lpspi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpspi_edma_driver + * @{ + */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI EDMA driver version. */ +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! + * @brief Forward declaration of the _lpspi_master_edma_handle typedefs. + */ +typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. + */ +typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */ +struct _lpspi_master_edma_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ + volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + + uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!async_status = status; + (void)xSemaphoreGiveFromISR(handle->event, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes LPSPI. + * + * This function initializes the LPSPI module and related RTOS context. + * + * param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the LPSPI instance to initialize. + * param masterConfig Configuration structure to set-up LPSPI in master mode. + * param srcClock_Hz Frequency of input clock of the LPSPI module. + * return status of the operation. + */ +status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle, + LPSPI_Type *base, + const lpspi_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(lpspi_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->event = xSemaphoreCreateBinary(); + if (handle->event == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + (void)LPSPI_MasterInit(handle->base, masterConfig, srcClock_Hz); + LPSPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, LPSPI_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the LPSPI. + * + * This function deinitializes the LPSPI module and related RTOS context. + * + * param handle The RTOS LPSPI handle. + */ +status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle) +{ + LPSPI_Deinit(handle->base); + vSemaphoreDelete(handle->event); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs LPSPI transfer. + * + * This function performs an LPSPI transfer according to data given in the transfer structure. + * + * param handle The RTOS LPSPI handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPSPI_Busy; + } + + /* Initiate transfer */ + status = LPSPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE) + { + return kStatus_LPSPI_Error; + } + + /* Retrieve status before releasing mutex */ + status = handle->async_status; + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Translate status of underlying driver */ + if (status == kStatus_LPSPI_Idle) + { + status = kStatus_Success; + } + + return status; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_freertos.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_freertos.h new file mode 100644 index 0000000000..98fe4b16f9 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpspi_freertos.h @@ -0,0 +1,103 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPSPI_FREERTOS_H__ +#define FSL_LPSPI_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" +#include "fsl_lpspi.h" + +/*! + * @addtogroup lpspi_freertos_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI FreeRTOS driver version 2.0.0. */ +#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief LPSPI FreeRTOS handle */ +typedef struct _lpspi_rtos_handle +{ + LPSPI_Type *base; /*!< LPSPI base address */ + lpspi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; + SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */ + SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */ +} lpspi_rtos_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPSPI RTOS Operation + * @{ + */ + +/*! + * @brief Initializes LPSPI. + * + * This function initializes the LPSPI module and related RTOS context. + * + * @param handle The RTOS LPSPI handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the LPSPI instance to initialize. + * @param masterConfig Configuration structure to set-up LPSPI in master mode. + * @param srcClock_Hz Frequency of input clock of the LPSPI module. + * @return status of the operation. + */ +status_t LPSPI_RTOS_Init(lpspi_rtos_handle_t *handle, + LPSPI_Type *base, + const lpspi_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the LPSPI. + * + * This function deinitializes the LPSPI module and related RTOS context. + * + * @param handle The RTOS LPSPI handle. + */ +status_t LPSPI_RTOS_Deinit(lpspi_rtos_handle_t *handle); + +/*! + * @brief Performs LPSPI transfer. + * + * This function performs an LPSPI transfer according to data given in the transfer structure. + * + * @param handle The RTOS LPSPI handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t LPSPI_RTOS_Transfer(lpspi_rtos_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_LPSPI_FREERTOS_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lptmr.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lptmr.c new file mode 100644 index 0000000000..4741e22a65 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lptmr.c @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lptmr.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lptmr" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(LPTMR_CLOCKS) +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base LPTMR peripheral base address + * + * @return The LPTMR instance + */ +static uint32_t LPTMR_GetInstance(LPTMR_Type *base); +#endif /* LPTMR_CLOCKS */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(LPTMR_CLOCKS) +/*! @brief Pointers to LPTMR bases for each instance. */ +static LPTMR_Type *const s_lptmrBases[] = LPTMR_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPTMR clocks for each instance. */ +static const clock_ip_name_t s_lptmrClocks[] = LPTMR_CLOCKS; + +#if defined(LPTMR_PERIPH_CLOCKS) +/* Array of LPTMR functional clock name. */ +static const clock_ip_name_t s_lptmrPeriphClocks[] = LPTMR_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPTMR_CLOCKS */ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(LPTMR_CLOCKS) +static uint32_t LPTMR_GetInstance(LPTMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lptmrBases); instance++) + { + if (s_lptmrBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lptmrBases)); + + return instance; +} +#endif /* LPTMR_CLOCKS */ + +/*! + * brief Ungates the LPTMR clock and configures the peripheral for a basic operation. + * + * note This API should be called at the beginning of the application using the LPTMR driver. + * + * param base LPTMR peripheral base address + * param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config) +{ + assert(NULL != config); + +#if defined(LPTMR_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPTMR_GetInstance(base); + + /* Ungate the LPTMR clock*/ + CLOCK_EnableClock(s_lptmrClocks[instance]); +#if defined(LPTMR_PERIPH_CLOCKS) + CLOCK_EnableClock(s_lptmrPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPTMR_CLOCKS */ + + /* Configure the timers operation mode and input pin setup */ + base->CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | + LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); + + /* Configure the prescale value and clock source */ + base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | + LPTMR_PSR_PCS(config->prescalerClockSource)); +} + +/*! + * brief Gates the LPTMR clock. + * + * param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base) +{ + /* Disable the LPTMR and reset the internal logic */ + base->CSR &= ~LPTMR_CSR_TEN_MASK; + +#if defined(LPTMR_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPTMR_GetInstance(base); + + /* Gate the LPTMR clock*/ + CLOCK_DisableClock(s_lptmrClocks[instance]); +#if defined(LPTMR_PERIPH_CLOCKS) + CLOCK_DisableClock(s_lptmrPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPTMR_CLOCKS */ +} + +/*! + * brief Fills in the LPTMR configuration structure with default settings. + * + * The default values are as follows. + * code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * endcode + * param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Use time counter mode */ + config->timerMode = kLPTMR_TimerModeTimeCounter; + /* Use input 0 as source in pulse counter mode */ + config->pinSelect = kLPTMR_PinSelectInput_0; + /* Pulse input pin polarity is active-high */ + config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + /* Counter resets whenever TCF flag is set */ + config->enableFreeRunning = false; + /* Bypass the prescaler */ + config->bypassPrescaler = true; + /* LPTMR clock source */ +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) + config->prescalerClockSource = kLPTMR_PrescalerClock_1; +#else + config->prescalerClockSource = kLPTMR_PrescalerClock_0; +#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */ + /* Divide the prescaler clock by 2 */ + config->value = kLPTMR_Prescale_Glitch_0; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lptmr.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lptmr.h new file mode 100644 index 0000000000..ba94fe1773 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lptmr.h @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPTMR_H_ +#define FSL_LPTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lptmr + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */ +/*@}*/ + +/*! @brief LPTMR pin selection used in pulse counter mode.*/ +typedef enum _lptmr_pin_select +{ + kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ + kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ + kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ + kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ +} lptmr_pin_select_t; + +/*! @brief LPTMR pin polarity used in pulse counter mode.*/ +typedef enum _lptmr_pin_polarity +{ + kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ + kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ +} lptmr_pin_polarity_t; + +/*! @brief LPTMR timer mode selection.*/ +typedef enum _lptmr_timer_mode +{ + kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ + kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ +} lptmr_timer_mode_t; + +/*! @brief LPTMR prescaler/glitch filter values*/ +typedef enum _lptmr_prescaler_glitch_value +{ + kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ + kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ + kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ + kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ + kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ + kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ + kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ + kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ + kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ + kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ + kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ + kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ + kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ + kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ + kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ + kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ +} lptmr_prescaler_glitch_value_t; + +/*! + * @brief LPTMR prescaler/glitch filter clock select. + * @note Clock connections are SoC-specific + */ +typedef enum _lptmr_prescaler_clock_select +{ + kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) + kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ +#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */ + kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) + kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ +#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT */ +} lptmr_prescaler_clock_select_t; + +/*! @brief List of the LPTMR interrupts */ +typedef enum _lptmr_interrupt_enable +{ + kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ +} lptmr_interrupt_enable_t; + +/*! @brief List of the LPTMR status flags */ +typedef enum _lptmr_status_flags +{ + kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ +} lptmr_status_flags_t; + +/*! + * @brief LPTMR config structure + * + * This structure holds the configuration settings for the LPTMR peripheral. To initialize this + * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a + * pointer to your configuration structure instance. + * + * The configuration struct can be made constant so it resides in flash. + */ +typedef struct _lptmr_config +{ + lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ + lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ + lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ + bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow + False: counter is reset when the compare flag is set */ + bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */ + lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ + lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ +} lptmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation. + * + * @note This API should be called at the beginning of the application using the LPTMR driver. + * + * @param base LPTMR peripheral base address + * @param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); + +/*! + * @brief Gates the LPTMR clock. + * + * @param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base); + +/*! + * @brief Fills in the LPTMR configuration structure with default settings. + * + * The default values are as follows. + * @code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * @endcode + * @param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg |= mask; + base->CSR = reg; +} + +/*! + * @brief Disables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t. + */ +static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg &= ~mask; + base->CSR = reg; +} + +/*! + * @brief Gets the enabled LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TIE_MASK); +} + +/*! @}*/ + +#if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE) +/*! + * @brief Enable or disable timer DMA request + * + * @param base base LPTMR peripheral base address + * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable. + */ +static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable) +{ + if (enable) + { + base->CSR |= LPTMR_CSR_TDRE_MASK; + } + else + { + base->CSR &= ~(LPTMR_CSR_TDRE_MASK); + } +} +#endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the LPTMR status flags. + * + * @param base LPTMR peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TCF_MASK); +} + +/*! + * @brief Clears the LPTMR status flags. + * + * @param base LPTMR peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::lptmr_status_flags_t. + */ +static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! @}*/ + +/*! + * @name Read and write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers counts from 0 until it equals the count value set here. The count value is written to + * the CMR register. + * + * @note + * 1. The TCF flag is set with the CNR equals the count provided here and then increments. + * 2. Call the utility macros provided in the fsl_common.h to convert to ticks. + * + * @param base LPTMR peripheral base address + * @param ticks A timer period in units of ticks, which should be equal or greater than 1. + */ +static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks) +{ + assert(ticks > 0U); + base->CMR = LPTMR_CMR_COMPARE(ticks - 1U); +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value in a range from 0 to a + * timer period. + * + * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. + * + * @param base LPTMR peripheral base address + * + * @return The current counter value in ticks + */ +static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) +{ + /* Must first write any value to the CNR. This synchronizes and registers the current value + * of the CNR into a temporary register which can then be read + */ + base->CNR = 0U; + return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT); +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer. + * + * After calling this function, the timer counts up to the CMR register value. + * Each time the timer reaches the CMR value and then increments, it generates a + * trigger pulse and sets the timeout interrupt flag. An interrupt is also + * triggered if the timer interrupt is enabled. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StartTimer(LPTMR_Type *base) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg |= LPTMR_CSR_TEN_MASK; + base->CSR = reg; +} + +/*! + * @brief Stops the timer. + * + * This function stops the timer and resets the timer's counter register. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StopTimer(LPTMR_Type *base) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg &= ~LPTMR_CSR_TEN_MASK; + base->CSR = reg; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPTMR_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart.c new file mode 100644 index 0000000000..a7afd86b56 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart.c @@ -0,0 +1,2129 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpuart" +#endif + +/*! + * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpuart_irq_handler_t` + */ +typedef union lpuart_to_lpflexcomm +{ + lpuart_irq_handler_t lpuart_handler; + lpflexcomm_irq_handler_t lpflexcomm_handler; +} lpuart_to_lpflexcomm_t; + +/* LPUART transfer state. */ +enum +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Check whether the RX ring buffer is full. + * + * @userData handle LPUART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Write to TX register using non-blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART peripheral base address. */ +static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; + +/* Array of LPUART IRQ number. */ +const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the LPUART instance from peripheral base address. + * + * param base LPUART peripheral base address. + * return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases); instance++) + { + if (s_lpuartBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpuartBases)); + + return instance; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * userData handle LPUART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + size_t size; + size_t tmpRxRingBufferSize = handle->rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; + + if (tmpRxRingBufferTail > tmpRxRingBufferHead) + { + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); + } + else + { + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (uint8_t)(base->DATA & 0x7FU); + } + else + { + data[i] = (uint8_t)base->DATA; + } +#else + data[i] = (uint8_t)(base->DATA); +#endif + } +} + +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = (uint16_t)(base->DATA & 0x03FFU); + } +} +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + assert(0U < config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->rxFifoWatermark); +#endif + + status_t status = kStatus_Success; + uint32_t temp; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 10U / (config->baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* For MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); + tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : + (config->baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + else + { +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + /* initialize flexcomm to LPUART mode */ + status = LP_FLEXCOMM_Init(LPUART_GetInstance(base), LP_FLEXCOMM_PERIPH_LPUART); + if (kStatus_Success != status) + { + return status; + } +#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | + LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (true == config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (true == config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (true == config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (true == config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (true == config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout configuration. */ + base->REIR = (uint32_t)config->timeoutConfig.rxExtendedTimeoutValue; + base->TEIR = (uint32_t)config->timeoutConfig.txExtendedTimeoutValue; + base->TOCR |= (uint32_t)config->timeoutConfig.rxCounter0.enableCounter | + ((uint32_t)config->timeoutConfig.rxCounter1.enableCounter << 1U) | + ((uint32_t)config->timeoutConfig.txCounter0.enableCounter << 2U) | + ((uint32_t)config->timeoutConfig.txCounter1.enableCounter << 3U); + base->TIMEOUT[0] = ((uint32_t)config->timeoutConfig.rxCounter0.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.rxCounter0.timeoutValue; + base->TIMEOUT[1] = ((uint32_t)config->timeoutConfig.rxCounter1.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.rxCounter1.timeoutValue; + base->TIMEOUT[2] = ((uint32_t)config->timeoutConfig.txCounter0.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.txCounter0.timeoutValue; + base->TIMEOUT[3] = ((uint32_t)config->timeoutConfig.txCounter1.timeoutCondition << 30U) | + (uint32_t)config->timeoutConfig.txCounter1.timeoutValue; +#endif + + /* Siglewire configuration. */ +#if defined(FSL_FEATURE_LPUART_HAS_HDCR) && FSL_FEATURE_LPUART_HAS_HDCR + base->HDCR = (uint32_t)config->rtsDelay << 8U; + if (config->enableSingleWire) + { + base->HDCR |= 0xFUL; + } +#endif + } + return status; +} +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shift out */ + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0U; + +#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) + LP_FLEXCOMM_Deinit(LPUART_GetInstance(base)); +#endif +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0U; + config->rxFifoWatermark = 0U; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +} + +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(0U < baudRate_Bps); + + status_t status = kStatus_Success; + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 10U / (baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* For MISRA 15.7 */ + } + + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); + + tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + + return status; +} + +/*! + * brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base LPUART peripheral base address. + * param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */ + temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK); + temp |= (uint32_t)LPUART_CTRL_M_MASK; + base->CTRL = temp; + } + else + { + /* Clear LPUART_CTRL_M. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK; + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT + /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */ + base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK; +#endif +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base LPUART peripheral base address. + * param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address) +{ + assert(base != NULL); + + uint32_t temp = base->DATA & 0xFFFFFC00UL; + temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT)); + base->DATA = temp; +} + +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Modem control interrupt enables */ + base->MCR |= (mask & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout interrupt enables. */ + base->TOSR |= ((mask >> 2U) & 0xF00UL); +#endif + /* Check int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD |= baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Check int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL |= mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Modem control interrupts. */ + base->MCR &= ~(mask & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout interrupt enables. */ + base->TOSR &= ~((mask >> 2U) & 0xF00UL); +#endif + + /* Clear int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD &= ~baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Clear int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL &= ~mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + /* Check int enable bits in base->CTRL */ + uint32_t temp = (uint32_t)(base->CTRL & 0xFF0C000UL); + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Check modem control interrupts. */ + temp |= (base->MCR & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Check timeout control interrupts. */ + temp |= ((base->TOCR & 0xF00UL) << 2U); +#endif + + /* Check int enable bits in base->BAUD */ + temp = (temp & ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable) | ((base->BAUD & LPUART_BAUD_RXEDGIE_MASK) >> 8U); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp = (temp & ~(uint32_t)kLPUART_LinBreakInterruptEnable) | ((base->BAUD & LPUART_BAUD_LBKDIE_MASK) >> 8U); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + temp = + (temp & ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable)) | + (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + + return temp; +} + +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + + temp = (base->STAT & 0xC1FFC000UL); +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + temp |= ((base->MSR & 0xFUL) << 2U); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + temp |= ((base->TOSR & 0xF00UL) << 2U); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16U; +#endif + /* Only keeps the status bits */ + temp &= (uint32_t)kLPUART_AllFlags; + return temp; +} + +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; + + /* Only deal with the clearable flags */ + mask &= (uint32_t)kLPUART_AllClearFlags; + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + /* Modem status */ + base->MSR = ((mask >> 2U) & 0xFUL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_TIMEOUT) && FSL_FEATURE_LPUART_HAS_TIMEOUT + /* Timeout status */ + base->TOSR = ((mask >> 2U) & 0xF00UL); +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Status bits in FIFO register */ + if ((mask & ((uint32_t)kLPUART_TxFifoOverflowFlag | (uint32_t)kLPUART_RxFifoUnderflowFlag)) != 0U) + { + /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case + they are written 1 accidentally. */ + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)( + ~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; + } +#endif + /* Status bits in STAT register */ + /* First get the STAT register value and mask all the bits that not represent status, then OR with the status bit + * that is to be W1C */ + temp = (base->STAT & 0x3E000000UL) | mask; + base->STAT = temp; + /* If some flags still pending. */ + if (0U != (mask & LPUART_GetStatusFlags(base))) + { + status = kStatus_LPUART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the data to be sent out to bus. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + const uint16_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint8_t *dataAddress = data; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + + if (kStatus_Success == status) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(dataAddress) = (uint8_t)(base->DATA & 0x7FU); + dataAddress++; + } + else + { + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; + } +#else + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; +#endif + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Reads the receiver data register in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint16_t *dataAddress = data; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + if (kStatus_Success == status) + { + *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU); + dataAddress++; + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + /* Get instance from peripheral base address. */ + uint32_t instance = LPUART_GetInstance(base); + + lpuart_to_lpflexcomm_t handler; + handler.lpuart_handler = LPUART_TransferHandleIRQ; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(LPUART_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPUART); + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(s_lpuartIRQ[instance]); +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable the interrupt to accept the data when user need the ring buffer. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kLPUART_RxIdle) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->txData); + assert(0U != xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kLPUART_TxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable transmitter interrupt. */ + base->CTRL |= (uint32_t)LPUART_CTRL_TIE_MASK; + EnableGlobalIRQ(irqMask); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_TIE_MASK | LPUART_CTRL_TCIE_MASK); + EnableGlobalIRQ(irqMask); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmptxDataSize = handle->txDataSize; + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + status = kStatus_NoTransferInProgress; + } + else + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + *count = handle->txDataSizeAll - tmptxDataSize - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U) + { + *count = handle->txDataSizeAll - tmptxDataSize; + } + else + { + *count = handle->txDataSizeAll - tmptxDataSize - 1U; + } +#endif + } + + return status; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->rxData); + assert(0U != xfer->dataSize); + + uint32_t i; + status_t status; + uint32_t irqMask; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (NULL != handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable LPUART RX IRQ, protect ring buffer. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (0U != bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + bytesCurrentReceived++; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (0U != bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kLPUART_RxBusy; + } + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Re-enable LPUART RX IRQ. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Enable RX interrupt. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + /* Return the how many bytes have read. */ + if (NULL != receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Disable RX interrupt. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmprxDataSize = handle->rxDataSize; + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxDataSizeAll - tmprxDataSize; + } + + return status; +} + +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param instance LPUART instance. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle) +{ + assert(NULL != irqHandle); + assert(instance < ARRAY_SIZE(s_lpuartBases)); + LPUART_Type *base = s_lpuartBases[instance]; + uint8_t count; + uint8_t tempCount; + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); + uint16_t tpmRxRingBufferHead; + uint32_t tpmData; + uint32_t irqMask; + lpuart_handle_t *handle = (lpuart_handle_t *)irqHandle; + + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (NULL != (handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((0U != handle->rxDataSize) && (0U != count)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, (uint16_t *)handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount * 2u]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, invoke rx idle callback.*/ + if (0U == (handle->rxDataSize)) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_IDLE_MASK); + + /* If rxDataSize is 0, disable rx ready, overrun and idle line interrupt.*/ + if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + /* Invoke callback if callback is not NULL and rxDataSize is not 0. */ + else if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + else + { + /* Avoid MISRA 15.7 */ + } + } + /* Receive data register full */ + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) + { + /* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((0U != handle->rxDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, (uint16_t *)handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount * 2]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (NULL != handle->rxRingBuffer) + { + while (0U != count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + tpmRxRingBufferHead = handle->rxRingBufferHead; + tpmData = base->DATA; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU); + } + else + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } +#else + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; +#endif + + /* Increase handle->rxRingBufferHead. */ + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK | LPUART_CTRL_ILIE_MASK); + EnableGlobalIRQ(irqMask); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((0U != handle->txDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + if (!handle->is16bitData) + { + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData = &handle->txData[tempCount]; + } + else + { + LPUART_WriteNonBlocking16bit(base, (const uint16_t *)handle->txData, tempCount); + handle->txData = &handle->txData[tempCount * 2u]; + } + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (0U == handle->txDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable TX register empty interrupt and enable transmission completion interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK) | LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + } + } + } + + /* Transmission complete and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && + (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + irqMask = DisableGlobalIRQ(); + /* Disable transmission complete interrupt. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + + /* Trigger callback. */ + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} + +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle) +{ + /* To be implemented by User. */ +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart.h new file mode 100644 index 0000000000..072c22aa1f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart.h @@ -0,0 +1,1175 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_H_ +#define FSL_LPUART_H_ + +#include "fsl_common.h" +#include "fsl_lpflexcomm.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*@}*/ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the LPUART driver. */ +enum +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ + kStatus_LPUART_Timeout = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeInterruptEnable = LPUART_MCR_CTS_MASK, /*!< Change of state on CTS_B pin. bit 0 */ + kLPUART_DsrStateChangeInterruptEnable = LPUART_MCR_DSR_MASK, /*!< Change of state on DSR_B pin. bit 1 */ + kLPUART_RinStateChangeInterruptEnable = LPUART_MCR_RIN_MASK, /*!< Change of state on RIN_B pin. bit 2 */ + kLPUART_DcdStateChangeInterruptEnable = LPUART_MCR_DCD_MASK, /*!< Change of state on DCD_B pin. bit 3 */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */ + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */ +#endif + kLPUART_RxCounter0TimeoutInterruptEnable = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ + kLPUART_RxCounter1TimeoutInterruptEnable = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ + kLPUART_TxCounter0TimeoutInterruptEnable = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ + kLPUART_TxCounter1TimeoutInterruptEnable = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch2InterruptEnable = + (LPUART_CTRL_MA2IE_MASK), /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ + kLPUART_DataMatch1InterruptEnable = + (LPUART_CTRL_MA1IE_MASK), /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */ +#endif + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. bit 20 */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. bit 21 */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. bit 22 */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. bit 23 */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. bit 24 */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. bit 25 */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. bit 26 */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. bit 27 */ + kLPUART_AllInterruptEnable = +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeInterruptEnable | kLPUART_DsrStateChangeInterruptEnable | + kLPUART_RinStateChangeInterruptEnable | kLPUART_DcdStateChangeInterruptEnable | +#endif + kLPUART_RxActiveEdgeInterruptEnable | kLPUART_IdleLineInterruptEnable | kLPUART_RxDataRegFullInterruptEnable | + kLPUART_TransmissionCompleteInterruptEnable | kLPUART_TxDataRegEmptyInterruptEnable | + kLPUART_ParityErrorInterruptEnable | kLPUART_FramingErrorInterruptEnable | kLPUART_NoiseErrorInterruptEnable | + kLPUART_RxOverrunInterruptEnable +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakInterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_RxFifoUnderflowInterruptEnable | kLPUART_TxFifoOverflowInterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch2InterruptEnable | kLPUART_DataMatch1InterruptEnable +#endif + , +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */ + kLPUART_RxFifoEmptyFlag = + (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */ + kLPUART_TxFifoEmptyFlag = + (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty. bit 7 */ +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeFlag = LPUART_MCR_CTS_MASK << 2U, /*!< Change of state on CTS_B pin. bit 2 */ + kLPUART_DsrStateChangeFlag = LPUART_MCR_DSR_MASK << 2U, /*!< Change of state on DSR_B pin. bit 3 */ + kLPUART_RinStateChangeFlag = LPUART_MCR_RIN_MASK << 2U, /*!< Change of state on RIN_B pin. bit 4 */ + kLPUART_DcdStateChangeFlag = LPUART_MCR_DCD_MASK << 2U, /*!< Change of state on DCD_B pin. bit 5 */ +#endif + kLPUART_RxCounter0TimeoutFlag = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */ + kLPUART_RxCounter1TimeoutFlag = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */ + kLPUART_TxCounter0TimeoutFlag = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */ + kLPUART_TxCounter1TimeoutFlag = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch2Flag = + LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ + kLPUART_DataMatch1Flag = + LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */ +#endif + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection. bit 16 */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any + of these samples differ, noise flag sets. bit 18 */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before + data is read from receive register. bit 19 */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected. bit 20 */ + kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the + receive data buffer is full. bit 21 */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */ + kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets + when active edge detected. bit 30 */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled. bit 31 */ +#endif + + kLPUART_AllClearFlags = +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeFlag | kLPUART_DsrStateChangeFlag | kLPUART_RinStateChangeFlag | + kLPUART_DcdStateChangeFlag | +#endif + kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag | kLPUART_RxOverrunFlag | + kLPUART_IdleLineFlag | kLPUART_RxActiveEdgeFlag +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch2Flag | kLPUART_DataMatch1Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , + + kLPUART_AllFlags = +#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR + kLPUART_CtsStateChangeFlag | kLPUART_DsrStateChangeFlag | kLPUART_RinStateChangeFlag | + kLPUART_DcdStateChangeFlag | +#endif + kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag | kLPUART_RxOverrunFlag | + kLPUART_IdleLineFlag | kLPUART_RxDataRegFullFlag | kLPUART_TransmissionCompleteFlag | + kLPUART_TxDataRegEmptyFlag | kLPUART_RxActiveFlag | kLPUART_RxActiveEdgeFlag +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag | kLPUART_TxFifoEmptyFlag | kLPUART_RxFifoEmptyFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch2Flag | kLPUART_DataMatch1Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , +}; + +/*! @brief LPUART timeout condition. + * This structure defines the conditions when the counter timeout occur. + */ +typedef enum _lpuart_timeout_condition +{ + kLPUART_TimeoutAfterCharacters = + 0U, /*!< Timeout occurs when the number of characters specified by timeoutValue are received. */ + kLPUART_TimeoutAfterIdle = 1U, /*!< Timeout occurs when rx/tx remains idle for timeoutValue of bit clocks after idle + condition is detected. */ + kLPUART_TimeoutAfterNext = 2U, /*!< Timeout occurs when rx/tx remains idle for timeoutValue of bit clocks after next + character is received/transmitted. */ + kLPUART_TimeoutAfterIdleBeforeExtended = 3U, /*!< Timeout occurs when tx/rx is idle for larger than timeoutValue of + bit clocks and smaller than tx/rx extended timeout value. */ +} lpuart_timeout_condition_t; + +/*! @brief LPUART timeout counter configuration structure. */ +typedef struct _lpuart_timeout_counter_config +{ + bool enableCounter; /*!< Eneble the timeout counter. */ + lpuart_timeout_condition_t timeoutCondition; /*!< Timeout condition. */ + uint16_t timeoutValue; /*!< Timeout value. */ +} lpuart_timeout_counter_config_t; + +/*! @brief LPUART timeout configuration structure. */ +typedef struct _lpuart_timeout_config +{ + uint16_t rxExtendedTimeoutValue; /*!< The number of bits since the last stop bit that is required for an + idle condition to be detected. Enable this will disable rxIdleType and rxIdleConfig. Set to 0 to disable. */ + uint16_t txExtendedTimeoutValue; /*!< The transmitter idle time in number of bits (baud rate) whenever an + idle character is queued through the transmit FIFO. */ + lpuart_timeout_counter_config_t rxCounter0; /*!< Rx counter 0 configuration. */ + lpuart_timeout_counter_config_t rxCounter1; /*!< Rx counter 1 configuration. */ + lpuart_timeout_counter_config_t txCounter0; /*!< Tx counter 0 configuration. */ + lpuart_timeout_counter_config_t txCounter1; /*!< Tx counter 1 configuration. */ +} lpuart_timeout_config_t; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + lpuart_timeout_config_t timeoutConfig; /*!< Timeout configuration. */ + bool enableSingleWire; /*!< Use TXD pin as the source for the receiver. When enabled the TXD pin should be + configured as open drain. */ + uint8_t rtsDelay; /*!< Delay the negation of RTS by the configured number of bit clocks. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif + bool is16bitData; /*!< 16bit data bits flag, only used for 9bit or 10bit data */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_irq_handler_t)(uint32_t instance, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART IRQ number. */ +extern const IRQn_Type s_lpuartIRQ[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} + +/*! + * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. + * + * This function Enable 16bit Data transmit in lpuart_handle_t. + * + * @param handle LPUART handle pointer. + * @param enable true to enable, false to disable. + */ +static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle,bool enable) +{ + handle->is16bitData = enable; +} + +/* @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); +/* @} */ + +/*! + * @name Module configuration + * @{ + */ +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base LPUART peripheral base address. + * @param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable); + +/*! + * @brief Set the LPUART address. + * + * This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address + * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being + * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one + * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in + * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with + * unmatched address. + * + * @note Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base LPUART peripheral base address. + * @param address1 LPUART slave address1. + * @param address2 LPUART slave address2. + */ +static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2) +{ + /* Configure match address. */ + uint32_t address = ((uint32_t)address2 << 16U) | (uint32_t)address1 | 0x1000100UL; + base->MATCH = address; +} + +/*! + * @brief Enable the LPUART match address feature. + * + * @param base LPUART peripheral base address. + * @param match1 true to enable match address1, false to disable. + * @param match2 true to enable match address2, false to disable. + */ +static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2) +{ + /* Configure match address1 enable bit. */ + if (match1) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN1_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN1_MASK; + } + /* Configure match address2 enable bit. */ + if (match2) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN2_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN2_MASK; + } +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_RXWATER_MASK) | LPUART_WATER_RXWATER(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water); +} +#endif +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of the enumeration _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); +/* @} */ + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @name DMA Configuration + * @{ + */ +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + uint8_t result; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) && + ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); + + if (isSevenDataBits) + { + result = (uint8_t)(base->DATA & 0x7FU); + } + else + { + result = (uint8_t)base->DATA; + } + + return result; +#else + return (uint8_t)(base->DATA); +#endif +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Gets the rx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +} +#endif + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base LPUART peripheral base address. + * @param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address); + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param instance LPUART instance. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_edma.c new file mode 100644 index 0000000000..6534965653 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_edma.c @@ -0,0 +1,510 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpuart_edma" +#endif + +/*base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle); + + /* Enable tx complete interrupt */ + LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(NULL != param); + + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (NULL != lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * + * note This function disables all LPUART interrupts. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = LPUART_GetInstance(base); + lpuart_to_lpflexcomm_edma_t handler; + + s_lpuartEdmaPrivateHandle[instance].base = base; + s_lpuartEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (NULL != rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + handler.lpuart_handler = LPUART_TransferEdmaHandleIRQ; + /* Save the handle in global variables to support the double weak mechanism. */ + LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPUART); + /* Disable all LPUART internal interrupts */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable); + /* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif + + /* Configure TX. */ + if (NULL != txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (NULL != rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success if succeed, others fail. + * retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * param instance LPUART peripheral index. + * param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(uint32_t instance, void *lpuartEdmaHandle) +{ + assert(lpuartEdmaHandle != NULL); + assert(instance < ARRAY_SIZE(s_lpuartBases)); + LPUART_Type *base = s_lpuartBases[instance]; + + if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U) + { + lpuart_edma_handle_t *handle = (lpuart_edma_handle_t *)lpuartEdmaHandle; + + /* Disable tx complete interrupt */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txState = (uint8_t)kLPUART_TxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_edma.h new file mode 100644 index 0000000000..2d25416da3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_edma.h @@ -0,0 +1,189 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPUART_EDMA_H_ +#define FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART EDMA driver version. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART eDMA handle + */ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * + * @note This function disables all LPUART interrupts. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * @note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * @param instance LPUART peripheral index. + * @param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(uint32_t instance, void *lpuartEdmaHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_freertos.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_freertos.c new file mode 100644 index 0000000000..f78a4dc9fa --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_freertos.c @@ -0,0 +1,489 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_freertos.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpflexcomm_lpuart_freertos" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void LPUART_RTOS_Callback(LPUART_Type *base, lpuart_handle_t *state, status_t status, void *param) +{ + lpuart_rtos_handle_t *handle = (lpuart_rtos_handle_t *)param; + BaseType_t xHigherPriorityTaskWoken, xResult; + + xHigherPriorityTaskWoken = pdFALSE; + xResult = pdFAIL; + + if (status == kStatus_LPUART_RxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RX_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_TxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_LPUART_TX_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_RxRingBufferOverrun) + { + xResult = + xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_LPUART_RxHardwareOverrun) + { + /* Clear Overrun flag (OR) in LPUART STAT register */ + (void)LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag); + xResult = + xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else + { + xResult = pdFAIL; + } + + if (xResult != pdFAIL) + { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Init + * Description : Initializes the LPUART instance for application + * + *END**************************************************************************/ +/*! + * brief Initializes an LPUART instance for operation in RTOS. + * + * param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context. + * param t_handle The pointer to an allocated space to store the transactional layer internal state. + * param cfg The pointer to the parameters required to configure the LPUART after initialization. + * return kStatus_Success, others failed + */ +int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg) +{ + status_t status; + lpuart_config_t defcfg; + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + if (NULL == t_handle) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg->base) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->srcclk) + { + return kStatus_InvalidArgument; + } + if (0u == cfg->baudrate) + { + return kStatus_InvalidArgument; + } + + handle->base = cfg->base; + handle->t_state = t_handle; + handle->rx_timeout_constant_ms = cfg->rx_timeout_constant_ms; + handle->rx_timeout_multiplier_ms = cfg->rx_timeout_multiplier_ms; + handle->tx_timeout_constant_ms = cfg->tx_timeout_constant_ms; + handle->tx_timeout_multiplier_ms = cfg->tx_timeout_multiplier_ms; + +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txSemaphore = xSemaphoreCreateMutexStatic(&handle->txSemaphoreBuffer); +#else + handle->txSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->txSemaphore) + { + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxSemaphore = xSemaphoreCreateMutexStatic(&handle->rxSemaphoreBuffer); +#else + handle->rxSemaphore = xSemaphoreCreateMutex(); +#endif + if (NULL == handle->rxSemaphore) + { + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->txEvent = xEventGroupCreateStatic(&handle->txEventBuffer); +#else + handle->txEvent = xEventGroupCreate(); +#endif + if (NULL == handle->txEvent) + { + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } +#if (configSUPPORT_STATIC_ALLOCATION == 1) + handle->rxEvent = xEventGroupCreateStatic(&handle->rxEventBuffer); +#else + handle->rxEvent = xEventGroupCreate(); +#endif + if (NULL == handle->rxEvent) + { + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + + LPUART_GetDefaultConfig(&defcfg); + + defcfg.baudRate_Bps = cfg->baudrate; + defcfg.parityMode = cfg->parity; + defcfg.stopBitCount = cfg->stopbits; +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + defcfg.enableRxRTS = cfg->enableRxRTS; + defcfg.enableTxCTS = cfg->enableTxCTS; + defcfg.txCtsSource = cfg->txCtsSource; + defcfg.txCtsConfig = cfg->txCtsConfig; +#endif + status = LPUART_Init(handle->base, &defcfg, cfg->srcclk); + if (status != kStatus_Success) + { + vEventGroupDelete(handle->rxEvent); + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + LPUART_TransferCreateHandle(handle->base, handle->t_state, LPUART_RTOS_Callback, handle); + LPUART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size); + + LPUART_EnableTx(handle->base, true); + LPUART_EnableRx(handle->base, true); + + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Deinit + * Description : Deinitializes the LPUART instance and frees resources + * + *END**************************************************************************/ +/*! + * brief Deinitializes an LPUART instance for operation. + * + * This function deinitializes the LPUART module, sets all register value to the reset value, + * and releases the resources. + * + * param handle The RTOS LPUART handle. + */ +int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle) +{ + LPUART_Deinit(handle->base); + + vEventGroupDelete(handle->txEvent); + vEventGroupDelete(handle->rxEvent); + + /* Give the semaphore. This is for functional safety */ + (void)xSemaphoreGive(handle->txSemaphore); + (void)xSemaphoreGive(handle->rxSemaphore); + + vSemaphoreDelete(handle->txSemaphore); + vSemaphoreDelete(handle->rxSemaphore); + + /* Invalidate the handle */ + handle->base = NULL; + handle->t_state = NULL; + + return 0; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_RTOS_Send + * Description : Send chars over LPUART + * + *END**************************************************************************/ +/*! + * brief Sends data in the background. + * + * This function sends data. It is an synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * param handle The RTOS LPUART handle. + * param buffer The pointer to buffer to send. + * param length The number of bytes to send. + */ +int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length) +{ + EventBits_t ev; + int retval = kStatus_Fail; + status_t status; + const TickType_t txTickTimeout = + (length * handle->tx_timeout_multiplier_ms + handle->tx_timeout_constant_ms) / portTICK_PERIOD_MS; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0u)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->txTransfer.data = (uint8_t *)buffer; + handle->txTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = LPUART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->txSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE, pdTRUE, pdFALSE, + (txTickTimeout > 0u) ? txTickTimeout : portMAX_DELAY); + if ((ev & RTOS_LPUART_TX_COMPLETE) != 0u) + { + retval = kStatus_Success; + } + else /* timeout expired or unknown error*/ + { + if (txTickTimeout > 0u) + { + LPUART_TransferAbortSend(handle->base, handle->t_state); + (void)xEventGroupClearBits(handle->txEvent, RTOS_LPUART_TX_COMPLETE); + retval = kStatus_Timeout; + } + else + { + retval = kStatus_Fail; + } + } + + if (pdFALSE == xSemaphoreGive(handle->txSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_Receive + * Description : Receives chars from LPUART + * + *END**************************************************************************/ +/*! + * brief Receives data. + * + * This function receives data from LPUART. It is an synchronous API. If any data is immediately available + * it is returned immediately and the number of bytes received. + * + * param handle The RTOS LPUART handle. + * param buffer The pointer to buffer where to write received data. + * param length The number of bytes to receive. + * param received The pointer to a variable of size_t where the number of received data is filled. + */ +int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received) +{ + EventBits_t ev; + size_t n = 0u; + int retval = kStatus_Fail; + uint32_t local_received = 0u; + status_t status; + const TickType_t rxTickTimeout = + (length * handle->rx_timeout_multiplier_ms + handle->rx_timeout_constant_ms) / portTICK_PERIOD_MS; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0u == length) + { + if (received != NULL) + { + *received = n; + } + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + /* New transfer can be performed only after current one is finished */ + if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->rxTransfer.data = buffer; + handle->rxTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = LPUART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->rxSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits( + handle->rxEvent, + RTOS_LPUART_RX_COMPLETE | RTOS_LPUART_RING_BUFFER_OVERRUN | RTOS_LPUART_HARDWARE_BUFFER_OVERRUN, pdTRUE, + pdFALSE, (rxTickTimeout > 0u) ? rxTickTimeout : portMAX_DELAY); + if ((ev & RTOS_LPUART_HARDWARE_BUFFER_OVERRUN) != 0u) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + LPUART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. + RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_LPUART_RxHardwareOverrun; + local_received = 0u; + } + else if ((ev & RTOS_LPUART_RING_BUFFER_OVERRUN) != 0u) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + LPUART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of LPUART_RTOS_Receive. + RTOS_LPUART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_LPUART_RxRingBufferOverrun; + local_received = 0u; + } + else if ((ev & RTOS_LPUART_RX_COMPLETE) != 0u) + { + retval = kStatus_Success; + local_received = length; + } + else /* timeout expired or unknown error*/ + { + if (rxTickTimeout > 0u) + { + (void)LPUART_TransferGetReceiveCount(handle->base, handle->t_state, &local_received); + LPUART_TransferAbortReceive(handle->base, handle->t_state); + (void)xEventGroupClearBits(handle->rxEvent, RTOS_LPUART_RX_COMPLETE); + retval = kStatus_Timeout; + } + else + { + retval = kStatus_LPUART_Error; + local_received = 0u; + } + } + + /* Prevent repetitive NULL check */ + if (received != NULL) + { + *received = (size_t)local_received; + } + + /* Enable next transfer. Current one is finished */ + if (pdFALSE == xSemaphoreGive(handle->rxSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_SetRxTimeout + * Description : Modify receive timeout value in alreaty initialized LPUART RTOS handle. + * + *END**************************************************************************/ +/*! + * brief Set RX timeout in runtime + * + * This function can modify RX timeout between initialization and receive. + * + * param handle The RTOS LPUART handle. + * param rx_timeout_constant_ms RX timeout applied per receive. + * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive. + */ +int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle, + uint32_t rx_timeout_constant_ms, + uint32_t rx_timeout_multiplier_ms) +{ + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + handle->rx_timeout_constant_ms = rx_timeout_constant_ms; + handle->rx_timeout_multiplier_ms = rx_timeout_multiplier_ms; + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : LPUART_RTOS_SetTxTimeout + * Description : Modify send timeout value in alreaty initialized LPUART RTOS handle. + * + *END**************************************************************************/ +/*! + * brief Set TX timeout in runtime + * + * This function can modify TX timeout between initialization and send. + * + * param handle The RTOS LPUART handle. + * param tx_timeout_constant_ms TX timeout applied per transmition. + * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition. + */ +int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle, + uint32_t tx_timeout_constant_ms, + uint32_t tx_timeout_multiplier_ms) +{ + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + handle->tx_timeout_constant_ms = tx_timeout_constant_ms; + handle->tx_timeout_multiplier_ms = tx_timeout_multiplier_ms; + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_freertos.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_freertos.h new file mode 100644 index 0000000000..57d453da16 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_lpuart_freertos.h @@ -0,0 +1,192 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPUART_FREERTOS_H__ +#define FSL_LPUART_FREERTOS_H__ + +#include "fsl_lpuart.h" +#include "FreeRTOS.h" +#include "event_groups.h" +#include "semphr.h" + +/*! + * @addtogroup lpuart_freertos_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART FreeRTOS driver version 2.0.0. */ +#define FSL_LPUART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief LPUART RTOS configuration structure. */ +typedef struct _lpuart_rtos_config +{ + LPUART_Type *base; /*!< UART base address */ + uint32_t srcclk; /*!< UART source clock in Hz*/ + uint32_t baudrate; /*!< Desired communication speed */ + lpuart_parity_mode_t parity; /*!< Parity setting */ + lpuart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */ + uint8_t *buffer; /*!< Buffer for background reception */ + uint32_t buffer_size; /*!< Size of buffer for background reception */ + /* Zero in constant and multiplier is interpreted as infinit timeout. */ + uint32_t rx_timeout_constant_ms; /*!< RX timeout applied per receive */ + uint32_t rx_timeout_multiplier_ms; /*!< RX timeout added for each byte of the receive. */ + uint32_t tx_timeout_constant_ms; /*!< TX timeout applied per transmition */ + uint32_t tx_timeout_multiplier_ms; /*!< TX timeout added for each byte of the transmition. */ +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif +} lpuart_rtos_config_t; + +/*! + * @cond RTOS_PRIVATE + * @name LPUART event flags + * + * This are only valid states for txEvent and rxEvent (lpuart_rtos_handle_t). + */ +/*@{*/ +/*! @brief Event flag - uart transmit complete. */ +#define RTOS_LPUART_TX_COMPLETE 0x1U +/*! @brief Event flag - uart receive complete. */ +#define RTOS_LPUART_RX_COMPLETE 0x2U +/*! @brief Event flag - ring buffer overrun. */ +#define RTOS_LPUART_RING_BUFFER_OVERRUN 0x4U +/*! @brief Event flag - hardware buffer overrun. */ +#define RTOS_LPUART_HARDWARE_BUFFER_OVERRUN 0x8U +/*@}*/ + +/*! @brief LPUART FreeRTOS transfer structure. */ +typedef struct _lpuart_rtos_handle +{ + LPUART_Type *base; /*!< UART base address */ + lpuart_transfer_t txTransfer; /*!< TX transfer structure */ + lpuart_transfer_t rxTransfer; /*!< RX transfer structure */ + SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */ + SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */ + EventGroupHandle_t rxEvent; /*!< RX completion event */ + EventGroupHandle_t txEvent; /*!< TX completion event */ + uint32_t rx_timeout_constant_ms; /*!< RX Timeout applied per transfer */ + uint32_t rx_timeout_multiplier_ms; /*!< RX Timeout added for each byte of the transfer. */ + uint32_t tx_timeout_constant_ms; /*!< TX Timeout applied per transfer */ + uint32_t tx_timeout_multiplier_ms; /*!< TX Timeout added for each byte of the transfer. */ + void *t_state; /*!< Transactional state of the underlying driver */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t txSemaphoreBuffer; /*!< Statically allocated memory for txSemaphore */ + StaticSemaphore_t rxSemaphoreBuffer; /*!< Statically allocated memory for rxSemaphore */ + StaticEventGroup_t txEventBuffer; /*!< Statically allocated memory for txEvent */ + StaticEventGroup_t rxEventBuffer; /*!< Statically allocated memory for rxEvent */ +#endif +} lpuart_rtos_handle_t; +/*! \endcond */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPUART RTOS Operation + * @{ + */ + +/*! + * @brief Initializes an LPUART instance for operation in RTOS. + * + * @param handle The RTOS LPUART handle, the pointer to an allocated space for RTOS context. + * @param t_handle The pointer to an allocated space to store the transactional layer internal state. + * @param cfg The pointer to the parameters required to configure the LPUART after initialization. + * @return 0 succeed, others failed + */ +int LPUART_RTOS_Init(lpuart_rtos_handle_t *handle, lpuart_handle_t *t_handle, const lpuart_rtos_config_t *cfg); + +/*! + * @brief Deinitializes an LPUART instance for operation. + * + * This function deinitializes the LPUART module, sets all register value to the reset value, + * and releases the resources. + * + * @param handle The RTOS LPUART handle. + */ +int LPUART_RTOS_Deinit(lpuart_rtos_handle_t *handle); + +/*! + * @name LPUART transactional Operation + * @{ + */ + +/*! + * @brief Sends data in the background. + * + * This function sends data. It is an synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * @param handle The RTOS LPUART handle. + * @param buffer The pointer to buffer to send. + * @param length The number of bytes to send. + */ +int LPUART_RTOS_Send(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length); + +/*! + * @brief Receives data. + * + * This function receives data from LPUART. It is an synchronous API. If any data is immediately available + * it is returned immediately and the number of bytes received. + * + * @param handle The RTOS LPUART handle. + * @param buffer The pointer to buffer where to write received data. + * @param length The number of bytes to receive. + * @param received The pointer to a variable of size_t where the number of received data is filled. + */ +int LPUART_RTOS_Receive(lpuart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received); + +/*! + * @brief Set RX timeout in runtime + * + * This function can modify RX timeout between initialization and receive. + * + * param handle The RTOS LPUART handle. + * param rx_timeout_constant_ms RX timeout applied per receive. + * param rx_timeout_multiplier_ms RX timeout added for each byte of the receive. + */ +int LPUART_RTOS_SetRxTimeout(lpuart_rtos_handle_t *handle, + uint32_t rx_timeout_constant_ms, + uint32_t rx_timeout_multiplier_ms); + +/*! + * @brief Set TX timeout in runtime + * + * This function can modify TX timeout between initialization and send. + * + * param handle The RTOS LPUART handle. + * param tx_timeout_constant_ms TX timeout applied per transmition. + * param tx_timeout_multiplier_ms TX timeout added for each byte of the transmition. + */ +int LPUART_RTOS_SetTxTimeout(lpuart_rtos_handle_t *handle, + uint32_t tx_timeout_constant_ms, + uint32_t tx_timeout_multiplier_ms); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_FREERTOS_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_mrt.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_mrt.c new file mode 100644 index 0000000000..69697a21b5 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_mrt.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_mrt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mrt" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Multi-Rate timer peripheral base address + * + * @return The MRT instance + */ +static uint32_t MRT_GetInstance(MRT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to MRT bases for each instance. */ +static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to MRT clocks for each instance. */ +static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(MRT_RSTS_N) +/*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; +#elif defined(MRT_RSTS) +/*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t MRT_GetInstance(MRT_Type *base) +{ + uint32_t instance; + uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < mrtArrayCount; instance++) + { + if (s_mrtBases[instance] == base) + { + break; + } + } + + assert(instance < mrtArrayCount); + + return instance; +} + +/*! + * brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the MRT driver. + * + * param base Multi-Rate timer peripheral base address + * param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the MRT clock */ + CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(MRT_RSTS_N) || defined(MRT_RSTS) + /* Reset the module. */ + RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Set timer operating mode */ + base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask); +#endif +} + +/*! + * brief Gate the MRT clock + * + * param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base) +{ + /* Stop all the timers */ + MRT_StopTimer(base, kMRT_Channel_0); + MRT_StopTimer(base, kMRT_Channel_1); +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 2U) + MRT_StopTimer(base, kMRT_Channel_2); +#endif +#if (FSL_FEATURE_MRT_NUMBER_OF_CHANNELS > 3U) + MRT_StopTimer(base, kMRT_Channel_3); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the MRT clock*/ + CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * param base Multi-Rate timer peripheral base address + * param channel Timer channel number + * param count Timer period in units of ticks + * param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t newValue = count; + if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) + { + /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ + newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; + } + + /* Update the timer interval value */ + base->CHANNEL[channel].INTVAL = newValue; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_mrt.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_mrt.h new file mode 100644 index 0000000000..3d398a0f93 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_mrt.h @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_MRT_H_ +#define FSL_MRT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mrt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ +/*@}*/ + +/*! @brief List of MRT channels */ +typedef enum _mrt_chnl +{ + kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/ + kMRT_Channel_1, /*!< MRT channel number 1 */ + kMRT_Channel_2, /*!< MRT channel number 2 */ + kMRT_Channel_3 /*!< MRT channel number 3 */ +} mrt_chnl_t; + +/*! @brief List of MRT timer modes */ +typedef enum _mrt_timer_mode +{ + kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */ + kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */ + kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */ +} mrt_timer_mode_t; + +/*! @brief List of MRT interrupts */ +typedef enum _mrt_interrupt_enable +{ + kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/ +} mrt_interrupt_enable_t; + +/*! @brief List of MRT status flags */ +typedef enum _mrt_status_flags +{ + kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */ + kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */ +} mrt_status_flags_t; + +/*! + * @brief MRT configuration structure + * + * This structure holds the configuration settings for the MRT peripheral. To initialize this + * structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _mrt_config +{ + bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */ +} mrt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the MRT clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the MRT driver. + * + * @param base Multi-Rate timer peripheral base address + * @param config Pointer to user's MRT config structure. If MRT has MULTITASK bit field in + * MODCFG reigster, param config is useless. + */ +void MRT_Init(MRT_Type *base, const mrt_config_t *config); + +/*! + * @brief Gate the MRT clock + * + * @param base Multi-Rate timer peripheral base address + */ +void MRT_Deinit(MRT_Type *base); + +/*! + * @brief Fill in the MRT config struct with the default settings + * + * The default values are: + * @code + * config->enableMultiTask = false; + * @endcode + * @param config Pointer to user's MRT config structure. + */ +static inline void MRT_GetDefaultConfig(mrt_config_t *config) +{ + assert(config != NULL); +#if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) + /* Use hardware status operating mode */ + config->enableMultiTask = false; +#endif +} + +/*! + * @brief Sets up an MRT channel mode. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Channel that is being configured. + * @param mode Timer mode to use for the channel. + */ +static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].CTRL; + + /* Clear old value */ + reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; + /* Add the new mode */ + reg |= (uint32_t)mode; + + base->CHANNEL[channel].CTRL = reg; +} + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL |= mask; +} + +/*! + * @brief Disables the selected MRT interrupt. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].CTRL &= ~mask; +} + +/*! + * @brief Gets the enabled MRT interrupts. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::mrt_interrupt_enable_t + */ +static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the MRT status flags + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); +} + +/*! + * @brief Clears the MRT status flags. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::mrt_status_flags_t + */ +static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Used to update the timer period in units of count. + * + * The new value will be immediately loaded or will be loaded at the end of the current time + * interval. For one-shot interrupt mode the new value will be immediately loaded. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + * @param immediateLoad true: Load the new value immediately into the TIMER register; + * false: Load the new value at the end of current timer interval + */ +void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad); + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + return base->CHANNEL[channel].TIMER; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, counts down to 0 and + * depending on the timer mode it will either load the respective start value again or stop. + * + * @note User can call the utility macros provided in fsl_common.h to convert to ticks + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. + */ +static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); + /* Write the timer interval value */ + base->CHANNEL[channel].INTVAL = count; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops the timer from counting. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + /* Stop the timer immediately */ + base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; +} + +/*! @}*/ + +/*! + * @name Get & release channel + * @{ + */ + +/*! + * @brief Find the available channel. + * + * This function returns the lowest available channel number. + * + * @param base Multi-Rate timer peripheral base address + */ +static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) +{ + return base->IDLE_CH; +} + +#if !(defined(FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) && FSL_FEATURE_MRT_HAS_NO_CHANNEL_STAT_INUSE) +/*! + * @brief Release the channel when the timer is using the multi-task mode. + * + * In multi-task mode, the INUSE flags allow more control over when MRT channels are released for + * further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as + * long as it is needed and release it by calling this function. This removes the need to ask for + * an available channel for every use. + * + * @param base Multi-Rate timer peripheral base address + * @param channel Timer channel number. + */ +static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) +{ + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + + uint32_t reg = base->CHANNEL[channel].STAT; + + /* Clear flag bits to prevent accidentally clearing anything when writing back */ + reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK; + reg |= MRT_CHANNEL_STAT_INUSE_MASK; + + base->CHANNEL[channel].STAT = reg; +} +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_MRT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ostimer.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ostimer.c new file mode 100644 index 0000000000..42feaf04a3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ostimer.c @@ -0,0 +1,394 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ostimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ostimer" +#endif + +#if defined(OSTIMER_RSTS) +#define OSTIMER_RESETS_ARRAY OSTIMER_RSTS +#endif + +/* Typedef for interrupt handler. */ +typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base OSTIMER peripheral base address + * + * @return The OSTIMER instance + */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of OSTIMER handle. */ +static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; +/* Array of OSTIMER peripheral base address. */ +static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; +/* Array of OSTIMER IRQ number. */ +static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of OSTIMER clock name. */ +static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* OSTIMER ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; +#else +static ostimer_isr_t s_ostimerIsr; +#endif + +#if defined(OSTIMER_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_ostimerResets[] = OSTIMER_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* @brief Function for getting the instance number of OS timer. */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) + { + if (s_ostimerBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ostimerBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) +{ + uint64_t decOut; + + SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); + SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer + __NOP(); + decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; + decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); + + return decOut; +} +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/* @brief Translate the value from gray-code to decimal. */ +/* + * @param gray The gray value input. + * + * @return the decimal value. + */ +uint64_t OSTIMER_GrayToDecimal(uint64_t gray) +{ +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + return OSTIMER_GrayToDecimalbyCodeGray(gray); +#else + uint64_t temp = gray; + while (temp != 0U) + { + temp >>= 1U; + gray ^= temp; + } + + return gray; +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +} + +/* @brief Enable the OSTIMER interrupt. + * + * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. + * + * @param base OSTIMER peripheral base address. + * @param enable enable/disable the IRQ and module interrupt enablement. + * - true: Disable the IRQ and module interrupt enablement. + * - false: Disable the IRQ and module interrupt enablement. + * @return none + */ +static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) +{ + assert(NULL != base); + + if (enable) + { + /* Enable the IRQ and module interrupt enablement. */ + (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; + } + else + { + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ + } +} + +/*! + * @brief Initializes an OSTIMER by turning it's clock on. + * + */ +void OSTIMER_Init(OSTIMER_Type *base) +{ + assert(NULL != base); + + uint32_t instance = OSTIMER_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) + /* Enable the OSTIMER 32k clock in PMC module. */ + CLOCK_EnableOstimer32kClock(); +#endif + /* Enable clock for OSTIMER. */ + CLOCK_EnableClock(s_ostimerClock[instance]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_EnableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(OSTIMER_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_ostimerResets[OSTIMER_GetInstance(base)]); +#endif +} + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable clock for OSTIMER. */ + CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_DisableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) +{ + return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; +} + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) +{ + base->OSEVENT_CTRL |= mask; +} + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + uint64_t decValueTimer; +#endif + status_t status; + uint64_t tmp = count; + uint32_t instance = OSTIMER_GetInstance(base); + + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + s_ostimerIsr = OSTIMER_HandleIRQ; + s_ostimerHandle[instance] = cb; + + /* Set the match value. */ + base->MATCH_L = (uint32_t)tmp; + base->MATCH_H = (uint32_t)(tmp >> 32U); + +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Workaround-2019-12-30: + * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match + * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is + * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it + * should not be necessary to test this bit", but we found the interruption would not be reported when the delta + * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such + * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. + */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } + + /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. + * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit + * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable + * interrupt and return success; if not, we will return fail directly. + * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. + */ + decValueTimer = OSTIMER_GetCurrentTimerValue(base); + if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && + (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) + { + status = kStatus_Fail; + } + else +#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ + { + /* Enable the module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, true); + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in + * API. ) + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ + uint64_t tmp = OSTIMER_DecimalToGray(count); + + return OSTIMER_SetMatchRawValue(base, tmp, cb); +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCurrentTimerRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCaptureRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) +{ + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + if (cb != NULL) + { + cb(); + } +} + +#if defined(OSTIMER0) +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(OSTIMER) +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ostimer.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ostimer.h new file mode 100644 index 0000000000..0cd991ef44 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_ostimer.h @@ -0,0 +1,273 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_OSTIMER_H_ +#define FSL_OSTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ostimer + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief OSTIMER driver version. */ +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +/*! + * @brief OSTIMER status flags. + */ +enum _ostimer_flags +{ + kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if + the match value was reached. */ +}; + +/*! @brief ostimer callback function. */ +typedef void (*ostimer_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an OSTIMER by turning its bus clock on + * + */ +void OSTIMER_Init(OSTIMER_Type *base); + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER bus clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base); + +/*! + * @brief Translate the value from gray-code to decimal. + * + * @param gray The gray value input. + * @return The decimal value. + */ +uint64_t OSTIMER_GrayToDecimal(uint64_t gray); + +/*! + * @brief Translate the value from decimal to gray-code. + * + * @param dec The decimal value. + * @return The gray code of the input value. + */ +static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) +{ + return (dec ^ (dec >> 1U)); +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intrrupt status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code + * internally.) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set value to OSTIMER MATCH register directly. + * + * This function writes the input value to OSTIMER MATCH register directly, + * it does not touch any other registers. Note that, the data format is + * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal + * value to gray code. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value (Value is gray-code format). + */ +static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Wait for MATCH register ready for write. */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } +#endif + + base->MATCH_L = (uint32_t)value; + base->MATCH_H = (uint32_t)(value >> 32U); +} + +/*! + * @brief Enable the OSTIMER counter match interrupt. + * + * Enable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} + +/*! + * @brief Disable the OSTIMER counter match interrupt. + * + * Disable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} + +/*! + * @brief Get current timer raw count value from OSTIMER. + * + * This function will get a gray code type timer count value from OS timer register. + * The raw value of timer count is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of OSTIMER, gray code format. + */ +static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->EVTIMERL; + tmp |= (uint64_t)(base->EVTIMERH) << 32U; + + return tmp; +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will be formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a captured gray-code value from OSTIMER. + * The Raw value of timer capture is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of capture register, data format is gray code. + */ +static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->CAPTURE_L; + tmp |= (uint64_t)(base->CAPTURE_H) << 32U; + + return tmp; +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); + +/*! + * @brief OS timer interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in OSTIMER_SetMatchValue()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base OS timer peripheral base address. + * @param cb callback scheduled for this instance of OS timer + * @return none + */ +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm.c new file mode 100644 index 0000000000..2132ed2a1d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm.c @@ -0,0 +1,969 @@ +/* + * Copyright (c) 2018, Freescale Semiconductor, Inc. + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pdm.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pdm" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/*! @brief Typedef for pdm rx interrupt handler. */ +typedef void (*pdm_isr_t)(PDM_Type *base, pdm_handle_t *pdmHandle); +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) +/*! + * @brief Get the instance number for PDM. + * + * @param channelMask enabled channel. + * @param qualitymode selected quality mode. + * @param osr oversample rate. + * @param regdiv register divider. + */ +static status_t PDM_ValidateSrcClockRate(uint32_t channelMask, + pdm_df_quality_mode_t qualityMode, + uint8_t osr, + uint32_t regDiv); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static PDM_Type *const s_pdmBases[] = PDM_BASE_PTRS; +/*!@brief PDM handle pointer */ +static pdm_handle_t *s_pdmHandle[ARRAY_SIZE(s_pdmBases)]; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_pdmClock[] = PDM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_PDM_HAS_FILTER_CLOCK_GATE) && FSL_PDM_HAS_FILTER_CLOCK_GATE +/* Clock name array */ +static const clock_ip_name_t s_pdmFilterClock[] = PDM_FILTER_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to tx IRQ handler for each instance. */ +static pdm_isr_t s_pdmIsr; +#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) +/*! @brief callback for hwvad. */ +static pdm_hwvad_notification_t s_pdm_hwvad_notification[ARRAY_SIZE(s_pdmBases)]; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t PDM_GetInstance(PDM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pdmBases); instance++) + { + if (s_pdmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pdmBases)); + + return instance; +} + +/*! + * brief PDM read fifo. + * Note: This function support 16 bit only for IP version that only supports 16bit. + * + * param base PDM base pointer. + * param startChannel start channel number. + * param channelNums total enabled channelnums. + * param buffer received buffer address. + * param size number of samples to read. + * param dataWidth sample width. + */ +void PDM_ReadFifo( + PDM_Type *base, uint32_t startChannel, uint32_t channelNums, void *buffer, size_t size, uint32_t dataWidth) +{ + uint32_t i = 0, j = 0U; + uint32_t *dataAddr = (uint32_t *)buffer; + + for (i = 0U; i < size; i++) + { + for (j = 0; j < channelNums; j++) + { +#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH != 2U) + *dataAddr = base->DATACH[startChannel + j] >> (dataWidth == 4U ? 0U : 8U); + dataAddr = (uint32_t *)((uint32_t)dataAddr + dataWidth); +#else + *dataAddr = base->DATACH[startChannel + j]; + dataAddr = (uint32_t *)((uint32_t)dataAddr + 2U); +#endif + } + } +} + +#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH == 2U) +/*! + * brief PDM read data non blocking, only support 16bit data read. + * So the actually read data byte size in this function is (size * 2 * channelNums). + * param base PDM base pointer. + * param startChannel start channel number. + * param channelNums total enabled channelnums. + * param buffer received buffer address. + * param size number of 16bit data to read. + */ +void PDM_ReadNonBlocking(PDM_Type *base, uint32_t startChannel, uint32_t channelNums, int16_t *buffer, size_t size) +{ + uint32_t i = 0, j = 0U; + + for (i = 0U; i < size; i++) + { + for (j = 0; j < channelNums; j++) + { + *buffer++ = (int16_t)base->DATACH[startChannel + j]; + } + } +} +#endif + +#if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) +static status_t PDM_ValidateSrcClockRate(uint32_t channelMask, + pdm_df_quality_mode_t qualityMode, + uint8_t osr, + uint32_t regDiv) +{ + uint32_t enabledChannel = 0U, i = 0U, factor = 0U, k = 0U; + + for (i = 0U; i < (uint32_t)FSL_FEATURE_PDM_CHANNEL_NUM; i++) + { + if (((channelMask >> i) & 0x01U) != 0U) + { + enabledChannel++; + } + } + + switch (qualityMode) + { + case kPDM_QualityModeMedium: + factor = FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR; + k = 2U; + break; + + case kPDM_QualityModeHigh: + factor = FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR; + k = 1U; + break; + + case kPDM_QualityModeLow: + factor = FSL_FEATURE_PDM_HIGH_QUALITY_CLKDIV_FACTOR; + k = 4U; + break; + + case kPDM_QualityModeVeryLow0: + factor = FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR; + k = 2U; + break; + + case kPDM_QualityModeVeryLow1: + factor = FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR; + k = 4U; + break; + + case kPDM_QualityModeVeryLow2: + factor = FSL_FEATURE_PDM_VERY_LOW_QUALITY_CLKDIV_FACTOR; + k = 8U; + break; + + default: + assert(false); + break; + } + + /* validate the minimum clock divider */ + /* 2U is for canculating k, 100U is for determing the specific float number of clock divider */ + if (((regDiv * k) / 2U * 100U) < (((10U + factor * enabledChannel) * 100U / (8U * osr)) * k / 2U)) + { + return kStatus_Fail; + } + + return kStatus_Success; +} +#endif + +/*! + * brief PDM set sample rate. + * + * note This function is depend on the configuration of the PDM and PDM channel, so the correct call sequence is + * code + * PDM_Init(base, pdmConfig) + * PDM_SetChannelConfig(base, channel, &channelConfig) + * PDM_SetSampleRateConfig(base, source, sampleRate) + * endcode + * param base PDM base pointer + * param sourceClock_HZ PDM source clock frequency. + * param sampleRate_HZ PDM sample rate. + */ +status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32_t sampleRate_HZ) +{ + uint32_t osr = (base->CTRL_2 & PDM_CTRL_2_CICOSR_MASK) >> PDM_CTRL_2_CICOSR_SHIFT; +#if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) + pdm_df_quality_mode_t qualityMode = + (pdm_df_quality_mode_t)(uint32_t)((base->CTRL_2 & PDM_CTRL_2_QSEL_MASK) >> PDM_CTRL_2_QSEL_SHIFT); + uint32_t enabledChannelMask = base->CTRL_1 & (uint32_t)kPDM_EnableChannelAll; +#endif + + uint32_t pdmClockRate = 0U; + uint32_t regDiv = 0U; + + /* get divider */ + osr = (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT) + 1U - osr; + pdmClockRate = sampleRate_HZ * osr * 8U; + regDiv = sourceClock_HZ / pdmClockRate; + + if (regDiv > PDM_CTRL_2_CLKDIV_MASK) + { + return kStatus_Fail; + } + +#if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) + if (PDM_ValidateSrcClockRate(enabledChannelMask, qualityMode, (uint8_t)osr, regDiv) == kStatus_Fail) + { + return kStatus_Fail; + } +#endif + + base->CTRL_2 = (base->CTRL_2 & (~PDM_CTRL_2_CLKDIV_MASK)) | PDM_CTRL_2_CLKDIV(regDiv); + + return kStatus_Success; +} + +/*! + * brief PDM set sample rate. + * + * deprecated Do not use this function. It has been superceded by @ref PDM_SetSampleRateConfig + * param base PDM base pointer + * param enableChannelMask PDM channel enable mask. + * param qualityMode quality mode. + * param osr cic oversample rate + * param clkDiv clock divider + */ +status_t PDM_SetSampleRate( + PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv) +{ +#if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) + uint8_t realOsr = (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT) + 1U - + (osr & (PDM_CTRL_2_CICOSR_MASK >> PDM_CTRL_2_CICOSR_SHIFT)); +#endif + uint32_t regDiv = clkDiv >> 1U; + + switch (qualityMode) + { + case kPDM_QualityModeHigh: + regDiv <<= 1U; + break; + case kPDM_QualityModeLow: + case kPDM_QualityModeVeryLow1: + regDiv >>= 1U; + break; + case kPDM_QualityModeVeryLow2: + regDiv >>= 2U; + break; + default: + assert(false); + break; + } + +#if !(defined FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV && FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV) + if (PDM_ValidateSrcClockRate(enableChannelMask, qualityMode, realOsr, regDiv) == kStatus_Fail) + { + return kStatus_Fail; + } +#endif + + assert(regDiv <= PDM_CTRL_2_CLKDIV_MASK); + base->CTRL_2 = (base->CTRL_2 & (~PDM_CTRL_2_CLKDIV_MASK)) | PDM_CTRL_2_CLKDIV(regDiv); + + return kStatus_Success; +} + +/*! + * brief Initializes the PDM peripheral. + * + * Ungates the PDM clock, resets the module, and configures PDM with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * PDM_GetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the PDM driver. Otherwise, accessing the PDM module can cause a hard fault + * because the clock is not enabled. + * + * param base PDM base pointer + * param config PDM configuration structure. + */ +void PDM_Init(PDM_Type *base, const pdm_config_t *config) +{ + assert(config != NULL); + assert(config->fifoWatermark <= PDM_FIFO_CTRL_FIFOWMK_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the PDM clock */ + CLOCK_EnableClock(s_pdmClock[PDM_GetInstance(base)]); +#if defined(FSL_PDM_HAS_FILTER_CLOCK_GATE) && FSL_PDM_HAS_FILTER_CLOCK_GATE + CLOCK_EnableClock(s_pdmFilterClock[PDM_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Enable the module and disable the interface/all channel */ + base->CTRL_1 &= + ~(PDM_CTRL_1_MDIS_MASK | PDM_CTRL_1_PDMIEN_MASK | PDM_CTRL_1_ERREN_MASK | (uint32_t)kPDM_EnableChannelAll); + + /* wait all filter stopped */ + while ((base->STAT & PDM_STAT_BSY_FIL_MASK) != 0U) + { + } + + /* software reset */ + base->CTRL_1 |= PDM_CTRL_1_SRES_MASK; + + /* Set the configure settings */ +#if !(defined(FSL_FEATURE_PDM_HAS_NO_DOZEN) && FSL_FEATURE_PDM_HAS_NO_DOZEN) + PDM_EnableDoze(base, config->enableDoze); +#endif + base->CTRL_2 = (base->CTRL_2 & (~(PDM_CTRL_2_CICOSR_MASK | PDM_CTRL_2_QSEL_MASK))) | + PDM_CTRL_2_CICOSR(config->cicOverSampleRate) | PDM_CTRL_2_QSEL(config->qualityMode); + +#if defined(FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS) && FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS + base->CTRL_2 = (base->CTRL_2 & ~PDM_CTRL_2_DEC_BYPASS_MASK) | PDM_CTRL_2_DEC_BYPASS(config->enableFilterBypass); +#endif + /* Set the watermark */ + base->FIFO_CTRL = PDM_FIFO_CTRL_FIFOWMK(config->fifoWatermark); +} + +/*! + * brief De-initializes the PDM peripheral. + * + * This API gates the PDM clock. The PDM module can't operate unless PDM_Init + * is called to enable the clock. + * + * param base PDM base pointer + */ +void PDM_Deinit(PDM_Type *base) +{ + /* disable PDM interface */ + PDM_DisableInterrupts(base, (uint32_t)kPDM_FIFOInterruptEnable | (uint32_t)kPDM_ErrorInterruptEnable); + PDM_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_pdmClock[PDM_GetInstance(base)]); +#if defined(FSL_PDM_HAS_FILTER_CLOCK_GATE) && FSL_PDM_HAS_FILTER_CLOCK_GATE + CLOCK_DisableClock(s_pdmFilterClock[PDM_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Enables the PDM interrupt requests. + * + * param base PDM base pointer + * param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * arg kPDM_ErrorInterruptEnable + * arg kPDM_FIFOInterruptEnable + */ +void PDM_EnableInterrupts(PDM_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kPDM_FIFOInterruptEnable) != 0U) + { + base->CTRL_1 = (base->CTRL_1 & (~PDM_CTRL_1_DISEL_MASK)) | (uint32_t)kPDM_FIFOInterruptEnable; + } + if ((mask & (uint32_t)kPDM_ErrorInterruptEnable) != 0U) + { + base->CTRL_1 = (base->CTRL_1 & (~PDM_CTRL_1_ERREN_MASK)) | (uint32_t)kPDM_ErrorInterruptEnable; + } +} + +/*! + * brief PDM one channel configurations. + * + * param base PDM base pointer + * param config PDM channel configurations. + * param channel channel number. + * after completing the current frame in debug mode. + */ +void PDM_SetChannelConfig(PDM_Type *base, uint32_t channel, const pdm_channel_config_t *config) +{ + assert(config != NULL); + assert(channel <= (uint32_t)FSL_FEATURE_PDM_CHANNEL_NUM); + + uint32_t dcCtrl = 0U; + +#if (defined(FSL_FEATURE_PDM_HAS_DC_OUT_CTRL) && (FSL_FEATURE_PDM_HAS_DC_OUT_CTRL)) + dcCtrl = base->DC_OUT_CTRL; + /* configure gain and cut off freq */ + dcCtrl &= ~((uint32_t)PDM_DC_OUT_CTRL_DCCONFIG0_MASK << (channel << 1U)); + dcCtrl |= (uint32_t)config->outputCutOffFreq << (channel << 1U); + base->DC_OUT_CTRL = dcCtrl; +#endif + +#if !(defined(FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED) && (FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED)) + dcCtrl = base->DC_CTRL; + /* configure gain and cut off freq */ + dcCtrl &= ~((uint32_t)PDM_DC_CTRL_DCCONFIG0_MASK << (channel << 1U)); + dcCtrl |= (uint32_t)config->cutOffFreq << (channel << 1U); + base->DC_CTRL = dcCtrl; +#endif + + PDM_SetChannelGain(base, channel, config->gain); + + /* enable channel */ + base->CTRL_1 |= 1UL << channel; +} + +/*! + * brief Set the PDM channel gain. + * + * Please note for different quality mode, the valid gain value is different, reference RM for detail. + * param base PDM base pointer. + * param channel PDM channel index. + * param gain channel gain, the register gain value range is 0 - 15. + */ +void PDM_SetChannelGain(PDM_Type *base, uint32_t channel, pdm_df_output_gain_t gain) +{ + assert(channel <= (uint32_t)FSL_FEATURE_PDM_CHANNEL_NUM); + +#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL + uint32_t outCtrl = base->RANGE_CTRL; +#else + uint32_t outCtrl = base->OUT_CTRL; +#endif + +#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL + outCtrl &= ~((uint32_t)PDM_RANGE_CTRL_RANGEADJ0_MASK << (channel << 2U)); +#else + outCtrl &= ~((uint32_t)PDM_OUT_CTRL_OUTGAIN0_MASK << (channel << 2U)); +#endif + + outCtrl |= (uint32_t)gain << (channel << 2U); + +#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL + base->RANGE_CTRL = outCtrl; +#else + base->OUT_CTRL = outCtrl; +#endif +} + +/*! + * brief PDM set channel transfer config. + * + * param base PDM base pointer. + * param handle PDM handle pointer. + * param channel PDM channel. + * param config channel config. + * param format data format. + */ +status_t PDM_TransferSetChannelConfig( + PDM_Type *base, pdm_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config, uint32_t format) +{ + assert(handle != NULL); + + PDM_SetChannelConfig(base, channel, config); + + handle->format = format; + + if (handle->channelNums == 0U) + { + handle->startChannel = (uint8_t)channel; + } + + handle->channelNums++; + + if (handle->channelNums > (uint8_t)FSL_FEATURE_PDM_CHANNEL_NUM) + { + return kStatus_PDM_ChannelConfig_Failed; + } + + return kStatus_Success; +} + +/*! + * brief Initializes the PDM handle. + * + * This function initializes the handle for the PDM transactional APIs. Call + * this function once to get the handle initialized. + * + * param base PDM base pointer. + * param handle PDM handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ +void PDM_TransferCreateHandle(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + s_pdmHandle[PDM_GetInstance(base)] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->watermark = (uint8_t)(base->FIFO_CTRL & PDM_FIFO_CTRL_FIFOWMK_MASK); + + /* Set the isr pointer */ + s_pdmIsr = PDM_TransferHandleIRQ; + + /* Enable RX event IRQ */ + (void)EnableIRQ(PDM_EVENT_IRQn); +#if !(defined FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ && FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ) + /* Enable FIFO error IRQ */ + (void)EnableIRQ(PDM_ERROR_IRQn); +#endif +} + +/*! + * brief Performs an interrupt non-blocking receive transfer on PDM. + * + * note This API returns immediately after the transfer initiates. + * Call the PDM_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_PDM_Busy, the transfer + * is finished. + * + * param base PDM base pointer + * param handle Pointer to the pdm_handle_t structure which stores the transfer state. + * param xfer Pointer to the pdm_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_PDM_Busy Previous receive still not finished. + */ +status_t PDM_TransferReceiveNonBlocking(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_t *xfer) +{ + assert(handle != NULL); + + /* Check if the queue is full */ + if (handle->pdmQueue[handle->queueUser].data != NULL) + { + return kStatus_PDM_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->pdmQueue[handle->queueUser].data = xfer->data; + handle->pdmQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1U) % PDM_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kStatus_PDM_Busy; + + /* Enable interrupt */ + PDM_EnableInterrupts(base, (uint32_t)kPDM_FIFOInterruptEnable); + + PDM_Enable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base PDM base pointer + * param handle Pointer to the pdm_handle_t structure which stores the transfer state. + */ +void PDM_TransferAbortReceive(PDM_Type *base, pdm_handle_t *handle) +{ + assert(handle != NULL); + + /* Use FIFO request interrupt and fifo error */ + PDM_DisableInterrupts(base, (uint32_t)kPDM_FIFOInterruptEnable | (uint32_t)kPDM_ErrorInterruptEnable); + PDM_Enable(base, false); + handle->state = kStatus_PDM_Idle; + /* Clear the queue */ + (void)memset(handle->pdmQueue, 0, sizeof(pdm_transfer_t) * PDM_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Tx interrupt handler. + * + * param base PDM base pointer. + * param handle Pointer to the pdm_handle_t structure. + */ +void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle) +{ + assert(handle != NULL); + +#if (defined FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ && FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ) + uint32_t status = 0U; + +#if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U)) + if (PDM_GetStatus(base) & PDM_STAT_LOWFREQF_MASK) + { + PDM_ClearStatus(base, PDM_STAT_LOWFREQF_MASK); + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_PDM_CLK_LOW, handle->userData); + } + } +#endif + status = PDM_GetFifoStatus(base); + if (status != 0U) + { + PDM_ClearFIFOStatus(base, status); + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_PDM_FIFO_ERROR, handle->userData); + } + } + +#if !(defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL) + status = PDM_GetOutputStatus(base); + if (status != 0U) + { + PDM_ClearOutputStatus(base, status); + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_PDM_Output_ERROR, handle->userData); + } + } +#endif +#endif + + /* Handle transfer */ + if (((base->STAT & 0xFFU) != 0U) && (handle->channelNums != 0U) && + ((base->CTRL_1 & PDM_CTRL_1_DISEL_MASK) == (0x2UL << PDM_CTRL_1_DISEL_SHIFT))) + { + PDM_ClearStatus(base, 0xFFU); + /* Judge if the data need to transmit is less than space */ + uint8_t size = (uint8_t)MIN((handle->pdmQueue[handle->queueDriver].dataSize), + ((uint32_t)handle->watermark * handle->channelNums * handle->format)); + + PDM_ReadFifo(base, handle->startChannel, handle->channelNums, + (uint8_t *)(uint32_t)handle->pdmQueue[handle->queueDriver].data, + ((size_t)size / handle->channelNums / handle->format), handle->format); + + /* Update the internal counter */ + handle->pdmQueue[handle->queueDriver].dataSize -= size; + handle->pdmQueue[handle->queueDriver].data = &(handle->pdmQueue[handle->queueDriver].data[size]); + } + + /* If finished a block, call the callback function */ + if (handle->pdmQueue[handle->queueDriver].dataSize == 0U) + { + handle->pdmQueue[handle->queueDriver].data = NULL; + handle->queueDriver = (handle->queueDriver + 1U) % PDM_XFER_QUEUE_SIZE; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_PDM_Idle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->pdmQueue[handle->queueDriver].data == NULL) + { + PDM_TransferAbortReceive(base, handle); + } +} + +#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) +/*! + * brief set HWVAD in envelope based mode . + * Recommand configurations, + * code + * static const pdm_hwvad_config_t hwvadConfig = { + * .channel = 0, + * .initializeTime = 10U, + * .cicOverSampleRate = 0U, + * .inputGain = 0U, + * .frameTime = 10U, + * .cutOffFreq = kPDM_HwvadHpfBypassed, + * .enableFrameEnergy = false, + * .enablePreFilter = true, +}; + + * static const pdm_hwvad_noise_filter_t noiseFilterConfig = { + * .enableAutoNoiseFilter = false, + * .enableNoiseMin = true, + * .enableNoiseDecimation = true, + * .noiseFilterAdjustment = 0U, + * .noiseGain = 7U, + * .enableNoiseDetectOR = true, + * }; + * code + * param base PDM base pointer. + * param hwvadConfig internal filter status. + * param noiseConfig Voice activity detector noise filter configure structure pointer. + * param zcdConfig Voice activity detector zero cross detector configure structure pointer . + * param signalGain signal gain value. + */ +void PDM_SetHwvadInEnvelopeBasedMode(PDM_Type *base, + const pdm_hwvad_config_t *hwvadConfig, + const pdm_hwvad_noise_filter_t *noiseConfig, + const pdm_hwvad_zero_cross_detector_t *zcdConfig, + uint32_t signalGain) +{ + assert(hwvadConfig != NULL); + assert(noiseConfig != NULL); + + uint32_t i = 0U; + + PDM_SetHwvadConfig(base, hwvadConfig); + PDM_SetHwvadSignalFilterConfig(base, true, signalGain); + PDM_SetHwvadNoiseFilterConfig(base, noiseConfig); + PDM_EnableHwvad(base, true); + + if (NULL != zcdConfig) + { + PDM_SetHwvadZeroCrossDetectorConfig(base, zcdConfig); + } + + PDM_Enable(base, true); + + while (PDM_GetHwvadInitialFlag(base) != 0U) + { + } + + for (i = 0; i < 3U; i++) + { + /* set HWVAD interal filter stauts initial */ + PDM_SetHwvadInternalFilterStatus(base, kPDM_HwvadInternalFilterInitial); + } + + PDM_SetHwvadInternalFilterStatus(base, kPDM_HwvadInternalFilterNormalOperation); +} + +/*! + * brief set HWVAD in energy based mode . + * Recommand configurations, + * code + * static const pdm_hwvad_config_t hwvadConfig = { + * .channel = 0, + * .initializeTime = 10U, + * .cicOverSampleRate = 0U, + * .inputGain = 0U, + * .frameTime = 10U, + * .cutOffFreq = kPDM_HwvadHpfBypassed, + * .enableFrameEnergy = true, + * .enablePreFilter = true, +}; + + * static const pdm_hwvad_noise_filter_t noiseFilterConfig = { + * .enableAutoNoiseFilter = true, + * .enableNoiseMin = false, + * .enableNoiseDecimation = false, + * .noiseFilterAdjustment = 0U, + * .noiseGain = 7U, + * .enableNoiseDetectOR = false, + * }; + * code + * param base PDM base pointer. + * param hwvadConfig internal filter status. + * param noiseConfig Voice activity detector noise filter configure structure pointer. + * param zcdConfig Voice activity detector zero cross detector configure structure pointer . + * param signalGain signal gain value, signal gain value should be properly according to application. + */ +void PDM_SetHwvadInEnergyBasedMode(PDM_Type *base, + const pdm_hwvad_config_t *hwvadConfig, + const pdm_hwvad_noise_filter_t *noiseConfig, + const pdm_hwvad_zero_cross_detector_t *zcdConfig, + uint32_t signalGain) +{ + assert(hwvadConfig != NULL); + assert(noiseConfig != NULL); + + PDM_SetHwvadConfig(base, hwvadConfig); + /* signal filter need to disable, but signal gain value should be set */ + base->VAD0_SCONFIG = PDM_VAD0_SCONFIG_VADSGAIN(signalGain); + PDM_SetHwvadNoiseFilterConfig(base, noiseConfig); + PDM_EnableHwvad(base, true); + + if (NULL != zcdConfig) + { + PDM_SetHwvadZeroCrossDetectorConfig(base, zcdConfig); + } + + PDM_Enable(base, true); +} + +/*! + * brief Configure voice activity detector. + * + * param base PDM base pointer + * param config Voice activity detector configure structure pointer . + */ +void PDM_SetHwvadConfig(PDM_Type *base, const pdm_hwvad_config_t *config) +{ + assert(config != NULL); + + uint32_t ctrl1 = base->VAD0_CTRL_1; + + /* Configure VAD0_CTRL_1 register */ + ctrl1 &= ~(PDM_VAD0_CTRL_1_VADCHSEL_MASK | PDM_VAD0_CTRL_1_VADCICOSR_MASK | PDM_VAD0_CTRL_1_VADINITT_MASK); + ctrl1 |= (PDM_VAD0_CTRL_1_VADCHSEL(config->channel) | PDM_VAD0_CTRL_1_VADCICOSR(config->cicOverSampleRate) | + PDM_VAD0_CTRL_1_VADINITT(config->initializeTime)); + base->VAD0_CTRL_1 = ctrl1; + + /* Configure VAD0_CTRL_2 register */ + base->VAD0_CTRL_2 = + (PDM_VAD0_CTRL_2_VADFRENDIS((config->enableFrameEnergy == true) ? 0U : 1U) | + PDM_VAD0_CTRL_2_VADPREFEN(config->enablePreFilter) | PDM_VAD0_CTRL_2_VADFRAMET(config->frameTime) | + PDM_VAD0_CTRL_2_VADINPGAIN(config->inputGain) | PDM_VAD0_CTRL_2_VADHPF(config->cutOffFreq)); +} + +/*! + * brief Configure voice activity detector signal filter. + * + * param base PDM base pointer + * param enableMaxBlock If signal maximum block enabled. + * param signalGain Gain value for the signal energy. + */ +void PDM_SetHwvadSignalFilterConfig(PDM_Type *base, bool enableMaxBlock, uint32_t signalGain) +{ + uint32_t signalConfig = base->VAD0_SCONFIG; + + signalConfig &= ~(PDM_VAD0_SCONFIG_VADSMAXEN_MASK | PDM_VAD0_SCONFIG_VADSGAIN_MASK); + signalConfig |= (PDM_VAD0_SCONFIG_VADSMAXEN(enableMaxBlock) | PDM_VAD0_SCONFIG_VADSGAIN(signalGain)) | + PDM_VAD0_SCONFIG_VADSFILEN_MASK; + base->VAD0_SCONFIG = signalConfig; +} + +/*! + * brief Configure voice activity detector noise filter. + * + * param base PDM base pointer + * param config Voice activity detector noise filter configure structure pointer . + */ +void PDM_SetHwvadNoiseFilterConfig(PDM_Type *base, const pdm_hwvad_noise_filter_t *config) +{ + assert(config != NULL); + + base->VAD0_NCONFIG = + (PDM_VAD0_NCONFIG_VADNFILAUTO(config->enableAutoNoiseFilter) | + PDM_VAD0_NCONFIG_VADNOREN(config->enableNoiseDetectOR) | PDM_VAD0_NCONFIG_VADNMINEN(config->enableNoiseMin) | + PDM_VAD0_NCONFIG_VADNDECEN(config->enableNoiseDecimation) | + PDM_VAD0_NCONFIG_VADNFILADJ(config->noiseFilterAdjustment) | PDM_VAD0_NCONFIG_VADNGAIN(config->noiseGain)); +} + +/*! + * brief Configure voice activity detector zero cross detector. + * + * param base PDM base pointer + * param config Voice activity detector zero cross detector configure structure pointer . + */ +void PDM_SetHwvadZeroCrossDetectorConfig(PDM_Type *base, const pdm_hwvad_zero_cross_detector_t *config) +{ + assert(config != NULL); + + uint32_t zcd = (base->VAD0_ZCD & (~(PDM_VAD0_ZCD_VADZCDTH_MASK | PDM_VAD0_ZCD_VADZCDADJ_MASK | + PDM_VAD0_ZCD_VADZCDAUTO_MASK | PDM_VAD0_ZCD_VADZCDAND_MASK))); + + zcd |= (PDM_VAD0_ZCD_VADZCDTH(config->threshold) | PDM_VAD0_ZCD_VADZCDADJ(config->adjustmentThreshold) | + PDM_VAD0_ZCD_VADZCDAUTO(config->enableAutoThreshold) | PDM_VAD0_ZCD_VADZCDAND(config->zcdAnd)) | + PDM_VAD0_ZCD_VADZCDEN_MASK; + + base->VAD0_ZCD = zcd; +} + +/*! + * brief Enable/Disable hwvad callback. + + * This function enable/disable the hwvad interrupt for the selected PDM peripheral. + * + * param base Base address of the PDM peripheral. + * param vadCallback callback Pointer to store callback function, should be NULL when disable. + * param userData user data. + * param enable true is enable, false is disable. + * retval None. + */ +void PDM_EnableHwvadInterruptCallback(PDM_Type *base, pdm_hwvad_callback_t vadCallback, void *userData, bool enable) +{ + uint32_t instance = PDM_GetInstance(base); + + if (enable) + { + PDM_EnableHwvadInterrupts(base, (uint32_t)kPDM_HwvadErrorInterruptEnable | (uint32_t)kPDM_HwvadInterruptEnable); + NVIC_ClearPendingIRQ(PDM_HWVAD_EVENT_IRQn); + (void)EnableIRQ(PDM_HWVAD_EVENT_IRQn); +#if !(defined FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ && FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ) + NVIC_ClearPendingIRQ(PDM_HWVAD_ERROR_IRQn); + (void)EnableIRQ(PDM_HWVAD_ERROR_IRQn); +#endif + s_pdm_hwvad_notification[instance].callback = vadCallback; + s_pdm_hwvad_notification[instance].userData = userData; + } + else + { + PDM_DisableHwvadInterrupts(base, + (uint32_t)kPDM_HwvadErrorInterruptEnable | (uint32_t)kPDM_HwvadInterruptEnable); + (void)DisableIRQ(PDM_HWVAD_EVENT_IRQn); +#if !(defined FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ && FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ) + (void)DisableIRQ(PDM_HWVAD_ERROR_IRQn); + NVIC_ClearPendingIRQ(PDM_HWVAD_ERROR_IRQn); +#endif + s_pdm_hwvad_notification[instance].callback = NULL; + s_pdm_hwvad_notification[instance].userData = NULL; + NVIC_ClearPendingIRQ(PDM_HWVAD_EVENT_IRQn); + } +} + +#if (defined PDM) +void PDM_HWVAD_EVENT_DriverIRQHandler(void); +void PDM_HWVAD_EVENT_DriverIRQHandler(void) +{ + if ((PDM_GetHwvadInterruptStatusFlags(PDM) & (uint32_t)kPDM_HwvadStatusVoiceDetectFlag) != 0U) + { + PDM_ClearHwvadInterruptStatusFlags(PDM, (uint32_t)kPDM_HwvadStatusVoiceDetectFlag); + if (s_pdm_hwvad_notification[0].callback != NULL) + { + s_pdm_hwvad_notification[0].callback(kStatus_PDM_HWVAD_VoiceDetected, s_pdm_hwvad_notification[0].userData); + } + } +#if (defined FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ && FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ) + else + { + PDM_ClearHwvadInterruptStatusFlags(PDM, (uint32_t)kPDM_HwvadStatusInputSaturation); + if (s_pdm_hwvad_notification[0].callback != NULL) + { + s_pdm_hwvad_notification[0].callback(kStatus_PDM_HWVAD_Error, s_pdm_hwvad_notification[0].userData); + } + } +#endif + SDK_ISR_EXIT_BARRIER; +} + +#if !(defined FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ && FSL_FEATURE_PDM_HAS_NO_INDEPENDENT_ERROR_IRQ) +void PDM_HWVAD_ERROR_DriverIRQHandler(void); +void PDM_HWVAD_ERROR_DriverIRQHandler(void) +{ + PDM_ClearHwvadInterruptStatusFlags(PDM, (uint32_t)kPDM_HwvadStatusInputSaturation); + if (s_pdm_hwvad_notification[0].callback != NULL) + { + s_pdm_hwvad_notification[0].callback(kStatus_PDM_HWVAD_Error, s_pdm_hwvad_notification[0].userData); + } + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(PDM) +void PDM_EVENT_DriverIRQHandler(void); +void PDM_EVENT_DriverIRQHandler(void) +{ + assert(s_pdmHandle[0] != NULL); + s_pdmIsr(PDM, s_pdmHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm.h new file mode 100644 index 0000000000..e8c402df06 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm.h @@ -0,0 +1,1217 @@ +/* + * Copyright (c) 2018, Freescale Semiconductor, Inc. + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_PDM_H_ +#define FSL_PDM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pdm_driver PDM Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PDM_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) /*!< Version 2.9.1 */ +/*@}*/ + +/*! @brief PDM XFER QUEUE SIZE */ +#define PDM_XFER_QUEUE_SIZE (4U) + +/*! @brief PDM return status*/ +enum +{ + kStatus_PDM_Busy = MAKE_STATUS(kStatusGroup_PDM, 0), /*!< PDM is busy. */ +#if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U)) + kStatus_PDM_CLK_LOW = MAKE_STATUS(kStatusGroup_PDM, 1), /*!< PDM clock frequency low */ +#endif + kStatus_PDM_FIFO_ERROR = MAKE_STATUS(kStatusGroup_PDM, 2), /*!< PDM FIFO underrun or overflow */ + kStatus_PDM_QueueFull = MAKE_STATUS(kStatusGroup_PDM, 3), /*!< PDM FIFO underrun or overflow */ + kStatus_PDM_Idle = MAKE_STATUS(kStatusGroup_PDM, 4), /*!< PDM is idle */ + kStatus_PDM_Output_ERROR = MAKE_STATUS(kStatusGroup_PDM, 5), /*!< PDM is output error */ + kStatus_PDM_ChannelConfig_Failed = MAKE_STATUS(kStatusGroup_PDM, 6), /*!< PDM channel config failed */ +#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) + kStatus_PDM_HWVAD_VoiceDetected = MAKE_STATUS(kStatusGroup_PDM, 7), /*!< PDM hwvad voice detected */ + kStatus_PDM_HWVAD_Error = MAKE_STATUS(kStatusGroup_PDM, 8), /*!< PDM hwvad error */ +#endif +}; + +/*! @brief The PDM interrupt enable flag */ +enum _pdm_interrupt_enable +{ + kPDM_ErrorInterruptEnable = PDM_CTRL_1_ERREN_MASK, /*!< PDM channel error interrupt enable. */ + kPDM_FIFOInterruptEnable = PDM_CTRL_1_DISEL(2U), /*!< PDM channel FIFO interrupt */ +}; + +/*! @brief The PDM status */ +enum _pdm_internal_status +{ + kPDM_StatusDfBusyFlag = (int)PDM_STAT_BSY_FIL_MASK, /*!< Decimation filter is busy processing data */ +#if !(defined(FSL_FEATURE_PDM_HAS_NO_FIR_RDY) && FSL_FEATURE_PDM_HAS_NO_FIR_RDY) + kPDM_StatusFIRFilterReady = PDM_STAT_FIR_RDY_MASK, /*!< FIR filter data is ready */ +#endif +#if (defined(FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ) && (FSL_FEATURE_PDM_HAS_STATUS_LOW_FREQ == 1U)) + kPDM_StatusFrequencyLow = PDM_STAT_LOWFREQF_MASK, /*!< Mic app clock frequency not high enough */ +#endif + kPDM_StatusCh0FifoDataAvaliable = PDM_STAT_CH0F_MASK, /*!< channel 0 fifo data reached watermark level */ + kPDM_StatusCh1FifoDataAvaliable = PDM_STAT_CH1F_MASK, /*!< channel 1 fifo data reached watermark level */ + kPDM_StatusCh2FifoDataAvaliable = PDM_STAT_CH2F_MASK, /*!< channel 2 fifo data reached watermark level */ + kPDM_StatusCh3FifoDataAvaliable = PDM_STAT_CH3F_MASK, /*!< channel 3 fifo data reached watermark level */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_StatusCh4FifoDataAvaliable = PDM_STAT_CH4F_MASK, /*!< channel 4 fifo data reached watermark level */ + kPDM_StatusCh5FifoDataAvaliable = PDM_STAT_CH5F_MASK, /*!< channel 5 fifo data reached watermark level */ + kPDM_StatusCh6FifoDataAvaliable = PDM_STAT_CH6F_MASK, /*!< channel 6 fifo data reached watermark level */ + kPDM_StatusCh7FifoDataAvaliable = PDM_STAT_CH7F_MASK, /*!< channel 7 fifo data reached watermark level */ +#endif +}; + +/*! @brief PDM channel enable mask */ +enum _pdm_channel_enable_mask +{ + kPDM_EnableChannel0 = PDM_STAT_CH0F_MASK, /*!< channgel 0 enable mask */ + kPDM_EnableChannel1 = PDM_STAT_CH1F_MASK, /*!< channgel 1 enable mask */ + kPDM_EnableChannel2 = PDM_STAT_CH2F_MASK, /*!< channgel 2 enable mask */ + kPDM_EnableChannel3 = PDM_STAT_CH3F_MASK, /*!< channgel 3 enable mask */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_EnableChannel4 = PDM_STAT_CH4F_MASK, /*!< channgel 4 enable mask */ + kPDM_EnableChannel5 = PDM_STAT_CH5F_MASK, /*!< channgel 5 enable mask */ + kPDM_EnableChannel6 = PDM_STAT_CH6F_MASK, /*!< channgel 6 enable mask */ + kPDM_EnableChannel7 = PDM_STAT_CH7F_MASK, /*!< channgel 7 enable mask */ + + kPDM_EnableChannelAll = kPDM_EnableChannel0 | kPDM_EnableChannel1 | kPDM_EnableChannel2 | kPDM_EnableChannel3 | + kPDM_EnableChannel4 | kPDM_EnableChannel5 | kPDM_EnableChannel6 | kPDM_EnableChannel7, +#else + kPDM_EnableChannelAll = kPDM_EnableChannel0 | kPDM_EnableChannel1 | kPDM_EnableChannel2 | kPDM_EnableChannel3, +#endif +}; + +/*! @brief The PDM fifo status */ +enum _pdm_fifo_status +{ + kPDM_FifoStatusUnderflowCh0 = PDM_FIFO_STAT_FIFOUND0_MASK, /*!< channel0 fifo status underflow */ + kPDM_FifoStatusUnderflowCh1 = PDM_FIFO_STAT_FIFOUND1_MASK, /*!< channel1 fifo status underflow */ + kPDM_FifoStatusUnderflowCh2 = PDM_FIFO_STAT_FIFOUND2_MASK, /*!< channel2 fifo status underflow */ + kPDM_FifoStatusUnderflowCh3 = PDM_FIFO_STAT_FIFOUND3_MASK, /*!< channel3 fifo status underflow */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_FifoStatusUnderflowCh4 = PDM_FIFO_STAT_FIFOUND4_MASK, /*!< channel4 fifo status underflow */ + kPDM_FifoStatusUnderflowCh5 = PDM_FIFO_STAT_FIFOUND5_MASK, /*!< channel5 fifo status underflow */ + kPDM_FifoStatusUnderflowCh6 = PDM_FIFO_STAT_FIFOUND6_MASK, /*!< channel6 fifo status underflow */ + kPDM_FifoStatusUnderflowCh7 = PDM_FIFO_STAT_FIFOUND6_MASK, /*!< channel7 fifo status underflow */ +#endif + + kPDM_FifoStatusOverflowCh0 = PDM_FIFO_STAT_FIFOOVF0_MASK, /*!< channel0 fifo status overflow */ + kPDM_FifoStatusOverflowCh1 = PDM_FIFO_STAT_FIFOOVF1_MASK, /*!< channel1 fifo status overflow */ + kPDM_FifoStatusOverflowCh2 = PDM_FIFO_STAT_FIFOOVF2_MASK, /*!< channel2 fifo status overflow */ + kPDM_FifoStatusOverflowCh3 = PDM_FIFO_STAT_FIFOOVF3_MASK, /*!< channel3 fifo status overflow */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_FifoStatusOverflowCh4 = PDM_FIFO_STAT_FIFOOVF4_MASK, /*!< channel4 fifo status overflow */ + kPDM_FifoStatusOverflowCh5 = PDM_FIFO_STAT_FIFOOVF5_MASK, /*!< channel5 fifo status overflow */ + kPDM_FifoStatusOverflowCh6 = PDM_FIFO_STAT_FIFOOVF6_MASK, /*!< channel6 fifo status overflow */ + kPDM_FifoStatusOverflowCh7 = PDM_FIFO_STAT_FIFOOVF7_MASK, /*!< channel7 fifo status overflow */ +#endif +}; + +#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL +/*! @brief The PDM output status */ +enum _pdm_range_status +{ + kPDM_RangeStatusUnderFlowCh0 = PDM_RANGE_STAT_RANGEUNF0_MASK, /*!< channel0 range status underflow */ + kPDM_RangeStatusUnderFlowCh1 = PDM_RANGE_STAT_RANGEUNF1_MASK, /*!< channel1 range status underflow */ + kPDM_RangeStatusUnderFlowCh2 = PDM_RANGE_STAT_RANGEUNF2_MASK, /*!< channel2 range status underflow */ + kPDM_RangeStatusUnderFlowCh3 = PDM_RANGE_STAT_RANGEUNF3_MASK, /*!< channel3 range status underflow */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_RangeStatusUnderFlowCh4 = PDM_RANGE_STAT_RANGEUNF4_MASK, /*!< channel4 range status underflow */ + kPDM_RangeStatusUnderFlowCh5 = PDM_RANGE_STAT_RANGEUNF5_MASK, /*!< channel5 range status underflow */ + kPDM_RangeStatusUnderFlowCh6 = PDM_RANGE_STAT_RANGEUNF6_MASK, /*!< channel6 range status underflow */ + kPDM_RangeStatusUnderFlowCh7 = PDM_RANGE_STAT_RANGEUNF7_MASK, /*!< channel7 range status underflow */ +#endif + kPDM_RangeStatusOverFlowCh0 = PDM_RANGE_STAT_RANGEOVF0_MASK, /*!< channel0 range status overflow */ + kPDM_RangeStatusOverFlowCh1 = PDM_RANGE_STAT_RANGEOVF1_MASK, /*!< channel1 range status overflow */ + kPDM_RangeStatusOverFlowCh2 = PDM_RANGE_STAT_RANGEOVF2_MASK, /*!< channel2 range status overflow */ + kPDM_RangeStatusOverFlowCh3 = PDM_RANGE_STAT_RANGEOVF3_MASK, /*!< channel3 range status overflow */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_RangeStatusOverFlowCh4 = PDM_RANGE_STAT_RANGEOVF4_MASK, /*!< channel4 range status overflow */ + kPDM_RangeStatusOverFlowCh5 = PDM_RANGE_STAT_RANGEOVF5_MASK, /*!< channel5 range status overflow */ + kPDM_RangeStatusOverFlowCh6 = PDM_RANGE_STAT_RANGEOVF6_MASK, /*!< channel6 range status overflow */ + kPDM_RangeStatusOverFlowCh7 = PDM_RANGE_STAT_RANGEOVF7_MASK, /*!< channel7 range status overflow */ +#endif +}; +#else +/*! @brief The PDM output status */ +enum _pdm_output_status +{ + kPDM_OutputStatusUnderFlowCh0 = PDM_OUT_STAT_OUTUNF0_MASK, /*!< channel0 output status underflow */ + kPDM_OutputStatusUnderFlowCh1 = PDM_OUT_STAT_OUTUNF1_MASK, /*!< channel1 output status underflow */ + kPDM_OutputStatusUnderFlowCh2 = PDM_OUT_STAT_OUTUNF2_MASK, /*!< channel2 output status underflow */ + kPDM_OutputStatusUnderFlowCh3 = PDM_OUT_STAT_OUTUNF3_MASK, /*!< channel3 output status underflow */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_OutputStatusUnderFlowCh4 = PDM_OUT_STAT_OUTUNF4_MASK, /*!< channel4 output status underflow */ + kPDM_OutputStatusUnderFlowCh5 = PDM_OUT_STAT_OUTUNF5_MASK, /*!< channel5 output status underflow */ + kPDM_OutputStatusUnderFlowCh6 = PDM_OUT_STAT_OUTUNF6_MASK, /*!< channel6 output status underflow */ + kPDM_OutputStatusUnderFlowCh7 = PDM_OUT_STAT_OUTUNF7_MASK, /*!< channel7 output status underflow */ +#endif + kPDM_OutputStatusOverFlowCh0 = PDM_OUT_STAT_OUTOVF0_MASK, /*!< channel0 output status overflow */ + kPDM_OutputStatusOverFlowCh1 = PDM_OUT_STAT_OUTOVF1_MASK, /*!< channel1 output status overflow */ + kPDM_OutputStatusOverFlowCh2 = PDM_OUT_STAT_OUTOVF2_MASK, /*!< channel2 output status overflow */ + kPDM_OutputStatusOverFlowCh3 = PDM_OUT_STAT_OUTOVF3_MASK, /*!< channel3 output status overflow */ +#if !defined(FSL_FEATURE_PDM_CHANNEL_NUM) || (FSL_FEATURE_PDM_CHANNEL_NUM == 8U) + kPDM_OutputStatusOverFlowCh4 = PDM_OUT_STAT_OUTOVF4_MASK, /*!< channel4 output status overflow */ + kPDM_OutputStatusOverFlowCh5 = PDM_OUT_STAT_OUTOVF5_MASK, /*!< channel5 output status overflow */ + kPDM_OutputStatusOverFlowCh6 = PDM_OUT_STAT_OUTOVF6_MASK, /*!< channel6 output status overflow */ + kPDM_OutputStatusOverFlowCh7 = PDM_OUT_STAT_OUTOVF7_MASK, /*!< channel7 output status overflow */ +#endif +}; +#endif + +#if (defined(FSL_FEATURE_PDM_HAS_DC_OUT_CTRL) && (FSL_FEATURE_PDM_HAS_DC_OUT_CTRL)) +/*! @brief PDM DC remover configurations */ +typedef enum _pdm_dc_remover +{ + kPDM_DcRemoverCutOff20Hz = 0U, /*!< DC remover cut off 20HZ */ + kPDM_DcRemoverCutOff13Hz = 1U, /*!< DC remover cut off 13.3HZ */ + kPDM_DcRemoverCutOff40Hz = 2U, /*!< DC remover cut off 40HZ */ + kPDM_DcRemoverBypass = 3U, /*!< DC remover bypass */ +} pdm_dc_remover_t; +#else +/*! @brief PDM DC remover configurations */ +typedef enum _pdm_dc_remover +{ + kPDM_DcRemoverCutOff21Hz = 0U, /*!< DC remover cut off 21HZ */ + kPDM_DcRemoverCutOff83Hz = 1U, /*!< DC remover cut off 83HZ */ + kPDM_DcRemoverCutOff152Hz = 2U, /*!< DC remover cut off 152HZ */ + kPDM_DcRemoverBypass = 3U, /*!< DC remover bypass */ +} pdm_dc_remover_t; +#endif + +/*! @brief PDM decimation filter quality mode */ +typedef enum _pdm_df_quality_mode +{ + kPDM_QualityModeMedium = 0U, /*!< quality mode memdium */ + kPDM_QualityModeHigh = 1U, /*!< quality mode high */ + kPDM_QualityModeLow = 7U, /*!< quality mode low */ + kPDM_QualityModeVeryLow0 = 6U, /*!< quality mode very low0 */ + kPDM_QualityModeVeryLow1 = 5U, /*!< quality mode very low1 */ + kPDM_QualityModeVeryLow2 = 4U, /*!< quality mode very low2 */ +} pdm_df_quality_mode_t; + +/*! @brief PDM quality mode K factor */ +enum _pdm_qulaity_mode_k_factor +{ + kPDM_QualityModeHighKFactor = 1U, /*!< high quality mode K factor = 1 / 2 */ + kPDM_QualityModeMediumKFactor = 2U, /*!< medium/very low0 quality mode K factor = 2 / 2 */ + kPDM_QualityModeLowKFactor = 4U, /*!< low/very low1 quality mode K factor = 4 / 2 */ + kPDM_QualityModeVeryLow2KFactor = 8U, /*!< very low2 quality mode K factor = 8 / 2 */ +}; + +/*! @brief PDM decimation filter output gain */ +typedef enum _pdm_df_output_gain +{ + kPDM_DfOutputGain0 = 0U, /*!< Decimation filter output gain 0 */ + kPDM_DfOutputGain1 = 1U, /*!< Decimation filter output gain 1 */ + kPDM_DfOutputGain2 = 2U, /*!< Decimation filter output gain 2 */ + kPDM_DfOutputGain3 = 3U, /*!< Decimation filter output gain 3 */ + kPDM_DfOutputGain4 = 4U, /*!< Decimation filter output gain 4 */ + kPDM_DfOutputGain5 = 5U, /*!< Decimation filter output gain 5 */ + kPDM_DfOutputGain6 = 6U, /*!< Decimation filter output gain 6 */ + kPDM_DfOutputGain7 = 7U, /*!< Decimation filter output gain 7 */ + kPDM_DfOutputGain8 = 8U, /*!< Decimation filter output gain 8 */ + kPDM_DfOutputGain9 = 9U, /*!< Decimation filter output gain 9 */ + kPDM_DfOutputGain10 = 0xAU, /*!< Decimation filter output gain 10 */ + kPDM_DfOutputGain11 = 0xBU, /*!< Decimation filter output gain 11 */ + kPDM_DfOutputGain12 = 0xCU, /*!< Decimation filter output gain 12 */ + kPDM_DfOutputGain13 = 0xDU, /*!< Decimation filter output gain 13 */ + kPDM_DfOutputGain14 = 0xEU, /*!< Decimation filter output gain 14 */ + kPDM_DfOutputGain15 = 0xFU, /*!< Decimation filter output gain 15 */ +} pdm_df_output_gain_t; + +/*! @brief PDM data width */ +enum _pdm_data_width +{ +#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH != 2U) + kPDM_DataWwidth24 = 3U, /*!< PDM data width 24bit */ + kPDM_DataWwidth32 = 4U, /*!< PDM data width 32bit */ +#else + kPDM_DataWdith16 = 2U, /*!< PDM data width 16bit */ +#endif +}; + +/*! @brief PDM channel configurations */ +typedef struct _pdm_channel_config +{ +#if (defined(FSL_FEATURE_PDM_HAS_DC_OUT_CTRL) && (FSL_FEATURE_PDM_HAS_DC_OUT_CTRL)) + pdm_dc_remover_t outputCutOffFreq; /*!< PDM output DC remover cut off frequency */ +#endif + +#if !(defined(FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED) && (FSL_FEATURE_PDM_DC_CTRL_VALUE_FIXED)) + pdm_dc_remover_t cutOffFreq; /*!< DC remover cut off frequency */ +#endif + + pdm_df_output_gain_t gain; /*!< Decimation Filter Output Gain */ +} pdm_channel_config_t; + +/*! @brief PDM user configuration structure */ +typedef struct _pdm_config +{ + bool + enableDoze; /*!< This module will enter disable/low leakage mode if DOZEN is active with ipg_doze is asserted */ +#if defined(FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS) && FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS + bool enableFilterBypass; /*!< Switchable bypass path for the decimation filter */ +#endif + uint8_t fifoWatermark; /*!< Watermark value for FIFO */ + pdm_df_quality_mode_t qualityMode; /*!< Quality mode */ + uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ +} pdm_config_t; + +#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) +/*! @brief PDM voice activity detector interrupt type */ +enum _pdm_hwvad_interrupt_enable +{ + kPDM_HwvadErrorInterruptEnable = PDM_VAD0_CTRL_1_VADERIE_MASK, /*!< PDM channel HWVAD error interrupt enable. */ + kPDM_HwvadInterruptEnable = PDM_VAD0_CTRL_1_VADIE_MASK, /*!< PDM channel HWVAD interrupt */ +}; + +/*! @brief The PDM hwvad interrupt status flag */ +enum _pdm_hwvad_int_status +{ + kPDM_HwvadStatusInputSaturation = PDM_VAD0_STAT_VADINSATF_MASK, /*!< HWVAD saturation condition */ + kPDM_HwvadStatusVoiceDetectFlag = PDM_VAD0_STAT_VADIF_MASK, /*!< HWVAD voice detect interrupt triggered */ +}; + +/*! @brief High pass filter configure cut-off frequency*/ +typedef enum _pdm_hwvad_hpf_config +{ + kPDM_HwvadHpfBypassed = 0x0U, /*!< High-pass filter bypass */ + kPDM_HwvadHpfCutOffFreq1750Hz = 0x1U, /*!< High-pass filter cut off frequency 1750HZ */ + kPDM_HwvadHpfCutOffFreq215Hz = 0x2U, /*!< High-pass filter cut off frequency 215HZ */ + kPDM_HwvadHpfCutOffFreq102Hz = 0x3U, /*!< High-pass filter cut off frequency 102HZ */ +} pdm_hwvad_hpf_config_t; + +/*! @brief HWVAD internal filter status */ +typedef enum _pdm_hwvad_filter_status +{ + kPDM_HwvadInternalFilterNormalOperation = 0U, /*!< internal filter ready for normal operation */ + kPDM_HwvadInternalFilterInitial = PDM_VAD0_CTRL_1_VADST10_MASK, /*!< interla filter are initial */ +} pdm_hwvad_filter_status_t; + +/*! @brief PDM voice activity detector user configuration structure */ +typedef struct _pdm_hwvad_config +{ + uint8_t channel; /*!< Which channel uses voice activity detector */ + uint8_t initializeTime; /*!< Number of frames or samples to initialize voice activity detector. */ + uint8_t cicOverSampleRate; /*!< CIC filter over sampling rate */ + + uint8_t inputGain; /*!< Voice activity detector input gain */ + uint32_t frameTime; /*!< Voice activity frame time */ + pdm_hwvad_hpf_config_t cutOffFreq; /*!< High pass filter cut off frequency */ + bool enableFrameEnergy; /*!< If frame energy enabled, true means enable */ + bool enablePreFilter; /*!< If pre-filter enabled */ +} pdm_hwvad_config_t; + +/*! @brief PDM voice activity detector noise filter user configuration structure */ +typedef struct _pdm_hwvad_noise_filter +{ + bool enableAutoNoiseFilter; /*!< If noise fileter automatically activated, true means enable */ + bool enableNoiseMin; /*!< If Noise minimum block enabled, true means enabled */ + bool enableNoiseDecimation; /*!< If enable noise input decimation */ + bool enableNoiseDetectOR; /*!< Enables a OR logic in the output of minimum noise estimator block */ + uint32_t noiseFilterAdjustment; /*!< The adjustment value of the noise filter */ + uint32_t noiseGain; /*!< Gain value for the noise energy or envelope estimated */ +} pdm_hwvad_noise_filter_t; + +/*! @brief PDM voice activity detector zero cross detector result */ +typedef enum _pdm_hwvad_zcd_result +{ + kPDM_HwvadResultOREnergyBasedDetection = + 0U, /*!< zero cross detector result will be OR with energy based detection */ + kPDM_HwvadResultANDEnergyBasedDetection = + 1U, /*!< zero cross detector result will be AND with energy based detection */ +} pdm_hwvad_zcd_result_t; + +/*! @brief PDM voice activity detector zero cross detector configuration structure */ +typedef struct _pdm_hwvad_zero_cross_detector +{ + bool enableAutoThreshold; /*!< If ZCD auto-threshold enabled, true means enabled. */ + pdm_hwvad_zcd_result_t zcdAnd; /*!< Is ZCD result is AND'ed with energy-based detection, false means OR'ed */ + uint32_t threshold; /*!< The adjustment value of the noise filter */ + uint32_t adjustmentThreshold; /*!< Gain value for the noise energy or envelope estimated */ +} pdm_hwvad_zero_cross_detector_t; +#endif + +/*! @brief PDM SDMA transfer structure */ +typedef struct _pdm_transfer +{ + volatile uint8_t *data; /*!< Data start address to transfer. */ + volatile size_t dataSize; /*!< Total Transfer bytes size. */ +} pdm_transfer_t; + +/*! @brief PDM handle */ +typedef struct _pdm_handle pdm_handle_t; + +/*! @brief PDM transfer callback prototype */ +typedef void (*pdm_transfer_callback_t)(PDM_Type *base, pdm_handle_t *handle, status_t status, void *userData); + +#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) +/*! @brief PDM HWVAD callback prototype */ +typedef void (*pdm_hwvad_callback_t)(status_t status, void *userData); +/*! @brief PDM HWVAD notification structure */ +typedef struct _pdm_hwvad_notification +{ + pdm_hwvad_callback_t callback; + void *userData; +} pdm_hwvad_notification_t; +#endif + +/*! @brief PDM handle structure */ +struct _pdm_handle +{ + uint32_t state; /*!< Transfer status */ + pdm_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + + pdm_transfer_t pdmQueue[PDM_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[PDM_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ + + uint32_t format; /*!< data format */ + uint8_t watermark; /*!< Watermark value */ + uint8_t startChannel; /*!< end channel */ + uint8_t channelNums; /*!< Enabled channel number */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the PDM peripheral. + * + * Ungates the PDM clock, resets the module, and configures PDM with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * PDM_GetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the PDM driver. Otherwise, accessing the PDM module can cause a hard fault + * because the clock is not enabled. + * + * @param base PDM base pointer + * @param config PDM configuration structure. + */ +void PDM_Init(PDM_Type *base, const pdm_config_t *config); + +/*! + * @brief De-initializes the PDM peripheral. + * + * This API gates the PDM clock. The PDM module can't operate unless PDM_Init + * is called to enable the clock. + * + * @param base PDM base pointer + */ +void PDM_Deinit(PDM_Type *base); + +/*! + * @brief Resets the PDM module. + * + * @param base PDM base pointer + */ +static inline void PDM_Reset(PDM_Type *base) +{ + base->CTRL_1 |= PDM_CTRL_1_SRES_MASK; +} + +/*! + * @brief Enables/disables PDM interface. + * + * @param base PDM base pointer + * @param enable True means PDM interface is enabled, false means PDM interface is disabled. + */ +static inline void PDM_Enable(PDM_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_1 |= PDM_CTRL_1_PDMIEN_MASK; + } + else + { + base->CTRL_1 &= ~PDM_CTRL_1_PDMIEN_MASK; + } +} + +#if !(defined(FSL_FEATURE_PDM_HAS_NO_DOZEN) && FSL_FEATURE_PDM_HAS_NO_DOZEN) +/*! + * @brief Enables/disables DOZE. + * + * @param base PDM base pointer + * @param enable True means the module will enter Disable/Low Leakage mode when ipg_doze is asserted, false means the + * module will not enter Disable/Low Leakage mode when ipg_doze is asserted. + */ +static inline void PDM_EnableDoze(PDM_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_1 |= PDM_CTRL_1_DOZEN_MASK; + } + else + { + base->CTRL_1 &= ~PDM_CTRL_1_DOZEN_MASK; + } +} +#endif +/*! + * @brief Enables/disables debug mode for PDM. + * The PDM interface cannot enter debug mode once in Disable/Low Leakage or Low Power mode. + * @param base PDM base pointer + * @param enable True means PDM interface enter debug mode, false means PDM interface in normal mode. + */ +static inline void PDM_EnableDebugMode(PDM_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_1 |= PDM_CTRL_1_DBG_MASK; + } + else + { + base->CTRL_1 &= ~PDM_CTRL_1_DBG_MASK; + } +} + +/*! + * @brief Enables/disables PDM interface in debug mode. + * + * @param base PDM base pointer + * @param enable True means PDM interface is enabled debug mode, false means PDM interface is disabled after + * after completing the current frame in debug mode. + */ +static inline void PDM_EnableInDebugMode(PDM_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_1 |= PDM_CTRL_1_DBGE_MASK; + } + else + { + base->CTRL_1 &= ~PDM_CTRL_1_DBGE_MASK; + } +} + +/*! + * @brief Enables/disables PDM interface disable/Low Leakage mode. + * + * @param base PDM base pointer + * @param enable True means PDM interface is in disable/low leakage mode, False means PDM interface is in normal mode. + */ +static inline void PDM_EnterLowLeakageMode(PDM_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_1 |= PDM_CTRL_1_MDIS_MASK; + } + else + { + base->CTRL_1 &= ~PDM_CTRL_1_MDIS_MASK; + } +} + +/*! + * @brief Enables/disables the PDM channel. + * + * @param base PDM base pointer + * @param channel PDM channel number need to enable or disable. + * @param enable True means enable PDM channel, false means disable. + */ +static inline void PDM_EnableChannel(PDM_Type *base, uint8_t channel, bool enable) +{ + if (enable) + { + base->CTRL_1 |= (1UL << channel); + } + else + { + base->CTRL_1 &= ~(1UL << channel); + } +} + +/*! + * @brief PDM one channel configurations. + * + * @param base PDM base pointer + * @param config PDM channel configurations. + * @param channel channel number. + * after completing the current frame in debug mode. + */ +void PDM_SetChannelConfig(PDM_Type *base, uint32_t channel, const pdm_channel_config_t *config); + +/*! + * @brief PDM set sample rate. + * + * @note This function is depend on the configuration of the PDM and PDM channel, so the correct call sequence is + * @code + * PDM_Init(base, pdmConfig) + * PDM_SetChannelConfig(base, channel, &channelConfig) + * PDM_SetSampleRateConfig(base, source, sampleRate) + * @endcode + * @param base PDM base pointer + * @param sourceClock_HZ PDM source clock frequency. + * @param sampleRate_HZ PDM sample rate. + */ +status_t PDM_SetSampleRateConfig(PDM_Type *base, uint32_t sourceClock_HZ, uint32_t sampleRate_HZ); + +/*! + * @brief PDM set sample rate. + * + * @deprecated Do not use this function. It has been superceded by @ref PDM_SetSampleRateConfig + * @param base PDM base pointer + * @param enableChannelMask PDM channel enable mask. + * @param qualityMode quality mode. + * @param osr cic oversample rate + * @param clkDiv clock divider + */ +status_t PDM_SetSampleRate( + PDM_Type *base, uint32_t enableChannelMask, pdm_df_quality_mode_t qualityMode, uint8_t osr, uint32_t clkDiv); + +/*! + * @brief Get the instance number for PDM. + * + * @param base PDM base pointer. + */ +uint32_t PDM_GetInstance(PDM_Type *base); +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the PDM internal status flag. + * Use the Status Mask in _pdm_internal_status to get the status value needed + * @param base PDM base pointer + * @return PDM status flag value. + */ +static inline uint32_t PDM_GetStatus(PDM_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Gets the PDM FIFO status flag. + * Use the Status Mask in _pdm_fifo_status to get the status value needed + * @param base PDM base pointer + * @return FIFO status. + */ +static inline uint32_t PDM_GetFifoStatus(PDM_Type *base) +{ + return base->FIFO_STAT; +} + +#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL +/*! + * @brief Gets the PDM Range status flag. + * Use the Status Mask in _pdm_range_status to get the status value needed + * @param base PDM base pointer + * @return output status. + */ +static inline uint32_t PDM_GetRangeStatus(PDM_Type *base) +{ + return base->RANGE_STAT; +} +#else +/*! + * @brief Gets the PDM output status flag. + * Use the Status Mask in _pdm_output_status to get the status value needed + * @param base PDM base pointer + * @return output status. + */ +static inline uint32_t PDM_GetOutputStatus(PDM_Type *base) +{ + return base->OUT_STAT; +} +#endif + +/*! + * @brief Clears the PDM Tx status. + * + * @param base PDM base pointer + * @param mask State mask. It can be a combination of the status between kPDM_StatusFrequencyLow and + * kPDM_StatusCh7FifoDataAvaliable. + */ +static inline void PDM_ClearStatus(PDM_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +/*! + * @brief Clears the PDM Tx status. + * + * @param base PDM base pointer + * @param mask State mask.It can be a combination of the status in _pdm_fifo_status. + */ +static inline void PDM_ClearFIFOStatus(PDM_Type *base, uint32_t mask) +{ + base->FIFO_STAT = mask; +} + +#if defined(FSL_FEATURE_PDM_HAS_RANGE_CTRL) && FSL_FEATURE_PDM_HAS_RANGE_CTRL +/*! + * @brief Clears the PDM range status. + * + * @param base PDM base pointer + * @param mask State mask. It can be a combination of the status in _pdm_range_status. + */ +static inline void PDM_ClearRangeStatus(PDM_Type *base, uint32_t mask) +{ + base->RANGE_STAT = mask; +} +#else +/*! + * @brief Clears the PDM output status. + * + * @param base PDM base pointer + * @param mask State mask. It can be a combination of the status in _pdm_output_status. + */ +static inline void PDM_ClearOutputStatus(PDM_Type *base, uint32_t mask) +{ + base->OUT_STAT = mask; +} +#endif + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the PDM interrupt requests. + * + * @param base PDM base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kPDM_ErrorInterruptEnable + * @arg kPDM_FIFOInterruptEnable + */ +void PDM_EnableInterrupts(PDM_Type *base, uint32_t mask); + +/*! + * @brief Disables the PDM interrupt requests. + * + * @param base PDM base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kPDM_ErrorInterruptEnable + * @arg kPDM_FIFOInterruptEnable + */ +static inline void PDM_DisableInterrupts(PDM_Type *base, uint32_t mask) +{ + base->CTRL_1 &= ~mask; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the PDM DMA requests. + * + * @param base PDM base pointer + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void PDM_EnableDMA(PDM_Type *base, bool enable) +{ + if (enable) + { + base->CTRL_1 = (base->CTRL_1 & (~PDM_CTRL_1_DISEL_MASK)) | PDM_CTRL_1_DISEL(0x1U); + } + else + { + base->CTRL_1 &= ~PDM_CTRL_1_DISEL_MASK; + } +} + +/*! + * @brief Gets the PDM data register address. + * + * This API is used to provide a transfer address for the PDM DMA transfer configuration. + * + * @param base PDM base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t PDM_GetDataRegisterAddress(PDM_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->DATACH)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ +#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH == 2U) +/*! + * @brief Reads data from the PDM FIFO. + * + * @param base PDM base pointer. + * @param channel Data channel used. + * @return Data in PDM FIFO. + */ +static inline int16_t PDM_ReadData(PDM_Type *base, uint32_t channel) +{ + return (int16_t)(base->DATACH[channel]); +} + +/*! + * @brief PDM read data non blocking. + * So the actually read data byte size in this function is (size * 2 * channelNums). + * @param base PDM base pointer. + * @param startChannel start channel number. + * @param channelNums total enabled channelnums. + * @param buffer received buffer address. + * @param size number of 16bit data to read. + */ +void PDM_ReadNonBlocking(PDM_Type *base, uint32_t startChannel, uint32_t channelNums, int16_t *buffer, size_t size); +#endif + +/*! + * @brief PDM read fifo. + * @note: This function support 16 bit only for IP version that only supports 16bit. + * + * @param base PDM base pointer. + * @param startChannel start channel number. + * @param channelNums total enabled channelnums. + * @param buffer received buffer address. + * @param size number of samples to read. + * @param dataWidth sample width. + */ +void PDM_ReadFifo( + PDM_Type *base, uint32_t startChannel, uint32_t channelNums, void *buffer, size_t size, uint32_t dataWidth); + +#if defined(FSL_FEATURE_PDM_FIFO_WIDTH) && (FSL_FEATURE_PDM_FIFO_WIDTH == 4U) +/*! + * @brief Reads data from the PDM FIFO. + * + * @param base PDM base pointer. + * @param channel Data channel used. + * @return Data in PDM FIFO. + */ +static inline uint32_t PDM_ReadData(PDM_Type *base, uint32_t channel) +{ + return base->DATACH[channel]; +} +#endif + +/*! + * @brief Set the PDM channel gain. + * + * Please note for different quality mode, the valid gain value is different, reference RM for detail. + * @param base PDM base pointer. + * @param channel PDM channel index. + * @param gain channel gain, the register gain value range is 0 - 15. + */ +void PDM_SetChannelGain(PDM_Type *base, uint32_t channel, pdm_df_output_gain_t gain); + +#if !(defined(FSL_FEATURE_PDM_HAS_NO_HWVAD) && FSL_FEATURE_PDM_HAS_NO_HWVAD) +/*! @} */ + +/*! + * @name Voice Activity Detector + * @{ + */ + +/*! + * @brief Configure voice activity detector. + * + * @param base PDM base pointer + * @param config Voice activity detector configure structure pointer . + */ +void PDM_SetHwvadConfig(PDM_Type *base, const pdm_hwvad_config_t *config); + +/*! + * @brief PDM hwvad force output disable. + * + * @param base PDM base pointer + * @param enable true is output force disable, false is output not force. + */ +static inline void PDM_ForceHwvadOutputDisable(PDM_Type *base, bool enable) +{ + if (enable) + { + base->VAD0_CTRL_2 &= ~PDM_VAD0_CTRL_2_VADFOUTDIS_MASK; + } + else + { + base->VAD0_CTRL_2 |= PDM_VAD0_CTRL_2_VADFOUTDIS_MASK; + } +} + +/*! + * @brief PDM hwvad reset. + * It will reset VADNDATA register and will clean all internal buffers, should be called when the PDM isn't running. + * + * @param base PDM base pointer + */ +static inline void PDM_ResetHwvad(PDM_Type *base) +{ + base->VAD0_CTRL_1 |= PDM_VAD0_CTRL_1_VADRST_MASK; +} +/*! + * @brief Enable/Disable Voice activity detector. + * Should be called when the PDM isn't running. + * @param base PDM base pointer. + * @param enable True means enable voice activity detector, false means disable. + */ +static inline void PDM_EnableHwvad(PDM_Type *base, bool enable) +{ + if (enable) + { + base->VAD0_CTRL_1 |= PDM_VAD0_CTRL_1_VADEN_MASK; + } + else + { + base->VAD0_CTRL_1 &= ~PDM_VAD0_CTRL_1_VADEN_MASK; + } +} + +/*! + * @brief Enables the PDM Voice Detector interrupt requests. + * + * @param base PDM base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kPDM_HWVADErrorInterruptEnable + * @arg kPDM_HWVADInterruptEnable + */ +static inline void PDM_EnableHwvadInterrupts(PDM_Type *base, uint32_t mask) +{ + base->VAD0_CTRL_1 |= mask; +} + +/*! + * @brief Disables the PDM Voice Detector interrupt requests. + * + * @param base PDM base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kPDM_HWVADErrorInterruptEnable + * @arg kPDM_HWVADInterruptEnable + */ +static inline void PDM_DisableHwvadInterrupts(PDM_Type *base, uint32_t mask) +{ + base->VAD0_CTRL_1 &= ~mask; +} + +/*! + * @brief Clears the PDM voice activity detector status flags. + * + * @param base PDM base pointer + * @param mask State mask,reference _pdm_hwvad_int_status. + */ +static inline void PDM_ClearHwvadInterruptStatusFlags(PDM_Type *base, uint32_t mask) +{ + base->VAD0_STAT = mask; +} + +/*! + * @brief Clears the PDM voice activity detector status flags. + * + * @param base PDM base pointer + * @return status, reference _pdm_hwvad_int_status + */ +static inline uint32_t PDM_GetHwvadInterruptStatusFlags(PDM_Type *base) +{ + return base->VAD0_STAT & (PDM_VAD0_STAT_VADIF_MASK | PDM_VAD0_STAT_VADINSATF_MASK); +} + +/*! + * @brief Get the PDM voice activity detector initial flags. + * + * @param base PDM base pointer + * @return initial flag. + */ +static inline uint32_t PDM_GetHwvadInitialFlag(PDM_Type *base) +{ + return base->VAD0_STAT & PDM_VAD0_STAT_VADINITF_MASK; +} + +#if !(defined(FSL_FEATURE_PDM_HAS_NO_VADEF) && (FSL_FEATURE_PDM_HAS_NO_VADEF)) +/*! + * @brief Get the PDM voice activity detector voice detected flags. + * NOte: this flag is auto cleared when voice gone. + * @param base PDM base pointer + * @return voice detected flag. + */ +static inline uint32_t PDM_GetHwvadVoiceDetectedFlag(PDM_Type *base) +{ + return base->VAD0_STAT & PDM_VAD0_STAT_VADEF_MASK; +} +#endif + +/*! + * @brief Enables/disables voice activity detector signal filter. + * + * @param base PDM base pointer + * @param enable True means enable signal filter, false means disable. + */ +static inline void PDM_EnableHwvadSignalFilter(PDM_Type *base, bool enable) +{ + if (enable) + { + base->VAD0_SCONFIG |= PDM_VAD0_SCONFIG_VADSFILEN_MASK; + } + else + { + base->VAD0_SCONFIG &= ~PDM_VAD0_SCONFIG_VADSFILEN_MASK; + } +} + +/*! + * @brief Configure voice activity detector signal filter. + * + * @param base PDM base pointer + * @param enableMaxBlock If signal maximum block enabled. + * @param signalGain Gain value for the signal energy. + */ +void PDM_SetHwvadSignalFilterConfig(PDM_Type *base, bool enableMaxBlock, uint32_t signalGain); + +/*! + * @brief Configure voice activity detector noise filter. + * + * @param base PDM base pointer + * @param config Voice activity detector noise filter configure structure pointer . + */ +void PDM_SetHwvadNoiseFilterConfig(PDM_Type *base, const pdm_hwvad_noise_filter_t *config); + +/*! + * @brief Enables/disables voice activity detector zero cross detector. + * + * @param base PDM base pointer + * @param enable True means enable zero cross detector, false means disable. + */ +static inline void PDM_EnableHwvadZeroCrossDetector(PDM_Type *base, bool enable) +{ + if (enable) + { + base->VAD0_ZCD |= PDM_VAD0_ZCD_VADZCDEN_MASK; + } + else + { + base->VAD0_ZCD &= ~PDM_VAD0_ZCD_VADZCDEN_MASK; + } +} + +/*! + * @brief Configure voice activity detector zero cross detector. + * + * @param base PDM base pointer + * @param config Voice activity detector zero cross detector configure structure pointer . + */ +void PDM_SetHwvadZeroCrossDetectorConfig(PDM_Type *base, const pdm_hwvad_zero_cross_detector_t *config); + +/*! + * @brief Reads noise data. + * + * @param base PDM base pointer. + * @return Data in PDM noise data register. + */ +static inline uint16_t PDM_GetNoiseData(PDM_Type *base) +{ + return (uint16_t)base->VAD0_NDATA; +} + +/*! + * @brief set hwvad internal filter status . + * Note: filter initial status should be asserted for two more cycles, then set it to normal operation. + * @param base PDM base pointer. + * @param status internal filter status. + */ +static inline void PDM_SetHwvadInternalFilterStatus(PDM_Type *base, pdm_hwvad_filter_status_t status) +{ + base->VAD0_CTRL_1 = (base->VAD0_CTRL_1 & (~PDM_VAD0_CTRL_1_VADST10_MASK)) | (uint32_t)status; +} + +/*! + * @brief set HWVAD in envelope based mode . + * Recommand configurations, + * @code + * static const pdm_hwvad_config_t hwvadConfig = { + * .channel = 0, + * .initializeTime = 10U, + * .cicOverSampleRate = 0U, + * .inputGain = 0U, + * .frameTime = 10U, + * .cutOffFreq = kPDM_HwvadHpfBypassed, + * .enableFrameEnergy = false, + * .enablePreFilter = true, +}; + + * static const pdm_hwvad_noise_filter_t noiseFilterConfig = { + * .enableAutoNoiseFilter = false, + * .enableNoiseMin = true, + * .enableNoiseDecimation = true, + * .noiseFilterAdjustment = 0U, + * .noiseGain = 7U, + * .enableNoiseDetectOR = true, + * }; + * @endcode + * @param base PDM base pointer. + * @param hwvadConfig internal filter status. + * @param noiseConfig Voice activity detector noise filter configure structure pointer. + * @param zcdConfig Voice activity detector zero cross detector configure structure pointer . + * @param signalGain signal gain value. + */ +void PDM_SetHwvadInEnvelopeBasedMode(PDM_Type *base, + const pdm_hwvad_config_t *hwvadConfig, + const pdm_hwvad_noise_filter_t *noiseConfig, + const pdm_hwvad_zero_cross_detector_t *zcdConfig, + uint32_t signalGain); + +/*! + * brief set HWVAD in energy based mode . + * Recommand configurations, + * code + * static const pdm_hwvad_config_t hwvadConfig = { + * .channel = 0, + * .initializeTime = 10U, + * .cicOverSampleRate = 0U, + * .inputGain = 0U, + * .frameTime = 10U, + * .cutOffFreq = kPDM_HwvadHpfBypassed, + * .enableFrameEnergy = true, + * .enablePreFilter = true, +}; + + * static const pdm_hwvad_noise_filter_t noiseFilterConfig = { + * .enableAutoNoiseFilter = true, + * .enableNoiseMin = false, + * .enableNoiseDecimation = false, + * .noiseFilterAdjustment = 0U, + * .noiseGain = 7U, + * .enableNoiseDetectOR = false, + * }; + * code + * param base PDM base pointer. + * param hwvadConfig internal filter status. + * param noiseConfig Voice activity detector noise filter configure structure pointer. + * param zcdConfig Voice activity detector zero cross detector configure structure pointer . + * param signalGain signal gain value, signal gain value should be properly according to application. + */ +void PDM_SetHwvadInEnergyBasedMode(PDM_Type *base, + const pdm_hwvad_config_t *hwvadConfig, + const pdm_hwvad_noise_filter_t *noiseConfig, + const pdm_hwvad_zero_cross_detector_t *zcdConfig, + uint32_t signalGain); + +/*! + * @brief Enable/Disable hwvad callback. + + * This function enable/disable the hwvad interrupt for the selected PDM peripheral. + * + * @param base Base address of the PDM peripheral. + * @param vadCallback callback Pointer to store callback function, should be NULL when disable. + * @param userData user data. + * @param enable true is enable, false is disable. + * @retval None. + */ +void PDM_EnableHwvadInterruptCallback(PDM_Type *base, pdm_hwvad_callback_t vadCallback, void *userData, bool enable); +/*! @} */ +#endif + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the PDM handle. + * + * This function initializes the handle for the PDM transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base PDM base pointer. + * @param handle PDM handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void PDM_TransferCreateHandle(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_callback_t callback, void *userData); + +/*! + * @brief PDM set channel transfer config. + * + * @param base PDM base pointer. + * @param handle PDM handle pointer. + * @param channel PDM channel. + * @param config channel config. + * @param format data format, support data width configurations,_pdm_data_width. + * @retval kStatus_PDM_ChannelConfig_Failed or kStatus_Success. + */ +status_t PDM_TransferSetChannelConfig( + PDM_Type *base, pdm_handle_t *handle, uint32_t channel, const pdm_channel_config_t *config, uint32_t format); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on PDM. + * + * @note This API returns immediately after the transfer initiates. + * Call the PDM_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_PDM_Busy, the transfer + * is finished. + * + * @param base PDM base pointer + * @param handle Pointer to the pdm_handle_t structure which stores the transfer state. + * @param xfer Pointer to the pdm_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_PDM_Busy Previous receive still not finished. + */ +status_t PDM_TransferReceiveNonBlocking(PDM_Type *base, pdm_handle_t *handle, pdm_transfer_t *xfer); + +/*! + * @brief Aborts the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base PDM base pointer + * @param handle Pointer to the pdm_handle_t structure which stores the transfer state. + */ +void PDM_TransferAbortReceive(PDM_Type *base, pdm_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base PDM base pointer. + * @param handle Pointer to the pdm_handle_t structure. + */ +void PDM_TransferHandleIRQ(PDM_Type *base, pdm_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* FSL_PDM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm_edma.c new file mode 100644 index 0000000000..3c8104b5f3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm_edma.c @@ -0,0 +1,459 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pdm_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pdm_edma" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) + +/*handle; + + if (!(pdmHandle->isLoopTransfer)) + { + (void)memset(&pdmHandle->tcd[pdmHandle->tcdDriver], 0, sizeof(edma_tcd_t)); + pdmHandle->tcdDriver = (pdmHandle->tcdDriver + 1U) % pdmHandle->tcdNum; + } + + pdmHandle->receivedBytes += + pdmHandle->tcd[pdmHandle->tcdDriver].BITER * (pdmHandle->tcd[pdmHandle->tcdDriver].NBYTES & 0x3FFU); + + /* If finished a block, call the callback function */ + if (pdmHandle->callback != NULL) + { + (pdmHandle->callback)(privHandle->base, pdmHandle, kStatus_PDM_Idle, pdmHandle->userData); + } + + pdmHandle->tcdUsedNum--; + /* If all data finished, just stop the transfer */ + if ((pdmHandle->tcdUsedNum == 0U) && !(pdmHandle->isLoopTransfer)) + { + /* Disable DMA enable bit */ + PDM_EnableDMA(privHandle->base, false); + EDMA_AbortTransfer(handle); + } +} + +/*! + * brief Initializes the PDM Rx eDMA handle. + * + * This function initializes the PDM slave DMA handle, which can be used for other PDM master transactional APIs. + * Usually, for a specified PDM instance, call this API once to get the initialized handle. + * + * param base PDM base pointer. + * param handle PDM eDMA handle pointer. + * param base PDM peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void PDM_TransferCreateHandleEDMA( + PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert((handle != NULL) && (dmaHandle != NULL)); + + uint32_t instance = PDM_GetInstance(base); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set pdm base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set PDM state to idle */ + handle->state = (uint32_t)kPDM_Idle; + + s_edmaPrivateHandle[instance].base = base; + s_edmaPrivateHandle[instance].handle = handle; + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, PDM_EDMACallback, &s_edmaPrivateHandle[instance]); +} + +/*! + * brief Initializes the multi PDM channel interleave type. + * + * This function initializes the PDM DMA handle member interleaveType, it shall be called only when application would + * like to use type kPDM_EDMAMultiChannelInterleavePerChannelBlock, since the default interleaveType is + * kPDM_EDMAMultiChannelInterleavePerChannelSample always + * + * param handle PDM eDMA handle pointer. + * param multiChannelInterleaveType Multi channel interleave type. + */ +void PDM_TransferSetMultiChannelInterleaveType(pdm_edma_handle_t *handle, + pdm_edma_multi_channel_interleave_t multiChannelInterleaveType) +{ + handle->interleaveType = multiChannelInterleaveType; +} + +/*! + * brief Install EDMA descriptor memory. + * + * param handle Pointer to EDMA channel transfer handle. + * param tcdAddr EDMA head descriptor address. + * param tcdNum EDMA link descriptor address. + */ +void PDM_TransferInstallEDMATCDMemory(pdm_edma_handle_t *handle, void *tcdAddr, size_t tcdNum) +{ + assert(handle != NULL); + + handle->tcd = (edma_tcd_t *)tcdAddr; + handle->tcdNum = tcdNum; +} + +/*! + * brief Configures the PDM channel. + * + * param base PDM base pointer. + * param handle PDM eDMA handle pointer. + * param channel channel index. + * param pdmConfig pdm channel configurations. + */ +void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, + pdm_edma_handle_t *handle, + uint32_t channel, + const pdm_channel_config_t *config) +{ + assert((handle != NULL) && (config != NULL)); + assert(channel < (uint32_t)FSL_FEATURE_PDM_CHANNEL_NUM); + + /* Configure the PDM channel */ + PDM_SetChannelConfig(base, channel, config); + + /* record end channel number */ + handle->endChannel = (uint8_t)channel; + /* increase totoal enabled channel number */ + handle->channelNums++; + /* increase count pre channel numbers */ + handle->count = (uint8_t)(base->FIFO_CTRL & PDM_FIFO_CTRL_FIFOWMK_MASK); +} + +/*! + * brief Performs a non-blocking PDM receive using eDMA. + * + * note This interface returns immediately after the transfer initiates. Call + * the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished. + * + * 1. Scatter gather case: + * This functio support dynamic scatter gather and staic scatter gather, + * a. for the dynamic scatter gather case: + * Application should call PDM_TransferReceiveEDMA function continuously to make sure new receive request is submit + *before the previous one finish. b. for the static scatter gather case: Application should use the link transfer + *feature and make sure a loop link transfer is provided, such as: code pdm_edma_transfer_t pdmXfer[2] = + * { + * { + * .data = s_buffer, + * .dataSize = BUFFER_SIZE, + * .linkTransfer = &pdmXfer[1], + * }, + * + * { + * .data = &s_buffer[BUFFER_SIZE], + * .dataSize = BUFFER_SIZE, + * .linkTransfer = &pdmXfer[0] + * }, + * }; + *endcode + * + * 2. Multi channel case: + * This function support receive multi pdm channel data, for example, if two channel is requested, + * code + * PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_0, &channelConfig); + * PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_1, &channelConfig); + * PDM_TransferReceiveEDMA(DEMO_PDM, &s_pdmRxHandle_0, pdmXfer); + * endcode + * The output data will be formatted as below if handle->interleaveType = + *kPDM_EDMAMultiChannelInterleavePerChannelSample : + * ------------------------------------------------------------------------- + * |CHANNEL0 | CHANNEL1 | CHANNEL0 | CHANNEL1 | CHANNEL0 | CHANNEL 1 | ....| + * ------------------------------------------------------------------------- + * + * The output data will be formatted as below if handle->interleaveType = kPDM_EDMAMultiChannelInterleavePerChannelBlock + *: + * ---------------------------------------------------------------------------------------------------------------------- + * |CHANNEL3 | CHANNEL3 | CHANNEL3 | .... | CHANNEL4 | CHANNEL 4 | CHANNEL4 |....| CHANNEL5 | CHANNEL 5 | CHANNEL5 + *|....| + * ---------------------------------------------------------------------------------------------------------------------- + * Note: the dataSize of xfer is the total data size, while application using + * kPDM_EDMAMultiChannelInterleavePerChannelBlock, the buffer size for each PDM channel is channelSize = dataSize / + * channelNums, there are limitation for this feature, + * 1. For 3 DMIC array: the dataSize shall be 4 * (channelSize) + * The addtional buffer is mandantory for edma modulo feature. + * 2. The kPDM_EDMAMultiChannelInterleavePerChannelBlock feature support below dmic array only, + * 2 DMIC array: CHANNEL3, CHANNEL4 + * 3 DMIC array: CHANNEL3, CHANNEL4, CHANNEL5 + * 4 DMIC array: CHANNEL3, CHANNEL4, CHANNEL5, CHANNEL6 + * Any other combinations is not support, that is to SAY, THE FEATURE SUPPORT RECEIVE START FROM CHANNEL3 ONLY AND 4 + * MAXIMUM DMIC CHANNELS. + * + * param base PDM base pointer + * param handle PDM eDMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a PDM eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_RxBusy PDM is busy receiving data. + */ +status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_transfer_t *xfer) +{ + assert((handle != NULL) && (xfer != NULL)); + + edma_transfer_config_t config = {0}; + uint32_t startAddr = PDM_GetDataRegisterAddress(base, handle->endChannel - (handle->channelNums - 1UL)); + pdm_edma_transfer_t *currentTransfer = xfer; + uint32_t nextTcdIndex = 0U, tcdIndex = handle->tcdUser, destOffset = FSL_FEATURE_PDM_FIFO_WIDTH; + uint32_t mappedChannel = handle->channelNums; + edma_modulo_t modulo = kEDMA_ModuloDisable; + /* minor offset used for channel sample interleave transfer */ + edma_minor_offset_config_t minorOffset = { + .enableSrcMinorOffset = true, + .enableDestMinorOffset = false, + .minorOffset = 0xFFFFFU - mappedChannel * (uint32_t)FSL_FEATURE_PDM_FIFO_OFFSET + 1U}; + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if ((handle->interleaveType == kPDM_EDMAMultiChannelInterleavePerChannelBlock) && (mappedChannel > 1U)) + { + /* Limitation of the feature, reference the API comments */ + if (((startAddr & 0xFU) != 0U) || (mappedChannel > 4U)) + { + return kStatus_InvalidArgument; + } + modulo = PDM_TransferMappingChannel(&mappedChannel); + if ((xfer->dataSize % mappedChannel) != 0U) + { + return kStatus_InvalidArgument; + } + destOffset = xfer->dataSize / mappedChannel; + /* reconfigure the minor loop offset for channel block interleave */ + minorOffset.enableSrcMinorOffset = false, minorOffset.enableDestMinorOffset = true, + minorOffset.minorOffset = + 0xFFFFFU - mappedChannel * (uint32_t)destOffset + (uint32_t)FSL_FEATURE_PDM_FIFO_WIDTH + 1U; + } + + while (currentTransfer != NULL) + { + if (handle->tcdUsedNum >= handle->tcdNum) + { + return kStatus_PDM_QueueFull; + } + else + { + uint32_t primask = DisableGlobalIRQ(); + handle->tcdUsedNum++; + EnableGlobalIRQ(primask); + } + + nextTcdIndex = (handle->tcdUser + 1U) % handle->tcdNum; + + if (mappedChannel == 1U) + { + EDMA_PrepareTransferConfig(&config, (void *)(uint32_t *)startAddr, FSL_FEATURE_PDM_FIFO_WIDTH, 0, + (uint8_t *)(uint32_t)currentTransfer->data, FSL_FEATURE_PDM_FIFO_WIDTH, + FSL_FEATURE_PDM_FIFO_WIDTH, handle->count * (uint32_t)FSL_FEATURE_PDM_FIFO_WIDTH, + currentTransfer->dataSize); + } + else + { + EDMA_PrepareTransferConfig(&config, (void *)(uint32_t *)startAddr, FSL_FEATURE_PDM_FIFO_WIDTH, + FSL_FEATURE_PDM_FIFO_OFFSET, (uint8_t *)(uint32_t)currentTransfer->data, + FSL_FEATURE_PDM_FIFO_WIDTH, (int16_t)destOffset, + mappedChannel * (uint32_t)FSL_FEATURE_PDM_FIFO_WIDTH, currentTransfer->dataSize); + } + + EDMA_TcdSetTransferConfig((edma_tcd_t *)&handle->tcd[handle->tcdUser], &config, + (edma_tcd_t *)&handle->tcd[nextTcdIndex]); + + if (mappedChannel > 1U) + { + EDMA_TcdSetMinorOffsetConfig((edma_tcd_t *)&handle->tcd[handle->tcdUser], &minorOffset); + + if (handle->interleaveType == kPDM_EDMAMultiChannelInterleavePerChannelBlock) + { + EDMA_TcdSetModulo((edma_tcd_t *)&handle->tcd[handle->tcdUser], modulo, kEDMA_ModuloDisable); + } + } + + EDMA_TcdEnableInterrupts((edma_tcd_t *)&handle->tcd[handle->tcdUser], (uint32_t)kEDMA_MajorInterruptEnable); + + handle->tcdUser = nextTcdIndex; + + currentTransfer = currentTransfer->linkTransfer; + + if (currentTransfer == xfer) + { + handle->isLoopTransfer = true; + break; + } + } + + if (handle->state != (uint32_t)kPDM_Busy) + { + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, (edma_tcd_t *)&handle->tcd[tcdIndex]); + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + PDM_EnableDMA(base, true); + /* enable PDM */ + PDM_Enable(base, true); + + handle->state = (uint32_t)kPDM_Busy; + } + + return kStatus_Success; +} + +/*! + * brief Aborts a PDM receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call PDM_TransferTerminateReceiveEDMA. + * + * param base PDM base pointer + * param handle PDM eDMA handle pointer. + */ +void PDM_TransferAbortReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + PDM_EnableDMA(base, false); + + /* Disable PDM */ + PDM_Enable(base, false); + + /* Handle the queue index */ + handle->tcdUsedNum--; + + /* Set the handle state */ + handle->state = (uint32_t)kPDM_Idle; +} + +/*! + * brief Terminate all PDM receive. + * + * This function will clear all transfer slots buffered in the pdm queue. If users only want to abort the + * current transfer slot, please call PDM_TransferAbortReceiveEDMA. + * + * param base PDM base pointer. + * param handle PDM eDMA handle pointer. + */ +void PDM_TransferTerminateReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Abort the current transfer */ + PDM_TransferAbortReceiveEDMA(base, handle); + + /* Clear all the internal information */ + (void)memset(handle->tcd, 0, sizeof(edma_tcd_t) * handle->tcdNum); + handle->tcdUser = 0U; + handle->tcdUsedNum = 0U; +} + +/*! + * brief Gets byte count received by PDM. + * + * param base PDM base pointer + * param handle PDM eDMA handle pointer. + * param count Bytes count received by PDM. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t PDM_TransferGetReceiveCountEDMA(PDM_Type *base, pdm_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + *count = handle->receivedBytes; + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm_edma.h new file mode 100644 index 0000000000..a1ca0442fa --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pdm_edma.h @@ -0,0 +1,254 @@ +/* + * Copyright 2019 - 2020, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_PDM_EDMA_H_ +#define FSL_PDM_EDMA_H_ + +#include "fsl_edma.h" +#include "fsl_pdm.h" + +/*! + * @addtogroup pdm_edma PDM EDMA Driver + * @ingroup pdm + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PDM_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 1)) /*!< Version 2.6.1 */ +/*@}*/ + +/*! @brief PDM edma handler */ +typedef struct _pdm_edma_handle pdm_edma_handle_t; + +/*!@brief pdm multi channel interleave type */ +typedef enum _pdm_edma_multi_channel_interleave +{ + kPDM_EDMAMultiChannelInterleavePerChannelSample = + 0U, /*!< multi channel PDM data interleave per channel sample + * ------------------------------------------------------------------------- + * |CHANNEL0 | CHANNEL1 | CHANNEL0 | CHANNEL1 | CHANNEL0 | CHANNEL 1 | ....| + * ------------------------------------------------------------------------- + */ + kPDM_EDMAMultiChannelInterleavePerChannelBlock = + 1U, /*!< multi channel PDM data interleave per channel block + * ---------------------------------------------------------------------------------------------------------------------------- + * |CHANNEL0 | CHANNEL0 | CHANNEL0 | ...... | CHANNEL1 | CHANNEL 1 | CHANNEL 1 | ....| CHANNEL2 | CHANNEL 2 + * | CHANNEL 2 | ....| + * ---------------------------------------------------------------------------------------------------------------------------- + */ +} pdm_edma_multi_channel_interleave_t; + +/*! @brief PDM edma transfer */ +typedef struct _pdm_edma_transfer +{ + volatile uint8_t *data; /*!< Data start address to transfer. */ + volatile size_t dataSize; /*!< Total Transfer bytes size. */ + struct _pdm_edma_transfer *linkTransfer; /*!< linked transfer configurations */ +} pdm_edma_transfer_t; + +/*! @brief PDM eDMA transfer callback function for finish and error */ +typedef void (*pdm_edma_callback_t)(PDM_Type *base, pdm_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief PDM DMA transfer handle, users should not touch the content of the handle.*/ +struct _pdm_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for PDM send */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t receivedBytes; /*!< total transfer count */ + uint32_t state; /*!< Internal state for PDM eDMA transfer */ + pdm_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + bool isLoopTransfer; /*!< loop transfer */ + void *userData; /*!< User callback parameter */ + edma_tcd_t *tcd; /*!< TCD pool for eDMA transfer. */ + uint32_t tcdNum; /*!< TCD number */ + uint32_t tcdUser; /*!< Index for user to queue transfer. */ + uint32_t tcdDriver; /*!< Index for driver to get the transfer data and size */ + volatile uint32_t tcdUsedNum; /*!< Index for user to queue transfer. */ + + pdm_edma_multi_channel_interleave_t interleaveType; /*!< multi channel transfer interleave type */ + + uint8_t endChannel; /*!< The last enabled channel */ + uint8_t channelNums; /*!< total channel numbers */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PDM eDMA Transactional + * @{ + */ + +/*! + * @brief Install EDMA descriptor memory. + * + * @param handle Pointer to EDMA channel transfer handle. + * @param tcdAddr EDMA head descriptor address. + * @param tcdNum EDMA link descriptor address. + */ +void PDM_TransferInstallEDMATCDMemory(pdm_edma_handle_t *handle, void *tcdAddr, size_t tcdNum); + +/*! + * @brief Initializes the PDM Rx eDMA handle. + * + * This function initializes the PDM slave DMA handle, which can be used for other PDM master transactional APIs. + * Usually, for a specified PDM instance, call this API once to get the initialized handle. + * + * @param base PDM base pointer. + * @param handle PDM eDMA handle pointer. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void PDM_TransferCreateHandleEDMA( + PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the multi PDM channel interleave type. + * + * This function initializes the PDM DMA handle member interleaveType, it shall be called only when application would + * like to use type kPDM_EDMAMultiChannelInterleavePerChannelBlock, since the default interleaveType is + * kPDM_EDMAMultiChannelInterleavePerChannelSample always + * + * @param handle PDM eDMA handle pointer. + * @param multiChannelInterleaveType Multi channel interleave type. + */ +void PDM_TransferSetMultiChannelInterleaveType(pdm_edma_handle_t *handle, + pdm_edma_multi_channel_interleave_t multiChannelInterleaveType); + +/*! + * @brief Configures the PDM channel. + * + * @param base PDM base pointer. + * @param handle PDM eDMA handle pointer. + * @param channel channel index. + * @param config pdm channel configurations. + */ +void PDM_TransferSetChannelConfigEDMA(PDM_Type *base, + pdm_edma_handle_t *handle, + uint32_t channel, + const pdm_channel_config_t *config); + +/*! + * @brief Performs a non-blocking PDM receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the PDM_GetReceiveRemainingBytes to poll the transfer status and check whether the PDM transfer is finished. + * + * 1. Scatter gather case: + * This functio support dynamic scatter gather and staic scatter gather, + * a. for the dynamic scatter gather case: + * Application should call PDM_TransferReceiveEDMA function continuously to make sure new receive request is submit + * before the previous one finish. b. for the static scatter gather case: Application should use the link transfer + * feature and make sure a loop link transfer is provided, such as: + * @code pdm_edma_transfer_t pdmXfer[2] = + * { + * { + * .data = s_buffer, + * .dataSize = BUFFER_SIZE, + * .linkTransfer = &pdmXfer[1], + * }, + * + * { + * .data = &s_buffer[BUFFER_SIZE], + * .dataSize = BUFFER_SIZE, + * .linkTransfer = &pdmXfer[0] + * }, + * }; + * @endcode + * + * 2. Multi channel case: + * This function support receive multi pdm channel data, for example, if two channel is requested, + * @code + * PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_0, &channelConfig); + * PDM_TransferSetChannelConfigEDMA(DEMO_PDM, &s_pdmRxHandle_0, DEMO_PDM_ENABLE_CHANNEL_1, &channelConfig); + * PDM_TransferReceiveEDMA(DEMO_PDM, &s_pdmRxHandle_0, pdmXfer); + * @endcode + * The output data will be formatted as below if handle->interleaveType = + * kPDM_EDMAMultiChannelInterleavePerChannelSample : + * ------------------------------------------------------------------------- + * |CHANNEL0 | CHANNEL1 | CHANNEL0 | CHANNEL1 | CHANNEL0 | CHANNEL 1 | ....| + * ------------------------------------------------------------------------- + * + * The output data will be formatted as below if handle->interleaveType = kPDM_EDMAMultiChannelInterleavePerChannelBlock + * : + * ---------------------------------------------------------------------------------------------------------------------- + * |CHANNEL3 | CHANNEL3 | CHANNEL3 | .... | CHANNEL4 | CHANNEL 4 | CHANNEL4 |....| CHANNEL5 | CHANNEL 5 | CHANNEL5 + * |....| + * ---------------------------------------------------------------------------------------------------------------------- + * Note: the dataSize of xfer is the total data size, while application using + * kPDM_EDMAMultiChannelInterleavePerChannelBlock, the buffer size for each PDM channel is channelSize = dataSize / + * channelNums, then there are limitation for this feature, + * 1. 3 DMIC array: the dataSize shall be 4 * (channelSize) + * The addtional buffer is mandantory for edma modulo feature. + * 2. The kPDM_EDMAMultiChannelInterleavePerChannelBlock feature support below dmic array only, + * 2 DMIC array: CHANNEL3, CHANNEL4 + * 3 DMIC array: CHANNEL3, CHANNEL4, CHANNEL5 + * 4 DMIC array: CHANNEL3, CHANNEL4, CHANNEL5, CHANNEL6 + * Any other combinations is not support, that is to SAY, THE FEATURE SUPPORT RECEIVE START FROM CHANNEL3 ONLY AND 4 + * MAXIMUM DMIC CHANNELS. + * + * @param base PDM base pointer + * @param handle PDM eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a PDM eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy PDM is busy receiving data. + */ +status_t PDM_TransferReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle, pdm_edma_transfer_t *xfer); + +/*! + * @brief Terminate all PDM receive. + * + * This function will clear all transfer slots buffered in the pdm queue. If users only want to abort the + * current transfer slot, please call PDM_TransferAbortReceiveEDMA. + * + * @param base PDM base pointer. + * @param handle PDM eDMA handle pointer. + */ +void PDM_TransferTerminateReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle); + +/*! + * @brief Aborts a PDM receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call PDM_TransferTerminateReceiveEDMA. + * + * @param base PDM base pointer + * @param handle PDM eDMA handle pointer. + */ +void PDM_TransferAbortReceiveEDMA(PDM_Type *base, pdm_edma_handle_t *handle); + +/*! + * @brief Gets byte count received by PDM. + * + * @param base PDM base pointer + * @param handle PDM eDMA handle pointer. + * @param count Bytes count received by PDM. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t PDM_TransferGetReceiveCountEDMA(PDM_Type *base, pdm_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pint.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pint.c new file mode 100644 index 0000000000..28745b270e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pint.c @@ -0,0 +1,1033 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for SECPINT(s). */ +static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; +#else + +#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[1] = PINT_IRQS; +#else +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; +#endif /* FSL_FEATURE_PINT_INTERRUPT_COMBINE */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Init(PINT_Type *base) +{ + uint32_t i; + uint32_t pmcfg = 0; + uint8_t pintcount = 0; + assert(base != NULL); + + if (base == PINT) + { + pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear SECPINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + + /* Disable all bit slices for pint*/ + for (i = 0; i < pintcount; i++) + { + pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#else + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ + + /* Disable all pattern match bit slices */ + base->PMCFG = pmcfg; +} + +/*! + * brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param intr Pin interrupt. + * param enable Selects detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) +{ + assert(base != NULL); + + /* Clear Rise and Fall flags first */ + PINT_PinInterruptClrRiseFlag(base, intr); + PINT_PinInterruptClrFallFlag(base, intr); + + /* Security PINT uses additional callback array */ + if (base == PINT) + { + s_pintCallback[intr] = callback; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + s_secpintCallback[intr] = callback; +#endif + } + + /* select level or edge sensitive */ + base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | + ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); + + /* enable rising or level interrupt */ + if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) + { + base->SIENR = 1UL << (uint32_t)intr; + } + else + { + base->CIENR = 1UL << (uint32_t)intr; + } + + /* Enable falling or select high level */ + if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) + { + base->SIENF = 1UL << (uint32_t)intr; + } + else + { + base->CIENF = 1UL << (uint32_t)intr; + } +} + +/*! + * brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param pintr Pin interrupt. + * param enable Pointer to store the detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) +{ + uint32_t mask; + bool level; + + assert(base != NULL); + + *enable = kPINT_PinIntEnableNone; + level = false; + + mask = 1UL << (uint32_t)pintr; + if ((base->ISEL & mask) != 0U) + { + /* Pin interrupt is level sensitive */ + level = true; + } + + if ((base->IENR & mask) != 0U) + { + if (level) + { + /* Level interrupt is enabled */ + *enable = kPINT_PinIntEnableLowLevel; + } + else + { + /* Rising edge interrupt */ + *enable = kPINT_PinIntEnableRiseEdge; + } + } + + if ((base->IENF & mask) != 0U) + { + if (level) + { + /* Level interrupt is active high */ + *enable = kPINT_PinIntEnableHighLevel; + } + else + { + /* Either falling or both edge */ + if (*enable == kPINT_PinIntEnableRiseEdge) + { + /* Rising and faling edge */ + *enable = kPINT_PinIntEnableBothEdges; + } + else + { + /* Falling edge */ + *enable = kPINT_PinIntEnableFallEdge; + } + } + } + + /* Security PINT uses additional callback array */ + if (base == PINT) + { + *callback = s_pintCallback[pintr]; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + *callback = s_secpintCallback[pintr]; +#endif + } +} + +/*! + * brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t pmcfg; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base != NULL); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + /* Input source selection for selected bit slice */ + base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); + + /* Bit slice configuration */ + pmcfg = base->PMCFG; + pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); + + /* If end point is true, enable the bits */ + if ((uint32_t)bslice != 7UL) + { + if (cfg->end_point) + { + pmcfg |= (1UL << (uint32_t)bslice); + } + else + { + pmcfg &= ~(1UL << (uint32_t)bslice); + } + } + + base->PMCFG = pmcfg; + + /* Save callback pointer */ + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_pintCallback[bslice] = cfg->callback; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_secpintCallback[bslice] = cfg->callback; + } +#endif + } +} + +/*! + * brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base != NULL); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); + + if ((uint32_t)bslice == 7U) + { + cfg->end_point = true; + } + else + { + cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; + } + + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_pintCallback[bslice]; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_secpintCallback[bslice]; + } +#endif + } +} + +/*! + * brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * param base Base address of the PINT peripheral. + * + * retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) +{ + uint32_t pmctrl; + uint32_t pmstatus; + uint32_t pmsrc; + + pmctrl = base->PMCTRL; + pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; + if (pmstatus != 0UL) + { + /* Reset Pattern match engine detection logic */ + pmsrc = base->PMSRC; + base->PMSRC = pmsrc; + } + return (pmstatus); +} + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); + uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + base->IST = (1UL << (uint32_t)pintr); + } +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base) +{ + uint32_t pinIntMode = 0; + uint32_t pinIntStatus = 0; + uint32_t pinIntCount = 0; + uint32_t mask = 0; + uint32_t i; + + if (base == PINT) + { + pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + + for (i = 0; i < pinIntCount; i++) + { + pinIntMode = base->ISEL & (1UL << i); + pinIntStatus = base->IST & (1UL << i); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + mask |= 1UL << i; + } + } + + base->IST = mask; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_EnableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + if (base == PINT) + { +#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + } + NVIC_ClearPendingIRQ(s_pintIRQ[0]); + (void)EnableIRQ(s_pintIRQ[0]); +#else + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + (void)EnableIRQ(s_pintIRQ[i]); + } +#endif + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +} + +/*! + * brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base != NULL); + + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* Get the right security pint irq index in array */ + if ((base == SECPINT) && ((uint32_t)pintIdx < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)) + { + pintIdx = + (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) + NVIC_ClearPendingIRQ(s_pintIRQ[0]); + (void)EnableIRQ(s_pintIRQ[0]); +#else + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + (void)EnableIRQ(s_pintIRQ[pintIdx]); +#endif +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void PINT_DisableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + if (base == PINT) + { +#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) + (void)DisableIRQ(s_pintIRQ[0]); + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + } + NVIC_ClearPendingIRQ(s_pintIRQ[0]); +#else + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } +#endif + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +} + +/*! + * brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base != NULL); + + if (base == PINT) + { +#if defined(FSL_FEATURE_PINT_INTERRUPT_COMBINE) && (FSL_FEATURE_PINT_INTERRUPT_COMBINE == 1) + (void)DisableIRQ(s_pintIRQ[0]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[0]); +#else + (void)DisableIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); +#endif + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); +#endif + } +} + +/*! + * brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Deinit(PINT_Type *base) +{ + uint32_t i; + + assert(base != NULL); + + /* Cleanup */ + PINT_DisableCallback(base); + if (base == PINT) + { + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* clear SECPINT callback array */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#else + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ +} +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) +{ + uint32_t pmstatus = 0; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_secpintCallback[kPINT_SecPinInt0] != NULL) + { + s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); + } + SDK_ISR_EXIT_BARRIER; +} + +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_secpintCallback[kPINT_SecPinInt1] != NULL) + { + s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +void PINT0_DriverIRQHandler(void); +void PINT0_DriverIRQHandler(void) +{ + uint32_t flags = (PINT->IST & PINT_IST_PSTAT_MASK) | PINT_PatternMatchGetStatusAll(PINT); + uint32_t pmstatus; + + for (uint8_t i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + if ((flags & (1UL << i)) != 0UL) + { + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[i] != NULL) + { + s_pintCallback[i]((pint_pin_int_t)i, pmstatus); + } + if ((PINT->ISEL & (1UL << i)) == 0x0UL) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)i); + } + } + } + + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void); +void PIN_INT0_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt0] != NULL) + { + s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); + } + if ((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } + SDK_ISR_EXIT_BARRIER; +} + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void); +void PIN_INT1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt1] != NULL) + { + s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); + } + if ((PINT->ISEL & 0x2U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void); +void PIN_INT2_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt2] != NULL) + { + s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); + } + if ((PINT->ISEL & 0x4U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void); +void PIN_INT3_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt3] != NULL) + { + s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); + } + if ((PINT->ISEL & 0x8U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void); +void PIN_INT4_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt4] != NULL) + { + s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); + } + if ((PINT->ISEL & 0x10U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void); +void PIN_INT5_DAC1_IRQHandler(void) +#else +void PIN_INT5_DriverIRQHandler(void); +void PIN_INT5_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt5] != NULL) + { + s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); + } + if ((PINT->ISEL & 0x20U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void); +void PIN_INT6_USART3_IRQHandler(void) +#else +void PIN_INT6_DriverIRQHandler(void); +void PIN_INT6_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt6] != NULL) + { + s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); + } + if ((PINT->ISEL & 0x40U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void); +void PIN_INT7_USART4_IRQHandler(void) +#else +void PIN_INT7_DriverIRQHandler(void); +void PIN_INT7_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt7] != NULL) + { + s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); + } + if ((PINT->ISEL & 0x80U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + } + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pint.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pint.h new file mode 100644 index 0000000000..41dae8c458 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pint.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_PINT_H_ +#define FSL_PINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 13)) +/*@}*/ + +/* Number of interrupt line supported by PINT */ +#define PINT_PIN_INT_COUNT 8U + +/* Number of interrupt line supported by SECURE PINT */ +#define SEC_PINT_PIN_INT_COUNT 2U + +/* Number of input sources supported by PINT */ +#define PINT_INPUT_COUNT 8U + +/* PININT Bit slice source register bits */ +#define PININT_BITSLICE_SRC_START 8U +#define PININT_BITSLICE_SRC_MASK 7U + +/* PININT Bit slice configuration register bits */ +#define PININT_BITSLICE_CFG_START 8U +#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_ENDP_MASK 7U + +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + +/*! @brief PINT Pin Interrupt enable type */ +typedef enum _pint_pin_enable +{ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ +} pint_pin_enable_t; + +/*! @brief PINT Pin Interrupt type */ +typedef enum _pint_int +{ + kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ +#endif +} pint_pin_int_t; + +/*! @brief PINT Pattern Match bit slice input source type */ +typedef enum _pint_pmatch_input_src +{ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ + kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ +} pint_pmatch_input_src_t; + +/*! @brief PINT Pattern Match bit slice type */ +typedef enum _pint_pmatch_bslice +{ + kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ +#endif +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#endif +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +} pint_pmatch_bslice_t; + +/*! @brief PINT Pattern Match configuration type */ +typedef enum _pint_pmatch_bslice_cfg +{ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ +} pint_pmatch_bslice_cfg_t; + +/*! @brief PINT Callback function. */ +typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); + +typedef struct _pint_pmatch_cfg +{ + pint_pmatch_input_src_t bs_src; + pint_pmatch_bslice_cfg_t bs_cfg; + bool end_point; + pint_cb_t callback; +} pint_pmatch_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Init(PINT_Type *base); + +/*! + * @brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param intr Pin interrupt. + * @param enable Selects detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); + +/*! + * @brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * @param enable Pointer to store the detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); + +/*! + * @brief Get Selected pin interrupt status. + + * This function returns the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base); + +/*! + * @brief Get all pin interrupts status. + + * This function returns the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the status of corresponding pin interrupt. + * = 0 No pin interrupt request. = 1 Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) +{ + return (base->IST); +} + +/*! + * @brief Clear Selected pin interrupt fall flag. + + * This function clears the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->FALL = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt fall flag. + + * This function returns the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt fall flags. + + * This function clears the fall flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) +{ + base->FALL = PINT_FALL_FDET_MASK; +} + +/*! + * @brief Get all pin interrupt fall flags. + + * This function returns the fall flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. + * 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) +{ + return (base->FALL); +} + +/*! + * @brief Clear Selected pin interrupt rise flag. + + * This function clears the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->RISE = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt rise flag. + + * This function returns the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt rise flags. + + * This function clears the rise flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) +{ + base->RISE = PINT_RISE_RDET_MASK; +} + +/*! + * @brief Get all pin interrupt rise flags. + + * This function returns the rise flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. + * 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) +{ + return (base->RISE); +} + +/*! + * @brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get pattern match bit slice status. + + * This function returns the status of selected bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * + * @retval status = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) +{ + return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; +} + +/*! + * @brief Get status of all pattern match bit slices. + + * This function returns the status of all bit slices. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the match status of corresponding bit slice. + * = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) +{ + return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; +} + +/*! + * @brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * @param base Base address of the PINT peripheral. + * + * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); + +/*! + * @brief Enable pattern match function. + + * This function enables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Disable pattern match function. + + * This function disables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Enable RXEV output. + + * This function enables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Disable RXEV output. + + * This function disables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_EnableCallback(PINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void PINT_DisableCallback(PINT_Type *base); + +/*! + * @brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Deinit(PINT_Type *base); + +/*! + * @brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * @param base Base address of the peripheral. + * @param pintIdx pin index. + * + * @retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +/*! + * @brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * @param base Base address of the peripheral. + * @param pintIdx pin index. + * + * @retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* FSL_PINT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_port.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_port.h new file mode 100644 index 0000000000..ded8005678 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_port.h @@ -0,0 +1,679 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_PORT_H_ +#define FSL_PORT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup port + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.port" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief PORT driver version. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*@}*/ + +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE +/*! @brief Internal resistor pull feature selection */ +enum _port_pull +{ + kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */ + kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */ + kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE +/*! @brief Internal resistor pull value selection */ +enum _port_pull_value +{ + kPORT_LowPullResistor = 0U, /*!< Low internal pull resistor value is selected. */ + kPORT_HighPullResistor = 1U, /*!< High internal pull resistor value is selected. */ +}; +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE +/*! @brief Slew rate selection */ +enum _port_slew_rate +{ + kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */ + kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! @brief Open Drain feature enable/disable */ +enum _port_open_drain_enable +{ + kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */ + kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER +/*! @brief Passive filter feature enable/disable */ +enum _port_passive_filter_enable +{ + kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */ + kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */ +}; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! @brief Configures the drive strength. */ +enum _port_drive_strength +{ + kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */ + kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */ + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 +/*! @brief Configures the drive strength1. */ +enum _port_drive_strength1 +{ + kPORT_NormalDriveStrength = 0U, /*!< Normal drive strength */ + kPORT_DoubleDriveStrength = 1U, /*!< Double drive strength */ +}; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */ + +#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER +/*! @brief input buffer disable/enable. */ +enum _port_input_buffer +{ + kPORT_InputBufferDisable = 0U, /*!< Digital input is disabled */ + kPORT_InputBufferEnable = 1U, /*!< Digital input is enabled */ +}; +#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */ + +#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT +/*! @brief Digital input is not inverted or it is inverted. */ +enum _port_invet_input +{ + kPORT_InputNormal = 0U, /*!< Digital input is not inverted */ + kPORT_InputInvert = 1U, /*!< Digital input is inverted */ +}; +#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */ + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! @brief Unlock/lock the pin control register field[15:0] */ +enum _port_lock_register +{ + kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ + kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief Pin mux selection */ +typedef enum _port_mux +{ + kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ + kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ + kPORT_MuxAlt0 = 0U, /*!< Chip-specific */ + kPORT_MuxAlt1 = 1U, /*!< Chip-specific */ + kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ + kPORT_MuxAlt3 = 3U, /*!< Chip-specific */ + kPORT_MuxAlt4 = 4U, /*!< Chip-specific */ + kPORT_MuxAlt5 = 5U, /*!< Chip-specific */ + kPORT_MuxAlt6 = 6U, /*!< Chip-specific */ + kPORT_MuxAlt7 = 7U, /*!< Chip-specific */ + kPORT_MuxAlt8 = 8U, /*!< Chip-specific */ + kPORT_MuxAlt9 = 9U, /*!< Chip-specific */ + kPORT_MuxAlt10 = 10U, /*!< Chip-specific */ + kPORT_MuxAlt11 = 11U, /*!< Chip-specific */ + kPORT_MuxAlt12 = 12U, /*!< Chip-specific */ + kPORT_MuxAlt13 = 13U, /*!< Chip-specific */ + kPORT_MuxAlt14 = 14U, /*!< Chip-specific */ + kPORT_MuxAlt15 = 15U, /*!< Chip-specific */ +} port_mux_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! @brief Configures the interrupt generation condition. */ +typedef enum _port_interrupt +{ + kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ +#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST || defined(DOXYGEN_OUTPUT) + kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ +#endif +#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG || defined(DOXYGEN_OUTPUT) + kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ +#endif + kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ +#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER || defined(DOXYGEN_OUTPUT) + kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +#endif +} port_interrupt_t; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! @brief Digital filter clock source selection */ +typedef enum _port_digital_filter_clock_source +{ + kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ + kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ +} port_digital_filter_clock_source_t; + +/*! @brief PORT digital filter feature configuration definition */ +typedef struct _port_digital_filter_config +{ + uint32_t digitalFilterWidth; /*!< Set digital filter width */ + port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ +} port_digital_filter_config_t; +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief PORT pin configuration structure */ +typedef struct _port_pin_config +{ +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE + uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */ +#else + uint16_t : 2; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE + uint16_t pullValueSelect : 1; /*!< Pull value select */ +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE + uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + +#if !(defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER + uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH + uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */ +#else + uint16_t : 1; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 + uint16_t driveStrength1 : 1; /*!< Normal/Double drive strength enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3) + uint16_t mux : 3; /*!< Pin mux Configure */ + uint16_t : 1; +#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4) + uint16_t mux : 4; /*!< Pin mux Configure */ +#else + uint16_t : 4; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER + uint16_t inputBuffer : 1; /*!< Input Buffer Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */ + +#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT + uint16_t invertInput : 1; /*!< Invert Input Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */ + + uint16_t : 1; + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK + uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ +} port_pin_config_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER +/*! @brief PORT version information. */ +typedef struct _port_version_info +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor Version Number. */ + uint8_t major; /*!< Major Version Number. */ +} port_version_info_t; +#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE +/*! @brief PORT voltage range. */ +typedef enum _port_voltage_range +{ + kPORT_VoltageRange1Dot71V_3Dot6V = 0x0U, /*!< Port voltage range is 1.71 V - 3.6 V. */ + kPORT_VoltageRange2Dot70V_3Dot6V = 0x1U, /*!< Port voltage range is 2.70 V - 3.6 V. */ +} port_voltage_range_t; +#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @name Configuration */ +/*@{*/ + +#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER +/*! + * @brief Get PORT version information. + * + * @param base PORT peripheral base pointer + * @param info PORT version information + */ +static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info) +{ + uint32_t verid = base->VERID; + info->feature = (uint16_t)verid; + info->minor = (uint8_t)(verid >> PORT_VERID_MINOR_SHIFT); + info->major = (uint8_t)(verid >> PORT_VERID_MAJOR_SHIFT); +} +#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE +/*! + * @brief Get PORT version information. + * + * @note : PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and + * PORTC_CONFIG[RANGE] does not take effect. + * + * @param base PORT peripheral base pointer + * @param range port voltage range + */ +static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range) +{ + base->CONFIG = (uint32_t)range; +} +#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */ + +/*! + * @brief Sets the port PCR register. + * + * This is an example to define an input pin or output pin PCR configuration. + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnLockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) +{ + assert(config); + uint32_t addr = (uint32_t)&base->PCR[pin]; + *(volatile uint16_t *)(addr) = *((const uint16_t *)(const void *)config); +} + +/*! + * @brief Sets the port PCR register for multiple pins. + * + * This is an example to define input pins or output pins PCR configuration. + * @code + * Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp , + * kPORT_PullEnable, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnlockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) +{ + assert(config); + + uint16_t pcrl = *((const uint16_t *)(const void *)config); + + if (0U != (mask & 0xffffU)) + { + base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; + } + if (0U != (mask >> 16)) + { + base->GPCHR = (mask & 0xffff0000U) | pcrl; + } +} + +#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG +/*! + * @brief Sets the port interrupt configuration in PCR register for multiple pins. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config) +{ + assert(config); + + if (0U != ((uint32_t)mask & 0xffffU)) + { + base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU); + } + mask = mask >> 16; + if (0U != mask) + { + base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU); + } +} +#endif + +/*! + * @brief Configures the pin muxing. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param mux pin muxing slot selection. + * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. + * - #kPORT_MuxAsGpio : Set as GPIO. + * - #kPORT_MuxAlt2 : chip-specific. + * - #kPORT_MuxAlt3 : chip-specific. + * - #kPORT_MuxAlt4 : chip-specific. + * - #kPORT_MuxAlt5 : chip-specific. + * - #kPORT_MuxAlt6 : chip-specific. + * - #kPORT_MuxAlt7 : chip-specific. + * @note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because + * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is + * reset to zero : kPORT_PinDisabledOrAnalog). + * This function is recommended to use to reset the pin mux + * + */ +static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); +} +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER + +/*! + * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param enable PORT digital filter configuration. + */ +static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) +{ + if (enable == true) + { + base->DFER |= mask; + } + else + { + base->DFER &= ~mask; + } +} + +/*! + * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param config PORT digital filter configuration structure. + */ +static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) +{ + assert(config); + + base->DFCR = PORT_DFCR_CS(config->clockSource); + base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); +} + +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ +/*@}*/ + +/*! @name Interrupt */ +/*@{*/ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); +} +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! + * @brief Configures the port pin drive strength. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param strength PORT pin drive strength + * - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured. + * - #kPORT_HighDriveStrength = 1U - High-drive strength is configured. + */ +static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); +} +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 +/*! + * @brief Enables the port pin double drive strength. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param enable PORT pin drive strength configuration. + */ +static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable); +} +#endif + +#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE +/*! + * @brief Configures the port pin pull value. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param value PORT pin pull value + * - #kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected. + * - #kPORT_HighPullResistor = 1U - High internal pull resistor value is selected. + */ +static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value); +} +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Reads the whole port status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base PORT peripheral base pointer. + * @return Current port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 16 have the interrupt. + */ +static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) +{ + return base->ISFR; +} + +/*! + * @brief Clears the multiple pin interrupt status flag. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + */ +static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) +{ + base->ISFR = mask; +} +#endif + +#if defined(FSL_FEATURE_PORT_SUPPORT_EFT) && FSL_FEATURE_PORT_SUPPORT_EFT +/*! + * @brief Get EFT detect flags. + * + * @param base PORT peripheral base pointer + * @return EFT detect flags + */ +static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base) +{ + return base->EDFR; +} + +/*! + * @brief Enable EFT detect interrupts. + * + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt) +{ + base->EDIER |= interrupt; +} + +/*! + * @brief Disable EFT detect interrupts. + * + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt) +{ + base->EDIER &= ~interrupt; +} + +/*! + * @brief Clear all low EFT detector. + * + * @note : Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the + * PORTB_EDCR does not take effect. + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base) +{ + base->EDCR |= PORT_EDCR_EDLC_MASK; + base->EDCR &= ~PORT_EDCR_EDLC_MASK; +} + +/*! + * @brief Clear all high EFT detector. + * + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base) +{ + base->EDCR |= PORT_EDCR_EDHC_MASK; + base->EDCR &= ~PORT_EDCR_EDHC_MASK; +} +#endif /* FSL_FEATURE_PORT_SUPPORT_EFT */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_PORT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_puf_v3.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_puf_v3.c new file mode 100644 index 0000000000..de5ff296b3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_puf_v3.c @@ -0,0 +1,1000 @@ +/* + * Copyright 2020,2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_puf_v3.h" +#include "fsl_clock.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.puf_v3" +#endif + +#define kPUF_OperationInProgress (0x0u) +#define kPUF_Enroll (0x1u) +#define kPUF_Start (0x2u) +#define kPUF_Stop (0x5u) +#define kPUF_GetKey (0x6u) +#define kPUF_Unwrap (0x7u) +#define kPUF_WrapGeneratedRandom (0x8u) +#define kPUF_Wrap (0x9u) +#define kPUF_GenerateRandom (0xfu) +#define kPUF_Test (0x1fu) +#define kPUF_Init (0x20u) +#define kPUF_Zeroize (0x2fu) +typedef uint32_t puf_last_operation_t; + +#define PUF_KEY_OPERATION_CONTEXT_TYPE (0x10UL << 16UL) +#define PUF_CONTEXT_GENERIC_KEY_TYPE (0x0u) +#define PUF_CONTEXT_KEY_LEN_MASK (0x1fffu) + +/******************************************************************************* + * Code + ******************************************************************************/ + +static status_t puf_waitForInit(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ + while (0u == base->SR) + { + } + + /* wait if busy */ + while ((base->SR & PUF_SR_BUSY_MASK) != 0u) + { + } + + /* return status */ + if (0U != (base->SR & (PUF_SR_OK_MASK | PUF_SR_ERROR_MASK))) + { + status = kStatus_Success; + } + + return status; +} + +static void puf_powerOn(PUF_Type *base, puf_config_t *conf) +{ + /* Power On PUF SRAM */ + base->SRAM_CFG = 0x1u; + while (0u == (PUF_SRAM_STATUS_READY_MASK & base->SRAM_STATUS)) + { + } +} + +static status_t puf_powerCycle(PUF_Type *base, puf_config_t *conf) +{ + /* Power off */ + base->SRAM_CFG = 0x0u; + + /* Reset PUF and reenable power to PUF SRAM */ + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); + puf_powerOn(base, conf); + + return kStatus_Success; +} + +static status_t puf_makeStatus(PUF_Type *base, puf_last_operation_t operation) +{ + uint32_t result; + status_t status = kStatus_Fail; + + if (((base->ORR & PUF_ORR_LAST_OPERATION_MASK) >> PUF_ORR_LAST_OPERATION_SHIFT) == operation) + { + result = (base->ORR & PUF_ORR_RESULT_CODE_MASK); + if ((result == kPUF_ResultOK) && (0u == (base->SR & PUF_SR_ERROR_MASK))) + { + status = kStatus_Success; + } + else + { + status = MAKE_STATUS((int32_t)kStatusGroup_PUF, (int32_t)result); + } + } + + return status; +} + +/*! + * brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * @param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf) +{ + /* Default configuration after reset */ + conf->dataEndianness = kPUF_EndianBig; + conf->CKGATING = 0U; +} + +/*! + * brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * @param conf PUF configuration structure + * @return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, puf_config_t *conf) +{ + status_t status = kStatus_Fail; + + /* Enable PUF clock */ + CLOCK_EnableClock(kCLOCK_Puf); + + /* Clear the PUF peripheral reset */ + RESET_ClearPeripheralReset(kPUF_RST_SHIFT_RSTn); + + /* Reset PUF */ +#if defined(FSL_FEATURE_PUF_HAS_RESET) && FSL_FEATURE_PUF_HAS_RESET + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_PUF_HAS_RESET */ + + /* Set configuration from SRAM */ + base->SRAM_CFG |= PUF_SRAM_CFG_CKGATING(conf->CKGATING); + + /* Enable power to PUF SRAM */ + puf_powerOn(base, conf); + + /* Wait for peripheral to become ready */ + status = puf_waitForInit(base); + + /* In case of error or enroll & start not allowed, do power-cycle */ + if ((status != kStatus_Success) || ((PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK) != + (base->AR & (PUF_AR_ALLOW_ENROLL_MASK | PUF_AR_ALLOW_START_MASK)))) + { + (void)puf_powerCycle(base, conf); + status = puf_waitForInit(base); + } + + if (kStatus_Success == status) + { + /* Set data endianness */ + base->MISC = PUF_MISC_DATA_ENDIANNESS(conf->dataEndianness); + + /* get status */ + status = puf_makeStatus(base, kPUF_Init); + } + + return status; +} + +/*! + * brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + */ +void PUF_Deinit(PUF_Type *base, puf_config_t *conf) +{ + base->SRAM_CFG = 0x0u; + + RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); + CLOCK_DisableClock(kCLOCK_Puf); +} + +/*! + * brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * @param base PUF peripheral base address + * @param[out] activationCode Word aligned address of the resulting activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize, uint8_t *score) +{ + status_t status = kStatus_Fail; + uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code buffer size is at least FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ + if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned and valid activationCode */ + if ((0U != (0x3u & (uintptr_t)activationCode)) || (activationCode == NULL)) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (uint32_t *)(uintptr_t)activationCode; + + /* check if ENROLL is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_ENROLL_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_ENROLL_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_ENROLL_MASK)) + { + } + + /* read out AC */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + temp32 = base->DOR; + if (activationCodeSize >= sizeof(uint32_t)) + { + *activationCodeAligned = temp32; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + } + } + + /* In case of success fill in score */ + if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) + { + *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Enroll); + + return status; +} + +/*! + * brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * @param base PUF peripheral base address + * @param[in] activationCode Word aligned address of the input activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. + * @param score Value of the PUF Score that was obtained during the start operation. + * return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize, uint8_t *score) +{ + status_t status = kStatus_Fail; + const uint32_t *activationCodeAligned = NULL; + register uint32_t temp32 = 0; + + /* check that activation code size is at least FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ + if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE) + { + return kStatus_InvalidArgument; + } + + /* Set activationCodeSize to FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes */ + activationCodeSize = PUF_ACTIVATION_CODE_SIZE; + + /* only work with aligned activationCode */ + if ((0U != (0x3u & (uintptr_t)activationCode)) || (activationCode == NULL)) + { + return kStatus_InvalidArgument; + } + + activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; + + /* check if START is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_START_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_START_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_START_MASK)) + { + } + + /* while busy send AC */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + if (activationCodeSize >= sizeof(uint32_t)) + { + temp32 = *activationCodeAligned; + activationCodeAligned++; + activationCodeSize -= sizeof(uint32_t); + } + /* Send AC again */ + else + { + activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode; + temp32 = *activationCodeAligned; + activationCodeAligned++; + activationCodeSize = PUF_ACTIVATION_CODE_SIZE - sizeof(uint32_t); + } + base->DIR = temp32; + } + } + + /* In case of success fill in score */ + if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) + { + *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Start); + + return status; +} + +/*! + * brief Stop PUF + * + * The Stop operation removes all key material from PUF flipflops and PUF SRAM, and sets + * PUF to the Stopped state. + * + * @param base PUF peripheral base address + * @return Status of stop operation. + */ +status_t PUF_Stop(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* check if STOP is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_STOP_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_STOP_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_STOP_MASK)) + { + } + + /* wait while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Stop); + + return status; +} + +/*! + * brief PUF Get Key + * + * The Get Key operation derives a key from the intrinsic PUF key and externally provided context. + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keyDest output destination of the derived PUF key + * @param[out] key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the derived key in bytes. + * @return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDest, uint8_t *key, size_t keySize) +{ + uint8_t idx = 0; + uint32_t *keyAligned = NULL; + uint32_t context[4] = {0}; + status_t status = kStatus_Fail; + + /* check if GET KEY is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_GET_KEY_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for key context */ + if (keyCtx == NULL) + { + return kStatus_InvalidArgument; + } + + /* check for valid key destination */ + if (((keyDest == kPUF_KeyDestRegister) && (key == NULL)) || (keyDest == kPUF_KeyDestInvalid)) + { + return kStatus_InvalidArgument; + } + + /* check for valid key size. */ + /* must be 8byte multiple */ + if (0U != (keySize & 0x7u)) + { + return kStatus_InvalidArgument; + } + /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned key */ + if (0U != (0x3u & (uintptr_t)key)) + { + return kStatus_InvalidArgument; + } + + keyAligned = (uint32_t *)(uintptr_t)key; + + /* fill in key context */ + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & PUF_CONTEXT_KEY_LEN_MASK); + context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; + context[2] = keyCtx->userCtx0; + context[3] = keyCtx->userCtx1; + + /* set key destination */ + base->DATA_DEST = keyDest; + + /* begin */ + base->CR = PUF_CR_GET_KEY_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_GET_KEY_MASK)) + { + } + + /* send context and read output data while busy */ + while (0U != (base->SR & PUF_SR_BUSY_MASK)) + { + if ((0U != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) + { + base->DIR = context[idx]; + idx++; + } + + if ((0U != (PUF_SR_DO_REQUEST_MASK & base->SR)) && (kPUF_KeyDestRegister == keyDest)) + { + if (keySize >= sizeof(uint32_t)) + { + *keyAligned = base->DOR; + keyAligned++; + keySize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_GetKey); + + return status; +} + +/*! + * brief PUF Wrap generated random + * + * The Wrap Generated Random operation wraps a random key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keySize Size of the key to be generated in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap generated random operation. + */ +status_t PUF_WrapGeneratedRandom( + PUF_Type *base, puf_key_ctx_t *keyCtx, size_t keySize, uint8_t *keyCode, size_t keyCodeSize) +{ + uint8_t idx = 0; + uint32_t *keyCodeAligned = NULL; + uint32_t context[4] = {0}; + status_t status = kStatus_Fail; + + /* check if WRAP GENERATED RANDOM is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_WRAP_GENERATED_RANDOM_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid key context and keyCode buffer */ + if ((keyCtx == NULL) || (keyCode == NULL)) + { + return kStatus_InvalidArgument; + } + + /* check for valid key size. */ + /* must be 8byte multiple */ + if (0U != (keySize & 0x7u)) + { + return kStatus_InvalidArgument; + } + /* if keySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + if ((keySize > 128u) && !((keySize == 256u) || (keySize == 384u) || (keySize == 512u))) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given keySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize)) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned key code */ + if (0U != (0x3u & (uintptr_t)keyCode)) + { + return kStatus_InvalidArgument; + } + + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* fill in key context */ + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((keySize * 8u) & 0x1FFFu); + context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; + context[2] = keyCtx->userCtx0; + context[3] = keyCtx->userCtx1; + + /* begin */ + base->CR = PUF_CR_WRAP_GENERATED_RANDOM_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_WRAP_GENERATED_RANDOM_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if ((0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) && (idx < 4u)) + { + base->DIR = context[idx]; + idx++; + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = base->DOR; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_WrapGeneratedRandom); + + return status; +} + +/*! + * brief PUF Wrap user key + * + * The Wrap operation wraps a user defined key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct. + * @param userKey Word aligned address of input user key. + * @param userKeySize Size of the key to be wrapped in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap operation. + */ +status_t PUF_Wrap( + PUF_Type *base, puf_key_ctx_t *keyCtx, uint8_t *userKey, size_t userKeySize, uint8_t *keyCode, size_t keyCodeSize) +{ + uint8_t ctxIdx = 0; + uint32_t *userKeyAligned = NULL; + uint32_t *keyCodeAligned = NULL; + uint32_t context[4] = {0}; + status_t status = kStatus_Fail; + + /* check if WRAP is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_WRAP_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid keyCtx and keyCode pointers */ + if ((keyCtx == NULL) || (keyCode == NULL)) + { + return kStatus_InvalidArgument; + } + + /* check for valid userKey size. */ + /* must be 8byte multiple */ + if (0U != (userKeySize & 0x7u)) + { + return kStatus_InvalidArgument; + } + /* if userKeySize > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + if ((userKeySize > 128u) && !((userKeySize == 256u) || (userKeySize == 384u) || (userKeySize == 512u))) + { + return kStatus_InvalidArgument; + } + + /* check that keyCodeSize is correct for given userKeySize */ + if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize)) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned userKey and key code */ + if (0U != ((0x3u & (uintptr_t)userKey)) || (0U != (0x3u & (uintptr_t)keyCode))) + { + return kStatus_InvalidArgument; + } + + userKeyAligned = (uint32_t *)(uintptr_t)userKey; + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* fill in key context */ + context[0] = PUF_KEY_OPERATION_CONTEXT_TYPE | ((userKeySize * 8u) & 0x1FFFu); + context[1] = PUF_CONTEXT_GENERIC_KEY_TYPE | (keyCtx->keyScopeStarted << 8u) | keyCtx->keyScopeEnrolled; + context[2] = keyCtx->userCtx0; + context[3] = keyCtx->userCtx1; + + /* begin */ + base->CR = PUF_CR_WRAP_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_WRAP_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + /* send context first */ + if (ctxIdx < 4u) + { + base->DIR = context[ctxIdx]; + ctxIdx++; + } + /* send userKey */ + else + { + base->DIR = *userKeyAligned; + userKeyAligned++; + } + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + *keyCodeAligned = base->DOR; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Wrap); + + return status; +} + +/*! + * brief PUF Unwrap user key + * + * The unwrap operation unwraps the key from a previously created Key Code (KC) + * + * @param base PUF peripheral base address + * @param keyDest output destination of the unwraped PUF key + * @param[in] keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the input keycode in bytes. + * @param key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the key to be generated in bytes. + * @return Status of unwrap operation. + */ +status_t PUF_Unwrap( + PUF_Type *base, puf_key_dest_t keyDest, uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize) +{ + uint32_t *keyAligned = NULL; + uint32_t *keyCodeAligned = NULL; + status_t status = kStatus_Fail; + + /* check if UNWRAP is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_UNWRAP_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid key destination */ + if (((keyDest == kPUF_KeyDestRegister) && (key == NULL)) || (keyDest == kPUF_KeyDestInvalid)) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned key and key code */ + if ((0U != (0x3u & (uintptr_t)key)) || (0U != (0x3u & (uintptr_t)keyCode)) || (keyCode == NULL)) + { + return kStatus_InvalidArgument; + } + + keyAligned = (uint32_t *)(uintptr_t)key; + keyCodeAligned = (uint32_t *)(uintptr_t)keyCode; + + /* set key destination */ + base->DATA_DEST = keyDest; + + /* begin */ + base->CR = PUF_CR_UNWRAP_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_UNWRAP_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + if (keyCodeSize >= sizeof(uint32_t)) + { + base->DIR = *keyCodeAligned; + keyCodeAligned++; + keyCodeSize -= sizeof(uint32_t); + } + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + if (keySize >= sizeof(uint32_t)) + { + *keyAligned = base->DOR; + keyAligned++; + keySize -= sizeof(uint32_t); + } + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_Unwrap); + + return status; +} + +/*! + * brief Generate Random + * + * The Generate Random operation outputs the requested amount of random data as specified in a + * provided context. + * + * @param base PUF peripheral base address + * @param size Size of random data to be genarated in bytes. + * @return Status of generate random operation. + */ +status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size) +{ + uint32_t context; + uint32_t *dataAligned = NULL; + status_t status = kStatus_Fail; + + if (data == NULL) + { + return kStatus_InvalidArgument; + } + + /* check if Generate random is allowed */ + if (0u == (base->AR & PUF_AR_ALLOW_GENERATE_RANDOM_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* check for valid size. */ + /* must be 8byte multiple */ + if (0U != (size & 0x7u)) + { + return kStatus_InvalidArgument; + } + /* if size > 128bytes, it must be equal to 256bytes or 384bytes or 512bytes */ + if ((size > 128u) && !((size == 256u) || (size == 384u) || (size == 512u))) + { + return kStatus_InvalidArgument; + } + + /* only work with aligned data buffer */ + if (0U != (0x3u & (uintptr_t)data)) + { + return kStatus_InvalidArgument; + } + + /* Configure context */ + context = ((size * 8u) & 0x1FFFu); + + dataAligned = (uint32_t *)(uintptr_t)data; + + /* begin */ + base->DATA_DEST = PUF_DATA_DEST_DEST_DOR_MASK; + + base->CR = PUF_CR_GENERATE_RANDOM_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_GENERATE_RANDOM_MASK)) + { + } + + /* send context and read output data while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + if (0u != (PUF_SR_DI_REQUEST_MASK & base->SR)) + { + base->DIR = context; + } + + if (0u != (PUF_SR_DO_REQUEST_MASK & base->SR)) + { + *dataAligned = base->DOR; + dataAligned++; + } + } + + /* get status */ + status = puf_makeStatus(base, kPUF_GenerateRandom); + + return status; +} + +/*! + * brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to zeroized state. + * + * @param base PUF peripheral base address + * @return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base) +{ + status_t status = kStatus_Fail; + + /* zeroize command is always allowed */ + base->CR = PUF_CR_ZEROIZE_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_ZEROIZE_MASK)) + { + } + + /* wait while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + } + + /* check status */ + if (((PUF_SR_ZEROIZED_MASK | PUF_SR_OK_MASK) == base->SR) && (0u == base->AR)) + { + status = puf_makeStatus(base, kPUF_Zeroize); + } + + return status; +} + +/*! + * brief Test PUF + * + * With the Test PUF operation, diagnostics about the PUF quality is collected and presented in a PUF + * score. + * + * @param base PUF peripheral base address + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of the test operation. + */ +status_t PUF_Test(PUF_Type *base, uint8_t *score) +{ + status_t status = kStatus_Fail; + + /* check if TEST is allowed */ + if (0x0u == (base->AR & PUF_AR_ALLOW_TEST_PUF_MASK)) + { + return kStatus_PUF_OperationNotAllowed; + } + + /* begin */ + base->CR = PUF_CR_TEST_PUF_MASK; + + /* wait till command is accepted */ + while (0u != (base->CR & PUF_CR_TEST_PUF_MASK)) + { + } + + /* wait while busy */ + while (0u != (base->SR & PUF_SR_BUSY_MASK)) + { + } + + /* In case of success fill in score */ + if ((0u != (base->SR & PUF_SR_OK_MASK)) && (score != NULL)) + { + *score = (uint8_t)(base->PSR & PUF_PSR_PUF_SCORE_MASK); + } + + /* Check status */ + status = puf_makeStatus(base, kPUF_Test); + + return status; +} + +/*! + * brief Set lock of PUF operation + * + * Lock the security level of PUF block until key generate, wrap or unwrap operation is completed. + * Note: Only secure-privilege code can change the security level. + * + * @param base PUF peripheral base address + * @param securityLevel Security level of PUF block. + * @return Status of the test operation. + */ +status_t PUF_SetLock(PUF_Type *base, puf_sec_level_t securityLevel) +{ + uint32_t sec_lock_option = 0u; + + if ((securityLevel != kPUF_NonsecureUser) && (securityLevel != kPUF_NonsecurePrivilege) && + (securityLevel != kPUF_SecureUser) && (securityLevel != kPUF_SecurePrivilege)) + { + return kStatus_InvalidArgument; + } + + /* Wait until PUF is in IDLE */ + while ((base->SR & PUF_SR_BUSY_MASK) != 0u) + { + } + + /* Prepare SEC_LOCK option word */ + /* [1:0] - Security level */ + /* [3:2] - anti-pole of security level [1:0] */ + /* [15:4] - PATTERN: This field must be written as 0xAC5 */ + sec_lock_option = SEC_LOCK_PATTERN | securityLevel; + + /* Apply setings */ + base->SEC_LOCK = sec_lock_option; + + /* Check if the security level is same as the level written */ + if (securityLevel != base->SEC_LOCK) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +/*! + * brief Set App Context mask + * + * This function sets Application defined context mask used in conjunction with key user context 2. + * Whenever bit in this register is 1, corresponding bit in user context 2 provided + * during key code creation should be zero only. + * + * This register is only modifiable by task running at secure-privilege level. + * + * @param base PUF peripheral base address + * @param appCtxMask Value of the Application defined context mask. + * @return Status of the test operation. + */ +status_t PUF_SetCtxMask(PUF_Type *base, uint32_t appCtxMask) +{ + base->APP_CTX_MASK = appCtxMask; + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_puf_v3.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_puf_v3.h new file mode 100644 index 0000000000..1acf08484d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_puf_v3.h @@ -0,0 +1,325 @@ +/* + * Copyright 2017-2018,2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PUF_V3_H_ +#define _PUF_V3_H_ + +#include +#include + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @addtogroup puf_v3_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief PUFv3 driver version. Version 2.0.2. + * + * Current version: 2.0.2 + * + * Change log: + * - 2.0.2 + * - Fix MISRA issue in driver. + * - 2.0.1 + * - Fix PUF initialization issue and update driver to reflect SoC header changes. + * - 2.0.0 + * - Initial version. + */ +#define FSL_PUF_V3_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +#define kPUF_EndianLittle (0x0u) +#define kPUF_EndianBig (0x1u) +typedef uint32_t puf_endianness_t; + +#define kPUF_KeyDestRegister (0x1u) +#define kPUF_KeyDestKeyBus (0x2u) +#define kPUF_KeyDestInvalid (0x3u) +typedef uint32_t puf_key_dest_t; + +#define kPUF_KeyAllowRegister (0x1u) +#define kPUF_KeyAllowKeyBus (0x2u) +#define kPUF_KeyAllowAll (0x3u) +typedef uint32_t puf_key_scope_t; + +#define kPUF_ResultOK (0x0u) +#define kPUF_AcNotForThisProductPhase1 (0xf0u) +#define kPUF_AcNotForThisProductPhase2 (0xf1u) +#define kPUF_AcCorruptedPhase1 (0xf2u) +#define kPUF_AcCorruptedPhase2 (0xf3u) +#define kPUF_AcAuthFailedPhase1 (0xf4u) +#define kPUF_AcAuthFailedPhase2 (0xf5u) +#define kPUF_QualityVerificationFail (0xf6u) +#define kPUF_ContextIncorrect (0xf7u) +#define kPUF_DestinationNotAllowed (0xf8u) +#define kPUF_Failure (0xFFu) +typedef uint32_t puf_result_code_t; + +#define kPUF_NonsecureUser (0xCu) /* b1100 */ +#define kPUF_NonsecurePrivilege (0x9u) /* b1001 */ +#define kPUF_SecureUser (0x6u) /* b0110 */ +#define kPUF_SecurePrivilege (0x3u) /* b0011 */ +typedef uint32_t puf_sec_level_t; + +typedef struct +{ + puf_endianness_t dataEndianness; + uint8_t CKGATING; +} puf_config_t; + +typedef struct +{ + puf_key_scope_t keyScopeStarted; + puf_key_scope_t keyScopeEnrolled; + uint32_t userCtx0; + uint32_t userCtx1; +} puf_key_ctx_t; + +#define PUF_ACTIVATION_CODE_SIZE (size_t)(FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE) +#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((0x34u + (x)) + 0x10u * ((x) / 0x32u)) +#define SEC_LOCK_PATTERN 0xAC50u + +enum +{ + kStatus_PUF_OperationNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 0xA5), + kStatus_PUF_AcNotForThisProductPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcNotForThisProductPhase1), + kStatus_PUF_AcNotForThisProductPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcNotForThisProductPhase2), + kStatus_PUF_AcCorruptedPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcCorruptedPhase1), + kStatus_PUF_AcCorruptedPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcCorruptedPhase2), + kStatus_PUF_AcAuthFailedPhase1 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcAuthFailedPhase1), + kStatus_PUF_NBOOT_AcAuthFailedPhase2 = MAKE_STATUS(kStatusGroup_PUF, kPUF_AcAuthFailedPhase2), + kStatus_PUF_QualityVerificationFail = MAKE_STATUS(kStatusGroup_PUF, kPUF_QualityVerificationFail), + kStatus_PUF_ContextIncorrect = MAKE_STATUS(kStatusGroup_PUF, kPUF_ContextIncorrect), + kStatus_PUF_DestinationNotAllowed = MAKE_STATUS(kStatusGroup_PUF, kPUF_DestinationNotAllowed), + kStatus_PUF_Failure = MAKE_STATUS(kStatusGroup_PUF, kPUF_Failure), +}; + +/******************************************************************************* + * API + *******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * @param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf); + +/*! + * brief Initialize PUF + * + * This function enables power to PUF block and waits until the block initializes. + * + * @param conf PUF configuration structure + * @return Status of the init operation + */ +status_t PUF_Init(PUF_Type *base, puf_config_t *conf); + +/*! + * brief Denitialize PUF + * + * This function disables power to PUF SRAM and peripheral clock. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + */ +void PUF_Deinit(PUF_Type *base, puf_config_t *conf); + +/*! + * brief Enroll PUF + * + * This function derives a digital fingerprint, generates the corresponding Activation Code (AC) + * and returns it to be stored in an NVM or a file. This step needs to be + * performed only once for each device. This function may be permanently disallowed by a fuse. + * + * @param base PUF peripheral base address + * @param[out] activationCode Word aligned address of the resulting activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of enroll operation. + */ +status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize, uint8_t *score); + +/*! + * brief Start PUF + * + * The Activation Code generated during the Enroll operation is used to + * reconstruct the digital fingerprint. This needs to be done after every power-up + * and reset. + * + * @param base PUF peripheral base address + * @param[in] activationCode Word aligned address of the input activation code. + * @param activationCodeSize Size of the activationCode buffer in bytes. Shall be FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE bytes. + * @param score Value of the PUF Score that was obtained during the start operation. + * return Status of start operation. + */ +status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize, uint8_t *score); + +/*! + * brief Stop PUF + * + * The Stop operation removes all key material from PUF flipflops and PUF SRAM, and sets + * PUF to the Stopped state. + * + * @param base PUF peripheral base address + * @return Status of stop operation. + */ +status_t PUF_Stop(PUF_Type *base); + +/*! + * brief PUF Get Key + * + * The Get Key operation derives a key from the intrinsic PUF key and externally provided context. + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keyDest output destination of the derived PUF key + * @param[out] key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the derived key in bytes. + * @return Status of get key operation. + */ +status_t PUF_GetKey(PUF_Type *base, puf_key_ctx_t *keyCtx, puf_key_dest_t keyDest, uint8_t *key, size_t keySize); + +/*! + * brief PUF Wrap generated random + * + * The Wrap Generated Random operation wraps a random key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct + * @param keySize Size of the key to be generated in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap generated random operation. + */ +status_t PUF_WrapGeneratedRandom( + PUF_Type *base, puf_key_ctx_t *keyCtx, size_t keySize, uint8_t *keyCode, size_t keyCodeSize); + +/*! + * brief PUF Wrap user key + * + * The Wrap operation wraps a user defined key into a Key Code (KC). + * + * @param base PUF peripheral base address + * @param keyCtx PUF key context struct. + * @param userKey Word aligned address of input user key. + * @param userKeySize Size of the key to be wrapped in bytes. + * @param[out] keyCode Word aligned address of the resulting key code. + * @param keyCodeSize Size of the output keycode in bytes. + * @return Status of wrap operation. + */ +status_t PUF_Wrap( + PUF_Type *base, puf_key_ctx_t *keyCtx, uint8_t *userKey, size_t userKeySize, uint8_t *keyCode, size_t keyCodeSize); + +/*! + * brief PUF Unwrap user key + * + * The unwrap operation unwraps the key from a previously created Key Code (KC) + * + * @param base PUF peripheral base address + * @param keyDest output destination of the unwraped PUF key + * @param[in] keyCode Word aligned address of the input key code. + * @param keyCodeSize Size of the input keycode in bytes. + * @param key Word aligned address of output key (only used when kPUF_KeyDestRegister). + * @param keySize Size of the key to be generated in bytes. + * @return Status of unwrap operation. + */ +status_t PUF_Unwrap( + PUF_Type *base, puf_key_dest_t keyDest, uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize); + +/*! + * brief Generate Random + * + * The Generate Random operation outputs the requested amount of random data as specified in a + * provided context. + * + * @param base PUF peripheral base address + * @param size Size of random data to be genarated in bytes. + * @return Status of generate random operation. + */ +status_t PUF_GenerateRandom(PUF_Type *base, uint8_t *data, size_t size); + +/*! + * brief Zeroize PUF + * + * This function clears all PUF internal logic and puts the PUF to zeroized state. + * + * @param base PUF peripheral base address + * @return Status of the zeroize operation. + */ +status_t PUF_Zeroize(PUF_Type *base); + +/*! + * brief Test PUF + * + * With the Test PUF operation, diagnostics about the PUF quality is collected and presented in a PUF + * score. + * + * @param base PUF peripheral base address + * @param score Value of the PUF Score that was obtained during the enroll operation. + * @return Status of the test operation. + */ +status_t PUF_Test(PUF_Type *base, uint8_t *score); + +/*! + * @brief Blocks specified PUF commands + * + * This function blocks PUF commands specified by mask parameter. + * + * @param base PUF peripheral base address + * @param mask Mask of parameters which should be blocked until power-cycle. + * @return Status of the test operation. + */ +static inline void PUF_BlockCommand(PUF_Type *base, uint32_t mask) +{ + base->CONFIG |= mask; +} + +/*! + * brief Set lock of PUF operation + * + * Lock the security level of PUF block until key generate, wrap or unwrap operation is completed. + * Note: Only security level defined in SEC_LOCK register can use PUFv3 or change its security level. + * Default setting after leaving ROM is Secure-Privilege + * + * @param base PUF peripheral base address + * @param securityLevel Security level of PUF block. + * @return Status of the test operation. + */ +status_t PUF_SetLock(PUF_Type *base, puf_sec_level_t securityLevel); + +/*! + * brief Set App Context mask + * + * This function sets Application defined context mask used in conjunction with key user context 2. + * Whenever bit in this register is 1, corresponding bit in user context 2 provided + * during key code creation should be zero only. + * + * This register is only modifiable by task running at secure-privilege level. + * + * @param base PUF peripheral base address + * @param appCtxMask Value of the Application defined context mask. + * @return Status of the test operation. + */ +status_t PUF_SetCtxMask(PUF_Type *base, uint32_t appCtxMask); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _PUF_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pwm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pwm.c new file mode 100644 index 0000000000..f227249ef0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pwm.c @@ -0,0 +1,1466 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pwm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pwm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PWM peripheral base address + * + * @return The PWM module instance + */ +static uint32_t PWM_GetInstance(PWM_Type *base); + +#if defined(PWM_RSTS) +#define PWM_RESETS_ARRAY PWM_RSTS +#elif defined(FLEXPWM_RSTS) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS +#elif defined(FLEXPWM_RSTS_N) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS_N +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PWM bases for each instance. */ +static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PWM clocks for each PWM submodule. */ +static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(PWM_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_pwmResets[] = PWM_RESETS_ARRAY; +#endif + +/*! @brief Temporary PWM duty cycle. */ +static uint8_t s_pwmGetPwmDutyCycle[FSL_FEATURE_PWM_SUBMODULE_COUNT][PWM_SUBMODULE_CHANNEL] = {{0}}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Complement the variable of type uint16_t as needed + * + * This function can complement the variable of type uint16_t as needed.For example, + * need to ask for the opposite of a positive integer. + * + * param value Parameters of type uint16_t + */ +static inline uint16_t PWM_GetComplementU16(uint16_t value) +{ + return (~value + 1U); +} + +static inline uint16_t dutyCycleToReloadValue(uint8_t dutyCyclePercent) +{ + /* Rounding calculations to improve the accuracy of reloadValue */ + return ((65535U * dutyCyclePercent) + 50U) / 100U; +} + +static uint32_t PWM_GetInstance(PWM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++) + { + if (s_pwmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pwmBases)); + + return instance; +} + +/*! + * brief Set register about period on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + */ +static void PWM_SetPeriodRegister(PWM_Type *base, pwm_submodule_t subModule, pwm_mode_t mode, uint16_t pulseCnt) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM period for a signed center aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_CenterAligned: + /* Setup the PWM period for an unsigned center aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + case kPWM_SignedEdgeAligned: + /* Setup the PWM period for a signed edge aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_EdgeAligned: + /* Setup the PWM period for a unsigned edge aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + default: + assert(false); + break; + } +} + +/*! + * brief Set register about dutycycle on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + * param dutyCycle New PWM pulse width, value should be between 0 to 65535 + */ +static void PWM_SetDutycycleRegister(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t mode, + uint16_t pulseCnt, + uint16_t pwmHighPulse) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM dutycycle for a signed center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL3 = (pwmHighPulse / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL5 = (pwmHighPulse / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_CenterAligned: + /* Setup the PWM dutycycle for an unsigned center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_SignedEdgeAligned: + modulo = (pulseCnt >> 1U); + + /* Setup the PWM dutycycle for a signed edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_EdgeAligned: + /* Setup the PWM dutycycle for a unsigned edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + default: + assert(false); + break; + } +} + +/*! + * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the PWM driver. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param config Pointer to user's PWM config structure. + * + * return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) +{ + assert(config); + + uint16_t reg; + + /* Source clock for submodule 0 cannot be itself */ + if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + + /* Reload source select clock for submodule 0 cannot be master reload */ + if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PWM submodule clock*/ + CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(PWM_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_pwmResets[PWM_GetInstance(base)]); +#endif + + /* Clear the fault status flags */ + base->FSTS |= PWM_FSTS_FFLAG_MASK; + + reg = base->SM[subModule].CTRL2; + + /* Setup the submodule clock-source, control source of the INIT signal, + * source of the force output signal, operation in debug & wait modes and reload source select + */ + reg &= + ~(uint16_t)(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | PWM_CTRL2_INDEP_MASK | +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + PWM_CTRL2_WAITEN_MASK | +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK); + reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | + PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) | +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + PWM_CTRL2_WAITEN(config->enableWait) | +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + PWM_CTRL2_RELOAD_SEL(config->reloadSelect)); + + /* Setup PWM A & B to be independent or a complementary-pair */ + switch (config->pairOperation) + { + case kPWM_Independent: + reg |= PWM_CTRL2_INDEP_MASK; + break; + case kPWM_ComplementaryPwmA: + base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); + break; + case kPWM_ComplementaryPwmB: + base->MCTRL |= ((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } + base->SM[subModule].CTRL2 = reg; + + reg = base->SM[subModule].CTRL; + + /* Setup the clock prescale, load mode and frequency */ + reg &= ~(uint16_t)(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); + reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); + + /* Setup register reload logic */ + switch (config->reloadLogic) + { + case kPWM_ReloadImmediate: + reg |= PWM_CTRL_LDMOD_MASK; + break; + case kPWM_ReloadPwmHalfCycle: + reg |= PWM_CTRL_HALF_MASK; + reg &= (uint16_t)(~PWM_CTRL_FULL_MASK); + break; + case kPWM_ReloadPwmFullCycle: + reg &= (uint16_t)(~PWM_CTRL_HALF_MASK); + reg |= PWM_CTRL_FULL_MASK; + break; + case kPWM_ReloadPwmHalfAndFullCycle: + reg |= PWM_CTRL_HALF_MASK; + reg |= PWM_CTRL_FULL_MASK; + break; + default: + assert(false); + break; + } + base->SM[subModule].CTRL = reg; + + /* Set PWM output normal */ +#if defined(PWM_MASK_UPDATE_MASK) + base->MASK &= (uint16_t)(~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | + PWM_MASK_MASKB_MASK | PWM_MASK_UPDATE_MASK_MASK)); +#else + base->MASK &= ~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK); +#endif + + base->DTSRCSEL = 0U; + + /* Issue a Force trigger event when configured to trigger locally */ + if (config->forceTrigger == kPWM_Force_Local) + { + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); + } + + return kStatus_Success; +} + +/*! + * brief Gate the PWM submodule clock + * + * param base PWM peripheral base address + * param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) +{ + /* Stop the submodule */ + base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_RUN_SHIFT + (uint16_t)subModule)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PWM submodule clock*/ + CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fill in the PWM config struct with the default settings + * + * The default values are: + * code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * endcode + * param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* PWM is paused in debug mode */ + config->enableDebugMode = false; + /* PWM is paused in wait mode */ +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + config->enableWait = false; +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + /* PWM module uses the local reload signal to reload registers */ + config->reloadSelect = kPWM_LocalReload; + /* Use the IP Bus clock as source clock for the PWM submodule */ + config->clockSource = kPWM_BusClock; + /* Clock source prescale is set to divide by 1*/ + config->prescale = kPWM_Prescale_Divide_1; + /* Local sync causes initialization */ + config->initializationControl = kPWM_Initialize_LocalSync; + /* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + config->forceTrigger = kPWM_Force_Local; + /* PWM reload frequency, reload opportunity is PWM half cycle or full cycle. + * This field is not used in Immediate reload mode + */ + config->reloadFrequency = kPWM_LoadEveryOportunity; + /* Buffered-registers get loaded with new values as soon as LDOK bit is set */ + config->reloadLogic = kPWM_ReloadImmediate; + /* PWM A & PWM B operate as 2 independent channels */ + config->pairOperation = kPWM_Independent; +} + +/*! + * brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param chnlParams Array of PWM channel parameters to configure the channel(s), PWMX submodule is not supported. + * param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. + * + * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + assert(pwmFreq_Hz); + assert(numOfChnls); + assert(srcClock_Hz); + + uint32_t pwmClock; + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint8_t i, polarityShift = 0, outputEnableShift = 0; + + for (i = 0; i < numOfChnls; i++) + { + if (chnlParams[i].pwmChannel == kPWM_PwmX) + { + /* PWMX configuration is not supported yet */ + return kStatus_Fail; + } + } + + /* Divide the clock by the prescale value */ + pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); + pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz); + + /* Setup each PWM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U; + + /* Setup the different match registers to generate the PWM signal */ + if (i == 0U) + { + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, mode, pulseCnt); + } + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, chnlParams->pwmChannel, mode, pulseCnt, pwmHighPulse); + + /* Setup register shift values based on the channel being configured. + * Also setup the deadtime value + */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + polarityShift = PWM_OCTRL_POLA_SHIFT; + outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; + base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); + } + else + { + polarityShift = PWM_OCTRL_POLB_SHIFT; + outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; + base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); + } + + /* Set PWM output fault status */ + switch (chnlParams->pwmChannel) + { + case kPWM_PwmA: + base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); + base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & + (uint16_t)PWM_OCTRL_PWMAFS_MASK); + break; + case kPWM_PwmB: + base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); + base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & + (uint16_t)PWM_OCTRL_PWMBFS_MASK); + break; + default: + assert(false); + break; + } + + /* Setup signal active level */ + if ((bool)chnlParams->level == kPWM_HighTrue) + { + base->SM[subModule].OCTRL &= ~((uint16_t)1U << (uint16_t)polarityShift); + } + else + { + base->SM[subModule].OCTRL |= ((uint16_t)1U << (uint16_t)polarityShift); + } + if (chnlParams->pwmchannelenable) + { + /* Enable PWM output */ + base->OUTEN |= ((uint16_t)1U << ((uint16_t)outputEnableShift + (uint16_t)subModule)); + } + + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][chnlParams->pwmChannel] = chnlParams->dutyCyclePercent; + + /* Get the next channel parameters */ + chnlParams++; + } + + return kStatus_Success; +} + +/*! + * brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz PWM main counter clock in Hz. + * param shiftvalue Phase shift value, range in 0 ~ 50 + * param doSync true: Set LDOK bit for the submodule list; + * false: LDOK bit don't set, need to call PWM_SetPwmLdok to sync update. + * + * return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise + */ +status_t PWM_SetupPwmPhaseShift(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint8_t shiftvalue, + bool doSync) +{ + assert(pwmFreq_Hz != 0U); + assert(srcClock_Hz != 0U); + assert(shiftvalue <= 50U); + + uint32_t pwmClock; + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint16_t modulo = 0; + uint16_t shift = 0; + + if (pwmChannel != kPWM_PwmX) + { + /* Divide the clock by the prescale value */ + pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); + pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz); + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + + /* Immediately upon when MCTRL[LDOK] being set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + + /* phase shift value */ + shift = (pulseCnt * shiftvalue) / 100U; + + /* duty cycle 50% */ + pwmHighPulse = pulseCnt / 2U; + + if (pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo) + shift; + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse + shift - 1U; + } + else if (pwmChannel == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo) + shift; + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse + shift - 1U; + } + else + { + return kStatus_Fail; + } + + if (doSync) + { + /* Set LDOK bit to load VALx bit */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + } + } + else + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +/*! + * brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent) +{ + assert(dutyCyclePercent <= 100U); + assert(pwmSignal != kPWM_PwmX); + uint16_t reloadValue = dutyCycleToReloadValue(dutyCyclePercent); + + PWM_UpdatePwmDutycycleHighAccuracy(base, subModule, pwmSignal, currPwmMode, reloadValue); +} + +/*! + * brief Updates the PWM signal's dutycycle with 16-bit accuracy. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCycle New PWM pulse width, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycleHighAccuracy( + PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle) +{ + assert(pwmSignal != kPWM_PwmX); + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint16_t modulo = 0; + + switch (currPwmMode) + { + case kPWM_SignedCenterAligned: + modulo = base->SM[subModule].VAL1 + 1U; + pulseCnt = modulo * 2U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + case kPWM_CenterAligned: + pulseCnt = base->SM[subModule].VAL1 + 1U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + case kPWM_SignedEdgeAligned: + modulo = base->SM[subModule].VAL1 + 1U; + pulseCnt = modulo * 2U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + case kPWM_EdgeAligned: + pulseCnt = base->SM[subModule].VAL1 + 1U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + default: + assert(false); + break; + } + + /* Update register about dutycycle */ + if (kPWM_PwmA == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmA, currPwmMode, pulseCnt, pwmHighPulse); + } + else if (kPWM_PwmB == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmB, currPwmMode, pulseCnt, pwmHighPulse); + } + else + { + ; /* Intentional empty */ + } + + if (kPWM_PwmX != pwmSignal) + { + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle * 100U / 65535U); + } +} + +/*! + * brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original dutycycle or update new dutycycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle) +{ + uint16_t pwmHighPulse = 0; + + assert(pwmSignal != kPWM_PwmX); + + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, currPwmMode, pulseCnt); + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, pwmSignal, currPwmMode, pulseCnt, pwmHighPulse); + + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)((dutyCycle * 100U) / 65535U); +} + +/*! + * brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel in the submodule to setup + * param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams) +{ + uint16_t reg = 0; + switch (pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + /* Setup the capture paramters for PWM A pin */ + reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) | + PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLA_ARMA_MASK; + + base->SM[subModule].CAPTCTRLA = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue); + /* Setup PWM A pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + /* Setup the capture paramters for PWM B pin */ + reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) | + PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLB_ARMB_MASK; + + base->SM[subModule].CAPTCTRLB = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue); + /* Setup PWM B pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | + PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLX_ARMX_MASK; + + base->SM[subModule].CAPTCTRLX = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue); + /* Setup PWM X pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} + +/*! + * @brief Sets up the PWM fault input filter. + * + * @param base PWM peripheral base address + * @param faultInputFilterParams Parameters passed in to set up the fault input filter. + */ +void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams) +{ + assert(NULL != faultInputFilterParams); + + /* When changing values for fault period from a non-zero value, first write a value of 0 to clear the filter. */ + if (0U != (base->FFILT & PWM_FFILT_FILT_PER_MASK)) + { + base->FFILT &= ~(uint16_t)(PWM_FFILT_FILT_PER_MASK); + } + + base->FFILT = (uint16_t)(PWM_FFILT_FILT_PER(faultInputFilterParams->faultFilterPeriod) | + PWM_FFILT_FILT_CNT(faultInputFilterParams->faultFilterCount) | + PWM_FFILT_GSTR(faultInputFilterParams->faultGlitchStretch ? 1U : 0U)); +} + +/*! + * brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * param base PWM peripheral base address + * param faultNum PWM fault to configure. + * param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) +{ + assert(faultParams); + uint16_t reg; + + reg = base->FCTRL; + /* Set the faults level-settting */ + if (faultParams->faultLevel) + { + reg |= ((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); + } + else + { + reg &= ~((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); + } + /* Set the fault clearing mode */ + if ((uint16_t)faultParams->faultClearingMode != 0U) + { + /* Use manual fault clearing */ + reg &= ~((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); + if (faultParams->faultClearingMode == kPWM_ManualSafety) + { + /* Use manual fault clearing with safety mode enabled */ + reg |= ((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); + } + else + { + /* Use manual fault clearing with safety mode disabled */ + reg &= ~((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); + } + } + else + { + /* Use automatic fault clearing */ + reg |= ((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); + } + base->FCTRL = reg; + + /* Set the combinational path option */ + if (faultParams->enableCombinationalPath) + { + /* Combinational path from the fault input to the PWM output is available */ + base->FCTRL2 &= ~((uint16_t)1U << (uint16_t)faultNum); + } + else + { + /* No combinational path available, only fault filter & latch signal can disable PWM output */ + base->FCTRL2 |= ((uint16_t)1U << (uint16_t)faultNum); + } + + /* Initially clear both recovery modes */ + reg = base->FSTS; + reg &= ~(((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)) | + ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum))); + /* Setup fault recovery */ + switch (faultParams->recoverMode) + { + case kPWM_NoRecovery: + break; + case kPWM_RecoverHalfCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); + break; + case kPWM_RecoverFullCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); + break; + case kPWM_RecoverHalfAndFullCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); + reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); + break; + default: + assert(false); + break; + } + base->FSTS = reg; +} + +/*! + * brief Fill in the PWM fault config struct with the default settings + * + * The default values are: + * code + * config->faultClearingMode = kPWM_Automatic; + * config->faultLevel = false; + * config->enableCombinationalPath = true; + * config->recoverMode = kPWM_NoRecovery; + * endcode + * param config Pointer to user's PWM fault config structure. + */ +void PWM_FaultDefaultConfig(pwm_fault_param_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* PWM uses automatic fault clear mode */ + config->faultClearingMode = kPWM_Automatic; + /* PWM fault level is set to logic 0 */ + config->faultLevel = false; + /* Combinational Path from fault input is enabled */ + config->enableCombinationalPath = true; + /* PWM output will stay inactive when recovering from a fault */ + config->recoverMode = kPWM_NoRecovery; +} + +/*! + * brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel to configure + * param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) + +{ + uint16_t shift; + uint16_t reg; + + /* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */ + shift = ((uint16_t)subModule * 4U) + ((uint16_t)pwmChannel * 2U); + + /* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */ + reg = base->DTSRCSEL; + reg &= ~((uint16_t)0x3U << shift); + reg |= (uint16_t)((uint16_t)mode << shift); + base->DTSRCSEL = reg; +} + +/*! + * brief Enables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + /* Upper 16 bits are for related to the submodule */ + base->SM[subModule].INTEN |= ((uint16_t)mask & 0xFFFFU); + /* Fault related interrupts */ + base->FCTRL |= ((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Disables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + base->SM[subModule].INTEN &= ~((uint16_t)mask & 0xFFFFU); + base->FCTRL &= ~((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Gets the enabled PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t enabledInterrupts; + + enabledInterrupts = base->SM[subModule].INTEN; + enabledInterrupts |= (((uint32_t)base->FCTRL & PWM_FCTRL_FIE_MASK) << 16UL); + return enabledInterrupts; +} + +/*! + * brief Gets the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t statusFlags; + + statusFlags = base->SM[subModule].STS; + statusFlags |= (((uint32_t)base->FSTS & PWM_FSTS_FFLAG_MASK) << 16UL); + + return statusFlags; +} + +/*! + * brief Clears the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + uint16_t reg; + + base->SM[subModule].STS = ((uint16_t)mask & 0xFFFFU); + reg = base->FSTS; + /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared + * by writing a login one + */ + reg &= ~(uint16_t)(PWM_FSTS_FFLAG_MASK); + reg |= (uint16_t)((mask >> 16U) & PWM_FSTS_FFLAG_MASK); + base->FSTS = reg; +} + +/*! + * brief Set PWM output in idle status (high or low). + * + * note This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported. + * + * param base PWM peripheral base address + * param pwmChannel PWM channel to configure + * param subModule PWM submodule to configure + * param idleStatus True: PWM output is high in idle status; false: PWM output is low in idle status. + * + * return kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success + */ +status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus) +{ + uint16_t valOn = 0, valOff = 0; + uint16_t ldmod; + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + + valOff = base->SM[subModule].INIT; + valOn = base->SM[subModule].VAL1 + 0x1U; + + if ((valOff + 1U) == valOn) + { + return kStatus_Fail; + } + + /* Should not PWM_X channel */ + if (kPWM_PwmA == pwmChannel) + { + if (0U != (base->SM[subModule].OCTRL & PWM_OCTRL_POLA_MASK)) + { + if (!idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + else + { + if (idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + base->SM[subModule].VAL2 = valOn; + base->SM[subModule].VAL3 = valOff; + } + else if (kPWM_PwmB == pwmChannel) + { + if (0U != (base->SM[subModule].OCTRL & PWM_OCTRL_POLB_MASK)) + { + if (!idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + else + { + if (idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + base->SM[subModule].VAL4 = valOn; + base->SM[subModule].VAL5 = valOff; + } + else + { + return kStatus_Fail; + } + + /* Record Load mode */ + ldmod = base->SM[subModule].CTRL; + /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + /* Set LDOK bit to load buffer registers */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + /* Restore Load mode */ + base->SM[subModule].CTRL = ldmod; + + /* Get pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmChannel] = 0x0U; + + return kStatus_Success; +} + +/*! + * brief Get the dutycycle value. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * + * return Current channel dutycycle value. + */ +uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel) +{ + return s_pwmGetPwmDutyCycle[subModule][pwmChannel]; +} + +/*! + * brief Set the pwm submodule prescaler. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param prescaler Set prescaler value + */ +void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler) +{ + uint16_t reg = base->SM[subModule].CTRL; + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + /* Set submodule prescaler. */ + reg &= ~(uint16_t)PWM_CTRL_PRSC_MASK; + reg |= PWM_CTRL_PRSC(prescaler); + base->SM[subModule].CTRL = reg; + /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + /* Set LDOK bit to load buffer registers */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + /* Restore Load mode */ + base->SM[subModule].CTRL = reg; +} + +/*! + * brief This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0. + * + * param base PWM peripheral base address + * param pwmChannel PWM channel to configure + * param subModule PWM submodule to configure + * param forcetozero True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal + * function. + */ +void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero) +{ +#if !defined(PWM_MASK_UPDATE_MASK) + uint16_t reg = base->SM[subModule].CTRL2; +#endif + uint16_t mask; + + if (kPWM_PwmA == pwmChannel) + { + mask = PWM_MASK_MASKA(0x01UL << (uint8_t)subModule); + } + else if (kPWM_PwmB == pwmChannel) + { + mask = PWM_MASK_MASKB(0x01UL << (uint8_t)subModule); + } + else + { + mask = PWM_MASK_MASKX(0x01UL << (uint8_t)subModule); + } + + if (forcetozero) + { + /* Disables the channel output, forcing output level to 0 */ + base->MASK |= mask; + } + else + { + /* Enables the channel output */ + base->MASK &= ~mask; + } + +#if defined(PWM_MASK_UPDATE_MASK) + /* Update output mask bits immediately with UPDATE_MASK bit */ + base->MASK |= PWM_MASK_UPDATE_MASK(0x01UL << (uint8_t)subModule); +#else + /* Select local force signal */ + base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; + /* Issue a local Force trigger event */ + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; + /* Restore the source of FORCE OUTPUT signal */ + base->SM[subModule].CTRL2 = reg; +#endif +} + +/*! + * brief This function set the output state of the PWM pin as requested for the current cycle. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * param outputstate Set pwm output state, see @ref pwm_output_state_t. + */ +void PWM_SetChannelOutput(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_output_state_t outputstate) +{ + uint16_t mask, swcout, sourceShift; + uint16_t reg = base->SM[subModule].CTRL2; + + if (kPWM_PwmA == pwmChannel) + { + mask = PWM_MASK_MASKA(0x01UL << (uint8_t)subModule); + swcout = (uint16_t)PWM_SWCOUT_SM0OUT23_MASK << ((uint8_t)subModule * 2U); + sourceShift = PWM_DTSRCSEL_SM0SEL23_SHIFT + ((uint16_t)subModule * 4U); + } + else if (kPWM_PwmB == pwmChannel) + { + mask = PWM_MASK_MASKB(0x01UL << (uint8_t)subModule); + swcout = (uint16_t)PWM_SWCOUT_SM0OUT45_MASK << ((uint8_t)subModule * 2U); + sourceShift = PWM_DTSRCSEL_SM0SEL45_SHIFT + ((uint16_t)subModule * 4U); + } + else + { + mask = PWM_MASK_MASKX(0x01UL << (uint8_t)subModule); + swcout = 0U; + sourceShift = 0U; + } + + if (kPWM_MaskState == outputstate) + { + /* Disables the channel output, forcing output level to 0 */ + base->MASK |= mask; + } + else + { + /* Enables the channel output first */ + base->MASK &= ~mask; + /* PwmX only support MASK mode */ + if (kPWM_PwmX != pwmChannel) + { + if (kPWM_HighState == outputstate) + { + base->SWCOUT |= swcout; + base->DTSRCSEL = + (base->DTSRCSEL & ~(uint16_t)(0x3UL << sourceShift)) | (uint16_t)(0x2UL << sourceShift); + } + else if (kPWM_LowState == outputstate) + { + base->SWCOUT &= ~swcout; + base->DTSRCSEL = + (base->DTSRCSEL & ~(uint16_t)(0x3UL << sourceShift)) | (uint16_t)(0x2UL << sourceShift); + } + else if (kPWM_NormalState == outputstate) + { + base->DTSRCSEL &= ~(uint16_t)(0x3UL << sourceShift); + } + else + { + base->DTSRCSEL = + (base->DTSRCSEL & ~(uint16_t)(0x3UL << sourceShift)) | (uint16_t)(0x1UL << sourceShift); + } + } + } + + /* Select local force signal */ + base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; + /* Issue a local Force trigger event */ + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; + /* Restore the source of FORCE OUTPUT signal */ + base->SM[subModule].CTRL2 = reg; +} + +#if defined(FSL_FEATURE_PWM_HAS_PHASE_DELAY) && FSL_FEATURE_PWM_HAS_PHASE_DELAY +/*! + * brief This function set the phase delay from the master sync signal of submodule 0. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * param delayCycles Number of cycles delayed from submodule 0. + * + * return kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; + * kStatus_Success if set phase delay success + */ +status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles) +{ + assert(subModule != kPWM_Module_0); + uint16_t reg = base->SM[subModule].CTRL2; + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + + if(base->SM[kPWM_Module_0].VAL1 < delayCycles) + { + return kStatus_Fail; + } + else + { + base->SM[subModule].PHASEDLY = delayCycles; + } + + /* Select the master sync signal as the source for initialization */ + reg = (reg & ~(uint16_t)PWM_CTRL2_INIT_SEL_MASK)| PWM_CTRL2_INIT_SEL(2); + /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + /* Set LDOK bit to load buffer registers */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + /* Restore the source of phase delay register intialization */ + base->SM[subModule].CTRL2 = reg; + return kStatus_Success; +} +#endif /* FSL_FEATURE_PWM_HAS_PHASE_DELAY */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pwm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pwm.h new file mode 100644 index 0000000000..0de61c1c0b --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_pwm.h @@ -0,0 +1,1372 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_PWM_H_ +#define FSL_PWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pwm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 8, 3)) /*!< Version 2.8.3 */ +/*@}*/ + +/*! Number of bits per submodule for software output control */ +#define PWM_SUBMODULE_SWCONTROL_WIDTH 2 +/*! Because setting the pwm duty cycle doesn't support PWMX, getting the pwm duty cycle also doesn't support PWMX. */ +#define PWM_SUBMODULE_CHANNEL 2 + +/*! @brief List of PWM submodules */ +typedef enum _pwm_submodule +{ + kPWM_Module_0 = 0U, /*!< Submodule 0 */ + kPWM_Module_1, /*!< Submodule 1 */ + kPWM_Module_2, /*!< Submodule 2 */ +#if defined(FSL_FEATURE_PWM_SUBMODULE_COUNT) && (FSL_FEATURE_PWM_SUBMODULE_COUNT > 3U) + kPWM_Module_3 /*!< Submodule 3 */ +#endif /* FSL_FEATURE_PWM_SUBMODULE_COUNT */ +} pwm_submodule_t; + +/*! @brief List of PWM channels in each module */ +typedef enum _pwm_channels +{ + kPWM_PwmB = 0U, + kPWM_PwmA, + kPWM_PwmX +} pwm_channels_t; + +/*! @brief List of PWM value registers */ +typedef enum _pwm_value_register +{ + kPWM_ValueRegister_0 = 0U, /*!< PWM Value0 register */ + kPWM_ValueRegister_1, /*!< PWM Value1 register */ + kPWM_ValueRegister_2, /*!< PWM Value2 register */ + kPWM_ValueRegister_3, /*!< PWM Value3 register */ + kPWM_ValueRegister_4, /*!< PWM Value4 register */ + kPWM_ValueRegister_5 /*!< PWM Value5 register */ +} pwm_value_register_t; + +/*! @brief List of PWM value registers mask */ +enum _pwm_value_register_mask +{ + kPWM_ValueRegisterMask_0 = (1U << 0), /*!< PWM Value0 register mask */ + kPWM_ValueRegisterMask_1 = (1U << 1), /*!< PWM Value1 register mask */ + kPWM_ValueRegisterMask_2 = (1U << 2), /*!< PWM Value2 register mask */ + kPWM_ValueRegisterMask_3 = (1U << 3), /*!< PWM Value3 register mask */ + kPWM_ValueRegisterMask_4 = (1U << 4), /*!< PWM Value4 register mask */ + kPWM_ValueRegisterMask_5 = (1U << 5) /*!< PWM Value5 register mask */ +}; + +/*! @brief PWM clock source selection.*/ +typedef enum _pwm_clock_source +{ + kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ + kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ + kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ +} pwm_clock_source_t; + +/*! @brief PWM prescaler factor selection for clock source*/ +typedef enum _pwm_clock_prescale +{ + kPWM_Prescale_Divide_1 = 0U, /*!< PWM clock frequency = fclk/1 */ + kPWM_Prescale_Divide_2, /*!< PWM clock frequency = fclk/2 */ + kPWM_Prescale_Divide_4, /*!< PWM clock frequency = fclk/4 */ + kPWM_Prescale_Divide_8, /*!< PWM clock frequency = fclk/8 */ + kPWM_Prescale_Divide_16, /*!< PWM clock frequency = fclk/16 */ + kPWM_Prescale_Divide_32, /*!< PWM clock frequency = fclk/32 */ + kPWM_Prescale_Divide_64, /*!< PWM clock frequency = fclk/64 */ + kPWM_Prescale_Divide_128 /*!< PWM clock frequency = fclk/128 */ +} pwm_clock_prescale_t; + +/*! @brief Options that can trigger a PWM FORCE_OUT */ +typedef enum _pwm_force_output_trigger +{ + kPWM_Force_Local = 0U, /*!< The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + kPWM_Force_Master, /*!< The master force signal from submodule 0 is used to force updates */ + kPWM_Force_LocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to + the state of LDOK */ + kPWM_Force_MasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set */ + kPWM_Force_LocalSync, /*!< The local sync signal from this submodule is used to force updates */ + kPWM_Force_MasterSync, /*!< The master sync signal from submodule0 is used to force updates */ + kPWM_Force_External, /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates */ + kPWM_Force_ExternalSync /*!< The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ +} pwm_force_output_trigger_t; + +/*! @brief PWM channel output status */ +typedef enum _pwm_output_state +{ + kPWM_HighState = 0, /*!< The output state of PWM channel is high */ + kPWM_LowState, /*!< The output state of PWM channel is low */ + kPWM_NormalState, /*!< The output state of PWM channel is normal */ + kPWM_InvertState, /*!< The output state of PWM channel is invert */ + kPWM_MaskState /*!< The output state of PWM channel is mask */ +} pwm_output_state_t; + +/*! @brief PWM counter initialization options */ +typedef enum _pwm_init_source +{ + kPWM_Initialize_LocalSync = 0U, /*!< Local sync causes initialization */ + kPWM_Initialize_MasterReload, /*!< Master reload from submodule 0 causes initialization */ + kPWM_Initialize_MasterSync, /*!< Master sync from submodule 0 causes initialization */ + kPWM_Initialize_ExtSync /*!< EXT_SYNC causes initialization */ +} pwm_init_source_t; + +/*! @brief PWM load frequency selection */ +typedef enum _pwm_load_frequency +{ + kPWM_LoadEveryOportunity = 0U, /*!< Every PWM opportunity */ + kPWM_LoadEvery2Oportunity, /*!< Every 2 PWM opportunities */ + kPWM_LoadEvery3Oportunity, /*!< Every 3 PWM opportunities */ + kPWM_LoadEvery4Oportunity, /*!< Every 4 PWM opportunities */ + kPWM_LoadEvery5Oportunity, /*!< Every 5 PWM opportunities */ + kPWM_LoadEvery6Oportunity, /*!< Every 6 PWM opportunities */ + kPWM_LoadEvery7Oportunity, /*!< Every 7 PWM opportunities */ + kPWM_LoadEvery8Oportunity, /*!< Every 8 PWM opportunities */ + kPWM_LoadEvery9Oportunity, /*!< Every 9 PWM opportunities */ + kPWM_LoadEvery10Oportunity, /*!< Every 10 PWM opportunities */ + kPWM_LoadEvery11Oportunity, /*!< Every 11 PWM opportunities */ + kPWM_LoadEvery12Oportunity, /*!< Every 12 PWM opportunities */ + kPWM_LoadEvery13Oportunity, /*!< Every 13 PWM opportunities */ + kPWM_LoadEvery14Oportunity, /*!< Every 14 PWM opportunities */ + kPWM_LoadEvery15Oportunity, /*!< Every 15 PWM opportunities */ + kPWM_LoadEvery16Oportunity /*!< Every 16 PWM opportunities */ +} pwm_load_frequency_t; + +/*! @brief List of PWM fault selections */ +typedef enum _pwm_fault_input +{ + kPWM_Fault_0 = 0U, /*!< Fault 0 input pin */ + kPWM_Fault_1, /*!< Fault 1 input pin */ + kPWM_Fault_2, /*!< Fault 2 input pin */ + kPWM_Fault_3 /*!< Fault 3 input pin */ +} pwm_fault_input_t; + +/*! @brief List of PWM fault disable mapping selections */ +typedef enum _pwm_fault_disable +{ + kPWM_FaultDisable_0 = (1U << 0), /*!< Fault 0 disable mapping */ + kPWM_FaultDisable_1 = (1U << 1), /*!< Fault 1 disable mapping */ + kPWM_FaultDisable_2 = (1U << 2), /*!< Fault 2 disable mapping */ + kPWM_FaultDisable_3 = (1U << 3) /*!< Fault 3 disable mapping */ +} pwm_fault_disable_t; + +/*! @brief List of PWM fault channels */ +typedef enum _pwm_fault_channels +{ + kPWM_faultchannel_0 = 0U, + kPWM_faultchannel_1 +} pwm_fault_channels_t; + +/*! @brief PWM capture edge select */ +typedef enum _pwm_input_capture_edge +{ + kPWM_Disable = 0U, /*!< Disabled */ + kPWM_FallingEdge, /*!< Capture on falling edge only */ + kPWM_RisingEdge, /*!< Capture on rising edge only */ + kPWM_RiseAndFallEdge /*!< Capture on rising or falling edge */ +} pwm_input_capture_edge_t; + +/*! @brief PWM output options when a FORCE_OUT signal is asserted */ +typedef enum _pwm_force_signal +{ + kPWM_UsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ + kPWM_InvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ + kPWM_SoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ + kPWM_UseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ +} pwm_force_signal_t; + +/*! @brief Options available for the PWM A & B pair operation */ +typedef enum _pwm_chnl_pair_operation +{ + kPWM_Independent = 0U, /*!< PWM A & PWM B operate as 2 independent channels */ + kPWM_ComplementaryPwmA, /*!< PWM A & PWM B are complementary channels, PWM A generates the signal */ + kPWM_ComplementaryPwmB /*!< PWM A & PWM B are complementary channels, PWM B generates the signal */ +} pwm_chnl_pair_operation_t; + +/*! @brief Options available on how to load the buffered-registers with new values */ +typedef enum _pwm_register_reload +{ + kPWM_ReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set */ + kPWM_ReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle */ + kPWM_ReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle */ + kPWM_ReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle */ +} pwm_register_reload_t; + +/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ +typedef enum _pwm_fault_recovery_mode +{ + kPWM_NoRecovery = 0U, /*!< PWM output will stay inactive */ + kPWM_RecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle */ + kPWM_RecoverFullCycle, /*!< PWM output re-enabled at the first full cycle */ + kPWM_RecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle */ +} pwm_fault_recovery_mode_t; + +/*! @brief List of PWM interrupt options */ +typedef enum _pwm_interrupt_enable +{ + kPWM_CompareVal0InterruptEnable = (1U << 0), /*!< PWM VAL0 compare interrupt */ + kPWM_CompareVal1InterruptEnable = (1U << 1), /*!< PWM VAL1 compare interrupt */ + kPWM_CompareVal2InterruptEnable = (1U << 2), /*!< PWM VAL2 compare interrupt */ + kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ + kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ + kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ + kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ + kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ + kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ + kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ + kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ + kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ + kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ + kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ + kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ +} pwm_interrupt_enable_t; + +/*! @brief List of PWM status flags */ +typedef enum _pwm_status_flags +{ + kPWM_CompareVal0Flag = (1U << 0), /*!< PWM VAL0 compare flag */ + kPWM_CompareVal1Flag = (1U << 1), /*!< PWM VAL1 compare flag */ + kPWM_CompareVal2Flag = (1U << 2), /*!< PWM VAL2 compare flag */ + kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ + kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ + kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ + kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ + kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ + kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ + kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ + kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ + kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ + kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ + kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ + kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ + kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ +} pwm_status_flags_t; + +/*! @brief List of PWM DMA options */ +typedef enum _pwm_dma_enable +{ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + kPWM_CaptureX0DMAEnable = (1U << 0), /*!< PWM capture X0 DMA */ + kPWM_CaptureX1DMAEnable = (1U << 1), /*!< PWM capture X1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + kPWM_CaptureB0DMAEnable = (1U << 2), /*!< PWM capture B0 DMA */ + kPWM_CaptureB1DMAEnable = (1U << 3), /*!< PWM capture B1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + kPWM_CaptureA0DMAEnable = (1U << 4), /*!< PWM capture A0 DMA */ + kPWM_CaptureA1DMAEnable = (1U << 5) /*!< PWM capture A1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +} pwm_dma_enable_t; + +/*! @brief List of PWM capture DMA enable source select */ +typedef enum _pwm_dma_source_select +{ + kPWM_DMARequestDisable = 0U, /*!< Read DMA requests disabled */ + kPWM_DMAWatermarksEnable, /*!< Exceeding a FIFO watermark sets the DMA read request */ + kPWM_DMALocalSync, /*!< A local sync (VAL1 matches counter) sets the read DMA request */ + kPWM_DMALocalReload /*!< A local reload (STS[RF] being set) sets the read DMA request */ +} pwm_dma_source_select_t; + +/*! @brief PWM FIFO Watermark AND Control */ +typedef enum _pwm_watermark_control +{ + kPWM_FIFOWatermarksOR = 0U, /*!< Selected FIFO watermarks are OR'ed together */ + kPWM_FIFOWatermarksAND /*!< Selected FIFO watermarks are AND'ed together */ +} pwm_watermark_control_t; + +/*! @brief PWM operation mode */ +typedef enum _pwm_mode +{ + kPWM_SignedCenterAligned = 0U, /*!< Signed center-aligned */ + kPWM_CenterAligned, /*!< Unsigned cente-aligned */ + kPWM_SignedEdgeAligned, /*!< Signed edge-aligned */ + kPWM_EdgeAligned /*!< Unsigned edge-aligned */ +} pwm_mode_t; + +/*! @brief PWM output pulse mode, high-true or low-true */ +typedef enum _pwm_level_select +{ + kPWM_HighTrue = 0U, /*!< High level represents "on" or "active" state */ + kPWM_LowTrue /*!< Low level represents "on" or "active" state */ +} pwm_level_select_t; + +/*! @brief PWM output fault status */ +typedef enum _pwm_fault_state +{ + kPWM_PwmFaultState0 = + 0U, /*!< Output is forced to logic 0 state prior to consideration of output polarity control. */ + kPWM_PwmFaultState1, /*!< Output is forced to logic 1 state prior to consideration of output polarity control. */ + kPWM_PwmFaultState2, /*!< Output is tristated. */ + kPWM_PwmFaultState3 /*!< Output is tristated. */ +} pwm_fault_state_t; + +/*! @brief PWM reload source select */ +typedef enum _pwm_reload_source_select +{ + kPWM_LocalReload = 0U, /*!< The local reload signal is used to reload registers */ + kPWM_MasterReload /*!< The master reload signal (from submodule 0) is used to reload */ +} pwm_reload_source_select_t; + +/*! @brief PWM fault clearing options */ +typedef enum _pwm_fault_clear +{ + kPWM_Automatic = 0U, /*!< Automatic fault clearing */ + kPWM_ManualNormal, /*!< Manual fault clearing with no fault safety mode */ + kPWM_ManualSafety /*!< Manual fault clearing with fault safety mode */ +} pwm_fault_clear_t; + +/*! @brief Options for submodule master control operation */ +typedef enum _pwm_module_control +{ + kPWM_Control_Module_0 = (1U << 0), /*!< Control submodule 0's start/stop,buffer reload operation */ + kPWM_Control_Module_1 = (1U << 1), /*!< Control submodule 1's start/stop,buffer reload operation */ + kPWM_Control_Module_2 = (1U << 2), /*!< Control submodule 2's start/stop,buffer reload operation */ + kPWM_Control_Module_3 = (1U << 3) /*!< Control submodule 3's start/stop,buffer reload operation */ +} pwm_module_control_t; + +/*! @brief Structure for the user to define the PWM signal characteristics */ +typedef struct _pwm_signal_param +{ + pwm_channels_t pwmChannel; /*!< PWM channel being configured; PWM A or PWM B */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=always active signal (100% duty cycle)*/ + pwm_level_select_t level; /*!< PWM output active level select */ + uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in complementary mode */ + pwm_fault_state_t faultState; /*!< PWM output fault status */ + bool pwmchannelenable; /*!< Enable PWM output */ +} pwm_signal_param_t; + +/*! + * @brief PWM config structure + * + * This structure holds the configuration settings for the PWM peripheral. To initialize this + * structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pwm_config +{ + bool enableDebugMode; /*!< true: PWM continues to run in debug mode; + false: PWM is paused in debug mode */ +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + bool enableWait; /*!< true: PWM continues to run in WAIT mode; + false: PWM is paused in WAIT mode */ +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + pwm_init_source_t initializationControl; /*!< Option to initialize the counter */ + pwm_clock_source_t clockSource; /*!< Clock source for the counter */ + pwm_clock_prescale_t prescale; /*!< Pre-scaler to divide down the clock */ + pwm_chnl_pair_operation_t pairOperation; /*!< Channel pair in indepedent or complementary mode */ + pwm_register_reload_t reloadLogic; /*!< PWM Reload logic setup */ + pwm_reload_source_select_t reloadSelect; /*!< Reload source select */ + pwm_load_frequency_t reloadFrequency; /*!< Specifies when to reload, used when user's choice + is not immediate reload */ + pwm_force_output_trigger_t forceTrigger; /*!< Specify which signal will trigger a FORCE_OUT */ +} pwm_config_t; + +/*! @brief Structure for the user to configure the fault input filter. */ +typedef struct _pwm_fault_input_filter_param +{ + uint8_t faultFilterCount; /*!< Fault filter count */ + uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ + bool faultGlitchStretch; /*!< Fault Glitch Stretch Enable: A logic 1 means that input + fault signals will be stretched to at least 2 IPBus clock cycles */ +} pwm_fault_input_filter_param_t; + +/*! @brief Structure is used to hold the parameters to configure a PWM fault */ +typedef struct _pwm_fault_param +{ + pwm_fault_clear_t faultClearingMode; /*!< Fault clearing mode to use */ + bool faultLevel; /*!< true: Logic 1 indicates fault; + false: Logic 0 indicates fault */ + bool enableCombinationalPath; /*!< true: Combinational Path from fault input is enabled; + false: No combination path is available */ + pwm_fault_recovery_mode_t recoverMode; /*!< Specify when to re-enable the PWM output */ +} pwm_fault_param_t; + +/*! + * @brief Structure is used to hold parameters to configure the capture capability of a signal pin + */ +typedef struct _pwm_input_capture_param +{ + bool captureInputSel; /*!< true: Use the edge counter signal as source + false: Use the raw input signal from the pin as source */ + uint8_t edgeCompareValue; /*!< Compare value, used only if edge counter is used as source */ + pwm_input_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ + pwm_input_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ + bool enableOneShotCapture; /*!< true: Use one-shot capture mode; + false: Use free-running capture mode */ + uint8_t fifoWatermark; /*!< Watermark level for capture FIFO. The capture flags in + the status register will set if the word count in the FIFO + is greater than this watermark level */ +} pwm_input_capture_param_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PWM driver. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param config Pointer to user's PWM config structure. + * + * @return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config); + +/*! + * @brief Gate the PWM submodule clock + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Fill in the PWM config struct with the default settings + * + * The default values are: + * @code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * @endcode + * @param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config); + +/*! @}*/ + +/*! + * @name Module PWM output + * @{ + */ +/*! + * @brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param chnlParams Array of PWM channel parameters to configure the channel(s), PWMX submodule is not supported. + * @param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. + * + * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle.. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz PWM main counter clock in Hz. + * @param shiftvalue Phase shift value + * @param doSync true: Set LDOK bit for the submodule list; + * false: LDOK bit don't set, need to call PWM_SetPwmLdok to sync update. + * + * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise + */ +status_t PWM_SetupPwmPhaseShift(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint8_t shiftvalue, + bool doSync); + +/*! + * @brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Updates the PWM signal's dutycycle with 16-bit accuracy. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCycle New PWM pulse width, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycleHighAccuracy( + PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle); + +/*! + * @brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * @param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * @param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original duty cycle or update new duty cycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle); + +/*! @}*/ + +/*! + * @brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel in the submodule to setup + * @param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams); + +/*! + * @brief Sets up the PWM fault input filter. + * + * @param base PWM peripheral base address + * @param faultInputFilterParams Parameters passed in to set up the fault input filter. + */ +void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams); + +/*! + * @brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * @param base PWM peripheral base address + * @param faultNum PWM fault to configure. + * @param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams); + +/*! + * @brief Fill in the PWM fault config struct with the default settings + * + * The default values are: + * @code + * config->faultClearingMode = kPWM_Automatic; + * config->faultLevel = false; + * config->enableCombinationalPath = true; + * config->recoverMode = kPWM_NoRecovery; + * @endcode + * @param config Pointer to user's PWM fault config structure. + */ +void PWM_FaultDefaultConfig(pwm_fault_param_t *config); + +/*! + * @brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_force_signal_t mode); + +/*! + * @name Interrupts Interface + * @{ + */ + +/*! + * @brief Enables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Disables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Gets the enabled PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule); + +/*! @}*/ + +/*! + * @name DMA Interface + * @{ + */ + +/*! + * @brief Capture DMA Enable Source Select. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwm_watermark_control PWM FIFO watermark and control + */ +static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, + pwm_submodule_t subModule, + pwm_watermark_control_t pwm_watermark_control) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (pwm_watermark_control == kPWM_FIFOWatermarksOR) + { + reg &= ~((uint16_t)PWM_DMAEN_FAND_MASK); + } + else + { + reg |= ((uint16_t)PWM_DMAEN_FAND_MASK); + } + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Capture DMA Enable Source Select. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwm_dma_source_select PWM capture DMA enable source select + */ +static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, + pwm_submodule_t subModule, + pwm_dma_source_select_t pwm_dma_source_select) +{ + uint16_t reg = base->SM[subModule].DMAEN; + + reg &= ~((uint16_t)PWM_DMAEN_CAPTDE_MASK); + reg |= (((uint16_t)pwm_dma_source_select << (uint16_t)PWM_DMAEN_CAPTDE_SHIFT) & (uint16_t)PWM_DMAEN_CAPTDE_MASK); + + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Enables or disables the selected PWM DMA Capture read request. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The DMA to enable or disable. This is a logical OR of members of the + * enumeration ::pwm_dma_enable_t + * @param activate true: Enable DMA read request; false: Disable DMA read request + */ +static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (activate) + { + reg |= (uint16_t)(mask); + } + else + { + reg &= ~((uint16_t)(mask)); + } + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Enables or disables the PWM DMA write request. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param activate true: Enable DMA write request; false: Disable DMA write request + */ +static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (activate) + { + reg |= ((uint16_t)PWM_DMAEN_VALDE_MASK); + } + else + { + reg &= ~((uint16_t)PWM_DMAEN_VALDE_MASK); + } + base->SM[subModule].DMAEN = reg; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Clears the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the PWM counter for a single or multiple submodules. + * + * Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStart PWM submodules to start. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart) +{ + base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); +} + +/*! + * @brief Stops the PWM counter for a single or multiple submodules. + * + * Clears the Run bit which resets the submodule's counter. This function can stop multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStop PWM submodules to stop. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop) +{ + base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); +} + +/*! @}*/ + +/*! + * @brief Set the PWM VALx registers. + * + * This function allows the user to write value into VAL registers directly. And it will destroying the PWM clock period + * set by the PWM_SetupPwm()/PWM_SetupPwmPhaseShift() functions. + * Due to VALx registers are bufferd, the new value will not active uless call PWM_SetPwmLdok() and the reload point is + * reached. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister VALx register that will be writen new value + * @param value Value that will been write into VALx register + */ +static inline void PWM_SetVALxValue(PWM_Type *base, + pwm_submodule_t subModule, + pwm_value_register_t valueRegister, + uint16_t value) +{ + switch (valueRegister) + { + case kPWM_ValueRegister_0: + base->SM[subModule].VAL0 = value; + break; + case kPWM_ValueRegister_1: + base->SM[subModule].VAL1 = value; + break; + case kPWM_ValueRegister_2: + base->SM[subModule].VAL2 = value; + break; + case kPWM_ValueRegister_3: + base->SM[subModule].VAL3 = value; + break; + case kPWM_ValueRegister_4: + base->SM[subModule].VAL4 = value; + break; + case kPWM_ValueRegister_5: + base->SM[subModule].VAL5 = value; + break; + default: + assert(false); + break; + } +} + +/*! + * @brief Get the PWM VALx registers. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister VALx register that will be read value + * @return The VALx register value + */ +static inline uint16_t PWM_GetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister) +{ + uint16_t temp = 0U; + + switch (valueRegister) + { + case kPWM_ValueRegister_0: + temp = base->SM[subModule].VAL0; + break; + case kPWM_ValueRegister_1: + temp = base->SM[subModule].VAL1; + break; + case kPWM_ValueRegister_2: + temp = base->SM[subModule].VAL2; + break; + case kPWM_ValueRegister_3: + temp = base->SM[subModule].VAL3; + break; + case kPWM_ValueRegister_4: + temp = base->SM[subModule].VAL4; + break; + case kPWM_ValueRegister_5: + temp = base->SM[subModule].VAL5; + break; + default: + assert(false); + break; + } + + return temp; +} + +/*! + * @brief Enables or disables the PWM output trigger. + * + * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 + * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated + * when the counter matches VAL 1, VAL 3, or VAL 5 register. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister Value register that will activate the trigger + * @param activate true: Enable the trigger; false: Disable the trigger + */ +static inline void PWM_OutputTriggerEnable(PWM_Type *base, + pwm_submodule_t subModule, + pwm_value_register_t valueRegister, + bool activate) +{ + if (activate) + { + base->SM[subModule].TCTRL |= ((uint16_t)1U << (uint16_t)valueRegister); + } + else + { + base->SM[subModule].TCTRL &= ~((uint16_t)1U << (uint16_t)valueRegister); + } +} + +/*! + * @brief Enables the PWM output trigger. + * + * This function allows the user to enable one or more (VAL0-5) PWM trigger. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegisterMask Value register mask that will activate one or more (VAL0-5) trigger + * enumeration ::_pwm_value_register_mask + */ +static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) +{ + base->SM[subModule].TCTRL |= (PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); +} + +/*! + * @brief Disables the PWM output trigger. + * + * This function allows the user to disables one or more (VAL0-5) PWM trigger. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegisterMask Value register mask that will Deactivate one or more (VAL0-5) trigger + * enumeration ::_pwm_value_register_mask + */ +static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) +{ + base->SM[subModule].TCTRL &= ~(PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); +} + +/*! + * @brief Sets the software control output for a pin to high or low. + * + * The user specifies which channel to modify by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param value true: Supply a logic 1, false: Supply a logic 0. + */ +static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value) +{ + if (value) + { + base->SWCOUT |= + ((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); + } + else + { + base->SWCOUT &= + ~((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); + } +} + +/*! + * @brief Sets or clears the PWM LDOK bit on a single or multiple submodules + * + * Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The + * values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the + * values are loaded at the next PWM reload point. + * This function can issue the load command to multiple submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToUpdate PWM submodules to update with buffered values. This is a logical OR of + * members of the enumeration ::pwm_module_control_t + * @param value true: Set LDOK bit for the submodule list; false: Clear LDOK bit + */ +static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value) +{ + if (value) + { + base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); + } + else + { + base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); + } +} + +/*! + * @brief Set PWM output fault status + * + * These bits determine the fault state for the PWM_A output in fault conditions + * and STOP mode. It may also define the output state in WAIT and DEBUG modes + * depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. + * This function can update PWM output fault status. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param faultState PWM output fault status + */ +static inline void PWM_SetPwmFaultState(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_fault_state_t faultState) +{ + uint16_t reg = base->SM[subModule].OCTRL; + switch (pwmChannel) + { + case kPWM_PwmA: + reg &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMAFS_MASK); + break; + case kPWM_PwmB: + reg &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMBFS_MASK); + break; + case kPWM_PwmX: + reg &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMXFS_MASK); + break; + default: + assert(false); + break; + } + base->SM[subModule].OCTRL = reg; +} + +/*! + * @brief Set PWM fault disable mapping + * + * Each of the four bits of this read/write field is one-to-one associated + * with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned + * off if there is a logic 1 on an FAULTx input and a 1 in the corresponding + * bit of this field. A reset sets all bits in this field. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param pwm_fault_channels PWM fault channel to configure + * @param value Fault disable mapping mask value + * enumeration ::pwm_fault_disable_t + */ +static inline void PWM_SetupFaultDisableMap(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_fault_channels_t pwm_fault_channels, + uint16_t value) +{ + uint16_t reg = base->SM[subModule].DISMAP[pwm_fault_channels]; + switch (pwmChannel) + { + case kPWM_PwmA: + reg &= ~((uint16_t)PWM_DISMAP_DIS0A_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0A_SHIFT) & (uint16_t)PWM_DISMAP_DIS0A_MASK); + break; + case kPWM_PwmB: + reg &= ~((uint16_t)PWM_DISMAP_DIS0B_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0B_SHIFT) & (uint16_t)PWM_DISMAP_DIS0B_MASK); + break; + case kPWM_PwmX: + reg &= ~((uint16_t)PWM_DISMAP_DIS0X_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0X_SHIFT) & (uint16_t)PWM_DISMAP_DIS0X_MASK); + break; + default: + assert(false); + break; + } + base->SM[subModule].DISMAP[pwm_fault_channels] = reg; +} + +/*! + * @brief Set PWM output enable + * + * This feature allows the user to enable the PWM Output. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + */ +static inline void PWM_OutputEnable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule) +{ + /* Set PWM output */ + switch (pwmChannel) + { + case kPWM_PwmA: + base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmB: + base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmX: + base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } +} + +/*! + * @brief Set PWM output disable + * + *This feature allows the user to disable the PWM output. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + */ +static inline void PWM_OutputDisable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule) +{ + switch (pwmChannel) + { + case kPWM_PwmA: + base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmB: + base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmX: + base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } +} + +/*! + * @brief Get the dutycycle value. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * + * @return Current channel dutycycle value. + */ +uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel); + +/*! + * @brief Set PWM output in idle status (high or low). + * + * @note This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + * @param idleStatus True: PWM output is high in idle status; false: PWM output is low in idle status. + * + * @return kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success + */ +status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus); + +/*! + * @brief Set the pwm submodule prescaler. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param prescaler Set prescaler value + */ +void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler); + +/*! + * @brief This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + * @param forcetozero True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal + * function. + */ +void PWM_SetPwmForceOutputToZero(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + bool forcetozero); + +/*! + * @brief This function set the output state of the PWM pin as requested for the current cycle. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param outputstate Set pwm output state, see @ref pwm_output_state_t. + */ +void PWM_SetChannelOutput(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_output_state_t outputstate); + +#if defined(FSL_FEATURE_PWM_HAS_PHASE_DELAY) && FSL_FEATURE_PWM_HAS_PHASE_DELAY +/*! + * @brief This function set the phase delay from the master sync signal of submodule 0. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param delayCycles Number of cycles delayed from submodule 0. + * + * @return kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; + * kStatus_Success if set phase delay success + */ +status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles); +#endif + +#if defined(FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE) && FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE +/*! + * @brief This function set the number of consecutive samples that must agree prior to the input filter. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param filterSampleCount Number of consecutive samples. + */ +static inline void PWM_SetFilterSampleCount(PWM_Type *base, + pwm_channels_t pwmChannel, + pwm_submodule_t subModule, + uint8_t filterSampleCount) +{ + switch(pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} + +/*! + * @brief This function set the sampling period of the fault pin input filter. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param filterSamplePeriod Sampling period of input filter. + */ +static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, + pwm_channels_t pwmChannel, + pwm_submodule_t subModule, + uint8_t filterSamplePeriod) +{ + switch(pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_PER_MASK); + base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_PER_MASK); + base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_PER_MASK); + base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_PWM_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_qdc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_qdc.c new file mode 100644 index 0000000000..75158b976c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_qdc.c @@ -0,0 +1,645 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_qdc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.qdc" +#endif + +#define QDC_CTRL_W1C_FLAGS (QDC_CTRL_HIRQ_MASK | QDC_CTRL_XIRQ_MASK | QDC_CTRL_DIRQ_MASK | QDC_CTRL_CMPIRQ_MASK) +#if (defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) +#define QDC_CTRL2_W1C_FLAGS (QDC_CTRL2_ROIRQ_MASK | QDC_CTRL2_RUIRQ_MASK) +#else +#define QDC_CTRL2_W1C_FLAGS (QDC_CTRL2_SABIRQ_MASK | QDC_CTRL2_ROIRQ_MASK | QDC_CTRL2_RUIRQ_MASK) +#endif + +#if defined(QDC_RSTS) +#define QDC_RESETS_ARRAY QDC_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for QDC module. + * + * @param base QDC peripheral base address + */ +static uint32_t QDC_GetInstance(QDC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to QDC bases for each instance. */ +static QDC_Type *const s_qdcBases[] = QDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to QDC clocks for each instance. */ +static const clock_ip_name_t s_qdcClocks[] = QDC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(QDC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_qdcResets[] = QDC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t QDC_GetInstance(QDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_qdcBases); instance++) + { + if (s_qdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_qdcBases)); + + return instance; +} + +/*! + * brief Initialization for the QDC module. + * + * This function is to make the initialization for the QDC module. It should be called firstly before any operation to + * the QDC with the operations like: + * - Enable the clock for QDC module. + * - Configure the QDC's working attributes. + * + * param base QDC peripheral base address. + * param config Pointer to configuration structure. See to "qdc_config_t". + */ +void QDC_Init(QDC_Type *base, const qdc_config_t *config) +{ + assert(NULL != config); + + uint16_t tmp16; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_qdcClocks[QDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(QDC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_qdcResets[QDC_GetInstance(base)]); +#endif + + /* QDC_CTRL. */ + tmp16 = base->CTRL & (uint16_t)(~(QDC_CTRL_W1C_FLAGS | QDC_CTRL_HIP_MASK | QDC_CTRL_HNE_MASK | QDC_CTRL_REV_MASK | + QDC_CTRL_PH1_MASK | QDC_CTRL_XIP_MASK | QDC_CTRL_XNE_MASK | QDC_CTRL_WDE_MASK)); + /* For HOME trigger. */ + if (kQDC_HOMETriggerDisabled != config->HOMETriggerMode) + { + tmp16 |= QDC_CTRL_HIP_MASK; + if (kQDC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) + { + tmp16 |= QDC_CTRL_HNE_MASK; + } + } + /* For encoder work mode. */ + if (config->enableReverseDirection) + { + tmp16 |= QDC_CTRL_REV_MASK; + } + if (kQDC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) + { + tmp16 |= QDC_CTRL_PH1_MASK; + } + /* For INDEX trigger. */ + if (kQDC_INDEXTriggerDisabled != config->INDEXTriggerMode) + { + tmp16 |= QDC_CTRL_XIP_MASK; + if (kQDC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) + { + tmp16 |= QDC_CTRL_XNE_MASK; + } + } + /* Watchdog. */ + if (config->enableWatchdog) + { + tmp16 |= QDC_CTRL_WDE_MASK; + base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ + } + base->CTRL = tmp16; + + /* QDC_FILT. */ + base->FILT = QDC_FILT_FILT_CNT(config->filterCount) | QDC_FILT_FILT_PER(config->filterSamplePeriod) +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + | QDC_FILT_FILT_PRSC(config->filterPrescaler) +#endif + ; + + /* QDC_CTRL2. */ + tmp16 = base->CTRL2 & (uint16_t)(~(QDC_CTRL2_W1C_FLAGS | QDC_CTRL2_OUTCTL_MASK | QDC_CTRL2_REVMOD_MASK | + QDC_CTRL2_MOD_MASK | QDC_CTRL2_UPDPOS_MASK | QDC_CTRL2_UPDHLD_MASK)); + if (kQDC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) + { + tmp16 |= QDC_CTRL2_OUTCTL_MASK; + } + if (kQDC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) + { + tmp16 |= QDC_CTRL2_REVMOD_MASK; + } + if (config->enableModuloCountMode) + { + tmp16 |= QDC_CTRL2_MOD_MASK; + /* Set modulus value. */ + base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ + base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ + } + if (config->enableTRIGGERClearPositionCounter) + { + tmp16 |= QDC_CTRL2_UPDPOS_MASK; + } + if (config->enableTRIGGERClearHoldPositionCounter) + { + tmp16 |= QDC_CTRL2_UPDHLD_MASK; + } + base->CTRL2 = tmp16; + +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + /* QDC_CTRL3. */ + tmp16 = base->CTRL3 & (uint16_t)(~(QDC_CTRL3_PMEN_MASK | QDC_CTRL3_PRSC_MASK)); + if (config->enablePeriodMeasurementFunction) + { + tmp16 |= QDC_CTRL3_PMEN_MASK; + /* Set prescaler value. */ + tmp16 |= ((uint16_t)config->prescalerValue << QDC_CTRL3_PRSC_SHIFT); + } + base->CTRL3 = tmp16; +#endif + + /* QDC_UCOMP & QDC_LCOMP. */ + base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ + base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ + + /* QDC_UINIT & QDC_LINIT. */ + base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ + base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ +} + +/*! + * brief De-initialization for the QDC module. + * + * This function is to make the de-initialization for the QDC module. It could be called when QDC is no longer used with + * the operations like: + * - Disable the clock for QDC module. + * + * param base QDC peripheral base address. + */ +void QDC_Deinit(QDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_qdcClocks[QDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Get an available pre-defined settings for QDC's configuration. + * + * This function initializes the QDC configuration structure with an available settings, the default value are: + * code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * config->prescalerValue = kQDC_ClockDiv1; + * config->enablePeriodMeasurementFunction = true; + * endcode + * param config Pointer to a variable of configuration structure. See to "qdc_config_t". + */ +void QDC_GetDefaultConfig(qdc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableReverseDirection = false; + config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + config->enableTRIGGERClearPositionCounter = false; + config->enableTRIGGERClearHoldPositionCounter = false; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->filterCount = 0U; + config->filterSamplePeriod = 0U; + config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + config->positionCompareValue = 0xFFFFFFFFU; + config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + config->enableModuloCountMode = false; + config->positionModulusValue = 0U; + config->positionInitialValue = 0U; +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + config->prescalerValue = kQDC_ClockDiv1; + config->enablePeriodMeasurementFunction = true; +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + config->filterPrescaler = kQDC_FilterPrescalerDiv1; +#endif +} + +/*! + * brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * param base QDC peripheral base address. + */ +void QDC_DoSoftwareLoadInitialPositionValue(QDC_Type *base) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~QDC_CTRL_W1C_FLAGS); + + tmp16 |= QDC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ + base->CTRL = tmp16; +} + +/*! + * brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * param base QDC peripheral base address. + * param config Pointer to configuration structure. See to "qdc_self_test_config_t". Pass "NULL" to disable. + */ +void QDC_SetSelfTestConfig(QDC_Type *base, const qdc_self_test_config_t *config) +{ + uint16_t tmp16 = 0U; + + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + tmp16 = 0U; + } + else + { + tmp16 = QDC_TST_TEN_MASK | QDC_TST_TCE_MASK | QDC_TST_TEST_PERIOD(config->signalPeriod) | + QDC_TST_TEST_COUNT(config->signalCount); + if (kQDC_SelfTestDirectionNegative == config->signalDirection) + { + tmp16 |= QDC_TST_QDN_MASK; + } + } + + base->TST = tmp16; +} + +/*! + * brief Enable watchdog for QDC module. + * + * param base QDC peripheral base address + * param enable Enables or disables the watchdog + */ +void QDC_EnableWatchdog(QDC_Type *base, bool enable) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~(QDC_CTRL_W1C_FLAGS | QDC_CTRL_WDE_MASK)); + + if (enable) + { + tmp16 |= QDC_CTRL_WDE_MASK; + } + base->CTRL = tmp16; +} + +/*! + * brief Get the status flags. + * + * param base QDC peripheral base address. + * + * return Mask value of status flags. For available mask, see to "_qdc_status_flags". + */ +uint32_t QDC_GetStatusFlags(QDC_Type *base) +{ + uint32_t ret32 = 0U; + + /* QDC_CTRL. */ + if (0U != (QDC_CTRL_HIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_HOMETransitionFlag; + } + if (0U != (QDC_CTRL_XIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_INDEXPulseFlag; + } + if (0U != (QDC_CTRL_DIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_WatchdogTimeoutFlag; + } + if (0U != (QDC_CTRL_CMPIRQ_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_PositionCompareFlag; + } + + /* QDC_CTRL2. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != (QDC_CTRL2_SABIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_SimultBothPhaseChangeFlag; + } +#endif + if (0U != (QDC_CTRL2_ROIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollOverFlag; + } + if (0U != (QDC_CTRL2_RUIRQ_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollUnderFlag; + } + if (0U != (QDC_CTRL2_DIR_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_LastCountDirectionFlag; + } + + return ret32; +} + +/*! + * brief Clear the status flags. + * + * param base QDC peripheral base address. + * param mask Mask value of status flags to be cleared. For available mask, see to "_qdc_status_flags". + */ +void QDC_ClearStatusFlags(QDC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionFlag & mask)) + { + tmp16 |= QDC_CTRL_HIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseFlag & mask)) + { + tmp16 |= QDC_CTRL_XIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutFlag & mask)) + { + tmp16 |= QDC_CTRL_DIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareFlag & mask)) + { + tmp16 |= QDC_CTRL_CMPIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~QDC_CTRL_W1C_FLAGS)) | tmp16); + } + + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeFlag & mask)) + { + tmp16 |= QDC_CTRL2_SABIRQ_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverFlag & mask)) + { + tmp16 |= QDC_CTRL2_ROIRQ_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderFlag & mask)) + { + tmp16 |= QDC_CTRL2_RUIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Enable the interrupts. + * + * param base QDC peripheral base address. + * param mask Mask value of interrupts to be enabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_EnableInterrupts(QDC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= QDC_CTRL_CMPIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~QDC_CTRL_W1C_FLAGS)) | tmp16); + } + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_SABIE_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~QDC_CTRL2_W1C_FLAGS)) | tmp16); + } +} + +/*! + * brief Disable the interrupts. + * + * param base QDC peripheral base address. + * param mask Mask value of interrupts to be disabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_DisableInterrupts(QDC_Type *base, uint32_t mask) +{ + uint16_t tmp16 = 0U; + + /* QDC_CTRL. */ + if (0U != ((uint32_t)kQDC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_HIE_MASK; + } + if (0U != ((uint32_t)kQDC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_XIE_MASK; + } + if (0U != ((uint32_t)kQDC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL_DIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= QDC_CTRL_CMPIE_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~QDC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); + } + /* QDC_CTRL2. */ + tmp16 = 0U; +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != ((uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_SABIE_MASK; + } +#endif + if (0U != ((uint32_t)kQDC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_ROIE_MASK; + } + if (0U != ((uint32_t)kQDC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= QDC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~QDC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); + } +} + +/*! + * brief Get the enabled interrupts' flags. + * + * param base QDC peripheral base address. + * + * return Mask value of enabled interrupts. + */ +uint32_t QDC_GetEnabledInterrupts(QDC_Type *base) +{ + uint32_t ret32 = 0U; + + /* QDC_CTRL. */ + if (0U != (QDC_CTRL_HIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_HOMETransitionInterruptEnable; + } + if (0U != (QDC_CTRL_XIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_INDEXPulseInterruptEnable; + } + if (0U != (QDC_CTRL_DIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_WatchdogTimeoutInterruptEnable; + } + if (0U != (QDC_CTRL_CMPIE_MASK & base->CTRL)) + { + ret32 |= (uint32_t)kQDC_PositionCompareInerruptEnable; + } + /* QDC_CTRL2. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + if (0U != (QDC_CTRL2_SABIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_SimultBothPhaseChangeInterruptEnable; + } +#endif + if (0U != (QDC_CTRL2_ROIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollOverInterruptEnable; + } + if (0U != (QDC_CTRL2_RUIE_MASK & base->CTRL2)) + { + ret32 |= (uint32_t)kQDC_PositionRollUnderInterruptEnable; + } + return ret32; +} + +/*! + * brief Set initial position value for QDC module. + * + * param base QDC peripheral base address + * param value Positive initial value + */ +void QDC_SetInitialPositionValue(QDC_Type *base, uint32_t value) +{ + base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ + base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ +} + +/*! + * brief Get the current position counter's value. + * + * param base QDC peripheral base address. + * + * return Current position counter's value. + */ +uint32_t QDC_GetPositionValue(QDC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} + +/*! + * brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * param base QDC peripheral base address. + * + * return Hold position counter's value. + */ +uint32_t QDC_GetHoldPositionValue(QDC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_qdc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_qdc.h new file mode 100644 index 0000000000..5a79f3de11 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_qdc.h @@ -0,0 +1,585 @@ +/* + * Copyright 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_QDC_H_ +#define FSL_QDC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup qdc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define FSL_QDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) + +/*! + * @brief Interrupt enable/disable mask. + */ +enum _qdc_interrupt_enable +{ + kQDC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ + kQDC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ + kQDC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ + kQDC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + kQDC_SimultBothPhaseChangeInterruptEnable = + (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ +#endif + kQDC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ + kQDC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ +}; + +/*! + * @brief Status flag mask. + * + * These flags indicate the counter's events. + */ +enum _qdc_status_flags +{ + kQDC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ + kQDC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ + kQDC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ + kQDC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ +#if !(defined(FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT) + kQDC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ +#endif + kQDC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ + kQDC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ + kQDC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ +}; + +/*! + * @brief Signal status flag mask. + * + * These flags indicate the counter's signal. + */ +enum _qdc_signal_status_flags +{ + kQDC_RawHOMEStatusFlag = QDC_IMR_HOME_MASK, /*!< Raw HOME input. */ + kQDC_RawINDEXStatusFlag = QDC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ + kQDC_RawPHBStatusFlag = QDC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kQDC_RawPHAEXStatusFlag = QDC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kQDC_FilteredHOMEStatusFlag = QDC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ + kQDC_FilteredINDEXStatusFlag = QDC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ + kQDC_FilteredPHBStatusFlag = QDC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ + kQDC_FilteredPHAStatusFlag = QDC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ +}; + +/*! + * @brief Define HOME signal's trigger mode. + * + * The QDC would count the trigger from HOME signal line. + */ +typedef enum _qdc_home_trigger_mode +{ + kQDC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ + kQDC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kQDC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} qdc_home_trigger_mode_t; + +/*! + * @brief Define INDEX signal's trigger mode. + * + * The QDC would count the trigger from INDEX signal line. + */ +typedef enum _qdc_index_trigger_mode +{ + kQDC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ + kQDC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kQDC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} qdc_index_trigger_mode_t; + +/*! + * @brief Define type for decoder work mode. + * + * The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, + * a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction + * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 + * means counting down. Otherwise, the direction is reversed. + */ +typedef enum _qdc_decoder_work_mode +{ + kQDC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ + kQDC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the + direction. */ +} qdc_decoder_work_mode_t; + +/*! + * @brief Define type for the condition of POSMATCH pulses. + */ +typedef enum _qdc_position_match_mode +{ + kQDC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the + position counters (POS) and the compare value (COMP). */ + kQDC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ +} qdc_position_match_mode_t; + +/*! + * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. + */ +typedef enum _qdc_revolution_count_condition +{ + kQDC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ + kQDC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution + counter. */ +} qdc_revolution_count_condition_t; + +/*! + * @brief Define type for direction of self test generated signal. + */ +typedef enum _qdc_self_test_direction +{ + kQDC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ + kQDC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ +} qdc_self_test_direction_t; + +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) +/*! + * @brief Define prescaler value for clock in CTRL3. + * + * The clock is prescaled by a value of 2^PRSC which means that the prescaler logic + * can divide the clock by a minimum of 1 and a maximum of 32,768. + */ +typedef enum _qdc_prescaler +{ + kQDC_ClockDiv1 = 0, + kQDC_ClockDiv2 = 1, + kQDC_ClockDiv4 = 2, + kQDC_ClockDiv8 = 3, + kQDC_ClockDiv16 = 4, + kQDC_ClockDiv32 = 5, + kQDC_ClockDiv64 = 6, + kQDC_ClockDiv128 = 7, + kQDC_ClockDiv256 = 8, + kQDC_ClockDiv512 = 9, + kQDC_ClockDiv1024 = 10, + kQDC_ClockDiv2048 = 11, + kQDC_ClockDiv4096 = 12, + kQDC_ClockDiv8192 = 13, + kQDC_ClockDiv16384 = 14, + kQDC_ClockDiv32768 = 15, +} qdc_prescaler_t; +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) +/*! + * @brief Define input filter prescaler value. + * + * The input filter prescaler value is to prescale the IPBus clock. + * (Frequency of FILT clock) = (Frequency of IPBus clock) / 2^FILT_PRSC. + */ +typedef enum _qdc_filter_prescaler +{ + kQDC_FilterPrescalerDiv1 = 0U, /*!< Input filter prescaler is 1. */ + kQDC_FilterPrescalerDiv2 = 1U, /*!< Input filter prescaler is 2. */ + kQDC_FilterPrescalerDiv4 = 2U, /*!< Input filter prescaler is 4. */ + kQDC_FilterPrescalerDiv8 = 3U, /*!< Input filter prescaler is 8. */ + kQDC_FilterPrescalerDiv16 = 4U, /*!< Input filter prescaler is 16. */ + kQDC_FilterPrescalerDiv32 = 5U, /*!< Input filter prescaler is 32. */ + kQDC_FilterPrescalerDiv64 = 6U, /*!< Input filter prescaler is 64. */ + kQDC_FilterPrescalerDiv128 = 7U, /*!< Input filter prescaler is 128. */ +} qdc_filter_prescaler_t; +#endif + +/*! + * @brief Define user configuration structure for QDC module. + */ +typedef struct _qdc_config +{ + /* Basic counter. */ + bool enableReverseDirection; /*!< Enable reverse direction counting. */ + qdc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ + + /* Signal detection. */ + qdc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ + qdc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ + bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ + bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. + */ + + /* Watchdog. */ + bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ + uint16_t watchdogTimeoutValue; /*!< Watchdog timeout count value. It stores the timeout count for the quadrature + decoder module watchdog timer. This field is only available when + "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ + +#if (defined(FSL_FEATURE_QDC_HAS_FILT_PRSC) && FSL_FEATURE_QDC_HAS_FILT_PRSC) + qdc_filter_prescaler_t filterPrescaler; /*!< Input filter prescaler. */ +#endif + + /* Filter for PHASEA, PHASEB, INDEX and HOME. */ + uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of + noisy samples causing an incorrect transition to be recognized. The value represent the + number of consecutive samples that must agree prior to the input filter accepting an + input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 + samples. The Available range is 0 - 7.*/ + uint16_t filterSamplePeriod; /*!< Input Filter Sample Period. This value should be set such that the sampling period + is larger than the period of the expected noise. This value represents the + sampling period (in IPBus clock cycles) of the decoder input signals. + The available range is 0 - 255. */ + + /* Position compare. */ + qdc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ + uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ + + /* Modulus counting. */ + qdc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ + bool enableModuloCountMode; /*!< Enable Modulo Counting. */ + uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when + "enableModuloCountMode" = true. The available value is a 32-bit number. */ + uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ + +#if (defined(FSL_FEATURE_QDC_HAS_CTRL3) && FSL_FEATURE_QDC_HAS_CTRL3) + /* Prescaler. */ + bool enablePeriodMeasurementFunction; /*!< Enable period measurement function. */ + qdc_prescaler_t prescalerValue; /*!< The value of prescaler. */ +#endif +} qdc_config_t; + +/*! + * @brief Define configuration structure for self test module. + * + * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. + * This is a factory test feature. It is also useful to customers' software development and testing. + */ +typedef struct _qdc_self_test_config +{ + qdc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ + uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ + uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. + The available range is 0 - 31. */ +} qdc_self_test_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initialization for the QDC module. + * + * This function is to make the initialization for the QDC module. It should be called firstly before any operation to + * the QDC with the operations like: + * - Enable the clock for QDC module. + * - Configure the QDC's working attributes. + * + * @param base QDC peripheral base address. + * @param config Pointer to configuration structure. See to "qdc_config_t". + */ +void QDC_Init(QDC_Type *base, const qdc_config_t *config); + +/*! + * @brief De-initialization for the QDC module. + * + * This function is to make the de-initialization for the QDC module. It could be called when QDC is no longer used with + * the operations like: + * - Disable the clock for QDC module. + * + * @param base QDC peripheral base address. + */ +void QDC_Deinit(QDC_Type *base); + +/*! + * @brief Get an available pre-defined settings for QDC's configuration. + * + * This function initializes the QDC configuration structure with an available settings, the default value are: + * @code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kQDC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kQDC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kQDC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kQDC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kQDC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * config->prescalerValue = kQDC_ClockDiv1; + * config->enablePeriodMeasurementFunction = true; + * @endcode + * @param config Pointer to a variable of configuration structure. See to "qdc_config_t". + */ +void QDC_GetDefaultConfig(qdc_config_t *config); + +/*! + * @brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * @param base QDC peripheral base address. + */ +void QDC_DoSoftwareLoadInitialPositionValue(QDC_Type *base); + +/*! + * @brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * @param base QDC peripheral base address. + * @param config Pointer to configuration structure. See to "qdc_self_test_config_t". Pass "NULL" to disable. + */ +void QDC_SetSelfTestConfig(QDC_Type *base, const qdc_self_test_config_t *config); + +/*! + * @brief Enable watchdog for QDC module. + * + * @param base QDC peripheral base address + * @param enable Enables or disables the watchdog + */ +void QDC_EnableWatchdog(QDC_Type *base, bool enable); + +/*! + * @brief Set initial position value for QDC module. + * + * @param base QDC peripheral base address + * @param value Positive initial value + */ +void QDC_SetInitialPositionValue(QDC_Type *base, uint32_t value); + +/*! @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the status flags. + * + * @param base QDC peripheral base address. + * + * @return Mask value of status flags. For available mask, see to "_qdc_status_flags". + */ +uint32_t QDC_GetStatusFlags(QDC_Type *base); + +/*! + * @brief Clear the status flags. + * + * @param base QDC peripheral base address. + * @param mask Mask value of status flags to be cleared. For available mask, see to "_qdc_status_flags". + */ +void QDC_ClearStatusFlags(QDC_Type *base, uint32_t mask); + +/*! + * @brief Get the signals' real-time status. + * + * @param base QDC peripheral base address. + * + * @return Mask value of signals' real-time status. For available mask, see to "_qdc_signal_status_flags" + */ +static inline uint16_t QDC_GetSignalStatusFlags(QDC_Type *base) +{ + return base->IMR; +} +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base QDC peripheral base address. + * @param mask Mask value of interrupts to be enabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_EnableInterrupts(QDC_Type *base, uint32_t mask); + +/*! + * @brief Disable the interrupts. + * + * @param base QDC peripheral base address. + * @param mask Mask value of interrupts to be disabled. For available mask, see to "_qdc_interrupt_enable". + */ +void QDC_DisableInterrupts(QDC_Type *base, uint32_t mask); + +/*! + * @brief Get the enabled interrupts' flags. + * + * @param base QDC peripheral base address. + * + * @return Mask value of enabled interrupts. + */ +uint32_t QDC_GetEnabledInterrupts(QDC_Type *base); + +/*! @} */ + +/*! + * @name Value Operation + * @{ + */ + +/*! + * @brief Get the current position counter's value. + * + * @param base QDC peripheral base address. + * + * @return Current position counter's value. + */ +uint32_t QDC_GetPositionValue(QDC_Type *base); + +/*! + * @brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base QDC peripheral base address. + * + * @return Hold position counter's value. + */ +uint32_t QDC_GetHoldPositionValue(QDC_Type *base); + +/*! + * @brief Get the position difference counter's value. + * + * @param base QDC peripheral base address. + * + * @return The position difference counter's value. + */ +static inline uint16_t QDC_GetPositionDifferenceValue(QDC_Type *base) +{ + return base->POSD; +} + +/*! + * @brief Get the hold position difference counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base QDC peripheral base address. + * + * @return Hold position difference counter's value. + */ +static inline uint16_t QDC_GetHoldPositionDifferenceValue(QDC_Type *base) +{ + return base->POSDH; +} + +/*! + * @brief Get the position revolution counter's value. + * + * @param base QDC peripheral base address. + * + * @return The position revolution counter's value. + */ +static inline uint16_t QDC_GetRevolutionValue(QDC_Type *base) +{ + return base->REV; +} + +/*! + * @brief Get the hold position revolution counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base QDC peripheral base address. + * + * @return Hold position revolution counter's value. + */ +static inline uint16_t QDC_GetHoldRevolutionValue(QDC_Type *base) +{ + return base->REVH; +} + +#if (defined(FSL_FEATURE_QDC_HAS_LASTEDGE) && FSL_FEATURE_QDC_HAS_LASTEDGE) +/*! + * @brief Get the last edge time value. + * + * @param base QDC peripheral base address. + * + * @return The last edge time hold value. + */ +static inline uint16_t QDC_GetLastEdgeTimeValue(QDC_Type *base) +{ + return base->LASTEDGE; +} + +/*! + * @brief Get the last edge time hold value. + * + * @param base QDC peripheral base address. + * + * @return The last edge time hold value. + */ +static inline uint16_t QDC_GetHoldLastEdgeTimeValue(QDC_Type *base) +{ + return base->LASTEDGEH; +} +#endif + +#if (defined(FSL_FEATURE_QDC_HAS_POSDPER) && FSL_FEATURE_QDC_HAS_POSDPER) +/*! + * @brief Get the position difference period value. + * + * @param base QDC peripheral base address. + * + * @return The position difference period hold value. + */ +static inline uint16_t QDC_GetPositionDifferencePeriodValue(QDC_Type *base) +{ + return base->POSDPER; +} + +/*! + * @brief Get the position difference period buffer value. + * + * @param base QDC peripheral base address. + * + * @return The position difference period hold value. + */ +static inline uint16_t QDC_GetPositionDifferencePeriodBufferValue(QDC_Type *base) +{ + return base->POSDPERBFR; +} + +/*! + * @brief Get the position difference period hold value. + * + * @param base QDC peripheral base address. + * + * @return The position difference period hold value. + */ +static inline uint16_t QDC_GetHoldPositionDifferencePeriodValue(QDC_Type *base) +{ + return base->POSDPERH; +} +#endif +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_QDC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_reset.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_reset.c new file mode 100644 index 0000000000..58c0599505 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_reset.c @@ -0,0 +1,102 @@ +/* + * Copyright 2022, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + pResetCtrl = &(SYSCON->PRESETCTRL0); + while (0u == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask)) + { + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl; + + assert(bitPos < 32u); + + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + pResetCtrl = &(SYSCON->PRESETCTRL0); + while (bitMask == ((uint32_t)((volatile uint32_t *)pResetCtrl)[regIndex] & bitMask)) + { + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_reset.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_reset.h new file mode 100644 index 0000000000..59922b4fd1 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_reset.h @@ -0,0 +1,224 @@ +/* + * Copyright 2022, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kFMU_RST_SHIFT_RSTn = 0 | 9U, /**< Flash management unit reset control */ + kMUX_RST_SHIFT_RSTn = 0 | 12U, /**< Input mux reset control */ + kPORT0_RST_SHIFT_RSTn = 0 | 13U, /**< PORT0 reset control */ + kPORT1_RST_SHIFT_RSTn = 0 | 14U, /**< PORT1 reset control */ + kPORT2_RST_SHIFT_RSTn = 0 | 15U, /**< PORT2 reset control */ + kPORT3_RST_SHIFT_RSTn = 0 | 16U, /**< PORT3 reset control */ + kPORT4_RST_SHIFT_RSTn = 0 | 17U, /**< PORT4 reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 19U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 20U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 21U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 22U, /**< GPIO3 reset control */ + kGPIO4_RST_SHIFT_RSTn = 0 | 23U, /**< GPIO4 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 25U, /**< Pin interrupt (PINT) reset control */ + kDMA0_RST_SHIFT_RSTn = 0 | 26U, /**< DMA0 reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 27U, /**< CRC reset control */ + + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer reset control */ + kADC0_RST_SHIFT_RSTn = 65536 | 3U, /**< ADC0 reset control */ + kADC1_RST_SHIFT_RSTn = 65536 | 4U, /**< ADC1 reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kMICFIL_RST_SHIFT_RSTn = 65536 | 21U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0_FS_DCD_RST_SHIFT_RSTn = 65536 | 24U, /**< USB0-FS DCD reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kSMART_DMA_RST_SHIFT_RSTn = 65536 | 31U, /**< SmartDMA reset control */ + + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kUSDHC_RST_SHIFT_RSTn = 131072 | 3U, /**< uSDHC reset control */ + kFLEXIO_RST_SHIFT_RSTn = 131072 | 4U, /**< FLEXIO reset control */ + kSAI0_RST_SHIFT_RSTn = 131072 | 5U, /**< SAI0 reset control */ + kSAI1_RST_SHIFT_RSTn = 131072 | 6U, /**< SAI1 reset control */ + kTRO_RST_SHIFT_RSTn = 131072 | 7U, /**< TRO reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kTRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< TRNG reset control */ + kFLEXCAN0_RST_SHIFT_RSTn = 131072 | 14U, /**< Flexcan0 reset control */ + kFLEXCAN1_RST_SHIFT_RSTn = 131072 | 15U, /**< Flexcan1 reset control */ + kUSB_HS_RST_SHIFT_RSTn = 131072 | 16U, /**< USB HS reset control */ + kUSB_HS_PHY_RST_SHIFT_RSTn = 131072 | 17U, /**< USB HS PHY reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kPKC_RST_SHIFT_RSTn = 131072 | 24U, /**< PKC reset control */ + kSM3_RST_SHIFT_RSTn = 131072 | 30U, /**< SM3 reset control */ + + kI3C0_RST_SHIFT_RSTn = 196608 | 0U, /**< I3C0 reset control */ + kI3C1_RST_SHIFT_RSTn = 196608 | 1U, /**< I3C1 reset control */ + kQDC0_RST_SHIFT_RSTn = 196608 | 4U, /**< QDC0 reset control */ + kQDC1_RST_SHIFT_RSTn = 196608 | 5U, /**< QDC1 reset control */ + kPWM0_RST_SHIFT_RSTn = 196608 | 6U, /**< PWM0 reset control */ + kPWM1_RST_SHIFT_RSTn = 196608 | 7U, /**< PWM1 reset control */ + kAOI0_RST_SHIFT_RSTn = 196608 | 8U, /**< AOI0 reset control */ + kVREF_RST_SHIFT_RSTn = 196608 | 19U, /**< VREF reset control */ + kEWM_RST_SHIFT_RSTn = 196608 | 23U, /**< EWM reset control */ + kEIM_RST_SHIFT_RSTn = 196608 | 24U, /**< EIM reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ + +#define LP_FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define FLASH_RSTS \ + { \ + kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define TRNG_RSTS \ + { \ + kTRNG_RST_SHIFT_RSTn \ + } /* Reset bits for TRNG peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define I3C_RSTS \ + { \ + kI3C0_RST_SHIFT_RSTn, kI3C1_RST_SHIFT_RSTn \ + } /* Reset bits for I3C peripheral */ +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai.c new file mode 100644 index 0000000000..6d69f5efb2 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai.c @@ -0,0 +1,3140 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sai.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/*! @brief _sai_transfer_state sai transfer state.*/ +enum +{ + kSAI_Busy = 0x0U, /*!< SAI is busy */ + kSAI_Idle, /*!< Transfer is done. */ + kSAI_Error /*!< Transfer error occurred. */ +}; + +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief check flag avalibility */ +#define IS_SAI_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL) + +#if defined(SAI_RSTS) +#define SAI_RESETS_ARRAY SAI_RSTS +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief sai get rx enabled interrupt status. + * + * + * @param base SAI base pointer. + * @param enableFlag enable flag to check. + * @param statusFlag status flag to check. + */ +static bool SAI_RxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag); + +/*! + * @brief sai get tx enabled interrupt status. + * + * + * @param base SAI base pointer. + * @param enableFlag enable flag to check. + * @param statusFlag status flag to check. + */ +static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag); + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag); + +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +/*! + * @brief Get the instance number for SAI. + * + * @param base SAI base pointer. + */ +static uint32_t SAI_GetInstance(I2S_Type *base); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size); + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations + * @param bitWidth audio data bitWidth. + * @param mode audio data channel + * @param saiChannelMask channel mask value to enable + */ +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +#if defined(SAI_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_saiReset[] = SAI_RESETS_ARRAY; +#endif +/*!@brief SAI handle pointer */ +static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; +/* IRQ number array */ +static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; +static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SAI_RxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag) +{ + uint32_t rcsr = base->RCSR; + + return IS_SAI_FLAG_SET(rcsr, enableFlag) && IS_SAI_FLAG_SET(rcsr, statusFlag); +} + +static bool SAI_TxGetEnabledInterruptStatus(I2S_Type *base, uint32_t enableFlag, uint32_t statusFlag) +{ + uint32_t tcsr = base->TCSR; + + return IS_SAI_FLAG_SET(tcsr, enableFlag) && IS_SAI_FLAG_SET(tcsr, statusFlag); +} + +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) +{ + assert(mclk_Hz <= mclkSrcClock_Hz); + + uint32_t sourceFreq = mclkSrcClock_Hz / 100U; /*In order to prevent overflow */ + uint32_t targetFreq = mclk_Hz / 100U; /*In order to prevent overflow */ + +#if FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV + uint32_t postDivider = sourceFreq / targetFreq; + + /* if source equal to target, then disable divider */ + if (postDivider == 1U) + { + base->MCR &= ~I2S_MCR_DIVEN_MASK; + } + else + { + base->MCR = (base->MCR & (~I2S_MCR_DIV_MASK)) | I2S_MCR_DIV(postDivider / 2U - 1U) | I2S_MCR_DIVEN_MASK; + } +#endif +#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER + uint16_t fract, divide; + uint32_t remaind = 0; + uint32_t current_remainder = 0xFFFFFFFFU; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; + + /* Compute the max fract number */ + max_fract = targetFreq * 4096U / sourceFreq + 1U; + if (max_fract > 256U) + { + max_fract = 256U; + } + + /* Looking for the closet frequency */ + for (fract = 1; fract < max_fract; fract++) + { + mul_freq = sourceFreq * fract; + remaind = mul_freq % targetFreq; + divide = (uint16_t)(mul_freq / targetFreq); + + /* Find the exactly frequency */ + if (remaind == 0U) + { + current_fract = fract; + current_divide = (uint16_t)(mul_freq / targetFreq); + break; + } + + /* Closer to next one, set the closest to next data */ + if (remaind > mclk_Hz / 2U) + { + remaind = targetFreq - remaind; + divide += 1U; + } + + /* Update the closest div and fract */ + if (remaind < current_remainder) + { + current_fract = fract; + current_divide = divide; + current_remainder = remaind; + } + } + + /* Fill the computed fract and divider to registers */ + base->MDR = I2S_MDR_DIVIDE(current_divide - 1UL) | I2S_MDR_FRACT(current_fract - 1UL); + + /* Waiting for the divider updated */ + while ((base->MCR & I2S_MCR_DUF_MASK) != 0UL) + { + } +#endif +} +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +static uint32_t SAI_GetInstance(I2S_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++) + { + if (s_saiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_saiBases)); + + return instance; +} + +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size) +{ + uint32_t i = 0, j = 0U; + uint8_t m = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = channel; j <= endChannel; j++) + { + if (IS_SAI_FLAG_SET((1UL << j), channelMask)) + { + for (m = 0; m < bytesPerWord; m++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * m)); + buffer++; + } + base->TDR[j] = data; + data = 0; + } + } + } +} + +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint8_t bitWidth, + uint8_t *buffer, + uint32_t size) +{ + uint32_t i = 0, j = 0; + uint8_t m = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = channel; j <= endChannel; j++) + { + if (IS_SAI_FLAG_SET((1UL << j), channelMask)) + { + data = base->RDR[j]; + for (m = 0; m < bytesPerWord; m++) + { + *buffer = (uint8_t)(data >> (8U * m)) & 0xFFU; + buffer++; + } + } + } + } +} + +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + (void)memset(config, 0, sizeof(sai_transceiver_t)); + + config->channelMask = (uint8_t)saiChannelMask; + /* sync mode default configurations */ + config->syncMode = kSAI_ModeAsync; + + /* master mode default */ + config->masterSlave = kSAI_Master; + + /* bit default configurations */ + config->bitClock.bclkSrcSwap = false; + config->bitClock.bclkInputDelay = false; + config->bitClock.bclkPolarity = kSAI_SampleOnRisingEdge; + config->bitClock.bclkSource = kSAI_BclkSourceMclkDiv; + + /* frame sync default configurations */ + config->frameSync.frameSyncWidth = (uint8_t)bitWidth; + config->frameSync.frameSyncEarly = true; +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE + config->frameSync.frameSyncGenerateOnDemand = false; +#endif + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow; + + /* serial data default configurations */ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + config->serialData.dataMode = kSAI_DataPinStateOutputZero; +#endif + config->serialData.dataOrder = kSAI_DataMSB; + config->serialData.dataWord0Length = (uint8_t)bitWidth; + config->serialData.dataWordLength = (uint8_t)bitWidth; + config->serialData.dataWordNLength = (uint8_t)bitWidth; + config->serialData.dataFirstBitShifted = (uint8_t)bitWidth; + config->serialData.dataWordNum = 2U; + config->serialData.dataMaskedWord = (uint32_t)mode; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + config->fifo.fifoContinueOneError = true; +#endif +} + +/*! + * brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * param base SAI base pointer + */ +void SAI_Init(I2S_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + (void)CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(SAI_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_saiReset[SAI_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + /* disable interrupt and DMA request*/ + base->TCSR &= + ~(I2S_TCSR_FRIE_MASK | I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK | I2S_TCSR_FRDE_MASK | I2S_TCSR_FWDE_MASK); + base->RCSR &= + ~(I2S_RCSR_FRIE_MASK | I2S_RCSR_FWIE_MASK | I2S_RCSR_FEIE_MASK | I2S_RCSR_FRDE_MASK | I2S_RCSR_FWDE_MASK); +#else + /* disable interrupt and DMA request*/ + base->TCSR &= ~(I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK | I2S_TCSR_FWDE_MASK); + base->RCSR &= ~(I2S_RCSR_FWIE_MASK | I2S_RCSR_FEIE_MASK | I2S_RCSR_FWDE_MASK); +#endif +} + +/*! + * brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * param base SAI base pointer + */ +void SAI_Deinit(I2S_Type *base) +{ + SAI_TxEnable(base, false); + SAI_RxEnable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + (void)CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Reset all Tx register values */ + base->TCR2 = 0; + base->TCR3 = 0; + base->TCR4 = 0; + base->TCR5 = 0; + base->TMR = 0; +} + +/*! + * brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Reset all Rx register values */ + base->RCR2 = 0; + base->RCR3 = 0; + base->RCR4 = 0; + base->RCR5 = 0; + base->RMR = 0; +} + +/*! + * brief Enables/disables the SAI Tx. + * + * param base SAI base pointer + * param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Rx, should enable RE bit. */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* If Rx not in sync with Tx, then disable Tx, otherwise, shall not disable Tx */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) != 0x1U) + { + /* Disable TE bit */ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); + } + } +} + +/*! + * brief Enables/disables the SAI Rx. + * + * param base SAI base pointer + * param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Tx, should enable TE bit. */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* If Tx not in sync with Rx, then disable Rx, otherwise, shall not disable Rx */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) != 0x1U) + { + /* Disable RE bit */ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); + } + } +} + +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param resetType Reset type, FIFO reset or software reset + */ +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType) +{ + base->TCSR |= (uint32_t)resetType; + + /* Clear the software reset */ + base->TCSR &= ~I2S_TCSR_SR_MASK; +} + +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param resetType Reset type, FIFO reset or software reset + */ +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType) +{ + base->RCSR |= (uint32_t)resetType; + + /* Clear the software reset */ + base->RCSR &= ~I2S_RCSR_SR_MASK; +} + +/*! + * brief Set the Tx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(mask); +} + +/*! + * brief Set the Rx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(mask); +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); + + val |= I2S_TCR4_MF(order); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); + + val |= I2S_RCR4_MF(order); + base->RCR4 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); + + val |= I2S_TCR2_BCP(polarity); + base->TCR2 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); + + val |= I2S_RCR2_BCP(polarity); + base->RCR2 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); + + val |= I2S_TCR4_FSP(polarity); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); + + val |= I2S_RCR4_FSP(polarity); + base->RCR4 = val; +} + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * brief Set Tx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->TCR4; + + val &= ~I2S_TCR4_FPACK_MASK; + val |= I2S_TCR4_FPACK(pack); + base->TCR4 = val; +} + +/*! + * brief Set Rx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->RCR4; + + val &= ~I2S_RCR4_FPACK_MASK; + val |= I2S_RCR4_FPACK(pack); + base->RCR4 = val; +} +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! + * brief Transmitter bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t tcr2 = base->TCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + tcr2 &= ~I2S_TCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + tcr2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + tcr2 |= I2S_TCR2_DIV(bitClockDiv / 2U - 1UL); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t rcr2 = base->RCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + rcr2 &= ~I2S_RCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + rcr2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + rcr2 |= I2S_RCR2_DIV(bitClockDiv / 2U - 1UL); + } + + base->RCR2 = rcr2; +} + +/*! + * brief Transmitter Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t tcr2 = base->TCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + tcr2 &= ~(I2S_TCR2_BCD_MASK | I2S_TCR2_BCP_MASK | I2S_TCR2_BCI_MASK | I2S_TCR2_BCS_MASK | I2S_TCR2_MSEL_MASK); + tcr2 |= I2S_TCR2_BCD(1U) | I2S_TCR2_BCP(config->bclkPolarity) | I2S_TCR2_BCI(config->bclkInputDelay) | + I2S_TCR2_BCS(config->bclkSrcSwap) | I2S_TCR2_MSEL(config->bclkSource); + } + else + { + tcr2 &= ~(I2S_TCR2_BCD_MASK); + tcr2 |= I2S_TCR2_BCP(config->bclkPolarity); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t rcr2 = base->RCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + rcr2 &= ~(I2S_RCR2_BCD_MASK | I2S_RCR2_BCP_MASK | I2S_RCR2_BCI_MASK | I2S_RCR2_BCS_MASK | I2S_RCR2_MSEL_MASK); + rcr2 |= I2S_RCR2_BCD(1U) | I2S_RCR2_BCP(config->bclkPolarity) | I2S_RCR2_BCI(config->bclkInputDelay) | + I2S_RCR2_BCS(config->bclkSrcSwap) | I2S_RCR2_MSEL(config->bclkSource); + } + else + { + rcr2 &= ~(I2S_RCR2_BCD_MASK); + rcr2 |= I2S_RCR2_BCP(config->bclkPolarity); + } + + base->RCR2 = rcr2; +} + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * brief Master clock configurations. + * + * param base SAI base pointer. + * param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config) +{ + assert(config != NULL); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + uint32_t val = 0; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) + /* Check if master clock divider enabled, then set master clock divider */ + if (config->mclkOutputEnable) + { + SAI_SetMasterClockDivider(base, config->mclkHz, config->mclkSourceClkHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ +} +#endif + +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE +/*! + * brief SAI transmitter fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((config->fifoWatermark == 0U) || + (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) + { + config->fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U); + } +#endif + + uint32_t tcr4 = base->TCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE + tcr4 &= ~I2S_TCR4_FCOMB_MASK; + tcr4 |= I2S_TCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + tcr4 &= ~I2S_TCR4_FCONT_MASK; + /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX + * not work */ + if (base->TMR == 0U) + { + tcr4 |= I2S_TCR4_FCONT(config->fifoContinueOneError); + } +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + tcr4 &= ~I2S_TCR4_FPACK_MASK; + tcr4 |= I2S_TCR4_FPACK(config->fifoPacking); +#endif + + base->TCR4 = tcr4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + base->TCR1 = (base->TCR1 & (~I2S_TCR1_TFW_MASK)) | I2S_TCR1_TFW(config->fifoWatermark); +#endif +} + +/*! + * brief SAI receiver fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((config->fifoWatermark == 0U) || + (config->fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) + { + config->fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U); + } +#endif + uint32_t rcr4 = base->RCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE + rcr4 &= ~I2S_RCR4_FCOMB_MASK; + rcr4 |= I2S_RCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + rcr4 &= ~I2S_RCR4_FCONT_MASK; + rcr4 |= I2S_RCR4_FCONT(config->fifoContinueOneError); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + rcr4 &= ~I2S_RCR4_FPACK_MASK; + rcr4 |= I2S_RCR4_FPACK(config->fifoPacking); +#endif + + base->RCR4 = rcr4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + base->RCR1 = (base->RCR1 & (~I2S_RCR1_RFW_MASK)) | I2S_RCR1_RFW(config->fifoWatermark); +#endif +} +#endif + +/*! + * brief SAI transmitter Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + assert(config != NULL); + assert((config->frameSyncWidth - 1UL) <= (I2S_TCR4_SYWD_MASK >> I2S_TCR4_SYWD_SHIFT)); + + uint32_t tcr4 = base->TCR4; + + tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE + tcr4 &= ~I2S_TCR4_ONDEM_MASK; + tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + tcr4 |= + I2S_TCR4_FSE(config->frameSyncEarly) | I2S_TCR4_FSP(config->frameSyncPolarity) | + I2S_TCR4_FSD(((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) ? 1UL : 0U) | + I2S_TCR4_SYWD(config->frameSyncWidth - 1UL); + + base->TCR4 = tcr4; +} + +/*! + * brief SAI receiver Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + assert(config != NULL); + assert((config->frameSyncWidth - 1UL) <= (I2S_RCR4_SYWD_MASK >> I2S_RCR4_SYWD_SHIFT)); + + uint32_t rcr4 = base->RCR4; + + rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE + rcr4 &= ~I2S_RCR4_ONDEM_MASK; + rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + rcr4 |= + I2S_RCR4_FSE(config->frameSyncEarly) | I2S_RCR4_FSP(config->frameSyncPolarity) | + I2S_RCR4_FSD(((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) ? 1UL : 0U) | + I2S_RCR4_SYWD(config->frameSyncWidth - 1UL); + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter Serial data configurations. + * + * param base SAI base pointer. + * param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t tcr4 = base->TCR4; + + base->TCR5 = I2S_TCR5_WNW(config->dataWordNLength - 1UL) | I2S_TCR5_W0W(config->dataWord0Length - 1UL) | + I2S_TCR5_FBT(config->dataFirstBitShifted - 1UL); + base->TMR = config->dataMaskedWord; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX + * not work */ + if (config->dataMaskedWord > 0U) + { + tcr4 &= ~I2S_TCR4_FCONT_MASK; + } +#endif + tcr4 &= ~(I2S_TCR4_FRSZ_MASK | I2S_TCR4_MF_MASK); + tcr4 |= I2S_TCR4_FRSZ(config->dataWordNum - 1UL) | I2S_TCR4_MF(config->dataOrder); + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + tcr4 &= ~I2S_TCR4_CHMOD_MASK; + tcr4 |= I2S_TCR4_CHMOD(config->dataMode); +#endif + + base->TCR4 = tcr4; +} + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t rcr4 = base->RCR4; + + base->RCR5 = I2S_RCR5_WNW(config->dataWordNLength - 1UL) | I2S_RCR5_W0W(config->dataWord0Length - 1UL) | + I2S_RCR5_FBT(config->dataFirstBitShifted - 1UL); + base->RMR = config->dataMaskedWord; + + rcr4 &= ~(I2S_RCR4_FRSZ_MASK | I2S_RCR4_MF_MASK); + rcr4 |= I2S_RCR4_FRSZ(config->dataWordNum - 1uL) | I2S_RCR4_MF(config->dataOrder); + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint8_t i = 0U; + uint32_t val = 0U; + uint8_t channelNums = 0U; + + /* reset transmitter */ + SAI_TxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET(1UL << i, config->channelMask)) + { + channelNums++; + config->endChannel = i; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + config->startChannel = i; + break; + } + } + + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(config->channelMask); + + if (config->syncMode == kSAI_ModeAsync) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + } + if (config->syncMode == kSAI_ModeSync) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + } +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + if (config->syncMode == kSAI_ModeSyncWithOtherTx) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + } + if (config->syncMode == kSAI_ModeSyncWithOtherRx) + { + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + } +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + + /* bit clock configurations */ + SAI_TxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_TxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_TxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE + /* fifo configurations */ + SAI_TxSetFifoConfig(base, &config->fifo); +#endif +} + +/*! + * brief SAI transmitter transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + assert(config->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + + handle->bitWidth = config->serialData.dataWordNLength; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((config->fifo.fifoWatermark == 0U) || + (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) + { + config->fifo.fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U); + } + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* transmitter configurations */ + SAI_TxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief SAI receiver configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint8_t i = 0U; + uint32_t val = 0U; + uint8_t channelNums = 0U; + + /* reset receiver */ + SAI_RxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + channelNums++; + config->endChannel = i; + } + } + + for (i = 0U; i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), config->channelMask)) + { + config->startChannel = i; + break; + } + } + + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(config->channelMask); + + /* Set Sync mode */ + if (config->syncMode == kSAI_ModeAsync) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + } + if (config->syncMode == kSAI_ModeSync) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + } +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + if (config->syncMode == kSAI_ModeSyncWithOtherTx) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + } + if (config->syncMode == kSAI_ModeSyncWithOtherRx) + { + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + } +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + + /* bit clock configurations */ + SAI_RxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_RxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_RxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE + /* fifo configurations */ + SAI_RxSetFifoConfig(base, &config->fifo); +#endif +} + +/*! + * brief SAI receiver transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + handle->bitWidth = config->serialData.dataWordNLength; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((config->fifo.fifoWatermark == 0U) || + (config->fifo.fifoWatermark > (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base)))) + { + config->fifo.fifoWatermark = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) / 2U); + } + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* receiver configurations */ + SAI_RxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief Get classic I2S mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); +} + +/*! + * brief Get left justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get right justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get DSP mode configurations. + * + * note DSP mode is also called PCM mode which support MODE A and MODE B, + * DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * config->frameSync.frameSyncEarly = true; + * SAI_TxSetConfig(base, config) + * endcode + * + * DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * SAI_TxSetConfig(base, config) + * endcode + * + * param config transceiver configurations. + * param frameSyncWidth length of frame sync. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask mask value of the channel to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + default: + assert(false); + break; + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get TDM mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + assert(dataWordNum <= 32U); + + SAI_GetCommonConfig(config, bitWidth, kSAI_Stereo, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + case kSAI_FrameSyncLenPerWordWidth: + break; + default: + assert(false); + break; + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; + config->serialData.dataWordNum = (uint8_t)dataWordNum; +} + +/*! + * brief Sends data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint32_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + bytesPerWord = (((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - base->TCR1) * bytesPerWord); +#endif + + while (i < size) + { + /* Wait until it can write data */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } + + SAI_WriteNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord); + i += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } +} + +/*! + * brief Sends data to multi channel using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t i = 0, j = 0; + uint32_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + bytesPerWord = (((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - base->TCR1) * bytesPerWord); +#endif + + for (i = 0U; (i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), channelMask)) + { + channelNums++; + endChannel = i; + } + } + + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until it can write data */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } + + SAI_WriteNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer, + bytesPerWord * channelNums); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums); + j += bytesPerWord * channelNums; + } + + /* Wait until the last data is sent */ + while (!(IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK))) + { + } +} + +/*! + * brief Receives multi channel data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t i = 0, j = 0; + uint32_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + bytesPerWord = base->RCR1 * bytesPerWord; +#endif + for (i = 0U; (i < (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) + { + if (IS_SAI_FLAG_SET((1UL << i), channelMask)) + { + channelNums++; + endChannel = i; + } + } + + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until data is received */ + while (!(IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK))) + { + } + + SAI_ReadNonBlocking(base, channel, channelMask, endChannel, (uint8_t)bitWidth, buffer, + bytesPerWord * channelNums); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord * channelNums); + j += bytesPerWord * channelNums; + } +} + +/*! + * brief Receives data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint32_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + bytesPerWord = base->RCR1 * bytesPerWord; +#endif + + while (i < size) + { + /* Wait until data is received */ + while (!(IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK))) + { + } + + SAI_ReadNonBlocking(base, channel, 1UL << channel, channel, (uint8_t)bitWidth, buffer, bytesPerWord); + buffer = (uint8_t *)((uintptr_t)buffer + bytesPerWord); + i += bytesPerWord; + } +} + +/*! + * brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->base = base; + + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + + /* Enable Tx irq */ + (void)EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); +} + +/*! + * brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle != NULL); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->base = base; + + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + + /* Enable Rx irq */ + (void)EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); +} + +/*! + * brief Performs an interrupt non-blocking send transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_TxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data != NULL) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = (uint32_t)kSAI_Busy; + + /* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + /* Use FIFO request interrupt and fifo error*/ + SAI_TxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_TxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + + /* Enable Tx transfer */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs an interrupt non-blocking receive transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle != NULL); + assert(handle->channelNums <= (uint32_t)FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data != NULL) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = (uint32_t)kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + /* Use FIFO request interrupt and fifo error*/ + SAI_RxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_RxEnableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + + /* Enable Rx transfer */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Gets a set byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + uint32_t queueDriverIndex = handle->queueDriver; + + if (handle->state != (uint32_t)kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[queueDriverIndex] - handle->saiQueue[queueDriverIndex].dataSize); + } + + return status; +} + +/*! + * brief Gets a received byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + uint32_t queueDriverIndex = handle->queueDriver; + + if (handle->state != (uint32_t)kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[queueDriverIndex] - handle->saiQueue[queueDriverIndex].dataSize); + } + + return status; +} + +/*! + * brief Aborts the current send. + * + * note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Stop Tx transfer and disable interrupt */ + SAI_TxEnable(base, false); +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + /* Use FIFO request interrupt and fifo error */ + SAI_TxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_TxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + + handle->state = (uint32_t)kSAI_Idle; + + /* Clear the queue */ + (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * (uint8_t)SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Stop Tx transfer and disable interrupt */ + SAI_RxEnable(base, false); +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + /* Use FIFO request interrupt and fifo error */ + SAI_RxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FRIE_MASK); +#else + SAI_RxDisableInterrupts(base, I2S_TCSR_FEIE_MASK | I2S_TCSR_FWIE_MASK); +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + + handle->state = (uint32_t)kSAI_Idle; + + /* Clear the queue */ + (void)memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * (uint8_t)SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Abort the current transfer */ + SAI_TransferAbortSend(base, handle); + + /* Clear all the internal information */ + (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue)); + (void)memset(handle->transferSize, 0, sizeof(handle->transferSize)); + + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + /* Abort the current transfer */ + SAI_TransferAbortReceive(base, handle); + + /* Clear all the internal information */ + (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue)); + (void)memset(handle->transferSize, 0, sizeof(handle->transferSize)); + + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint32_t dataSize = (handle->bitWidth / 8UL) * handle->channelNums; + + /* Handle Error */ + if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FEF_MASK)) + { + /* Clear FIFO error flag to continue transfer */ + SAI_TxClearStatusFlags(base, I2S_TCSR_FEF_MASK); + + /* Reset FIFO for safety */ + SAI_TxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FRF_MASK)) + { + /* Judge if the data need to transmit is less than space */ + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), + (size_t)(((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - handle->watermark) * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); + } +#else + if (IS_SAI_FLAG_SET(base->TCSR, I2S_TCSR_FWF_MASK)) + { + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); + } +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + + /* If finished a block, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortSend(base, handle); + } +} + +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle != NULL); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint32_t dataSize = (handle->bitWidth / 8UL) * handle->channelNums; + + /* Handle Error */ + if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FEF_MASK)) + { + /* Clear FIFO error flag to continue transfer */ + SAI_RxClearStatusFlags(base, I2S_TCSR_FEF_MASK); + + /* Reset FIFO for safety */ + SAI_RxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FRF_MASK)) + { + /* Judge if the data need to transmit is less than space */ + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), handle->watermark * dataSize); + + /* Copy the data from sai buffer to FIFO */ + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); + } +#else + if (IS_SAI_FLAG_SET(base->RCSR, I2S_RCSR_FWF_MASK)) + { + size_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update internal state */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data = (uint8_t *)((uintptr_t)buffer + size); + } +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + + /* If finished a block, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortReceive(base, handle); + } +} + +#if defined(I2S0) +void I2S0_DriverIRQHandler(void); +void I2S0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S0, s_saiHandle[0][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S0_Tx_DriverIRQHandler(void); +void I2S0_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][0] != NULL); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S0_Rx_DriverIRQHandler(void); +void I2S0_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][1] != NULL); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S0*/ + +#if defined(I2S1) +void I2S1_DriverIRQHandler(void); +void I2S1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S1, s_saiHandle[1][1]); + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S1_Tx_DriverIRQHandler(void); +void I2S1_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][0] != NULL); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S1_Rx_DriverIRQHandler(void); +void I2S1_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][1] != NULL); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S1*/ + +#if defined(I2S2) +void I2S2_DriverIRQHandler(void); +void I2S2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S2, s_saiHandle[2][1]); + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S2, s_saiHandle[2][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S2_Tx_DriverIRQHandler(void); +void I2S2_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][0] != NULL); + s_saiTxIsr(I2S2, s_saiHandle[2][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S2_Rx_DriverIRQHandler(void); +void I2S2_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][1] != NULL); + s_saiRxIsr(I2S2, s_saiHandle[2][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S2*/ + +#if defined(I2S3) +void I2S3_DriverIRQHandler(void); +void I2S3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S3, s_saiHandle[3][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S3_Tx_DriverIRQHandler(void); +void I2S3_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0] != NULL); + s_saiTxIsr(I2S3, s_saiHandle[3][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S3_Rx_DriverIRQHandler(void); +void I2S3_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1] != NULL); + s_saiRxIsr(I2S3, s_saiHandle[3][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* I2S3*/ + +#if defined(I2S4) +void I2S4_DriverIRQHandler(void); +void I2S4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S4, s_saiHandle[4][1]); + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S4, s_saiHandle[4][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S4_Tx_DriverIRQHandler(void); +void I2S4_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][0] != NULL); + s_saiTxIsr(I2S4, s_saiHandle[4][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S4_Rx_DriverIRQHandler(void); +void I2S4_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][1] != NULL); + s_saiRxIsr(I2S4, s_saiHandle[4][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && \ + defined(I2S6) +void I2S56_DriverIRQHandler(void); +void I2S56_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + I2S_Type *base = s_saiHandle[5][1]->base; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(base, s_saiHandle[5][1]); + } + + base = s_saiHandle[5][0]->base; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(base, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(base, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(base, s_saiHandle[5][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S56_Tx_DriverIRQHandler(void); +void I2S56_Tx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][0] != NULL); + s_saiTxIsr(s_saiHandle[5][0]->base, s_saiHandle[5][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S56_Rx_DriverIRQHandler(void); +void I2S56_Rx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][1] != NULL); + s_saiRxIsr(s_saiHandle[5][1]->base, s_saiHandle[5][1]); + SDK_ISR_EXIT_BARRIER; +} + +#else + +#if defined(I2S5) +void I2S5_DriverIRQHandler(void); +void I2S5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S5, s_saiHandle[5][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S5_Tx_DriverIRQHandler(void); +void I2S5_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][0] != NULL); + s_saiTxIsr(I2S5, s_saiHandle[5][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S5_Rx_DriverIRQHandler(void); +void I2S5_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][1] != NULL); + s_saiRxIsr(I2S5, s_saiHandle[5][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(I2S6) +void I2S6_DriverIRQHandler(void); +void I2S6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(I2S6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(I2S6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(I2S6, s_saiHandle[6][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void I2S6_Tx_DriverIRQHandler(void); +void I2S6_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][0] != NULL); + s_saiTxIsr(I2S6, s_saiHandle[6][0]); + SDK_ISR_EXIT_BARRIER; +} + +void I2S6_Rx_DriverIRQHandler(void); +void I2S6_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][1] != NULL); + s_saiRxIsr(I2S6, s_saiHandle[6][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(AUDIO__SAI0) +void AUDIO_SAI0_INT_DriverIRQHandler(void); +void AUDIO_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[0][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI0, s_saiHandle[0][1]); + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[0][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI0 */ + +#if defined(AUDIO__SAI1) +void AUDIO_SAI1_INT_DriverIRQHandler(void); +void AUDIO_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI1 */ + +#if defined(AUDIO__SAI2) +void AUDIO_SAI2_INT_DriverIRQHandler(void); +void AUDIO_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[2][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[2][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI2, s_saiHandle[2][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI2 */ + +#if defined(AUDIO__SAI3) +void AUDIO_SAI3_INT_DriverIRQHandler(void); +void AUDIO_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[3][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[3][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI3, s_saiHandle[3][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(AUDIO__SAI6) +void AUDIO_SAI6_INT_DriverIRQHandler(void); +void AUDIO_SAI6_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[6][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[6][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI6, s_saiHandle[6][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI6 */ + +#if defined(AUDIO__SAI7) +void AUDIO_SAI7_INT_DriverIRQHandler(void); +void AUDIO_SAI7_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[7][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[7][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(AUDIO__SAI7, s_saiHandle[7][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[7][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[7][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(AUDIO__SAI7, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(AUDIO__SAI7, s_saiHandle[7][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* AUDIO__SAI7 */ + +#if defined(ADMA__SAI0) +void ADMA_SAI0_INT_DriverIRQHandler(void); +void ADMA_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI0 */ + +#if defined(ADMA__SAI1) +void ADMA_SAI1_INT_DriverIRQHandler(void); +void ADMA_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI1 */ + +#if defined(ADMA__SAI2) +void ADMA_SAI2_INT_DriverIRQHandler(void); +void ADMA_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI2 */ + +#if defined(ADMA__SAI3) +void ADMA_SAI3_INT_DriverIRQHandler(void); +void ADMA_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI3 */ + +#if defined(ADMA__SAI4) +void ADMA_SAI4_INT_DriverIRQHandler(void); +void ADMA_SAI4_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]); + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI4 */ + +#if defined(ADMA__SAI5) +void ADMA_SAI5_INT_DriverIRQHandler(void); +void ADMA_SAI5_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && + SAI_RxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && + SAI_TxGetEnabledInterruptStatus(ADMA__SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* ADMA__SAI5 */ + +#if defined(SAI0) +void SAI0_DriverIRQHandler(void); +void SAI0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[0][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI0, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI0, s_saiHandle[0][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI0 */ + +#if defined(SAI1) +void SAI1_DriverIRQHandler(void); +void SAI1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[1][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI1, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI1, s_saiHandle[1][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI1 */ + +#if defined(SAI2) +void SAI2_DriverIRQHandler(void); +void SAI2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[2][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI2, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI2, s_saiHandle[2][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI2 */ + +#if defined(SAI3) +void SAI3_DriverIRQHandler(void); +void SAI3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[3][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI3, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI3, s_saiHandle[3][0]); + } + SDK_ISR_EXIT_BARRIER; +} + +void SAI3_TX_DriverIRQHandler(void); +void SAI3_TX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0] != NULL); + s_saiTxIsr(SAI3, s_saiHandle[3][0]); + SDK_ISR_EXIT_BARRIER; +} + +void SAI3_RX_DriverIRQHandler(void); +void SAI3_RX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1] != NULL); + s_saiRxIsr(SAI3, s_saiHandle[3][1]); + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI3 */ + +#if defined(SAI4) +void SAI4_DriverIRQHandler(void); +void SAI4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI4, s_saiHandle[4][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[4][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI4, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI4, s_saiHandle[4][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI4 */ + +#if defined(SAI5) +void SAI5_DriverIRQHandler(void); +void SAI5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[5][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI5, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI5, s_saiHandle[5][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI5 */ + +#if defined(SAI6) +void SAI6_DriverIRQHandler(void); +void SAI6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][1] != NULL) && SAI_RxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiRxIsr(SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FRIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FRF_MASK | I2S_TCSR_FEF_MASK))) +#else + if ((s_saiHandle[6][0] != NULL) && SAI_TxGetEnabledInterruptStatus(SAI6, (I2S_TCSR_FWIE_MASK | I2S_TCSR_FEIE_MASK), + (I2S_TCSR_FWF_MASK | I2S_TCSR_FEF_MASK))) +#endif + { + s_saiTxIsr(SAI6, s_saiHandle[6][0]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif /* SAI6 */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai.h new file mode 100644 index 0000000000..d00f81e98b --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai.h @@ -0,0 +1,1437 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SAI_H_ +#define FSL_SAI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sai_driver SAI Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*!< Version 2.4.2 */ +/*@}*/ + +/*! @brief _sai_status_t, SAI return status.*/ +enum +{ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ +}; + +/*! @brief _sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific */ +enum +{ + kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */ + kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */ + kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */ + kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */ + kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */ + kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */ + kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */ + kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */ +}; + +/*! @brief Define the SAI bus type */ +typedef enum _sai_protocol +{ + kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ + kSAI_BusRightJustified, /*!< Uses right justified format. */ + kSAI_BusI2S, /*!< Uses I2S format. */ + kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ + kSAI_BusPCMB /*!< Uses I2S PCM B format. */ +} sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSAI_Master = 0x0U, /*!< Master mode include bclk and frame sync */ + kSAI_Slave = 0x1U, /*!< Slave mode include bclk and frame sync */ + kSAI_Bclk_Master_FrameSync_Slave = 0x2U, /*!< bclk in master mode, frame sync in slave mode */ + kSAI_Bclk_Slave_FrameSync_Master = 0x3U, /*!< bclk in slave mode, frame sync in master mode */ +} sai_master_slave_t; + +/*! @brief Mono or stereo audio format */ +typedef enum _sai_mono_stereo +{ + kSAI_Stereo = 0x0U, /*!< Stereo sound. */ + kSAI_MonoRight, /*!< Only Right channel have sound. */ + kSAI_MonoLeft /*!< Only left channel have sound. */ +} sai_mono_stereo_t; + +/*! @brief SAI data order, MSB or LSB */ +typedef enum _sai_data_order +{ + kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */ + kSAI_DataMSB /*!< MSB bit transferred first */ +} sai_data_order_t; + +/*! @brief SAI clock polarity, active high or low */ +typedef enum _sai_clock_polarity +{ + kSAI_PolarityActiveHigh = 0x0U, /*!< Drive outputs on rising edge */ + kSAI_PolarityActiveLow = 0x1U, /*!< Drive outputs on falling edge */ + kSAI_SampleOnFallingEdge = 0x0U, /*!< Sample inputs on falling edge */ + kSAI_SampleOnRisingEdge = 0x1U, /*!< Sample inputs on rising edge */ +} sai_clock_polarity_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ + kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ +} sai_sync_mode_t; + +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ + kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ + kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ + kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ +} sai_mclk_source_t; +#endif + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ + /* General device bit source definition */ + kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */ + kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2 */ + kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */ + /* Kinetis device bit clock source definition */ + kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 = 0x3U /*!< Bit clock from other SAI device */ +} sai_bclk_source_t; + +/*! @brief _sai_interrupt_enable_t, The SAI interrupt enable flag */ +enum +{ + kSAI_WordStartInterruptEnable = + I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ +}; + +/*! @brief _sai_dma_enable_t, The DMA request sources */ +enum +{ + kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ +}; + +/*! @brief _sai_flags, The SAI status flag */ +enum +{ + kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ +}; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ +} sai_reset_type_t; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ +} sai_fifo_packing_t; +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! @brief SAI user configuration structure */ +typedef struct _sai_config +{ + sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ + sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +#endif + sai_bclk_source_t bclkSource; /*!< Bit Clock source */ + sai_master_slave_t masterSlave; /*!< Master or slave */ +} sai_config_t; + +#ifndef SAI_XFER_QUEUE_SIZE +/*!@brief SAI transfer queue size, user can refine it according to use case. */ +#define SAI_XFER_QUEUE_SIZE (4U) +#endif + +/*! @brief Audio sample rate */ +typedef enum _sai_sample_rate +{ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ + kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ + kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ + kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ +} sai_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _sai_word_width +{ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} sai_word_width_t; + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE +/*! @brief sai data pin state definition */ +typedef enum _sai_data_pin_state +{ + kSAI_DataPinStateTriState = + 0U, /*!< transmit data pins are tri-stated when slots are masked or channels are disabled */ + kSAI_DataPinStateOutputZero = 1U, /*!< transmit data pins are never tri-stated and will output zero when slots + are masked or channel disabled */ +} sai_data_pin_state_t; +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE +/*! @brief sai fifo combine mode definition */ +typedef enum _sai_fifo_combine +{ + kSAI_FifoCombineDisabled = 0U, /*!< sai fifo combine mode disabled */ + kSAI_FifoCombineModeEnabledOnRead, /*!< sai fifo combine mode enabled on FIFO reads */ + kSAI_FifoCombineModeEnabledOnWrite, /*!< sai fifo combine mode enabled on FIFO write */ + kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */ +} sai_fifo_combine_t; +#endif + +/*! @brief sai transceiver type */ +typedef enum _sai_transceiver_type +{ + kSAI_Transmitter = 0U, /*!< sai transmitter */ + kSAI_Receiver = 1U, /*!< sai receiver */ +} sai_transceiver_type_t; + +/*! @brief sai frame sync len */ +typedef enum _sai_frame_sync_len +{ + kSAI_FrameSyncLenOneBitClk = 0U, /*!< 1 bit clock frame sync len for DSP mode */ + kSAI_FrameSyncLenPerWordWidth = 1U, /*!< Frame sync length decided by word width */ +} sai_frame_sync_len_t; + +/*! @brief sai transfer format */ +typedef struct _sai_transfer_format +{ + uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ + uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ + sai_mono_stereo_t stereo; /*!< Mono or stereo */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + + sai_protocol_t protocol; /*!< Which audio protocol used */ + bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame + sync length is 64 times of bit clock. */ +} sai_transfer_format_t; + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! @brief master clock configurations */ +typedef struct _sai_master_clock +{ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< master clock output enable */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif +#endif + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) + uint32_t mclkHz; /*!< target mclk frequency */ + uint32_t mclkSourceClkHz; /*!< mclk source frequency*/ +#endif +} sai_master_clock_t; +#endif + +/*! @brief sai fifo feature*/ +#if (defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) || \ + (defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) || \ + (defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING) || \ + (defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)) +#define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 1 +#else +#define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 0 +#endif + +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE +/*! @brief sai fifo configurations */ +typedef struct _sai_fifo +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + bool fifoContinueOneError; /*!< fifo continues when error occur */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE + sai_fifo_combine_t fifoCombine; /*!< fifo combine mode */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + sai_fifo_packing_t fifoPacking; /*!< fifo packing mode */ +#endif +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + uint8_t fifoWatermark; /*!< fifo watermark */ +#endif +} sai_fifo_t; +#endif + +/*! @brief sai bit clock configurations */ +typedef struct _sai_bit_clock +{ + bool bclkSrcSwap; /*!< bit clock source swap */ + bool bclkInputDelay; /*!< bit clock actually used by the transmitter is delayed by the pad output delay, + this has effect of decreasing the data input setup time, but increasing the data output valid + time .*/ + sai_clock_polarity_t bclkPolarity; /*!< bit clock polarity */ + sai_bclk_source_t bclkSource; /*!< bit Clock source */ +} sai_bit_clock_t; + +/*! @brief sai frame sync configurations */ +typedef struct _sai_frame_sync +{ + uint8_t frameSyncWidth; /*!< frame sync width in number of bit clocks */ + bool frameSyncEarly; /*!< TRUE is frame sync assert one bit before the first bit of frame + FALSE is frame sync assert with the first bit of the frame */ + +#if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE + bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */ +#endif + + sai_clock_polarity_t frameSyncPolarity; /*!< frame sync polarity */ + +} sai_frame_sync_t; + +/*! @brief sai serial data configurations */ +typedef struct _sai_serial_data +{ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + sai_data_pin_state_t dataMode; /*!< sai data pin state when slots masked or channel disabled */ +#endif + + sai_data_order_t dataOrder; /*!< configure whether the LSB or MSB is transmitted first */ + uint8_t dataWord0Length; /*!< configure the number of bits in the first word in each frame */ + uint8_t dataWordNLength; /*!< configure the number of bits in the each word in each frame, except the first word */ + uint8_t dataWordLength; /*!< used to record the data length for dma transfer */ + uint8_t + dataFirstBitShifted; /*!< Configure the bit index for the first bit transmitted for each word in the frame */ + uint8_t dataWordNum; /*!< configure the number of words in each frame */ + uint32_t dataMaskedWord; /*!< configure whether the transmit word is masked */ +} sai_serial_data_t; + +/*! @brief sai transceiver configurations */ +typedef struct _sai_transceiver +{ + sai_serial_data_t serialData; /*!< serial data configurations */ + sai_frame_sync_t frameSync; /*!< ws configurations */ + sai_bit_clock_t bitClock; /*!< bit clock configurations */ +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE + sai_fifo_t fifo; /*!< fifo configurations */ +#endif + sai_master_slave_t masterSlave; /*!< transceiver is master or slave */ + + sai_sync_mode_t syncMode; /*!< transceiver sync mode */ + + uint8_t startChannel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + +} sai_transceiver_t; + +/*! @brief SAI transfer structure */ +typedef struct _sai_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} sai_transfer_t; + +typedef struct _sai_handle sai_handle_t; + +/*! @brief SAI transfer callback prototype */ +typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI handle structure */ +struct _sai_handle +{ + I2S_Type *base; /*!< base address */ + + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + uint8_t watermark; /*!< Watermark value */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * @param base SAI base pointer. + */ +void SAI_Init(I2S_Type *base); + +/*! + * @brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * @param base SAI base pointer. + */ +void SAI_Deinit(I2S_Type *base); + +/*! + * @brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base); + +/*! + * @brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base); + +/*! + * @brief Enables/disables the SAI Tx. + * + * @param base SAI base pointer. + * @param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Enables/disables the SAI Rx. + * + * @param base SAI base pointer. + * @param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR4 |= I2S_RCR4_FSD_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } +} + +/*! + * @brief Set Tx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR4 |= I2S_TCR4_FSD_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } +} + +/*! + * @brief Transmitter bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz Bit clock source frequency. + * @param sampleRate Audio data sample rate. + * @param bitWidth Audio data bitWidth. + * @param channelNumbers Audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Receiver bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz Bit clock source frequency. + * @param sampleRate Audio data sample rate. + * @param bitWidth Audio data bitWidth. + * @param channelNumbers Audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Transmitter Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +/*! + * @brief Receiver Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * @brief Master clock configurations. + * + * @param base SAI base pointer. + * @param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config); +#endif + +#if FSL_SAI_HAS_FIFO_EXTEND_FEATURE +/*! + * @brief SAI transmitter fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); + +/*! + * @brief SAI receiver fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); +#endif + +/*! + * @brief SAI transmitter Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI receiver Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI transmitter Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI transmitter configurations. + * + * @param base SAI base pointer. + * @param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief SAI receiver configurations. + * + * @param base SAI base pointer. + * @param config receiver configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get left justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get right justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get TDM mode configurations. + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data word width. + * @param dataWordNum word number in one frame. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask); + +/*! + * @brief Get DSP mode configurations. + * + * @note DSP mode is also called PCM mode which support MODE A and MODE B, + * DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * @code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * config->frameSync.frameSyncEarly = true; + * SAI_TxSetConfig(base, config) + * @endcode + * + * DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig: + * @code + * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask) + * SAI_TxSetConfig(base, config) + * @endcode + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) +{ + return base->TCSR; +} + +/*! + * @brief Clears the SAI Tx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) +{ + return base->RCSR; +} + +/*! + * @brief Clears the SAI Rx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following sources if defined. + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param tresetType Reset type, FIFO reset or software reset + */ +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType); + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param resetType Reset type, FIFO reset or software reset + */ +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType); + +/*! + * @brief Set the Tx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Rx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param polarity + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief Set Tx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); + +/*! + * @brief Set Rx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR +/*! + * @brief Set Tx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in TCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ +static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->TCR4 |= I2S_TCR4_FCONT_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FCONT_MASK; + } +} + +/*! + * @brief Set Rx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in RCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ +static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->RCR4 |= I2S_RCR4_FCONT_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FCONT_MASK; + } +} +#endif + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Enables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Disables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! + * @brief Disables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the SAI Tx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Enables/disables the SAI Rx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Gets the SAI Tx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uintptr_t)(&(base->TDR)[channel]); +} + +/*! + * @brief Gets the SAI Rx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uintptr_t)(&(base->RDR)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Sends data to multi channel using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param data Data needs to be written. + */ +static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) +{ + base->TDR[channel] = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Receives multi channel data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from the SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @return Data in SAI FIFO. + */ +static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) +{ + return base->RDR[channel]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief SAI transmitter transfer configurations. + * + * This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + +/*! + * @brief SAI receiver transfer configurations. + * + * This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config receiver configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + + +/*! + * @brief Performs an interrupt non-blocking send transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Aborts the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* FSL_SAI_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai_edma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai_edma.c new file mode 100644 index 0000000000..64ea0711af --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai_edma.c @@ -0,0 +1,1013 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sai_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai_edma" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32UL) & ~0x1FU) + +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +/* Only support 2 and 4 channel */ +#define SAI_CHANNEL_MAP_MODULO(channel) ((channel) == 2U ? kEDMA_Modulo8bytes : kEDMA_Modulo16bytes) + +/*handle; + status_t status = kStatus_SAI_TxBusy; + + if (saiHandle->state != (uint32_t)kSAI_BusyLoopTransfer) + { + if (saiHandle->queueDriver + tcds > (uint32_t)SAI_XFER_QUEUE_SIZE) + { + (void)memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, + sizeof(sai_transfer_t) * ((uint32_t)SAI_XFER_QUEUE_SIZE - saiHandle->queueDriver)); + (void)memset(&saiHandle->saiQueue[0U], 0, + sizeof(sai_transfer_t) * (saiHandle->queueDriver + tcds - (uint32_t)SAI_XFER_QUEUE_SIZE)); + } + else + { + (void)memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t) * tcds); + } + saiHandle->queueDriver = (uint8_t)((saiHandle->queueDriver + tcds) % (uint32_t)SAI_XFER_QUEUE_SIZE); + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + /* Disable DMA enable bit */ + SAI_TxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); + EDMA_AbortTransfer(handle); + status = kStatus_SAI_TxIdle; + } + } + + /* If finished a block, call the callback function */ + if (saiHandle->callback != NULL) + { + (saiHandle->callback)(privHandle->base, saiHandle, status, saiHandle->userData); + } +} + +static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; + sai_edma_handle_t *saiHandle = privHandle->handle; + status_t status = kStatus_SAI_RxBusy; + + if (saiHandle->state != (uint32_t)kSAI_BusyLoopTransfer) + { + if (saiHandle->queueDriver + tcds > (uint32_t)SAI_XFER_QUEUE_SIZE) + { + (void)memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, + sizeof(sai_transfer_t) * ((uint32_t)SAI_XFER_QUEUE_SIZE - saiHandle->queueDriver)); + (void)memset(&saiHandle->saiQueue[0U], 0, + sizeof(sai_transfer_t) * (saiHandle->queueDriver + tcds - (uint32_t)SAI_XFER_QUEUE_SIZE)); + } + else + { + (void)memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t) * tcds); + } + saiHandle->queueDriver = (uint8_t)((saiHandle->queueDriver + tcds) % (uint32_t)SAI_XFER_QUEUE_SIZE); + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + /* Disable DMA enable bit */ + SAI_RxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); + EDMA_AbortTransfer(handle); + status = kStatus_SAI_RxIdle; + } + } + + /* If finished a block, call the callback function */ + if (saiHandle->callback != NULL) + { + (saiHandle->callback)(privHandle->base, saiHandle, status, saiHandle->userData); + } +} + +/*! + * brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param base SAI peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *txDmaHandle) +{ + assert((handle != NULL) && (txDmaHandle != NULL)); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = txDmaHandle; + handle->callback = callback; + handle->userData = userData; + handle->interleaveType = kSAI_EDMAInterleavePerChannelSample; + + /* Set SAI state to idle */ + handle->state = (uint32_t)kSAI_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(txDmaHandle, (edma_tcd_t *)(STCD_ADDR(handle->tcd)), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(txDmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +/*! + * brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param base SAI peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *rxDmaHandle) +{ + assert((handle != NULL) && (rxDmaHandle != NULL)); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = rxDmaHandle; + handle->callback = callback; + handle->userData = userData; + handle->interleaveType = kSAI_EDMAInterleavePerChannelSample; + + /* Set SAI state to idle */ + handle->state = (uint32_t)kSAI_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(rxDmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(rxDmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +/*! + * brief Initializes the SAI interleave type. + * + * This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would + * like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is + * kSAI_EDMAInterleavePerChannelSample always + * + * param handle SAI eDMA handle pointer. + * param interleaveType SAI interleave type. + */ +void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType) +{ + handle->interleaveType = interleaveType; +} + +/*! + * brief Configures the SAI Tx. + * + * note SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. + * To activate the multi-channel transfer enable SAI channels by filling the channelMask + * of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine + * mode by assigning kSAI_FifoCombineModeEnabledOnWrite to the fifoCombine member of sai_fifo_combine_t + * which is a member of sai_transceiver_t. + * This is an example of multi-channel data transfer configuration step. + * code + * sai_transceiver_t config; + * SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask); + * config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnWrite; + * SAI_TransferTxSetConfigEDMA(I2S0, &edmaHandle, &config); + * endcode + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param saiConfig sai configurations. + */ +void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig) +{ + assert((handle != NULL) && (saiConfig != NULL)); + + /* Configure the audio format to SAI registers */ + SAI_TxSetConfig(base, saiConfig); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE + /* Allow multi-channel transfer only if FIFO Combine mode is enabled */ + assert( + (saiConfig->channelNums <= 1U) || + ((saiConfig->channelNums > 1U) && ((saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnWrite) || + (saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnReadWrite)))); +#endif + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (saiConfig->serialData.dataWordLength == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U; + } + /* Update the data channel SAI used */ + handle->channel = saiConfig->startChannel; + handle->channelMask = saiConfig->channelMask; + handle->channelNums = saiConfig->channelNums; + + /* Clear the channel enable bits until do a send/receive */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + handle->count = (uint8_t)((uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - saiConfig->fifo.fifoWatermark); +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ +} + +/*! + * brief Configures the SAI Rx. + * + * note SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. + * To activate the multi-channel transfer enable SAI channels by filling the channelMask + * of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine + * mode by assigning kSAI_FifoCombineModeEnabledOnRead to the fifoCombine member of sai_fifo_combine_t + * which is a member of sai_transceiver_t. + * This is an example of multi-channel data transfer configuration step. + * code + * sai_transceiver_t config; + * SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask); + * config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead; + * SAI_TransferRxSetConfigEDMA(I2S0, &edmaHandle, &config); + * endcode + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param saiConfig sai configurations. + */ +void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig) +{ + assert((handle != NULL) && (saiConfig != NULL)); + + /* Configure the audio format to SAI registers */ + SAI_RxSetConfig(base, saiConfig); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE + /* Allow multi-channel transfer only if FIFO Combine mode is enabled */ + assert( + (saiConfig->channelNums <= 1U) || + ((saiConfig->channelNums > 1U) && ((saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnRead) || + (saiConfig->fifo.fifoCombine == kSAI_FifoCombineModeEnabledOnReadWrite)))); +#endif + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (saiConfig->serialData.dataWordLength == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = saiConfig->startChannel; + handle->channelMask = saiConfig->channelMask; + handle->channelNums = saiConfig->channelNums; + /* Clear the channel enable bits until do a send/receive */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; +#if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO) + handle->count = saiConfig->fifo.fifoWatermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_HAS_FIFO */ +} + +/*! + * brief Performs a non-blocking SAI transfer using DMA. + * + * note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * In classic I2S mode configuration. + * 1. The data source sent should be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelSample : + * -------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------- + * 2. The data source sent should be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelBlock : + * ------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ...| RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * ------------------------------------------------------------------------------------------------------- + * + * This function support multi channel transfer, + * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation + * on channel numbers + * 2. for the sai IP not support fifo combine mode, sai edma provide another solution which using + * EDMA modulo feature, but support 2 or 4 channels only. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA send successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert((handle != NULL) && (xfer != NULL)); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + uint32_t destOffset = 0U; + uint32_t srcOffset = xfer->dataSize / 2U; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + edma_minor_offset_config_t minorOffset = {.enableSrcMinorOffset = true, + .enableDestMinorOffset = false, + .minorOffset = 0xFFFFFU - 2U * srcOffset + 1U + handle->bytesPerFrame}; + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data != NULL) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = (uint32_t)kSAI_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + +#if !(defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + if (handle->channelNums > 1U) + { + destOffset = sizeof(uint32_t); + } +#endif + + if (handle->interleaveType == kSAI_EDMAInterleavePerChannelSample) + { + /* Prepare edma configure */ + EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, + (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + } + else + { + EDMA_PrepareTransferConfig(&config, xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + (uint32_t *)destAddr, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)2U * handle->bytesPerFrame, xfer->dataSize); + EDMA_TcdSetTransferConfig(currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfig(currentTCD, &minorOffset); + EDMA_TcdEnableInterrupts(currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequest(currentTCD, true); + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, currentTCD); + } + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + if (EDMA_SubmitTransfer(handle->dmaHandle, &config) != kStatus_Success) + { + return kStatus_SAI_QueueFull; + } + +#if !(defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + if (handle->channelNums > 1U) + { + if ((handle->channelNums % 2U) != 0U) + { + return kStatus_InvalidArgument; + } + + EDMA_SetModulo(handle->dmaHandle->base, handle->dmaHandle->channel, kEDMA_ModuloDisable, + SAI_CHANNEL_MAP_MODULO(handle->channelNums)); + } +#endif + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Tx clock */ + SAI_TxEnable(base, true); + + /* Enable the channel FIFO */ + base->TCR3 |= I2S_TCR3_TCE(handle->channelMask); + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SAI receive using eDMA. + * + * note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * In classic I2S mode configuration. + * 1. The output data will be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelSample : + * -------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------- + * 2. The output data will be formatted as below if handle->interleaveType = + * kSAI_EDMAInterleavePerChannelBlock : + * ------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ...| RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * ------------------------------------------------------------------------------------------------------- + * + * This function support multi channel transfer, + * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation + * on channel numbers + * 2. for the sai IP not support fifo combine mode, sai edma provide another solution which using + * EDMA modulo feature, but support 2 or 4 channels only. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert((handle != NULL) && (xfer != NULL)); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + uint32_t srcOffset = 0U; + uint32_t destOffset = xfer->dataSize / 2U; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + edma_minor_offset_config_t minorOffset = { + .enableSrcMinorOffset = false, + .enableDestMinorOffset = true, + .minorOffset = 0xFFFFFU - 2U * destOffset + 1U + (uint32_t)handle->bytesPerFrame}; + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data != NULL) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = (uint32_t)kSAI_Busy; + + /* Update queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + +#if !(defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + if (handle->channelNums > 1U) + { + srcOffset = sizeof(uint32_t); + } +#endif + + if (handle->interleaveType == kSAI_EDMAInterleavePerChannelSample) + { + /* Prepare edma configure */ + EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)handle->bytesPerFrame, + (uint32_t)handle->count * handle->bytesPerFrame, xfer->dataSize); + } + else + { + EDMA_PrepareTransferConfig(&config, (uint32_t *)srcAddr, (uint32_t)handle->bytesPerFrame, (int16_t)srcOffset, + xfer->data, (uint32_t)handle->bytesPerFrame, (int16_t)destOffset, + (uint32_t)2U * handle->bytesPerFrame, xfer->dataSize); + EDMA_TcdSetTransferConfig(currentTCD, &config, NULL); + EDMA_TcdSetMinorOffsetConfig(currentTCD, &minorOffset); + EDMA_TcdEnableInterrupts(currentTCD, (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_TcdEnableAutoStopRequest(currentTCD, true); + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, currentTCD); + } + + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + if (EDMA_SubmitTransfer(handle->dmaHandle, &config) != kStatus_Success) + { + return kStatus_SAI_QueueFull; + } + +#if !(defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + if (handle->channelNums > 1U) + { + if ((handle->channelNums % 2U) != 0U) + { + return kStatus_InvalidArgument; + } + + EDMA_SetModulo(handle->dmaHandle->base, handle->dmaHandle->channel, SAI_CHANNEL_MAP_MODULO(handle->channelNums), + kEDMA_ModuloDisable); + } +#endif + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable the channel FIFO */ + base->RCR3 |= I2S_RCR3_RCE(handle->channelMask); + + /* Enable SAI Rx clock */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SAI loop transfer using eDMA. + * + * note This function support loop transfer only,such as A->B->...->A, application must be aware of + * that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in + * sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. + * This function support one sai channel only. + * + * Once the loop transfer start, application can use function SAI_TransferAbortSendEDMA to stop the loop transfer. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). + * param loopTransferCount the counts of xfer array. + * retval kStatus_Success Start a SAI eDMA send successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + */ +status_t SAI_TransferSendLoopEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert((handle != NULL) && (xfer != NULL)); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + sai_transfer_t *transfer = xfer; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + uint32_t tcdIndex = 0U; + + /* Change the state of handle */ + handle->state = (uint32_t)kSAI_Busy; + + for (uint32_t i = 0U; i < loopTransferCount; i++) + { + transfer = &xfer[i]; + + if ((transfer->data == NULL) || (transfer->dataSize == 0U) || (tcdIndex >= (uint32_t)SAI_XFER_QUEUE_SIZE)) + { + return kStatus_InvalidArgument; + } + + /* Update the queue state */ + handle->transferSize[tcdIndex] = transfer->dataSize; + handle->saiQueue[tcdIndex].data = transfer->data; + handle->saiQueue[tcdIndex].dataSize = transfer->dataSize; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, transfer->data, handle->bytesPerFrame, (uint32_t *)destAddr, + handle->bytesPerFrame, (uint32_t)handle->count * handle->bytesPerFrame, transfer->dataSize, + kEDMA_MemoryToPeripheral); + + if (i == (loopTransferCount - 1U)) + { + EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[0U]); + EDMA_TcdEnableInterrupts(¤tTCD[tcdIndex], (uint32_t)kEDMA_MajorInterruptEnable); + handle->state = (uint32_t)kSAI_BusyLoopTransfer; + break; + } + else + { + EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[tcdIndex + 1U]); + EDMA_TcdEnableInterrupts(¤tTCD[tcdIndex], (uint32_t)kEDMA_MajorInterruptEnable); + } + + tcdIndex = tcdIndex + 1U; + } + + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, ¤tTCD[0]); + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Tx clock */ + SAI_TxEnable(base, true); + + /* Enable the channel FIFO */ + base->TCR3 |= I2S_TCR3_TCE(1UL << handle->channel); + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SAI loop transfer using eDMA. + * + * note This function support loop transfer only,such as A->B->...->A, application must be aware of + * that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in + * sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. + * This function support one sai channel only. + * + * Once the loop transfer start, application can use function SAI_TransferAbortReceiveEDMA to stop the loop transfer. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). + * param loopTransferCount the counts of xfer array. + * retval kStatus_Success Start a SAI eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + */ +status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert((handle != NULL) && (xfer != NULL)); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + sai_transfer_t *transfer = xfer; + edma_tcd_t *currentTCD = STCD_ADDR(handle->tcd); + uint32_t tcdIndex = 0U; + + /* Change the state of handle */ + handle->state = (uint32_t)kSAI_Busy; + + for (uint32_t i = 0U; i < loopTransferCount; i++) + { + transfer = &xfer[i]; + + if ((tcdIndex >= (uint32_t)SAI_XFER_QUEUE_SIZE) || (xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Update the queue state */ + handle->transferSize[tcdIndex] = transfer->dataSize; + handle->saiQueue[tcdIndex].data = transfer->data; + handle->saiQueue[tcdIndex].dataSize = transfer->dataSize; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (uint32_t *)srcAddr, handle->bytesPerFrame, transfer->data, handle->bytesPerFrame, + (uint32_t)handle->count * handle->bytesPerFrame, transfer->dataSize, + kEDMA_PeripheralToMemory); + + if (i == (loopTransferCount - 1U)) + { + EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[0U]); + EDMA_TcdEnableInterrupts(¤tTCD[tcdIndex], (uint32_t)kEDMA_MajorInterruptEnable); + handle->state = (uint32_t)kSAI_BusyLoopTransfer; + break; + } + else + { + EDMA_TcdSetTransferConfig(¤tTCD[tcdIndex], &config, ¤tTCD[tcdIndex + 1U]); + EDMA_TcdEnableInterrupts(¤tTCD[tcdIndex], (uint32_t)kEDMA_MajorInterruptEnable); + } + + tcdIndex = tcdIndex + 1U; + } + + EDMA_InstallTCD(handle->dmaHandle->base, handle->dmaHandle->channel, ¤tTCD[0]); + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + /* Enable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable the channel FIFO */ + base->RCR3 |= I2S_RCR3_RCE(1UL << handle->channel); + + /* Enable SAI Rx clock */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts a SAI transfer using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable the channel FIFO */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + + /* Disable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Tx */ + SAI_TxEnable(base, false); + + /* If Tx is disabled, reset the FIFO pointer and clear error flags */ + if ((base->TCSR & I2S_TCSR_TE_MASK) == 0UL) + { + base->TCSR |= (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK); + base->TCSR &= ~I2S_TCSR_SR_MASK; + } + + /* Handle the queue index */ + (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + + /* Set the handle state */ + handle->state = (uint32_t)kSAI_Idle; +} + +/*! + * brief Aborts a SAI receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable the channel FIFO */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + + /* Disable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Rx */ + SAI_RxEnable(base, false); + + /* If Rx is disabled, reset the FIFO pointer and clear error flags */ + if ((base->RCSR & I2S_RCSR_RE_MASK) == 0UL) + { + base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK); + base->RCSR &= ~I2S_RCSR_SR_MASK; + } + + /* Handle the queue index */ + (void)memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1U) % (uint8_t)SAI_XFER_QUEUE_SIZE; + + /* Set the handle state */ + handle->state = (uint32_t)kSAI_Idle; +} + +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Abort the current transfer */ + SAI_TransferAbortSendEDMA(base, handle); + + /* Clear all the internal information */ + (void)memset(handle->tcd, 0, sizeof(handle->tcd)); + (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue)); + (void)memset(handle->transferSize, 0, sizeof(handle->transferSize)); + + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceiveEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Abort the current transfer */ + SAI_TransferAbortReceiveEDMA(base, handle); + + /* Clear all the internal information */ + (void)memset(handle->tcd, 0, sizeof(handle->tcd)); + (void)memset(handle->saiQueue, 0, sizeof(handle->saiQueue)); + (void)memset(handle->transferSize, 0, sizeof(handle->transferSize)); + + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Gets byte count sent by SAI. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param count Bytes count sent by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + + if (handle->state != (uint32_t)kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} + +/*! + * brief Gets byte count received by SAI. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param count Bytes count received by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + + if (handle->state != (uint32_t)kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} + +/*! + * @rief Gets valid transfer slot. + * + * This function can be used to query the valid transfer request slot that the application can submit. + * It should be called in the critical section, that means the application could call it in the corresponding callback + * function or disable IRQ before calling it in the application, otherwise, the returned value may not correct. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * retval valid slot count that application submit. + */ +uint32_t SAI_TransferGetValidTransferSlotsEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + uint32_t validSlot = 0U; + + for (uint32_t i = 0U; i < (uint32_t)SAI_XFER_QUEUE_SIZE; i++) + { + if (handle->saiQueue[i].data == NULL) + { + validSlot++; + } + } + + return validSlot; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai_edma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai_edma.h new file mode 100644 index 0000000000..82d7fb0f22 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_sai_edma.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_SAI_EDMA_H_ +#define FSL_SAI_EDMA_H_ + +#include "fsl_edma.h" +#include "fsl_sai.h" + +/*! + * @addtogroup sai_edma SAI EDMA Driver + * @ingroup sai + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) /*!< Version 2.7.0 */ +/*@}*/ + +typedef struct sai_edma_handle sai_edma_handle_t; + +/*! @brief SAI eDMA transfer callback function for finish and error */ +typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); + +/*!@brief sai interleave type */ +typedef enum _sai_edma_interleave +{ + kSAI_EDMAInterleavePerChannelSample = + 0U, /*!< SAI data interleave per channel sample + * --------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | LEFT CHANNEL | RIGHT CHANNEL | ....| + * --------------------------------------------------------------------------------------------------- + */ + kSAI_EDMAInterleavePerChannelBlock = + 1U, /*!< SAI data interleave per channel block + * -------------------------------------------------------------------------------------------------------- + * |LEFT CHANNEL | LEFT CHANNEL | LEFT CHANNEL | ... | RIGHT CHANNEL | RIGHT CHANNEL | RIGHT CHANNEL | ...| + * -------------------------------------------------------------------------------------------------------- + */ +} sai_edma_interleave_t; + +/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ +struct sai_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channelMask; /*!< Enabled channel mask value, reference _sai_channel_mask */ + uint8_t channelNums; /*!< total enabled channel nums */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + sai_edma_interleave_t interleaveType; /*!< Transfer interleave type */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param txDmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_edma_callback_t callback, + void *userData, + edma_handle_t *txDmaHandle); + +/*! + * @brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param rxDmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle); + +/*! + * @brief Initializes the SAI interleave type. + * + * This function initializes the SAI DMA handle member interleaveType, it shall be called only when application would + * like to use type kSAI_EDMAInterleavePerChannelBlock, since the default interleaveType is + * kSAI_EDMAInterleavePerChannelSample always + * + * @param handle SAI eDMA handle pointer. + * @param interleaveType Multi channel interleave type. + */ +void SAI_TransferSetInterleaveType(sai_edma_handle_t *handle, sai_edma_interleave_t interleaveType); + +/*! + * @brief Configures the SAI Tx. + * + * @note SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. + * To activate the multi-channel transfer enable SAI channels by filling the channelMask + * of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine + * mode by assigning kSAI_FifoCombineModeEnabledOnWrite to the fifoCombine member of sai_fifo_combine_t + * which is a member of sai_transceiver_t. + * This is an example of multi-channel data transfer configuration step. + * @code + * sai_transceiver_t config; + * SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask); + * config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnWrite; + * SAI_TransferTxSetConfigEDMA(I2S0, &edmaHandle, &config); + * @endcode + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig); + +/*! + * @brief Configures the SAI Rx. + * + * @note SAI eDMA supports data transfer in a multiple SAI channels if the FIFO Combine feature is supported. + * To activate the multi-channel transfer enable SAI channels by filling the channelMask + * of sai_transceiver_t with the corresponding values of _sai_channel_mask enum, enable the FIFO Combine + * mode by assigning kSAI_FifoCombineModeEnabledOnRead to the fifoCombine member of sai_fifo_combine_t + * which is a member of sai_transceiver_t. + * This is an example of multi-channel data transfer configuration step. + * @code + * sai_transceiver_t config; + * SAI_GetClassicI2SConfig(&config, kSAI_WordWidth16bits, kSAI_Stereo, kSAI_Channel0Mask|kSAI_Channel1Mask); + * config.fifo.fifoCombine = kSAI_FifoCombineModeEnabledOnRead; + * SAI_TransferRxSetConfigEDMA(I2S0, &edmaHandle, &config); + * @endcode + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig); + +/*! + * @brief Performs a non-blocking SAI transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * This function support multi channel transfer, + * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation + * on channel numbers + * 2. for the sai IP not support fifo combine mode, sai edma provide another solution which using + * EDMA modulo feature, but support 2 or 4 channels only. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SAI receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * This function support multi channel transfer, + * 1. for the sai IP support fifo combine mode, application should enable the fifo combine mode, no limitation + * on channel numbers + * 2. for the sai IP not support fifo combine mode, sai edma provide another solution which using + * EDMA modulo feature, but support 2 or 4 channels only. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SAI loop transfer using eDMA. + * + * @note This function support loop transfer only,such as A->B->...->A, application must be aware of + * that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in + * sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. + * This function support one sai channel only. + * + * Once the loop transfer start, application can use function SAI_TransferAbortSendEDMA to stop the loop transfer. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). + * @param loopTransferCount the counts of xfer array. + * @retval kStatus_Success Start a SAI eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + */ +status_t SAI_TransferSendLoopEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_t *xfer, + uint32_t loopTransferCount); + +/*! + * @brief Performs a non-blocking SAI loop transfer using eDMA. + * + * @note This function support loop transfer only,such as A->B->...->A, application must be aware of + * that the more counts of the loop transfer, then more tcd memory required, as the function use the tcd pool in + * sai_edma_handle_t, so application could redefine the SAI_XFER_QUEUE_SIZE to determine the proper TCD pool size. + * This function support one sai channel only. + * + * Once the loop transfer start, application can use function SAI_TransferAbortReceiveEDMA to stop the loop transfer. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure, should be a array with elements counts >=1(loopTransferCount). + * @param loopTransferCount the counts of xfer array. + * @retval kStatus_Success Start a SAI eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + */ +status_t SAI_TransferReceiveLoopEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_t *xfer, + uint32_t loopTransferCount); + +/*! + * @brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSendEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceiveEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI transfer using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SAI. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param count Bytes count sent by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SAI. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param count Bytes count received by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets valid transfer slot. + * + * This function can be used to query the valid transfer request slot that the application can submit. + * It should be called in the critical section, that means the application could call it in the corresponding callback + * function or disable IRQ before calling it in the application, otherwise, the returned value may not correct. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @retval valid slot count that application submit. + */ +uint32_t SAI_TransferGetValidTransferSlotsEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma.c new file mode 100644 index 0000000000..d1560d46b6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma.c @@ -0,0 +1,159 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_smartdma" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +typedef void (*smartdma_func_t)(void); + +#define SMARTDMA_HANDSHAKE_EVENT 0U +#define SMARTDMA_HANDSHAKE_ENABLE 1U +#define SMARTDMA_MASK_RESP 2U +#define SMARTDMA_ENABLE_AHBBUF 3U +#define SMARTDMA_ENABLE_GPISYNCH 4U + +#if defined(SMARTDMA0) && !(defined(SMARTDMA)) +#define SMARTDMA SMARTDMA0 +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +static smartdma_func_t *s_smartdmaApiTable; +static smartdma_callback_t s_smartdmaCallback; +static void *s_smartdmaCallbackParam; +static smartdma_param_t s_smartdmaParam; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ +/*! + * brief Initialize the SMARTDMA. + * + * param apiMemAddr The address firmware will be copied to. + * param firmware The firmware to use. + * param firmwareSizeByte Size of firmware. + */ +void SMARTDMA_Init(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte) +{ + SMARTDMA_InitWithoutFirmware(); + SMARTDMA_InstallFirmware(apiMemAddr, firmware, firmwareSizeByte); +} + +/*! + * brief Initialize the SMARTDMA. + * + * This function is similar with SMARTDMA_Init, the difference is this function + * does not install the firmware, the firmware could be installed using + * SMARTDMA_InstallFirmware. + */ +void SMARTDMA_InitWithoutFirmware(void) +{ + /* Clear Smart DMA RAM */ + RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_Smartdma); +} + +/*! + * @brief Install the firmware. + * + * param apiMemAddr The address firmware will be copied to. + * param firmware The firmware to use. + * param firmwareSizeByte Size of firmware. + */ +void SMARTDMA_InstallFirmware(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte) +{ + (void)memcpy((void *)(uint8_t *)apiMemAddr, firmware, firmwareSizeByte); + SMARTDMA->CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); + s_smartdmaApiTable = (smartdma_func_t *)apiMemAddr; +} + +/*! + * brief Install the complete callback function.. + * + * param callback The callback called when smartdma program finished. + */ +void SMARTDMA_InstallCallback(smartdma_callback_t callback, void *param) +{ + s_smartdmaCallback = callback; + s_smartdmaCallbackParam = param; +} + +/*! + * brief Boot the SMARTDMA to run program. + * + * param apiIndex Index of the API to call. + * param pParam Pointer to the parameter allocated by caller. + * param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. + */ +void SMARTDMA_Boot(uint32_t apiIndex, void *pParam, uint8_t mask) +{ + SMARTDMA->ARM2EZH = (uint32_t)(uint8_t *)pParam | (uint32_t)mask; + SMARTDMA->BOOTADR = (uint32_t)(s_smartdmaApiTable[apiIndex]); + SMARTDMA->CTRL = 0xC0DE0011U | (0U << SMARTDMA_MASK_RESP) | (0U << SMARTDMA_ENABLE_AHBBUF); /* BOOT */ +}; + +/* + * brief Copy SMARTDMA params and Boot to run program. + * + * This function is similar with SMARTDMA_Boot, the only difference + * is, this function copies the *pParam to a local variable, upper layer + * can free the pParam's memory before the SMARTDMA execution finished, + * for example, upper layer can define the param as a local variable. + * + * param apiIndex Index of the API to call. + * param pParam Pointer to the parameter. + * param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. + * note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_Boot1(uint32_t apiIndex, const smartdma_param_t *pParam, uint8_t mask) +{ + (void)memcpy(&s_smartdmaParam, pParam, sizeof(smartdma_param_t)); + SMARTDMA_Boot(apiIndex, &s_smartdmaParam, mask); +} + +/*! + * brief Deinitialize the SMARTDMA. + */ +void SMARTDMA_Deinit(void) +{ + SMARTDMA->CTRL = 0xC0DE0000U; + CLOCK_DisableClock(kCLOCK_Smartdma); +} + +/*! + * brief Reset the SMARTDMA. + */ +void SMARTDMA_Reset(void) +{ + RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); + SMARTDMA->CTRL = (0xC0DE0000U | (1U << SMARTDMA_ENABLE_GPISYNCH)); +} + +/*! + * brief SMARTDMA IRQ. + */ +void SMARTDMA_HandleIRQ(void) +{ + if (NULL != s_smartdmaCallback) + { + s_smartdmaCallback(s_smartdmaCallbackParam); + } +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma.h new file mode 100644 index 0000000000..8741711c9c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma.h @@ -0,0 +1,136 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_H_ +#define FSL_SMARTDMA_H_ + +#include "fsl_common.h" + +#if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) +#include "fsl_smartdma_rt500.h" +#elif defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || \ + defined(MCXN547_cm33_core0_SERIES) || defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || \ + defined(MCXN946_cm33_core1_SERIES) || defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || \ + defined(MCXN236_SERIES) || defined(MCXN235_SERIES) +#include "fsl_smartdma_mcxn.h" +#else +#error "Device not supported" +#endif + +/*! + * @addtogroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SMARTDMA driver version */ +#define FSL_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 9, 1)) +/*@}*/ + +/*! @brief Callback function prototype for the smartdma driver. */ +typedef void (*smartdma_callback_t)(void *param); + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Initialize the SMARTDMA. + * + * @param apiMemAddr The address firmware will be copied to. + * @param firmware The firmware to use. + * @param firmwareSizeByte Size of firmware. + * @deprecated Do not use this function. It has been superceded by + * @ref SMARTDMA_InitWithoutFirmware and @ref SMARTDMA_InstallFirmware. + */ +void SMARTDMA_Init(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte); + +/*! + * @brief Initialize the SMARTDMA. + * + * This function is similar with @ref SMARTDMA_Init, the difference is this function + * does not install the firmware, the firmware could be installed using + * @ref SMARTDMA_InstallFirmware. + */ +void SMARTDMA_InitWithoutFirmware(void); + +/*! + * @brief Install the firmware. + * + * @param apiMemAddr The address firmware will be copied to. + * @param firmware The firmware to use. + * @param firmwareSizeByte Size of firmware. + * @note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_InstallFirmware(uint32_t apiMemAddr, const void *firmware, uint32_t firmwareSizeByte); + +/*! + * @brief Install the complete callback function. + * + * @param callback The callback called when smartdma program finished. + * @param param Parameter for the callback. + * @note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_InstallCallback(smartdma_callback_t callback, void *param); + +/*! + * @brief Boot the SMARTDMA to run program. + * + * @param apiIndex Index of the API to call. + * @param pParam Pointer to the parameter allocated by caller. + * @param mask Value set to register SMARTDMA->ARM2EZH[0:1]. + * @note Only call this function when SMARTDMA is not busy. + * @note The memory *pParam shall not be freed before the SMARTDMA function finished. + */ +void SMARTDMA_Boot(uint32_t apiIndex, void *pParam, uint8_t mask); + +/*! + * @brief Copy SMARTDMA params and Boot to run program. + * + * This function is similar with @ref SMARTDMA_Boot, the only difference + * is, this function copies the *pParam to a local variable, upper layer + * can free the pParam's memory before the SMARTDMA execution finished, + * for example, upper layer can define the param as a local variable. + * + * @param apiIndex Index of the API to call. + * @param pParam Pointer to the parameter. + * @param mask Value set to SMARTDMA_ARM2SMARTDMA[0:1]. + * @note Only call this function when SMARTDMA is not busy. + */ +void SMARTDMA_Boot1(uint32_t apiIndex, const smartdma_param_t *pParam, uint8_t mask); + +/*! + * @brief Deinitialize the SMARTDMA. + */ +void SMARTDMA_Deinit(void); + +/*! + * @brief Reset the SMARTDMA. + */ +void SMARTDMA_Reset(void); + +/*! + * @brief SMARTDMA IRQ. + */ +void SMARTDMA_HandleIRQ(void); + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* FSL_SMARTDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_mcxn.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_mcxn.c new file mode 100644 index 0000000000..8879018792 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_mcxn.c @@ -0,0 +1,445 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +#if defined(MCXN546_cm33_core0_SERIES) || defined(MCXN546_cm33_core1_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \ + defined(MCXN547_cm33_core1_SERIES) || defined(MCXN946_cm33_core0_SERIES) || defined(MCXN946_cm33_core1_SERIES) || \ + defined(MCXN947_cm33_core0_SERIES) || defined(MCXN947_cm33_core1_SERIES) || defined(MCXN236_SERIES) + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x24U, 0x00U, 0x00U, 0x04U, 0x18U, 0x01U, 0x00U, 0x04U, 0xC8U, 0x02U, 0x00U, 0x04U, 0xF0U, 0x01U, 0x00U, 0x04U, + 0x7CU, 0x03U, 0x00U, 0x04U, 0xACU, 0x08U, 0x00U, 0x04U, 0x10U, 0x0EU, 0x00U, 0x04U, 0x38U, 0x10U, 0x00U, 0x04U, + 0xC0U, 0x12U, 0x00U, 0x04U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, + 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x08U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x00U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x01U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x02U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x03U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x04U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x05U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x06U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x02U, 0xC0U, 0x25U, 0x07U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xF2U, 0x01U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, + 0x0CU, 0x88U, 0x30U, 0x00U, 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0x07U, 0x07U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x06U, 0x00U, 0xC4U, 0x01U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, + 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x02U, 0xC0U, 0x25U, 0x00U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x01U, 0x11U, 0x10U, 0x40U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x02U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x02U, 0xC0U, 0x55U, 0x03U, 0x01U, 0x08U, 0x1CU, 0xFFU, 0x01U, 0x0CU, 0x1CU, 0xFFU, + 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0x08U, 0x11U, 0x08U, 0x20U, 0x00U, 0x02U, 0xC0U, 0x25U, 0x04U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x02U, 0xC0U, 0x35U, 0x05U, 0x11U, 0x10U, 0x40U, 0x00U, 0x02U, 0xC0U, 0x45U, 0x06U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x02U, 0xC0U, 0x55U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x03U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x33U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x06U, 0x18U, 0x10U, 0x00U, + 0x10U, 0x04U, 0x14U, 0x05U, 0x00U, 0x08U, 0x26U, 0x05U, 0x00U, 0x0CU, 0x0CU, 0x01U, 0x0CU, 0x88U, 0x30U, 0x00U, + 0x00U, 0x1CU, 0x0EU, 0x04U, 0x0CU, 0xDCU, 0x21U, 0x00U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x06U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, 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0x02U, 0xC0U, 0x45U, 0x06U, 0x01U, 0x08U, 0x14U, 0xFFU, + 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, + 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, + 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, + 0x02U, 0xC0U, 0x25U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x02U, 0xC0U, 0x35U, 0x00U, + 0x02U, 0xC0U, 0x45U, 0x01U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x02U, 0x02U, 0xC0U, 0x35U, 0x03U, + 0x02U, 0xC0U, 0x45U, 0x04U, 0x01U, 0x08U, 0x14U, 0xFFU, 0x01U, 0x0CU, 0x14U, 0xFFU, 0x01U, 0x10U, 0x14U, 0xFFU, + 0x01U, 0x14U, 0x14U, 0xFFU, 0x11U, 0x88U, 0x21U, 0x28U, 0x11U, 0x0CU, 0x30U, 0x08U, 0x10U, 0x88U, 0x30U, 0x58U, + 0x0DU, 0xCCU, 0x60U, 0x48U, 0x11U, 0x10U, 0x40U, 0x08U, 0x10U, 0xCCU, 0x40U, 0x50U, 0x0DU, 0x10U, 0x61U, 0x50U, + 0x11U, 0x14U, 0x50U, 0x08U, 0x10U, 0x10U, 0x51U, 0x48U, 0x02U, 0xC0U, 0x25U, 0x05U, 0x02U, 0xC0U, 0x35U, 0x06U, + 0x02U, 0xC0U, 0x45U, 0x07U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x5AU, 0x2AU, 0x00U}; + +const uint32_t s_smartdmaDisplayFirmwareSize = sizeof(s_smartdmaDisplayFirmware); + +const uint8_t s_smartdmaCameraFirmware[] = { + 0x21U, 0x00U, 0x00U, 0x04U, 0xE1U, 0x00U, 0x00U, 0x04U, 0xE1U, 0x02U, 0x00U, 0x04U, 0x00U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00U, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21U, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25U, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x04U, 0xF4U, 0x0FU, + 0x1CU, 0x36U, 0xD0U, 0x04U, 0x10U, 0x40U, 0xE8U, 0x20U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x9FU, 0x00U, 0x00U, 0x04U, + 0xBBU, 0x00U, 0x00U, 0x04U, 0x02U, 0xC4U, 0x08U, 0x01U, 0x83U, 0x00U, 0x00U, 0x04U, 0x18U, 0xECU, 0x02U, 0xC0U, + 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x01U, 0x8CU, 0x05U, 0x01U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x05U, 0x44U, 0x00U, 0x33U, 0x83U, 0x00U, 0x00U, 0x04U, 0x18U, 0xCCU, 0x00U, 0x20U, 0x18U, 0xCCU, 0x00U, 0x21U, + 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x18U, 0x20U, 0x02U, 0xF2U, 0x83U, 0x00U, 0x00U, 0x04U, + 0x70U, 0x47U, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x01U, 0x8CU, 0x05U, 0x03U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00U, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21U, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25U, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x08U, 0x14U, 0x00U, + 0x00U, 0x14U, 0x04U, 0x00U, 0x1CU, 0x36U, 0xD0U, 0x04U, 0x0DU, 0x80U, 0xF7U, 0x0FU, 0x18U, 0xECU, 0x02U, 0xC2U, + 0x67U, 0x01U, 0x00U, 0x04U, 0x87U, 0x01U, 0x00U, 0x04U, 0x08U, 0x76U, 0xC7U, 0x01U, 0x02U, 0xC4U, 0x08U, 0x01U, + 0x18U, 0x20U, 0x02U, 0xF2U, 0x18U, 0xECU, 0x02U, 0xC0U, 0x00U, 0x08U, 0x14U, 0x00U, 0x00U, 0x14U, 0x04U, 0x00U, + 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x01U, 0x8CU, 0x05U, 0x03U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x47U, 0x01U, 0x00U, 0x04U, 0x18U, 0xCCU, 0x00U, 0x20U, 0x18U, 0xCCU, 0x00U, 0x21U, 0x00U, 0x14U, 0x04U, 0x00U, + 0x0DU, 0x88U, 0xF4U, 0x1FU, 0x01U, 0x90U, 0x05U, 0x02U, 0x0EU, 0x82U, 0xF4U, 0x00U, 0x20U, 0x04U, 0x04U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xE4U, 0x01U, 0x20U, 0x04U, 0x14U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xD4U, 0x02U, + 0x20U, 0x04U, 0x24U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0xC4U, 0x03U, + 0x20U, 0x04U, 0x34U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0xB4U, 0x04U, 0x20U, 0x04U, 0x44U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0xA4U, 0x05U, 0x20U, 0x04U, 0x54U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x94U, 0x06U, 0x20U, 0x04U, 0x64U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x84U, 0x07U, 0x20U, 0x04U, 0x74U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, + 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x74U, 0x08U, 0x20U, 0x04U, 0x84U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x64U, 0x09U, 0x20U, 0x04U, 0x94U, 0x00U, + 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x54U, 0x0AU, + 0x20U, 0x04U, 0xA4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x44U, 0x0BU, + 0x20U, 0x04U, 0xB4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0x34U, 0x0CU, 0x20U, 0x04U, 0xC4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x0EU, 0x82U, 0x24U, 0x0DU, 0x20U, 0x04U, 0xD4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x0EU, 0x82U, 0x14U, 0x0EU, 0x20U, 0x04U, 0xE4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, + 0x25U, 0x44U, 0x00U, 0x33U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x0EU, 0x82U, 0x04U, 0x0FU, + 0x20U, 0x04U, 0xF4U, 0x00U, 0x22U, 0x00U, 0x15U, 0x00U, 0x21U, 0x8CU, 0x05U, 0x03U, 0x25U, 0x44U, 0x00U, 0x33U, + 0x38U, 0xECU, 0x02U, 0x21U, 0x38U, 0xECU, 0x02U, 0x22U, 0x06U, 0x88U, 0x14U, 0x00U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x47U, 0x01U, 0x00U, 0x04U, 0x70U, 0x47U, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, 0x00U, 0xBFU, + 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x04U, 0x18U, 0x04U, 0x33U, 0x10U, 0x18U, 0x68U, 0x02U, 0x10U, 0x18U, 0x60U, 0x02U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x01U, 0x68U, 0x07U, 0x01U, 0x01U, 0x6CU, 0x07U, 0x01U, 0x06U, 0x74U, 0x47U, 0x00U, + 0x00U, 0x88U, 0x00U, 0x00U, 0x01U, 0x92U, 0x6CU, 0xDBU, 0x18U, 0x64U, 0x02U, 0x20U, 0x18U, 0x64U, 0x02U, 0x21U, + 0x18U, 0x64U, 0x02U, 0x22U, 0x18U, 0x64U, 0x02U, 0x23U, 0x18U, 0x64U, 0x02U, 0x24U, 0x18U, 0x64U, 0x02U, 0x25U, + 0x18U, 0x64U, 0x02U, 0x26U, 0x18U, 0x64U, 0x02U, 0x27U, 0x18U, 0x64U, 0x02U, 0xD2U, 0x00U, 0x04U, 0xF4U, 0x0FU, + 0x1CU, 0x36U, 0xD0U, 0x04U, 0x10U, 0x40U, 0xE8U, 0x20U, 0x18U, 0xECU, 0x02U, 0xC2U, 0x6BU, 0x03U, 0x00U, 0x04U, + 0x8BU, 0x03U, 0x00U, 0x04U, 0x08U, 0xBEU, 0x04U, 0x3CU, 0x82U, 0xC4U, 0x08U, 0x01U, 0x08U, 0x76U, 0x47U, 0x02U, + 0x98U, 0x20U, 0x02U, 0xF2U, 0x06U, 0x88U, 0x14U, 0x00U, 0x18U, 0xECU, 0x02U, 0xC0U, 0x18U, 0xECU, 0x02U, 0xC1U, + 0x01U, 0x8CU, 0x05U, 0x01U, 0x00U, 0x08U, 0x04U, 0x00U, 0x00U, 0x10U, 0x04U, 0x00U, 0x18U, 0x20U, 0x02U, 0xF2U, + 0x05U, 0x44U, 0x00U, 0x33U, 0x43U, 0x03U, 0x00U, 0x04U, 0x18U, 0xECU, 0x02U, 0xC1U, 0x06U, 0x10U, 0x15U, 0x00U, + 0x08U, 0x3EU, 0x05U, 0x05U, 0xB8U, 0xECU, 0x02U, 0xC2U, 0x08U, 0x3EU, 0x05U, 0x19U, 0xB8U, 0xECU, 0x02U, 0x22U, + 0x00U, 0x08U, 0x04U, 0x00U, 0x43U, 0x03U, 0x00U, 0x04U, 0x70U, 0x47U, 0x00U, 0x00, +}; + +const uint32_t s_smartdmaCameraFirmwareSize = sizeof(s_smartdmaCameraFirmware); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void SMARTDMA_IRQHandler(void); +void SMARTDMA_IRQHandler(void) +{ + SMARTDMA_HandleIRQ(); +} + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_mcxn.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_mcxn.h new file mode 100644 index 0000000000..ceadc88415 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_mcxn.h @@ -0,0 +1,136 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_MCXN_H_ +#define FSL_SMARTDMA_MCXN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup smartdma_mcxn MCXN SMARTDMA Firmware + * @ingroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(MCXN236_SERIES) || defined(MCXN235_SERIES) +#define SMARTDMA_USE_FLEXIO_SHIFTER_DMA 1 +#endif + +/*! @brief The firmware used for display. */ +extern const uint8_t s_smartdmaDisplayFirmware[]; + +/*! @brief The s_smartdmaDisplayFirmware firmware memory address. */ +#define SMARTDMA_DISPLAY_MEM_ADDR 0x04000000U + +/*! @brief Size of s_smartdmaDisplayFirmware */ +#define SMARTDMA_DISPLAY_FIRMWARE_SIZE (s_smartdmaDisplayFirmwareSize) + +/*! @brief Size of s_smartdmaDisplayFirmware */ +extern const uint32_t s_smartdmaDisplayFirmwareSize; + +/*! @brief The firmware used for camera. */ +extern const uint8_t s_smartdmaCameraFirmware[]; + +/*! @brief The s_smartdmaCameraFirmware firmware memory address. */ +#define SMARTDMA_CAMERA_MEM_ADDR 0x04000000U + +/*! @brief Size of s_smartdmacameraFirmware */ +#define SMARTDMA_CAMERA_FIRMWARE_SIZE (s_smartdmaCameraFirmwareSize) + +/*! @brief Size of s_smartdmacameraFirmware */ +extern const uint32_t s_smartdmaCameraFirmwareSize; + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_RGB565To888, /*!< Convert RGB565 to RGB888 and save to output memory, use parameter + smartdma_rgb565_rgb888_param_t. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to FlexIO, use + parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ +}; + +/*! + * @brief Parameter for FlexIO MCULCD + */ +typedef struct _smartdma_flexio_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_flexio_mculcd_param_t; + +/*! + * @brief Parameter for RGB565To888 + */ +typedef struct _smartdma_rgb565_rgb888_param +{ + uint32_t *inBuf; + uint32_t *outBuf; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_rgb565_rgb888_param_t; + +/*! + * @brief The API index when using s_smartdmaCameraFirmware + */ +enum _smartdma_camera_api +{ + /*! Save whole camera frame to buffer, only supports QVGA(320x240), QQVGA(160x120). */ + kSMARTDMA_FlexIO_CameraWholeFrame = 0U, + /*! Save only first 1/16 of camera frame to buffer, only supports QVGA(320x240). */ + kSMARTDMA_FlexIO_CameraDiv16Frame = 1U, +}; + +/*! + * @brief Parameter for camera + */ +typedef struct _smartdma_camera_param +{ + uint32_t *smartdma_stack; /*!< Stack used by SMARTDMA, shall be at least 64 bytes. */ + uint32_t *p_buffer; /*!< Buffer to store the received camera data. */ +} smartdma_camera_param_t; + +/*! + * @brief Parameter for all supported APIs. + */ +typedef union +{ + smartdma_flexio_mculcd_param_t flexioMcuLcdParam; /*!< Parameter for flexio MCULCD. */ + smartdma_rgb565_rgb888_param_t rgb565_rgb888Param; /*!< Parameter for RGB565_RGB888 convertion. */ + smartdma_camera_param_t cameraParam; /*!< Parameter for camera. */ +} smartdma_param_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* FSL_SMARTDMA_MCXN_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_prv.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_prv.h new file mode 100644 index 0000000000..f297aa0687 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_prv.h @@ -0,0 +1,6058 @@ +/* + * @brief IOH Architecture B mnemonics + * + * @note + * Copyright 2014, 2019, NXP + * All rights reserved. + * + * @par + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * LPC products. This software is supplied "AS IS" without any warranties of + * any kind, and NXP Semiconductors and its licensor disclaim any and + * all warranties, express or implied, including all implied warranties of + * merchantability, fitness for a particular purpose and non-infringement of + * intellectual property rights. NXP Semiconductors assumes no responsibility + * or liability for the use of the software, conveys no license or rights under any + * patent, copyright, mask work right, or any other intellectual property rights in + * or to any products. NXP Semiconductors reserves the right to make changes + * in the software without notification. NXP Semiconductors also makes no + * representation or warranty that such application will be suitable for the + * specified use without further testing or modification. + * + * @par + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' and its + * licensor's relevant copyrights in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. + */ + +#ifndef FSL_SMARTDMA_PRV_H_ +#define FSL_SMARTDMA_PRV_H_ + +#include "fsl_common.h" + +#define SMARTDMA_INPUT_SOURCE_0 0 +#define SMARTDMA_INPUT_SOURCE_1 1 +#define SMARTDMA_INPUT_SOURCE_2 2 +#define SMARTDMA_INPUT_SOURCE_3 3 +#define SMARTDMA_INPUT_SOURCE_4 4 +#define SMARTDMA_INPUT_SOURCE_5 5 +#define SMARTDMA_INPUT_SOURCE_6 6 +#define SMARTDMA_INPUT_SOURCE_7 7 + +#define BS0(c) (c << 8) +#define BS1(c) (c << 11) +#define BS2(c) (c << 14) +#define BS3(c) (c << 17) +#define BS4(c) (c << 20) +#define BS5(c) (c << 23) +#define BS6(c) (c << 26) +#define BS7(c) (c << 29) + +#define SMARTDMA_DISABLE_EMERGENCY_BIT 8 + +#define SMARTDMA_HANDSHAKE_EVENT 0 +#define SMARTDMA_HANDSHAKE_ENABLE 1 + +#define SMARTDMA_MASK_RESP 2 +#define SMARTDMA_ENABLE_AHBBUF 3 +#define SMARTDMA_ENABLE_GPISYNCH 4 + +typedef enum +{ + ezh_trap_low = 1, + ezh_trap_high = 0 +} trap_pol; + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* SMARTDMA ARCH B */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define R0 0x00 +#define R1 0x01 +#define R2 0x02 +#define R3 0x03 +#define R4 0x04 +#define R5 0x05 +#define R6 0x06 +#define R7 0x07 +#define GPO 0x08 +#define GPD 0x09 +#define CFS 0x0a +#define CFM 0x0b +#define SP 0x0c +#define PC 0x0d +#define GPI 0x0e +#define RA 0x0f + +/* Conditional Flags */ +#define EU 0x0 +#define ZE 0x1 +#define NZ 0x2 +#define PO 0x3 +#define NE 0x4 +#define AZ 0x5 +#define ZB 0x6 +#define CA 0x7 +#define NC 0x8 +#define CZ 0x9 +#define SPO 0xa +#define SNE 0xb +#define NBS 0xc +#define NEX 0xd +#define BS 0xe +#define EX 0xf + +#define UNS 0xa +#define NZS 0xb + +#define VECT0 0x1 +#define VECT1 0x2 +#define VECT2 0x4 +#define VECT3 0x8 +#define VECT4 0x10 +#define VECT5 0x20 +#define VECT6 0x40 +#define VECT7 0x80 + +/* Bit Slice Mux cfg */ + +#define BS_1 0 +#define BS_RISE 1 +#define BS_FALL 2 +#define BS_CHANGE 3 +#define BS_SIG 4 +#define BS_SIGN 5 +#define BS_0 6 +#define BS_EVENT 7 + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Unconditional OpCodes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_GOSUB(a30) DCD 0x03 + a30 +#define E_NOP DCD 0x12 +#define E_INT_TRIGGER(x24) DCD 0x14 + (x24 << 8) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_GOTO */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* the pre-processor/linker will calculate it this way (<< relative not allowed) */ +#define E_GOTO(a21) \ + DCD 0x15 + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_GOTO_REG(raddr) DCD 0x15 + (raddr << 14) + +/* the pre-processor/linker will calculate it this way (<< relative not allowed) */ +#define E_GOTOL(a21) \ + DCD 0x15 + (1 << 10) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_GOTO_REGL(raddr) DCD 0x15 + (raddr << 14) + (1 << 10) + +#define E_COND_GOTO(cond, a21) \ + DCD 0x15 + (cond << 5) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_COND_GOTO_REG(cond, raddr) DCD 0x15 + (raddr << 14) + (cond << 5) + +/* the pre-processor/linker will calculate it this way (<< relative not allowed) */ +#define E_COND_GOTOL(cond, a21) \ + DCD 0x15 + (1 << 10) + (cond << 5) + (1 << 9) + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + 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a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + \ + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + a21 + +#define E_COND_GOTO_REGL(cond, raddr) DCD 0x15 + (raddr << 14) + (1 << 10) + (cond << 5) +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_MOV */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_MOV(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5) +#define E_MOVS(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU << 5) +#define E_COND_MOV(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5) +#define E_COND_MOVS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond << 5) + +/* Invert */ +#define E_MVN(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (EU << 5) + (1 << 31) +#define E_MVNS(dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (EU << 5) + (1 << 31) +#define E_COND_MVN(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (cond << 5) + (1 << 31) +#define E_COND_MVNS(cond, dest, source) DCD 0x0 + (source << 14) + (dest << 10) + (1 << 9) + (cond << 5) + (1 << 31) + +/* Load Immediate */ +#define E_LOAD_IMM(dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) +#define E_LOAD_IMMS(dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) +#define E_COND_LOAD_IMM(cond, dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) +#define E_COND_LOAD_IMMS(cond, dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + +/* Load Shifted Immediate */ +#define E_LOAD_SIMM(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) +#define E_LOAD_SIMMS(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) +#define E_COND_LOAD_SIMM(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) +#define E_COND_LOAD_SIMMS(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + +/* Load Inverted Immediate */ +#define E_LOAD_IMMN(dest, imm11s) DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + (1 << 31) +#define E_LOAD_IMMNS(dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + (1 << 31) +#define E_COND_LOAD_IMMN(cond, dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + (1 << 31) +#define E_COND_LOAD_IMMNS(cond, dest, imm11s) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + (1 << 31) + +/* Load Shifted then inverted Immediate */ +#define E_LOAD_SIMMN(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) +#define E_LOAD_SIMMNS(dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (EU << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) +#define E_COND_LOAD_SIMMN(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) +#define E_COND_LOAD_SIMMNS(cond, dest, imm11s, sam) \ + DCD 0x0 + (dest << 10) + ((imm11s & 0x7ff) << 20) + (1 << 18) + (1 << 9) + (cond << 5) + ((sam & 0xf) << 14) + \ + (((sam & 0x10) >> 4) << 19) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_AHB_READ Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Ptr PostIncrement (0 means pre-inc) Rdata Dest */ +/* Pointer WData Source Offset UpdatePointer */ +/* SizeWord Signed Access Cond */ + +/* LDR (Load, Load Byte, LoadByteSigned) */ +#define E_LDR(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (1 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRB(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRBS(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (1 << 21) + \ + (EU << 5) + +/* Conditional LDR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_LDR(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (1 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRB(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRBS(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (0 << 20) + (0 << 18) + (1 << 21) + \ + (cond << 5) + +/* With Update Pointer */ +#define E_LDR_PRE(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRB_PRE(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRBS_PRE(dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (EU << 5) +#define E_COND_LDR_PRE(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRB_PRE(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRBS_PRE(cond, dest, source, offset8s) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (cond << 5) + +/* With Update Pointer (Post Increment pointer) */ +#define E_LDR_POST(dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRB_POST(dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (EU << 5) +#define E_LDRBS_POST(dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (EU << 5) +#define E_COND_LDR_POST(cond, dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (1 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRB_POST(cond, dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (0 << 21) + \ + (cond << 5) +#define E_COND_LDRBS_POST(cond, dest, source, offset8s) \ + DCD 0x1 + (1 << 19) + (dest << 10) + (source << 14) + (offset8s << 24) + (1 << 20) + (0 << 18) + (1 << 21) + \ + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_AHB_WRITE Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Ptr PostIncrement (0 means pre-inc) Rdata Dest */ +/* Pointer WData Source offset8s UpdatePointer */ +/* SizeWord Signed Access Cond */ + +/* STR (Load, Load Byte, LoadByteSigned) */ +#define E_STR(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (1 << 18) + (0 << 11) + \ + (EU << 5) +#define E_STRB(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (0 << 18) + (0 << 11) + \ + (EU << 5) + +/* Conditional STR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_STR(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (1 << 18) + (0 << 11) + \ + (cond << 5) +#define E_COND_STRB(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (0 << 10) + (0 << 18) + (0 << 11) + \ + (cond << 5) + +/* With Update Pointer */ +#define E_STR_PRE(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (EU << 5) +#define E_STRB_PRE(raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (EU << 5) +#define E_COND_STR_PRE(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (cond << 5) +#define E_COND_STRB_PRE(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (0 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (cond << 5) + +/* With Update Pointer (Post Increment pointer) */ +#define E_STR_POST(raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (EU << 5) +#define E_STRB_POST(raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (EU << 5) +#define E_COND_STR_POST(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (1 << 18) + (0 << 11) + \ + (cond << 5) +#define E_COND_STRB_POST(cond, raddr, rdata, offset8s) \ + DCD 0x2 + (1 << 19) + (raddr << 14) + (rdata << 20) + (offset8s << 24) + (1 << 10) + (0 << 18) + (0 << 11) + \ + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Stack Operations (built up from E_LDR and E_STR codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Ptr PostIncrement (0 means pre-inc) Rdata Dest */ +/* Pointer WData Source Offset UpdatePointer + */ +/* SizeWord Signed Access Cond */ + +#define E_PUSH(source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (1 << 18) + (0 << 11) + (EU << 5) +#define E_POP(dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (1 << 18) + (0 << 21) + (EU << 5) +#define E_PUSHB(source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (0 << 18) + (0 << 11) + (EU << 5) +#define E_POPB(dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (0 << 21) + (EU << 5) + +#define E_POPBS(dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (1 << 21) + (EU << 5) + +#define E_COND_PUSH(cond, source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (1 << 18) + (0 << 11) + (cond << 5) +#define E_COND_POP(cond, dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (1 << 18) + (0 << 21) + (cond << 5) +#define E_COND_PUSHB(cond, source) \ + DCD 0x2 + (1 << 19) + (SP << 14) + (source << 20) + (1 << 24) + (1 << 10) + (0 << 18) + (0 << 11) + (cond << 5) +#define E_COND_POPB(cond, dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (0 << 21) + (cond << 5) + +#define E_COND_POPBS(cond, dest) \ + DCD 0x1 + (0 << 19) + (dest << 10) + (SP << 14) + ((-1) << 24) + (1 << 20) + (0 << 18) + (1 << 21) + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_PER_READ Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Address Cond */ + +#define E_PER_READ(dest, addr20) DCD 0x4 + (dest << 10) + ((addr20 & 0x000ffffc) << 12) + (EU << 5) +#define E_COND_PER_READ(cond, dest, addr20) DCD 0x4 + (dest << 10) + ((addr20 & 0x000ffffc) << 12) + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_PER_WRITE Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Address Cond */ + +#define E_PER_WRITE(source, addr20) \ + DCD 0x5 + (source << 20) + ((addr20 & 0x000ff000) << 12) + ((addr20 & 0x00000ffc) << 8) + (EU << 5) +#define E_COND_PER_WRITE(cond, source, addr20) \ + DCD 0x5 + (source << 20) + ((addr20 & 0x000ff000) << 12) + ((addr20 & 0x00000ffc) << 8) + (cond << 5) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ADD Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Amount + */ +/* Shift/Rotate Left/Right Flip */ + +/* Add reg to reg */ +#define E_ADD(dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ADDS(dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_ADD(cond, dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ADDS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* Add reg to reg and invert result */ +#define E_ADDN(dest, src1, src2) DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ADDNS(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ADDN(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ADDNS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* Add imm12s to reg */ +#define E_ADD_IMM(dest, src1, imm12s) DCD 0x6 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_ADD_IMMS(dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADD_IMM(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADD_IMMS(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* Add imm12s to reg and invert result */ +#define E_ADDN_IMM(dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ADDN_IMMS(dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADDN_IMM(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADDN_IMMS(cond, dest, src1, imm12s) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* Add reg to reg with Post Shift Left */ +#define E_ADD_LSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADD_LSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADD_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADD_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg and invert result with Post Shift Left */ +#define E_ADDN_LSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ADDN_LSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg with Post Shift Right */ +#define E_ADD_LSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADD_LSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADD_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADD_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg and invert result with Post Shift Right */ +#define E_ADDN_LSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ADDN_LSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg with Post Arith Shift Right */ +#define E_ADD_ASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADD_ASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADD_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADD_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg and invert result with Post Arith Shift Right */ +#define E_ADDN_ASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ADDN_ASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADDN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* Add reg to reg with Post ROR */ +#define E_ADD_ROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADD_RORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADD_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADD_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg and invert result with ROR */ +#define E_ADDN_ROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ADDN_RORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADDN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Add reg to reg with Flip */ +#define E_ADD_F(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_ADD_FS(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADD_F(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_ADD_FS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Flip */ +#define E_ADDN_F(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADDN_FS(dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_F(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FS(cond, dest, src1, src2) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg with Post Shift Left */ +#define E_ADD_FLSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADD_FLSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADD_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADD_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Post Shift Left */ +#define E_ADDN_FLSL(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ADDN_FLSLS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg with Post Shift Right */ +#define E_ADD_FLSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADD_FLSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADD_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADD_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Post Shift Right */ +#define E_ADDN_FLSR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ADDN_FLSRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* Add reg to reg with Post Arith Shift Right */ +#define E_ADD_FASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADD_FASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADD_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADD_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg and invert result with Post Arith Shift Right */ +#define E_ADDN_FASR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ADDN_FASRS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADDN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* Add reg to reg with Post ROR */ +#define E_ADD_FROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADD_FRORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADD_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADD_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* Add reg to reg and invert result with ROR */ +#define E_ADDN_FROR(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ADDN_FRORS(dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADDN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x6 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_SUB Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* sub reg from reg */ +#define E_SUB(dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_SUBS(dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_SUB(cond, dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_SUBS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* sub reg from reg and invert result */ +#define E_SUBN(dest, src1, src2) DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_SUBNS(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_SUBN(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_SUBNS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* sub imm12s from reg */ +#define E_SUB_IMM(dest, src1, imm12s) DCD 0x8 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_SUB_IMMS(dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SUB_IMM(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SUB_IMMS(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* sub imm12s from reg and invert result */ +#define E_SUBN_IMM(dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_SUBN_IMMS(dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SUBN_IMM(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SUBN_IMMS(cond, dest, src1, imm12s) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* SUB reg to reg with Post Shift Left */ +#define E_SUB_LSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SUB_LSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUB_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SUB_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with Post Shift Left */ +#define E_SUBN_LSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_SUBN_LSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg with Post Shift Right */ +#define E_SUB_LSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SUB_LSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUB_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SUB_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with Post Shift Right */ +#define E_SUBN_LSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_SUBN_LSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* SUB reg to reg with Post Arith Shift Right */ +#define E_SUB_ASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SUB_ASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUB_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SUB_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with Post Arith Shift Right */ +#define E_SUBN_ASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_SUBN_ASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SUBN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* SUB reg to reg with Post ROR */ +#define E_SUB_ROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SUB_RORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUB_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SUB_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* SUB reg to reg and invert result with ROR */ +#define E_SUBN_ROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_SUBN_RORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SUBN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* Sub reg to reg with Flip */ +#define E_SUB_F(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_SUB_FS(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUB_F(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_SUB_FS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* Sub reg to reg and invert result with Flip */ +#define E_SUBN_F(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SUBN_FS(dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_F(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FS(cond, dest, src1, src2) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg with Post Shift Left */ +#define E_SUB_FLSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SUB_FLSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUB_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUB_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with Post Shift Left */ +#define E_SUBN_FLSL(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_SUBN_FLSLS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg with Post Shift Right */ +#define E_SUB_FLSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SUB_FLSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUB_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SUB_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with Post Shift Right */ +#define E_SUBN_FLSR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_SUBN_FLSRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* SUB reg to reg with Post Arith Shift Right */ +#define E_SUB_FASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SUB_FASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUB_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SUB_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with Post Arith Shift Right */ +#define E_SUBN_FASR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_SUBN_FASRS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SUBN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* SUB reg to reg with Post ROR */ +#define E_SUB_FROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SUB_FRORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUB_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SUB_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* SUB reg to reg and invert result with ROR */ +#define E_SUBN_FROR(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_SUBN_FRORS(dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SUBN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x8 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ADC Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* carry add reg from reg */ +#define E_ADC(dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ADCS(dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_ADC(cond, dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ADCS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* carry add reg from reg and invert result */ +#define E_ADCN(dest, src1, src2) DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ADCNS(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ADCN(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ADCNS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* carry add imm12s from reg */ +#define E_ADC_IMM(dest, src1, imm12s) DCD 0x9 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_ADC_IMMS(dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADC_IMM(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_ADC_IMMS(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* carry add imm12s from reg and invert result */ +#define E_ADCN_IMM(dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ADCN_IMMS(dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADCN_IMM(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ADCN_IMMS(cond, dest, src1, imm12s) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* ADC reg to reg with Post Shift Left */ +#define E_ADC_LSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADC_LSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADC_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADC_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with Post Shift Left */ +#define E_ADCN_LSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ADCN_LSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg with Post Shift Right */ +#define E_ADC_LSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADC_LSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADC_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADC_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with Post Shift Right */ +#define E_ADCN_LSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ADCN_LSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* ADC reg to reg with Post Arith Shift Right */ +#define E_ADC_ASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_ADC_ASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADC_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_ADC_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with Post Arith Shift Right */ +#define E_ADCN_ASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ADCN_ASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ADCN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* ADC reg to reg with Post ROR */ +#define E_ADC_ROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_ADC_RORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADC_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_ADC_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* ADC reg to reg and invert result with ROR */ +#define E_ADCN_ROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ADCN_RORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ADCN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* adc reg to reg with Flip */ +#define E_ADC_F(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_ADC_FS(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADC_F(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_ADC_FS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Flip */ +#define E_ADCN_F(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADCN_FS(dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_F(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FS(cond, dest, src1, src2) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg with Post Shift Left */ +#define E_ADC_FLSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADC_FLSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADC_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADC_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Post Shift Left */ +#define E_ADCN_FLSL(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ADCN_FLSLS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg with Post Shift Right */ +#define E_ADC_FLSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADC_FLSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADC_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADC_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Post Shift Right */ +#define E_ADCN_FLSR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ADCN_FLSRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* ADC reg to reg with Post Arith Shift Right */ +#define E_ADC_FASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ADC_FASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADC_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ADC_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with Post Arith Shift Right */ +#define E_ADCN_FASR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ADCN_FASRS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ADCN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* ADC reg to reg with Post ROR */ +#define E_ADC_FROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_ADC_FRORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADC_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_ADC_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* ADC reg to reg and invert result with ROR */ +#define E_ADCN_FROR(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ADCN_FRORS(dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ADCN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0x9 + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_SBC Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* carry sub reg from reg */ +#define E_SBC(dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_SBCS(dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_SBC(cond, dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_SBCS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* carry sub reg from reg and invert result */ +#define E_SBCN(dest, src1, src2) DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_SBCNS(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_SBCN(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_SBCNS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* carry sub imm12s from reg */ +#define E_SBC_IMM(dest, src1, imm12s) DCD 0xA + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_SBC_IMMS(dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SBC_IMM(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_SBC_IMMS(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* carry sub imm12s from reg and invert result */ +#define E_SBCN_IMM(dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_SBCN_IMMS(dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SBCN_IMM(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_SBCN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* SBC reg to reg with Post Shift Left */ +#define E_SBC_LSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SBC_LSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBC_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SBC_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with Post Shift Left */ +#define E_SBCN_LSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_SBCN_LSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg with Post Shift Right */ +#define E_SBC_LSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SBC_LSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBC_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SBC_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with Post Shift Right */ +#define E_SBCN_LSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_SBCN_LSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* SBC reg to reg with Post Arith Shift Right */ +#define E_SBC_ASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_SBC_ASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBC_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_SBC_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with Post Arith Shift Right */ +#define E_SBCN_ASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_SBCN_ASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_SBCN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* SBC reg to reg with Post ROR */ +#define E_SBC_ROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_SBC_RORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBC_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_SBC_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* SBC reg to reg and invert result with ROR */ +#define E_SBCN_ROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_SBCN_RORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_SBCN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* SBC reg to reg with Flip */ +#define E_SBC_F(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_SBC_FS(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBC_F(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_SBC_FS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Flip */ +#define E_SBCN_F(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SBCN_FS(dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_F(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FS(cond, dest, src1, src2) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg with Post Shift Left */ +#define E_SBC_FLSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SBC_FLSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBC_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBC_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Post Shift Left */ +#define E_SBCN_FLSL(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_SBCN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg with Post Shift Right */ +#define E_SBC_FLSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SBC_FLSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBC_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SBC_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Post Shift Right */ +#define E_SBCN_FLSR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_SBCN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* SBC reg to reg with Post Arith Shift Right */ +#define E_SBC_FASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_SBC_FASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBC_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_SBC_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with Post Arith Shift Right */ +#define E_SBCN_FASR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_SBCN_FASRS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_SBCN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* SBC reg to reg with Post ROR */ +#define E_SBC_FROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_SBC_FRORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBC_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_SBC_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* SBC reg to reg and invert result with ROR */ +#define E_SBCN_FROR(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_SBCN_FRORS(dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_SBCN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xA + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_OR Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* or reg with reg */ +#define E_OR(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ORS(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_OR(cond, dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ORS(cond, dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* or reg with reg and invert result */ +#define E_ORN(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ORNS(dest, src1, src2) DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ORN(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ORNS(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* or imm12s with reg */ +#define E_OR_IMM(dest, src1, imm12s) DCD 0xC + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_OR_IMMS(dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_OR_IMM(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_OR_IMMS(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* or imm12s with reg and invert result */ +#define E_ORN_IMM(dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ORN_IMMS(dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ORN_IMM(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ORN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* OR reg to reg with Post Shift Left */ +#define E_OR_LSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_OR_LSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_OR_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_OR_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg and invert result with Post Shift Left */ +#define E_ORN_LSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ORN_LSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg with Post Shift Right */ +#define E_OR_LSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_OR_LSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_OR_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_OR_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* OR reg to reg and invert result with Post Shift Right */ +#define E_ORN_LSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ORN_LSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* OR reg to reg with Post Arith Shift Right */ +#define E_OR_ASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_OR_ASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_OR_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_OR_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg and invert result with Post Arith Shift Right */ +#define E_ORN_ASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ORN_ASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ORN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* OR reg to reg with Post ROR */ +#define E_OR_ROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_OR_RORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_OR_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_OR_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* OR reg to reg and invert result with ROR */ +#define E_ORN_ROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ORN_RORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ORN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +/* Flip Endianness and then shift5/Rotate */ + +/* OR reg to reg with Flip */ +#define E_OR_F(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_OR_FS(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_OR_F(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_OR_FS(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Flip */ +#define E_ORN_F(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ORN_FS(dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_F(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ORN_FS(cond, dest, src1, src2) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg with Post Shift Left */ +#define E_OR_FLSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_OR_FLSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_OR_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_OR_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Post Shift Left */ +#define E_ORN_FLSL(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ORN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg with Post Shift Right */ +#define E_OR_FLSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_OR_FLSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_OR_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_OR_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Post Shift Right */ +#define E_ORN_FLSR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ORN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* OR reg to reg with Post Arith Shift Right */ +#define E_OR_FASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_OR_FASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_OR_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_OR_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg and invert result with Post Arith Shift Right */ +#define E_ORN_FASR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ORN_FASRS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ORN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* OR reg to reg with Post ROR */ +#define E_OR_FROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_OR_FRORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_OR_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_OR_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* OR reg to reg and invert result with ROR */ +#define E_ORN_FROR(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ORN_FRORS(dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ORN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xC + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_AND Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* AND reg with reg */ +#define E_AND(dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_ANDS(dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_AND(cond, dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_ANDS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* AND reg with reg and invert result */ +#define E_ANDN(dest, src1, src2) DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_ANDNS(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_ANDN(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_ANDNS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* AND imm12s with reg */ +#define E_AND_IMM(dest, src1, imm12s) DCD 0xd + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_AND_IMMS(dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_AND_IMM(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_AND_IMMS(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* AND imm12s with reg and invert result */ +#define E_ANDN_IMM(dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_ANDN_IMMS(dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ANDN_IMM(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_ANDN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* AND reg to reg with Post Shift Left */ +#define E_AND_LSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_AND_LSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_AND_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_AND_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg and invert result with Post Shift Left */ +#define E_ANDN_LSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_ANDN_LSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg with Post Shift Right */ +#define E_AND_LSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_AND_LSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_AND_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_AND_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* AND reg to reg and invert result with Post Shift Right */ +#define E_ANDN_LSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_ANDN_LSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* AND reg to reg with Post Arith Shift Right */ +#define E_AND_ASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_AND_ASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_AND_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_AND_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg and invert result with Post Arith Shift Right */ +#define E_ANDN_ASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_ANDN_ASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_ANDN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* AND reg to reg with Post ROR */ +#define E_AND_ROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_AND_RORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_AND_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_AND_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* AND reg to reg and invert result with ROR */ +#define E_ANDN_ROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_ANDN_RORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_ANDN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* AND reg to reg with Flip */ +#define E_AND_F(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_AND_FS(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_AND_F(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_AND_FS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Flip */ +#define E_ANDN_F(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_ANDN_FS(dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_F(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FS(cond, dest, src1, src2) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg with Post Shift Left */ +#define E_AND_FLSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_AND_FLSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_AND_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_AND_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Post Shift Left */ +#define E_ANDN_FLSL(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_ANDN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg with Post Shift Right */ +#define E_AND_FLSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_AND_FLSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_AND_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_AND_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Post Shift Right */ +#define E_ANDN_FLSR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_ANDN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* AND reg to reg with Post Arith Shift Right */ +#define E_AND_FASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_AND_FASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_AND_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_AND_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg and invert result with Post Arith Shift Right */ +#define E_ANDN_FASR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_ANDN_FASRS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_ANDN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* AND reg to reg with Post ROR */ +#define E_AND_FROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_AND_FRORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_AND_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_AND_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* AND reg to reg and invert result with ROR */ +#define E_ANDN_FROR(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_ANDN_FRORS(dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_ANDN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xd + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_XOR Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Use_Imm Invert Result Shift Result */ + +/* XOR reg with reg */ +#define E_XOR(dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) +#define E_XORS(dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) +#define E_COND_XOR(cond, dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) +#define E_COND_XORS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + +/* XOR reg with reg XOR invert result */ +#define E_XORN(dest, src1, src2) DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) +#define E_XORNS(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) +#define E_COND_XORN(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) +#define E_COND_XORNS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + +/* XOR imm12s with reg */ +#define E_XOR_IMM(dest, src1, imm12s) DCD 0xe + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_XOR_IMMS(dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_XOR_IMM(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) +#define E_COND_XOR_IMMS(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + +/* XOR imm12s with reg XOR invert result */ +#define E_XORN_IMM(dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_XORN_IMMS(dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (EU << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_XORN_IMM(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) +#define E_COND_XORN_IMMS(cond, dest, src1, imm12s) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (1 << 9) + (cond << 5) + (imm12s << 20) + (1 << 18) + (1 << 19) + +/* XOR reg to reg with Post Shift Left */ +#define E_XOR_LSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_XOR_LSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XOR_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_XOR_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Left */ +#define E_XORN_LSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_XORN_LSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_LSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_LSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg with Post Shift Right */ +#define E_XOR_LSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_XOR_LSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XOR_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_XOR_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Right */ +#define E_XORN_LSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_XORN_LSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_LSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_LSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (0 << 31) + +/* XOR reg to reg with Post Arith Shift Right */ +#define E_XOR_ASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_XOR_ASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XOR_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (0 << 31) +#define E_COND_XOR_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with Post Arith Shift Right */ +#define E_XORN_ASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_XORN_ASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_ASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (0 << 31) +#define E_COND_XORN_ASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (0 << 31) + +/* XOR reg to reg with Post ROR */ +#define E_XOR_ROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_XOR_RORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XOR_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (0 << 31) +#define E_COND_XOR_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) + +/* XOR reg to reg XOR invert result with ROR */ +#define E_XORN_ROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_XORN_RORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_ROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (0 << 31) +#define E_COND_XORN_RORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (0 << 31) + +/* Flip Endianness and then shift5/Rotate */ + +/* XOR reg to reg with Flip */ +#define E_XOR_F(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_XOR_FS(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XOR_F(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + (0 << 30) + \ + (1 << 31) +#define E_COND_XOR_FS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) + +/* XOR reg to reg and invert result with Flip */ +#define E_XORN_F(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_XORN_FS(dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_F(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XORN_FS(cond, dest, src1, src2) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + ((0 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg with Post Shift Left */ +#define E_XOR_FLSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_XOR_FLSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XOR_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XOR_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Left */ +#define E_XORN_FLSL(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_XORN_FLSLS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FLSL(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FLSLS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg with Post Shift Right */ +#define E_XOR_FLSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_XOR_FLSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XOR_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_XOR_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with Post Shift Right */ +#define E_XORN_FLSR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_XORN_FLSRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FLSR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (0 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FLSRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (0 << 29) + (1 << 30) + (1 << 31) + +/* XOR reg to reg with Post Arith Shift Right */ +#define E_XOR_FASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_XOR_FASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XOR_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (0 << 30) + (1 << 31) +#define E_COND_XOR_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with Post Arith Shift Right */ +#define E_XORN_FASR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_XORN_FASRS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FASR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 30) + (1 << 31) +#define E_COND_XORN_FASRS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (0 << 30) + (1 << 31) + +/* XOR reg to reg with Post ROR */ +#define E_XOR_FROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_XOR_FRORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XOR_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + ((shift5 & 0x1f) << 24) + (1 << 29) + \ + (1 << 30) + (1 << 31) +#define E_COND_XOR_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) + +/* XOR reg to reg XOR invert result with ROR */ +#define E_XORN_FROR(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (EU << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_XORN_FRORS(dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (EU << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FROR(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (cond << 5) + (1 << 19) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 30) + (1 << 31) +#define E_COND_XORN_FRORS(cond, dest, src1, src2, shift5) \ + DCD 0xe + (dest << 10) + (src1 << 14) + (src2 << 20) + (1 << 9) + (cond << 5) + (1 << 19) + \ + ((shift5 & 0x1f) << 24) + (1 << 29) + (1 << 30) + (1 << 31) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_Shift Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation */ +/* Left/Right Shift/Rotate */ + +/* Logical Shift */ +#define E_LSL(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_LSR(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_LSLS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_LSRS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_LSL_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_LSL_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_LSL_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_LSL_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_LSL_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_LSL_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_LSL_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_LSL_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_LSL_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_LSL_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_LSL_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_LSL_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_LSL_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_LSL_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_LSR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/* Conditional */ +/* Logical Shift */ +#define E_COND_LSL(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_LSR(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_COND_LSLS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_LSRS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_COND_LSL_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_COND_LSL_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_COND_LSL_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_COND_LSL_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_COND_LSL_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_LSL_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_COND_LSL_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_LSL_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_COND_LSL_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_LSL_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_COND_LSL_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_LSL_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_COND_LSL_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_LSL_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_LSR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ROTATE Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate */ + +/* Rotate */ +#define E_ROR(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_RORS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_ROR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_ROR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_ROR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_ROR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_ROR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_ROR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_ROR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_ROR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_ROR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_ROR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_ROR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_ROR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_ROR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_ROR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/* Conditional */ +/* Rotate */ +#define E_COND_ROR(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_COND_RORS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_COND_ROR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_COND_ROR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_COND_ROR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_COND_ROR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_COND_ROR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_COND_ROR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_COND_ROR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_COND_ROR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_COND_ROR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_COND_ROR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_COND_ROR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_COND_ROR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_COND_ROR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_COND_ROR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Arithmetical Shift Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate Arith/Shift */ + +/* Arith Shift Right */ +#define E_ASR(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag */ +#define E_ASRS(dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then AND */ +#define E_ASR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then AND */ +#define E_ASR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then OR */ +#define E_ASR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then OR */ +#define E_ASR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then XOR */ +#define E_ASR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then XOR */ +#define E_ASR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADD */ +#define E_ASR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADD */ +#define E_ASR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SUB */ +#define E_ASR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SUB */ +#define E_ASR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADC */ +#define E_ASR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADC */ +#define E_ASR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SBC */ +#define E_ASR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SBC */ +#define E_ASR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/* Conditional */ +/* Conditional Arith Shift */ +#define E_COND_ASR(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag */ +#define E_COND_ASRS(cond, dest, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then AND */ +#define E_COND_ASR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_ASR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then OR */ +#define E_COND_ASR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_ASR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_ASR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_ASR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_ASR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_ASR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_ASR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_ASR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_ASR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_ASR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_ASR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_ASR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x10 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Flip Opcodes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Endian/bit + */ +/* ARITH Arith/Shift */ + +/* Flip Endian , ASR Right */ +#define E_FEND_ASR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag */ +#define E_FEND_ASRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , AND */ +#define E_FEND_ASR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then AND */ +#define E_FEND_ASR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , OR */ +#define E_FEND_ASR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then OR */ +#define E_FEND_ASR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , XOR */ +#define E_FEND_ASR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then XOR */ +#define E_FEND_ASR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , ADD */ +#define E_FEND_ASR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then ADD */ +#define E_FEND_ASR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , SUB */ +#define E_FEND_ASR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then SUB */ +#define E_FEND_ASR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , ADC */ +#define E_FEND_ASR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then ADC */ +#define E_FEND_ASR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) + +/* Flip Endian , ASR Right , SBC */ +#define E_FEND_ASR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) +/* Flip Endian , ASR Right ,Set Flag then SBC */ +#define E_FEND_ASR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) + +/* Conditional */ +/* Conditional Flip Endian , ASR */ +#define E_COND_FEND_ASR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag */ +#define E_COND_FEND_ASRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , AND */ +#define E_COND_FEND_ASR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then AND */ +#define E_COND_FEND_ASR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , OR */ +#define E_COND_FEND_ASR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then OR */ +#define E_COND_FEND_ASR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , XOR */ +#define E_COND_FEND_ASR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then XOR */ +#define E_COND_FEND_ASR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , ADD */ +#define E_COND_FEND_ASR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then ADD */ +#define E_COND_FEND_ASR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , SUB */ +#define E_COND_FEND_ASR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then SUB */ +#define E_COND_FEND_ASR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , ADC */ +#define E_COND_FEND_ASR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then ADC */ +#define E_COND_FEND_ASR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (1 << 19) + +/* Conditional Flip Endian , ASR , SBC */ +#define E_COND_FEND_ASR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) +/* Conditional Flip Endian , ASR ,Set Flag then SBC */ +#define E_COND_FEND_ASR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (1 << 19) + +/* Bitwise Flip ASR */ + +/* Flip Bitwise , ASR Right */ +#define E_FBIT_ASR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag */ +#define E_FBIT_ASRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , AND */ +#define E_FBIT_ASR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then AND */ +#define E_FBIT_ASR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , OR */ +#define E_FBIT_ASR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then OR */ +#define E_FBIT_ASR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , XOR */ +#define E_FBIT_ASR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then XOR */ +#define E_FBIT_ASR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , ADD */ +#define E_FBIT_ASR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then ADD */ +#define E_FBIT_ASR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , SUB */ +#define E_FBIT_ASR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then SUB */ +#define E_FBIT_ASR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , ADC */ +#define E_FBIT_ASR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then ADC */ +#define E_FBIT_ASR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) + +/* Flip Bitwise , ASR Right , SBC */ +#define E_FBIT_ASR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) +/* Flip Bitwise , ASR Right ,Set Flag then SBC */ +#define E_FBIT_ASR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) + +/* Conditional */ +/* Conditional Flip Bitwise , ASR */ +#define E_COND_FBIT_ASR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag */ +#define E_COND_FBIT_ASRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , AND */ +#define E_COND_FBIT_ASR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then AND */ +#define E_COND_FBIT_ASR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , OR */ +#define E_COND_FBIT_ASR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then OR */ +#define E_COND_FBIT_ASR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , XOR */ +#define E_COND_FBIT_ASR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then XOR */ +#define E_COND_FBIT_ASR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , ADD */ +#define E_COND_FBIT_ASR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then ADD */ +#define E_COND_FBIT_ASR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , SUB */ +#define E_COND_FBIT_ASR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then SUB */ +#define E_COND_FBIT_ASR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , ADC */ +#define E_COND_FBIT_ASR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then ADC */ +#define E_COND_FBIT_ASR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (1 << 19) + +/* Conditional Flip Bitwise , ASR , SBC */ +#define E_COND_FBIT_ASR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) +/* Conditional Flip Bitwise , ASR ,Set Flag then SBC */ +#define E_COND_FBIT_ASR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (1 << 19) + +/* Flip Endian , LSR Right */ +#define E_FEND_LSR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag */ +#define E_FEND_LSRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , AND */ +#define E_FEND_LSR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then AND */ +#define E_FEND_LSR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , OR */ +#define E_FEND_LSR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then OR */ +#define E_FEND_LSR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , XOR */ +#define E_FEND_LSR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then XOR */ +#define E_FEND_LSR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , ADD */ +#define E_FEND_LSR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then ADD */ +#define E_FEND_LSR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , SUB */ +#define E_FEND_LSR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then SUB */ +#define E_FEND_LSR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , ADC */ +#define E_FEND_LSR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then ADC */ +#define E_FEND_LSR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) + +/* Flip Endian , LSR Right , SBC */ +#define E_FEND_LSR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) +/* Flip Endian , LSR Right ,Set Flag then SBC */ +#define E_FEND_LSR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) + +/* Conditional */ +/* Conditional Flip Endian , LSR */ +#define E_COND_FEND_LSR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag */ +#define E_COND_FEND_LSRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , AND */ +#define E_COND_FEND_LSR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then AND */ +#define E_COND_FEND_LSR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , OR */ +#define E_COND_FEND_LSR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then OR */ +#define E_COND_FEND_LSR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , XOR */ +#define E_COND_FEND_LSR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then XOR */ +#define E_COND_FEND_LSR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , ADD */ +#define E_COND_FEND_LSR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then ADD */ +#define E_COND_FEND_LSR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , SUB */ +#define E_COND_FEND_LSR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then SUB */ +#define E_COND_FEND_LSR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , ADC */ +#define E_COND_FEND_LSR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then ADC */ +#define E_COND_FEND_LSR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (0 << 18) + (0 << 19) + +/* Conditional Flip Endian , LSR , SBC */ +#define E_COND_FEND_LSR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) +/* Conditional Flip Endian , LSR ,Set Flag then SBC */ +#define E_COND_FEND_LSR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (0 << 18) + (0 << 19) + +/* Bitwise Flip LSR */ + +/* Flip Bitwise , LSR Right */ +#define E_FBIT_LSR(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag */ +#define E_FBIT_LSRS(dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , AND */ +#define E_FBIT_LSR_AND(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then AND */ +#define E_FBIT_LSR_ANDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , OR */ +#define E_FBIT_LSR_OR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then OR */ +#define E_FBIT_LSR_ORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , XOR */ +#define E_FBIT_LSR_XOR(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then XOR */ +#define E_FBIT_LSR_XORS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , ADD */ +#define E_FBIT_LSR_ADD(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then ADD */ +#define E_FBIT_LSR_ADDS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , SUB */ +#define E_FBIT_LSR_SUB(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then SUB */ +#define E_FBIT_LSR_SUBS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , ADC */ +#define E_FBIT_LSR_ADC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then ADC */ +#define E_FBIT_LSR_ADCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) + +/* Flip Bitwise , LSR Right , SBC */ +#define E_FBIT_LSR_SBC(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) +/* Flip Bitwise , LSR Right ,Set Flag then SBC */ +#define E_FBIT_LSR_SBCS(dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) + +/* Conditional */ +/* Conditional Flip Bitwise , LSR */ +#define E_COND_FBIT_LSR(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag */ +#define E_COND_FBIT_LSRS(cond, dest, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + (0 << 29) + \ + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , AND */ +#define E_COND_FBIT_LSR_AND(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then AND */ +#define E_COND_FBIT_LSR_ANDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (1 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , OR */ +#define E_COND_FBIT_LSR_OR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then OR */ +#define E_COND_FBIT_LSR_ORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (2 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , XOR */ +#define E_COND_FBIT_LSR_XOR(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then XOR */ +#define E_COND_FBIT_LSR_XORS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (3 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , ADD */ +#define E_COND_FBIT_LSR_ADD(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then ADD */ +#define E_COND_FBIT_LSR_ADDS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (4 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , SUB */ +#define E_COND_FBIT_LSR_SUB(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then SUB */ +#define E_COND_FBIT_LSR_SUBS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (5 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , ADC */ +#define E_COND_FBIT_LSR_ADC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then ADC */ +#define E_COND_FBIT_LSR_ADCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (6 << 29) + (1 << 18) + (0 << 19) + +/* Conditional Flip Bitwise , LSR , SBC */ +#define E_COND_FBIT_LSR_SBC(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) +/* Conditional Flip Bitwise , LSR ,Set Flag then SBC */ +#define E_COND_FBIT_LSR_SBCS(cond, dest, roperand, r2shift, shift5) \ + DCD 0x11 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((shift5 & 0x1f) << 24) + \ + (7 << 29) + (1 << 18) + (0 << 19) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ANDOR */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* opcode Dest Src1 src2 SFlag */ +/* Cond SRC3 */ + +/* ANDOR */ +#define E_ANDOR(dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (0 << 9) + (EU << 5) + (ror << 24) +#define E_ANDORS(dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (1 << 9) + (EU << 5) + (ror << 24) +#define E_COND_ANDOR(cond, dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (0 << 9) + (cond << 5) + (ror << 24) +#define E_COND_ANDORS(cond, dest, rsrc, rand, ror) \ + DCD 0x16 + (dest << 10) + (rsrc << 14)(rand << 20) + (1 << 9) + (cond << 5) + (ror << 24) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_Shift byte reg Codes */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 src2 SFlag Cond + */ +/* Imm Extra Operation Left/Right */ +/* Shift/Rotate Invert */ + +/* Logical Shift */ +#define E_RLSL(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_RLSR(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_RLSLS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_RLSRS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_RLSL_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_RLSL_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_RLSL_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_RLSL_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_RLSL_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_RLSL_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_RLSL_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_RLSL_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_RLSL_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_RLSL_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_RLSL_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_RLSL_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_RLSL_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_RLSL_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_RLSR_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/* Conditional */ +/* Logical Shift */ +#define E_COND_RLSL(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_RLSR(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag */ +#define E_COND_RLSLS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) +#define E_COND_RLSRS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + +/* Logical Shift and then AND */ +#define E_COND_RLSL_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then AND */ +#define E_COND_RLSL_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then OR */ +#define E_COND_RLSL_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then OR */ +#define E_COND_RLSL_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then XOR */ +#define E_COND_RLSL_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_RLSL_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADD */ +#define E_COND_RLSL_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_RLSL_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SUB */ +#define E_COND_RLSL_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_RLSL_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then ADC */ +#define E_COND_RLSL_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_RLSL_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + +/* Logical Shift and then SBC */ +#define E_COND_RLSL_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_RLSL_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) +#define E_COND_RLSR_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation */ +/* Left/Right Shift/Rotate POSTshift */ + +/* Logical Shift and then AND */ +#define E_AND_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_AND_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_AND_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_AND_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_OR_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_OR_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_OR_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_OR_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_XOR_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_XOR_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_XOR_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_XOR_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_ADD_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADD_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_ADD_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADD_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_SUB_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SUB_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_SUB_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SUB_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_ADC_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADC_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_ADC_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_ADC_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_SBC_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SBC_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_SBC_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_SBC_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Conditional */ + +/* Logical Shift and then AND */ +#define E_COND_AND_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_AND_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_COND_AND_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_AND_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_COND_OR_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_OR_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_COND_OR_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_OR_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_COND_XOR_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_XOR_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_XOR_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_XOR_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_COND_ADD_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADD_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_ADD_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADD_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_COND_SUB_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SUB_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_SUB_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SUB_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_COND_ADC_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADC_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_ADC_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_ADC_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_COND_SBC_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SBC_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_SBC_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 28) +#define E_COND_SBC_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 28) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_Shift byte reg with inversion */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* Logical Shift */ +#define E_RLSLN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSRN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag */ +#define E_RLSLNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSRNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then AND */ +#define E_RLSL_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then AND */ +#define E_RLSL_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then OR */ +#define E_RLSL_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then OR */ +#define E_RLSL_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then XOR */ +#define E_RLSL_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then XOR */ +#define E_RLSL_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADD */ +#define E_RLSL_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADD */ +#define E_RLSL_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SUB */ +#define E_RLSL_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SUB */ +#define E_RLSL_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADC */ +#define E_RLSL_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADC */ +#define E_RLSL_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SBC */ +#define E_RLSL_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SBC */ +#define E_RLSL_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_RLSR_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Conditional */ +/* Logical Shift */ +#define E_COND_RLSLN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSRN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag */ +#define E_COND_RLSLNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSRNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then AND */ +#define E_COND_RLSL_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then AND */ +#define E_COND_RLSL_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then OR */ +#define E_COND_RLSL_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then OR */ +#define E_COND_RLSL_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then XOR */ +#define E_COND_RLSL_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_RLSL_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADD */ +#define E_COND_RLSL_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_RLSL_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SUB */ +#define E_COND_RLSL_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_RLSL_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then ADC */ +#define E_COND_RLSL_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_RLSL_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* Logical Shift and then SBC */ +#define E_COND_RLSL_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_RLSL_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) +#define E_COND_RLSR_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation */ +/* Left/Right Shift/Rotate Inv POSTshift */ + +/* Logical Shift and then AND */ +#define E_ANDN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ANDN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_ANDN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ANDN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_ORN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ORN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_ORN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ORN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_XORN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_XORN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_XORN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_XORN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_ADDN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADDN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_ADDN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADDN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_SUBN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SUBN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_SUBN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SUBN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_ADCN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADCN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_ADCN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_ADCN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_SBCN_RLSL(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SBCN_RLSR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_SBCN_RLSLS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_SBCN_RLSRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Conditional */ + +/* Logical Shift and then AND */ +#define E_COND_ANDN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ANDN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then AND */ +#define E_COND_ANDN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ANDN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then OR */ +#define E_COND_ORN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ORN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then OR */ +#define E_COND_ORN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ORN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then XOR */ +#define E_COND_XORN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_XORN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then XOR */ +#define E_COND_XORN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_XORN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADD */ +#define E_COND_ADDN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADDN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADD */ +#define E_COND_ADDN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADDN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SUB */ +#define E_COND_SUBN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SUBN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SUB */ +#define E_COND_SUBN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SUBN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then ADC */ +#define E_COND_ADCN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADCN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then ADC */ +#define E_COND_ADCN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_ADCN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/* Logical Shift and then SBC */ +#define E_COND_SBCN_RLSL(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SBCN_RLSR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +/* Logical Shift and Set Flag then SBC */ +#define E_COND_SBCN_RLSLS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (0 << 18) + (1 << 27) + (1 << 28) +#define E_COND_SBCN_RLSRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (0 << 18) + (1 << 27) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ROTATE by Reg Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate */ + +/* Rotate */ +#define E_RROR(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_RRORS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_RROR_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_RROR_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_RROR_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_RROR_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_RROR_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_RROR_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_RROR_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_RROR_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_RROR_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_RROR_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_RROR_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_RROR_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_RROR_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_RROR_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/* Conditional */ +/* Rotate */ +#define E_COND_RROR(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) +/* Rotate and Set Flag */ +#define E_COND_RRORS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_COND_RROR_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then AND */ +#define E_COND_RROR_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then OR */ +#define E_COND_RROR_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then OR */ +#define E_COND_RROR_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then XOR */ +#define E_COND_RROR_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then XOR */ +#define E_COND_RROR_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADD */ +#define E_COND_RROR_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADD */ +#define E_COND_RROR_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SUB */ +#define E_COND_RROR_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SUB */ +#define E_COND_RROR_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then ADC */ +#define E_COND_RROR_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then ADC */ +#define E_COND_RROR_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then SBC */ +#define E_COND_RROR_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) +/* Rotate and Set Flag then SBC */ +#define E_COND_RROR_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + +/* Rotate and then AND */ +#define E_AND_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_AND_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then OR */ +#define E_OR_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_OR_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then XOR */ +#define E_XOR_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_XOR_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADD */ +#define E_ADD_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_ADD_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SUB */ +#define E_SUB_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_SUB_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADC */ +#define E_ADC_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_ADC_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SBC */ +#define E_SBC_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_SBC_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Conditional */ + +/* Rotate and then AND */ +#define E_COND_AND_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_COND_AND_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then OR */ +#define E_COND_OR_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_COND_OR_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then XOR */ +#define E_COND_XOR_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_COND_XOR_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADD */ +#define E_COND_ADD_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_COND_ADD_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SUB */ +#define E_COND_SUB_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_COND_SUB_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then ADC */ +#define E_COND_ADC_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_COND_ADC_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/* Rotate and then SBC */ +#define E_COND_SBC_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_COND_SBC_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* E_ROTATE by Reg Codes and invert ALU result */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate */ + +/* Rotate */ +#define E_RRORN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag */ +#define E_RRORNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then AND */ +#define E_RROR_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then AND */ +#define E_RROR_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then OR */ +#define E_RROR_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then OR */ +#define E_RROR_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then XOR */ +#define E_RROR_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then XOR */ +#define E_RROR_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADD */ +#define E_RROR_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADD */ +#define E_RROR_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SUB */ +#define E_RROR_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SUB */ +#define E_RROR_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADC */ +#define E_RROR_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADC */ +#define E_RROR_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SBC */ +#define E_RROR_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SBC */ +#define E_RROR_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Conditional */ +/* Rotate */ +#define E_COND_RRORN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag */ +#define E_COND_RRORNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then AND */ +#define E_COND_RROR_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then AND */ +#define E_COND_RROR_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then OR */ +#define E_COND_RROR_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then OR */ +#define E_COND_RROR_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then XOR */ +#define E_COND_RROR_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then XOR */ +#define E_COND_RROR_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADD */ +#define E_COND_RROR_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADD */ +#define E_COND_RROR_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SUB */ +#define E_COND_RROR_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SUB */ +#define E_COND_RROR_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then ADC */ +#define E_COND_RROR_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then ADC */ +#define E_COND_RROR_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then SBC */ +#define E_COND_RROR_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) +/* Rotate and Set Flag then SBC */ +#define E_COND_RROR_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + +/* Rotate and then AND */ +#define E_ANDN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_ANDN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then OR */ +#define E_ORN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_ORN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then XOR */ +#define E_XORN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_XORN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADD */ +#define E_ADDN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_ADDN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SUB */ +#define E_SUBN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_SUBN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADC */ +#define E_ADCN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_ADCN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SBC */ +#define E_SBCN_RROR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_SBCN_RRORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional */ + +/* Rotate and then AND */ +#define E_COND_ANDN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then AND */ +#define E_COND_ANDN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then OR */ +#define E_COND_ORN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then OR */ +#define E_COND_ORN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then XOR */ +#define E_COND_XORN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then XOR */ +#define E_COND_XORN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADD */ +#define E_COND_ADDN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADD */ +#define E_COND_ADDN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SUB */ +#define E_COND_SUBN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SUB */ +#define E_COND_SUBN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then ADC */ +#define E_COND_ADCN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then ADC */ +#define E_COND_ADCN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Rotate and then SBC */ +#define E_COND_SBCN_RROR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Rotate and Set Flag then SBC */ +#define E_COND_SBCN_RRORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (1 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Arithmetical Shift Codes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate Arith/Shift */ + +/* Arith Shift Right */ +#define E_RASR(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag */ +#define E_RASRS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then AND */ +#define E_RASR_AND(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then AND */ +#define E_RASR_ANDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then OR */ +#define E_RASR_OR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then OR */ +#define E_RASR_ORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then XOR */ +#define E_RASR_XOR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then XOR */ +#define E_RASR_XORS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADD */ +#define E_RASR_ADD(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADD */ +#define E_RASR_ADDS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SUB */ +#define E_RASR_SUB(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SUB */ +#define E_RASR_SUBS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then ADC */ +#define E_RASR_ADC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then ADC */ +#define E_RASR_ADCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then SBC */ +#define E_RASR_SBC(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Arith Shift Right and Set Flag then SBC */ +#define E_RASR_SBCS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/* Conditional */ +/* Conditional Arith Shift */ +#define E_COND_RASR(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag */ +#define E_COND_RASRS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then AND */ +#define E_COND_RASR_AND(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_RASR_ANDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then OR */ +#define E_COND_RASR_OR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_RASR_ORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_RASR_XOR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_RASR_XORS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_RASR_ADD(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_RASR_ADDS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_RASR_SUB(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_RASR_SUBS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_RASR_ADC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_RASR_ADCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_RASR_SBC(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_RASR_SBCS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + +/* Arith Shift Right and then AND */ +#define E_AND_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then AND */ +#define E_AND_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then OR */ +#define E_OR_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then OR */ +#define E_OR_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then XOR */ +#define E_XOR_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then XOR */ +#define E_XOR_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then ADD */ +#define E_ADD_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then ADD */ +#define E_ADD_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then SUB */ +#define E_SUB_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then SUB */ +#define E_SUB_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then ADC */ +#define E_ADC_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then ADC */ +#define E_ADC_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Arith Shift Right and then SBC */ +#define E_SBC_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Arith Shift Right and Set Flag then SBC */ +#define E_SBC_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional */ + +/* Conditional Arith Shift and then AND */ +#define E_COND_AND_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_AND_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then OR */ +#define E_COND_OR_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_OR_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_XOR_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_XOR_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_ADD_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_ADD_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_SUB_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_SUB_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_ADC_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_ADC_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_SBC_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_SBC_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Arithmetical Shift Codes with invert ALU */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Dest Src1 r2shift SFlag + */ +/* Cond Imm Extra Operation Left/Right + */ +/* Shift/Rotate pOSTShift */ + +/* Arith Shift Right */ +#define E_RASRN(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag */ +#define E_RASRNS(dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then AND */ +#define E_RASR_ANDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then AND */ +#define E_RASR_ANDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then OR */ +#define E_RASR_ORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then OR */ +#define E_RASR_ORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then XOR */ +#define E_RASR_XORN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then XOR */ +#define E_RASR_XORNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then ADD */ +#define E_RASR_ADDN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then ADD */ +#define E_RASR_ADDNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then SUB */ +#define E_RASR_SUBN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then SUB */ +#define E_RASR_SUBNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then ADC */ +#define E_RASR_ADCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then ADC */ +#define E_RASR_ADCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then SBC */ +#define E_RASR_SBCN(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Arith Shift Right and Set Flag then SBC */ +#define E_RASR_SBCNS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional */ +/* Conditional Arith Shift */ +#define E_COND_RASRN(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag */ +#define E_COND_RASRNS(cond, dest, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + (0 << 29) + \ + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then AND */ +#define E_COND_RASR_ANDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_RASR_ANDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then OR */ +#define E_COND_RASR_ORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_RASR_ORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_RASR_XORN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_RASR_XORNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_RASR_ADDN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_RASR_ADDNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_RASR_SUBN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_RASR_SUBNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_RASR_ADCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_RASR_ADCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_RASR_SBCN(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_RASR_SBCNS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + +/* Arith Shift Right and then AND */ +#define E_ANDN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then AND */ +#define E_ANDN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then OR */ +#define E_ORN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then OR */ +#define E_ORN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then XOR */ +#define E_XORN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then XOR */ +#define E_XORN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then ADD */ +#define E_ADDN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then ADD */ +#define E_ADDN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then SUB */ +#define E_SUBN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then SUB */ +#define E_SUBN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then ADC */ +#define E_ADCN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then ADC */ +#define E_ADCN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Arith Shift Right and then SBC */ +#define E_SBCN_RASR(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Arith Shift Right and Set Flag then SBC */ +#define E_SBCN_RASRS(dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (EU << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional */ + +/* Conditional Arith Shift and then AND */ +#define E_COND_ANDN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then AND */ +#define E_COND_ANDN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (1 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then OR */ +#define E_COND_ORN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then OR */ +#define E_COND_ORN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (2 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then XOR */ +#define E_COND_XORN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then XOR */ +#define E_COND_XORN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (3 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then ADD */ +#define E_COND_ADDN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADD */ +#define E_COND_ADDN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (4 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then SUB */ +#define E_COND_SUBN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SUB */ +#define E_COND_SUBN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (5 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then ADC */ +#define E_COND_ADCN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then ADC */ +#define E_COND_ADCN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (6 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/* Conditional Arith Shift and then SBC */ +#define E_COND_SBCN_RASR(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (0 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) +/* Conditional Arith Shift and Set Flag then SBC */ +#define E_COND_SBCN_RASRS(cond, dest, roperand, r2shift, rshift) \ + DCD 0x19 + (dest << 10) + (roperand << 14) + (r2shift << 20) + (1 << 9) + (cond << 5) + ((rshift & 0x1f) << 24) + \ + (7 << 29) + (0 << 19) + (1 << 18) + (1 << 27) + (1 << 28) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Bit Manipulate */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* opcode Dest Src1 src2 SFlag */ +/* Cond Imm Extra Operation ShiftByByte + */ +/* Neg/Pos Mask */ + +/* Bit test by byte */ +#define E_BTST(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BCLR(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_BSET(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BTOG(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (EU << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Bit test by byte with set flags */ +#define E_BTSTS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BCLRS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_BSETS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_BTOGS(dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (EU << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Conditional Bit test by byte */ +#define E_COND_BTST(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BCLR(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_COND_BSET(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BTOG(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (0 << 9) + (cond << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Conditional Bit test by byte with set flags */ +#define E_COND_BTSTS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BCLRS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (1 << 29) + \ + (1 << 18) + (0 << 31) +#define E_COND_BSETS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (2 << 29) + \ + (1 << 18) + (1 << 31) +#define E_COND_BTOGS(cond, dest, rdata, rbit) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (rbit << 20) + (1 << 9) + (cond << 5) + (0 << 24) + (3 << 29) + \ + (1 << 18) + (1 << 31) + +/* Bit test by imm */ +#define E_BTST_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BCLR_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_BSET_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BTOG_IMM(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/* Bit test by imm with set flags */ +#define E_BTST_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BCLR_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_BSET_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_BTOG_IMMS(dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (EU << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/* Conditional Bit test by imm */ +#define E_COND_BTST_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BCLR_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_COND_BSET_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BTOG_IMM(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (0 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/* Conditional Bit test by imm with set flags */ +#define E_COND_BTST_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BCLR_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (1 << 29) + (0 << 18) + \ + (0 << 31) +#define E_COND_BSET_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (2 << 29) + (0 << 18) + \ + (1 << 31) +#define E_COND_BTOG_IMMS(cond, dest, rdata, bit5) \ + DCD 0x18 + (dest << 10) + (rdata << 14) + (1 << 9) + (cond << 5) + ((bit5 & 0x1f) << 24) + (3 << 29) + (0 << 18) + \ + (1 << 31) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Tight Loop */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_TIGHT_LOOP(rend, rcount) DCD 0x1A + (rend << 14) + (rcount << 20) +#define E_COND_TIGHT_LOOP(cond, rend, rcount) DCD 0x1A + (rend << 14) + (rcount << 20) + (cond << 5) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Boolean Detect */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Opcode Dest Vector/Single NoUpdateRA */ +/* LargeVectors Cond Table */ + +#define E_HOLD DCD 0x1C + (PC << 10) + (1 << 15) + (0 << 18) + (0 << 19) + (EU << 5) +#define E_COND_HOLD(cond) DCD 0x1C + (PC << 10) + (1 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + +/* Small Vector Versions */ +#define E_VECTORED_HOLD(table) DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD(cond, table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + (table << 20) +#define E_VECTORED_HOLD_NRA(table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD_NRA \ + (cond, table) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (cond << 5) + (table << 20) + +/* Large Vector Versions */ +#define E_VECTORED_HOLD_LV(table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD_LV(cond, table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (cond << 5) + (table << 20) +#define E_VECTORED_HOLD_LV_NRA(table) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (EU << 5) + (table << 20) +#define E_COND_VECTORED_HOLD_LV_NRA \ + (cond, table) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (cond << 5) + (table << 20) + +/*/ Accelarated Vectored_hold */ +/* Small Vector Versions */ +#define E_ACC_VECTORED_HOLD(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD(cond, table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (0 << 19) + (cond << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_ACC_VECTORED_HOLD_NRA(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD_NRA \ + (cond, table, vectors) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (0 << 19) + (cond << 5) + \ + (table << 20) + (1 << 9) + (vectors << 24) + +/* Large Vector Versions */ +#define E_ACC_VECTORED_HOLD_LV(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD_LV(cond, table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (0 << 18) + (1 << 19) + (cond << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_ACC_VECTORED_HOLD_LV_NRA(table, vectors) \ + DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (EU << 5) + (table << 20) + (1 << 9) + \ + (vectors << 24) +#define E_COND_ACC_VECTORED_HOLD_LV_NRA \ + (cond, table, vectors) DCD 0x1C + (table << 10) + (0 << 15) + (1 << 18) + (1 << 19) + (cond << 5) + \ + (table << 20) + (1 << 9) + (vectors << 24) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Reg offset Read */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Rdata Dest Pointer WData Source */ +/* Offset SizeWord Signed Access Cond Write */ + +/* LDR (Load, Load Byte, LoadByteSigned) */ +#define E_LDR_REG(dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (1 << 18) + (0 << 21) + (EU << 5) +#define E_LDR_REGB(dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (0 << 21) + (EU << 5) +#define E_LDR_REGBS(dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (1 << 21) + (EU << 5) + +/* Conditional LDR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_LDR_REG(cond, dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (1 << 18) + (0 << 21) + (cond << 5) +#define E_COND_LDR_REGB(cond, dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (0 << 21) + (cond << 5) +#define E_COND_LDR_REGBS(cond, dest, source, offset) \ + DCD 0x1D + (dest << 10) + (source << 14) + (offset << 24) + (0 << 18) + (1 << 21) + (cond << 5) + +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* Reg offset Write */ +/*------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +/* opcode Rdata Dest Pointer WData Source */ +/* Offset SizeWord Signed Access Cond Write */ + +/* STR (Load, Load Byte, LoadByteSigned) */ +#define E_STR_REG(raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (1 << 18) + (0 << 11) + (EU << 5) + (1 << 30) +#define E_STR_REGB(raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (0 << 18) + (0 << 11) + (EU << 5) + (1 << 30) + +/* Conditional STR (Load, Load Byte, LoadByteSigned) */ +#define E_COND_STR_REG(cond, raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (1 << 18) + (0 << 11) + (cond << 5) + (1 << 30) +#define E_COND_STR_REGB(cond, raddr, rdata, roffset) \ + DCD 0x1D + (raddr << 14) + (rdata << 20) + (roffset << 24) + (0 << 18) + (0 << 11) + (cond << 5) + (1 << 30) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* GPO modify Byte */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_MODIFY_GPO_BYTE(andmask, ormask, xormask) DCD 0x1E + (andmask << 8) + (ormask << 16) + (xormask << 24) + +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ +/* HeartBeat opcodes */ +/*-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ + +#define E_HEART_RYTHM_IMM(val16imm) DCD 0x32 + (val16imm << 16) +#define E_HEART_RYTHM(r16bit) DCD 0x32 + (r16bit << 14) + (1 << 9) +#define E_SYNCH_ALL_TO_BEAT(on1imm) DCD 0x52 + (on1imm << 31) +#define E_WAIT_FOR_BEAT DCD 0x72 + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_rt500.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_rt500.c new file mode 100644 index 0000000000..f8952e16e1 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_rt500.c @@ -0,0 +1,2518 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_smartdma.h" + +#if defined(MIMXRT533S_SERIES) || defined(MIMXRT555S_SERIES) || defined(MIMXRT595S_cm33_SERIES) + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_AND_FLEXIO) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x60U, 0x00U, 0x10U, 0x24U, 0x40U, 0x01U, 0x10U, 0x24U, 0xC8U, 0x02U, 0x10U, 0x24U, + 0x04U, 0x02U, 0x10U, 0x24U, 0x68U, 0x03U, 0x10U, 0x24U, 0x98U, 0x08U, 0x10U, 0x24U, + 0xE8U, 0x0DU, 0x10U, 0x24U, 0xFCU, 0x0FU, 0x10U, 0x24U, 0x70U, 0x12U, 0x10U, 0x24U, + 0xE8U, 0x14U, 0x10U, 0x24U, 0xACU, 0x25U, 0x10U, 0x24U, 0x54U, 0x16U, 0x10U, 0x24U, + 0xCCU, 0x27U, 0x10U, 0x24U, 0x18U, 0x19U, 0x10U, 0x24U, 0x7CU, 0x2BU, 0x10U, 0x24U, + 0xE4U, 0x1BU, 0x10U, 0x24U, 0x54U, 0x1DU, 0x10U, 0x24U, 0x24U, 0x20U, 0x10U, 0x24U, + 0xDCU, 0x2EU, 0x10U, 0x24U, 0x68U, 0x33U, 0x10U, 0x24U, 0x70U, 0x38U, 0x10U, 0x24U, + 0x8CU, 0x3BU, 0x10U, 0x24U, 0xF8U, 0x22U, 0x10U, 0x24U, 0x44U, 0x3EU, 0x10U, 0x24U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, + 0x06U, 0x48U, 0xC7U, 0x08U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, + 0x05U, 0x04U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x08U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, + 0x05U, 0x10U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x14U, 0x22U, 0x32U, 0x11U, 0x08U, 0x38U, 0x00U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, 0x05U, 0x18U, 0x22U, 0x32U, + 0x11U, 0x08U, 0x38U, 0x00U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x10U, 0x08U, 0x2CU, 0x10U, + 0x05U, 0x1CU, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x42U, 0x02U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x14U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0x07U, 0x07U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x06U, 0x00U, 0xC4U, 0x01U, 0x01U, 0x08U, 0x1CU, 0xFFU, + 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0xFFU, + 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x05U, 0x04U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x08U, 0x42U, 0x32U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x0CU, 0x52U, 0x32U, 0x01U, 0x08U, 0x1CU, 0xFFU, + 0x01U, 0x0CU, 0x1CU, 0xFFU, 0x01U, 0x10U, 0x1CU, 0xFFU, 0x01U, 0x14U, 0x1CU, 0x08U, + 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x10U, 0x22U, 0x32U, 0x11U, 0x0CU, 0x30U, 0x00U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, 0x05U, 0x18U, 0x42U, 0x32U, + 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x1CU, 0x52U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xCAU, 0x03U, 0x20U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, + 0x01U, 0xB0U, 0x05U, 0x02U, 0x06U, 0x18U, 0x10U, 0x00U, 0x10U, 0x04U, 0x14U, 0x05U, + 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x06U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x01U, 0x88U, 0x15U, 0xFFU, 0x01U, 0x8CU, 0x15U, 0xFFU, 0x01U, 0x90U, 0x15U, 0xFFU, + 0x01U, 0x94U, 0x15U, 0xFFU, 0x11U, 0x08U, 0x20U, 0x00U, 0x05U, 0x00U, 0x22U, 0x32U, + 0x11U, 0x0CU, 0x30U, 0x00U, 0x05U, 0x04U, 0x32U, 0x32U, 0x11U, 0x10U, 0x40U, 0x00U, + 0x05U, 0x08U, 0x42U, 0x32U, 0x11U, 0x14U, 0x50U, 0x00U, 0x05U, 0x0CU, 0x52U, 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0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0xDAU, 0x76U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0xB0U, 0x05U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x44U, 0x00U, 0x27U, + 0x00U, 0x00U, 0xD4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x02U, 0x04U, 0x4FU, 0x01U, 0x02U, 0xC0U, 0x45U, 0x00U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x77U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xAAU, 0x77U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x77U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x77U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x0AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x78U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x6AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x78U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xCAU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x78U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x0AU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x2AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x8AU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x79U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xEAU, 0x79U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x0AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x4AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x6AU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xAAU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xCAU, 0x7AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xEAU, 0x7AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x0AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x2AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x4AU, 0x7BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x6AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x8AU, 0x7BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xAAU, 0x7BU, 0x20U, + 0x00U, 0x00U, 0xF4U, 0x03U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, + 0x02U, 0x80U, 0x45U, 0x00U, 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, + 0x00U, 0x08U, 0x06U, 0x06U, 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x02U, 0x40U, 0x05U, 0x00U, + 0x00U, 0x00U, 0x04U, 0x00U, 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x24U, 0x0FU, 0x02U, + 0x02U, 0xC0U, 0x45U, 0x00U, 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x4AU, 0x7CU, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x1CU, 0xF4U, 0x0FU, 0x05U, 0x10U, 0x70U, 0x32U, + 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x10U, 0x04U, 0x18U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x20U, 0x32U, 0x04U, 0x4CU, 0x20U, 0x32U, + 0x04U, 0x90U, 0x20U, 0x32U, 0x04U, 0xD4U, 0x20U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, + 0x04U, 0x1CU, 0x21U, 0x32U, 0x04U, 0x4CU, 0x21U, 0x32U, 0x04U, 0x90U, 0x21U, 0x32U, + 0x04U, 0xD4U, 0x21U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, 0x02U, 0x04U, 0x3CU, 0x01U, + 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0xA2U, 0x7DU, 0x20U +}; +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_FLEXIO_ONLY) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x28U, 0x00U, 0x10U, 0x24U, 0x08U, 0x01U, 0x10U, 0x24U, 0x90U, 0x02U, 0x10U, 0x24U, 0xCCU, 0x01U, 0x10U, 0x24U, + 0x30U, 0x03U, 0x10U, 0x24U, 0x80U, 0x08U, 0x10U, 0x24U, 0x94U, 0x0AU, 0x10U, 0x24U, 0x08U, 0x0DU, 0x10U, 0x24U, + 0x80U, 0x0FU, 0x10U, 0x24U, 0x34U, 0x12U, 0x10U, 0x24U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 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0x02U, 0x20U, 0x05U, 0x00U, 0x32U, 0x32U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x00U, 0x22U, 0x32U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x04U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x04U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x04U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x08U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x08U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, + 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x0CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x0CU, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x0CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x10U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x10U, 0x32U, 0x32U, + 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x10U, 0x22U, 0x32U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x14U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x14U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, + 0x45U, 0x14U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, 0x06U, 0x48U, 0x47U, 0x02U, + 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, 0x01U, 0x0CU, 0x1CU, 0x01U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x22U, 0x32U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x18U, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, 0x41U, 0x08U, 0x1CU, 0x01U, + 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x18U, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x2AU, 0x24U, 0x20U, + 0x06U, 0x48U, 0x47U, 0x02U, 0x1AU, 0x80U, 0x10U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x01U, 0x08U, 0x1CU, 0x01U, + 0x01U, 0x0CU, 0x1CU, 0x01U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x22U, 0x32U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x05U, 0x1CU, 0x32U, 0x32U, 0x00U, 0x12U, 0x01U, 0x00U, + 0x41U, 0x08U, 0x1CU, 0x01U, 0x5CU, 0xB4U, 0x00U, 0x00U, 0x45U, 0x1CU, 0x22U, 0x32U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, + 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x15U, 0x2AU, 0x24U, 0x20U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x2CU, 0x14U, 0x10U, + 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, + 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x00U, 0x1CU, 0xF4U, 0x0FU, 0x05U, 0x10U, 0x70U, 0x32U, + 0x10U, 0x04U, 0x18U, 0x05U, 0x08U, 0x44U, 0x14U, 0x00U, 0x06U, 0x48U, 0xC7U, 0x04U, 0x1AU, 0x80U, 0x10U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, 0x04U, 0x1CU, 0x20U, 0x32U, + 0x04U, 0x4CU, 0x20U, 0x32U, 0x04U, 0x90U, 0x20U, 0x32U, 0x04U, 0xD4U, 0x20U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x04U, 0x1CU, 0x21U, 0x32U, + 0x04U, 0x4CU, 0x21U, 0x32U, 0x04U, 0x90U, 0x21U, 0x32U, 0x04U, 0xD4U, 0x21U, 0x32U, 0x02U, 0x04U, 0x7CU, 0x01U, + 0x02U, 0x04U, 0x3CU, 0x01U, 0x02U, 0x04U, 0x4CU, 0x01U, 0x02U, 0x04U, 0x5CU, 0x01U, 0x14U, 0x00U, 0x00U, 0x00U, + 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, + 0x0EU, 0x00U, 0x10U, 0x00U, 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x82U, 0x25U, 0x20U}; +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_ONLY) +const uint8_t s_smartdmaDisplayFirmware[] = { + 0x34U, 0x00U, 0x10U, 0x24U, 0x44U, 0x0EU, 0x10U, 0x24U, 0xA0U, 0x01U, 0x10U, 0x24U, + 0x64U, 0x10U, 0x10U, 0x24U, 0x64U, 0x04U, 0x10U, 0x24U, 0x14U, 0x14U, 0x10U, 0x24U, + 0x30U, 0x07U, 0x10U, 0x24U, 0xA0U, 0x08U, 0x10U, 0x24U, 0x70U, 0x0BU, 0x10U, 0x24U, + 0x74U, 0x17U, 0x10U, 0x24U, 0x00U, 0x1CU, 0x10U, 0x24U, 0x08U, 0x21U, 0x10U, 0x24U, + 0x24U, 0x24U, 0x10U, 0x24U, 0x12U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, + 0x00U, 0x2CU, 0x14U, 0x10U, 0x04U, 0x18U, 0x04U, 0x27U, 0x01U, 0x80U, 0x05U, 0x00U, + 0x01U, 0x84U, 0x05U, 0x01U, 0x01U, 0xB0U, 0x05U, 0x02U, 0x01U, 0x9CU, 0x05U, 0x03U, + 0x00U, 0x0CU, 0xC4U, 0x02U, 0x00U, 0xDEU, 0x01U, 0x00U, 0x35U, 0xCAU, 0x00U, 0x20U, + 0x15U, 0xF2U, 0x01U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, 0x60U, 0x08U, 0xC4U, 0x0FU, + 0x80U, 0x48U, 0x00U, 0x00U, 0x06U, 0x98U, 0x34U, 0x00U, 0x10U, 0x18U, 0x68U, 0x02U, + 0x04U, 0x1CU, 0x29U, 0x31U, 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0xF2U, 0x00U, 0x20U, + 0x01U, 0x10U, 0x1CU, 0x01U, 0x11U, 0x10U, 0x48U, 0x00U, 0x10U, 0x10U, 0x4CU, 0x10U, + 0x10U, 0xDCU, 0x40U, 0x48U, 0x05U, 0x80U, 0x72U, 0x31U, 0x10U, 0x0CU, 0x48U, 0x18U, + 0x08U, 0x9AU, 0x15U, 0x00U, 0x55U, 0xF2U, 0x00U, 0x20U, 0x04U, 0x1CU, 0x29U, 0x31U, + 0x08U, 0xDEU, 0x05U, 0x04U, 0x35U, 0x4AU, 0x01U, 0x20U, 0x0DU, 0x9AU, 0x34U, 0x00U, + 0x25U, 0x80U, 0x32U, 0x31U, 0x00U, 0x9CU, 0x9CU, 0x07U, 0x0CU, 0xDCU, 0x21U, 0x00U, + 0x06U, 0xDCU, 0x15U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x18U, 0xECU, 0x02U, 0x20U, + 0x05U, 0x84U, 0x72U, 0x31U, 0x04U, 0x5CU, 0x2AU, 0x31U, 0x04U, 0x1CU, 0x2AU, 0x31U, + 0x00U, 0x1CU, 0x14U, 0x00U, 0x05U, 0x88U, 0x72U, 0x31U, 0x00U, 0x0CU, 0xC4U, 0x03U, + 0x08U, 0x46U, 0x20U, 0x00U, 0xB5U, 0xCAU, 0x00U, 0x20U, 0x1CU, 0xB4U, 0x00U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x15U, 0x02U, 0x03U, 0x20U, 0x08U, 0x4AU, 0xC4U, 0x0FU, + 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0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x02U, 0x04U, 0x4FU, 0x01U, + 0x02U, 0xC0U, 0x45U, 0x00U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x48U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x48U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xFAU, 0x48U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x49U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x5AU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x49U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xBAU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x49U, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xFAU, 0x49U, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x1AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x5AU, 0x4AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x7AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x4AU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xDAU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xFAU, 0x4AU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x3AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x5AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x9AU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xBAU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x4BU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xFAU, 0x4BU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x1AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x3AU, 0x4CU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0x5AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x7AU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, + 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0x9AU, 0x4CU, 0x20U, + 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, 0x08U, 0x46U, 0x14U, 0x00U, + 0x55U, 0xBAU, 0x4CU, 0x20U, 0x00U, 0x04U, 0x46U, 0x00U, 0x12U, 0x00U, 0x00U, 0x00U, + 0x08U, 0x46U, 0x14U, 0x00U, 0x55U, 0xDAU, 0x4CU, 0x20U, 0x00U, 0x00U, 0xF4U, 0x03U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x20U, 0x0FU, 0x02U, 0x02U, 0x80U, 0x45U, 0x00U, + 0x00U, 0x00U, 0x0EU, 0x04U, 0x00U, 0x04U, 0x1CU, 0x01U, 0x00U, 0x08U, 0x06U, 0x06U, + 0x0CU, 0x14U, 0x10U, 0x00U, 0x0CU, 0x54U, 0x21U, 0x00U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x02U, 0x40U, 0x05U, 0x00U, 0x00U, 0x00U, 0x04U, 0x00U, + 0x02U, 0x04U, 0x0FU, 0x01U, 0x05U, 0x24U, 0x0FU, 0x02U, 0x02U, 0xC0U, 0x45U, 0x00U, + 0x14U, 0x00U, 0x00U, 0x00U, 0x00U, 0x28U, 0x04U, 0x00U, 0x00U, 0x00U, 0xBEU, 0x0DU, + 0x00U, 0x04U, 0xDCU, 0x06U, 0x00U, 0x08U, 0x66U, 0x0BU, 0x0EU, 0x00U, 0x10U, 0x00U, + 0x0EU, 0x2CU, 0x20U, 0x00U, 0x1CU, 0xB4U, 0x00U, 0x00U, 0x15U, 0x7AU, 0x4DU, 0x20U +}; +#endif +const uint32_t s_smartdmaDisplayFirmwareSize = sizeof(s_smartdmaDisplayFirmware); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +void SDMA_IRQHandler(void); +void SDMA_IRQHandler(void) +{ + SMARTDMA_HandleIRQ(); +} + +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_rt500.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_rt500.h new file mode 100644 index 0000000000..fe2c47f8b0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_smartdma_rt500.h @@ -0,0 +1,321 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SMARTDMA_RT500_H_ +#define FSL_SMARTDMA_RT500_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup smartdma_rt500 RT500 SMARTDMA Firmware + * @ingroup smartdma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SMARTDMA_DISPLAY_MIPI_AND_FLEXIO 0 +#define SMARTDMA_DISPLAY_MIPI_ONLY 1 +#define SMARTDMA_DISPLAY_FLEXIO_ONLY 2 + +/* Select firmware for MIPI and FLEXIO by default. */ +#ifndef SMARTDMA_DISPLAY_FIRMWARE_SELECT +#define SMARTDMA_DISPLAY_FIRMWARE_SELECT SMARTDMA_DISPLAY_MIPI_AND_FLEXIO +#endif + +/*! @brief The firmware used for display. */ +extern const uint8_t s_smartdmaDisplayFirmware[]; + +/*! @brief The s_smartdmaDisplayFirmware firmware memory address. */ +#define SMARTDMA_DISPLAY_MEM_ADDR 0x24100000U + +/*! @brief Size of s_smartdmaDisplayFirmware */ +#define SMARTDMA_DISPLAY_FIRMWARE_SIZE (s_smartdmaDisplayFirmwareSize) + +/*! @brief Size of s_smartdmaDisplayFirmware */ +extern const uint32_t s_smartdmaDisplayFirmwareSize; + +#if (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_AND_FLEXIO) +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_RGB565To888, /*!< Convert RGB565 to RGB888 and save to output memory, use parameter + smartdma_rgb565_rgb888_param_t. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to + FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_RGB888_DMA, /*!< Send RGB888 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB888_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_DMA, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_param_t */ + kSMARTDMA_MIPI_XRGB2RGB_DMA2D, /*!< Send XRGB8888 data to MIPI DSI, use parameter + smartdma_dsi_2d_param_t. */ + kSMARTDMA_MIPI_RGB565_R180_DMA, /*!< Send RGB565 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_R180_DMA, /*!< Send RGB888 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_R180_DMA, /*!< Send XRGB8888 data to MIPI DSI, Rotate 180, use parameter + smartdma_dsi_param_t */ + kSMARTDMA_MIPI_RGB5652RGB888_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA, /*!< Send RGB888 data to MIPI DSI with checker board pattern, + use parameter smartdma_dsi_checkerboard_param_t. */ + kSMARTDMA_MIPI_Enter_ULPS, /*!< Set MIPI-DSI to enter ultra low power state. */ + kSMARTDMA_MIPI_Exit_ULPS, /*!< Set MIPI-DSI to exit ultra low power state. */ + kSMARTDMA_FlexIO_DMA_ONELANE, /*!< FlexIO DMA for one SHIFTBUF, Write Data to SHIFTBUF[OFFSET] */ + kSMARTDMA_FlexIO_FIFO2RAM, /*!< Read data from FlexIO FIFO to ram space. */ +}; + +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_MIPI_ONLY) + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_MIPI_RGB565_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB565_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_RGB888_DMA, /*!< Send RGB888 data to MIPI DSI, use parameter smartdma_dsi_param_t. */ + kSMARTDMA_MIPI_RGB888_DMA2D, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_2d_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_DMA, /*!< Send XRGB8888 data to MIPI DSI, use parameter smartdma_dsi_param_t */ + kSMARTDMA_MIPI_XRGB2RGB_DMA2D, /*!< Send XRGB8888 data to MIPI DSI, use parameter + smartdma_dsi_2d_param_t. */ + kSMARTDMA_MIPI_RGB565_R180_DMA, /*!< Send RGB565 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_R180_DMA, /*!< Send RGB888 data to MIPI DSI, Rotate 180, use parameter + * smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_XRGB2RGB_R180_DMA, /*!< Send XRGB8888 data to MIPI DSI, Rotate 180, use parameter + smartdma_dsi_param_t */ + kSMARTDMA_MIPI_RGB5652RGB888_DMA, /*!< Send RGB565 data to MIPI DSI, use parameter smartdma_dsi_param_t. + */ + kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA, /*!< Send RGB888 data to MIPI DSI with checker board pattern, + use parameter smartdma_dsi_checkerboard_param_t. */ + kSMARTDMA_MIPI_Enter_ULPS, /*!< Set MIPI-DSI to enter ultra low power state. */ + kSMARTDMA_MIPI_Exit_ULPS, /*!< Set MIPI-DSI to exit ultra low power state. */ +}; + +#elif (SMARTDMA_DISPLAY_FIRMWARE_SELECT == SMARTDMA_DISPLAY_FLEXIO_ONLY) + +/*! + * @brief The API index when using s_smartdmaDisplayFirmware. + */ +enum _smartdma_display_api +{ + kSMARTDMA_FlexIO_DMA_Endian_Swap = 0U, + kSMARTDMA_FlexIO_DMA_Reverse32, + kSMARTDMA_FlexIO_DMA, + kSMARTDMA_FlexIO_DMA_Reverse, /*!< Send data to FlexIO with reverse order. */ + kSMARTDMA_FlexIO_DMA_RGB565To888, /*!< Convert RGB565 to RGB888 and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB, /*!< Convert ARGB to RGB and send to FlexIO, use parameter + smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap, /*!< Convert ARGB to RGB, then swap endian, and send to FlexIO, use + parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ARGB2RGB_Endian_Swap_Reverse, /*!< Convert ARGB to RGB, then swap endian and reverse, and send + to FlexIO, use parameter smartdma_flexio_mculcd_param_t. */ + kSMARTDMA_FlexIO_DMA_ONELANE, /*!< FlexIO DMA for one SHIFTBUF, Write Data to SHIFTBUF[OFFSET] */ + kSMARTDMA_FlexIO_FIFO2RAM, /*!< Read data from FlexIO FIFO to ram space. */ +}; +#endif + +/*! + * @brief Parameter for FlexIO MCULCD except kSMARTDMA_FlexIO_DMA_ONELANE + */ +typedef struct _smartdma_flexio_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_flexio_mculcd_param_t; + +/*! + * @brief Parameter for kSMARTDMA_FlexIO_DMA_ONELANE + */ +typedef struct _smartdma_flexio_onelane_mculcd_param +{ + uint32_t *p_buffer; + uint32_t buffersize; + uint32_t offset; + uint32_t *smartdma_stack; +} smartdma_flexio_onelane_mculcd_param_t; + +/*! + * @brief Parameter for MIPI DSI + */ +typedef struct _smartdma_dsi_param +{ + /*! Pointer to the buffer to send. */ + const uint8_t *p_buffer; + /*! Buffer size in byte. */ + uint32_t buffersize; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * format is RGB565: + * LSB MSB + * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_param_t; + +/*! + * @brief Parameter for kSMARTDMA_MIPI_RGB565_DMA2D, kSMARTDMA_MIPI_RGB888_DMA2D + * and kSMARTDMA_MIPI_XRGB2RGB_DMA2D. + */ +typedef struct _smartdma_dsi_2d_param +{ + /*! Pointer to the buffer to send. */ + const uint8_t *p_buffer; + /*! SRC data transfer in a minor loop */ + uint32_t minorLoop; + /*! SRC data offset added after a minor loop */ + uint32_t minorLoopOffset; + /*! SRC data transfer in a major loop */ + uint32_t majorLoop; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * format is RGB565: + * LSB MSB + * B0 B1 B2 B3 B4 G0 G1 G2 | G3 G4 G5 R0 R1 R2 R3 R4 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * G3 G4 G5 R0 R1 R2 R3 R4 | B0 B1 B2 B3 B4 G0 G1 G2 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_2d_param_t; + +/*! + * @brief Parameter for kSMARTDMA_MIPI_RGB888_CHECKER_BOARD_DMA + */ +typedef struct _smartdma_dsi_checkerboard_param +{ + /*! Pointer to the buffer to send, pixel format is ARGB8888. */ + const uint8_t *p_buffer; + uint32_t height; /*! Height resolution in pixel. */ + uint32_t width; /*! Width resolution in pixel. */ + /*! Cube block type. + * cbType=1 : 1/2 pixel mask cases + * cbType=2 : 1/4 pixel mask cases + */ + uint32_t cbType; + /*! which pixel is turned off in each type + * cbType=2: indexOff= 1,2,3,4 + * cbType=1: indexOff= 0,1 + */ + uint32_t indexOff; + /*! Stack used by SMARTDMA. */ + uint32_t *smartdma_stack; + /*! + * If set to 1, the pixels are filled to MIPI DSI FIFO directly. + * If set to 0, the pixel bytes are swapped then filled to + * MIPI DSI FIFO. For example, when set to 0 and frame buffer pixel + * for example + * format is RGB888: + * LSB MSB + * B0 B1 B2 B3 B4 B5 B6 B7 | G0 G1 G2 G3 G4 G5 G6 G7 | R0 R1 R2 R3 R4 R5 R6 R7 + * Then the pixel filled to DSI FIFO is: + * LSB MSB + * R0 R1 R2 R3 R4 R5 R6 R7 | G0 G1 G2 G3 G4 G5 G6 G7 | B0 B1 B2 B3 B4 B5 B6 B7 + */ + uint32_t disablePixelByteSwap; +} smartdma_dsi_checkerboard_param_t; + +/*! + * @brief Parameter for RGB565To888 + */ +typedef struct _smartdma_rgb565_rgb888_param +{ + uint32_t *inBuf; + uint32_t *outBuf; + uint32_t buffersize; + uint32_t *smartdma_stack; +} smartdma_rgb565_rgb888_param_t; + +/*! + * @brief Parameter for all supported APIs. + */ +typedef union +{ + /*! Parameter for flexio MCULCD. */ + smartdma_flexio_mculcd_param_t flexioMcuLcdParam; + /*! Parameter for flexio MCULCD with one shift buffer. */ + smartdma_flexio_onelane_mculcd_param_t flexioOneLineMcuLcdParam; + /*! Parameter for MIPI DSI functions. */ + smartdma_dsi_param_t dsiParam; + /*! Parameter for MIPI DSI 2D functions. */ + smartdma_dsi_2d_param_t dsi2DParam; + /*! Parameter for MIPI DSI checker board functions. */ + smartdma_dsi_checkerboard_param_t dsiCheckerBoardParam; + /*! Parameter for RGB565_RGB888 convertion. */ + smartdma_rgb565_rgb888_param_t rgb565_rgb888Param; +} smartdma_param_t; + +typedef struct +{ + uint8_t RESERVED_0[32]; + __IO uint32_t BOOTADR; /* 0x20 */ + __IO uint32_t CTRL; /* 0x24 */ + __I uint32_t PC; /* 0x28 */ + __I uint32_t SP; /* 0x2C */ + __IO uint32_t BREAK_ADDR; /* 0x30 */ + __IO uint32_t BREAK_VECT; /* 0x34 */ + __IO uint32_t EMER_VECT; /* 0x38 */ + __IO uint32_t EMER_SEL; /* 0x3C */ + __IO uint32_t ARM2EZH; /* 0x40 */ + __IO uint32_t EZH2ARM; /* 0x44 */ + __IO uint32_t PENDTRAP; /* 0x48 */ +} SMARTDMA_Type; + +#define SMARTDMA_BASE 0x40027000 +#define SMARTDMA ((volatile SMARTDMA_Type *)SMARTDMA_BASE) + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#if defined(__cplusplus) +} +#endif + +/* @} */ + +#endif /* FSL_SMARTDMA_RT500_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_spc.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_spc.c new file mode 100644 index 0000000000..fa09ae1f40 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_spc.c @@ -0,0 +1,1753 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_spc" +#endif + +/* + * $Coverage Justification Reference$ + * + * $Justification spc_c_ref_1$ + * The SPC busy status flag is too short to get coverage data. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets selected power domain's requested low power mode. + * + * param base SPC peripheral base address. + * param powerDomainId Power Domain Id, please refer to spc_power_domain_id_t. + * + * return The selected power domain's requested low power mode, please refer to spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + + uint32_t val; + + val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT); + return (spc_power_domain_low_power_mode_t)val; +} + +/*! + * brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * param base SPC peripheral base address. + * return Current isolation status for each power domains. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base) +{ + uint32_t reg; + + reg = base->SC; + return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT); +} + +/*! + * brief Configs Low power request output pin. + * + * This function configs the low power request output pin + * + * param base SPC peripheral base address. + * param config Pointer the spc_LowPower_Request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = base->LPREQ_CFG; + reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK); + + if (config->enable) + { + reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) | + SPC_LPREQ_CFG_LPREQOV((uint8_t)(config->override)); + } + else + { + reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK; + } + + base->LPREQ_CFG = reg; +} + +/*! + * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * param base SPC peripheral base address. + * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = (base->VDD_CORE_GLITCH_DETECT_SC) & + ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK); + + reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) | + SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) | + SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt); + + base->VDD_CORE_GLITCH_DETECT_SC = reg; +} + +/*! + * brief Set SRAM operate voltage. + * + * param base SPC peripheral base address. + * param config The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= SPC_SRAMCTL_VSM(config->operateVoltage); + + base->SRAMCTL = reg; + + if (config->requestVoltageUpdate) + { + base->SRAMCTL |= SPC_SRAMCTL_REQ_MASK; + while ((base->SRAMCTL & SPC_SRAMCTL_ACK_MASK) == 0UL) + { + /* Wait until acknowledged */ + ; + } + base->SRAMCTL &= ~SPC_SRAMCTL_REQ_MASK; + } +} + +/*! + * brief Configs Bandgap mode in Active mode. + * + * note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to + * disable Bandgap in active mode + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * retval kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->ACTIVE_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = SPC_GetActiveModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + } + + reg &= ~SPC_ACTIVE_CFG_BGMODE_MASK; + reg |= SPC_ACTIVE_CFG_BGMODE(mode); + + base->ACTIVE_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs Bandgap mode in Low Power mode. + * + * This function configs Bandgap mode in Low Power mode. + * IF user wants to disable Bandgap while keeping any of the Regulator in Normal Driver Strength + * or if any of the High voltage detectors/Low voltage detectors are kept enabled, the Bandgap mode + * will be set as Bandgap Enabled with Buffer Disabled. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->LP_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == + SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) == + SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + reg &= ~SPC_LP_CFG_BGMODE_MASK; + reg |= SPC_LP_CFG_BGMODE(mode); + base->LP_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs CORE voltage detect options. + * + * This function configs CORE voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U); + + base->VD_CORE_CFG = reg; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * brief Enables the Core High Voltage Detector in Active mode. + * + * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * retval kStatus_Success Enable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + + return status; +} + + +/*! + * brief Enables the Core High Voltage Detector in Low Power mode. + * + * note If the CORE_LDO high voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each regulator + * must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * retval kStatus_Success Enable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_HVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! + * brief Enables the Core Low Voltage Detector in Active mode. + * + * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core Low Voltage Detector in Low Power mode. + * + * note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * param base SPC peripheral base address. + * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + uint32_t reg; + + reg = base->VD_SYS_CFG; + /* Before changing voltage level, must disable low voltage detect interrupt and reset. */ + base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK); + reg |= SPC_VD_SYS_CFG_LVSEL(level); + + base->VD_SYS_CFG = reg; +} + +/*! + * brief Configs SYS voltage detect options. + * + * This function config SYS voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_SYS_CFG_HVDIE(1U) : SPC_VD_SYS_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_SYS_CFG_LVDIE(1U) : SPC_VD_SYS_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_SYS_CFG_HVDRE(1U) : SPC_VD_SYS_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_SYS_CFG_LVDRE(1U) : SPC_VD_SYS_CFG_LVDRE(0U); + + base->VD_SYS_CFG = reg; + + /* Set trip voltage level. */ + SPC_SetSystemVDDLowVoltageLevel(base, config->level); +} + +/*! + * brief Enables the System High Voltage Detector in Active mode. + * + * note If the System_LDO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of + * each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * retval kStatus_Success Enable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System Low Voltage Detector in Active mode. + * + * note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * retval kStatus_Success Enable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System High Voltage Detector in Low Power mode. + * + * note If the System_LDO high voltage detect is enabled in low power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * retval kStatus_Success Enable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System Low Voltage Detector in Low Power mode. + * + * note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * retval kStatus_Success Enable System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_LVDE_MASK; + } + + return status; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * param base SPC peripheral base address. + * param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + uint32_t reg; + + reg = base->VD_IO_CFG; + + base->VD_IO_CFG &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_LVSEL_MASK); + reg |= SPC_VD_IO_CFG_LVSEL(level); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Configs IO voltage detect options. + * + * This function config IO voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_IO_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + /* Set trip voltage level. */ + SPC_SetIOVDDLowVoltageLevel(base, config->level); + + reg = base->VD_IO_CFG; + reg &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_HVDRE_MASK | SPC_VD_IO_CFG_HVDIE_MASK); + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_IO_CFG_HVDIE(1U) : SPC_VD_IO_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_IO_CFG_LVDIE(1U) : SPC_VD_IO_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_IO_CFG_HVDRE(1U) : SPC_VD_IO_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_IO_CFG_LVDRE(1U) : SPC_VD_IO_CFG_LVDRE(0U); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Enables the IO High Voltage Detector in Active mode. + * + * note If the IO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * retval kStatus_Success Enable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO Low Voltage Detector in Active mode. + * + * note If the IO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO High Voltage Detector in Low Power mode. + * + * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * retval kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO Low Voltage Detector in Low Power mode. + * + * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_LVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * param base SPC peripheral base address. + * param lowPowerIsoMask The mask of external domains isolate enable during low power mode. + * param IsoMask The mask of external domains isolate. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask) +{ + uint32_t reg = 0UL; + + reg |= SPC_EVD_CFG_REG_EVDISO(IsoMask) | SPC_EVD_CFG_REG_EVDLPISO(lowPowerIsoMask); + base->EVD_CFG = reg; +} + +/*! + * brief Configs Core LDO VDD Regulator in Active mode. + * + * note If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + * note Core VDD level for the Core LDO low power regulator can only be changed when CORELDO_VDD_DS is normal + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Core_LDO_option_t structure. + * + * retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, core_ldo's drive strength can not + * set to low. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) && (SPC_GetActiveModeCoreLDODriveStrength(base) == kSPC_CoreLDO_LowDriveStrength) && (option->CoreLDOVoltage != SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))) + { + /* In active mode, CORE_LDO voltage level should only be changed when the CORE_LDO is in Normal strength. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + if ((option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) && (SPC_GetActiveModeCoreLDODriveStrength(base) == kSPC_CoreLDO_NormalDriveStrength)) + { + /* Change Voltage level firstly. */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + /* Then change drive strength. */ + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + } + + if (option->CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* Change drive strength firstly. */ + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + /* Then change Voltage level. */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } +#else /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | + SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel)); + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | + SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength is set as Normal. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure. + * retval kStatus_Success Config Core LDO regulator in power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in low powermode is wrong. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option) +{ + status_t status = kStatus_Success; + spc_core_ldo_drive_strength_t activeCoreLdoDS = kSPC_CoreLDO_NormalDriveStrength; + + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + activeCoreLdoDS = SPC_GetActiveModeCoreLDODriveStrength(base); +#endif /* (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) */ + + if ((option->CoreLDODriveStrength == activeCoreLdoDS) && (option->CoreLDOVoltage != SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))) + { + /* If attemp to set to same drive strength as active mode, voltage level must same in active mode and low power mode. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + if ((option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength) && (option->CoreLDOVoltage != SPC_GetLowPowerCoreLDOVDDVoltageLevel(base))) + { + /* Can change core VDD levels for the LDO_CORE low power regulator only when the LDO_CORE is work as normal drive strength. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + if (status == kStatus_Success) + { + status = SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * param base SPC peripheral base address. + * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((SPC_GetLowPowerCoreLDOVDDDriveStrength(base) == kSPC_CoreLDO_NormalDriveStrength) && ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base))) + { + /* If LDO_CORE VDD Drive strength is set as normal, the voltage level in active mode and low power mode must be same. */ + return kStatus_SPC_CORELDOVoltageWrong; + } + + if ((SPC_GetLowPowerCoreLDOVDDDriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength) && ((uint8_t)SPC_GetLowPowerCoreLDOVDDVoltageLevel(base) != (uint8_t)voltageLevel)) + { + /* Voltage level for the LDO_CORE low power regulatorcan only be changed when core LDO work as normal drive strength. */ + return kStatus_SPC_CORELDOVoltageSetFail; + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel)); + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + else + { + /* To specify normal drive strength, the bandgap must be enabled in low power mode. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | + SPC_LP_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * brief Configs System LDO VDD Regulator in Active mode. + * + * This function configs System LDO VDD Regulator in Active mode. + * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enable the bandgap. + * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. + * Otherwise it will be fail to regulator to Over Drive Voltage. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure. + * retval kStatus_Success Config System LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option) +{ + assert(option != NULL); + + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + if (status == kStatus_Success) + { + status = SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel) +{ + if (voltageLevel == kSPC_SysLDO_OverDriveVoltage) + { + /* Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + } + + base->ACTIVE_CFG = (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | + SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_SysLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * param base SPC peripheral base address. + * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure. + * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option) +{ + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set System LDO Regulator drive strength in Low Power Mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + else + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * brief Configs DCDC VDD Regulator in Active mode. + * + * Before switching DCDC drive strength from low to normal, the DCDC voltage level should be configured back to + * what it was before switching to low drive strength. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_DCDC_option_t structure. + * retval kStatus_Success Config DCDC regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option) +{ + assert(option != NULL); + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + + if (status == kStatus_Success) + { + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_LowDriveStrength) + { + /*If enabled LVDs or HVDs, and attempt to specify low drive strength, + SPC will ignore the attempt. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_DCDCLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs DCDC VDD Regulator in Low power modes. + * + * This function configs DCDC VDD Regulator in Low Power modes. + * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * If any of voltage detectors are kept enabled, configuration to set DCDC VDD Drive Strength to Low or Pulse mode + * will be ignored. + * In Deep Power Down mode, DCDC regulator is always turned off. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure. + * retval kStatus_Success Config DCDC regulator in low power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option) +{ + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + if (status == kStatus_Success) + { + SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_LowDriveStrength) + { + /*If enabled LVDs or HVDs, and attempt to specify low drive strength, + SPC will ignore the attempt. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_DCDCLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Config DCDC Burst options + * + * param base SPC peripheral base address. + * param config Pointer to spc_DCDC_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config) +{ + assert(config != NULL); + uint32_t reg; + reg = base->DCDC_CFG; + reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK); + reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq); + reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U); + base->DCDC_CFG = reg; + + /* Clear DCDC burst acknowledge flag. */ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest); + + if (config->sofwareBurstRequest) + { + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0U) + { + } + /* DCDC burst request has completed and acknowledged, need to clear this flag. */ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; + } +} + +/*! + * brief Set the count value of the reference clock. + * + * This function set the count value of the reference clock to control the frequency + * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * + * param base SPC peripheral base address. + * param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count) +{ + uint32_t reg; + + reg = base->DCDC_BURST_CFG; + reg &= ~SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK; + reg |= SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(count); + + base->DCDC_BURST_CFG = reg; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + +/*! + * brief Configs regulators in Active mode. + * + * This function provides the method to config all on-chip regulators in active mode. + * + * param base SPC peripheral base address. + * param config Pointer to spc_active_mode_regulators_config_t structure. + * retval kStatus_Success Config regulators in Active power mode successful. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config) +{ + assert(config != NULL); + + status_t status; + bool bandgapConfigured = false; + spc_bandgap_mode_t curBandgapMode = SPC_GetActiveModeBandgapMode(base); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if (((config->DCDCOption.DCDCDriveStrength) == kSPC_DCDC_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + if (((config->CoreLDOOption.CoreLDODriveStrength) == kSPC_CoreLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if (((config->SysLDOOption.SysLDODriveStrength) == kSPC_SysLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->ACTIVE_CFG = ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + /* Must specify the same level for both DCDC and CORE LDO, even if LDO_CORE is off. */ + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if (SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) < (config->CoreLDOOption.CoreLDOVoltage)) + { + /* If want to switch to higher voltage level. */ + + /* Set DCDC configuration previously. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + status = SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + if (status == kStatus_Success) + { + /* Configure CORE LDO after DCDC is configured successfully. */ + status = SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + } + else + { + return status; + } + } + else + { + /* If want to switch to lower/same voltage level. */ + + /* Set LDO configuration previously. */ + status = SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if (status == kStatus_Success) + { + /* Configure DCDC after CORE_LDO is configured successfully. */ + status = SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); + } + else + { + return status; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + } + + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + status = SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + if (status == kStatus_Success) + { + if (bandgapConfigured == false) + { + status = SPC_SetActiveModeBandgapModeConfig(base, config->bandgapMode); + } +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + if (status == kStatus_Success) + { + SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff); + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + } + } + return status; +} + +/*! + * brief Configs regulators in Low Power mode. + * + * This function provides the method to config all on-chip regulators in Low Power mode. + * + * param base SPC peripheral base address. + * param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * retval kStatus_Success Config regulators in Low power mode successful. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + bool bandgapConfigured = false; + spc_bandgap_mode_t curBandgapMode = SPC_GetActiveModeBandgapMode(base); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if (((config->DCDCOption.DCDCDriveStrength) == kSPC_DCDC_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if (((config->CoreLDOOption.CoreLDODriveStrength) == kSPC_CoreLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if (((config->SysLDOOption.SysLDODriveStrength) == kSPC_SysLDO_NormalDriveStrength) && (bandgapConfigured == false)) + { + if (curBandgapMode == kSPC_BandgapDisabled) + { + if ((config->bandgapMode) == kSPC_BandgapDisabled) + { + /* Bandgap must be enabled if any regulator attemp to work as normal drive strength. */ + return kStatus_SPC_BandgapModeWrong; + } + else + { + /* Set bandgap firstly, if current bandgap is disabled and attempt to set regulator as normal drive + strength. */ + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); + bandgapConfigured = true; + } + } + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + /* Must specify the same level for both DCDC and CORE LDO, even if LDO_CORE is off. */ + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + status = SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + status = SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + status = SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + if (status == kStatus_Success) + { + if (bandgapConfigured == false) + { + status = SPC_SetLowPowerModeBandgapmodeConfig(base, config->bandgapMode); + } + if (status == kStatus_Success) + { +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableLowPowerModeCMPBandgapBufferMode(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + } + } + } + } + + return status; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_spc.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_spc.h new file mode 100644 index 0000000000..3562838505 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_spc.h @@ -0,0 +1,2223 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SPC_H_ +#define FSL_SPC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_spc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPC driver version 2.2.1. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) +/*@}*/ + +#define SPC_EVD_CFG_REG_EVDISO_SHIFT 0UL +#define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL +#define SPC_EVD_CFG_REG_EVDSTAT_SHIFT 16UL + +#define SPC_EVD_CFG_REG_EVDISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDSTAT(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT) + +#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)) +#define VDD_CORE_GLITCH_DETECT_SC GLITCH_DETECT_SC +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG +#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK SPC_GLITCH_DETECT_SC_LOCK_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT SPC_GLITCH_DETECT_SC_CNT_SELECT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK SPC_GLITCH_DETECT_SC_RE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE SPC_GLITCH_DETECT_SC_RE +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK SPC_GLITCH_DETECT_SC_TIMEOUT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT SPC_GLITCH_DETECT_SC_TIMEOUT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK SPC_GLITCH_DETECT_SC_IE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE SPC_GLITCH_DETECT_SC_IE +#endif + +/*! + * @brief SPC status enumeration. + * + * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual + * to check. + */ +enum +{ + kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any + type of power mode transition. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be + ignored for LVD/HVD enabled. */ + kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive + strength setting be ignored for LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive + voltage failed for SYS LDO HVD must be disabled. */ + kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U), /*!< SYS LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ + kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO voltage is wrong. */ + kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U), /*!< Core LDO voltage set fail. */ + kStatus_SPC_BandgapModeWrong = MAKE_STATUS(kStatusGroup_SPC, 6U), /*!< Selected Bandgap Mode wrong. */ +}; + +/*! + * @brief Voltage Detect Status Flags. + */ +enum _spc_voltage_detect_flags +{ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK, /*!< IO VDD High-Voltage detect flag. */ + kSPC_IOVDDLowVoltageDetectFlag = SPC_VD_STAT_IOVDD_LVDF_MASK, /*!< IO VDD Low-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */ + kSPC_SystemVDDLowVoltageDetectFlag = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage detect flag. */ +}; + +/*! + * @brief SPC power domain isolation status. + * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to + * check. + */ +enum _spc_power_domains +{ + kSPC_MAINPowerDomainRetain = 1UL << 16U, /*!< Peripherals and IO pads retain in MAIN Power Domain. */ + kSPC_WAKEPowerDomainRetain = 1UL << 17U, /*!< Peripherals and IO pads retain in WAKE Power Domain. */ +}; + +/*! + * @brief The enumeration of all analog module that can be controlled by SPC in active or low-power modes. + * @anchor spc_analog_module_control + */ +enum _spc_analog_module_control +{ + kSPC_controlVref = 1UL << 0UL, /*!< Enable/disable VREF in active or low-power modes. */ + kSPC_controlUsb3vDet = 1UL << 1UL, /*!< Enable/disable USB3V_Det in active or low-power modes. */ + kSPC_controlDac0 = 1UL << 4UL, /*!< Enable/disable DAC0 in active or low-power modes. */ + kSPC_controlDac1 = 1UL << 5UL, /*!< Enable/disable DAC1 in active or low-power modes. */ + kSPC_controlDac2 = 1UL << 6UL, /*!< Enable/disable DAC2 in active or low-power modes. */ + kSPC_controlOpamp0 = 1UL << 8UL, /*!< Enable/disable OPAMP0 in active or low-power modes. */ + kSPC_controlOpamp1 = 1UL << 9UL, /*!< Enable/disable OPAMP1 in active or low-power modes. */ + kSPC_controlOpamp2 = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */ + kSPC_controlCmp0 = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */ + kSPC_controlCmp1 = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */ + kSPC_controlCmp2 = 1UL << 18UL, /*!< Enable/disable CMP2 in active or low-power modes. */ + kSPC_controlCmp0Dac = 1UL << 20UL, /*!< Enable/disable CMP0_DAC in active or low-power modes. */ + kSPC_controlCmp1Dac = 1UL << 21UL, /*!< Enable/disable CMP1_DAC in active or low-power modes. */ + kSPC_controlCmp2Dac = 1UL << 22UL, /*!< Enable/disable CMP2_DAC in active or low-power modes. */ + kSPC_controlAllModules = 0x770773UL, /*!< Enable/disable all modules in active or low-power modes. */ +}; + +/*! + * @brief The enumeration of spc power domain, the connected power domain is chip specfic, please refer to chip's RM + * for details. + */ +typedef enum _spc_power_domain_id +{ + kSPC_PowerDomain0 = 0U, /*!< Power domain0, the connected power domain is chip specific. */ + kSPC_PowerDomain1 = 1U, /*!< Power domain1, the connected power domain is chip specific. */ +} spc_power_domain_id_t; + +/*! + * @brief The enumeration of Power domain's low power mode. + */ +typedef enum _spc_power_domain_low_power_mode +{ + kSPC_SleepWithSYSClockRunning = 0U, /*!< Power domain request SLEEP mode with SYS clock running. */ + kSPC_DeepSleepWithSysClockOff = 1U, /*!< Power domain request deep sleep mode with system clock off. */ + kSPC_PowerDownWithSysClockOff = 2U, /*!< Power domain request power down mode with system clock off. */ + kSPC_DeepPowerDownWithSysClockOff = 4U, /*!< Power domain request deep power down mode with system clock off. */ +} spc_power_domain_low_power_mode_t; + +/*! + * @brief SPC low power request output pin polarity. + */ +typedef enum _spc_lowPower_request_pin_polarity +{ + kSPC_HighTruePolarity = 0x0U, /*!< Control the High Polarity of the Low Power Reqest Pin. */ + kSPC_LowTruePolarity = 0x1U, /*!< Control the Low Polarity of the Low Power Reqest Pin. */ +} spc_lowpower_request_pin_polarity_t; + +/*! + * @brief SPC low power request output override. + */ +typedef enum _spc_lowPower_request_output_override +{ + kSPC_LowPowerRequestNotForced = 0x0U, /*!< Not Forced. */ + kSPC_LowPowerRequestReserved = 0x1U, /*!< Reserved. */ + kSPC_LowPowerRequestForcedLow = 0x2U, /*!< Forced Low (Ignore LowPower request output polarity setting.) */ + kSPC_LowPowerRequestForcedHigh = 0x3U, /*!< Forced High (Ignore LowPower request output polarity setting.) */ +} spc_lowpower_request_output_override_t; + +/*! + * @brief SPC Bandgap mode enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_bandgap_mode +{ + kSPC_BandgapDisabled = 0x0U, /*!< Bandgap disabled. */ + kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */ + kSPC_BandgapEnabledBufferEnabled = 0x2U, /*!< Bandgap enabled with Buffer enabled. */ + kSPC_BandgapReserved = 0x3U, /*!< Reserved. */ +} spc_bandgap_mode_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode. + */ +typedef enum _spc_dcdc_voltage_level +{ + kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC VDD Regulator regulate to Mid Voltage(1.0V). */ + kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC VDD Regulator regulate to Normal Voltage(1.1V). */ + kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC VDD Regulator regulate to Safe-Mode Voltage(1.2V). */ +} spc_dcdc_voltage_level_t; + +/*! + * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode. + */ +typedef enum _spc_dcdc_drive_strength +{ + kSPC_DCDC_PulseRefreshMode = 0x0U, /*!< DCDC VDD Regulator Drive Strength set to Pulse Refresh Mode, + * This enum member is only useful for Low Power Mode config, please + * note that pluse refresh mode is invalid in SLEEP mode. + */ + kSPC_DCDC_LowDriveStrength = 0x1U, /*!< DCDC VDD regulator Drive Strength set to low. */ + kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC VDD regulator Drive Strength set to Normal. */ +} spc_dcdc_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief SYS LDO regulator voltage level enumeration in Active mode. + */ +typedef enum _spc_sys_ldo_voltage_level +{ + kSPC_SysLDO_NormalVoltage = 0x0U, /*!< SYS LDO VDD Regulator regulate to Normal Voltage(1.8V). */ + kSPC_SysLDO_OverDriveVoltage = 0x1U, /*!< SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V). */ +} spc_sys_ldo_voltage_level_t; + +/*! + * @brief SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_sys_ldo_drive_strength +{ + kSPC_SysLDO_LowDriveStrength = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */ + kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */ +} spc_sys_ldo_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +/*! + * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_core_ldo_voltage_level +{ + kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to Under Drive Voltage, please note that + underDrive voltage only useful in low power modes. */ + kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ + kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ + kSPC_CoreLDO_OverDriveVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to overdrive Voltage. */ +} spc_core_ldo_voltage_level_t; + +/*! + * @brief CORE LDO VDD regulator Drive Strength enumeration in Low Power mode. + */ +typedef enum _spc_core_ldo_drive_strength +{ + kSPC_CoreLDO_LowDriveStrength = 0x0U, /*!< Core LDO VDD regulator Drive Strength set to low. */ + kSPC_CoreLDO_NormalDriveStrength = 0x1U, /*!< Core LDO VDD regulator Drive Strength set to Normal. */ +} spc_core_ldo_drive_strength_t; + +/*! + * @brief System/IO VDD Low-Voltage Level Select. + */ +typedef enum _spc_low_voltage_level_select +{ + kSPC_LowVoltageNormalLevel = 0x0U, /*!< Trip point set to Normal level. */ + kSPC_LowVoltageSafeLevel = 0x1U, /*!< Trip point set to Safe level. */ +} spc_low_voltage_level_select_t; + +/*! + * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core. + */ +typedef enum _spc_vdd_core_glitch_ripple_counter_select +{ + kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ +} spc_vdd_core_glitch_ripple_counter_select_t; + +/*! + * @brief The list of the operating voltage for the SRAM's read/write timing margin. + */ +typedef enum _spc_sram_operate_voltage +{ + kSPC_sramOperateAt1P0V = 0x1U, /*!< SRAM configured for 1.0V operation. */ + kSPC_sramOperateAt1P1V = 0x2U, /*!< SRAM configured for 1.1V operation. */ + kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */ +} spc_sram_operate_voltage_t; + +/*! + * @brief The configuration of VDD Core glitch detector. + */ +typedef struct _spc_vdd_core_glitch_detector_config +{ + spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */ + uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial + glitch is detected. */ + bool enableReset; /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */ + bool enableInterrupt; /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */ +} spc_vdd_core_glitch_detector_config_t; + +typedef struct _spc_sram_voltage_config +{ + spc_sram_operate_voltage_t operateVoltage; /*!< Specifies the operating voltage for the SRAM's + read/write timing margin. */ + bool requestVoltageUpdate; /*!< Used to control whether request an SRAM trim value change. */ +} spc_sram_voltage_config_t; + +/*! + * @brief Low Power Request output pin configuration. + */ +typedef struct _spc_lowpower_request_config +{ + bool enable; /*!< Low Power Request Output enable. */ + spc_lowpower_request_pin_polarity_t polarity; /*!< Low Power Request Output pin polarity select. */ + spc_lowpower_request_output_override_t override; /*!< Low Power Request Output Override. */ +} spc_lowpower_request_config_t; + +/*! + * @brief Core LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */ +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Active mode */ +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ +} spc_active_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_sys_ldo_option +{ + spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Active mode. */ +} spc_active_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Active mode. + */ +typedef struct _spc_active_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Active mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC VDD Regulator Drive Strength selection in Active mode. */ +} spc_active_mode_dcdc_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief Core LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */ + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Low Power mode */ +} spc_lowpower_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_sys_ldo_option +{ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Low Power mode. */ +} spc_lowpower_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Low Power mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC VDD Regulator Drive Strength selection in Low Power mode. */ +} spc_lowpower_mode_dcdc_option_t; + +/*! + * @brief DCDC Burst configuration. + */ +typedef struct _spc_dcdc_burst_config +{ + bool sofwareBurstRequest; /*!< Enable/Disable DCDC Software Burst Request. */ + bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */ + bool stabilizeBurstFreq; /*!< Enable/Disable DCDC frequency stabilization. */ + uint8_t freq; /*!< The frequency of the current burst. */ +} spc_dcdc_burst_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief CORE/SYS/IO VDD Voltage Detect options. + */ +typedef struct _spc_voltage_detect_option +{ + bool HVDInterruptEnable; /*!< CORE/SYS/IO VDD High Voltage Detect interrupt enable. */ + bool HVDResetEnable; /*!< CORE/SYS/IO VDD High Voltage Detect reset enable. */ + bool LVDInterruptEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect interrupt enable. */ + bool LVDResetEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */ +} spc_voltage_detect_option_t; + +/*! + * @brief Core Voltage Detect configuration. + */ +typedef struct _spc_core_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< Core VDD Voltage Detect option. */ +} spc_core_voltage_detect_config_t; + +/*! + * @brief System Voltage Detect Configuration. + */ +typedef struct _spc_system_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< System VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< System VDD low-voltage selection. */ +} spc_system_voltage_detect_config_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @brief IO Voltage Detect Configuration. + */ +typedef struct _spc_io_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< IO VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */ +} spc_io_voltage_detect_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @brief Active mode configuration. + */ +typedef struct _spc_active_mode_regulators_config +{ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_active_mode_sys_ldo_option_t SysLDOOption; /*!< Specify System LDO configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */ +} spc_active_mode_regulators_config_t; + +/*! + * @brief Low Power Mode configuration. + */ +typedef struct _spc_lowpower_mode_regulators_config +{ + bool lpIREF; /*!< Enable/disable low power IREF in low power modes. */ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_lowpower_mode_sys_ldo_option_t SysLDOOption; /*!< Specify system LDO configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */ +} spc_lowpower_mode_regulators_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name SPC Status + * @{ + */ +/*! + * @brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * @param base SPC peripheral base address. + * @return Current isolation status for each power domains. See @ref _spc_power_domains for details. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base); + +/*! + * @brief Clears peripherals and I/O pads isolation flags for each power domains. + * + * This function clears peripherals and I/O pads isolation flags for each power domains. + * After recovering from the POWERDOWN mode, user must invoke this function to release the + * I/O pads and certain peripherals to their normal run mode state. Before invoking this + * function, user must restore chip configuration in particular pin configuration for enabled + * WUU wakeup pins. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base) +{ + base->SC |= SPC_SC_ISO_CLR_MASK; +} + +/*! + * @brief Gets SPC busy status flag. + * + * This function gets SPC busy status flag. When SPC executing any type of power mode + * transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set + * and this function returns true. When changing CORE LDO voltage level and DCDC voltage level + * in ACTIVE mode, the SPC busy status flag is set and this function return true. + * + * @param base SPC peripheral base address. + * @return Ack busy flag. + * true - SPC is busy. + * false - SPC is not busy. + */ +static inline bool SPC_GetBusyStatusFlag(SPC_Type *base) +{ + return ((base->SC & SPC_SC_BUSY_MASK) != 0UL); +} + +/*! + * @brief Checks system low power request. + * + * @note Only when all power domains request low power mode entry, the result of this function is true. That means when + * all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register. + * + * @param base SPC peripheral base address. + * @return The system low power request check result. + * - \b true All power domains have requested low power mode and SPC has entered a low power state and power mode + * configuration are based on the LP_CFG configuration register. + * - \b false SPC in active mode and ACTIVE_CFG register control system power supply. + */ +static inline bool SPC_CheckLowPowerReqest(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SPC_LP_REQ_MASK) == SPC_SC_SPC_LP_REQ_MASK); +} + +/*! + * @brief Clears system low power request, set SPC in active mode. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearLowPowerRequest(SPC_Type *base) +{ + base->SC |= SPC_SC_SPC_LP_REQ_MASK; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) +/*! + * @brief Checks whether the power switch is on. + * + * @param base SPC peripheral base address. + * + * @retval true The power switch is on. + * @retval false The power switch is off. + */ +static inline bool SPC_CheckSwitchState(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL); +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */ + +/*! + * @brief Gets selected power domain's requested low power mode. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * + * @return The selected power domain's requested low power mode, please refer to @ref spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId); + +/*! + * @brief Checks power domain's low power request. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * @return The result of power domain's low power request. + * - \b true The selected power domain requests low power mode entry. + * - \b false The selected power domain does not request low power mode entry. + */ +static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) == + SPC_PD_STATUS_PWR_REQ_STATUS_MASK); +} + +/*! + * @brief Clears selected power domain's low power request flag. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + */ +static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK; +} + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) +/*! + * @name SRAM Retention LDO Control APIs + * @{ + */ + +/*! + * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V. + * + * @param base SPC peripheral base address. + * @param trimValue Reference voltage trim value. + */ +static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue) +{ + base->SRAMRETLDO_REFTRIM = ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue)); +} + +/*! + * @brief Enables/disables SRAM retention LDO. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable SRAM LDO : + * - \b true Enable SRAM LDO; + * - \b false Disable SRAM LDO. + */ +static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable) +{ + if (enable) + { + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } + else + { + base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } +} + +/*! + * @brief + * + * @todo Need to check. + * + * @param base SPC peripheral base address. + * @param mask The OR'ed value of SRAM Array. + */ +static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask) +{ + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask); +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */ + +/*! + * @name Low Power Request configuration + * @{ + */ +/*! + * @brief Configs Low power request output pin. + * + * This function config the low power request output pin + * + * @param base SPC peripheral base address. + * @param config Pointer the @ref spc_lowpower_request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config); + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG) +/*! + * @name Integrated Power Switch Control APIs + * @{ + */ + +/*! + * @brief Enables/disables the integrated power switch manually. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable the integrated power switch: + * - \b true Enable the integrated power switch; + * - \b false Disable the integrated power switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } + else + { + base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } +} + +/*! + * @brief Enables/disables the integrated power switch automatically. + * + * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low + * power modes: + * @code + * SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true); + * @endcode + * + * @param base SPC peripheral base address. + * @param sleepGate Enable the integrated power switch when chip enter low power modes: + * - \b true SPC asserts an output pin at low-power entry to power-gate the switch; + * - \b false SPC does not assert an output pin at low-power entry to power-gate the switch. + * @param wakeupUngate Enables the switch after wake-up from low power modes: + * - \b true SPC asserts an output pin at low-power exit to power-ungate the switch; + * - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate) +{ + uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)); + + tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate); + + base->CFG = tmp32; +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */ + +/*! + * @name VDD Core Glitch Detector Control APIs + * @{ + */ + +/*! + * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * @param base SPC peripheral base address. + * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config); + +/*! + * @brief Checks selected 4-bit glitch ripple counter's output. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + * + * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings. + * @retval false The selected ripple counter output is 0. + */ + +static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) == + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter))); +} + +/*! + * @brief Clears output of selected glitch ripple counter. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + */ +static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)); +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * + * @param base SPC peripheral base address. + * + * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable. + */ +static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL); +} + +/* @} */ + +/*! + * @name SRAM Control APIs + * @{ + */ + +/*! + * @brief Set SRAM operate voltage. + * + * @param base SPC peripheral base address. + * @param config The pointer to @ref spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config); + +/* @} */ + +/*! + * @name Active Mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Active mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_BGMODE_MASK) >> + SPC_ACTIVE_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets all voltage detectors status in Active mode. + * + * @param base SPC peripheral base address. + * @return All voltage detectors status in Active mode. + */ +static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->ACTIVE_CFG & + ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK | \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK \ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_ACTIVE_CFG_CORE_HVDE_MASK \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Configs Bandgap mode in Active mode. + * + * @note In active mode, beacause CORELDO_VDD_DS is reserved and set to Normal, so it is impossible to + * disable Bandgap in active mode + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * @retval #kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disable the CMP Bandgap Buffer in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference voltage to CMP. + * false - Disable Buffer Stored Reference voltage to CMP. + */ +static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +/*! + * @brief Sets the delay when the regulators change voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles. + */ +static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay) +{ + base->ACTIVE_VDELAY = SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(delay); +} + +/*! + * @brief Configs regulators in Active mode. + * + * This function provides the method to config all on-chip regulators in active mode. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_active_mode_regulators_config_t structure. + * @retval #kStatus_Success Config regulators in Active power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config); + +/*! + * @brief Disables/Enables VDD Core Glitch Detect in Active mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Enables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 |= SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 &= ~SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in active mode. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in active mode. + */ +static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base) +{ + return base->ACTIVE_CFG1; +} + +/* @} */ + +/*! + * @name Low Power mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Low Power mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_BGMODE_MASK) >> SPC_LP_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets the status of all voltage detectors in Low Power mode. + * + * @param base SPC peripheral base address. + * @return The status of all voltage detectors in low power mode. + */ +static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->LP_CFG & ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK | \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK \ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_LP_CFG_CORE_HVDE_MASK \ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Enables/Disables Low Power IREF in low power modes. + * + * This function enables/disables Low Power IREF. Low Power IREF can only get + * disabled in Deep power down mode. In other low power modes, the Low Power IREF + * is always enabled. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Low Power IREF. + * true - Enable Low Power IREF for Low Power modes. + * false - Disable Low Power IREF for Deep Power Down mode. + */ +static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LP_IREFEN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LP_IREFEN_MASK; + } +} + +/*! + * @brief Configs Bandgap mode in Low Power mode. + * + * This function configs Bandgap mode in Low Power mode. + * IF user want to disable Bandgap while keeping any of the Regulator in Normal Driver Strength + * or if any of the High voltage detectors/Low voltage detectors are kept enabled, the Bandgap mode + * will be set as Bandgap Enabled with Buffer Disabled. + * + * @note This API shall be invoked following set HVDs/LVDs and regulators' driver strength. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) +/*! + * @brief Enables/disables SRAM_LDO deep power low power IREF. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable low power IREF : + * - \b true: Low Power IREF is enabled ; + * - \b false: Low Power IREF is disabled for power saving. + */ +static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) +/*! + * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes. + * + * This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the + * external input CORE VDD to a lower voltage level to reduce internal leakage. + * IVS is invalid in Sleep or Deep power down mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IVS. + * true - enable CORE VDD IVS in Power Down mode. + * false - disable CORE VDD IVS in Power Down mode. + */ +static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +/*! + * @brief Sets the delay when exit the low power modes. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles that the SPC waits on exit from low power modes. + */ +static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay) +{ + base->LPWKUP_DELAY = SPC_LPWKUP_DELAY_LPWKUP_DELAY(delay); +} + +/*! + * @brief Configs regulators in Low Power mode. + * + * This function provides the method to config all on-chip regulators in Low Power mode. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * @retval #kStatus_Success Config regulators in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level is wrong. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config); + +/*! + * @brief Disable/Enable VDD Core Glitch Detect in low power mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->LP_CFG |= SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Enables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 |= SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 &= ~SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in low power modes. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in low power modes. + */ +static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base) +{ + return base->LP_CFG1; +} + +/* @} */ + +/*! + * @name Voltage Detect Status + * @{ + */ +/*! + * @brief Get Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base) +{ + return (uint8_t)(base->VD_STAT); +} + +/*! + * @brief Clear Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @param mask The mask of the voltage detect status flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask) +{ + base->VD_STAT |= mask; +} + +/* @} */ + +/*! + * @name Voltage Detect configuration for Core voltage domain. + * @{ + */ + +/*! + * @brief Configs CORE voltage detect options. + * + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config); + +/*! + * @brief Locks Core voltage detect reset setting. + * + * This function locks core voltage detect reset setting. After invoking this function + * any configuration of Core voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG |= SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Unlocks Core voltage detect reset setting. + * + * This function unlocks core voltage detect reset setting. If locks the Core + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Active mode. + * + * @note If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode. + * + * This function enables/disables the Core Low Voltage Detector. + * If enabled the Core Low Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * @brief Enables/Disables the Core High Voltage Detector in Active mode. + * + * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core High Voltage Detector in Low Power mode. + * + * This function enables/disables the Core High Voltage Detector. + * If enabled the Core High Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in low power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/* @} */ + +/*! + * @name Voltage detect configuration for System Voltage domain + * @{ + */ +/*! + * @brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @param base SPC peripheral base address. + * @param level System VDD Low-Voltage level selection. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs SYS voltage detect options. + * + * This function config SYS voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config); + +/*! + * @brief Lock System voltage detect reset setting. + * + * This function locks system voltage detect reset setting. After invoking this function + * any configuration of System Voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG |= SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock System voltage detect reset setting. + * + * This function unlocks system voltage detect reset setting. If locks the System + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG &= ~SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the System High Voltage Detector in Active mode. + * + * @note If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disable the System Low Voltage Detector in Active mode. + * + * @note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System High Voltage Detector in Low Power mode. + * + * @note If the System_LDO high voltage detect is enabled in Low Power mode, please note + * that the bandgap must be enabled and the drive strength of each regulator must + * not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System Low Voltage Detector in Low Power mode. + * + * @note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enables System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @name Voltage detect configuration for IO voltage domain + * @{ + */ +/*! + * @brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * @param base SPC peripheral base address. + * @param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs IO voltage detect options. + * + * This function config IO voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config); + +/*! + * @brief Lock IO Voltage detect reset setting. + * + * This function locks IO voltage detect reset setting. After invoking this function + * any configuration of system voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG |= SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock IO voltage detect reset setting. + * + * This function unlocks IO voltage detect reset setting. If locks the IO + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG &= ~SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Active mode. + * + * @note If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Active mode. + * + * @note If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Low Power mode. + * + * @note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Low Power mode. + * + * @note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/* @} */ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @name External Voltage domains configuration + * @{ + */ +/*! + * @brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * @param base SPC peripheral base address. + * @param lowPowerIsoMask The mask of external domains isolate enable during low power mode. Please read the Reference + * Manual for the Bitmap. + * @param IsoMask The mask of external domains isolate. Please read the Reference Manual for the Bitmap. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask); + +/*! + * @brief Gets External Domains status. + * + * This function configs external voltage domains status. + * + * @param base SPC peripheral base address. + * @return The status of each external domain. + */ +static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base) +{ + return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); +} + +/* @} */ + +/*! + * @name Set CORE LDO Regulator + * @{ + */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) +/*! + * @brief Enable/Disable Core LDO regulator. + * + * @note The CORE LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CORE LDO Regulator. + * true - Enable CORE LDO Regulator. + * false - Disable CORE LDO Regulator. + */ +static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_CORELDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If CORE_LDO is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) +/*! + * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down. + * + * @note This function only useful when enabled the CORE LDO Regulator. + * + * @param base SPC peripheral base address. + * @param pulldown Enable/Disable CORE LDO pulldown in Deep Power Down mode. + * true - CORE LDO Regulator will discharge in Deep Power Down mode. + * false - CORE LDO Regulator will not discharge in Deep Power Down mode. + */ +static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown) +{ + if (pulldown) + { + base->CORELDO_CFG &= ~SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } + else + { + base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */ + +/*! + * @brief Configs Core LDO VDD Regulator in Active mode. + * + * @note If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + * + * @note Core VDD level for the Core LDO low power regulator can only be changed when CORELDO_VDD_DS is normal + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_core_ldo_option_t structure. + * + * @retval #kStatus_Success Config Core LDO regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, core_ldo's drive strength can not + * set to low. + * @retval #kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets CORE LDO VDD Regulator Voltage level. + * + * This function returns the voltage level of CORE LDO Regulator in Active mode. + * + * @param base SPC peripheral base address. + * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT); +} + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT); +} +#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + +/*! + * @brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength set as Normal. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_core_ldo_option_t structure. + * + * @retval #kStatus_Success Config Core LDO regulator in power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * @param base SPC peripheral base address. + * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO VDD Regulator's voltage level. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Drive Strength for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO's VDD Drive Strength. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >> + SPC_LP_CFG_CORELDO_VDD_DS_SHIFT); +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @name Set System LDO Regulator. + * @{ + */ + +/*! + * @brief Enable/Disable System LDO regulator. + * + * @note The SYSTEM LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LDO Regulator. + * true - Enable System LDO Regulator. + * false - Disable System LDO Regulator. + */ +static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_SYSLDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If SYSTEM_LDO is disabled, may cause some unexpected issues. + */ + base->CNTRL &= ~SPC_CNTRL_SYSLDO_EN_MASK; + } +} + +/*! + * @brief Enable/Disable current sink feature of System LDO Regulator. + * + * @param base SPC peripheral base address. + * @param sink Enable/Disable current sink feature. + * true - Enable current sink feature of System LDO Regulator. + * false - Disable current sink feature of System LDO Regulator. + */ +static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink) +{ + if (sink) + { + base->SYSLDO_CFG |= SPC_SYSLDO_CFG_ISINKEN_MASK; + } + else + { + base->SYSLDO_CFG &= ~SPC_SYSLDO_CFG_ISINKEN_MASK; + } +} + +/*! + * @brief Configs System LDO VDD Regulator in Active mode. + * + * This function configs System LDO VDD Regulator in Active mode. + * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enables the bandgap. + * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. + * Otherwise it will be fail to regulator to Over Drive Voltage. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Get System LDO Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t. + */ +static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >> SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT); +} + +/*! + * @brief Set System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >> SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT); +} + +/*! + * @brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * @param base SPC peripheral base address. + * @param option Pointer to spc_lowpower_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >> SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT); +} +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @name Set DCDC Regulator. + * @{ + */ + +/*! + * @brief Enable/Disable DCDC Regulator. + * + * @note The DCDC enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable DCDC Regulator. + * true - Enable DCDC Regulator. + * false - Disable DCDC Regulator. + */ +static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_DCDC_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If DCDC is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_DCDC_EN_MASK; + } +} + +/*! + * @brief Config DCDC Burst options + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_dcdc_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config); + +/*! + * @brief Set the count value of the reference clock. + * + * This function set the count value of the reference clock to control the frequency + * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * + * @param base SPC peripheral base address. + * @param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count); + +/*! + * @brief Configs DCDC VDD Regulator in Active mode. + * + * @note Before switching DCDC drive strength from low to normal, the DCDC voltage level should be configured back to + * what it was before switching to low drive strength. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC VDD Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC VDD Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT); +} + +/*! + * @brief Set DCDC VDD Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC VDD Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT); +} + +/*! + * @brief Configs DCDC VDD Regulator in Low power modes. + * + * This function configs DCDC VDD Regulator in Low Power modes. + * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * If any of voltage detectors are kept enabled, configuration to set DCDC VDD Drive Strength to Low or Pulse mode + * will be ignored. + * In Deep Power Down mode, DCDC regulator is always turned off. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in low power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_DCDCPulseRefreshModeIgnore Set driver strength to Pulse Refresh mode will be ignored. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low Drive Strength will be ignored. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC VDD Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC VDD Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >> + SPC_LP_CFG_DCDC_VDD_LVL_SHIFT); +} + +/*! + * @brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * @retval #kStatus_SPC_DCDCLowDriveStrengthIgnore Any of the voltage detects are kept enabled, set driver strength to + * Low will be ignored. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC VDD Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >> SPC_LP_CFG_DCDC_VDD_DS_SHIFT); +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* FSL_SPC_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_syspm.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_syspm.c new file mode 100644 index 0000000000..2fecd525bc --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_syspm.c @@ -0,0 +1,215 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_syspm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.syspm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) +/*! + * @brief Get instance number for ESYSPM. + * + * @param base ESYSPM peripheral base address. + */ +static uint32_t SYSPM_GetInstance(SYSPM_Type *base); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) +/*! @brief Array to map SYSPM instance number to base pointer. */ +static SYSPM_Type *const s_syspmBases[] = SYSPM_BASE_PTRS; + +/*! @brief Array to map SYSPM instance number to clock name. */ +static const clock_ip_name_t s_syspmClockName[] = SYSPM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) +static uint32_t SYSPM_GetInstance(SYSPM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_syspmBases); instance++) + { + if (s_syspmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_syspmBases)); + + return instance; +} +#endif + +/* + * brief Initializes the SYSPM + * + * This function enables the SYSPM clock. + * + * param base SYSPM peripheral base address. + */ +void SYSPM_Init(SYSPM_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) + CLOCK_EnableClock(s_syspmClockName[SYSPM_GetInstance(base)]); +#endif +} + +/* + * brief Deinitializes the SYSPM + * + * This function disables the SYSPM clock. + * + * param base SYSPM peripheral base address. + */ +void SYSPM_Deinit(SYSPM_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) && defined(SYSPM_CLOCKS) + CLOCK_DisableClock(s_syspmClockName[SYSPM_GetInstance(base)]); +#endif +} + +/*! + * @brief Select event counters + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param event syspm select event, see to #syspm_event_t. + * @param eventCode select which event to be counted in PMECTRx., see to table Events. + */ +void SYSPM_SelectEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event, uint8_t eventCode) +{ + uint32_t pmcr; + uint8_t shift; + + shift = 7U * (uint8_t)event; + + pmcr = base->PMCR[(uint8_t)monitor].PMCR; + pmcr &= ~(SYSPM_PMCR_SELEVT1_MASK << shift); + pmcr |= SYSPM_PMCR_SELEVT1(eventCode) << shift; + + base->PMCR[(uint8_t)monitor].PMCR = pmcr; +} + +/*! + * @brief Reset event counters + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event) +{ + base->PMCR[(uint8_t)monitor].PMCR |= ((uint32_t)SYSPM_PMCR_RECTR1_MASK << (uint8_t)event); +} + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_RICTR) && (FSL_FEATURE_SYSPM_HAS_PMCR_RICTR == 0U))) +/*! + * @brief Reset Instruction Counter + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetInstructionEvent(SYSPM_Type *base, syspm_monitor_t monitor) +{ + base->PMCR[(uint8_t)monitor].PMCR |= SYSPM_PMCR_RICTR_MASK; +} +#endif /* FSL_FEATURE_SYSPM_HAS_PMCR_RICTR */ + +/*! + * @brief Set count mode + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param mode syspm select counter mode, see to #syspm_mode_t. + */ +void SYSPM_SetCountMode(SYSPM_Type *base, syspm_monitor_t monitor, syspm_mode_t mode) +{ + base->PMCR[(uint8_t)monitor].PMCR = + (base->PMCR[(uint8_t)monitor].PMCR & ~SYSPM_PMCR_CMODE_MASK) | SYSPM_PMCR_CMODE(mode); +} + +/*! + * @brief Set Start/Stop Control + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param ssc This 3-bit field provides a three-phase mechanism to start/stop the counters. It includes a + * prioritized scheme with local start > local stop > global start > global stop > conditional + * TSTART > TSTOP. The global and conditional start/stop affect all configured PM/PSAM module concurrently so counters + * are "coherent". see to #syspm_startstop_control_t + */ +void SYSPM_SetStartStopControl(SYSPM_Type *base, syspm_monitor_t monitor, syspm_startstop_control_t ssc) +{ + base->PMCR[(uint8_t)monitor].PMCR = + (base->PMCR[(uint8_t)monitor].PMCR & ~SYSPM_PMCR_SSC_MASK) | SYSPM_PMCR_SSC(ssc); +} + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH)) && (FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH == 0U)) +/*! + * @brief Disable Counters if Stopped or Halted + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_DisableCounter(SYSPM_Type *base, syspm_monitor_t monitor) +{ + base->PMCR[(uint8_t)monitor].PMCR |= SYSPM_PMCR_DCIFSH_MASK; +} +#endif /* FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH */ + +/*! + * @brief This is the the 40-bits of eventx counter. + The value in this register increments each time the event + selected in PMCRx[SELEVTx] occurs. + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param event syspm select event, see to #syspm_event_t. + * @return get the the 40 bits of eventx counter. + */ +uint64_t SYSPM_GetEventCounter(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event) +{ + uint32_t highOld; + uint32_t high; + uint32_t low; + + highOld = base->PMCR[(uint8_t)monitor].PMECTR[(uint8_t)event].HI; + while (true) + { + low = base->PMCR[(uint8_t)monitor].PMECTR[(uint8_t)event].LO; + high = base->PMCR[(uint8_t)monitor].PMECTR[(uint8_t)event].HI; + if (high == highOld) + { + break; + } + else + { + highOld = high; + } + } + + return ((uint64_t)high << 32U) + low; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_syspm.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_syspm.h new file mode 100644 index 0000000000..397b1f9aeb --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_syspm.h @@ -0,0 +1,165 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SYSPM_H_ +#define FSL_SYSPM_H_ + +#include "fsl_common.h" + +/*! @addtogroup syspm */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SYSPM driver version */ +#define FSL_SYSPM_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) + +/*@}*/ +/*! @brief syspm select control monitor */ +typedef enum _syspm_monitor +{ + kSYSPM_Monitor0 = 0U, /*!< Monitor 0 */ +#if (SYSPM_PMCR_COUNT > 1U) + kSYSPM_Monitor1 = 1U, /*!< Monitor 1 */ +#endif +} syspm_monitor_t; + +/*! @brief syspm select event */ +typedef enum _syspm_event +{ + kSYSPM_Event1 = 0U, /*!< Event 1 */ + kSYSPM_Event2 = 1U, /*!< Event 2 */ + kSYSPM_Event3 = 2U, /*!< Event 3 */ +} syspm_event_t; + +/*! @brief syspm set count mode */ +typedef enum _syspm_mode +{ + kSYSPM_BothMode = 0x00, /*!< count in both modes */ + kSYSPM_UserMode = 0x02, /*!< count only in user mode */ + kSYSPM_PrivilegedMode = 0x03, /*!< count only in privileged mode */ +} syspm_mode_t; + +/*! @brief syspm start/stop control */ +typedef enum _syspm_startstop_control +{ + kSYSPM_Idle = 0x00, /*!< idle >*/ + kSYSPM_LocalStop = 0x01, /*!< local stop */ + kSYSPM_LocalStart = 0x02, /*!< local start */ + KSYSPM_EnableTraceControl = 0x04, /*!< enable global TSTART/TSTOP */ + kSYSPM_GlobalStart = 0x05, /*!< global stop */ + kSYSPM_GlobalStop = 0x06, /*!< global start */ +} syspm_startstop_control_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @brief Initializes the SYSPM + * + * This function enables the SYSPM clock. + * + * @param base SYSPM peripheral base address. + */ +void SYSPM_Init(SYSPM_Type *base); + +/*! + * @brief Deinitializes the SYSPM + * + * This function disables the SYSPM clock. + * + * @param base SYSPM peripheral base address. + */ +void SYSPM_Deinit(SYSPM_Type *base); + +/*! + * @brief Select event counters + * + * @param base SYSPM peripheral base address. + * @param event syspm select event, see to #syspm_event_t. + * @param eventCode select which event to be counted in PMECTRx., see to table Events. + */ +void SYSPM_SelectEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event, uint8_t eventCode); + +/*! + * @brief Reset event counters + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetEvent(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event); + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_RICTR) && (FSL_FEATURE_SYSPM_HAS_PMCR_RICTR == 0U))) +/*! + * @brief Reset Instruction Counter + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_ResetInstructionEvent(SYSPM_Type *base, syspm_monitor_t monitor); +#endif + +/*! + * @brief Set count mode + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param mode syspm select counter mode, see to #syspm_mode_t. + */ +void SYSPM_SetCountMode(SYSPM_Type *base, syspm_monitor_t monitor, syspm_mode_t mode); + +/*! + * @brief Set Start/Stop Control + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param ssc This 3-bit field provides a three-phase mechanism to start/stop the counters. It includes a + * prioritized scheme with local start > local stop > global start > global stop > conditional + * TSTART > TSTOP. The global and conditional start/stop affect all configured PM/PSAM module concurrently so counters + * are "coherent". see to #syspm_startstop_control_t + */ +void SYSPM_SetStartStopControl(SYSPM_Type *base, syspm_monitor_t monitor, syspm_startstop_control_t ssc); + +#if !((defined(FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH)) && (FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH == 0U)) +/*! + * @brief Disable Counters if Stopped or Halted + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + */ +void SYSPM_DisableCounter(SYSPM_Type *base, syspm_monitor_t monitor); +#endif + +/*! + * @brief This is the the 40-bits of eventx counter. + The value in this register increments each time the event + selected in PMCRx[SELEVTx] occurs. + * + * @param base SYSPM peripheral base address. + * @param monitor syspm control monitor, see to #syspm_monitor_t. + * @param event syspm select event, see to #syspm_event_t. + * @return get the the 40 bits of eventx counter. + */ +uint64_t SYSPM_GetEventCounter(SYSPM_Type *base, syspm_monitor_t monitor, syspm_event_t event); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* FSL_SYSPM_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_tdet.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_tdet.c new file mode 100644 index 0000000000..4caa262a50 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_tdet.c @@ -0,0 +1,656 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_tdet.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tdet" +#endif + +/* all bits defined in the LOCK Register. */ +#define TDET_ALL_LC_MASK 0x00FF3FF0u + +/* all bits defined in the Interrupt Enable Register. */ +#define TDET_ALL_IER_MASK 0x00FF03FDu + +/* all bits defined in the Tamper Enable Register. */ +#define TDET_ALL_TER_MASK 0x00FF0FFCu + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * Weak implementation of TDET IRQ, should be re-defined by user when using TDET IRQ + */ +__WEAK void VBAT0_DriverIRQHandler(void) +{ + /* TDET generates IRQ until corresponding bit in STATUS is cleared by calling + * TDET_ClearStatusFlags(TDET0,kTDET_StatusAll); + * which clear all bits or kTDET_StatusXXX to clear only one bit + */ +} + +static bool tdet_IsRegisterWriteAllowed(DIGTMP_Type *base, uint32_t mask) +{ + bool retval; + + retval = false; + mask = mask & TDET_ALL_LC_MASK; + + /* specified LR bit(s) must be set */ + if (mask == (mask & base->LR)) + { + retval = true; + } + return retval; +} + +static status_t tdet_PinConfigure(DIGTMP_Type *base, const tdet_pin_config_t *pinConfig, uint32_t pin) +{ + uint32_t temp; + uint32_t mask; + status_t status; + + if ((tdet_IsRegisterWriteAllowed( + base, DIGTMP_LR_PDL_MASK | DIGTMP_LR_PPL_MASK | (((uint32_t)1u << DIGTMP_LR_GFL0_SHIFT) << pin))) && + (pinConfig != NULL)) + { + /* pin 0 to 7 selects bit0 to bit7 */ + mask = ((uint32_t)1u << pin); + + /* Pin Direction Register */ + temp = base->PDR; + temp &= ~mask; /* clear the bit */ + if (kTDET_TamperPinDirectionOut == pinConfig->pinDirection) + { + temp |= mask; /* set the bit, if configured */ + } + base->PDR = temp; + + /* Pin Polarity Register */ + temp = base->PPR; + temp &= ~mask; /* clear the bit */ + if (kTDET_TamperPinPolarityExpectInverted == pinConfig->pinPolarity) + { + temp |= mask; /* set the bit, if configured */ + } + base->PPR = temp; + + /* compute and set the configured value to the glitch filter register */ + temp = 0; + temp |= DIGTMP_PGFR_GFW(pinConfig->glitchFilterWidth); + temp |= DIGTMP_PGFR_GFP(pinConfig->glitchFilterPrescaler); + temp |= DIGTMP_PGFR_TPSW(pinConfig->tamperPinSampleWidth); + temp |= DIGTMP_PGFR_TPSF(pinConfig->tamperPinSampleFrequency); + temp |= DIGTMP_PGFR_TPEX(pinConfig->tamperPinExpected); + temp |= DIGTMP_PGFR_TPE(pinConfig->tamperPullEnable); + temp |= DIGTMP_PGFR_TPS(pinConfig->tamperPullSelect); + /* make sure the glitch filter is disabled when we configure glitch filter width */ + base->PGFR[pin] = temp; + /* add glitch filter enabled */ + if (pinConfig->glitchFilterEnable) + { + temp |= DIGTMP_PGFR_GFE(1u); + base->PGFR[pin] = temp; + } + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +static status_t tdet_ActiveTamperConfigure(DIGTMP_Type *base, + const tdet_active_tamper_config_t *activeTamperConfig, + uint32_t activeTamperRegister) +{ + uint32_t temp; + status_t status; + + /* check if writing to active tamper register is allowed */ + if ((tdet_IsRegisterWriteAllowed(base, ((uint32_t)1u << DIGTMP_LR_ATL0_SHIFT) << activeTamperRegister)) && + (activeTamperConfig != NULL)) + { + /* compute and set the configured value to the active tamper register */ + temp = 0; + temp |= DIGTMP_ATR_ATSR(activeTamperConfig->activeTamperShift); + temp |= DIGTMP_ATR_ATP(activeTamperConfig->activeTamperPolynomial); + base->ATR[activeTamperRegister] = temp; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Initialize TDET + * + * This function initializes TDET. + * + * param base TDET peripheral base address + * return Status of the init operation + */ +status_t TDET_Init(DIGTMP_Type *base) +{ + return kStatus_Success; +} + +/*! + * brief Deinitialize TDET + * + * This function disables glitch filters and active tampers + * This function disables the TDET clock and prescaler in TDET Control Register. + * param base TDET peripheral base address + */ +void TDET_Deinit(DIGTMP_Type *base) +{ + uint32_t i, j, k; + j = ARRAY_SIZE(base->PGFR); + k = ARRAY_SIZE(base->ATR); + /* disable all glitch filters and active tampers */ + for (i = 0; i < j; i++) + { + base->PGFR[i] = 0; + } + for (i = 0; i < k; i++) + { + base->ATR[i] = 0; + } + + /* disable inner TDET clock and prescaler */ + base->CR &= ~DIGTMP_CR_DEN_MASK; +} + +/*! + * brief Gets default values for the TDET Control Register. + * + * This function fills the given structure with default values for the TDET Control Register. + * The default values are: + * code + * defaultConfig->innerClockAndPrescalerEnable = true + * defaultConfig->tamperForceSystemResetEnable = false + * defaultConfig->updateMode = kTDET_StatusLockWithTamper + * defaultConfig->clockSourceActiveTamper0 = kTDET_ClockType1Hz + * defaultConfig->clockSourceActiveTamper1 = kTDET_ClockType1Hz + * defaultConfig->disablePrescalerAfterTamper = false + * defaultConfig->prescaler = 0 + * endcode + * param base TDET peripheral base address + * param[out] defaultConfig Pointer to structure to be filled with default parameters + */ +void TDET_GetDefaultConfig(DIGTMP_Type *base, tdet_config_t *defaultConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(defaultConfig, 0, sizeof(*defaultConfig)); + + struct _tdet_config myDefaultConfig = { + true, /* innerClockAndPrescalerEnable */ + false, /* tamperForceSystemResetEnable */ + kTDET_StatusLockWithTamper, /* updateMode */ + kTDET_ClockType1Hz, /* clockSourceActiveTamper0 */ + kTDET_ClockType1Hz, /* clockSourceActiveTamper1 */ + false, /* disable prescaler on tamper event */ + 0, /* prescaler */ + }; + + *defaultConfig = myDefaultConfig; +} + +/*! + * brief Writes to the TDET Control Register. + * + * This function writes the given structure to the TDET Control Register. + * param base TDET peripheral base address + * param config Pointer to structure with TDET peripheral configuration parameters + * return kStatus_Fail when writing to TDET Control Register is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_SetConfig(DIGTMP_Type *base, const tdet_config_t *config) +{ + uint32_t tmpCR; + + status_t retval = kStatus_Fail; + + /* check if writing to CR is allowed */ + if ((tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_CRL_MASK)) && (config != NULL)) + { + /* compute CR value */ + tmpCR = 0; + tmpCR |= DIGTMP_CR_TFSR(config->tamperForceSystemResetEnable); + tmpCR |= DIGTMP_CR_UM(config->updateMode); + tmpCR |= DIGTMP_CR_ATCS0(config->clockSourceActiveTamper0); + tmpCR |= DIGTMP_CR_ATCS1(config->clockSourceActiveTamper1); + tmpCR |= DIGTMP_CR_DISTAM(config->disablePrescalerAfterTamper); + tmpCR |= DIGTMP_CR_DPR(config->prescaler); + /* write the computed value to the CR register */ + base->CR = tmpCR; + /* after the prescaler is written to CR register, enable the inner TDET clock and prescaler */ + if (config->innerClockAndPrescalerEnable) + { + base->CR = tmpCR | DIGTMP_CR_DEN_MASK; + } + retval = kStatus_Success; + } + else + { + retval = kStatus_Fail; + } + + return retval; +} + +/*! + * brief Software reset. + * + * This function resets all TDET registers. The CR[SWR] itself is not affected; + * it is reset by VBAT POR only. + * + * param base TDET peripheral base address + * return kStatus_Fail when writing to TDET Control Register is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_SoftwareReset(DIGTMP_Type *base) +{ + status_t retval = kStatus_Fail; + + /* check if writing to CR is allowed */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_CRL_MASK)) + { + /* set the CR[SWR] */ + base->CR = DIGTMP_CR_SWR_MASK; + retval = kStatus_Success; + } + else + { + retval = kStatus_Fail; + } + + return retval; +} + +/*! + * brief Writes to the active tamper register(s). + * + * This function writes per active tamper register parameters to active tamper register(s). + * + * param base TDET peripheral base address + * param activeTamperConfig Pointer to structure with active tamper register parameters + * param activeTamperRegisterSelect Bit mask for active tamper registers to be configured. The passed value is + * combination of tdet_active_tamper_register_t values (OR'ed). + * return kStatus_Fail when writing to TDET Active Tamper Register(s) is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_ActiveTamperSetConfig(DIGTMP_Type *base, + const tdet_active_tamper_config_t *activeTamperConfig, + uint32_t activeTamperRegisterSelect) +{ + uint32_t mask; + status_t status; + uint32_t i, j; + + mask = 1u; + status = kStatus_Success; + j = ARRAY_SIZE(base->ATR); + /* configure active tamper register by active tamper register, by moving through all active tamper registers */ + for (i = 0; i < j; i++) + { + if ((activeTamperRegisterSelect & mask) != 0U) + { + /* configure this active tamper register */ + status = tdet_ActiveTamperConfigure(base, activeTamperConfig, i); + if (status != kStatus_Success) + { + break; + } + } + mask = mask << 1u; + } + + return status; +} + +/*! + * brief Gets default values for tamper pin configuration. + * + * This function fills the give structure with default values for the tamper pin and glitch filter configuration. + * The default values are: + * code + * pinConfig->pinPolarity = kTDET_TamperPinPolarityExpectNormal; + * pinConfig->pinDirection = kTDET_TamperPinDirectionIn; + * pinConfig->tamperPullEnable = false; + * pinConfig->tamperPinSampleFrequency = kTDET_GlitchFilterSamplingEveryCycle8; + * pinConfig->tamperPinSampleWidth = kTDET_GlitchFilterSampleDisable; + * pinConfig->glitchFilterEnable = false; + * pinConfig->glitchFilterPrescaler = kTDET_GlitchFilterClock512Hz; + * pinConfig->glitchFilterWidth = 0; + * pinConfig->tamperPinExpected = kTDET_GlitchFilterExpectedLogicZero; + * pinConfig->tamperPullSelect = kTDET_GlitchFilterPullTypeAssert; + * endcode + * + * param base TDET peripheral base address + * param[out] pinConfig Pointer to structure to be filled with tamper pins default parameters + */ +void TDET_PinGetDefaultConfig(DIGTMP_Type *base, tdet_pin_config_t *pinConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(pinConfig, 0, sizeof(*pinConfig)); + + struct _tdet_pin_config myPinDefaultConfig = { + kTDET_TamperPinPolarityExpectNormal, /* pinPolarity */ + kTDET_TamperPinDirectionIn, /* pinDirection */ + false, /* tamperPullEnable */ + kTDET_GlitchFilterSamplingEveryCycle8, /* tamperPinSampleFrequency */ + kTDET_GlitchFilterSampleDisable, /* tamperPinSampleWidth */ + false, /* glitchFilterEnable */ + kTDET_GlitchFilterClock512Hz, /* glitchFilterPrescaler */ + 0, /* glitchFilterWidth */ + kTDET_GlitchFilterExpectedLogicZero, /* tamperPinExpected */ + kTDET_GlitchFilterPullTypeAssert, /* tamperPullSelect */ + }; + + *pinConfig = myPinDefaultConfig; +} + +/*! + * brief Writes the tamper pin configuration. + * + * This function writes per pin parameters to tamper pin and glitch filter configuration registers. + * + * param base TDET peripheral base address + * param pinConfig Pointer to structure with tamper pin and glitch filter configuration parameters + * param pinSelect Bit mask for tamper pins to be configured. The passed value is combination of + * enum _tdet_external_tamper_pin (tdet_external_tamper_pin_t) values (OR'ed). + * return kStatus_Fail when writing to TDET Pin Direction, Pin Polarity or Glitch Filter Register(s) is not allowed + * return kStatus_Success when operation completes successfully + */ +status_t TDET_PinSetConfig(DIGTMP_Type *base, const tdet_pin_config_t *pinConfig, uint32_t pinSelect) +{ + uint32_t mask; + status_t status; + uint32_t i, j; + + mask = 1u; + status = kStatus_Success; + j = ARRAY_SIZE(base->PGFR); + /* configure pin by pin, by moving through all selected pins */ + for (i = 0; i < j; i++) + { + if ((pinSelect & mask) != 0U) + { + /* clear this pin from pinSelect */ + pinSelect &= ~mask; + + /* configure this pin */ + status = tdet_PinConfigure(base, pinConfig, i); + + /* if pinSelect is zero, we have configured all pins selected by pinSelect, so skip */ + if ((status != kStatus_Success) || (0U == pinSelect)) + { + break; + } + } + mask = mask << 1u; + } + + return status; +} + +/*! + * brief Reads the Status Register. + * + * This function reads flag bits from TDET Status Register. + * + * param base TDET peripheral base address + * param[out] result Pointer to uint32_t where to write Status Register read value. Use tdet_status_flag_t to decode + * individual flags. + * return kStatus_Fail when Status Register reading is not allowed + * return kStatus_Success when result is written with the Status Register read value + */ +status_t TDET_GetStatusFlags(DIGTMP_Type *base, uint32_t *result) +{ + status_t status; + + if (result != NULL) + { + *result = base->SR; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Status Register. + * + * This function clears specified flag bits in TDET Status Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the flag bits to be cleared. Use tdet_status_flag_t to encode flags. + * return kStatus_Fail when Status Register writing is not allowed + * return kStatus_Success when mask is written to the Status Register + */ +status_t TDET_ClearStatusFlags(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_SRL_MASK)) + { + base->SR = mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Interrupt Enable Register. + * + * This function sets specified interrupt enable bits in TDET Interrupt Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the interrupt enable bits to be set. + * return kStatus_Fail when Interrupt Enable Register writing is not allowed + * return kStatus_Success when mask is written to the Interrupt Enable Register + */ +status_t TDET_EnableInterrupts(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_IER_MASK; /* only set the bits documented in Reference Manual. */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_IEL_MASK)) + { + base->IER |= mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Interrupt Enable Register. + * + * This function clears specified interrupt enable bits in TDET Interrupt Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the interrupt enable bits to be cleared. + * return kStatus_Fail when Interrupt Enable Register writing is not allowed + * return kStatus_Success when specified bits are cleared in the Interrupt Enable Register + */ +status_t TDET_DisableInterrupts(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_IER_MASK; /* only clear the bits documented in Reference Manual. */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_IEL_MASK)) + { + base->IER &= ~mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Tamper Enable Register. + * + * This function sets specified tamper enable bits in TDET Tamper Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the tamper enable bits to be set. + * return kStatus_Fail when Tamper Enable Register writing is not allowed + * return kStatus_Success when mask is written to the Tamper Enable Register + */ +status_t TDET_EnableTampers(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_TER_MASK; /* only set the bits documented in Reference Manual */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_TEL_MASK)) + { + base->TER |= mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Tamper Enable Register. + * + * This function clears specified tamper enable bits in TDET Tamper Enable Register. + * + * param base TDET peripheral base address + * param mask Bit mask for the tamper enable bits to be cleared. + * return kStatus_Fail when Tamper Enable Register writing is not allowed + * return kStatus_Success when specified bits are cleared in the Tamper Enable Register + */ +status_t TDET_DisableTampers(DIGTMP_Type *base, uint32_t mask) +{ + status_t status; + + mask = mask & TDET_ALL_TER_MASK; /* only clear the bits documented in Reference Manual */ + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_TEL_MASK)) + { + base->TER &= ~mask; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the Tamper Seconds Register. + * + * This function writes to TDET Tamper Seconds Register. This causes Status Register DTF flag to be set (TDET + * tampering detected). + * + * param base TDET peripheral base address + * return kStatus_Fail when Tamper Seconds Register writing is not allowed + * return kStatus_Success when Tamper Seconds Register is written + */ +status_t TDET_ForceTamper(DIGTMP_Type *base) +{ + status_t status; + + if (tdet_IsRegisterWriteAllowed(base, DIGTMP_LR_TSL_MASK)) + { + base->TSR = 0; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Reads the Tamper Seconds Register. + * + * This function reads TDET Tamper Seconds Register. The read value returns the time in seconds at which the Status + * Register DTF flag was set. + * + * param base TDET peripheral base address + * param tamperTimeSeconds Time in seconds at which the tamper detection SR[DTF] flag was set. + * return kStatus_Fail when Tamper Seconds Register reading is not allowed + * return kStatus_Success when Tamper Seconds Register is read + */ +status_t TDET_GetTamperTimeSeconds(DIGTMP_Type *base, uint32_t *tamperTimeSeconds) +{ + status_t status; + + if (tamperTimeSeconds != NULL) + { + *tamperTimeSeconds = base->TSR; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Writes to the TDET Lock Register. + * + * This function clears specified lock bits in the TDET Lock Register. + * When a lock bit is clear, a write to corresponding TDET Register is ignored. + * Once cleared, these bits can only be set by VBAT POR or software reset. + * + * param base TDET peripheral base address + * param mask Bit mask for the lock bits to be cleared. Use tdet_register_t values to encode (OR'ed) which TDET + * Registers shall be locked. + */ +void TDET_LockRegisters(DIGTMP_Type *base, uint32_t mask) +{ + mask &= (uint32_t)kTDET_AllRegisters; /* make sure only documented registers are selected by the mask */ + base->LR &= ~mask; /* clear the selected bits */ +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_tdet.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_tdet.h new file mode 100644 index 0000000000..e56234933d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_tdet.h @@ -0,0 +1,601 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_TDET_H_ +#define FSL_TDET_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup TDET + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines TDET driver version 2.1.0. + * + * Change log: + * - Version 2.1.0 + * - Added setting of disabling prescaler on tamper event into TDET_SetConfig() and TDET_GetDefaultConfig functions. + * - Version 2.0.0 + * - Initial version + */ +#define FSL_TDET_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! + * @brief TDET Update Mode. + * + * These constants allow TDET interrupts to be cleared if no tampering has been detected, while still preventing + * the TDET Tamper Flag (SR[DTF]) from being cleared once it is set. + */ +typedef enum _tdet_update_mode +{ + kTDET_StatusLockNormal = 0U, /*!< TDET Status Register cannot be written when the Status Register Lock bit + within the Lock Register (LR[SRL]) is clear */ + kTDET_StatusLockWithTamper = 1U, /*!< TDET Status Register cannot be written when the Status Register Lock bit + within the Lock Register (LR[SRL]) is clear and TDET Tamper Flag (SR[DTF]) + is set*/ +} tdet_update_mode_t; + +/*! + * @brief TDET Active Tamper Clock Source. + * + * These constants define the clock source for Active Tamper Shift Register to configure in a TDET base. + */ +typedef enum _tdet_active_tamper_clock +{ + kTDET_ClockType1Hz = 0U, /*!< clocked by 1 Hz prescaler clock */ + kTDET_ClockType64Hz = 1U, /*!< clocked by 614 Hz prescaler clock */ +} tdet_active_tamper_clock_t; + +/*! + * @brief TDET Control Register. + * + * This structure defines values for TDET Control Register. + */ +typedef struct _tdet_config +{ + bool innerClockAndPrescalerEnable; /*!< Enable/disable 32768 Hz clock within TDET and the TDET prescaler that + generates 512 Hz, 64Hz and 1 Hz prescaler clocks */ + bool tamperForceSystemResetEnable; /*!< Enable/disable assertion of chip reset when tampering is detected */ + enum _tdet_update_mode updateMode; /*!< Selects update mode for TDET Status Register */ + enum _tdet_active_tamper_clock + clockSourceActiveTamper0; /*!< Selects clock source for Active Tamper Shift Register 0 */ + enum _tdet_active_tamper_clock + clockSourceActiveTamper1; /*!< Selects clock source for Active Tamper Shift Register 1 */ + bool disablePrescalerAfterTamper; /*!< Allows the 32-KHz clock and prescaler to be automatically disabled after + tamper detection and until the system acknowledges the tamper. Disabling the + prescaler after detecting a tamper event conserves power and freezes the state + of the active tamper outputs and glitch filters. To ensure a clean transition, + the prescaler is disabled at the end of a 1 Hz period. */ + uint32_t prescaler; /*!< Initial value for the TDET prescaler 15-bit value. */ +} tdet_config_t; + +/*! + * @brief TDET Tamper Pin Polarity. + * + * These constants define tamper pin polarity to configure in a TDET base. + */ +typedef enum _tdet_pin_polarity +{ + kTDET_TamperPinPolarityExpectNormal = 0U, /*!< Tamper pin expected value is not inverted */ + kTDET_TamperPinPolarityExpectInverted = 1U, /*!< Tamper pin expected value is inverted */ +} tdet_pin_polarity_t; + +/*! + * @brief TDET Tamper Pin Direction. + * + * These constants define tamper pin direction to configure in a TDET base. + */ +typedef enum _tdet_pin_direction +{ + kTDET_TamperPinDirectionIn = 0U, /*!< Tamper pins configured as input */ + kTDET_TamperPinDirectionOut = 1U, /*!< Tamper pins configured as output, drives inverse of expected value */ +} tdet_pin_direction_t; + +/*! + * @brief TDET Glitch Filter Tamper Pin Sample Frequency. + * + * These constants define tamper pin glitch filter sample frequency to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_sample_freq +{ + kTDET_GlitchFilterSamplingEveryCycle8 = 0U, /*!< Sample once every 8 cycles */ + kTDET_GlitchFilterSamplingEveryCycle32 = 1U, /*!< Sample once every 32 cycles */ + kTDET_GlitchFilterSamplingEveryCycle128 = 2U, /*!< Sample once every 128 cycles */ + kTDET_GlitchFilterSamplingEveryCycle512 = 3U, /*!< Sample once every 512 cycles */ +} tdet_glitch_filter_sample_freq_t; +/*! + * @brief TDET Glitch Filter Tamper Pin Sample Width. + * + * These constants define tamper pin glitch filter sample width to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_sample_width +{ + kTDET_GlitchFilterSampleDisable = 0U, /*!< Sampling disabled */ + kTDET_GlitchFilterSampleCycle2 = 1U, /*!< Sample width pull enable/input buffer enable=2 cycles/1 cycle */ + kTDET_GlitchFilterSampleCycle4 = 2U, /*!< Sample width pull enable/input buffer enable=4 cycles/2 cycles */ + kTDET_GlitchFilterSampleCycle8 = 3U, /*!< Sample width pull enable/input buffer enable=8 cycles/4 cycles */ +} tdet_glitch_filter_sample_width_t; + +/*! + * @brief TDET Glitch Filter Tamper Pin Clock Source. + * + * These constants define tamper pin glitch filter clock source to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_prescaler +{ + kTDET_GlitchFilterClock512Hz = 0U, /*!< Glitch Filter on tamper pin is clocked by the 512 Hz prescaler clock */ + kTDET_GlitchFilterClock32768Hz = 1U, /*!< Glitch Filter on tamper pin is clocked by the 32768 Hz prescaler clock */ +} tdet_glitch_filter_prescaler_t; + +/*! + * @brief TDET Glitch Filter Tamper Pin Expected Value. + * + * These constants define tamper pin glitch filter expected value to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_expected +{ + kTDET_GlitchFilterExpectedLogicZero = 0U, /*!< Expected value is logic zero */ + kTDET_GlitchFilterExpectedActTamperOut0 = 1U, /*!< Expected value is active tamper 0 output */ + kTDET_GlitchFilterExpectedActTamperOut1 = 2U, /*!< Expected value is active tamper 1 output */ + kTDET_GlitchFilterExpectedActTamperOutXOR = + 3U, /*!< Expected value is active tamper 0 output XORed with active tamper 1 output */ +} tdet_glitch_filter_expected_t; + +/*! + * @brief TDET Glitch Filter Tamper Pull Select. + * + * These constants define tamper pin glitch filter pull direction to configure in a TDET base. + */ +typedef enum _tdet_glitch_filter_pull +{ + kTDET_GlitchFilterPullTypeAssert = 0U, /*!< Tamper pin pull direction always asserts the tamper pin. */ + kTDET_GlitchFilterPullTypeNegate = 1U, /*!< Tamper pin pull direction always negates the tamper pin. */ +} tdet_glitch_filter_pull_t; + +/*! + * @brief TDET Tamper Pin configuration registers. + * + * This structure defines values for TDET Pin Direction, Pin Polarity, and Glitch Filter registers. + */ +typedef struct _tdet_pin_config +{ + enum _tdet_pin_polarity pinPolarity; /*!< Selects tamper pin expected value */ + enum _tdet_pin_direction pinDirection; /*!< Selects tamper pin direction */ + bool tamperPullEnable; /*!< Enable/disable pull resistor on the tamper pin */ + enum _tdet_glitch_filter_sample_freq tamperPinSampleFrequency; /*!< Selects tamper pin sample frequency */ + enum _tdet_glitch_filter_sample_width tamperPinSampleWidth; /*!< Selects tamper pin sample width */ + bool glitchFilterEnable; /*!< Enable/disable glitch filter on the tamper pin */ + enum _tdet_glitch_filter_prescaler + glitchFilterPrescaler; /*!< Selects the prescaler for the glitch filter on tamper pin */ + + uint8_t glitchFilterWidth; /*!< 6-bit value to configure number of clock edges the input must remain stable for to + be passed through the glitch filter for the tamper pin */ + + enum _tdet_glitch_filter_expected tamperPinExpected; /*!< Selects tamper pin expected value */ + enum _tdet_glitch_filter_pull tamperPullSelect; /*!< Selects the direction of the tamper pin pull resistor */ +} tdet_pin_config_t; + +/*! @brief List of TDET external tampers */ +typedef enum _tdet_external_tamper_pin +{ + kTDET_ExternalTamper0 = 1U << 0, + kTDET_ExternalTamper1 = 1U << 1, + kTDET_ExternalTamper2 = 1U << 2, + kTDET_ExternalTamper3 = 1U << 3, + kTDET_ExternalTamper4 = 1U << 4, + kTDET_ExternalTamper5 = 1U << 5, + kTDET_ExternalTamper6 = 1U << 6, + kTDET_ExternalTamper7 = 1U << 7 +} tdet_external_tamper_pin_t; + +/*! + * @brief TDET Active Tamper Register Select. + * + * These constants are used to define activeTamperRegisterSelect argument to be used with + * TDET_ActiveTamperConfigure(). + */ +typedef enum _tdet_active_tamper_register +{ + kTDET_ActiveTamperRegister0 = 1u << 0, + kTDET_ActiveTamperRegister1 = 1u << 1, +} tdet_active_tamper_register_t; + +/*! + * @brief TDET Active Tamper registers. + * + * This structure defines values for TDET Active Tamper Registers. + */ +typedef struct _tdet_active_tamper_config +{ + uint32_t activeTamperShift; /*!< Active tamper shift register. initialize to non-zero value. */ + uint32_t activeTamperPolynomial; /*!< Polynomial of the active tamper shift register. */ +} tdet_active_tamper_config_t; + +/*! + * @brief TDET Status Register flags. + * + * This provides constants for the TDET Status Register. + */ +typedef enum _tdet_status_flag +{ + kTDET_StatusTamperFlag = 1U << DIGTMP_SR_DTF_SHIFT, /*!< TDET Digital Tamper Flag */ + kTDET_StatusTamperAcknowledgeFlag = 1U << DIGTMP_SR_TAF_SHIFT, /*!< TDET Tamper Acknowledge Flag */ + kTDET_StatusClockTamper = 1U << DIGTMP_IER_TIIE0_SHIFT, /*!< TDET Clock Tamper detected */ + kTDET_StatusConfigurationTamper = 1U << DIGTMP_IER_TIIE1_SHIFT, /*!< TDET Configuration Tamper detected */ + kTDET_StatusVoltageTamper = 1U << DIGTMP_IER_TIIE2_SHIFT, /*!< TDET Voltage Tamper detected */ + kTDET_StatusTemperatureTamper = 1U << DIGTMP_IER_TIIE3_SHIFT, /*!< TDET Temperature Tamper detected */ + kTDET_StatusRamZeroizeTamper = 1U << DIGTMP_IER_TIIE6_SHIFT, /*!< TDET RAM Zeroize Tamper detected */ + kTDET_StatusTamperPinTamper0 = 1U << DIGTMP_IER_TPIE0_SHIFT, /*!< TDET Tamper Pin 0 Tamper detected */ + kTDET_StatusTamperPinTamper1 = 1U << DIGTMP_IER_TPIE1_SHIFT, /*!< TDET Tamper Pin 1 Tamper detected */ + kTDET_StatusTamperPinTamper2 = 1U << DIGTMP_IER_TPIE2_SHIFT, /*!< TDET Tamper Pin 2 Tamper detected */ + kTDET_StatusTamperPinTamper3 = 1U << DIGTMP_IER_TPIE3_SHIFT, /*!< TDET Tamper Pin 3 Tamper detected */ + kTDET_StatusTamperPinTamper4 = 1U << DIGTMP_IER_TPIE4_SHIFT, /*!< TDET Tamper Pin 4 Tamper detected */ + kTDET_StatusTamperPinTamper5 = 1U << DIGTMP_IER_TPIE5_SHIFT, /*!< TDET Tamper Pin 5 Tamper detected */ + kTDET_StatusTamperPinTamper6 = 1U << DIGTMP_IER_TPIE6_SHIFT, /*!< TDET Tamper Pin 6 Tamper detected */ + kTDET_StatusTamperPinTamper7 = 1U << DIGTMP_IER_TPIE7_SHIFT, /*!< TDET Tamper Pin 7 Tamper detected */ + kTDET_StatusAll = DIGTMP_SR_DTF_MASK | DIGTMP_SR_TAF_MASK | DIGTMP_IER_TIIE0_MASK | DIGTMP_IER_TIIE1_MASK | + DIGTMP_IER_TIIE2_MASK | DIGTMP_IER_TIIE3_MASK | DIGTMP_IER_TIIE6_MASK | DIGTMP_IER_TPIE0_MASK | + DIGTMP_IER_TPIE1_MASK | DIGTMP_IER_TPIE2_MASK | DIGTMP_IER_TPIE3_MASK | DIGTMP_IER_TPIE4_MASK | + DIGTMP_IER_TPIE5_MASK | DIGTMP_IER_TPIE6_MASK | + DIGTMP_IER_TPIE7_MASK, /*!< Mask for all of the TDET Status Register bits */ +} tdet_status_flag_t; + +/*! + * @brief TDET Interrupt Enable Register. + * + * This provides constants for the TDET Interrupt Enable Register. + */ +typedef enum _tdet_interrupt +{ + kTDET_InterruptTamper = 1U << DIGTMP_IER_DTIE_SHIFT, /*!< TDET Digital Tamper Interrupt */ + kTDET_InterruptClockTamper = 1U << DIGTMP_IER_TIIE0_SHIFT, /*!< TDET Clock Tamper Interrupt */ + kTDET_InterruptConfigurationTamper = 1U << DIGTMP_IER_TIIE1_SHIFT, /*!< TDET Configuration error */ + kTDET_InterruptVoltageTamper = 1U << DIGTMP_IER_TIIE2_SHIFT, /*!< TDET Voltage Tamper */ + kTDET_InterruptTemperatureTamper = 1U << DIGTMP_IER_TIIE3_SHIFT, /*!< TDET Temperature Tamper Interrupt */ + kTDET_InterruptRamZeroizeTamper = 1U << DIGTMP_IER_TIIE6_SHIFT, /*!< TDET RAM Zeroize Tamper Interrupt */ + kTDET_InterruptTamperPinTamper0 = 1U << DIGTMP_IER_TPIE0_SHIFT, /*!< TDET Tamper Pin Tamper 0 Interrupt */ + kTDET_InterruptTamperPinTamper1 = 1U << DIGTMP_IER_TPIE1_SHIFT, /*!< TDET Tamper Pin Tamper 1 Interrupt */ + kTDET_InterruptTamperPinTamper2 = 1U << DIGTMP_IER_TPIE2_SHIFT, /*!< TDET Tamper Pin Tamper 2 Interrupt */ + kTDET_InterruptTamperPinTamper3 = 1U << DIGTMP_IER_TPIE3_SHIFT, /*!< TDET Tamper Pin Tamper 3 Interrupt */ + kTDET_InterruptTamperPinTamper4 = 1U << DIGTMP_IER_TPIE4_SHIFT, /*!< TDET Tamper Pin Tamper 4 Interrupt */ + kTDET_InterruptTamperPinTamper5 = 1U << DIGTMP_IER_TPIE5_SHIFT, /*!< TDET Tamper Pin Tamper 5 Interrupt */ + kTDET_InterruptTamperPinTamper6 = 1U << DIGTMP_IER_TPIE6_SHIFT, /*!< TDET Tamper Pin Tamper 6 Interrupt */ + kTDET_InterruptTamperPinTamper7 = 1U << DIGTMP_IER_TPIE7_SHIFT, /*!< TDET Tamper Pin Tamper 7 Interrupt */ + kTDET_InterruptTamperPinTamper_All = DIGTMP_IER_TPIE0_MASK | DIGTMP_IER_TPIE1_MASK | DIGTMP_IER_TPIE2_MASK | + DIGTMP_IER_TPIE3_MASK | DIGTMP_IER_TPIE4_MASK | DIGTMP_IER_TPIE5_MASK | + DIGTMP_IER_TPIE6_MASK | + DIGTMP_IER_TPIE7_MASK, /*!< TDET All Tamper Pins Interrupt */ + kTDET_InterruptAll = DIGTMP_IER_DTIE_MASK | DIGTMP_IER_TIIE0_MASK | DIGTMP_IER_TIIE1_MASK | DIGTMP_IER_TIIE2_MASK | + DIGTMP_IER_TIIE3_MASK | DIGTMP_IER_TIIE6_MASK | DIGTMP_IER_TPIE0_MASK | DIGTMP_IER_TPIE1_MASK | + DIGTMP_IER_TPIE2_MASK | DIGTMP_IER_TPIE3_MASK | DIGTMP_IER_TPIE4_MASK | DIGTMP_IER_TPIE5_MASK | + DIGTMP_IER_TPIE6_MASK | + DIGTMP_IER_TPIE7_MASK, /*!< Mask to select all TDET Interrupt Enable Register bits */ +} tdet_interrupt_t; + +/*! + * @brief TDET Tamper Enable Register. + * + * This provides constants for the TDET Tamper Enable Register. + */ +typedef enum _tdet_tamper +{ + kTDET_TamperClock = 1U << DIGTMP_TER_TIE0_SHIFT, /*!< Clock Tamper Enable */ + kTDET_TamperConfiguration = 1U << DIGTMP_TER_TIE1_SHIFT, /*!< Configuration error Tamper Enable */ + kTDET_TamperVoltage = 1U << DIGTMP_TER_TIE2_SHIFT, /*!< Voltage Tamper Enable */ + kTDET_TamperTemperature = 1U << DIGTMP_TER_TIE3_SHIFT, /*!< Temperature Tamper Enable */ + kTDET_TamperRamZeroize = 1U << DIGTMP_TER_TIE6_SHIFT, /*!< RAM Zeroize Tamper Enable */ + kTDET_TamperTamperPin0 = 1U << DIGTMP_TER_TPE0_SHIFT, /*!< Tamper Pin 0 Tamper Enable */ + kTDET_TamperTamperPin1 = 1U << DIGTMP_TER_TPE1_SHIFT, /*!< Tamper Pin 1 Tamper Enable */ + kTDET_TamperTamperPin2 = 1U << DIGTMP_TER_TPE2_SHIFT, /*!< Tamper Pin 2 Tamper Enable */ + kTDET_TamperTamperPin3 = 1U << DIGTMP_TER_TPE3_SHIFT, /*!< Tamper Pin 3 Tamper Enable */ + kTDET_TamperTamperPin4 = 1U << DIGTMP_TER_TPE4_SHIFT, /*!< Tamper Pin 4 Tamper Enable */ + kTDET_TamperTamperPin5 = 1U << DIGTMP_TER_TPE5_SHIFT, /*!< Tamper Pin 5 Tamper Enable */ + kTDET_TamperTamperPin6 = 1U << DIGTMP_TER_TPE6_SHIFT, /*!< Tamper Pin 6 Tamper Enable */ + kTDET_TamperTamperPin7 = 1U << DIGTMP_TER_TPE7_SHIFT, /*!< Tamper Pin 7 Tamper Enable */ + kTDET_TamperTamperPinAll = DIGTMP_TER_TPE0_MASK | DIGTMP_TER_TPE1_MASK | DIGTMP_TER_TPE2_MASK | + DIGTMP_TER_TPE3_MASK | DIGTMP_TER_TPE4_MASK | DIGTMP_TER_TPE5_MASK | + DIGTMP_TER_TPE6_MASK | DIGTMP_TER_TPE7_MASK, /*!< All Tamper Pin Tamper Enable */ + kTDET_TamperAll = DIGTMP_TER_TIE0_MASK | DIGTMP_TER_TIE1_MASK | DIGTMP_TER_TIE2_MASK | DIGTMP_TER_TIE3_MASK | + DIGTMP_TER_TIE6_MASK | DIGTMP_TER_TPE0_MASK | DIGTMP_TER_TPE1_MASK | DIGTMP_TER_TPE2_MASK | + DIGTMP_TER_TPE3_MASK | DIGTMP_TER_TPE4_MASK | DIGTMP_TER_TPE5_MASK | DIGTMP_TER_TPE6_MASK | + DIGTMP_TER_TPE7_MASK, /*!< Mask to select all Tamper Enable Register bits */ +} tdet_tamper_t; + +/*! + * @brief TDET Registers. + * + * This provides constants to encode a mask for the TDET Registers. + */ +typedef enum _tdet_register +{ + kTDET_NoRegister = 0U, /*!< No Register */ + kTDET_Control = 1U << DIGTMP_LR_CRL_SHIFT, /*!< Control Register */ + kTDET_Status = 1U << DIGTMP_LR_SRL_SHIFT, /*!< Status Register */ + kTDET_Lock = 1U << DIGTMP_LR_LRL_SHIFT, /*!< Lock Register */ + kTDET_InterruptEnable = 1U << DIGTMP_LR_IEL_SHIFT, /*!< Interrupt Enable Register */ + kTDET_TamperSeconds = 1U << DIGTMP_LR_TSL_SHIFT, /*!< Tamper Seconds Register */ + kTDET_TamperEnable = 1U << DIGTMP_LR_TEL_SHIFT, /*!< Tamper Enable Register */ + kTDET_PinDirection = 1U << DIGTMP_LR_PDL_SHIFT, /*!< Pin Direction Register */ + kTDET_PinPolarity = 1U << DIGTMP_LR_PPL_SHIFT, /*!< Pin Polarity Register */ + kTDET_ActiveTamper0 = 1U << DIGTMP_LR_ATL0_SHIFT, /*!< Active Tamper Register 0 */ + kTDET_ActiveTamper1 = 1U << DIGTMP_LR_ATL1_SHIFT, /*!< Active Tamper Register 1 */ + kTDET_GlitchFilter0 = 1U << DIGTMP_LR_GFL0_SHIFT, /*!< Glitch Filter Register 0 */ + kTDET_GlitchFilter1 = 1U << DIGTMP_LR_GFL1_SHIFT, /*!< Glitch Filter Register 1 */ + kTDET_GlitchFilter2 = 1U << DIGTMP_LR_GFL2_SHIFT, /*!< Glitch Filter Register 2 */ + kTDET_GlitchFilter3 = 1U << DIGTMP_LR_GFL3_SHIFT, /*!< Glitch Filter Register 3 */ + kTDET_GlitchFilter4 = 1U << DIGTMP_LR_GFL4_SHIFT, /*!< Glitch Filter Register 4 */ + kTDET_GlitchFilter5 = 1U << DIGTMP_LR_GFL5_SHIFT, /*!< Glitch Filter Register 5 */ + kTDET_GlitchFilter6 = 1U << DIGTMP_LR_GFL6_SHIFT, /*!< Glitch Filter Register 6 */ + kTDET_GlitchFilter7 = 1U << DIGTMP_LR_GFL7_SHIFT, /*!< Glitch Filter Register 7 */ + kTDET_PinConfigurationRegisters = + DIGTMP_LR_PDL_MASK | DIGTMP_LR_PPL_MASK | DIGTMP_LR_ATL0_MASK | DIGTMP_LR_ATL1_MASK | DIGTMP_LR_GFL0_MASK | + DIGTMP_LR_GFL1_MASK | DIGTMP_LR_GFL2_MASK | DIGTMP_LR_GFL3_MASK | DIGTMP_LR_GFL4_MASK | DIGTMP_LR_GFL5_MASK | + DIGTMP_LR_GFL6_MASK | DIGTMP_LR_GFL7_MASK, /*!< Mask to select all TDET Pin Configuration Registers */ + kTDET_AllRegisters = DIGTMP_LR_CRL_MASK | DIGTMP_LR_SRL_MASK | DIGTMP_LR_LRL_MASK | DIGTMP_LR_IEL_MASK | + DIGTMP_LR_TSL_MASK | DIGTMP_LR_TEL_MASK | DIGTMP_LR_PDL_MASK | DIGTMP_LR_PPL_MASK | + DIGTMP_LR_ATL0_MASK | DIGTMP_LR_ATL1_MASK | DIGTMP_LR_GFL0_MASK | DIGTMP_LR_GFL1_MASK | + DIGTMP_LR_GFL2_MASK | DIGTMP_LR_GFL3_MASK | DIGTMP_LR_GFL4_MASK | DIGTMP_LR_GFL5_MASK | + DIGTMP_LR_GFL6_MASK | DIGTMP_LR_GFL7_MASK, /*!< Mask to select all TDET Registers */ +} tdet_register_t; + +/******************************************************************************* + * API + *******************************************************************************/ +extern void VBAT0_DriverIRQHandler(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name TDET Functional Operation + * @{ + */ + +/*! + * @brief Initialize TDET + * + * This function initializes TDET. + * + * @param base TDET peripheral base address + * @return Status of the init operation + */ +status_t TDET_Init(DIGTMP_Type *base); + +/*! + * @brief Deinitialize TDET + * + * This function disables glitch filters and active tampers + * This function disables the TDET clock and prescaler in TDET Control Register. + * @param base TDET peripheral base address + */ +void TDET_Deinit(DIGTMP_Type *base); + +/*! + * @brief Gets default values for the TDET Control Register. + * + * This function fills the given structure with default values for the TDET Control Register. + * The default values are: + * @code + * defaultConfig->innerClockAndPrescalerEnable = true + * defaultConfig->tamperForceSystemResetEnable = false + * defaultConfig->updateMode = kTDET_StatusLockWithTamper + * defaultConfig->clockSourceActiveTamper0 = kTDET_ClockType1Hz + * defaultConfig->clockSourceActiveTamper1 = kTDET_ClockType1Hz + * defaultConfig->prescaler = 0 + * @endcode + * @param base TDET peripheral base address + * @param[out] defaultConfig Pointer to structure to be filled with default parameters + */ +void TDET_GetDefaultConfig(DIGTMP_Type *base, tdet_config_t *defaultConfig); + +/*! + * @brief Writes to the TDET Control Register. + * + * This function writes the given structure to the TDET Control Register. + * @param base TDET peripheral base address + * @param config Pointer to structure with TDET peripheral configuration parameters + * @return kStatus_Fail when writing to TDET Control Register is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_SetConfig(DIGTMP_Type *base, const tdet_config_t *config); + +/*! + * @brief Software reset. + * + * This function resets all TDET registers. The CR[SWR] itself is not affected; + * it is reset by VBAT POR only. + * + * @param base TDET peripheral base address + * @return kStatus_Fail when writing to TDET Control Register is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_SoftwareReset(DIGTMP_Type *base); + +/*! + * @brief Writes to the active tamper register(s). + * + * This function writes per active tamper register parameters to active tamper register(s). + * + * @param base TDET peripheral base address + * @param activeTamperConfig Pointer to structure with active tamper register parameters + * @param activeTamperRegisterSelect Bit mask for active tamper registers to be configured. The passed value is + * combination of tdet_active_tamper_register_t values (OR'ed). + * @return kStatus_Fail when writing to TDET Active Tamper Register(s) is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_ActiveTamperSetConfig(DIGTMP_Type *base, + const tdet_active_tamper_config_t *activeTamperConfig, + uint32_t activeTamperRegisterSelect); + +/*! + * @brief Gets default values for tamper pin configuration. + * + * This function fills the give structure with default values for the tamper pin and glitch filter configuration. + * The default values are: + * code + * pinConfig->pinPolarity = kTDET_TamperPinPolarityExpectNormal; + * pinConfig->pinDirection = kTDET_TamperPinDirectionIn; + * pinConfig->tamperPullEnable = false; + * pinConfig->tamperPinSampleFrequency = kTDET_GlitchFilterSamplingEveryCycle8; + * pinConfig->tamperPinSampleWidth = kTDET_GlitchFilterSampleDisable; + * pinConfig->glitchFilterEnable = false; + * pinConfig->glitchFilterPrescaler = kTDET_GlitchFilterClock512Hz; + * pinConfig->glitchFilterWidth = 0; + * pinConfig->tamperPinExpected = kTDET_GlitchFilterExpectedLogicZero; + * pinConfig->tamperPullSelect = kTDET_GlitchFilterPullTypeAssert; + * endcode + * + * @param base TDET peripheral base address + * @param[out] pinConfig Pointer to structure to be filled with tamper pins default parameters + */ + +void TDET_PinGetDefaultConfig(DIGTMP_Type *base, tdet_pin_config_t *pinConfig); + +/*! + * @brief Writes the tamper pin configuration. + * + * This function writes per pin parameters to tamper pin and glitch filter configuration registers. + * + * @param base TDET peripheral base address + * @param pinConfig Pointer to structure with tamper pin and glitch filter configuration parameters + * @param pinSelect Bit mask for tamper pins to be configured. The passed value is combination of + * enum _tdet_tamper_pin (tdet_tamper_pin_t) values (OR'ed). + * @return kStatus_Fail when writing to TDET Pin Direction, Pin Polarity or Glitch Filter Register(s) is not allowed + * @return kStatus_Success when operation completes successfully + */ +status_t TDET_PinSetConfig(DIGTMP_Type *base, const tdet_pin_config_t *pinConfig, uint32_t pinSelect); + +/*! + * @brief Reads the Status Register. + * + * This function reads flag bits from TDET Status Register. + * + * @param base TDET peripheral base address + * @param[out] result Pointer to uint32_t where to write Status Register read value. Use tdet_status_flag_t to decode + * individual flags. + * @return kStatus_Fail when Status Register reading is not allowed + * @return kStatus_Success when result is written with the Status Register read value + */ +status_t TDET_GetStatusFlags(DIGTMP_Type *base, uint32_t *result); + +/*! + * @brief Writes to the Status Register. + * + * This function clears specified flag bits in TDET Status Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the flag bits to be cleared. Use tdet_status_flag_t to encode flags. + * @return kStatus_Fail when Status Register writing is not allowed + * @return kStatus_Success when mask is written to the Status Register + */ +status_t TDET_ClearStatusFlags(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Interrupt Enable Register. + * + * This function sets specified interrupt enable bits in TDET Interrupt Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the interrupt enable bits to be set. + * @return kStatus_Fail when Interrupt Enable Register writing is not allowed + * @return kStatus_Success when mask is written to the Interrupt Enable Register + */ +status_t TDET_EnableInterrupts(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Interrupt Enable Register. + * + * This function clears specified interrupt enable bits in TDET Interrupt Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the interrupt enable bits to be cleared. + * @return kStatus_Fail when Interrupt Enable Register writing is not allowed + * @return kStatus_Success when specified bits are cleared in the Interrupt Enable Register + */ +status_t TDET_DisableInterrupts(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Tamper Enable Register. + * + * This function sets specified tamper enable bits in TDET Tamper Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the tamper enable bits to be set. + * @return kStatus_Fail when Tamper Enable Register writing is not allowed + * @return kStatus_Success when mask is written to the Tamper Enable Register + */ +status_t TDET_EnableTampers(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Tamper Enable Register. + * + * This function clears specified tamper enable bits in TDET Tamper Enable Register. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the tamper enable bits to be cleared. + * @return kStatus_Fail when Tamper Enable Register writing is not allowed + * @return kStatus_Success when specified bits are cleared in the Tamper Enable Register + */ +status_t TDET_DisableTampers(DIGTMP_Type *base, uint32_t mask); + +/*! + * @brief Writes to the Tamper Seconds Register. + * + * This function writes to TDET Tamper Seconds Register. This causes Status Register DTF flag to be set (TDET + * tampering detected). + * + * @param base TDET peripheral base address + * @return kStatus_Fail when Tamper Seconds Register writing is not allowed + * @return kStatus_Success when Tamper Seconds Register is written + */ +status_t TDET_ForceTamper(DIGTMP_Type *base); + +/*! + * @brief Reads the Tamper Seconds Register. + * + * This function reads TDET Tamper Seconds Register. The read value returns the time in seconds at which the Status + * Register DTF flag was set. + * + * @param base TDET peripheral base address + * @param tamperTimeSeconds Time in seconds at which the tamper detection SR[DTF] flag was set. + * @return kStatus_Fail when Tamper Seconds Register reading is not allowed + * @return kStatus_Success when Tamper Seconds Register is read + */ +status_t TDET_GetTamperTimeSeconds(DIGTMP_Type *base, uint32_t *tamperTimeSeconds); + +/*! + * @brief Writes to the TDET Lock Register. + * + * This function clears specified lock bits in the TDET Lock Register. + * When a lock bit is clear, a write to corresponding TDET Register is ignored. + * Once cleared, these bits can only be set by VBAT POR or software reset. + * + * @param base TDET peripheral base address + * @param mask Bit mask for the lock bits to be cleared. Use tdet_register_t values to encode (OR'ed) which TDET + * Registers shall be locked. + */ +void TDET_LockRegisters(DIGTMP_Type *base, uint32_t mask); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group tdet */ + +#endif /* FSL_TDET_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_utick.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_utick.c new file mode 100644 index 0000000000..0eea419cd3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_utick.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_utick.h" +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) +#include "fsl_power.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.utick" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base UTICK peripheral base address + * + * @return The UTICK instance + */ +static uint32_t UTICK_GetInstance(UTICK_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UTICK handle. */ +static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; +/* Array of UTICK peripheral base address. */ +static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; +/* Array of UTICK IRQ number. */ +static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UTICK clock name. */ +static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) +/*! @brief Pointers to UTICK resets for each instance. */ +static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; +#endif + +/* UTICK ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; +#else +static utick_isr_t s_utickIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t UTICK_GetInstance(UTICK_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) + { + if (s_utickBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_utickBases)); + + return instance; +} + +/*! + * brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * param base UTICK peripheral base address. + * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) +{ + uint32_t instance; + + /* Get instance from peripheral base address. */ + instance = UTICK_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_utickHandle[instance] = cb; +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ + !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) + EnableDeepSleepIRQ(s_utickIRQ[instance]); +#else + (void)EnableIRQ(s_utickIRQ[instance]); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ + base->CTRL = count | UTICK_CTRL_REPEAT(mode); +} + +/*! + * brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable utick clock */ + CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) + RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) + /* Power up Watchdog oscillator*/ + POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); +#endif + + s_utickIsr = UTICK_HandleIRQ; +} + +/*! + * brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base) +{ + /* Turn off utick */ + base->CTRL = 0; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable utick clock */ + CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif +} + +/*! + * brief Get Status Flags. + * + * This returns the status flag + * + * param base UTICK peripheral base address. + * return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base) +{ + return (base->STAT); +} + +/*! + * brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * param base UTICK peripheral base address. + * return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base) +{ + base->STAT = UTICK_STAT_INTR_MASK; +} + +/*! + * brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * param base UTICK peripheral base address. + * param cb callback scheduled for this instance of UTICK + * return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) +{ + UTICK_ClearStatusFlags(base); + if (cb != NULL) + { + cb(); + } +} + +#if defined(UTICK0) +void UTICK0_DriverIRQHandler(void); +void UTICK0_DriverIRQHandler(void) +{ + s_utickIsr(UTICK0, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK1) +void UTICK1_DriverIRQHandler(void); +void UTICK1_DriverIRQHandler(void) +{ + s_utickIsr(UTICK1, s_utickHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK2) +void UTICK2_DriverIRQHandler(void); +void UTICK2_DriverIRQHandler(void) +{ + s_utickIsr(UTICK2, s_utickHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK) +void UTICK_DriverIRQHandler(void); +void UTICK_DriverIRQHandler(void) +{ + s_utickIsr(UTICK, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_utick.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_utick.h new file mode 100644 index 0000000000..836b518f4c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_utick.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_UTICK_H_ +#define FSL_UTICK_H_ + +#include "fsl_common.h" +/*! + * @addtogroup utick + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief UTICK driver version 2.0.5. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*@}*/ + +/*! @brief UTICK timer operational mode. */ +typedef enum _utick_mode +{ + kUTICK_Onetime = 0x0U, /*!< Trigger once*/ + kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ +} utick_mode_t; + +/*! @brief UTICK callback function. */ +typedef void (*utick_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base); + +/*! + * @brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * @param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base); +/*! + * @brief Get Status Flags. + * + * This returns the status flag + * + * @param base UTICK peripheral base address. + * @return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base); +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * @param base UTICK peripheral base address. + * @return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base); + +/*! + * @brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * @param base UTICK peripheral base address. + * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * @return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); +/*! + * @brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base UTICK peripheral base address. + * @param cb callback scheduled for this instance of UTICK + * @return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_UTICK_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vbat.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vbat.c new file mode 100644 index 0000000000..676adcdf57 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vbat.c @@ -0,0 +1,498 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_vbat.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_vbat" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_fro16k_config_t structure. + */ +void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config) +{ + assert(config != NULL); + + VBAT_EnableFRO16k(base, config->enableFRO16k); + VBAT_UngateFRO16k(base, config->enabledConnectionsMask); +} + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. + * + * param base VBAT peripheral base address. + * param operateMode Specify the crystal oscillator mode, please refer to vbat_osc32k_operate_mode_t. + * param xtalCap Specify the internal capacitance for the XTAL pin from the capacitor bank. + * param extalCap Specify the internal capacitance for the EXTAL pin from the capacitor bank. + * + * retval kStatus_VBAT_WrongCapacitanceValue The load capacitance value to set is not align with operate mode's + * requirements. + * retval kStatus_Success Success to set operate mode and load capacitance. + */ +status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, + vbat_osc32k_operate_mode_t operateMode, + vbat_osc32k_load_capacitance_select_t xtalCap, + vbat_osc32k_load_capacitance_select_t extalCap) +{ + if (operateMode == kVBAT_Osc32kEnabledToTransconductanceMode) + { + if (((uint8_t)extalCap & 0x1U) == 0U) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if (operateMode == kVBAT_Osc32kEnabledToLowPowerSwitchedMode) + { + if ((extalCap != kVBAT_Osc32kCrystalLoadCap0pF) && (xtalCap != kVBAT_Osc32kCrystalLoadCap0pF)) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if (operateMode == kVBAT_Osc32kEnabledToLowPowerBackupMode) + { + if ((extalCap & 0x1U) != 0U) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if ((xtalCap != kVBAT_Osc32kCrystalLoadCapBankDisabled) && (extalCap != kVBAT_Osc32kCrystalLoadCapBankDisabled)) + { + base->OSCCTLA |= VBAT_OSCCTLA_CAP_SEL_EN_MASK; + base->OSCCTLB &= ~VBAT_OSCCTLA_CAP_SEL_EN_MASK; + base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | + (VBAT_OSCCTLA_XTAL_CAP_SEL(xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(extalCap))); + base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | + VBAT_OSCCTLA_XTAL_CAP_SEL(~xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~extalCap)); + } + + base->OSCCTLA = (((base->OSCCTLA & ~VBAT_OSCCTLA_MODE_EN_MASK)) | VBAT_OSCCTLA_MODE_EN(operateMode)); + base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN((uint8_t)~operateMode)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * brief Enable/disable Bandgap. + * + * note The FRO16K must be enabled before enableing the bandgap. + * note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable bandgap. + * - \b true Enable the bandgap. + * - \b false Disable the bandgap. + * + * retval kStatus_Success Success to enable/disable the bandgap. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable the bandgap due to FRO16k is not enabled previously. + */ +status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + base->LDOCTLA |= VBAT_LDOCTLA_BG_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_BG_EN_MASK; + } + else + { + /* FRO16K must be enabled before enabling the Bandgap. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_BG_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_BG_EN_MASK; + } + + return status; +} + +/*! + * brief Enable/disable Backup RAM Regulator(RAM_LDO). + * + * note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable RAM_LDO. + * - \b true Enable backup SRAM regulator. + * - \b false Disable backup SRAM regulator. + * + * retval kStatusSuccess Success to enable/disable backup SRAM regulator. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable backup SRAM regulator due to FRO16k is not enabled previously. + * retval kStatus_VBAT_BandgapNotEnabled Fail to enable backup SRAM regulator due to the bandgap is not enabled + * previously. + */ +status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + base->LDOCTLA |= VBAT_LDOCTLA_LDO_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_LDO_EN_MASK; + /* Polling until LDO is enabled. */ + while ((base->STATUSA & VBAT_STATUSA_LDO_RDY_MASK) == 0UL) + { + } + } + else + { + /* The bandgap must be enabled previously. */ + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + /* FRO16k must be enabled previously. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_LDO_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_LDO_EN_MASK; + } + + return status; +} + +/*! + * brief Switch the SRAM to be powered by VBAT. + * + * param base VBAT peripheral base address. + * + * retval kStatusSuccess Success to Switch SRAM powered by VBAT. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously. + */ +status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base) +{ + status_t status = kStatus_Success; + + status = VBAT_EnableBandgap(base, true); + + if (status == kStatus_Success) + { + VBAT_EnableBandgapRefreshMode(base, true); + (void)VBAT_EnableBackupSRAMRegulator(base, true); + + /* Isolate the SRAM array */ + base->LDORAMC |= VBAT_LDORAMC_ISO_MASK; + /* Switch the supply to VBAT LDO. */ + base->LDORAMC |= VBAT_LDORAMC_SWI_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * brief Enable/disable Bandgap timer. + * + * note The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable bandgap timer. + * param timerIdMask The mask of bandgap timer Id, should be the OR'ed value of vbat_bandgap_timer_id_t. + * + * retval kStatus_Success Success to enable/disable selected bandgap timer. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable/disable selected bandgap timer due to FRO16k not enabled + * previously. retval kStatus_VBAT_BandgapNotEnabled Fail to enable/disable selected bandgap timer due to bandgap not + * enabled previously. + */ +status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer0) != 0U) + { + base->LDOTIMER0 |= VBAT_LDOTIMER0_TIMEN_MASK; + } + + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer1) != 0U) + { + base->LDOTIMER1 |= VBAT_LDOTIMER1_TIMEN_MASK; + } + } + else + { + /* Bandgap must be enabled previously. */ + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + /* FRO16K must be enabled previously. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer0) != 0U) + { + base->LDOTIMER0 &= ~VBAT_LDOTIMER0_TIMEN_MASK; + } + + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer1) != 0U) + { + base->LDOTIMER1 &= ~VBAT_LDOTIMER1_TIMEN_MASK; + } + } + + return status; +} + +/*! + * brief Set bandgap timer0 timeout value. + * + * param base VBAT peripheral base address. + * param timeoutPeriod Bandgap timer timeout value, please refer to vbat_bandgap_timer0_timeout_period_t. + */ +void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod) +{ + bool timerEnabled = false; + + timerEnabled = ((base->LDOTIMER0 & VBAT_LDOTIMER0_TIMEN_MASK) != 0UL) ? true : false; + + if (timerEnabled) + { + base->LDOTIMER0 &= ~VBAT_LDOTIMER0_TIMEN_MASK; + } + + base->LDOTIMER0 = ((base->LDOTIMER0 & (~VBAT_LDOTIMER0_TIMCFG_MASK)) | VBAT_LDOTIMER0_TIMCFG(timeoutPeriod)); + + if (timerEnabled) + { + base->LDOTIMER0 |= VBAT_LDOTIMER0_TIMEN_MASK; + } +} + +/*! + * brief Set bandgap timer1 timeout value. + * + * note The timeout value can only be changed when the timer is disabled. + * + * param base VBAT peripheral base address. + * param timeoutPeriod The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s. + */ +void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod) +{ + bool timerEnabled = false; + + timerEnabled = ((base->LDOTIMER1 & VBAT_LDOTIMER1_TIMEN_MASK) != 0UL) ? true : false; + + if (timerEnabled) + { + base->LDOTIMER1 &= ~VBAT_LDOTIMER1_TIMEN_MASK; + } + + base->LDOTIMER1 = ((base->LDOTIMER1 & (~VBAT_LDOTIMER1_TIMCFG_MASK)) | VBAT_LDOTIMER1_TIMCFG(timeoutPeriod)); + + if (timerEnabled) + { + base->LDOTIMER1 |= VBAT_LDOTIMER1_TIMEN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * brief Initializes the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_clock_monitor_config_t structure. + * + * retval kStatus_Success Clock monitor is initialized successfully. + * retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if ((VBAT_GetStatusFlags(base) & kVBAT_StatusFlagOsc32kReady) != 0UL) + { + if (VBAT_CheckClockMonitorControlLocked(base)) + { + status = kStatus_VBAT_ClockMonitorLocked; + } + else + { + /* Disable clock monitor before configuring clock monitor. */ + VBAT_EnableClockMonitor(base, false); + /* Set clock monitor divide trim value. */ + VBAT_SetClockMonitorDivideTrim(base, config->divideTrim); + /* Set clock monitor frequency trim value. */ + VBAT_SetClockMonitorFrequencyTrim(base, config->freqTrim); + /* Enable clock monitor. */ + VBAT_EnableClockMonitor(base, true); + + if (config->lock) + { + VBAT_LockClockMonitorControl(base); + } + } + } + else + { + status = kStatus_VBAT_OSC32KNotReady; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief Deinitialize the VBAT clock monitor. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Clock monitor is de-initialized successfully. + * retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base) +{ + if (VBAT_CheckClockMonitorControlLocked(base)) + { + return kStatus_VBAT_ClockMonitorLocked; + } + + VBAT_EnableClockMonitor(base, false); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * brief Initialize tamper control. + * + * note Both FRO16K and bandgap should be enabled before calling this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_tamper_config_t structure. + * + * retval kStatus_Success Tamper is initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + * retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + else + { + base->TAMCTLA = ((base->TAMCTLA & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN(config->enableVoltageDetect) | + VBAT_TAMCTLA_TEMP_EN(config->enableTemperatureDetect)); + base->TAMCTLB = ((base->TAMCTLB & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN((config->enableVoltageDetect) ? 0U : 1U) | + VBAT_TAMCTLA_TEMP_EN((config->enableTemperatureDetect) ? 0U : 1U)); + + if (config->lock) + { + VBAT_LockTamperControl(base); + } + } + } + else + { + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief De-initialize tamper control. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Tamper is de-initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base) +{ + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + + base->TAMCTLA &= ~(VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + base->TAMCTLB |= (VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vbat.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vbat.h new file mode 100644 index 0000000000..72290b49fc --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vbat.h @@ -0,0 +1,1386 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_VBAT_H_ +#define FSL_VBAT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mcx_vbat + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief VBAT driver version 2.3.0. */ +#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +#if !defined(VBAT_LDORAMC_RET_MASK) +#define VBAT_LDORAMC_RET_MASK (0xF00U) +#define VBAT_LDORAMC_RET_SHIFT (8U) +#define VBAT_LDORAMC_RET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK) +#endif + +/*! + * @brief The enumeration of VBAT module status. + */ +enum +{ + kStatus_VBAT_Fro16kNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 0), /*!< Internal 16kHz free running + oscillator not enabled. */ + kStatus_VBAT_BandgapNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 1), /*!< Bandgap not enabled. */ + kStatus_VBAT_WrongCapacitanceValue = MAKE_STATUS(kStatusGroup_VBAT, 2), /*!< Wrong capacitance for + selected oscillator mode. */ + kStatus_VBAT_ClockMonitorLocked = MAKE_STATUS(kStatusGroup_VBAT, 3), /*!< Clock monitor locked. */ + kStatus_VBAT_OSC32KNotReady = MAKE_STATUS(kStatusGroup_VBAT, 4), /*!< OSC32K not ready. */ + kStatus_VBAT_LDONotReady = MAKE_STATUS(kStatusGroup_VBAT, 5), /*!< LDO not ready. */ + kStatus_VBAT_TamperLocked = MAKE_STATUS(kStatusGroup_VBAT, 6), /*!< Tamper locked. */ +}; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) +/*! + * @brief The enumeration of VBAT status flags. + * + * @anchor vbat_status_flag_t + */ +enum _vbat_status_flag +{ + kVBAT_StatusFlagPORDetect = VBAT_STATUSA_POR_DET_MASK, /*!< VBAT domain has been reset */ + kVBAT_StatusFlagWakeupPin = VBAT_STATUSA_WAKEUP_FLAG_MASK, /*!< A falling edge is detected on the wakeup pin. */ + kVBAT_StatusFlagBandgapTimer0 = VBAT_STATUSA_TIMER0_FLAG_MASK, /*!< Bandgap Timer0 period reached. */ + kVBAT_StatusFlagBandgapTimer1 = VBAT_STATUSA_TIMER1_FLAG_MASK, /*!< Bandgap Timer1 period reached. */ + kVBAT_StatusFlagLdoReady = VBAT_STATUSA_LDO_RDY_MASK, /*!< LDO is enabled and ready. */ + kVBAT_StatusFlagOsc32kReady = VBAT_STATUSA_OSC_RDY_MASK, /*!< OSC32k is enabled and clock is ready. */ +#if defined(VBAT_STATUSA_CLOCK_DET_MASK) + kVBAT_StatusFlagClockDetect = VBAT_STATUSA_CLOCK_DET_MASK, /*!< The clock monitor has detected an error. */ +#endif /* VBAT_STATUSA_CLOCK_DET_MASK */ + kVBAT_StatusFlagConfigDetect = VBAT_STATUSA_CONFIG_DET_MASK, /*!< Configuration error detected. */ +#if defined(VBAT_STATUSA_VOLT_DET_MASK) + kVBAT_StatusFlagVoltageDetect = VBAT_STATUSA_VOLT_DET_MASK, /*!< Voltage monitor has detected + an error with VBAT supply. */ +#endif /* VBAT_STATUSA_VOLT_DET_MASK */ +#if defined(VBAT_STATUSA_TEMP_DET_MASK) + kVBAT_StatusFlagTemperatureDetect = VBAT_STATUSA_TEMP_DET_MASK, /*!< Temperature monitor has detected an error. */ +#endif /* VBAT_STATUSA_TEMP_DET_MASK */ +#if defined(VBAT_STATUSA_SEC0_DET_MASK) + kVBAT_StatusFlagSec0Detect = VBAT_STATUSA_SEC0_DET_MASK, /*!< Security input 0 has detected an error. */ +#endif /* VBAT_STATUSA_SEC0_DET_MASK */ + kVBAT_StatusFlagInterrupt0Detect = VBAT_STATUSA_IRQ0_DET_MASK, /*!< Interrupt 0 asserted. */ + kVBAT_StatusFlagInterrupt1Detect = VBAT_STATUSA_IRQ1_DET_MASK, /*!< Interrupt 1 asserted. */ + kVBAT_StatusFlagInterrupt2Detect = VBAT_STATUSA_IRQ2_DET_MASK, /*!< Interrupt 2 asserted. */ + kVBAT_StatusFlagInterrupt3Detect = VBAT_STATUSA_IRQ3_DET_MASK, /*!< Interrupt 2 asserted. */ +}; + +/*! + * @brief The enumeration of VBAT interrupt enable. + * + * @anchor vbat_interrupt_enable_t + */ +enum _vbat_interrupt_enable +{ + kVBAT_InterruptEnablePORDetect = VBAT_IRQENA_POR_DET_MASK, /*!< Enable POR detect interrupt. */ + kVBAT_InterruptEnableWakeupPin = VBAT_IRQENA_WAKEUP_FLAG_MASK, /*!< Enable the interrupt when a falling edge is + detected on the wakeup pin. */ + kVBAT_InterruptEnableBandgapTimer0 = VBAT_IRQENA_TIMER0_FLAG_MASK, /*!< Enable the interrupt if Bandgap + Timer0 period reached. */ + kVBAT_InterruptEnableBandgapTimer1 = VBAT_IRQENA_TIMER1_FLAG_MASK, /*!< Enable the interrupt if Bandgap + Timer1 period reached. */ + kVBAT_InterruptEnableLdoReady = VBAT_IRQENA_LDO_RDY_MASK, /*!< Enable LDO ready interrupt. */ + kVBAT_InterruptEnableOsc32kReady = VBAT_IRQENA_OSC_RDY_MASK, /*!< Enable OSC32K ready interrupt. */ +#if defined(VBAT_IRQENA_CLOCK_DET_MASK) + kVBAT_InterruptEnableClockDetect = VBAT_IRQENA_CLOCK_DET_MASK, /*!< Enable clock monitor detect interrupt. */ +#endif /* VBAT_IRQENA_CLOCK_DET_MASK */ + kVBAT_InterruptEnableConfigDetect = + VBAT_IRQENA_CONFIG_DET_MASK, /*!< Enable configuration error detected interrupt. */ +#if defined(VBAT_IRQENA_VOLT_DET_MASK) + kVBAT_InterruptEnableVoltageDetect = VBAT_IRQENA_VOLT_DET_MASK, /*!< Enable voltage monitor detect interrupt. */ +#endif /* VBAT_IRQENA_VOLT_DET_MASK */ +#if defined(VBAT_IRQENA_TEMP_DET_MASK) + kVBAT_InterruptEnableTemperatureDetect = VBAT_IRQENA_TEMP_DET_MASK, /*!< Enable temperature monitor detect + interrupt. */ +#endif /* VBAT_IRQENA_TEMP_DET_MASK */ +#if defined(VBAT_IRQENA_SEC0_DET_MASK) + kVBAT_InterruptEnableSec0Detect = VBAT_IRQENA_SEC0_DET_MASK, /*!< Enable security input 0 detect interrupt. */ +#endif /* VBAT_IRQENA_SEC0_DET_MASK */ + kVBAT_InterruptEnableInterrupt0 = VBAT_IRQENA_IRQ0_DET_MASK, /*!< Enable the interrupt0. */ + kVBAT_InterruptEnableInterrupt1 = VBAT_IRQENA_IRQ1_DET_MASK, /*!< Enable the interrupt1. */ + kVBAT_InterruptEnableInterrupt2 = VBAT_IRQENA_IRQ2_DET_MASK, /*!< Enable the interrupt2. */ + kVBAT_InterruptEnableInterrupt3 = VBAT_IRQENA_IRQ3_DET_MASK, /*!< Enable the interrupt3. */ + + kVBAT_AllInterruptsEnable = + (VBAT_IRQENA_POR_DET_MASK | VBAT_IRQENA_WAKEUP_FLAG_MASK | VBAT_IRQENA_TIMER0_FLAG_MASK | + VBAT_IRQENA_TIMER1_FLAG_MASK | VBAT_IRQENA_LDO_RDY_MASK | VBAT_IRQENA_OSC_RDY_MASK | + VBAT_IRQENA_CONFIG_DET_MASK | VBAT_IRQENA_IRQ0_DET_MASK | VBAT_IRQENA_IRQ1_DET_MASK | + VBAT_IRQENA_IRQ2_DET_MASK | VBAT_IRQENA_IRQ3_DET_MASK), /*!< Enable all interrupts. */ +}; + +/*! + * @brief The enumeration of VBAT wakeup enable. + * + * @anchor vbat_wakeup_enable_t + */ +enum _vbat_wakeup_enable +{ + kVBAT_WakeupEnablePORDetect = VBAT_WAKENA_POR_DET_MASK, /*!< Enable POR detect wakeup. */ + kVBAT_WakeupEnableWakeupPin = VBAT_WAKENA_WAKEUP_FLAG_MASK, /*!< Enable wakeup feature when a falling edge is + detected on the wakeup pin. */ + kVBAT_WakeupEnableBandgapTimer0 = VBAT_WAKENA_TIMER0_FLAG_MASK, /*!< Enable wakeup feature when bandgap + timer0 period reached. */ + kVBAT_WakeupEnableBandgapTimer1 = VBAT_WAKENA_TIMER1_FLAG_MASK, /*!< Enable wakeup feature when bandgap + timer1 period reached. */ + kVBAT_WakeupEnableLdoReady = VBAT_WAKENA_LDO_RDY_MASK, /*!< Enable wakeup when LDO ready. */ + kVBAT_WakeupEnableOsc32kReady = VBAT_WAKENA_OSC_RDY_MASK, /*!< Enable wakeup when OSC32k ready. */ +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + kVBAT_WakeupEnableClockDetect = + VBAT_WAKENA_CLOCK_DET_MASK, /*!< Enable wakeup when clock monitor detect an error. */ +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ + kVBAT_WakeupEnableConfigDetect = VBAT_WAKENA_CONFIG_DET_MASK, /*!< Enable wakeup when + configuration error detected. */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + kVBAT_WakeupEnableVoltageDetect = VBAT_WAKENA_VOLT_DET_MASK, /*!< Enable wakeup when voltage monitor detect an + error. */ +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + kVBAT_WakeupEnableTemperatureDetect = VBAT_WAKENA_TEMP_DET_MASK, /*!< Enable wakeup when temperature monitor + detect an error. */ +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + kVBAT_WakeupEnableSec0Detect = VBAT_WAKENA_SEC0_DET_MASK, /*!< Enable wakeup when security input 0 detect an + error. */ +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ + kVBAT_WakeupEnableInterrupt0 = VBAT_WAKENA_IRQ0_DET_MASK, /*!< Enable wakeup when interrupt0 asserted. */ + kVBAT_WakeupEnableInterrupt1 = VBAT_WAKENA_IRQ1_DET_MASK, /*!< Enable wakeup when interrupt1 asserted. */ + kVBAT_WakeupEnableInterrupt2 = VBAT_WAKENA_IRQ2_DET_MASK, /*!< Enable wakeup when interrupt2 asserted. */ + kVBAT_WakeupEnableInterrupt3 = VBAT_WAKENA_IRQ3_DET_MASK, /*!< Enable wakeup when interrupt3 asserted. */ + + kVBAT_AllWakeupsEnable = (VBAT_WAKENA_POR_DET_MASK | VBAT_WAKENA_WAKEUP_FLAG_MASK | VBAT_WAKENA_TIMER0_FLAG_MASK | + VBAT_WAKENA_TIMER1_FLAG_MASK | VBAT_WAKENA_LDO_RDY_MASK | VBAT_WAKENA_OSC_RDY_MASK | + VBAT_WAKENA_CONFIG_DET_MASK | VBAT_WAKENA_IRQ0_DET_MASK | VBAT_WAKENA_IRQ1_DET_MASK | + VBAT_WAKENA_IRQ2_DET_MASK | VBAT_WAKENA_IRQ3_DET_MASK + +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + | VBAT_WAKENA_CLOCK_DET_MASK + +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + | VBAT_WAKENA_VOLT_DET_MASK + +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + | VBAT_WAKENA_TEMP_DET_MASK + +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + | VBAT_WAKENA_SEC0_DET_MASK + +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ + ), /*!< Enable all wakeup. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The enumeration of VBAT tamper enable. + */ +enum _vbat_tamper_enable +{ + kVBAT_TamperEnablePOR = VBAT_TAMPERA_POR_DET_MASK, /*!< Enable tamper if POR asserted in STATUS register. */ + kVBAT_TamperEnableClockDetect = VBAT_TAMPERA_CLOCK_DET_MASK, /*!< Enable tamper if clock monitor detect an error. */ + kVBAT_TamperEnableConfigDetect = + VBAT_TAMPERA_CONFIG_DET_MASK, /*!< Enable tamper if configuration error detected. */ + kVBAT_TamperEnableVoltageDetect = VBAT_TAMPERA_VOLT_DET_MASK, /*!< Enable tamper if voltage monitor detect an + error. */ + kVBAT_TamperEnableTemperatureDetect = VBAT_TAMPERA_TEMP_DET_MASK, /*!< Enable tamper if temperature monitor + detect an error. */ + kVBAT_TamperEnableSec0Detect = VBAT_TAMPERA_SEC0_DET_MASK, /*!< Enable tamper if security input 0 detect an + error. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * @brief The enumeration of bandgap timer id, VBAT support two bandgap timers. + * + * @anchor vbat_bandgap_timer_id_t + */ +enum _vbat_bandgap_timer_id +{ + kVBAT_BandgapTimer0 = 1U << 0U, /*!< Bandgap Timer0. */ + kVBAT_BandgapTimer1 = 1U << 1U, /*!< Bandgap Timer1. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +/*! + * @brief The enumeration of connections for OSC32K/FRO32K output clock to other modules. + * + * @anchor vbat_clock_enable_t + */ +enum _vbat_clock_enable +{ + kVBAT_EnableClockToDomain0 = 1U << 0U, /*!< Enable clock to power domain0. */ + kVBAT_EnableClockToDomain1 = 1U << 1U, /*!< Enable clock to power domain1. */ + kVBAT_EnableClockToDomain2 = 1U << 2U, /*!< Enable clock to power domain2. */ + kVBAT_EnableClockToDomain3 = 1U << 3U, /*!< Enable clock to power domain3. */ +}; +#define kVBAT_EnableClockToVddBat kVBAT_EnableClockToDomain0 +#define kVBAT_EnableClockToVddSys kVBAT_EnableClockToDomain1 +#define kVBAT_EnableClockToVddWake kVBAT_EnableClockToDomain2 +#define kVBAT_EnableClockToVddMain kVBAT_EnableClockToDomain3 + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * @brief The enumeration of SRAM arrays that controlled by VBAT. + * @anchor vbat_ram_array_t + */ +enum _vbat_ram_array +{ + kVBAT_SramArray0 = 1U << 0U, /*!< Specify SRAM array0 that controlled by VBAT. */ + kVBAT_SramArray1 = 1U << 1U, /*!< Specify SRAM array1 that controlled by VBAT. */ + kVBAT_SramArray2 = 1U << 2U, /*!< Specify SRAM array2 that controlled by VBAT. */ + kVBAT_SramArray3 = 1U << 3U, /*!< Specify SRAM array3 that controlled by VBAT. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ + +/*! + * @brief The enumeration of bandgap refresh period. + */ +typedef enum _vbat_bandgap_refresh_period +{ + kVBAT_BandgapRefresh7P8125ms = 0U, /*!< Bandgap refresh every 7.8125ms. */ + kVBAT_BandgapRefresh15P625ms = 1U, /*!< Bandgap refresh every 15.625ms. */ + kVBAT_BandgapRefresh31P25ms = 2U, /*!< Bandgap refresh every 31.25ms. */ + kVBAT_BandgapRefresh62P5ms = 3U, /*!< Bandgap refresh every 62.5ms. */ +} vbat_bandgap_refresh_period_t; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * @brief The enumeration of bandgap timer0 timeout period. + */ +typedef enum _vbat_bandgap_timer0_timeout_period +{ + kVBAT_BangapTimer0Timeout1s = 0U, /*!< Bandgap timer0 timerout every 1s. */ + kVBAT_BangapTimer0Timeout500ms = 1U, /*!< Bandgap timer0 timerout every 500ms. */ + kVBAT_BangapTimer0Timeout250ms = 2U, /*!< Bandgap timer0 timerout every 250ms. */ + kVBAT_BangapTimer0Timeout125ms = 3U, /*!< Bandgap timer0 timerout every 125ms. */ + kVBAT_BangapTimer0Timeout62P5ms = 4U, /*!< Bandgap timer0 timerout every 62.5ms. */ + kVBAT_BangapTimer0Timeout31P25ms = 5U, /*!< Bandgap timer0 timerout every 31.25ms. */ +} vbat_bandgap_timer0_timeout_period_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * @brief The enumeration of osc32k operate mode, including Bypass mode, low power switched mode and so on. + */ +typedef enum _vbat_osc32k_operate_mode +{ + kVBAT_Osc32kEnabledToTransconductanceMode = 0U, /*!< Set to transconductance mode. */ + kVBAT_Osc32kEnabledToLowPowerBackupMode = 1U, /*!< Set to low power backup mode. */ + kVBAT_Osc32kEnabledToLowPowerSwitchedMode = 2U, /*!< Set to low power switched mode. */ +} vbat_osc32k_operate_mode_t; + +/*! + * @brief The enumeration of OSC32K load capacitance. + */ +typedef enum _vbat_osc32k_load_capacitance_select +{ + kVBAT_Osc32kCrystalLoadCap0pF = + 0U, /*!< Internal capacitance bank is enabled, set the internal capacitance to 0 pF. */ + kVBAT_Osc32kCrystalLoadCap2pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 2 pF. */ + kVBAT_Osc32kCrystalLoadCap4pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 4 pF. */ + kVBAT_Osc32kCrystalLoadCap6pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 6 pF. */ + kVBAT_Osc32kCrystalLoadCap8pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 8 pF. */ + kVBAT_Osc32kCrystalLoadCap10pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 10 pF. */ + kVBAT_Osc32kCrystalLoadCap12pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 12 pF. */ + kVBAT_Osc32kCrystalLoadCap14pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 14 pF. */ + kVBAT_Osc32kCrystalLoadCap16pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 16 pF. */ + kVBAT_Osc32kCrystalLoadCap18pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 18 pF. */ + kVBAT_Osc32kCrystalLoadCap20pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 20 pF. */ + kVBAT_Osc32kCrystalLoadCap22pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 22 pF. */ + kVBAT_Osc32kCrystalLoadCap24pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 24 pF. */ + kVBAT_Osc32kCrystalLoadCap26pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 26 pF. */ + kVBAT_Osc32kCrystalLoadCap28pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 28 pF. */ + kVBAT_Osc32kCrystalLoadCap30pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 30 pF. */ + kVBAT_Osc32kCrystalLoadCapBankDisabled = 0xF0U, /*!< Internal capacitance bank is disabled. */ +} vbat_osc32k_load_capacitance_select_t; + +/*! + * @brief The enumeration of start-up time of the oscillator. + */ +typedef enum _vbat_osc32k_start_up_time +{ + kVBAT_Osc32kStartUpTime8Sec = 0U, /*!< Configure the start-up time as 8 seconds. */ + kVBAT_Osc32kStartUpTime4Sec, /*!< Configure the start-up time as 4 seconds. */ + kVBAT_Osc32kStartUpTime2Sec, /*!< Configure the start-up time as 2 seconds. */ + kVBAT_Osc32kStartUpTime1Sec, /*!< Configure the start-up time as 1 seconds. */ + kVBAT_Osc32kStartUpTime0P5Sec, /*!< Configure the start-up time as 0.5 seconds. */ + kVBAT_Osc32kStartUpTime0P25Sec, /*!< Configure the start-up time as 0.25 seconds. */ + kVBAT_Osc32kStartUpTime0P125Sec, /*!< Configure the start-up time as 0.125 seconds. */ + kVBAT_Osc32kStartUpTime0P5MSec, /*!< Configure the start-up time as 0.5 milliseconds. */ +} vbat_osc32k_start_up_time_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) +/*! + * @brief The enumeration of VBAT module supplies. + */ +typedef enum _vbat_internal_module_supply +{ + kVBAT_ModuleSuppliedByVddBat = 0U, /*!< VDD_BAT supplies VBAT modules. */ + kVBAT_ModuleSuppliedByVddSys = 1U, /*!< VDD_SYS supplies VBAT modules. */ +} vbat_internal_module_supply_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The enumeration of VBAT clock monitor divide trim value + */ +typedef enum _vbat_clock_monitor_divide_trim +{ + kVBAT_ClockMonitorOperateAt1kHz = 0U, /*!< Clock monitor operates at 1 kHz. */ + kVBAT_ClockMonitorOperateAt64Hz = 1U, /*!< Clock monitor operates at 64 Hz. */ +} vbat_clock_monitor_divide_trim_t; + +/*! + * @brief The enumeration of VBAT clock monitor frequency trim value used to adjust the clock monitor assert. + */ +typedef enum _vbat_clock_monitor_freq_trim +{ + kVBAT_ClockMonitorAssert2Cycle = 0U, /*!< Clock monitor assert 2 cycles after expected edge. */ + kVBAT_ClockMonitorAssert4Cycle = 1U, /*!< Clock monitor assert 4 cycles after expected edge. */ + kVBAT_ClockMonitorAssert6Cycle = 2U, /*!< Clock monitor assert 8 cycles after expected edge. */ + kVBAT_ClockMonitorAssert8Cycle = 3U, /*!< Clock monitor assert 8 cycles after expected edge. */ +} vbat_clock_monitor_freq_trim_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +/*! + * @brief The structure of internal 16kHz free running oscillator attributes. + */ +typedef struct _vbat_fro16k_config +{ + bool enableFRO16k; /*!< Enable/disable internal 16kHz free running oscillator. */ + uint8_t enabledConnectionsMask; /*!< The mask of connected modules to enable FRO16k clock output. */ +} vbat_fro16k_config_t; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The structure of internal clock monitor, including divide trim and frequency trim. + */ +typedef struct _vbat_clock_monitor_config +{ + vbat_clock_monitor_divide_trim_t divideTrim : 1U; /* !< Divide trim value, please + refer to @ref vbat_clock_monitor_divide_trim_t */ + vbat_clock_monitor_freq_trim_t freqTrim : 2U; /*!< Frequency trim value used to adjust the clock monitor + assert, please refer to @ref vbat_clock_monitor_freq_trim_t. */ + bool lock : 1U; /*!< Lock the clock monitor control after enabled. */ +} vbat_clock_monitor_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The structure of Tamper configuration. + */ +typedef struct _vbat_tamper_config +{ + bool enableVoltageDetect : 1U; /*!< Enable/disable voltage detection. */ + bool enableTemperatureDetect : 1U; /*!< Enable/disable temperature detection. */ + bool lock : 1U; /*!< Lock the tamper control after enabled. */ +} vbat_tamper_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FRO16K Control Interfaces + * @{ + */ + +/*! + * @brief Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_fro16k_config_t structure. + */ +void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config); + +/*! + * @brief Enable/disable internal 16kHz free running oscillator. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable 16kHz FRO. + * - \b true Enable internal 16kHz free running oscillator. + * - \b false Disable internal 16kHz free running oscillator. + */ +static inline void VBAT_EnableFRO16k(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) + base->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ + } + else + { + base->FROCTLA &= ~VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) + base->FROCTLB |= VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ + } +} + +/*! + * @brief Check if internal 16kHz free running oscillator is enabled. + * + * @param base VBAT peripheral base address. + * + * @retval true The internal 16kHz Free running oscillator is enabled. + * @retval false The internal 16kHz Free running oscillator is enabled. + */ +static inline bool VBAT_CheckFRO16kEnabled(VBAT_Type *base) +{ + return (bool)((base->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) == VBAT_FROCTLA_FRO_EN_MASK); +} + +/*! + * @brief Enable FRO16kHz output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The mask of modules that FRO16k is connected, should be the OR'ed + * value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_UngateFRO16k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->FROCLKE |= VBAT_FROCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Disable FRO16kHz output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_GateFRO16k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->FROCLKE &= ~VBAT_FROCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Lock settings of internal 16kHz free running oscillator, please note that if locked 16kHz FRO's settings can + * not be updated until the next POR. + * + * @note Please note that the operation to ungate/gate FRO 16kHz output clock can not be locked by this function. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockFRO16kSettings(VBAT_Type *base) +{ + base->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; +#if (defined(VBAT_FROLCKB_LOCK_MASK)) + base->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK; +#endif /* VBAT_FROLCKB_LOCK_MASK */ +} + +/*! + * @brief Check if FRO16K settings are locked. + * + * @param base VBAT peripheral base address. + * + * @return @c true in case of FRO16k settings are locked, @c false in case of FRO16k settings are not locked. + */ +static inline bool VBAT_CheckFRO16kSettingsLocked(VBAT_Type *base) +{ + return ((base->FROLCKA & VBAT_FROLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * @name OSC32K Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable 32K Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable 32k Crystal Oscillator: + * - \b true Enable crystal oscillator and polling status register to check clock is ready. + * - \b false Disable crystal oscillator. + */ +static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->OSCCTLA |= VBAT_OSCCTLA_OSC_EN_MASK; + base->OSCCTLB &= ~VBAT_OSCCTLA_OSC_EN_MASK; + + /* Polling status register to check clock is ready. */ + while ((base->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0UL) + ; + } + else + { + base->OSCCTLA &= ~VBAT_OSCCTLA_OSC_EN_MASK; + base->OSCCTLB |= VBAT_OSCCTLA_OSC_EN_MASK; + } +} + +/*! + * @brief Bypass 32k crystal oscillator, the clock is still output by oscillator but this clock is the same as clock + * provided on EXTAL pin. + * + * @note In bypass mode, oscillator must be enabled; To exit bypass mode, oscillator must be disabled. + * + * @param base VBAT peripheral base address. + * @param enableBypass Used to enter/exit bypass mode: + * - \b true Enter into bypass mode; + * - \b false Exit bypass mode. + */ +static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass) +{ + if (enableBypass) + { + base->OSCCTLA |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + base->OSCCTLB &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + } + else + { + base->OSCCTLA &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + base->OSCCTLB |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + } +} + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) +/*! + * @brief Adjust 32k crystal oscillator amplifier gain. + * + * @param base VBAT peripheral base address. + * @param coarse Specify amplifier coarse trim value. + * @param fine Specify amplifier fine trim value. + */ +static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse, uint8_t fine) +{ + base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) | + (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(fine))); + base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) | + (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(~fine))); +} +#else +/*! + * @brief Adjust 32k crystal oscillator amplifier gain. + * + * @param base VBAT peripheral base address. + * @param coarse Specify amplifier coarse trim value. + */ +static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse) +{ + base->OSCCTLA = (base->OSCCTLA & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse)); + base->OSCCTLB = (base->OSCCTLB & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse)); +} + +#endif /* */ + +/*! + * @brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. + * + * @param base VBAT peripheral base address. + * @param operateMode Specify the crystal oscillator mode, please refer to @ref vbat_osc32k_operate_mode_t. + * @param xtalCap Specify the internal capacitance for the XTAL pin from the capacitor bank. + * @param extalCap Specify the internal capacitance for the EXTAL pin from the capacitor bank. + * + * @retval kStatus_VBAT_WrongCapacitanceValue The load capacitance value to set is not align with operate mode's + * requirements. + * @retval kStatus_Success Success to set operate mode and load capacitance. + */ +status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, + vbat_osc32k_operate_mode_t operateMode, + vbat_osc32k_load_capacitance_select_t xtalCap, + vbat_osc32k_load_capacitance_select_t extalCap); + +/*! + * @brief Trim 32k crystal oscillator startup time. + * + * @param base VBAT peripheral base address. + * @param startupTime Specify the startup time of the oscillator. + */ +static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime) +{ + base->OSCCFGA = ((base->OSCCFGA & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(startupTime)); + base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~((uint32_t)startupTime))); +} + +/*! + * @brief Set crystal oscillator comparator trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param comparatorTrimValue Comparator trim value, ranges from 0 to 7. + */ +static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(comparatorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~((uint32_t)comparatorTrimValue))); +} + +/*! + * @brief Set crystal oscillator delay trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param delayTrimValue Delay trim value, ranges from 0 to 15. + */ +static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(delayTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~((uint32_t)delayTrimValue))); +} + +/*! + * @brief Set crystal oscillator capacitor trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param capacitorTrimValue Capacitor value to trim, ranges from 0 to 3. + */ +static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(capacitorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~((uint32_t)capacitorTrimValue))); +} + +/*! + * @brief Lock Osc32k settings, after locked all writes to the Oscillator registers are blocked. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LookOsc32kSettings(VBAT_Type *base) +{ + base->OSCLCKA |= VBAT_OSCLCKA_LOCK_MASK; + base->OSCLCKB &= ~VBAT_OSCLCKB_LOCK_MASK; +} + +/*! + * @brief Unlock Osc32k settings. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockOsc32kSettings(VBAT_Type *base) +{ + base->OSCLCKA &= ~VBAT_OSCLCKA_LOCK_MASK; + base->OSCLCKB |= VBAT_OSCLCKB_LOCK_MASK; +} + +/*! + * @brief Check if osc32k settings are locked. + * + * @param base VBAT peripheral base address. + * @return \c true in case of osc32k settings are locked, \c false in case of osc32k settings are not locked. + */ +static inline bool VBAT_CheckOsc32kSettingsLocked(VBAT_Type *base) +{ + return ((base->OSCLCKA & VBAT_OSCLCKA_LOCK_MASK) != 0UL); +} + +/*! + * @brief Enable OSC32k output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_UngateOsc32k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->OSCCLKE |= VBAT_OSCCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Disable OSC32k output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_GateOsc32k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->OSCCLKE &= ~VBAT_OSCCLKE_CLKE(connectionsMask); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * @name RAM_LDO Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable Bandgap. + * + * @note The FRO16K must be enabled before enabling the bandgap. + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable bandgap. + * - \b true Enable the bandgap. + * - \b false Disable the bandgap. + * + * @retval kStatus_Success Success to enable/disable the bandgap. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable the bandgap due to FRO16k is not enabled previously. + */ +status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable); + +/*! + * @brief Check if bandgap is enabled. + * + * @param base VBAT peripheral base address. + * + * @retval true The bandgap is enabled. + * @retval false The bandgap is disabled. + */ +static inline bool VBAT_CheckBandgapEnabled(VBAT_Type *base) +{ + return (bool)((base->LDOCTLA & VBAT_LDOCTLA_BG_EN_MASK) == VBAT_LDOCTLA_BG_EN_MASK); +} + +/*! + * @brief Enable/disable bandgap low power refresh mode. + * + * @note For lowest power consumption, refresh mode must be enabled. + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enableRefreshMode Used to enable/disable bandgap low power refresh mode. + * - \b true Enable bandgap low power refresh mode. + * - \b false Disable bandgap low power refresh mode. + */ +static inline void VBAT_EnableBandgapRefreshMode(VBAT_Type *base, bool enableRefreshMode) +{ + if (enableRefreshMode) + { + base->LDOCTLA |= VBAT_LDOCTLA_REFRESH_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_REFRESH_EN_MASK; + } +} + +/*! + * @brief Enable/disable Backup RAM Regulator(RAM_LDO). + * + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable RAM_LDO. + * - \b true Enable backup SRAM regulator. + * - \b false Disable backup SRAM regulator. + * + * @retval kStatusSuccess Success to enable/disable backup SRAM regulator. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable backup SRAM regulator due to FRO16k is not enabled previously. + * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable backup SRAM regulator due to the bandgap is not enabled + * previously. + */ +status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable); + +/*! + * @brief Lock settings of RAM_LDO, please note that if locked then RAM_LDO's settings + * can not be updated until the next POR. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockRamLdoSettings(VBAT_Type *base) +{ + base->LDOLCKA |= VBAT_LDOLCKA_LOCK_MASK; + base->LDOLCKB &= ~VBAT_LDOLCKA_LOCK_MASK; +} + +/*! + * @brief Check if RAM_LDO settings is locked. + * + * @param base VBAT peripheral base address. + * @return @c true in case of RAM_LDO settings are locked, @c false in case of RAM_LDO settings are unlocked. + */ +static inline bool VBAT_CheckRamLdoSettingsLocked(VBAT_Type *base) +{ + return ((base->LDOLCKA & VBAT_LDOLCKA_LOCK_MASK) != 0UL); +} + +/*! + * @brief Switch the SRAM to be powered by LDO_RAM. + * + * @note This function can be used to switch the SRAM to the VBAT retention supply at any time, but please note that the + * SRAM must not be accessed during this time. + * @note Invoke this function to switch power supply before switching off external power. + * @note RAM_LDO must be enabled before invoking this function. + * @note To access the SRAM arrays retained by the LDO_RAM, please invoke VBAT_SwitchSRAMPowerBySocSupply(), after + * external power is switched back on. + * + * @param base VBAT peripheral base address. + * + * @retval kStatusSuccess Success to Switch SRAM powered by VBAT. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously. + */ +status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base); + +/*! + * @brief Switch the RAM to be powered by Soc Supply in software mode. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base) +{ + base->LDORAMC &= ~VBAT_LDORAMC_SWI_MASK; + base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK; +} + +/*! + * @brief Power off selected SRAM array in low power modes. + * + * @param base VBAT peripheral base address. + * @param sramMask The mask of SRAM array to power off, should be the OR'ed value of @ref vbat_ram_array_t. + */ +static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) +{ + base->LDORAMC |= (uint32_t)VBAT_LDORAMC_RET(sramMask); +} + +/*! + * @brief Retain selected SRAM array in low power modes. + * + * @param base VBAT peripheral base address. + * @param sramMask The mask of SRAM array to retain, should be the OR'ed value of @ref vbat_ram_array_t. + */ +static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) +{ + base->LDORAMC &= ~(uint32_t)VBAT_LDORAMC_RET(sramMask); +} + +/*! + * @brief Enable/disable SRAM isolation. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable SRAM violation. + * - \b true SRAM will be isolated. + * - \b false SRAM state follows the SoC power modes. + */ +static inline void VBAT_EnableSRAMIsolation(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->LDORAMC |= VBAT_LDORAMC_ISO_MASK; + } + else + { + base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK; + } +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_RAM_LDO */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! @name Bandgap Timer Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable Bandgap timer. + * + * @note The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable bandgap timer. + * @param timerIdMask The mask of bandgap timer Id, should be the OR'ed value of @ref vbat_bandgap_timer_id_t. + * + * @retval kStatus_Success Success to enable/disable selected bandgap timer. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable/disable selected bandgap timer due to FRO16k not enabled + * previously. + * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable/disable selected bandgap timer due to bandgap not enabled + * previously. + */ +status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask); + +/*! + * @brief Set bandgap timer0 timeout value. + * + * @note The timeout value can only be changed when the timer is disabled. + * + * @param base VBAT peripheral base address. + * @param timeoutPeriod Bandgap timer timeout value, please refer to @ref vbat_bandgap_timer0_timeout_period_t. + */ +void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod); + +/*! + * @brief Set bandgap timer1 timeout value. + * + * @note The timeout value can only be changed when the timer is disabled. + * + * @param base VBAT peripheral base address. + * @param timeoutPeriod The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s. + */ +void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod); + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) +/*! @name Switch Control Interfaces + * @{ + */ + +/*! + * @brief Control the VBAT internal switch in active mode, VBAT modules can be suppiled by VDD_BAT and VDD_SYS. + * + * @param base VBAT peripheral base address. + * @param supply Used to control the VBAT internal switch. + */ +static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_internal_module_supply_t supply) +{ + if (supply == kVBAT_ModuleSuppliedByVddBat) + { + base->SWICTLA &= ~VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB |= VBAT_SWICTLA_SWI_EN_MASK; + } + else + { + base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK; + } +} + +/*! + * @brief Get VBAT module supply in active mode. + * + * @param base VBAT peripheral base address. + * @return VDD_SYS supplies VBAT modules or VDD_BAT supplies VBAT modules, in type of @ref + * vbat_internal_module_supply_t. + */ +static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base) +{ + return (vbat_internal_module_supply_t)(base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK); +} + +/*! + * @brief Control the VBAT internal switch in low power modes. + * + * @note If VBAT modules are supplied by VDD_SYS in low power modes, VBAT module will also supplied by VDD_SYS in active + * mode. + * + * @param base VBAT peripheral base address. + * @param supply Used to specify which voltage input supply VBAT modules in low power mode. + */ +static inline void VBAT_SwitchVBATModuleSupplyLowPowerMode(VBAT_Type *base, vbat_internal_module_supply_t supply) +{ + if (supply == kVBAT_ModuleSuppliedByVddBat) + { + base->SWICTLA &= ~VBAT_SWICTLA_LP_EN_MASK; + base->SWICTLB |= VBAT_SWICTLA_LP_EN_MASK; + } + else + { + base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLA |= VBAT_SWICTLA_LP_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_LP_EN_MASK; + } +} + +/*! + * @brief Lock switch control, if locked all writes to the switch registers will be blocked. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockSwitchControl(VBAT_Type *base) +{ + base->SWILCKA |= VBAT_SWILCKA_LOCK_MASK; + base->SWILCKB &= ~VBAT_SWILCKB_LOCK_MASK; +} + +/*! + * @brief Unlock switch control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockSwitchControl(VBAT_Type *base) +{ + base->SWILCKA &= ~VBAT_SWILCKA_LOCK_MASK; + base->SWILCKB |= VBAT_SWILCKB_LOCK_MASK; +} + +/*! + * @brief Check if switch control is locked. + * + * @param base VBAT peripheral base address. + * + * @retval false switch control is not locked. + * @retval true switch control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckSwitchControlLocked(VBAT_Type *base) +{ + return ((base->SWILCKA & VBAT_SWILCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @name Clock Monitor Interfaces + * @{ + */ + +/*! + * @brief Initialize the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * @note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_clock_monitor_config_t structure. + * + * @retval kStatus_Success Clock monitor is initialized successfully. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * @retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * @retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config); + +/*! + * @brief Deinitialize the VBAT clock monitor. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Clock monitor is de-initialized successfully. + * @retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base); + +/*! + * @brief Enable/disable clock monitor. + * + * @param base VBAT peripheral base address. + * @param enable Switcher to enable/disable clock monitor: + * - true: enable clock monitor; + * - false: disable clock monitor. + */ +static inline void VBAT_EnableClockMonitor(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->MONCTLA |= VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB &= ~VBAT_MONCTLA_MON_EN_MASK; + } + else + { + base->MONCTLA &= ~VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB |= VBAT_MONCTLA_MON_EN_MASK; + } +} + +/*! + * @brief Set clock monitor's divide trim, avaiable value is #kVBAT_ClockMonitorOperateAt1kHz and + * #kVBAT_ClockMonitorOperateAt64Hz + * + * @param base VBAT peripheral base address. + * @param divideTrim Specify divide trim value, please refer to @ref vbat_clock_monitor_divide_trim_t. + */ +static inline void VBAT_SetClockMonitorDivideTrim(VBAT_Type *base, vbat_clock_monitor_divide_trim_t divideTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(divideTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(~divideTrim); +} + +/*! + * @brief Set clock monitor's frequency trim, avaiable value is #kVBAT_ClockMonitorAssert2Cycle, + * #kVBAT_ClockMonitorAssert4Cycle, #kVBAT_ClockMonitorAssert6Cycle and #kVBAT_ClockMonitorAssert8Cycle. + * + * @param base VBAT peripheral base address. + * @param freqTrim Specify frequency trim value, please refer to @ref vbat_clock_monitor_freq_trim_t. + */ +static inline void VBAT_SetClockMonitorFrequencyTrim(VBAT_Type *base, vbat_clock_monitor_freq_trim_t freqTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(freqTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(~freqTrim); +} + +/*! + * @brief Lock clock monitor enable/disable control. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA |= VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB &= ~VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock clock monitor enable/disable control. + * + * @param base VBTA peripheral base address. + */ +static inline void VBAT_UnlockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA &= ~VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB |= VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Check if clock monitor enable/disable control is locked. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + * + * @retval false clock monitor enable/disable control is not locked. + * @retval true clock monitor enable/disable control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckClockMonitorControlLocked(VBAT_Type *base) +{ + return ((base->MONLCKA & VBAT_MONLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_CLOCK_MONITOR */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! @name Tamper Control Interfaces + * + */ + +/*! + * @brief Initialize tamper control. + * + * @note Both FRO16K and bandgap should be enabled before calling this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_tamper_config_t structure. + * + * @retval kStatus_Success Tamper is initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + * @retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config); + +/*! + * @brief De-initialize tamper control. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Tamper is de-initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base); + +/*! + * @brief Enable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be enabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_EnableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA |= tamperEnableMask; + base->TAMPERB &= ~tamperEnableMask; +} + +/*! + * @brief Disable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be disabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_DisableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA &= ~tamperEnableMask; + base->TAMPERB |= tamperEnableMask; +} + +/*! + * @brief Get tamper enable information. + * + * @param base VBAT peripheral base address. + * + * @return Mask of tamper enable information, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline uint32_t VBAT_GetTamperEnableInfo(VBAT_Type *base) +{ + return base->TAMPERA; +} + +/*! + * @brief Lock tamper control, if locked, it is not allowed to change tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA |= VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB &= ~VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA &= ~VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB |= VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Check if tamper control is locked. + * + * @param base VBAT peripheral base address. + * + * @retval false Tamper control is not locked. + * @retval true Tamper control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckTamperControlLocked(VBAT_Type *base) +{ + return ((base->TAMLCKA & VBAT_TAMLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_TAMPER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) +/*! @name Status, Interrupt, Wakeup Control Interfaces + * @{ + */ + +/*! + * @brief Get VBAT status flags + * + * @param base VBAT peripheral base address. + * @return The asserted status flags, should be the OR'ed value of @ref vbat_status_flag_t. + */ +static inline uint32_t VBAT_GetStatusFlags(VBAT_Type *base) +{ + return (uint32_t)(base->STATUSA); +} + +/*! + * @brief Clear VBAT status flags. + * + * @param base VBAT peripheral base address. + * @param mask The mask of status flags to be cleared, should be the OR'ed value of @ref vbat_status_flag_t except + * @ref kVBAT_StatusFlagLdoReady, @ref kVBAT_StatusFlagOsc32kReady, @ref kVBAT_StatusFlagInterrupt0Detect, + * @ref kVBAT_StatusFlagInterrupt1Detect, @ref kVBAT_StatusFlagInterrupt2Detect, + * @ref kVBAT_StatusFlagInterrupt3Detect. + */ +static inline void VBAT_ClearStatusFlags(VBAT_Type *base, uint32_t mask) +{ + base->STATUSA = mask; + base->STATUSB = ~mask; +} + +/*! + * @brief Enable interrupts for the VBAT module, such as POR detect interrupt, Wakeup Pin interrupt and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of interrupts to be enabled, should be the OR'ed value of @ref vbat_interrupt_enable_t. + */ +static inline void VBAT_EnableInterrupts(VBAT_Type *base, uint32_t mask) +{ + base->IRQENA |= mask; + base->IRQENB &= (uint32_t)~mask; +} + +/*! + * @brief Disable interrupts for the VBAT module, such as POR detect interrupt, wakeup pin interrupt and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of interrupts to be disabled, should be the OR'ed value of @ref vbat_interrupt_enable_t. + */ +static inline void VBAT_DisableInterrupts(VBAT_Type *base, uint32_t mask) +{ + base->IRQENA &= ~mask; + base->IRQENB |= mask; +} + +/*! + * @brief Enable wakeup for the VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t. + */ +static inline void VBAT_EnableWakeup(VBAT_Type *base, uint32_t mask) +{ + base->WAKENA |= mask; + base->WAKENB &= ~mask; +} + +/*! + * @brief Disable wakeup for VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t. + */ +static inline void VBAT_DisableWakeup(VBAT_Type *base, uint32_t mask) +{ + base->WAKENA &= ~mask; + base->WAKENB |= mask; +} + +/*! + * @brief Lock VBAT interrupt and wakeup settings, please note that if locked the interrupt and wakeup settings can not + * be updated until the next POR. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockInterruptWakeupSettings(VBAT_Type *base) +{ + base->LOCKA |= VBAT_LOCKA_LOCK_MASK; +} + +/*! + * @brief Set the default state of the WAKEUP_b pin output when no enabled wakeup source is asserted. + * + * @param base VBAT peripheral base address. + * @param assert Used to set default state of the WAKEUP_b pin output: + * - \b true WAKEUP_b output state is logic one; + * - \b false WAKEUP_b output state is logic zero. + */ +static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert) +{ + if (assert) + { + base->WAKECFG |= VBAT_WAKECFG_OUT_MASK; + } + else + { + base->WAKECFG &= ~VBAT_WAKECFG_OUT_MASK; + } +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_VBAT_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vref.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vref.c new file mode 100644 index 0000000000..fd8ee68ae2 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vref.c @@ -0,0 +1,308 @@ +/* + * Copyright 2019-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_vref.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.vref_1" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base VREF peripheral base address + * + * @return The VREF instance + */ +static uint32_t VREF_GetInstance(VREF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to VREF bases for each instance. */ +static VREF_Type *const s_vrefBases[] = VREF_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to VREF clocks for each instance. */ +static const clock_ip_name_t s_vrefClocks[] = VREF_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t VREF_GetInstance(VREF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_vrefBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_vrefBases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_vrefBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (s_vrefBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_vrefBases)); + + return instance; +} + +/*! + * brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all other VREF driver functions, read/write registers, and + * configurations with user-defined settings. The example below shows how to set up vref_config_t parameters + * and how to call the VREF_Init function by passing in these parameters. + * code + * vref_config_t vrefConfig; + * VREF_GetDefaultConfig(VREF, &vrefConfig); + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * VREF_Init(VREF, &vrefConfig); + * endcode + * + * param base VREF peripheral address. + * param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate clock for VREF */ + CLOCK_EnableClock(s_vrefClocks[VREF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CSR |= VREF_CSR_LPBGEN_MASK; + /* After enabling low power bandgap, delay 20 us. */ + SDK_DelayAtLeastUs(20U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Provides bias current for other peripherals. */ + if (config->enableLowPowerBuff) + { + base->CSR |= VREF_CSR_LPBG_BUF_EN_MASK; + } + + if (config->bufferMode != kVREF_ModeBandgapOnly) + { + if (config->enableHCBandgap) + { + tmp32 |= VREF_CSR_HCBGEN_MASK; + } + + if (config->enableInternalVoltageRegulator) + { + tmp32 |= VREF_CSR_REGEN_MASK; + } + + if (config->enableChopOscillator) + { + tmp32 |= (VREF_CSR_REGEN_MASK | VREF_CSR_CHOPEN_MASK); + } + + if (config->enableCurvatureCompensation) + { + tmp32 |= VREF_CSR_ICOMPEN_MASK; + } + + if (config->bufferMode == kVREF_ModeLowPowerBuffer) + { + tmp32 |= VREF_CSR_BUF21EN_MASK; + } + else + { + tmp32 |= (VREF_CSR_BUF21EN_MASK | VREF_CSR_HI_PWR_LV_MASK); + } + + base->CSR |= tmp32; + /* After enabling high accurancy bandgap, delay 400 us. */ + SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } +} + +/*! + * brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * This is an example. + * code + * vref_config_t vrefUserConfig; + * VREF_GetDefaultConfig(VREF, &vrefUserConfig); + * VREF_Init(VREF, &vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * endcode + * + * param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock for VREF */ + CLOCK_DisableClock(s_vrefClocks[VREF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to default values. + * This is an example. + * code + * config->bufferMode = kVREF_ModeHighPowerBuffer; + * config->enableInternalVoltageRegulator = true; + * config->enableChopOscillator = true; + * config->enableHCBandgap = true; + * config->enableCurvatureCompensation = true; + * config->enableLowPowerBuff = true; + * endcode + * + * param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->bufferMode = kVREF_ModeHighPowerBuffer; + config->enableInternalVoltageRegulator = true; + config->enableChopOscillator = true; + config->enableHCBandgap = true; + config->enableCurvatureCompensation = true; + config->enableLowPowerBuff = true; +} + +/*! + * brief Sets a TRIM value for the accurate 1.0V bandgap output. + * + * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step. + * + * param base VREF peripheral address. + * param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue) +{ + uint32_t tmp32 = base->UTRIM; + + tmp32 &= (~VREF_UTRIM_VREFTRIM_MASK); + tmp32 |= VREF_UTRIM_VREFTRIM(trimValue); + + base->UTRIM = tmp32; + + if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) + { + /* After enabling high accurancy bandgap, delay 400 us. */ + SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + else + { + /*Wait internal HC voltage reference stable*/ + /* + * $Branch Coverage Justification$ + * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible, + * the internal HC voltage stable state is too short not to catch. + */ + while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) + { + } + } +} + +/*! + * brief Sets a TRIM value for the accurate buffered VREF output. + * + * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21 + * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V. + * + * note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the + * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. + * + * param base VREF peripheral address. + * param trim21Value Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). + */ +void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value) +{ + uint32_t tmp32 = base->UTRIM; + + tmp32 &= (~VREF_UTRIM_TRIM2V1_MASK); + tmp32 |= VREF_UTRIM_TRIM2V1(trim21Value); + + base->UTRIM = tmp32; + + if (VREF_CSR_CHOPEN_MASK == (base->CSR & VREF_CSR_CHOPEN_MASK)) + { + /* After enabling high accurancy bandgap, delay 400 us. */ + SDK_DelayAtLeastUs(400U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + else + { + /*Wait internal HC voltage reference stable*/ + /* + * $Branch Coverage Justification$ + * while ((base->CSR & VREF_CSR_VREFST_MASK) != 0U) not covered. Test unfeasible, + * the internal HC voltage stable state is too short not to catch. + */ + while ((base->CSR & VREF_CSR_VREFST_MASK) == 0U) + { + } + } +} + +/*! + * brief Reads the VREF trim value. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) + * + * param base VREF peripheral address. + * return 6-bit value of trim setting. + */ +uint8_t VREF_GetVrefTrimVal(VREF_Type *base) +{ + uint8_t trimValue; + + trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_VREFTRIM_MASK) >> VREF_UTRIM_VREFTRIM_SHIFT); + + return trimValue; +} + +/*! + * brief Reads the VREF 2.1V trim value. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), + * + * param base VREF peripheral address. + * return 4-bit value of trim setting. + */ +uint8_t VREF_GetTrim21Val(VREF_Type *base) +{ + uint8_t trimValue; + + trimValue = (uint8_t)((base->UTRIM & VREF_UTRIM_TRIM2V1_MASK) >> VREF_UTRIM_TRIM2V1_SHIFT); + + return trimValue; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vref.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vref.h new file mode 100644 index 0000000000..99689610c4 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_vref.h @@ -0,0 +1,172 @@ +/* + * Copyright 2019-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_VREF_H_ +#define FSL_VREF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup vref + * @{ + */ + +/****************************************************************************** + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_VREF_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2. */ +/*@}*/ + +/*! @brief VREF buffer modes. */ +typedef enum _vref_buffer_mode +{ + kVREF_ModeBandgapOnly = 0U, /*!< Bandgap enabled/standby. */ + kVREF_ModeLowPowerBuffer = 1U, /*!< Low-power buffer mode enabled */ + kVREF_ModeHighPowerBuffer = 2U, /*!< High-power buffer mode enabled */ +} vref_buffer_mode_t; + +/*! @brief The description structure for the VREF module. */ +typedef struct _vref_config +{ + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection */ + bool enableInternalVoltageRegulator; /*!< Provide additional supply noise rejection. */ + bool enableChopOscillator; /*!< Enable Chop oscillator.*/ + bool enableHCBandgap; /*!< Enable High-Accurate bandgap.*/ + bool enableCurvatureCompensation; /*!< Enable second order curvature compensation. */ + bool enableLowPowerBuff; /*!< Provides bias current for other peripherals.*/ + +} vref_config_t; + +/****************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Enables the clock gate and configures the VREF module according to the configuration structure. + * + * This function must be called before calling all other VREF driver functions, read/write registers, and + * configurations with user-defined settings. The example below shows how to set up vref_config_t parameters + * and how to call the VREF_Init function by passing in these parameters. + * @code + * vref_config_t vrefConfig; + * VREF_GetDefaultConfig(VREF, &vrefConfig); + * vrefConfig.bufferMode = kVREF_ModeHighPowerBuffer; + * VREF_Init(VREF, &vrefConfig); + * @endcode + * + * @param base VREF peripheral address. + * @param config Pointer to the configuration structure. + */ +void VREF_Init(VREF_Type *base, const vref_config_t *config); + +/*! + * @brief Stops and disables the clock for the VREF module. + * + * This function should be called to shut down the module. + * This is an example. + * @code + * vref_config_t vrefUserConfig; + * VREF_GetDefaultConfig(VREF, &vrefUserConfig); + * VREF_Init(VREF, &vrefUserConfig); + * ... + * VREF_Deinit(VREF); + * @endcode + * + * @param base VREF peripheral address. + */ +void VREF_Deinit(VREF_Type *base); + +/*! + * @brief Initializes the VREF configuration structure. + * + * This function initializes the VREF configuration structure to default values. + * This is an example. + * @code + * config->bufferMode = kVREF_ModeHighPowerBuffer; + * config->enableInternalVoltageRegulator = true; + * config->enableChopOscillator = true; + * config->enableHCBandgap = true; + * config->enableCurvatureCompensation = true; + * config->enableLowPowerBuff = true; + * @endcode + * + * @param config Pointer to the initialization structure. + */ +void VREF_GetDefaultConfig(vref_config_t *config); + +/* @} */ + +/*! + * @name Trim functions + * @{ + */ + +/*! + * @brief Sets a TRIM value for the accurate 1.0V bandgap output. + * + * This function sets a TRIM value for the reference voltage. It will trim the accurate 1.0V bandgap by 0.5mV each step. + * + * @param base VREF peripheral address. + * @param trimValue Value of the trim register to set the output reference voltage (maximum 0x3F (6-bit)). + */ +void VREF_SetVrefTrimVal(VREF_Type *base, uint8_t trimValue); + +/*! + * @brief Sets a TRIM value for the accurate buffered VREF output. + * + * This function sets a TRIM value for the reference voltage. If buffer mode be set to other values (Buf21 + * enabled), it will trim the VREF_OUT by 0.1V each step from 1.0V to 2.1V. + * + * @note When Buf21 is enabled, the value of UTRIM[TRIM2V1] should be ranged from 0b0000 to 0b1011 in order to trim the + * output voltage from 1.0V to 2.1V, other values will make the VREF_OUT to default value, 1.0V. + * + * @param base VREF peripheral address. + * @param trim21Value Value of the trim register to set the output reference voltage (maximum 0xF (4-bit)). + */ +void VREF_SetTrim21Val(VREF_Type *base, uint8_t trim21Value); + +/*! + * @brief Reads the trim value. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[VREFTRIM] (13:8) + * + * @param base VREF peripheral address. + * @return 6-bit value of trim setting. + */ +uint8_t VREF_GetVrefTrimVal(VREF_Type *base); + +/*! + * @brief Reads the VREF 2.1V trim value. + * + * This function gets the TRIM value from the UTRIM register. It reads UTRIM[TRIM2V1] (3:0), + * + * @param base VREF peripheral address. + * @return 4-bit value of trim setting. + */ +uint8_t VREF_GetTrim21Val(VREF_Type *base); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* FSL_VREF_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wuu.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wuu.c new file mode 100644 index 0000000000..453907ba43 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wuu.c @@ -0,0 +1,292 @@ +/* + * Copyright 2019-2023 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wuu.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wuu" +#endif + +#define WUU_PE_REG_BIT_FIELD_MASK 0x03UL +#define WUU_PDC_REG_BIT_FIELD_MASK 0x03UL +#define WUU_PMC_REG_BIT_FIELD_MASK 0x01UL + +#define WUU_ME_REG_WUME_FIELD_MASK 0x01UL +#define WUU_DE_REG_WUME_FIELD_MASK 0x01UL + +#define WUU_FILT_REG_FILTE_FIELD_MASK 0x60U +#define WUU_FILT_REG_FILTSET_FIELD_MASK 0x1FU +#define WUU_FDC_REG_FILTC_FIELD_MASK 0x3U +#define WUU_FMC_REG_FILTM_FIELD_MASK 0x1U + +#define WUU_FILT_REG_FILTSET_FIELD(x) (((uint32_t)(x) << 5UL) & WUU_FILT_REG_FILTE_FIELD_MASK) +#define WUU_CLEAR_BIT_FIELD_IN_REG(mask, offset) (~((uint32_t)(mask) << (offset))) +#define WUU_SET_BIT_FIELD_IN_REG(val, offset) ((uint32_t)(val) << (offset)) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Enables and Configs External WakeUp Pins. + * + * This function enables/disables the external pin as wakeup input. What's more this + * function configs pins options, including edge detection wakeup event and operate mode. + * + * param base MUU peripheral base address. + * param pinIndex The index of the external input pin. See Reference Manual for the details. + * param config Pointer to wuu_external_wakeup_pin_config_t structure. + */ +void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config) +{ + assert(config != NULL); + + volatile uint32_t *edgeRegBase = NULL; + volatile uint32_t *eventRegBase = NULL; + uint32_t edgeReg; + uint32_t eventReg; + uint32_t modeReg; + uint8_t offset; + + /* Calculate offset. */ + offset = 2U * (pinIndex & 0xFU); + + if (config->edge != kWUU_ExternalPinDisable) + { + /* Based on pin index, get register base address. */ + if ((pinIndex >> 4U) != 0U) + { + edgeRegBase = &base->PE2; + eventRegBase = &base->PDC2; + } + else + { + edgeRegBase = &base->PE1; + eventRegBase = &base->PDC1; + } + + /* Enable and config the edge detection. */ + edgeReg = *edgeRegBase; + edgeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PE_REG_BIT_FIELD_MASK, offset); + edgeReg |= WUU_SET_BIT_FIELD_IN_REG(config->edge, offset); + *edgeRegBase = edgeReg; + + /* Config the wakeup event. */ + eventReg = *eventRegBase; + eventReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PDC_REG_BIT_FIELD_MASK, offset); + eventReg |= WUU_SET_BIT_FIELD_IN_REG(config->event, offset); + *eventRegBase = eventReg; + + /* Config operate mode. */ + modeReg = base->PMC; + modeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PMC_REG_BIT_FIELD_MASK, pinIndex); + modeReg |= WUU_SET_BIT_FIELD_IN_REG(config->mode, pinIndex); + + base->PMC = modeReg; + } + else + { + /* Based on pin index, get register base address. */ + if ((pinIndex >> 4U) != 0U) + { + edgeRegBase = &base->PE2; + } + else + { + edgeRegBase = &base->PE1; + } + + edgeReg = *edgeRegBase; + edgeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PE_REG_BIT_FIELD_MASK, offset); + *edgeRegBase = edgeReg; + } +} + +/*! + * brief Config Internal modules' event as the wake up soures. + * + * This function configs the internal modules event as the wake up sources. + * + * param base WUU peripheral base address. + * param moduleIndex The selected internal module. See the Reference Manual for the details. + * param event Select interrupt or DMA/Trigger of the internal module as the wake up source. + */ +void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event) +{ + switch (event) + { + case kWUU_InternalModuleInterrupt: + base->ME |= WUU_SET_BIT_FIELD_IN_REG(WUU_ME_REG_WUME_FIELD_MASK, moduleIndex); + break; + case kWUU_InternalModuleDMATrigger: + base->DE |= WUU_SET_BIT_FIELD_IN_REG(WUU_DE_REG_WUME_FIELD_MASK, moduleIndex); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Disable an on-chip internal modules' event as the wakeup sources. + * + * param base WUU peripheral base address. + * param moduleIndex The selected internal module. See the Reference Manual for the details. + * param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event) +{ + switch(event) + { + case kWUU_InternalModuleInterrupt: + base->ME &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_ME_REG_WUME_FIELD_MASK, moduleIndex); + break; + case kWUU_InternalModuleDMATrigger: + base->DE &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_DE_REG_WUME_FIELD_MASK, moduleIndex); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Configs and Enables Pin filters. + * + * This function configs Pin filter, including pin select, filer operate mode + * filer wakeup event and filter edge detection. + * + * param base WUU peripheral base address. + * param filterIndex The index of the pin filer. + * param config Pointer to wuu_pin_filter_config_t structure. + */ +void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config) +{ + assert(config != NULL); + + uint8_t shift; + uint32_t filterReg; + uint32_t eventReg; + uint32_t modeReg; + + shift = (filterIndex - 1U) * 8U; + filterReg = base->FILT; + filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTE_FIELD_MASK, shift); + filterReg |= WUU_SET_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD(config->edge), shift); + + if (config->edge != kWUU_FilterDisabled) + { + filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD_MASK, shift); + filterReg |= WUU_SET_BIT_FIELD_IN_REG(config->pinIndex, shift); + + /* Config wake up event. */ + shift = (filterIndex - 1U) * 2U; + eventReg = base->FDC; + eventReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FDC_REG_FILTC_FIELD_MASK, shift); + eventReg |= WUU_SET_BIT_FIELD_IN_REG(config->event, shift); + base->FDC = eventReg; + + /* Config operate mode. */ + shift = (filterIndex - 1U) * 1U; + modeReg = base->FMC; + modeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FMC_REG_FILTM_FIELD_MASK, shift); + modeReg |= WUU_SET_BIT_FIELD_IN_REG(config->mode, shift); + base->FMC = modeReg; + } + + base->FILT = filterReg; +} + +/*! + * brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * param base WUU peripheral base address. + * param filterIndex A pin filter index, which starts from 1. + * return True if the flag is a source of the existing low-leakage power mode. + */ +bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex) +{ + bool ret = false; + + switch (filterIndex) + { + case 1: + ret = ((base->FILT & WUU_FILT_FILTF1_MASK) != 0U); + break; + case 2: + ret = ((base->FILT & WUU_FILT_FILTF2_MASK) != 0U); + break; + default: + ret = false; + break; + } + + return ret; +} + +/*! + * brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * param base WUU peripheral base address. + * param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex) +{ + uint32_t reg; + + reg = base->FILT; + /* Clean the W1C bits, in case the flags are cleared by mistake. */ + reg &= ~(WUU_FILT_FILTF1_MASK | WUU_FILT_FILTF2_MASK); + + reg |= WUU_SET_BIT_FIELD_IN_REG(WUU_FILT_FILTF1_MASK, ((filterIndex - 1U) * 8U)); + + base->FILT = reg; +} + +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + * return True if the specific pin is a wakeup source. + */ +bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex) +{ + return (0U != (base->PF & (1UL << pinIndex))); +} + +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + */ +void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex) +{ + base->PF = (1UL << pinIndex); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wuu.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wuu.h new file mode 100644 index 0000000000..87a2ae13f1 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wuu.h @@ -0,0 +1,286 @@ +/* + * Copyright 2019-2023 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_WUU_H_ +#define FSL_WUU_H_ + +#include "fsl_common.h" + +/*! @addtogroup wuu */ +/*! @{ */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WUU driver version 2.3.0. */ +#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*@}*/ + +/*! + * @brief External WakeUp pin edge detection enumeration. + */ +typedef enum _wuu_external_pin_edge_detection +{ + kWUU_ExternalPinDisable = 0x0U, /*!< External input Pin disabled as wake up input. */ + kWUU_ExternalPinRisingEdge = 0x1U, /*!< External input Pin enabled with the rising edge detection. */ + kWUU_ExternalPinFallingEdge = 0x2U, /*!< External input Pin enabled with the falling edge detection. */ + kWUU_ExternalPinAnyEdge = 0x3U, /*!< External input Pin enabled with any change detection. */ +} wuu_external_pin_edge_detection_t; + +/*! + * @brief External input wake up pin event enumeration. + */ +typedef enum _wuu_external_wakeup_pin_event +{ + kWUU_ExternalPinInterrupt = 0x0U, /*!< External input Pin configured as interrupt. */ + kWUU_ExternalPinDMARequest = 0x1U, /*!< External input Pin configured as DMA request. */ + kWUU_ExternalPinTriggerEvent = 0x2U, /*!< External input Pin configured as Trigger event. */ +} wuu_external_wakeup_pin_event_t; + +/*! + * @brief External input wake up pin mode enumeration. + */ +typedef enum _wuu_external_wakeup_pin_mode +{ + kWUU_ExternalPinActiveDSPD = 0x0U, /*!< External input Pin is active only during Deep Sleep/Power Down Mode. */ + kWUU_ExternalPinActiveAlways = 0x1U, /*!< External input Pin is active during all power modes. */ +} wuu_external_wakeup_pin_mode_t; + +/*! + * @brief Internal module wake up event enumeration. + */ +typedef enum _wuu_internal_wakeup_module_event +{ + kWUU_InternalModuleInterrupt = 0x0U, /*!< Internal modules' interrupt as a wakeup source. */ + kWUU_InternalModuleDMATrigger = 0x1U, /*!< Internal modules' DMA/Trigger as a wakeup source. */ +} wuu_internal_wakeup_module_event_t; + +/*! + * @brief Pin filter edge enumeration. + */ +typedef enum _wuu_filter_edge +{ + kWUU_FilterDisabled = 0x0U, /*!< Filter disabled. */ + kWUU_FilterPosedgeEnable = 0x1U, /*!< Filter posedge detect enabled. */ + kWUU_FilterNegedgeEnable = 0x2U, /*!< Filter negedge detect enabled. */ + kWUU_FilterAnyEdge = 0x3U, /*!< Filter any edge detect enabled. */ +} wuu_filter_edge_t; + +/*! + * @brief Pin Filter event enumeration. + */ +typedef enum _wuu_filter_event +{ + kWUU_FilterInterrupt = 0x0U, /*!< Filter output configured as interrupt. */ + kWUU_FilterDMARequest = 0x1U, /*!< Filter output configured as DMA request. */ + kWUU_FilterTriggerEvent = 0x2U, /*!< Filter output configured as Trigger event. */ +} wuu_filter_event_t; + +/*! + * @brief Pin filter mode enumeration. + */ +typedef enum _wuu_filter_mode +{ + kWUU_FilterActiveDSPD = 0x0U, /*!< External input pin filter is active only during Deep Sleep/Power Down Mode. */ + kWUU_FilterActiveAlways = 0x1U, /*!< External input Pin filter is active during all power modes. */ +} wuu_filter_mode_t; + +/*! + * @brief External WakeUp pin configuration + */ +typedef struct _wuu_external_wakeup_pin_config +{ + wuu_external_pin_edge_detection_t edge; /*!< External Input pin edge detection. */ + wuu_external_wakeup_pin_event_t event; /*!< External Input wakeup Pin event */ + wuu_external_wakeup_pin_mode_t mode; /*!< External Input wakeup Pin operate mode. */ +} wuu_external_wakeup_pin_config_t; + +/*! + * @brief Pin Filter configuration. + */ +typedef struct _wuu_pin_filter_config +{ + uint32_t pinIndex; /*!< The index of wakeup pin to be muxxed into filter. */ + wuu_filter_edge_t edge; /*!< The edge of the pin digital filter. */ + wuu_filter_event_t event; /*!< The event of the filter output. */ + wuu_filter_mode_t mode; /*!< The mode of the filter operate. */ +} wuu_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name External Wake up Pins Control APIs. + * @{ + */ +/*! + * @brief Enables and Configs External WakeUp Pins. + * + * This function enables/disables the external pin as wakeup input. What's more this + * function configs pins options, including edge detection wakeup event and operate mode. + * + * @param base MUU peripheral base address. + * @param pinIndex The index of the external input pin. See Reference Manual for the details. + * @param config Pointer to wuu_external_wakeup_pin_config_t structure. + */ +void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config); + +/*! + * @brief Gets External Wakeup pin flags. + * + * This function return the external wakeup pin flags. + * + * @param base WUU peripheral base address. + * @return Wakeup flags for all external wakeup pins. + */ +static inline uint32_t WUU_GetExternalWakeUpPinsFlag(WUU_Type *base) +{ + return base->PF; +} + +/*! + * @brief Clears External WakeUp Pin flags. + * + * This function clears external wakeup pins flags based on the mask. + * + * @param base WUU peripheral base address. + * @param mask The mask of Wakeup pin index to be cleared. + */ +static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask) +{ + base->PF = mask; +} +/* @} */ + +/*! + * @name Internal Wakeup Module control APIs. + * @{ + */ + +/*! + * @brief Config Internal modules' event as the wake up soures. + * + * This function configs the internal modules event as the wake up sources. + * + * @param base WUU peripheral base address. + * @param moduleIndex The selected internal module. See the Reference Manual for the details. + * @param event Select interrupt or DMA/Trigger of the internal module as the wake up source. + */ +void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); + +/*! + * @brief Disable an on-chip internal modules' event as the wakeup sources. + * + * @param base WUU peripheral base address. + * @param moduleIndex The selected internal module. See the Reference Manual for the details. + * @param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); + +#if (defined(FSL_FEATURE_WUU_HAS_MF) && FSL_FEATURE_WUU_HAS_MF) +/*! + * @brief Get wakeup flags for internal wakeup modules. + * + * @param base WUU peripheral base address. + * @return Wakeup flags for all internal wakeup modules. + */ +static inline uint32_t WUU_GetModuleInterruptFlag(WUU_Type *base) +{ + return base->MF; +} + +/*! + * @brief Gets the internal module wakeup source flag. + * + * This function checks the flag to detect whether the system is + * woken up by specific on-chip module interrupt. + * + * @param base WWU peripheral base address. + * @param moduleIndex A module index, which starts from 0. + * @return True if the specific pin is a wake up source. + */ +static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t moduleIndex) +{ + return ((1UL << moduleIndex) == (WUU_GetModuleInterruptFlag(base) & (1UL << moduleIndex))); +} +#endif /* FSL_FEATURE_WUU_HAS_MF */ + +/* @} */ + +/*! + * @name Pin Filter Control APIs + * @{ + */ +/*! + * @brief Configs and Enables Pin filters. + * + * This function configs Pin filter, including pin select, filer operate mode + * filer wakeup event and filter edge detection. + * + * @param base WUU peripheral base address. + * @param filterIndex The index of the pin filer. + * @param config Pointer to wuu_pin_filter_config_t structure. + */ +void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base WUU peripheral base address. + * @param filterIndex A pin filter index, which starts from 1. + * @return True if the flag is a source of the existing low-leakage power mode. + */ +bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex); + +/*! + * @brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * @param base WUU peripheral base address. + * @param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex); + +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + * return True if the specific pin is a wakeup source. + */ +bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); + +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + */ +void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*FSL_WUU_H_*/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wwdt.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wwdt.c new file mode 100644 index 0000000000..6680148acf --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wwdt.c @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wwdt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wwdt" +#endif + +#define FREQUENCY_3MHZ (3000000U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base WWDT peripheral base address + * + * @return The WWDT instance + */ +static uint32_t WWDT_GetInstance(WWDT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to WWDT bases for each instance. */ +static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to WWDT clocks for each instance. */ +static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +/*! @brief Pointers to WWDT resets for each instance. */ +static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WWDT_GetInstance(WWDT_Type *base) +{ + uint32_t instance; + uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < wwdtArrayCount; instance++) + { + if (s_wwdtBases[instance] == base) + { + break; + } + } + + assert(instance < wwdtArrayCount); + + return instance; +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * endcode + * + * param config Pointer to WWDT config structure. + * see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Enable the watch dog */ + config->enableWwdt = true; + /* Disable the watchdog timeout reset */ + config->enableWatchdogReset = false; + /* Disable the watchdog protection for updating the timeout value */ + config->enableWatchdogProtect = false; +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + /* Do not lock the watchdog oscillator */ + config->enableLockOscillator = false; +#endif + /* Windowing is not in effect */ + config->windowValue = 0xFFFFFFU; + /* Set the timeout value to the max */ + config->timeoutValue = 0xFFFFFFU; + /* No warning is provided */ + config->warningValue = 0; + /* Set clock frequency. */ + config->clockFreq_Hz = 0U; +} + +/*! + * brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * endcode + * + * param base WWDT peripheral base address + * param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) +{ + assert(NULL != config); + + uint32_t value = 0U; + uint32_t DelayUs = 0U; + uint32_t primaskValue = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the WWDT clock */ + CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) + /* Reset the module. */ + RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it by write 1. */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; + /* Enable the watchdog reset event to affect the system in the Power Management Controller */ + PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | + WWDT_MOD_LOCK(config->enableLockOscillator); +#else + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); +#endif + /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ + if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) + { + value |= WWDT_MOD_WDINT_MASK; + } + /* Set configuration */ + primaskValue = DisableGlobalIRQ(); + base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD = value; + base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); + base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); + /* Refreshes the WWDT timer. */ + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); + /* Read counter value to wait wwdt timer start*/ + if (config->enableWwdt) + { + while (base->TV == 0xFFUL) + { + } + } + + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) + { + /* The config->clockFreq_Hz must be set in order to config the delay time. */ + assert(0U != config->clockFreq_Hz); + + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ + DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; + SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + base->MOD |= WWDT_MOD_WDPROTECT(1U); + } +} + +/*! + * brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the WWDT clock */ + CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} + +/*! + * brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * endcode + * param base WWDT peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) +{ + /* Clear the WDINT bit so that we don't accidentally clear it */ + uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); + + /* Clear timeout by writing a zero */ + if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) + { + reg &= ~WWDT_MOD_WDTOF_MASK; +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + } + + /* Clear warning interrupt flag by writing a one */ + if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) + { + reg |= WWDT_MOD_WDINT_MASK; + } + + base->MOD = reg; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wwdt.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wwdt.h new file mode 100644 index 0000000000..e1ee183dd5 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/fsl_wwdt.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_WWDT_H_ +#define FSL_WWDT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wwdt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WWDT driver version. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ +#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ +/*@}*/ + +/*! @brief Describes WWDT configuration structure. */ +typedef struct _wwdt_config +{ + bool enableWwdt; /*!< Enables or disables WWDT */ + bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset + false: Watchdog timeout will not cause a chip reset */ + bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be + changed after counter is below warning & window values + false: Disable watchdog protect; timeout value can be changed + at any time */ +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented + Once set, this bit can only be cleared by a reset + false: Do not lock oscillator */ +#endif + uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ + uint32_t timeoutValue; /*!< Timeout value */ + uint32_t warningValue; /*!< Watchdog time counter value that will generate a + warning interrupt. Set this to 0 for no warning */ + uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ +} wwdt_config_t; + +/*! + * @brief WWDT status flags. + * + * This structure contains the WWDT status flags for use in the WWDT functions. + */ +enum _wwdt_status_flags_t +{ + kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ + kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WWDT Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * @code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * @endcode + * + * @param config Pointer to WWDT config structure. + * @see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config); + +/*! + * @brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * @code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * @endcode + * + * @param base WWDT peripheral base address + * @param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); + +/*! + * @brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * @param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base); + +/* @} */ + +/*! + * @name WWDT Functional Operation + * @{ + */ + +/*! + * @brief Enables the WWDT module. + * + * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; + * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run + * permanently. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Enable(WWDT_Type *base) +{ + base->MOD |= WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Disables the WWDT module. + * @deprecated Do not use this function. It will be deleted in next release version, for + * once the bit field of WDEN written with a 1, it can not be re-written with a 0. + * + * This function write value into WWDT_MOD register to disable the WWDT. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Disable(WWDT_Type *base) +{ + base->MOD &= ~WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Gets all WWDT status flags. + * + * This function gets all status flags. + * + * Example for getting Timeout Flag: + * @code + * uint32_t status; + * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; + * @endcode + * @param base WWDT peripheral base address + * @return The status flags. This is the logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) +{ +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + uint32_t status; + /* WDTOF is not set in case of WD reset - get info from PMC instead */ + status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); + if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) + { + status |= kWWDT_TimeoutFlag; + } + return status; +#else + return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ +} + +/*! + * @brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * @code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * @endcode + * @param base WWDT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); + +/*! + * @brief Set the WWDT warning value. + * + * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog + * interrupt. When the watchdog timer counter is no longer greater than the value defined by + * WARNINT, an interrupt will be generated after the subsequent WDCLK. + * + * @param base WWDT peripheral base address + * @param warningValue WWDT warning value. + */ +static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) +{ + base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); +} + +/*! + * @brief Set the WWDT timeout value. + * + * This function sets the timeout value. Every time a feed sequence occurs the value in the TC + * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be + * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. + * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change + * the timeout value before the watchdog counter is below the warning and window values + * will cause a watchdog reset and set the WDTOF flag. + * + * @param base WWDT peripheral base address + * @param timeoutCount WWDT timeout value, count of WWDT clock tick. + */ +static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) +{ + base->TC = WWDT_TC_COUNT(timeoutCount); +} + +/*! + * @brief Sets the WWDT window value. + * + * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. + * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog + * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer + * value) so windowing is not in effect. + * + * @param base WWDT peripheral base address + * @param windowValue WWDT window value. + */ +static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) +{ + base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); +} + +/*! + * @brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* FSL_WWDT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_efuse.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_efuse.h new file mode 100644 index 0000000000..aad5bf341c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_efuse.h @@ -0,0 +1,112 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_EFUSE_H_ +#define FSL_EFUSE_H_ + +#include "fsl_flash.h" + +/*! + * @addtogroup efuse_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EFUSE APIs + * @{ + */ + +/*! + * @brief Initialize EFUSE controller. + * + * This function enables EFUSE Controller clock. + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Init(void); + +/*! + * @brief De-Initialize EFUSE controller. + * + * This functin disables EFUSE Controller Clock. + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Deinit(void); + +/*! + * @brief Read Fuse value from eFuse word. + * + * This function read fuse data from eFuse word to specified data buffer. + * + * @param addr Fuse address + * @param data Buffer to hold the data read from eFuse word + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Read(uint32_t addr, uint32_t *data); + +/*! + * @brief Program value to eFuse block. + * + * This function program data to specified eFuse address. + * + * @param addr Fuse address + * @param data data to be programmed into eFuse Fuse block + * + * @retval #kStatus_Success 0 Operation succeeded without error. + * @retval #kStatus_Fail 1 The operation failed with a generic error. + * @retval #kStatus_ReadOnly 2 Requested value cannot be changed because it is read-only. + * @retval #kStatus_OutOfRange 3 Requested value is out of range. + * @retval #kStatus_InvalidArgument 4 The requested command's argument is undefined. + * @retval #kStatus_Timeout An invalid 5 A timeout occurred + * @retval #kStatus_NoTransferInProgress 6 No send in progress. + */ +status_t EFUSE_Program(uint32_t addr, uint32_t data); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /*! FSL_EFUSE_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flash.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flash.h new file mode 100644 index 0000000000..ccdf3ff900 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flash.h @@ -0,0 +1,591 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLASH_H_ +#define FSL_FLASH_H_ + +#include "fsl_common.h" +/*! + * @addtogroup flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @name Flash version + * @{ + */ +/*! @brief Constructs the version number for drivers. */ +#if !defined(MAKE_VERSION) +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +#endif + +/*! @brief Flash driver version for SDK*/ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) /*!< Version 1.0.0. */ + +/*! @brief Flash driver version for ROM*/ +enum _flash_driver_version_constants +{ + kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ + kFLASH_DriverVersionMajor = 1, /*!< Major flash driver version.*/ + kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ +}; +/*@}*/ + +/*! + * @name Flash driver support feature + * @{ + */ +#define FSL_FEATURE_SYSCON_HAS_FLASH_HIDING 1U + +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/ + kStatus_FLASH_RegionExecuteOnly = + MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/ + kStatus_FLASH_ExecuteInRamFunctionNotReady = + MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/ + + kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/ + kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/ + kStatus_FLASH_InvalidPropertyValue = + MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/ + kStatus_FLASH_InvalidSpeculationOption = + MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/ + kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver, + 0x10), /*!< A correctable or uncorrectable error during command execution. */ + kStatus_FLASH_CompareError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */ + kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */ + kStatus_FLASH_InvalidWaitStateCycles = + MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */ + + kStatus_FLASH_OutOfDateCfpaPage = + MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */ + kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */ + kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce = + MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */ + kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS( + kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */ + kStatus_FLASH_HashCheckError = + MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */ + kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */ + kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS( + kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */ + kStatus_FLASH_NmpaAccessNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */ + kStatus_FLASH_CmpaCfgDirectEraseNotAllowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */ + kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */ + kStatus_FLASH_CfpaScratchPageInvalid = + MAKE_STATUS(kStatusGroupFlashDriver, 0x30), /*!< CFPA Scratch Page is invalid*/ + kStatus_FLASH_CfpaVersionRollbackDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x31), /*!< CFPA version rollback is not allowed */ + kStatus_FLASH_ReadHidingAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x32), /*!< Flash hiding read is not allowed */ + kStatus_FLASH_ModifyProtectedAreaDisallowed = + MAKE_STATUS(kStatusGroupFlashDriver, 0x33), /*!< Flash firewall page locked erase and program are not allowed */ + kStatus_FLASH_CommandOperationInProgress = MAKE_STATUS( + kStatusGroupFlashDriver, 0x34), /*!< The flash state is busy, indicate that a flash command in progress. */ +}; +/*@}*/ + +/*! + * @name Flash API key + * @{ + */ +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/ + + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! + * @brief Enumeration for flash max pages to erase. + */ +enum _flash_max_erase_page_value +{ + kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */ +}; + +/*! + * @brief Enumeration for flash alignment property. + */ +enum _flash_alignment_property +{ + kFLASH_AlignementUnitVerifyErase = 4U, /*!< The alignment unit in bytes used for verify erase operation.*/ + kFLASH_AlignementUnitProgram = 512U, /*!< The alignment unit in bytes used for program operation.*/ + /*kFLASH_AlignementUnitVerifyProgram = 4U,*/ /*!< The alignment unit in bytes used for verify program operation.*/ + kFLASH_AlignementUnitSingleWordRead = 16U /*!< The alignment unit in bytes used for SingleWordRead command.*/ +}; + +/*! + * @brief Enumeration for flash read ecc option + */ +enum _flash_read_ecc_option +{ + kFLASH_ReadWithEccOn = 0U, /*! ECC is on */ + kFLASH_ReadWithEccOff = 1U /*! ECC is off */ +}; + +/*! + * @brief Enumeration for flash read margin option + */ +enum _flash_read_margin_option +{ + kFLASH_ReadMarginNormal = 0U, /*!< Normal read */ + kFLASH_ReadMarginVsProgram = 1U, /*!< Margin vs. program */ + kFLASH_ReadMarginVsErase = 2U, /*!< Margin vs. erase */ + kFLASH_ReadMarginIllegalBitCombination = 3U /*!< Illegal bit combination */ +}; + +/*! + * @brief Enumeration for flash read dmacc option + */ +enum _flash_read_dmacc_option +{ + kFLASH_ReadDmaccDisabled = 0U, /*!< Memory word */ + kFLASH_ReadDmaccEnabled = 1U /*!< DMACC word */ +}; + +/*! + * @brief Enumeration for flash ramp control option + */ +enum _flash_ramp_control_option +{ + kFLASH_RampControlDivisionFactorReserved = 0U, /*!< Reserved */ + kFLASH_RampControlDivisionFactor256 = 1U, /*!< clk48mhz / 256 = 187.5KHz */ + kFLASH_RampControlDivisionFactor128 = 2U, /*!< clk48mhz / 128 = 375KHz */ + kFLASH_RampControlDivisionFactor64 = 3U /*!< clk48mhz / 64 = 750KHz */ +}; + +/*! @brief Flash ECC log info. */ +typedef struct _flash_ecc_log +{ + uint32_t firstEccEventAddress; + uint32_t eccErrorCount; + uint32_t eccCorrectionCount; + uint32_t reserved; +} flash_ecc_log_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_mode_config +{ + uint32_t sysFreqInMHz; + /* ReadSingleWord parameter. */ + struct + { + uint8_t readWithEccOff : 1; + uint8_t readMarginLevel : 2; + uint8_t readDmaccWord : 1; + uint8_t reserved0 : 4; + uint8_t reserved1[3]; + } readSingleWord; + /* SetWriteMode parameter. */ + struct + { + uint8_t programRampControl; + uint8_t eraseRampControl; + uint8_t reserved[2]; + } setWriteMode; + /* SetReadMode parameter. */ + struct + { + uint16_t readInterfaceTimingTrim; + uint16_t readControllerTimingTrim; + uint8_t readWaitStates; + uint8_t reserved[3]; + } setReadMode; +} flash_mode_config_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; + flash_mode_config_t modeConfig; + uint32_t *nbootCtx; + bool useAhbRead; +} flash_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Init(flash_config_t *config); + +/*! + * @brief De-Initializes the global flash properties structure members. + * + * This API De-initializes the FLASH default parameters and related FLASH clock for the FLASH and FMC. + * The flash_deinit API should be called after all the other FLASH APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_Deinit(flash_config_t *config); + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * NOTE: The start address need to be 4 Bytes-aligned. + * + * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. + * + * @param key The value used to validate all flash erase APIs. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError The address is out of range. + * @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + +/*! + * @name Reading + * @{ + */ + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + +/*@}*/ + +/*! + * @name Verification + * @{ + */ + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param margin Read margin choice. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param margin Read margin choice. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + +/*@}*/ + +/*! + * @name Properties + * @{ + */ + +/*! + * @brief Returns the desired flash property. + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + +/*@}*/ + +/*! + * @name CustKeyStore + * @{ + */ + +/*! + * @brief Get the customer key store data from the customer key store region . + * + * @param config Pointer to flash_config_t data structure in memory to store driver runtime state. + * @param pData Pointer to the customer key store data buffer, which got from the customer key store region. + * @param offset Point to the offset value based on the customer key store address(0x3e400) of the device. + * @param len Point to the length of the expected get customer key store data, and the offset + len <= 512B. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*@}*/ + +/*! + * @name flash status + * @{ + */ +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + * + * @param config A pointer to the storage for the driver runtime state. + * @param startAddress The start address of the desired flash memory to be verified. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +#endif + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FLASH_FLASH_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flash_ffr.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flash_ffr.h new file mode 100644 index 0000000000..29a764f812 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flash_ffr.h @@ -0,0 +1,591 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLASH_FFR_H_ +#define FSL_FLASH_FFR_H_ + +#include "fsl_flash.h" + +/*! + * @addtogroup flash_ffr_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Alignment(down) utility. */ +#if !defined(ALIGN_DOWN) +#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) +#endif + +/*! @brief Alignment(up) utility. */ +#if !defined(ALIGN_UP) +#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) +#endif + +#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_CUST_ADDRESS (0x200U) +#define FLASH_FFR_CUST_PAGE_NUMBER (15u) + +#define FLASH_FFR_HASH_DIGEST_SIZE (32u) +#define FLASH_FFR_IV_CODE_SIZE (52u) +#define FLASH_FFR_KETBLOB_OFFSET (0x160u) +#define FLASH_FFR_KETBLOB_SIZE (0x30u) +#define CFPA_HEADER_MARKER (0x9635u) +#define CMPA_HEADER_MARKER (0x5963u) +#define FLASH_FFR_UUID_SIZE (16u) +enum flash_ffr_page_offset +{ + kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ + kFfrPageOffset_CFPA_CfgPing = 0, /*!< CFPA Configuration area (Ping page)*/ + kFfrPageOffset_CFPA_CfgPong = 1, /*!< Same as CFPA page (Pong page)*/ + kFfrPageOffset_CMPA_Cfg = 2, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_NMPA_Cfg = 3, /*!< Customer Manufacturing programmed area*/ + kFfrPageOffset_SBL_Cfg = 4, /*!< SBL recovery programmed area*/ + kFfrPageOffset_B0_IFR1_Visible = 128, /*!< Trim programmed area*/ + +}; + +enum flash_ffr_page_num +{ + kFfrSectorNum_CFPA = 2, /*!< Customer In-Field programmed area*/ + kFfrSectorNum_CMPA = 1, /*!< Customer Manufacturing programmed area*/ + kFfrSectorNum_NMPA = 1, /*!< NXP Manufacturing programmed area*/ + kFfrSectorNum_SBL = 4, /*!< SBL Cus programmed area*/ + kFfrSectorNum_Total = (kFfrSectorNum_CFPA + kFfrSectorNum_CMPA + kFfrSectorNum_NMPA + kFfrSectorNum_SBL), +}; + +enum flash_ffr_block_size +{ + kFfrBlockSize_Key = 52u, + kFfrBlockSize_ActivationCode = 1000u, +}; + +enum cfpa_cfg_cmpa_prog_status +{ + kFfrCmpaProgStatus_Idle = 0x0u, + kFfrCmpaProgStatus_InProgress = 0x5CC55AA5u, +}; + +typedef enum +{ + kFfrCmpaProgProcess_Pre = 0x0u, + kFfrCmpaProgProcess_Post = 0xFFFFFFFFu, +} cmpa_prog_process_t; + +typedef struct +{ + struct + { + uint32_t cfpa_lc_state : 8; + uint32_t cfpa_lc_state_inv : 8; + uint32_t header_marker : 16; + } header; //!< [0x000-0x003] + + struct //!< [0x004-0x007] + { + uint32_t version : 24; //!< cfpa version + uint32_t img_upd : 2; //!< image cmac update + uint32_t reserved0 : 1; + uint32_t cmpa_update : 3; //!< CFPA page updated through SB command. + uint32_t reserved1 : 1; + uint32_t dice_en : 1; //!< Update DICE certificate during next boot + } cfpa_page_version; + + uint32_t secureFwVersion; //!< [0x008-0x00b] + uint32_t nsFwVersion; //!< [0x00c-0x00f] + uint32_t recFwVersion; //!< [0x010-0x013] + uint32_t secBootFlags; //!< [0x014-0x01f] + uint32_t imageKeyRevoke; //!< [0x018-0x01b] + uint32_t lpVectorAddr; //!< [0x01c-0x01f] + uint32_t vendorUsage; //!< [0x020-0x02f] + uint32_t dcfgNsPin; //!< [0x024-0x027] + uint32_t dcfgNsDflt; //!< [0x028-0x02b] + uint32_t reserved0; //!< [0x02c-0x02f] + uint32_t ivPrince[4]; //!< [0x030-0x03f] + uint32_t ivIped[8]; //!< [0x040-0x05f] + + uint32_t errCnt[8]; //!< [0x060-0x07f] + + uint32_t custCtr[8]; //!< [0x080-0x09f] + uint32_t mflagCtr[8]; //!< [0x0a0-0x0bf] + uint32_t flashAcl[8]; //!< [0x0C0-0x0Df] + uint32_t sblImg0Cmac[4]; //!< [0x0E0-0x0Ef] + uint32_t img1Cmac[4]; //!< [0x0F0-0x0Ff] + uint32_t diceCert[36]; //!< [0x100-0x18f] + uint32_t reserved2[23]; //!< [0x190-0x1eb] + uint32_t cfpaCrc; //!< [0x1ec-0x1ef] + uint32_t cfpaCmac[4]; //!< [0x1f0-0x1ff] +} cfpa_cfg_info_t; + +#define FFR_BOOTCFG_USBSPEED_SHIFT (9U) +#define FFR_BOOTCFG_USBSPEED_MASK (0x3u << FFR_BOOTCFG_USBSPEED_SHIFT) +#define FFR_BOOTCFG_USBSPEED_NMPASEL0 (0x0U) +#define FFR_BOOTCFG_USBSPEED_FS (0x1U) +#define FFR_BOOTCFG_USBSPEED_HS (0x2U) +#define FFR_BOOTCFG_USBSPEED_NMPASEL3 (0x3U) + +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) +#define FFR_BOOTCFG_BOOTSPEED_NMPASEL (0x0U) +#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x1U) +#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x2U) + +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_PRODUCTID_SHIFT (16U) + +#define FFR_IMAGE0_CMAC_UPDATE_MASK (0x1) +#define FFR_IMAGE1_CMAC_UPDATE_MASK (0x2) + +#define FFR_IFR1_PUF_AC_CODE_ADDR (0x01100200UL) +#define FFR_IFR1_PUF_AC_CODE_LEN (1024UL) + +#define FFR_IFR1_NXP_CERT_ADDR (0x01100600UL) +#define FFR_IFR1_NXP_CERT_LEN (1448UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY0_ADDR (0x01101900UL) +#define FFR_IFR1_ROM_PATCH_ARRAY0_LEN (1792UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY1_ADDR (0x01102000UL) +#define FFR_IFR1_ROM_PATCH_ARRAY1_LEN (3584UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY2_ADDR (0x01103000UL) +#define FFR_IFR1_ROM_PATCH_ARRAY2_LEN (2048UL) + +#define FFR_IFR1_ROM_PATCH_ARRAY3_ADDR (0x01103800UL) +#define FFR_IFR1_ROM_PATCH_ARRAY3_LEN (2048UL) + +#define FFR_IFR1_NXP_WRITEABLE_REGION0_START (FFR_IFR1_PUF_AC_CODE_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION0_END \ + (FFR_IFR1_PUF_AC_CODE_ADDR + FFR_IFR1_PUF_AC_CODE_LEN + FFR_IFR1_NXP_CERT_LEN) +#define FFR_IFR1_NXP_WRITEABLE_REGION1_START (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION1_END \ + (FFR_IFR1_ROM_PATCH_ARRAY0_ADDR + FFR_IFR1_ROM_PATCH_ARRAY0_LEN + FFR_IFR1_ROM_PATCH_ARRAY1_LEN) +#define FFR_IFR1_NXP_WRITEABLE_REGION2_START (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR) +#define FFR_IFR1_NXP_WRITEABLE_REGION2_END \ + (FFR_IFR1_ROM_PATCH_ARRAY2_ADDR + FFR_IFR1_ROM_PATCH_ARRAY2_LEN + FFR_IFR1_ROM_PATCH_ARRAY3_LEN) + +typedef struct +{ + struct + { + uint32_t boot_src : 2; + uint32_t rsv0 : 2; + uint32_t isp_boot_if : 3; + uint32_t rsv1 : 1; + uint32_t rec_boot_src : 2; + uint32_t rsv2 : 2; + uint32_t boot_speed : 2; + uint32_t rsv3 : 2; + uint32_t header_marker : 16; + } bootCfg; //!< [0x000-0x003] + + struct + { + uint32_t flash_remap_size : 5; + uint32_t bank1_ifr0_usage : 3; + uint32_t reserved : 24; + } FlashCfg; //!< [0x004-0x007] + + struct + { + uint8_t recLed; + uint8_t ispLed; + uint8_t bootFailLed; + uint8_t resv0; + } bootLedStatus; //!< [0x008-0x00b] + + struct + { + uint16_t powerDnTimeout; + uint16_t wdogTimeout; + } bootTimers; //!< [0x00c-0x00f] + + uint32_t resv2; //!< [0x010-0x013] + uint32_t resv3; //!< [0x014-0x017] + + uint32_t recSpiFlashCfg0; //!< [0x018-0x01b] + uint32_t recSpiFlashCfg1; //!< [0x01c-0x01f] + + uint32_t isp_uart_cfg; //!< [0x020-0x023] + uint32_t isp_i2c_cfg; //!< [0x024-0x027] + uint32_t isp_can_cfg; //!< [0x028-0x02b] + uint32_t isp_spi_cfg0; //!< [0x02c-0x02f] + uint32_t isp_spi_cfg1; //!< [0x030-0x034] + + struct + { + uint16_t vid; + uint16_t pid; + } usbId; //!< [0x034-0x037] + + uint32_t isp_usb_cfg; //!< [0x038-0x038] + uint32_t isp_misc_cfg; //!< [0x03c-0x03f] + uint32_t dcfgPin; //!< [0x040-0x043] + uint32_t dcfgDflt; //!< [0x044-0x047] + uint32_t dapVendorUsage; //!< [0x048-0x04b] + uint32_t resv1; //!< [0x04c-0x04f] + uint32_t secureBootCfg; //!< [0x050-0x053] + uint32_t rokthUsage; //!< [0x054-0x057] + uint32_t resv4; //!< [0x058-0x05b] + uint32_t resv5; //!< [0x05c-0x05f] + uint32_t rotkh[12]; //!< [0x060-0x08f] + + struct + { + uint32_t npx_w0; + uint32_t npx_w1; + } princeSr[4]; //!< [0x090-0x0af] + + struct + { + uint32_t ipedStartAddr; + uint32_t ipedEndAddr; + } ipedRegions[8]; //!< [0x0b0-0x11f] + + uint32_t rec_img_exit0; + uint32_t rec_img_exit1; + + uint32_t resv6[10]; + + struct + { + uint32_t set0; + uint32_t clr0; + } quickSetGpio[6]; //!< [0x120-0x14f] + + uint32_t resv7[4]; //!< [0x150-0x15f] + uint32_t cust_key_blob[12]; //!< [0x160-0x18f] + + uint32_t resv8[23]; //!< [0x190-0x1eb] + uint32_t cmpaCrc; //!< [0x1ec-0x1ef] + uint32_t cmpaCmac[4]; //!< [0x1f0-0x1ff] + +} cmpa_cfg_info_t; + +typedef struct +{ + uint32_t header; + uint8_t reserved[4]; +} cmpa_key_store_header_t; + +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) +#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) + +#define FFR_USBCFG_USBSPEED_HS (0x0U) +#define FFR_USBCFG_USBSPEED_FS (0x1U) +#define FFR_USBCFG_USBSPEED_NO (0x2U) + +#define FFR_MCAN_BAUDRATE_MASK (0xF0000U) +#define FFR_MCAN_BAUDRATE_SHIFT (16U) + +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) + +#define FFR_PUF_SRAM_CONFIG_MASK (0x3FFFF07) +#define FFR_PUF_SRAM_CONFIG_MASK_SHIFT (0U) +#define FFR_PUF_SRAM_VALID_MASK (0x1U) +#define FFR_PUF_SRAM_VALID_SHIFT (0U) +#define FFR_PUF_SRAM_MODE_MASK (0x2U) +#define FFR_PUF_SRAM_MODE_SHIFT (1U) +#define FFR_PUF_SRAM_CKGATING_MASK (0x4U) +#define FFR_PUF_SRAM_CKGATING_SHIFT (2) +#define FFR_PUF_SRAM_SMB_MASK (0x300U) +#define FFR_PUF_SRAM_SMB_SHIFT (8U) +#define FFR_PUF_SRAM_RM_MASK (0x1C00U) +#define FFR_PUF_SRAM_RM_SHIFT (10U) +#define FFR_PUF_SRAM_WM_MASK (0xE000U) +#define FFR_PUF_SRAM_WM_SHIFT (13U) +#define FFR_PUF_SRAM_WRME_MASK (0x10000U) +#define FFR_PUF_SRAM_WRME_SHIFT (16U) +#define FFR_PUF_SRAM_RAEN_MASK (0x20000U) +#define FFR_PUF_SRAM_RAEN_SHIFT (17U) +#define FFR_PUF_SRAM_RAM_MASK (0x3C0000U) +#define FFR_PUF_SRAM_RAM_SHIFT (18U) +#define FFR_PUF_SRAM_WAEN_MASK (0x400000U) +#define FFR_PUF_SRAM_WAEN_SHIFT (22U) +#define FFR_PUF_SRAM_WAM_MASK (0x1800000U) +#define FFR_PUF_SRAM_WAM_SHIFT (23U) +#define FFR_PUF_SRAM_STBP_MASK (0x2000000U) +#define FFR_PUF_SRAM_STBP_SHIFT (25U) + +typedef struct +{ + uint32_t fro32kCfg; //!< [0x000-0x003] + uint32_t puf_cfg; //!< [0x004-0x007] + uint32_t bod; //!< [0x008-0x00b] + uint32_t trim; //!< [0x00c-0x00f] + uint32_t deviceID; //!< [0x010-0x03f] + uint32_t peripheralCfg; //!< [0x014-0x017] + uint32_t dcdPowerProFileLOW[2]; //!< [0x018-0x01f] + uint32_t deviceType; //!< [0x020-0x023] + uint32_t ldo_ao; //!< [0x024-0x027] + uint32_t gdetDelayCfg; //!< [0x028-0x02b] + uint32_t gdetMargin; //!< [0x02c-0x02f] + uint32_t gdetTrim1; //!< [0x030-0x033] + uint32_t gdetEanble1; //!< [0x034-0x037] + uint32_t gdetCtrl1; //!< [0x038-0x03b] + uint32_t gdetUpdateTimer; //!< [0x03c-0x03f] + uint32_t GpoDataChecksum[4]; //!< [0x040-0x04f] + uint32_t finalTestBatchId[4]; //!< [0x050-0x05f] + uint32_t ecidBackup[4]; //!< [0x060-0x06f] + uint32_t uuid[4]; //!< [0x070-0x07f] + uint32_t reserved1[7]; //!< [0x080-0x09b] + struct + { + uint8_t xo32mReadyTimeoutInMs; + uint8_t usbSpeed; + uint8_t reserved[2]; + } usbCfg; //!< [0x09c-0x09f] + uint32_t reserved2[80]; //!< [0x0a0-0x1df] + uint8_t cmac[16]; //!< [0x1e0-0x1ef] + uint32_t pageChecksum[4]; //!< [0x1f0-0x1ff] +} nmpa_cfg_info_t; + +typedef struct +{ + uint8_t reserved[1][FLASH_FFR_MAX_PAGE_SIZE]; +} ffr_key_store_t; + +typedef enum +{ + kFFR_KeyTypeSbkek = 0x00U, + kFFR_KeyTypeUser = 0x01U, + kFFR_KeyTypeUds = 0x02U, + kFFR_KeyTypePrinceRegion0 = 0x03U, + kFFR_KeyTypePrinceRegion1 = 0x04U, + kFFR_KeyTypePrinceRegion2 = 0x05U, +} ffr_key_type_t; + +typedef enum +{ + kFFR_BankTypeBank0_CFPA0 = 0x00u, + kFFR_BankTypeBank0_CFPA1 = 0x01u, + kFFR_BankTypeBank0_CMPA = 0x02U, + kFFR_BankTypeBank0_NMPA = 0x03U, + kFFR_BankTypeBank0_SBL = 0x04U, + +} ffr_bank_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FFR APIs + * @{ + */ + +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + */ +status_t FFR_Lock(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_SizeError Error size + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_EraseKeyError API erase key is invalid. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + * @retval #kStatus_Fail Generic status for Fail. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A pointer to the source buffer of data that is to be programmed + * into the "Key store". + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_CommandFailure access error. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + * @retval #kStatus_FLASH_SealedFfrRegion The FFR region is sealed. + * @retval #kStatus_FLASH_FfrBankIsLocked The FFR bank region is locked. + * @retval #kStatus_FLASH_AddressError Address is out of range + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed Flash firewall page locked erase and program are not allowed + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed Flash hiding read is not allowed + * @retval #kStatus_FLASH_CommandFailure Run-time error during command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported + * @retval #kStatus_FLASH_RegulationLoss A loss of regulation during read. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /*! FSL_FLASH_FFR_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flexspi_nor_flash.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flexspi_nor_flash.h new file mode 100644 index 0000000000..2adabba33a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/fsl_flexspi_nor_flash.h @@ -0,0 +1,721 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef FSL_FLEXSPI_NOR_FLASH_H__ +#define FSL_FLEXSPI_NOR_FLASH_H__ + +#include "fsl_common.h" +/*! + * @addtogroup flexspi_nor_flash_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 0 /*!< FLEXSPI Feature related definitions */ + +#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +#define CMD_SDR 0x01U +#define CMD_DDR 0x21U +#define RADDR_SDR 0x02U +#define RADDR_DDR 0x22U +#define CADDR_SDR 0x03U +#define CADDR_DDR 0x23U +#define MODE1_SDR 0x04U +#define MODE1_DDR 0x24U +#define MODE2_SDR 0x05U +#define MODE2_DDR 0x25U +#define MODE4_SDR 0x06U +#define MODE4_DDR 0x26U +#define MODE8_SDR 0x07U +#define MODE8_DDR 0x27U +#define WRITE_SDR 0x08U +#define WRITE_DDR 0x28U +#define READ_SDR 0x09U +#define READ_DDR 0x29U +#define LEARN_SDR 0x0AU +#define LEARN_DDR 0x2AU +#define DATSZ_SDR 0x0BU +#define DATSZ_DDR 0x2BU +#define DUMMY_SDR 0x0CU +#define DUMMY_DDR 0x2CU +#define DUMMY_RWDS_SDR 0x0DU +#define DUMMY_RWDS_DDR 0x2DU +#define JMP_ON_CS 0x1FU +#define FLEXSPI_STOP 0U + +#define FLEXSPI_1PAD 0U +#define FLEXSPI_2PAD 1U +#define FLEXSPI_4PAD 2U +#define FLEXSPI_8PAD 3U + +/*! + * @brief NOR LUT sequence index used for default LUT assignment + * NOTE: + * The will take effect if the lut sequences are not customized. + */ +#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READID 7U +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */ + +/*! @brief FLEXSPI status group numbers. */ +enum _flexspi_status_groups +{ + kStatusROMGroup_FLEXSPI = 60, /*!< Group number for ROM FLEXSPI status codes. */ + kStatusROMGroup_FLEXSPINOR = 201, /*!< ROM FLEXSPI NOR status group number.*/ +}; + +/*! @brief FLEXSPI NOR status */ +enum _flexspi_nor_status +{ + kStatus_FLEXSPINOR_ProgramFail = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 0), /*!< Status for Page programming failure */ + kStatus_FLEXSPINOR_EraseSectorFail = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 1), /*!< Status for Sector Erase failure */ + kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 2), /*!< Status for Chip Erase failure */ + kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 3), /*!< Status for timeout */ + kStatus_FlexSPINOR_NotSupported = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 4), // Status for PageSize overflow */ + kStatus_FlexSPINOR_WriteAlignmentError = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 5), /*!< Status for Alignement error */ + kStatus_FlexSPINOR_CommandFailure = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 6), /*!< Status for Erase/Program Verify Error */ + kStatus_FlexSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */ + kStatus_FLEXSPINOR_Unsupported_SFDP_Version = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 8), /*!< Status for Unrecognized SFDP version */ + kStatus_FLEXSPINOR_Flash_NotFound = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */ + kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = + MAKE_STATUS(kStatusROMGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */ + + kStatus_FLEXSPI_SequenceExecutionTimeout = + MAKE_STATUS(kStatusROMGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */ + kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */ + kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusROMGroup_FLEXSPI, 2), /*!< Status for Device timeout */ + +}; + +/*! @brief Configure the device_type of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorCfgOption_Tag = 0x0cU, + kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0U, + kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1U, + kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2U, + kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3U, + kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4U, + kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5U, + kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6U, + kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7U, + kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8U, + kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9U, +}; + +/*! @brief Configure the quad_mode_setting of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorQuadMode_NotConfig = 0U, + kSerialNorQuadMode_StatusReg1_Bit6 = 1U, + kSerialNorQuadMode_StatusReg2_Bit1 = 2U, + kSerialNorQuadMode_StatusReg2_Bit7 = 3U, + kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4U, +}; + +/*! @brief FLEXSPI NOR Octal mode */ +enum +{ + kSerialNorOctaldMode_NoOctalEnableBit = 0U, + kSerialNorOctaldMode_HasOctalEnableBit = 1U, +}; + +/*! @brief miscellaneous mode */ +enum +{ + kSerialNorEnhanceMode_Disabled = 0U, + kSerialNorEnhanceMode_0_4_4_Mode = 1U, + kSerialNorEnhanceMode_0_8_8_Mode = 2U, + kSerialNorEnhanceMode_DataOrderSwapped = 3U, + kSerialNorEnhanceMode_2ndPinMux = 4U, + kSerialNorEnhanceMode_InternalLoopback = 5U, + kSerialNorEnhanceMode_SpiMode = 6U, + kSerialNorEnhanceMode_ExtDqs = 8U, +}; + +/*! @brief FLEXSPI NOR reset logic options */ +enum +{ + kFlashResetLogic_Disabled = 0U, + kFlashResetLogic_ResetPin = 1U, + kFlashResetLogic_JedecHwReset = 2U, +}; + +/*! @brief Configure the flash_connection of "serial_nor_config_option_t" structure */ +enum +{ + kSerialNorConnection_SinglePortA, + kSerialNorConnection_Parallel, + kSerialNorConnection_SinglePortB, + kSerialNorConnection_BothPorts +}; + +/*! @brief + * FLEXSPI ROOT clock soruce related definitions + */ +enum +{ + kFLEXSPIClkSrc_MainClk = 0U, + kFLEXSPIClkSrc_Pll0 = 1U, + kFLEXSPIClkSrc_FroHf = 3U, + kFLEXSPIClkSrc_Pll1 = 5U, +}; + +/*! @brief Restore sequence options + * Configure the restore_sequence of "flash_run_context_t" structure + */ +enum +{ + kRestoreSequence_None = 0U, + kRestoreSequence_HW_Reset = 1U, + kRestoreSequence_QPI_4_0xFFs = 2U, + kRestoreSequence_QPI_Mode_0x00 = 3U, + kRestoreSequence_8QPI_FF = 4U, + kRestoreSequence_Send_F0 = 5U, + kRestoreSequence_Send_66_99 = 6U, + kRestoreSequence_Send_6699_9966 = 7U, + kRestoreSequence_Send_06_FF = 8U, /*!< Adesto EcoXIP */ + kRestoreSequence_QPI_5_0xFFs = 9U, + kRestoreSequence_Send_QPI_8_0xFFs = 10U, + kRestoreSequence_Wakeup_0xAB = 11U, + kRestoreSequence_Wakeup_0xAB_54 = 12U, +}; + +/*! @brief Port mode options*/ +enum +{ + kFlashInstMode_ExtendedSpi = 0x00U, + kFlashInstMode_0_4_4_SDR = 0x01U, + kFlashInstMode_0_4_4_DDR = 0x02U, + kFlashInstMode_DPI_SDR = 0x21U, + kFlashInstMode_DPI_DDR = 0x22U, + kFlashInstMode_QPI_SDR = 0x41U, + kFlashInstMode_QPI_DDR = 0x42U, + kFlashInstMode_OPI_SDR = 0x81U, + kFlashInstMode_OPI_DDR = 0x82U, +}; + +/*! + * @name Support for init FLEXSPI NOR configuration + * @{ + */ +/*! @brief Flash Pad Definitions */ +enum +{ + kSerialFlash_1Pad = 1U, + kSerialFlash_2Pads = 2U, + kSerialFlash_4Pads = 4U, + kSerialFlash_8Pads = 8U, +}; + +/*! @brief FLEXSPI clock configuration type */ +enum +{ + kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */ + kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */ +}; + +/*! @brief FLEXSPI Read Sample Clock Source definition */ +enum _flexspi_read_sample_clk +{ + kFLEXSPIReadSampleClk_LoopbackInternally = 0U, + kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, + kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, + kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, +}; + +/*! @brief Flash Type Definition */ +enum +{ + kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ +}; + +/*! @brief Flash Configuration Command Type */ +enum +{ + kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */ + kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */ + kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */ + kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */ + kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */ + kDeviceConfigCmdType_Reset, /*!< Reset device command */ +}; + +/*! @brief Defintions for FLEXSPI Serial Clock Frequency */ +enum _flexspi_serial_clk_freq +{ + kFLEXSPISerialClk_NoChange = 0U, + kFLEXSPISerialClk_30MHz = 1U, + kFLEXSPISerialClk_50MHz = 2U, + kFLEXSPISerialClk_60MHz = 3U, + kFLEXSPISerialClk_75MHz = 4U, + kFLEXSPISerialClk_100MHz = 5U, +}; + +/*! @brief Misc feature bit definitions */ +enum +{ + kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */ + kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */ + kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */ + kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */ + kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */ + kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */ + kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */ + kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ +}; + +/*@}*/ + +/*! @brief Manufacturer ID */ +enum +{ + kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */ + kSerialFlash_Adesto_ManufacturerID = 0x1FU, /*!< Manufacturer ID of the Adesto Technologies serial flash*/ + kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */ + kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */ +}; + +/*! @brief + * Serial NOR configuration option + */ +typedef struct _serial_nor_config_option +{ + union + { + struct + { + uint32_t max_freq : 4; /*!< Maximum supported Frequency */ + uint32_t misc_mode : 4; /*!< miscellaneous mode */ + uint32_t quad_mode_setting : 4; /*!< Quad mode setting */ + uint32_t cmd_pads : 4; /*!< Command pads */ + uint32_t query_pads : 4; /*!< SFDP read pads */ + uint32_t device_type : 4; /*!< Device type */ + uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */ + uint32_t tag : 4; /*!< Tag, must be 0x0E */ + } B; + uint32_t U; + } option0; + + union + { + struct + { + uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */ + uint32_t status_override : 8; /*!< Override status register value during device mode configuration */ + uint32_t pinmux_group : 4; /*!< The pinmux group selection */ + uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */ + uint32_t drive_strength : 4; /*!< The Drive Strength of FLEXSPI Pads */ + uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 - */ + /*!< Parallel mode, 2 - Single Flash connected to Port B */ + } B; + uint32_t U; + } option1; + +} serial_nor_config_option_t; + +typedef union +{ + struct + { + uint8_t por_mode; + uint8_t current_mode; + uint8_t exit_no_cmd_sequence; + uint8_t restore_sequence; + } B; + uint32_t U; +} flash_run_context_t; + +/*! @brief + * FLEXSPI LUT Sequence structure + */ +typedef struct _lut_sequence +{ + uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */ + uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} flexspi_lut_seq_t; + +typedef struct +{ + uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */ + uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */ +} flexspi_dll_time_t; + +/*! @brief + * FLEXSPI Memory Configuration Block + */ +typedef struct _FlexSPIConfig +{ + uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ + uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */ + uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ + uint8_t csHoldTime; /*!< [0x00d-0x00d] CS hold time, default value: 3 */ + uint8_t csSetupTime; /*!< [0x00e-0x00e] CS setup time, default value: 3 */ + uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + Serial NAND, need to refer to datasheet */ + uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ + uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + Generic configuration, etc. */ + uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + DPI/QPI/OPI switch or reset command */ + flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + sequence number, [31:16] Reserved */ + uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */ + uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ + uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ + flexspi_lut_seq_t + configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ + uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */ + uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ + uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */ + uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + details */ + uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */ + uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ + uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot + Chapter for more details */ + uint8_t lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ + uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */ + uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */ + uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */ + uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */ + uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */ + uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */ + uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */ + flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ + uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + busy flag is 0 when flash device is busy */ + uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */ + flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */ + uint32_t dll0CrVal; //!> [0x1b0-0x1b3] Customizable DLL0CR setting */ + uint32_t dll1CrVal; //!> [0x1b4-0x1b7] Customizable DLL1CR setting */ + uint32_t reserved4[2]; /*!< [0x1b8-0x1bf] Reserved for future use */ +} flexspi_mem_config_t; + +/*! @brief + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */ + uint32_t pageSize; /*!< Page size of Serial NOR */ + uint32_t sectorSize; /*!< Sector size of Serial NOR */ + uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */ + uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */ + uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ + uint8_t reserved0[1]; /*!< Reserved for future use */ + uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */ + uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */ + uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */ + uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */ + uint32_t blockSize; /*!< Block size */ + uint32_t flashStateCtx; /*!< Flash State Context */ + uint32_t reserve2[10]; /*!< Reserved for future use */ +} flexspi_nor_config_t; + +typedef enum _flexspi_operation +{ + kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */ + kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */ + kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */ + kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */ + kFLEXSPIOperation_End = kFLEXSPIOperation_Read, +} flexspi_operation_t; + +/*! @brief FLEXSPI Transfer Context */ +typedef struct _flexspi_xfer +{ + flexspi_operation_t operation; /*!< FLEXSPI operation */ + uint32_t baseAddress; /*!< FLEXSPI operation base address */ + uint32_t seqId; /*!< Sequence Id */ + uint32_t seqNum; /*!< Sequence Number */ + bool isParallelModeEnable; /*!< Is a parallel transfer */ + uint32_t *txBuffer; /*!< Tx buffer */ + uint32_t txSize; /*!< Tx size in bytes */ + uint32_t *rxBuffer; /*!< Rx buffer */ + uint32_t rxSize; /*!< Rx size in bytes */ +} flexspi_xfer_t; + +/*! @brief + * FLEXSPI Clock Type + */ +typedef enum +{ + kFlexSpiClock_CoreClock, /*!< ARM Core Clock */ + kFlexSpiClock_AhbClock, /*!< AHB clock */ + kFlexSpiClock_SerialRootClock, /*!< Serial Root Clock */ + kFlexSpiClock_IpgClock, /*!< IPG clock */ +} flexspi_clock_type_t; + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t FLEXSPI_NorFlash_GetVersion(void); +/*! + * @brief Initialize Serial NOR devices via FLEXSPI + * + * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config); + +/*! + * @brief Program data to Serial NOR via FLEXSPI. + * + * This function programs the NOR flash memory with the dest address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst_addr A pointer to the desired flash memory to be programmed. + * NOTE: + * It is recommended that use page aligned access; + * If the dst_addr is not aligned to page,the driver automatically + * aligns address down with the page address. + * @param src A pointer to the source buffer of data that is to be programmed + * into the NOR flash. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src); + +/*! + * @brief Erase all the Serial NOR devices connected on FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config); + +/*! + * @brief Erase one sector specified by address + * + * This function erases one of NOR flash sectors based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param address The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,The driver automatically + * aligns address down with the sector address. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + +/*! + * @brief Erase one block specified by address + * + * This function erases one block of NOR flash based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use block-aligned access nor device; + * If dstAddr is not aligned with the block,The driver automatically + * aligns address down with the block address. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + +/*! + * @brief Get FLEXSPI NOR Configuration Block based on specified option. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param option A pointer to the storage Serial NOR Configuration Option Context. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, + flexspi_nor_config_t *config, + serial_nor_config_option_t *option); + +/*! + * @brief Erase Flash Region specified by address and length + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,the driver automatically + * aligns address down with the sector address. + * @param length The length, given in bytes to be erased. + * NOTE: + * It is recommended that use sector-aligned access nor device; + * If length is not aligned with the sector,the driver automatically + * aligns up with the sector. + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + +/*! + * @brief Read data from Serial NOR via FLEXSPI. + * + * This function read the NOR flash memory with the start address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst A pointer to the dest buffer of data that is to be read from the NOR flash. + * NOTE: + * It is recommended that use page aligned access; + * If the dstAddr is not aligned to page,the driver automatically + * aligns address down with the page address. + * @param start The start address of the desired NOR flash memory to be read. + * @param lengthInBytes The length, given in bytes to be read. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + * @retval #kStatus_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval #kStatus_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval #kStatus_FLEXSPI_DeviceTimeout the device timeout + */ +status_t FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + +/*! + * @brief FLEXSPI command + * + * This function is used to perform the command write sequence to the NOR device. + * + * @param instance storage the index of FLEXSPI. + * @param xfer A pointer to the storage FLEXSPI Transfer Context. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer); + +/*! + * @brief Configure FLEXSPI Lookup table + * + * @param instance storage the index of FLEXSPI. + * @param seqIndex storage the sequence Id. + * @param lutBase A pointer to the look-up-table for command sequences. + * @param seqNumber storage sequence number. + * + * @retval kStatus_Success Api was executed succesfuly. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber); + +/*! + * @brief Set the clock source for FLEXSPI NOR + * + * @param clockSource Clock source for FLEXSPI NOR. See to "_flexspi_nor_clock_source". + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + */ +status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource); + +/*! + * @brief Configure the FlexSPI clock. + * + *The API is used for configuring the FlexSPI clock. + * + * @param instance storage the index of FLEXSPI. + * @param freqOption storage FlexSPIFlexSPI flash serial clock frequency. + * @param sampleClkMode storage the FlexSPI clock configuration type. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument A invalid argument is provided. + */ +void FLEXSPI_NorFlash_ConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); + +#ifdef __cplusplus +} +#endif + +#endif /*! FSL_FLEXSPI_NOR_FLASH_H__ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/src/fsl_flash.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/src/fsl_flash.c new file mode 100644 index 0000000000..d2a2edeada --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/flash/src/fsl_flash.c @@ -0,0 +1,567 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flashiap" +#endif + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/*! + * @name flash, ffr, flexspi nor flash Structure + * @{ + */ + +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*isFlashAreaReadable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); + status_t (*isFlashAreaModifiable)(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes); +} function_command_option_t; + +/*! + * @brief Structure of version property. + * + * @ingroup bl_core + */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number. */ + /* Flash driver */ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + const uint32_t reserved0[3]; + + /*!< Flash FFR driver */ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_cust_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t reserved1; + status_t reserved2; + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + const uint32_t reserved3; + status_t (*flash_get_cust_keystore)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*flash_deinit)(flash_config_t *config); +} flash_driver_interface_t; + +/*! @brief FLEXSPI Flash driver API Interface */ +typedef struct +{ + uint32_t version; + status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src); + status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); + status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); + status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); + status_t (*set_clock_source)(uint32_t clockSrc); + void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode); + status_t (*partial_program)( + uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src, uint32_t length); +} flexspi_nor_flash_driver_t; + +/* !@brief EFUSE driver API Interface */ +typedef struct +{ + standard_version_t version; + status_t (*init)(void); + status_t (*deinit)(void); + status_t (*read)(uint32_t addr, uint32_t *data); + status_t (*program)(uint32_t addr, uint32_t data); +} efuse_driver_t; + +/*! @}*/ + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const flash_driver_interface_t *flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const efuse_driver_t *efuseDriver; /*!< eFuse driver API */ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************** + * Internal Flash driver API + *******************************************************************************/ +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ +status_t FLASH_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_init(config); +} + +/*! + * @brief De-Initializes the global flash properties structure members. + * + * This API De-initializes the FLASH default parameters and related FLASH clock for the FLASH and FMC. + */ +status_t FLASH_Deinit(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_deinit(config); +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ +status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase(config, start, lengthInBytes, key); +} + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + */ +status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program(config, start, src, lengthInBytes); +} + +/*! + * @brief Verifies an erasure of the desired flash area at a specified margin level. + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * to the specified read margin level. + */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_read(config, start, dest, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ +status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program(config, start, lengthInBytes, expectedData, + failedAddress, failedData); +} + +/*! + * @brief Returns the desired flash property. + */ +status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_property(config, whichProperty, value); +} + +status_t FLASH_GetCustKeyStore(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); +} + +#if defined(BL_FEATURE_HAS_BUS_CRYPTO_ENGINE) && BL_FEATURE_HAS_BUS_CRYPTO_ENGINE +status_t FLASH_ErasePrologue(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_erase_with_checker(config, start, lengthInBytes, key); +} + +status_t FLASH_ProgramPrologue(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_program_with_checker(config, start, src, lengthInBytes); +} + +status_t FLASH_VerifyProgramPrologue(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_verify_program_with_checker( + config, start, lengthInBytes, expectedData, failedAddress, failedData); +} + +#endif // BL_FEATURE_HAS_BUS_CRYPTO_ENGINE + +#if defined(FSL_FEATURE_SYSCON_HAS_FLASH_HIDING) && (FSL_FEATURE_SYSCON_HAS_FLASH_HIDING == 1) +/*! + * @brief Validates the given address range is loaded in the flash hiding region. + */ +status_t FLASH_IsFlashAreaReadable(flash_config_t *config, uint32_t startAddress, uint32_t lengthInBytes) +{ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x130366f9u; + return runCmdFuncOption.isFlashAreaReadable(config, startAddress, lengthInBytes); +} +#endif + +/******************************************************************************** + * fsl iap ffr CODE + *******************************************************************************/ + +/*! + * @brief Initializes the global FFR properties structure members. + */ +status_t FFR_Init(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_init(config); +} + +/*! + * @brief Enable firewall for all flash banks. + */ +status_t FFR_Lock(flash_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_lock(config); +} + +/*! + * @brief APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ +status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_factory_page_write(config, page_data, seal_part); +} + +/*! + * @brief See fsl_iap_ffr.h for documentation of this function. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_uuid(config, uuid); +} + +/*! + * @brief APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ +status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_data(config, pData, offset, len); +} + +/*! + * @brief This routine writes the 3 pages allocated for Key store data. + */ +status_t FFR_CustKeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_cust_keystore_write(config, pKeyStore); +} + +/*! + * @brief APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ +status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_infield_page_write(config, page_data, valid_len); +} + +/*! + * @brief APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ +status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->ffr_get_customer_infield_data(config, pData, offset, len); +} + +/*! + * @brief The API is used for getting the customer key store data from the customer key store region(0x3e400 �C + * 0x3e600), and the API should be called after the FLASH_Init and FFR_Init. + */ +status_t FFR_GetCustKeystoreData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flashDriver->flash_get_cust_keystore(config, pData, offset, len); +} + +/******************************************************************************** + * FlexSPI NOR FLASH Driver API + *******************************************************************************/ +/*! + * @brief Initialize Serial NOR devices via FLEXSPI. + */ +status_t FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->init(instance, config); +} + +/*! + * @brief Program data to Serial NOR via FlexSPI + */ +status_t FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dstAddr, + const uint32_t *src) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->page_program(instance, config, dstAddr, src); +} + +/*! + * @brief Erase all the Serial NOR devices connected on FlexSPI + */ +status_t FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_all(instance, config); +} + +/*! + * @brief Erase Flash Region specified by address and length + */ +status_t FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase(instance, config, start, length); +} + +/*! + * @brief Erase one sector specified by address + */ +status_t FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_sector(instance, config, address); +} + +/*! + * @brief Erase one block specified by address + */ +status_t FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->erase_block(instance, config, address); +} + +/*! + * @brief Get FlexSPI NOR driver version + */ +uint32_t FLEXSPI_NorFlash_GetVersion(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->version; +} + +/*! + * @brief Get FlexSPI NOR Configuration Block based on specified option + */ +status_t FLEXSPI_NorFlash_GetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->get_config(instance, config, option); +} + +/*! + * @brief Read data from Serial NOR + */ +status_t FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->read(instance, config, dst, start, bytes); +} + +/*! + * @brief Perform FlexSPI command + */ +status_t FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->xfer(instance, xfer); +} + +/*! + * @brief Configure FlexSPI Lookup table + */ +status_t FLEXSPI_NorFlash_UpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->update_lut(instance, seqIndex, lutBase, numberOfSeq); +} + +/*! + * @brief Set flexspi clock source + */ +status_t FLEXSPI_NorFlash_SetClockSource(uint32_t clockSource) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->set_clock_source(clockSource); +} + +/*! + * @brief config flexspi clock + */ +void FLEXSPI_NorFlash_ConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->flexspiNorDriver->config_clock(instance, freqOption, sampleClkMode); +} + +/******************************************************************************** + * EFUSE driver API + *******************************************************************************/ + +/*! + * @brief Initialize EFUSE controller. + */ +status_t EFUSE_Init(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->init(); +} + +/*! + * @brief De-Initialize EFUSE controller. + */ +status_t EFUSE_Deinit(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->deinit(); +} + +/*! + * @brief Read Fuse value from eFuse word. + */ +status_t EFUSE_Read(uint32_t addr, uint32_t *data) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->efuseDriver->read(addr, data); +} + +/*! + * @brief Program value to eFuse block. + */ +status_t EFUSE_Program(uint32_t addr, uint32_t data) +{ + assert(BOOTLOADER_API_TREE_POINTER); + status_t status; + bool is_hvd_enabled = false; + + /* Disable SYS_HVD */ + if (0 != (SPC0->ACTIVE_CFG & SPC_ACTIVE_CFG_SYS_HVDE_MASK)) + { + is_hvd_enabled = true; + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + /* Call ROM API to program efuse */ + status = BOOTLOADER_API_TREE_POINTER->efuseDriver->program(addr, data); + + /* Bring VDD_SYS back to 1.8v */ + SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK; + + /* Wait for voltage to settle */ + SDK_DelayAtLeastUs(5000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Enable SYS_HVD back */ + if (is_hvd_enabled) + { + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_mem_interface.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_mem_interface.h new file mode 100644 index 0000000000..98147b6baf --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_mem_interface.h @@ -0,0 +1,379 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_MEM_INTERFACE_H_ +#define FSL_MEM_INTERFACE_H_ + +#include "fsl_sbloader.h" +#include "fsl_common.h" + +/*! + * @addtogroup memory_interface + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Bit mask for device ID. */ +#define DEVICE_ID_MASK (0xffU) +/*! @brief Bit position of device ID. */ +#define DEVICE_ID_SHIFT 0U +/*! @brief Bit mask for group ID. */ +#define GROUP_ID_MASK (0xf00U) +/*! @brief Bit position of group ID. */ +#define GROUP_ID_SHIFT 8U + +/*! @brief Construct a memory ID from a given group ID and device ID. */ +#define MAKE_MEMORYID(group, device) \ + ((((group) << GROUP_ID_SHIFT) & GROUP_ID_MASK) | (((device) << DEVICE_ID_SHIFT) & DEVICE_ID_MASK)) +/*! @brief Get group ID from a given memory ID. */ +#define GROUPID(memoryId) (((memoryId)&GROUP_ID_MASK) >> GROUP_ID_SHIFT) + +/*! @brief Get device ID from a given memory ID. */ +#define DEVICEID(memoryId) (((memoryId)&DEVICE_ID_MASK) >> DEVICE_ID_SHIFT) + +/*! @brief Memory group definition. */ +enum +{ + kMemoryGroup_Internal = 0U, /*!< Memory belongs internal 4G memory region. */ + kMemoryGroup_External = 1U, /*!< Memory belongs external memory region. */ +}; + +/*! @brief Memory device ID definition. */ +enum +{ + /* Memory ID bitfiled definition. + | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | Reserved | INT/EXT | Type | Sub-Type | + | | 0: INT | INT: | | + | | 1: EXT | 0: NorFlash0 | 0: Internal Flash(FTFX) | + | | | | 1: QSPI | + | | | | 4: IFR | + | | | | 5: LPC FFR | + | | | | 8: SEMC | + | | | | 9: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: ExecuteOnlyRegion | 0: Internal Flash(FTFX) | + | | | | others: Unused | + | | | | | + | | | others: Unused | | + | | | | | + | | | EXT: | | + | | | 0: NandFlash | 0: SEMC | + | | | | 1: FlexSPI | + | | | | others: Unused | + | | | | | + | | | 1: NorFlash/EEPROM | 0: LPSPI | + | | | | 1: LPI2C | + | | | | others: Unused | + | | | | | + | | | 2: SD/SDHC/SDXC/MMC/eMMC | 0: uSDHC SD | + | | | | 1: uSDHC MMC | + | | | | others: Unused | + | | | others: Unused | | + + INT : Internal 4G memory, including internal memory modules, and XIP external memory modules. + EXT : Non-XIP external memory modules. + */ + kMemoryInternal = MAKE_MEMORYID(kMemoryGroup_Internal, 0U), /*!< Internal memory (include all on chip memory) */ + kMemoryQuadSpi0 = MAKE_MEMORYID(kMemoryGroup_Internal, 1U), /*!< Qsuad SPI memory 0 */ + kMemoryIFR0 = + MAKE_MEMORYID(kMemoryGroup_Internal, 4U), /*!< Nonvolatile information register 0. Only used by SB loader. */ + kMemoryFFR = MAKE_MEMORYID(kMemoryGroup_Internal, 5U), /*!< LPCc040hd flash FFR region. */ + kMemorySemcNor = MAKE_MEMORYID(kMemoryGroup_Internal, 8U), /*!< SEMC Nor memory */ + kMemoryFlexSpiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 9U), /*!< Flex SPI Nor memory */ + kMemorySpifiNor = MAKE_MEMORYID(kMemoryGroup_Internal, 0xAU), /*!< SPIFI Nor memory */ + kMemoryFlashExecuteOnly = MAKE_MEMORYID(kMemoryGroup_Internal, 0x10U), /*!< Execute-only region on internal Flash */ + + kMemorySemcNand = MAKE_MEMORYID(kMemoryGroup_External, 0U), /*!< SEMC NAND memory */ + kMemorySpiNand = MAKE_MEMORYID(kMemoryGroup_External, 1U), /*!< SPI NAND memory */ + kMemorySpiNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x10U), /*!< SPI NOR/EEPROM memory */ + kMemoryI2cNorEeprom = MAKE_MEMORYID(kMemoryGroup_External, 0x11U), /*!< I2C NOR/EEPROM memory */ + kMemorySDCard = MAKE_MEMORYID(kMemoryGroup_External, 0x20U), /*!< eSD, SD, SDHC, SDXC memory Card */ + kMemoryMMCCard = MAKE_MEMORYID(kMemoryGroup_External, 0x21U), /*!< MMC, eMMC memory Card */ +}; + +/*! @brief Bootloader status group numbers. + * + * @ingroup bl_core + */ +enum +{ + kStatusGroup_Bootloader = 100, /*!< Bootloader status group number (100). */ + kStatusGroup_MemoryInterface = 102, /*!< Memory interface status group number (102). */ +}; + +/*! @brief Memory interface status codes. */ +enum +{ + kStatusMemoryRangeInvalid = MAKE_STATUS(kStatusGroup_MemoryInterface, 0), + kStatusMemoryReadFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 1), + kStatusMemoryWriteFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 2), + kStatusMemoryCumulativeWrite = MAKE_STATUS(kStatusGroup_MemoryInterface, 3), + kStatusMemoryAppOverlapWithExecuteOnlyRegion = MAKE_STATUS(kStatusGroup_MemoryInterface, 4), + kStatusMemoryNotConfigured = MAKE_STATUS(kStatusGroup_MemoryInterface, 5), + kStatusMemoryAlignmentError = MAKE_STATUS(kStatusGroup_MemoryInterface, 6), + kStatusMemoryVerifyFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 7), + kStatusMemoryWriteProtected = MAKE_STATUS(kStatusGroup_MemoryInterface, 8), + kStatusMemoryAddressError = MAKE_STATUS(kStatusGroup_MemoryInterface, 9), + kStatusMemoryBlankCheckFailed = MAKE_STATUS(kStatusGroup_MemoryInterface, 10), + kStatusMemoryBlankPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 11), + kStatusMemoryProtectedPageReadDisallowed = MAKE_STATUS(kStatusGroup_MemoryInterface, 12), + kStatusMemoryFfrSpecRegionWriteBroken = MAKE_STATUS(kStatusGroup_MemoryInterface, 13), + kStatusMemoryUnsupportedCommand = MAKE_STATUS(kStatusGroup_MemoryInterface, 14), +}; + +/*! @brief Bootloader status codes. */ +enum +{ + kStatus_UnknownCommand = MAKE_STATUS(kStatusGroup_Bootloader, 0), + kStatus_SecurityViolation = MAKE_STATUS(kStatusGroup_Bootloader, 1), + kStatus_AbortDataPhase = MAKE_STATUS(kStatusGroup_Bootloader, 2), + kStatus_Ping = MAKE_STATUS(kStatusGroup_Bootloader, 3), + kStatus_NoResponse = MAKE_STATUS(kStatusGroup_Bootloader, 4), + kStatus_NoResponseExpected = MAKE_STATUS(kStatusGroup_Bootloader, 5), + kStatus_CommandUnsupported = MAKE_STATUS(kStatusGroup_Bootloader, 6), +}; + +/*! + * @brief Interface to memory operations. + * + * This is the main abstract interface to all memory operations. + */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer, uint32_t memoryId); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer, uint32_t memoryId); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*finalize)(void); + status_t (*erase)(uint32_t address, uint32_t length, uint32_t memoryId); +} memory_interface_t; + +/*! @brief Interface to memory operations for one region of memory. */ +typedef struct +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +//! @brief Structure of a memory map entry. +typedef struct +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +/*! @brief Structure of version property. */ +typedef union StandardVersion +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ +} standard_version_t; + +/*! @brief API initialization data structure */ +typedef struct kb_api_parameter_struct +{ + uint32_t allocStart; + uint32_t allocSize; +} kp_api_init_param_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void); + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx); + +/*! + * @brief Initialize memory interface. + * + * @retval #kStatus_Fail + * @retval #kStatus_Success + */ +status_t MEM_Init(api_core_context_t *coreCtx); + +/*! + * @brief Configure memory interface + * + * @param config A pointer to the storage for the driver runtime state. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport +*/ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId); + +/*! + * @brief Write memory. + * + * @param address The start address of the desired flash memory to be programmed. + For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param buffer A pointer to the source buffer of data that is to be programmed into the flash. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatus_FLASH_CompareError + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId); + +/*! + * @brief Fill memory with a word pattern. + * + * @param address The start address of the desired flash memory to be programmed. + * For internal flash the address need to be 512bytes-aligned. + * @param length Number of bytes to be programmed. + * @param pattern The data to be written into the specified memory area. + * + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_Success + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId); + +/*! + * @brief Flush memory. + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatusMemoryCumulativeWrite + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ReadHidingAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + */ +status_t MEM_Flush(api_core_context_t *coreCtx); + +/*! + * @brief Erase memory. + * + * @param address The start address of the desired flash memory to be erased. + * @param length Number of bytes to be read. + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatusMemoryAddressError + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatus_Fail + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatusMemoryNotConfigured + * @retval #kStatusMemoryVerifyFailed + + */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId); + +/*! + * @brief Erase entire memory based on memoryId + * + * @param memoryId Indicates the index of the memory type. Please refer to "Memory group definition" + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_FLASH_InvalidArgument + * @retval #kStatus_FLASH_AlignmentError + * @retval #kStatus_FLASH_Success + * @retval #kStatus_FLASH_AddressError + * @retval #kStatus_FLASH_EraseKeyError + * @retval #kStatus_FLASH_CommandFailure + * @retval #kStatus_FLASH_CommandNotSupported + * @retval #kStatus_FLASH_EccError + * @retval #kStatus_FLASH_RegulationLoss + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryVerifyFailed + * @retval #kStatusMemoryNotConfigured + * @retval #kStatus_InvalidArgument + */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_MEM_INTERFACE_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_sbloader.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_sbloader.h new file mode 100644 index 0000000000..c2862e73db --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_sbloader.h @@ -0,0 +1,373 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_SBLOADER_H_ +#define FSL_SBLOADER_H_ + +#include "fsl_flash.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_sbloader_v3.h" +#include "fsl_common.h" +/*! + * @addtogroup sbloader + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Determines the version of SB loader implementation (1: sb1.0; 2: sb2.0; 3.1: sb3.1) */ +#define SB_FILE_MAJOR_VERSION (3) +#define SB_FILE_MINOR_VERSION (1) + +/*! @brief Bootloader status group numbers */ +#define kStatusGroup_SBLoader (101U) + +/*! @brief Contiguous RAM region count */ +#define RAM_REGION_COUNT (2U) + +/*! @brief Contiguous FLASH region count */ +#define FLASH_REGION_COUNT (1U) + +/*! @brief Contiguous FFR region count */ +#define FFR_REGION_COUNT (1U) + +/*! @brief Memory Interface count */ +#define MEM_INTERFACE_COUNT (4U) + +/*! @brief Contiguous FLEXSPINOR meomry count */ +#define FLEXSPINOR_REGION_COUNT (1U) + +/*! @brief SB loader status codes.*/ +enum +{ + kStatusRomLdrSectionOverrun = MAKE_STATUS(kStatusGroup_SBLoader, 0), + kStatusRomLdrSignature = MAKE_STATUS(kStatusGroup_SBLoader, 1), + kStatusRomLdrSectionLength = MAKE_STATUS(kStatusGroup_SBLoader, 2), + kStatusRomLdrUnencryptedOnly = MAKE_STATUS(kStatusGroup_SBLoader, 3), + kStatusRomLdrEOFReached = MAKE_STATUS(kStatusGroup_SBLoader, 4), + kStatusRomLdrChecksum = MAKE_STATUS(kStatusGroup_SBLoader, 5), + kStatusRomLdrCrc32Error = MAKE_STATUS(kStatusGroup_SBLoader, 6), + kStatusRomLdrUnknownCommand = MAKE_STATUS(kStatusGroup_SBLoader, 7), + kStatusRomLdrIdNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 8), + kStatusRomLdrDataUnderrun = MAKE_STATUS(kStatusGroup_SBLoader, 9), + kStatusRomLdrJumpReturned = MAKE_STATUS(kStatusGroup_SBLoader, 10), + kStatusRomLdrCallFailed = MAKE_STATUS(kStatusGroup_SBLoader, 11), + kStatusRomLdrKeyNotFound = MAKE_STATUS(kStatusGroup_SBLoader, 12), + kStatusRomLdrSecureOnly = MAKE_STATUS(kStatusGroup_SBLoader, 13), + kStatusRomLdrResetReturned = MAKE_STATUS(kStatusGroup_SBLoader, 14), + + kStatusRomLdrRollbackBlocked = MAKE_STATUS(kStatusGroup_SBLoader, 15), + kStatusRomLdrInvalidSectionMacCount = MAKE_STATUS(kStatusGroup_SBLoader, 16), + kStatusRomLdrUnexpectedCommand = MAKE_STATUS(kStatusGroup_SBLoader, 17), + kStatusRomLdrBadSBKEK = MAKE_STATUS(kStatusGroup_SBLoader, 18), + kStatusRomLdrPendingJumpCommand = MAKE_STATUS(kStatusGroup_SBLoader, 19), +}; + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define BYTES_PER_CHUNK 16 + +#define SB_SECTION_COUNT_MAX 8 + +/*! @brief Boot image signature in 32-bit little-endian format "PMTS" */ +#define BOOT_SIGNATURE 0x504d5453 + +/*! @brief Boot image signature in 32-bit little-endian format "ltgs" */ +#define BOOT_SIGNATURE2 0x6c746773 + +/*! @brief These define file header flags */ +#define FFLG_DISPLAY_PROGRESS 0x0001 + +/*! @brief These define section header flags */ +#define SFLG_SECTION_BOOTABLE 0x0001 + +/*! @brief These define boot command flags */ +#define CFLG_LAST_TAG 0x01 + +/*! @brief ROM_ERASE_CMD flags */ +#define ROM_ERASE_ALL_MASK 0x01 +#define ROM_ERASE_ALL_UNSECURE_MASK 0x02 + +/*! @brief ROM_JUMP_CMD flags */ +#define ROM_JUMP_SP_MASK 0x02 + +/*! @brief Memory device id shift at sb command flags */ +#define ROM_MEM_DEVICE_ID_SHIFT 0x8 + +/*! @brief Memory device id mask */ +#define ROM_MEM_DEVICE_ID_MASK 0xff00 + +/*! @brief Memory group id shift at sb command flags */ +#define ROM_MEM_GROUP_ID_SHIFT 0x4 + +/*! @brief Memory group id flags mask */ +#define ROM_MEM_GROUP_ID_MASK 0xf0 + +/*! @brief ROM_PROG_CMD flags */ +#define ROM_PROG_8BYTE_MASK 0x01 + +/*! @brief These define the boot command tags */ +#define ROM_NOP_CMD 0x00 +#define ROM_TAG_CMD 0x01 +#define ROM_LOAD_CMD 0x02 +#define ROM_FILL_CMD 0x03 +#define ROM_JUMP_CMD 0x04 +#define ROM_CALL_CMD 0x05 +#define ROM_MODE_CMD 0x06 +#define ROM_ERASE_CMD 0x07 +#define ROM_RESET_CMD 0x08 +#define ROM_MEM_ENABLE_CMD 0x09 +#define ROM_PROG_CMD 0x0a +#define ROM_FW_VER_CHK 0x0b + +#if SB_FILE_MAJOR_VERSION == 2 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V2_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V2_CMD_SET_IN_REC_MODE) +#elif SB_FILE_MAJOR_VERSION == 3 +#define SBLOADER_CMD_SET_IN_ISP_MODE (SBLOADER_V3_CMD_SET_IN_ISP_MODE) +#define SBLOADER_CMD_SET_IN_REC_MODE (SBLOADER_V3_CMD_SET_IN_REC_MODE) +#endif + +/*! @brief Plugin return codes */ +#define ROM_BOOT_SECTION_ID 1 +#define ROM_BOOT_IMAGE_ID 2 + +enum _fw_version_check_option +{ + kRomLdr_FwCheckOption_SecureVersion = 0x0U, + kRomLdr_FwCheckOption_NonSecureVersion = 0x1U, +}; + +typedef uint8_t chunk_t[BYTES_PER_CHUNK]; + +/*! @brief Boot command definition */ +typedef struct _boot_cmd +{ + uint8_t checksum; /*!< 8-bit checksum over command chunk */ + uint8_t tag; /*!< command tag (identifier) */ + uint16_t flags; /*!< command flags (modifier) */ + uint32_t address; /*!< address argument */ + uint32_t count; /*!< count argument */ + uint32_t data; /*!< data argument */ +} boot_cmd_t; + +/*! @brief Definition for boot image file header chunk 1 */ +typedef struct _boot_hdr1 +{ + uint32_t hash; /*!< last 32-bits of SHA-1 hash */ + uint32_t signature; /*!< must equal "STMP" */ + uint8_t major; /*!< major file format version */ + uint8_t minor; /*!< minor file format version */ + uint16_t fileFlags; /*!< global file flags */ + uint32_t fileChunks; /*!< total chunks in the file */ +} boot_hdr1_t; + +/*! @brief Definition for boot image file header chunk 2 */ +typedef struct _boot_hdr2 +{ + uint32_t bootOffset; /*!< chunk offset to the first boot section */ + uint32_t bootSectID; /*!< section ID of the first boot section */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint16_t keyOffset; /*!< chunk offset to the key dictionary */ + uint16_t hdrChunks; /*!< number of chunks in the header */ + uint16_t sectCount; /*!< number of sections in the image */ +} boot_hdr2_t; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context ldr_Context_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_t)(ldr_Context_t *context); + +/*! @brief Jump command function pointer definition. */ +typedef status_t (*pJumpFnc_t)(uint32_t parameter); + +/*! @brief Call command function pointer definition. */ +typedef status_t (*pCallFnc_t)(uint32_t parameter, uint32_t *func); + +/*! @brief State information for the CRC32 algorithm. */ +typedef struct Crc32Data +{ + uint32_t currentCrc; /*!< Current CRC value. */ + uint32_t byteCountCrc; /*!< Number of bytes processed. */ +} crc32_data_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context +{ + pLdrFnc_t Action; /*!< pointer to loader action function */ + uint32_t fileChunks; /*!< chunks remaining in file */ + uint32_t sectChunks; /*!< chunks remaining in section */ + uint32_t bootSectChunks; /*!< number of chunks we need to complete the boot section */ + uint32_t receivedChunks; /*!< number of chunks we need to complete the boot section */ + uint16_t fileFlags; /*!< file header flags */ + uint16_t keyCount; /*!< number of keys in the key dictionary */ + uint32_t objectID; /*!< ID of the current boot section or image */ + crc32_data_t crc32; /*!< crc calculated over load command payload */ + uint8_t *src; /*!< source buffer address */ + chunk_t initVector; /*!< decryption initialization vector */ + chunk_t dek; /*!< chunk size DEK if the image is encrypted */ + chunk_t scratchPad; /*!< chunk size scratch pad area */ + boot_cmd_t bootCmd; /*!< current boot command */ + uint32_t skipCount; /*!< Number of chunks to skip */ + bool skipToEnd; /*!< true if skipping to end of file */ + + // extended for SB 2.0 + uint32_t nonce[4]; + uint32_t keyBlobBlock; + uint32_t keyBlobBlockCount; + uint8_t *keyBlobBuffer; + uint32_t offsetSignatureBytes; /*!< offset to signagure block header in bytesn */ + uint8_t *headerBuffer; +}; + +typedef struct soc_memory_map_struct +{ + struct + { + uint32_t start; + uint32_t end; + } ramRegions[RAM_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } flashRegions[FLASH_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } ffrRegions[FFR_REGION_COUNT]; + struct + { + uint32_t start; + uint32_t end; + } flexspiNorRegions[FLEXSPINOR_REGION_COUNT]; +} soc_mem_regions_t; + +typedef struct arena_context +{ + uint32_t start; + uint32_t end; + uint32_t nextAddr; +} arena_context_t; + +/*! @brief Memory region information table */ +typedef struct mem_region +{ + uint32_t start; + uint32_t end; +} mem_region_t; + +/*! @brief Memory Attribute Structure */ +typedef struct memory_attribute_struct +{ + uint32_t memId; + uint32_t regionCount; + mem_region_t *memRegions; + void *context; +} mem_attribute_t; + +/*! @brief Memory context structure */ +typedef struct memory_context_struct +{ + status_t (*flush)(mem_attribute_t *attr); + mem_attribute_t *attr; +} mem_context_t; + +/*! @brief Memory region interface structure */ +typedef struct api_memory_region_interface +{ + status_t (*init)(mem_attribute_t *attr); +#if ROM_API_HAS_FEATURE_MEM_READ + status_t (*read)(mem_attribute_t *attr, uint32_t addr, uint32_t leth, uint8_t *buf); +#endif + status_t (*write)(mem_attribute_t *attr, uint32_t addr, uint32_t len, const uint8_t *buf); + status_t (*fill)(mem_attribute_t *attr, uint32_t addr, uint32_t len, uint32_t pattern); + status_t (*flush)(mem_attribute_t *attr); + status_t (*erase)(mem_attribute_t *attr, uint32_t addr, uint32_t len); + status_t (*config)(mem_attribute_t *attr, uint32_t *buf); + status_t (*erase_all)(mem_attribute_t *attr); + status_t (*alloc_ctx)(arena_context_t *ctx, mem_attribute_t *attr, void *miscParams); +} api_memory_region_interface_t; + +/*! @brief Memory entry data structure */ +typedef struct memory_map_entry +{ + mem_attribute_t *memoryAttribute; + const api_memory_region_interface_t *memoryInterface; +} api_memory_map_entry_t; + +/*! @brief The API context structure */ +typedef struct api_core_context +{ + soc_mem_regions_t memRegions; + arena_context_t arenaCtx; + flash_config_t flashConfig; + flexspi_nor_config_t flexspinorCfg; + mem_context_t memCtx; + ldr_Context_v3_t *sbloaderCtx; + nboot_context_t *nbootCtx; + uint8_t *sharedBuf; + api_memory_map_entry_t memEntries[MEM_INTERFACE_COUNT]; +} api_core_context_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Perform the Sbloader runtime environment initialization + * This API is used for initializing the sbloader state machine before calling + * the api_sbloader_pump. This API should be called after the iap_api_init API. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Init(api_core_context_t *ctx); + +/*! + * @brief Handle the SB data stream + * This API is used for handling the secure binary(SB3.1 format) data stream, + * which is used for image update, lifecycle advancing, etc. + * This API should be called after the iap_api_init and api_sbloader_init APIs. + + * @param ctx Pointer to IAP API core context structure. + * @param data Pointer to source data that is the sb file buffer data. + * @param length The size of the process buffer data. + * + * @retval #kStatus_Success Api was executed succesfuly. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_Fail API execution failed. + */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length); + +/*! + * @brief Finish the sbloader handling + * The API is used for finalizing the sbloader operations. + * + * @param ctx Pointer to IAP API core context structure. + * + * @retval #kStatus_Success Api was executed succesfuly. + */ +status_t Sbloader_Finalize(api_core_context_t *ctx); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_SBLOADER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_sbloader_v3.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_sbloader_v3.h new file mode 100644 index 0000000000..795d8f19e7 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/fsl_sbloader_v3.h @@ -0,0 +1,271 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SBLOADER_V3_H_ +#define FSL_SBLOADER_V3_H_ + +#include + +#include "fsl_nboot_hal.h" + +/*! @addtogroup sbloader */ +/*! @{ */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! + * @brief Defines the number of bytes in a cipher block (chunk). This is dictated by + * the encryption algorithm. + */ +#define SB3_BYTES_PER_CHUNK 16 + +typedef uint8_t chunk_v3_t[SB3_BYTES_PER_CHUNK]; + +typedef struct _ldr_buf ldr_buf_t; + +struct _ldr_buf +{ + chunk_v3_t data; + uint32_t fillPosition; +}; + +/*! @brief Provides forward reference to the loader context definition. */ +typedef struct _ldr_Context_v3 ldr_Context_v3_t; + +/*! @brief Function pointer definition for all loader action functions. */ +typedef status_t (*pLdrFnc_v3_t)(ldr_Context_v3_t *content); + +/*! @brief sb3 section definitions */ +/*! @brief section type */ +typedef enum _sectionType +{ + kSectionNone = 0, /*!< end or invalid */ + kSectionDataRange = 1, + kSectionDiffUpdate = 2, + kSectionDDRConfig = 3, + kSectionRegister = 4, +} section_type_t; + +#define SB3_DATA_RANGE_HEADER_FLAGS_ERASE_MASK (0x1u) /*!< bit 0 */ +#define SB3_DATA_RANGE_HEADER_FLAGS_LOAD_MASK (0x2u) /*!< bit 1 */ + +/*! @brief section data range structure */ +typedef struct range_header +{ + uint32_t tag; + uint32_t startAddress; + uint32_t length; + uint32_t cmd; +} sb3_data_range_header_t; + +typedef struct range_header_expansion +{ + uint32_t memoryId; + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb3_data_range_expansion_t; + +typedef struct copy_memory_expansion +{ + uint32_t destAddr; + uint32_t memoryIdFrom; + uint32_t memoryIdTo; + uint32_t pad; +} sb3_copy_memory_expansion_t; + +typedef struct copy +{ + sb3_data_range_header_t header; + sb3_copy_memory_expansion_t expansion; +} sb3_copy_memory_t; + +typedef struct load_keyblob +{ + uint32_t tag; + uint16_t offset; + uint16_t keyWrapId; + uint32_t length; + uint32_t cmd; +} sb3_load_keyblob_t; + +typedef struct fill_memory_expansion +{ + uint32_t pattern; /*!< word to be used as pattern */ + uint32_t pad0; + uint32_t pad1; + uint32_t pad2; +} sb3_fill_memory_expansion_t; + +typedef struct fill_memory +{ + sb3_data_range_header_t header; + sb3_fill_memory_expansion_t arg; +} sb3_fill_memory_t; + +typedef struct config_memory +{ + uint32_t tag; + uint32_t memoryId; + uint32_t address; /*!< address of config blob */ + uint32_t cmd; +} sb3_config_memory_t; + +enum +{ + kFwVerChk_Id_none = 0, + kFwVerChk_Id_nonsecure = 1, + kFwVerChk_Id_secure = 2, +}; + +typedef struct fw_ver_check +{ + uint32_t tag; + uint32_t version; + uint32_t id; + uint32_t cmd; +} sb3_fw_ver_check_t; + +/*! @brief sb3 DATA section header format */ +typedef struct section_header +{ + uint32_t sectionUid; + uint32_t sectionType; + uint32_t length; + uint32_t _pad; +} sb3_section_header_t; + +/*! @brief loader command enum */ +typedef enum _loader_command_sb3 +{ + kSB3_CmdInvalid = 0, + kSB3_CmdErase = 1, + kSB3_CmdLoad = 2, + kSB3_CmdExecute = 3, + kSB3_CmdCall = 4, + kSB3_CmdProgramFuse = 5, + kSB3_CmdProgramIFR = 6, + kSB3_CmdLoadCmac = 7, + kSB3_CmdCopy = 8, + kSB3_CmdLoadHashLocking = 9, + kSB3_CmdLoadKeyBlob = 10, + kSB3_CmdConfigMem = 11, + kSB3_CmdFillMem = 12, + kSB3_CmdFwVerCheck = 13, +} sb3_cmd_t; + +/*! @brief The all of the allowed command */ +#define SBLOADER_V3_CMD_SET_ALL \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdCall) | \ + (1u << kSB3_CmdProgramFuse) | (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | \ + (1u << kSB3_CmdConfigMem) | (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) +/*! @brief The allowed command set in ISP mode */ +#define SBLOADER_V3_CMD_SET_IN_ISP_MODE \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ + (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ + (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) +/*! @brief The allowed command set in recovery mode */ +#define SBLOADER_V3_CMD_SET_IN_REC_MODE \ + ((1u << kSB3_CmdErase) | (1u << kSB3_CmdLoad) | (1u << kSB3_CmdExecute) | (1u << kSB3_CmdProgramFuse) | \ + (1u << kSB3_CmdProgramIFR) | (1u << kSB3_CmdCopy) | (1u << kSB3_CmdLoadKeyBlob) | (1u << kSB3_CmdConfigMem) | \ + (1u << kSB3_CmdFillMem) | (1u << kSB3_CmdFwVerCheck)) + +#define SB3_DATA_BUFFER_SIZE_IN_BYTE (MAX(128, NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX)) + +/*! @brief Memory region definition. */ +typedef struct +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image. */ + kRomLoadImage = 2, /*!< Load SB file. */ + kRomOperationCount = 3, +} kb_operation_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct +{ + uint32_t version; /*!< Should be set to #kKbootApiVersion. */ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot. */ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*!< Settings for #kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*!< Settings for #kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! @brief Loader context definition. */ +struct _ldr_Context_v3 +{ + pLdrFnc_v3_t Action; /*!< pointer to loader action function */ + uint32_t block_size; /*!< size of each block in bytes */ + uint32_t block_data_size; /*!< data size in bytes (NBOOT_SB3_CHUNK_SIZE_IN_BYTES) */ + uint32_t block_data_total; /*!< data max size in bytes (block_size * data_size */ + uint32_t block_buffer_size; /*!< block0 and block size */ + uint32_t block_buffer_position; + uint8_t block_buffer[MAX(NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES, + NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES)]; /*! will be used for both block0 and blockx */ + uint32_t processedBlocks; + + uint8_t data_block_offset; /*! data block offset in a block. */ + bool in_data_block; /*!< in progress of handling a data block within a block */ + uint8_t *data_block; + uint32_t data_block_position; + + bool in_data_section; /*!< in progress of handling a data section within a data block */ + uint32_t data_section_handled; + sb3_section_header_t data_section_header; + + bool in_data_range; /*!< in progress of handling a data range within a data section */ + uint32_t data_range_handled; + uint32_t data_range_gap; + sb3_data_range_header_t data_range_header; + bool has_data_range_expansion; + sb3_data_range_expansion_t data_range_expansion; + + uint32_t commandSet; /*!< support command set during sb file handling */ + + uint32_t data_position; + uint8_t data_buffer[SB3_DATA_BUFFER_SIZE_IN_BYTE]; /*!< temporary data buffer */ + + kb_options_t fromAPI; /*!< options from ROM API */ +}; + +/*! @} */ + +#endif /* FSL_SBLOADER_V3_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/src/fsl_mem_interface.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/src/fsl_mem_interface.c new file mode 100644 index 0000000000..b95b82c8a3 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/mem_interface/src/fsl_mem_interface.c @@ -0,0 +1,154 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_mem_interface.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.memInterface" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/*! @brief IAP API Interface structure */ +typedef struct iap_api_interface_struct +{ + standard_version_t version; /*!< IAP API version number. */ + status_t (*api_init)(api_core_context_t *coreCtx, const kp_api_init_param_t *param); + status_t (*api_deinit)(api_core_context_t *coreCtx); + status_t (*mem_init)(api_core_context_t *ctx); + status_t (*mem_read)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint8_t *buf, uint32_t memoryId); + status_t (*mem_write)(api_core_context_t *ctx, uint32_t addr, uint32_t len, const uint8_t *buf, uint32_t memoryId); + status_t (*mem_fill)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t pattern, uint32_t memoryId); + status_t (*mem_flush)(api_core_context_t *ctx); + status_t (*mem_erase)(api_core_context_t *ctx, uint32_t addr, uint32_t len, uint32_t memoryId); + status_t (*mem_config)(api_core_context_t *ctx, uint32_t *buf, uint32_t memoryId); + status_t (*mem_erase_all)(api_core_context_t *ctx, uint32_t memoryId); + status_t (*sbloader_init)(api_core_context_t *ctx); + status_t (*sbloader_pump)(api_core_context_t *ctx, uint8_t *data, uint32_t length); + status_t (*sbloader_finalize)(api_core_context_t *ctx); +} iap_api_interface_t; + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const uint32_t flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t efuseDriver; /*!< eFuse driver API */ + const iap_api_interface_t *iapAPIDriver; /*!< IAP driver API */ +} bootloader_tree_t; +/******************************************************************************* + * API + ******************************************************************************/ + +standard_version_t API_Version(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->version; +} + +/*! @brief Initialize the IAP API runtime environment */ +status_t API_Init(api_core_context_t *coreCtx, const kp_api_init_param_t *param) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->api_init(coreCtx, param); +} + +/*! @brief Deinitialize the IAP API runtime environment */ +status_t API_Deinit(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->api_deinit(coreCtx); +} + +/*! @brief Intialize the memory interface of the IAP API */ +status_t MEM_Init(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_init(coreCtx); +} + +/*! @brief Perform the memory write operation */ +status_t MEM_Write( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, const uint8_t *buf, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_write(coreCtx, start, lengthInBytes, buf, memoryId); +} + +/*! @brief Perform the Fill operation */ +status_t MEM_Fill( + api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t pattern, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_fill(coreCtx, start, lengthInBytes, pattern, memoryId); +} + +/*! @brief Perform the Memory erase operation */ +status_t MEM_Erase(api_core_context_t *coreCtx, uint32_t start, uint32_t lengthInBytes, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_erase(coreCtx, start, lengthInBytes, memoryId); +} +/*! @brief Perform the full Memory erase operation */ +status_t MEM_EraseAll(api_core_context_t *coreCtx, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_erase_all(coreCtx, memoryId); +} + +/*! @brief Perform the Memory configuration operation */ +status_t MEM_Config(api_core_context_t *coreCtx, uint32_t *config, uint32_t memoryId) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_config(coreCtx, config, memoryId); +} + +/*! @brief Perform the Memory Flush operation */ +status_t MEM_Flush(api_core_context_t *coreCtx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->mem_flush(coreCtx); +} + +/*! @brief Perform the Sbloader runtime environment initialization */ +status_t Sbloader_Init(api_core_context_t *ctx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_init(ctx); +} + +/*! @brief Handle the SB data stream */ +status_t Sbloader_Pump(api_core_context_t *ctx, uint8_t *data, uint32_t length) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_pump(ctx, data, length); +} +/*! @brief Finish the sbloader handling */ +status_t Sbloader_Finalize(api_core_context_t *ctx) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->iapAPIDriver->sbloader_finalize(ctx); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/fsl_nboot.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/fsl_nboot.h new file mode 100644 index 0000000000..f1cca4da17 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/fsl_nboot.h @@ -0,0 +1,346 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_NBOOT_H_ +#define FSL_NBOOT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup nboot + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/** @def NXPCLHASH_WA_SIZE_MAX + * @brief Define the max workarea size required for this component + */ +#define NXPCLHASH_WA_SIZE_MAX (128U + 64U) +#define NBOOT_ROOT_CERT_COUNT (4U) +#define NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL ((size_t)32U) ///< Size of RTF appendix to hash output buffer, in bytes + +#define NBOOT_KEYINFO_WORDLEN (23U) +#define NBOOT_CONTEXT_BYTELEN (192U + NXPCLHASH_WA_SIZE_MAX) +#define NBOOT_CONTEXT_WORDLEN (NBOOT_CONTEXT_BYTELEN / sizeof(uint32_t)) +typedef int romapi_status_t; + +/*! + * @brief NBOOT type for the root key usage + * + * This type defines the NBOOT root key usage; + * any other value means the root key is not valid (treat as if revoked). + */ +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA_ImageKey_FwKey (0x0U) +#define kNBOOT_RootKeyUsage_DebugCA (0x1U) +#define kNBOOT_RootKeyUsage_ImageCA_FwCA (0x2U) +#define kNBOOT_RootKeyUsage_DebugCA_ImageCA_FwCA (0x3U) +#define kNBOOT_RootKeyUsage_ImageKey_FwKey (0x4U) +#define kNBOOT_RootKeyUsage_ImageKey (0x5U) +#define kNBOOT_RootKeyUsage_FwKey (0x6U) +#define kNBOOT_RootKeyUsage_Unused (0x7U) +typedef uint32_t nboot_root_key_usage_t; + +/*! + * @brief NBOOT type for the root key revocation + * + * This type defines the NBOOT root key revocation; + * any other value means the root key is revoked. + */ +#define kNBOOT_RootKey_Enabled (0xAAU) +#define kNBOOT_RootKey_Revoked (0xBBU) +typedef uint32_t nboot_root_key_revocation_t; + +/*! + * @brief NBOOT type specifying the elliptic curve to be used + * + * This type defines the elliptic curve type and length + */ +#define kNBOOT_RootKey_Ecdsa_P256 (0x0000FE01U) +#define kNBOOT_RootKey_Ecdsa_P384 (0x0000FD02U) +typedef uint32_t nboot_root_key_type_and_length_t; + +/*! @brief Enumeration for SoC Lifecycle. */ +#define nboot_lc_nxpBlank (0xFFFF0000U) +#define nboot_lc_nxpFab (0xFFFE0001U) +#define nboot_lc_nxpDev (0xFF0300FCU) +#define nboot_lc_nxpProvisioned (0xFFFC0003U) +#define nboot_lc_oemOpen (0xFFFC0003U) +#define nboot_lc_oemSecureWorld (0xFFF80007U) +#define nboot_lc_oemClosed (0xFFF0000FU) +#define nboot_lc_oemLocked (0xFF3000CFU) +#define nboot_lc_oemFieldReturn (0xFFE0001FU) +#define nboot_lc_nxpFieldReturn (0xFF80007FU) +#define nboot_lc_shredded (0xFF0000FFU) +typedef uint32_t nboot_soc_lifecycle_t; + +/*! @brief Type for nboot status codes */ +typedef uint32_t nboot_status_t; + +/*! @brief Type for nboot protected status codes */ +typedef uint64_t nboot_status_protected_t; + +/*! + * @brief nboot status codes. + */ +enum +{ + kStatus_NBOOT_Success = 0x5A5A5A5AU, /*!< Operation completed successfully. */ + kStatus_NBOOT_Fail = 0x5A5AA5A5U, /*!< Operation failed. */ + kStatus_NBOOT_InvalidArgument = 0x5A5AA5F0U, /*!< Invalid argument passed to the function. */ + kStatus_NBOOT_RequestTimeout = 0x5A5AA5E1U, /*!< Operation timed out. */ + kStatus_NBOOT_KeyNotLoaded = 0x5A5AA5E2U, /*!< The requested key is not loaded. */ + kStatus_NBOOT_AuthFail = 0x5A5AA5E4U, /*!< Authentication failed. */ + kStatus_NBOOT_OperationNotAvaialable = 0x5A5AA5E5U, /*!< Operation not available on this HW. */ + kStatus_NBOOT_KeyNotAvailable = 0x5A5AA5E6U, /*!< Key is not avaialble. */ + kStatus_NBOOT_IvCounterOverflow = 0x5A5AA5E7U, /*!< Overflow of IV counter (PRINCE/IPED). */ + kStatus_NBOOT_SelftestFail = 0x5A5AA5E8U, /*!< FIPS self-test failure. */ + kStatus_NBOOT_InvalidDataFormat = 0x5A5AA5E9U, /*!< Invalid data format for example antipole */ + kStatus_NBOOT_IskCertUserDataTooBig = + 0x5A5AA5EAU, /*!< Size of User data in ISK certificate is greater than 96 bytes */ + kStatus_NBOOT_IskCertSignatureOffsetTooSmall = + 0x5A5AA5EBU, /*!< Signature offset in ISK certificate is smaller than expected */ + kStatus_NBOOT_MemcpyFail = 0x5A5A845AU, /*!< Unexpected error detected during nboot_memcpy() */ +}; + +/*! @brief Data structure holding secure counter value used by nboot library */ +typedef struct _nboot_secure_counter +{ + uint32_t sc; + uint32_t scAp; +} nboot_secure_counter_t; + +/*! + * @brief NBOOT context type + * + * This type defines the NBOOT context + * + */ +typedef struct _nboot_context +{ + uint32_t totalBlocks; /*!< holds number of SB3 blocks. Initialized by nboot_sb3_load_header(). */ + uint32_t processData; /*!< flag, initialized by nboot_sb3_load_header(). + SB3 related flag set by NBOOT in case the nboot_sb3_load_block() + provides plain data to output buffer (for processing by ROM SB3 loader */ + uint32_t timeout; /*!< timeout value for css operation. In case it is 0, infinite wait is performed */ + uint32_t keyinfo[NBOOT_KEYINFO_WORDLEN]; /*!< data for NBOOT key management. */ + uint32_t context[NBOOT_CONTEXT_WORDLEN]; /*!< work area for NBOOT lib. */ + uint32_t uuid[4]; /*!< holds UUID value from NMPA */ + uint32_t prngReadyFlag; /*!< flag, used by nboot_rng_generate_lq_random() to determine whether CSS is ready to + generate rnd number */ + uint32_t multipartMacBuffer[1024 / sizeof(uint32_t)]; + uint32_t oemShareValidFlag; /*!< flag, used during TP to determine whether valid oemShare was set by + nboot_tp_isp_gen_oem_master_share() */ + uint32_t oemShare[4]; /*!< buffer to store OEM_SHARE computed by nxpCLTrustProv_nboot_isp_gen_oem_master_share() */ + nboot_secure_counter_t secureCounter; /*!< Secure counter used by nboot */ + uint32_t rtf[NXPCLCSS_HASH_RTF_OUTPUT_SIZE_HAL / sizeof(uint32_t)]; + uint32_t imageHash[48 / sizeof(uint32_t)]; + uint32_t authStatus; +} nboot_context_t; + +/*! + * @brief NBOOT type for the root of trust parameters + * + * This type defines the NBOOT root of trust parameters + * + */ +typedef struct _nboot_rot_auth_parms +{ + /* trusted information originated from CFPA */ + nboot_root_key_revocation_t soc_rootKeyRevocation[NBOOT_ROOT_CERT_COUNT]; /*!< Provided by caller based on NVM + information in CFPA: ROTKH_REVOKE */ + uint32_t soc_imageKeyRevocation; /*!< Provided by caller based on NVM information in CFPA: IMAGE_KEY_REVOKE */ + + /* trusted information originated from CMPA */ + uint32_t soc_rkh[12]; /*!< Provided by caller based on NVM information in CMPA: ROTKH (hash of hashes) */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P384, sock_rkh[0..11] are used */ + /*!< In case of kNBOOT_RootKey_Ecdsa_P256, sock_rkh[0..7] are used */ + + uint32_t soc_numberOfRootKeys; /*!< unsigned int, between minimum = 1 and maximum = 4; */ + nboot_root_key_usage_t soc_rootKeyUsage[NBOOT_ROOT_CERT_COUNT]; /*!< CMPA */ + nboot_root_key_type_and_length_t + soc_rootKeyTypeAndLength; /*!< static selection between ECDSA P-256 or ECDSA P-384 based root keys */ + + /* trusted information originated from OTP fuses */ + nboot_soc_lifecycle_t soc_lifecycle; +} nboot_rot_auth_parms_t; + +/*! + * @brief manifest loading parameters + * + * This type defines the NBOOT SB3.1 manifest loading parameters + * + */ +typedef struct _nboot_sb3_load_manifest_parms +{ + nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ + uint8_t pckBlob[48]; +} nboot_sb3_load_manifest_parms_t; + +/*! + * @brief Data structure holding input arguments to POR secure boot (authentication) algorithm. + * Shall be read from SoC trusted NVM or SoC fuses. + */ +typedef struct _nboot_img_auth_ecdsa_parms +{ + nboot_rot_auth_parms_t soc_RoTNVM; /*!< trusted information originated from CFPA and NMPA */ + uint32_t soc_trustedFirmwareVersion; /*!< Provided by caller based on NVM information in CFPA: Secure_FW_Version */ +} nboot_img_auth_ecdsa_parms_t; + +/*! @brief Data structure holding input arguments for CMAC authentication */ +typedef struct _nboot_cmac_authenticate_parms +{ + uint32_t expectedMAC[4]; /*!< expected MAC result */ +} nboot_img_authenticate_cmac_parms_t; + +/*! + * @brief Boolean type for the NBOOT functions + * + * This type defines boolean values used by NBOOT functions that are not easily disturbed by Fault Attacks + */ +typedef enum _nboot_bool +{ + kNBOOT_TRUE = 0x3C5AC33CU, /*!< Value for TRUE. */ + kNBOOT_TRUE256 = 0x3C5AC35AU, /*!< Value for TRUE when P256 was used to sign the image. */ + kNBOOT_TRUE384 = 0x3C5AC3A5U, /*!< Value for TRUE when P384 was used to sign the image. */ + kNBOOT_FALSE = 0x5AA55AA5U, /*!< Value for FALSE. */ + kNBOOT_OperationAllowed = 0x3c5a33ccU, + kNBOOT_OperationDisallowed = 0x5aa5cc33U, +} nboot_bool_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief This API function is used to generate random number with specified length. + * + * @param output Pointer to random number buffer + * @param outputByteLen length of generated random number in bytes. Length has to be in range <1, 2^16> + * + * @retval #kStatus_NBOOT_InvalidArgument Invalid input parameters (Input pointers points to NULL or length is invalid) + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +status_t NBOOT_GenerateRandom(uint8_t *output, size_t outputByteLen); + +/*! + * @brief The function is used for initializing of the nboot context data structure. + * It should be called prior to any other calls of nboot API. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextInit(nboot_context_t *context); + +/*! + * @brief The function is used to deinitialize nboot context data structure. + * Its contents are overwritten with random data so that any sensitive data does not remain in memory. + * + * @param context Pointer to nboot_context_t structure. + + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextDeinit(nboot_context_t *context); + +/*! + * @brief Verify NBOOT SB3.1 manifest (header message) + * + * This function verifies the NBOOT SB3.1 manifest (header message), initializes + * the context and loads keys into the CSS key store so that they can be used by nboot_sb3_load_block + * function. The NBOOT context has to be initialized by the function nboot_context_init before calling + * this function. Please note that this API is intended to be used only by users who needs to split + * FW update process (loading of SB3.1 file) to partial steps to customize whole operation. + * For regular SB3.1 processing, please use API described in chapter ��SBloader APIs��. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * @param manifest Pointer to the input manifest buffer + * @param params additional input parameters. Please refer to nboot_sb3_load_manifest_parms_t definition for details. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadManifest(nboot_context_t *context, + uint32_t *manifest, + nboot_sb3_load_manifest_parms_t *parms); + +/*! + * @brief Verify NBOOT SB3.1 block + * + * This function verifies and decrypts an NBOOT SB3.1 block. Decryption is performed in-place. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * Please note that this API is intended to be used only by users who needs to split FW update process + * (loading of SB3.1 file) to partial steps to customize whole operation. For regular SB3.1 processing, + * please use API described in chapter ��SBloader APIs��. + * + * @param context Pointer to nboot_context_t structure. + * @param block Pointer to the input SB3.1 data block + * + * @retval #kStatus_NBOOT_Success successfully finished + * @retval #kStatus_NBOOT_Fail occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadBlock(nboot_context_t *context, uint32_t *block); + +/*! + * @brief This function authenticates image with asymmetric cryptography. + * The NBOOT context has to be initialized by the function nboot_context_init + * before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + * After the function returns, the value will be set to kNBOOT_TRUE when the image is + * authentic. Any other value means the authentication does not pass. + * + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Returned in all other cases. Doesn't always mean invalid image, + * it could also mean transient error caused by short time environmental conditions. + */ +nboot_status_protected_t NBOOT_ImgAuthenticateEcdsa(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_ecdsa_parms_t *parms); + +/*! + * @brief This function calculates the CMAC over the given image and compares it to the expected value. + * To be more resistant against SPA, it is recommended that imageStartAddress is word aligned. + * The NBOOT context has to be initialized by the nboot_context_init() before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + After the function returns, the value will be set to + * @param parms Pointer to a data structure in trusted memory, holding the reference MAC. + The data structure shall be correctly filled before the function call. + * + * @retval kStatus_NBOOT_Success + * @retval kStatus_NBOOT_Fail + */ +nboot_status_protected_t NBOOT_ImgAuthenticateCmac(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_authenticate_cmac_parms_t *parms); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_NBOOT_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/fsl_nboot_hal.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/fsl_nboot_hal.h new file mode 100644 index 0000000000..79e0dd490e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/fsl_nboot_hal.h @@ -0,0 +1,231 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_NBOOT_HAL_H_ +#define FSL_NBOOT_HAL_H_ + +#include "fsl_nboot.h" + +/*! @addtogroup nbot_hal */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The size of the UUID. */ +#define NBOOT_UUID_SIZE_IN_WORD (4) +#define NBOOT_UUID_SIZE_IN_BYTE (NBOOT_UUID_SIZE_IN_WORD * 4) + +/*! @brief The size of the PUF activation code. */ +#define NBOOT_PUF_AC_SIZE_IN_BYTE (996) +/*! @brief The size of the PUF key code. */ +#define NBOOT_PUF_KC_SIZE_IN_BYTE (84) + +/*! @brief The size of the key store. */ +#define NBOOT_KEY_STORE_SIZE_IN_BYTE (NBOOT_PUF_AC_SIZE_IN_BYTE + 8) + +/*! @brief The size of the root of trust key table hash. */ +#define NBOOT_ROOT_ROTKH_SIZE_IN_WORD (12) +#define NBOOT_ROOT_ROTKH_SIZE_IN_BYTE (NBOOT_ROOT_ROTKH_SIZE_IN_WORD * 4) + +/*! @brief The size of the blob with Key Blob. */ +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_256 (32) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_384 (48) +#define NBOOT_KEY_BLOB_SIZE_IN_BYTE_MAX (NBOOT_KEY_BLOB_SIZE_IN_BYTE_384) + +/*! @brief The mask of the value of the debug state . */ +#define NBOOT_DBG_AUTH_DBG_STATE_MASK (0x0000FFFFu) +/*! @brief The shift inverted value of the debug state. */ +#define NBOOT_DBG_AUTH_DBG_STATE_SHIFT (16) +/*! @brief The value with all debug feature disabled. */ +#define NBOOT_DBG_AUTH_DBG_STATE_ALL_DISABLED (0xFFFF0000u) + +#define NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES (48u) + +#define NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES (48u) +#define NBOOT_EC_COORDINATE_MAX_SIZE NBOOT_EC_COORDINATE_384_SIZE_IN_BYTES + +/* SB3.1 */ +#define NBOOT_SB3_CHUNK_SIZE_IN_BYTES (256u) +#define NBOOT_SB3_BLOCK_HASH256_SIZE_IN_BYTES (32u) +#define NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES (48u) + +/*! + * @brief NBOOT type for a timestamp + * + * This type defines the NBOOT timestamp + * + */ +typedef uint32_t nboot_timestamp_t[2]; + +/*! + * @brief NBOOT SB3.1 header type + * + * This type defines the header used in the SB3.1 manifest + * + */ +typedef struct _nboot_sb3_header +{ + uint32_t magic; /*!< offset 0x00: Fixed 4-byte string of 'sbv3' without the trailing NULL */ + uint32_t formatVersion; /*!< offset 0x04: (major = 3, minor = 1); The format version determines the manifest + (block0) size. */ + uint32_t flags; /*!< offset 0x08: not defined yet, keep zero for future compatibility */ + uint32_t blockCount; /*!< offset 0x0C: Number of blocks not including the manifest (block0). */ + uint32_t + blockSize; /*!< offset 0x10: Size in bytes of data block (repeated blockCount times for SB3 data stream). */ + nboot_timestamp_t timeStamp; /*!< offset 0x14: 64-bit value used as key derivation data. */ + uint32_t firmwareVersion; /*!< offset 0x1c: Version number of the included firmware */ + uint32_t imageTotalLength; /*!< offset 0x20: Total manifest length in bytes, including signatures etc. */ + uint32_t imageType; /*!< offset 0x24: image type and flags */ + uint32_t certificateBlockOffset; /*!< offset 0x28: Offset from start of header block to the certificate block. */ + uint8_t description[16]; /*!< offset 0x32: This field provides description of the file. It is an arbitrary + string injected by the signing tool, which helps to identify the file. */ +} nboot_sb3_header_t; + +/*! + * @brief NBOOT type for the header of the certificate block + * + * This type defines the NBOOT header of the certificate block, it is part of the nboot_certificate_block_t + * + */ +typedef struct _nboot_certificate_header_block +{ + uint32_t magic; /*!< magic number. */ + uint32_t formatMajorMinorVersion; /*!< format major minor version */ + uint32_t certBlockSize; /*!< Size of the full certificate block */ +} nboot_certificate_header_block_t; + +typedef uint8_t nboot_ctrk_hash_t[NBOOT_ROOT_OF_TRUST_HASH_SIZE_IN_BYTES]; + +/*! + * @brief NBOOT type for the hash table + * + * This type defines the NBOOT hash table + * + */ +typedef struct _nboot_ctrk_hash_table +{ + nboot_ctrk_hash_t ctrkHashTable[NBOOT_ROOT_CERT_COUNT]; +} nboot_ctrk_hash_table_t; + +/*! + * @brief NBOOT type for an ECC coordinate + * + * This type defines the NBOOT ECC coordinate type + * + */ +typedef uint8_t + nboot_ecc_coordinate_t[NBOOT_EC_COORDINATE_MAX_SIZE]; /*!< ECC point coordinate, up to 384-bits. big endian. */ + +/*! + * @brief NBOOT type for an ECC point + * + * This type defines the NBOOT ECC point type + */ +typedef struct +{ + nboot_ecc_coordinate_t x; /*!< x portion of the ECDSA public key, up to 384-bits. big endian. */ + nboot_ecc_coordinate_t y; /*!< y portion of the ECDSA public key, up to 384-bits. big endian. */ +} nboot_ecdsa_public_key_t; + +/*! + * @brief NBOOT type for the root certificate block + * + * This type defines the NBOOT root certificate block, it is part of the nboot_certificate_block_t + */ +typedef struct _nboot_root_certificate_block +{ + uint32_t flags; /*!< root certificate flags */ + nboot_ctrk_hash_table_t ctrkHashTable; /*!< hash table */ + nboot_ecdsa_public_key_t rootPublicKey; /*!< root public key */ +} nboot_root_certificate_block_t; + +/*! + * @brief NBOOT type for an ECC signature + * + * This type defines the NBOOT ECC signature type + */ +typedef struct +{ + nboot_ecc_coordinate_t r; /*!< r portion of the ECDSA signature, up to 384-bits. big endian. */ + nboot_ecc_coordinate_t s; /*!< s portion of the ECDSA signature, up to 384-bits. big endian. */ +} nboot_ecdsa_signature_t; + +/*! + * @brief NBOOT type for the isk block + * + * This type defines the constant length part of an NBOOT isk block + */ +typedef struct +{ + uint32_t signatureOffset; /*!< Offset of signature in ISK block. */ + uint32_t constraints; /*!< Version number of signing certificate. */ + uint32_t iskFlags; /*!< Reserved for definiton of ISK certificate flags. */ + nboot_ecdsa_public_key_t + iskPubKey; /*!< Public key of signing certificate. Variable length; only used to determine start address*/ + nboot_ecdsa_public_key_t userData; /*!< Space for at lest one addition public key*/ + nboot_ecdsa_signature_t iskSign; /*!< ISK signature*/ +} nboot_isk_block_t; + +/*! + * @brief NBOOT type for the certificate block + * + * This type defines the constant length part of an NBOOT certificate block + */ +typedef struct _nboot_certificate_block +{ + nboot_certificate_header_block_t header; + nboot_root_certificate_block_t rootCertBlock; /*! Details of selected root certificate (root certificate which will + be used for ISK signing/SB3 header signing) */ + nboot_isk_block_t iskBlock; +} nboot_certificate_block_t; + +#define NBOOT_SB3_MANIFEST_MAX_SIZE_IN_BYTES \ + (sizeof(nboot_sb3_header_t) + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + sizeof(nboot_certificate_block_t) + \ + NBOOT_EC_COORDINATE_MAX_SIZE * 2) +#define NBOOT_SB3_BLOCK_MAX_SIZE_IN_BYTES \ + (4 /* blockNumber */ + NBOOT_SB3_BLOCK_HASH384_SIZE_IN_BYTES + NBOOT_SB3_CHUNK_SIZE_IN_BYTES) + +/*! @brief The size of the DICE certificate. */ +#define NBOOT_DICE_CSR_SIZE_IN_WORD (36) +#define NBOOT_DICE_CSR_SIZE_IN_BYTES (NBOOT_DICE_CSR_SIZE_IN_WORD * 4) + +/*! @brief The physical address to put the DICE certificate. */ +#define NBOOT_DICE_CSR_ADDRESS (0x30000000u) + +/*! @brief The offset for the PRCINE/IPED erase region return by nboot mem checker. */ +#define NBOOT_IPED_IV_OFFSET (3U) + +#define NBOOT_IMAGE_CMAC_UPDATE_NONE (0u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX0 (1u) +#define NBOOT_IMAGE_CMAC_UPDATE_INDEX1 (2u) +#define NBOOT_IMAGE_CMAC_UPDATE_BOTH (3u) +#define NBOOT_IMAGE_CMAC_UPDATE_MASK (3u) + +#define NBOOT_CMPA_CMAC_UPDATE_MASK (0x1Cu) +#define NBOOT_CMPA_CMAC_UPDATE_SHIFT (0x2u) + +#define NBOOT_CMPA_UPDATE_CMAC_PFR (0x2u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_SECURE (0x3u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_CLOSE (0x5u) +#define NBOOT_CMPA_UPDATE_CMAC_PFR_OTP_OEM_LOCKED (0x6u) + +/*! @brief Algorithm used for nboot HASH operation */ +typedef enum _nboot_hash_algo_t +{ + kHASH_Sha1 = 1, /*!< SHA_1 */ + kHASH_Sha256 = 2, /*!< SHA_256 */ + kHASH_Sha512 = 3, /*!< SHA_512 */ + kHASH_Aes = 4, /*!< AES */ + kHASH_AesIcb = 5, /*!< AES_ICB */ +} nboot_hash_algo_t; + +/*! @} */ + +#endif /*FSL_NBOOT_HAL_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/src/fsl_nboot.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/src/fsl_nboot.c new file mode 100644 index 0000000000..909be4ae3e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/nboot/src/fsl_nboot.c @@ -0,0 +1,212 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_nboot.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.nboot" +#endif + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/** + * @brief Image authentication operations. + * + * These abstract interface are used for image verification operations. + */ +typedef struct +{ + romapi_status_t (*romapi_rng_generate_random)(uint8_t *output, size_t outputByteLen); + nboot_status_t (*nboot_context_init)(nboot_context_t *context); + nboot_status_t (*nboot_context_deinit)(nboot_context_t *context); + nboot_status_protected_t (*nboot_sb3_load_manifest)(nboot_context_t *context, + uint32_t *manifest, + nboot_sb3_load_manifest_parms_t *parms); + nboot_status_protected_t (*nboot_sb3_load_block)(nboot_context_t *context, uint32_t *block); + nboot_status_protected_t (*nboot_img_authenticate_ecdsa)(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_ecdsa_parms_t *parms); + nboot_status_protected_t (*nboot_img_authenticate_cmac)(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_authenticate_cmac_parms_t *parms); +} nboot_interface_t; + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + const uint32_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const nboot_interface_t *nbootDriver; /*!< nBoot driver API */ + const uint32_t flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t efuseDriver; /*!< eFuse driver API */ + const uint32_t iapAPIDriver; /*!< IAP driver API */ +} bootloader_tree_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief This API function is used to generate random number with specified length. + * + * @param output Pointer to random number buffer + * @param outputByteLen length of generated random number in bytes. Length has to be in range <1, 2^16> + * + * @retval #kStatus_NBOOT_InvalidArgument Invalid input parameters (Input pointers points to NULL or length is invalid) + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +status_t NBOOT_GenerateRandom(uint8_t *output, size_t outputByteLen) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->romapi_rng_generate_random(output, outputByteLen); +} + +/*! + * @brief The function is used for initializing of the nboot context data structure. + * It should be called prior to any other calls of nboot API. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextInit(nboot_context_t *context) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_context_init(context); +} + +/*! + * @brief The function is used to deinitialize nboot context data structure. + * Its contents are overwritten with random data so that any sensitive data does not remain in memory. + * + * @param context Pointer to nboot_context_t structure. + + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_t NBOOT_ContextDeinit(nboot_context_t *context) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_context_deinit(context); +} +/*! + * @brief Verify NBOOT SB3.1 manifest (header message) + * + * This function verifies the NBOOT SB3.1 manifest (header message), initializes + * the context and loads keys into the CSS key store so that they can be used by nboot_sb3_load_block + * function. The NBOOT context has to be initialized by the function nboot_context_init before calling + * this function. Please note that this API is intended to be used only by users who needs to split + * FW update process (loading of SB3.1 file) to partial steps to customize whole operation. + * For regular SB3.1 processing, please use API described in chapter SBloader APIs. + * + * @param nbootCtx Pointer to nboot_context_t structure. + * @param manifest Pointer to the input manifest buffer + * @param params additional input parameters. Please refer to nboot_sb3_load_manifest_parms_t definition for details. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Error occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadManifest(nboot_context_t *context, + uint32_t *manifest, + nboot_sb3_load_manifest_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_sb3_load_manifest(context, manifest, parms); +} + +/*! + * @brief Verify NBOOT SB3.1 block + * + * This function verifies and decrypts an NBOOT SB3.1 block. Decryption is performed in-place. + * The NBOOT context has to be initialized by the function nboot_context_init before calling this function. + * Please note that this API is intended to be used only by users who needs to split FW update process + * (loading of SB3.1 file) to partial steps to customize whole operation. For regular SB3.1 processing, + * please use API described in chapter SBloader APIs. + * + * @param context Pointer to nboot_context_t structure. + * @param block Pointer to the input SB3.1 data block + * + * @retval #kStatus_NBOOT_Success successfully finished + * @retval #kStatus_NBOOT_Fail occured during operation + */ +nboot_status_protected_t NBOOT_Sb3LoadBlock(nboot_context_t *context, uint32_t *block) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_sb3_load_block(context, block); +} + +/*! + * @brief This function authenticates image with asymmetric cryptography. + * The NBOOT context has to be initialized by the function nboot_context_init + * before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + * After the function returns, the value will be set to kNBOOT_TRUE when the image is + * authentic. Any other value means the authentication does not pass. + * + * @param parms Pointer to a data structure in trusted memory, holding input parameters for the algorithm. + * The data structure shall be correctly filled before the function call. + * + * @retval #kStatus_NBOOT_Success Operation successfully finished + * @retval #kStatus_NBOOT_Fail Returned in all other cases. Doesn't always mean invalid image, + * it could also mean transient error caused by short time environmental conditions. + */ +nboot_status_protected_t NBOOT_ImgAuthenticateEcdsa(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_auth_ecdsa_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_img_authenticate_ecdsa(context, imageStartAddress, + isSignatureVerified, parms); +} + +/*! + * @brief This function calculates the CMAC over the given image and compares it to the expected value. + * To be more resistant against SPA, it is recommended that imageStartAddress is word aligned. + * The NBOOT context has to be initialized by the nboot_context_init() before calling this function. + * + * @param context Pointer to nboot_context_t structure. + * @param imageStartAddress Pointer to start of the image in memory. + * @param isSignatureVerified Pointer to memory holding function call result. + After the function returns, the value will be set to + * @param parms Pointer to a data structure in trusted memory, holding the reference MAC. + The data structure shall be correctly filled before the function call. + * + * @retval kStatus_NBOOT_Success + * @retval kStatus_NBOOT_Fail + */ +nboot_status_protected_t NBOOT_ImgAuthenticateCmac(nboot_context_t *context, + uint8_t imageStartAddress[], + nboot_bool_t *isSignatureVerified, + nboot_img_authenticate_cmac_parms_t *parms) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->nbootDriver->nboot_img_authenticate_cmac(context, imageStartAddress, + isSignatureVerified, parms); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/runbootloader/fsl_runbootloader.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/runbootloader/fsl_runbootloader.h new file mode 100644 index 0000000000..de0ed4a9c5 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/runbootloader/fsl_runbootloader.h @@ -0,0 +1,72 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_RUN_BOOTLOADER_H_ +#define FSL_RUN_BOOTLOADER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup runbootloader + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* API prototype fields definition. +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | + | Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | +| | | | Used For Boot mode 0| | | +| | 0: Passive mode | 0 - Auto detection | | | | +| | 1: ISP mode | 1 - USB-HID | | | | +| | | 2 - UART | | | | +| | | 3 - SPI | | | | +| | | 4 - I2C | | | | +| | | 5 - CAN | | | | +*/ + +typedef struct +{ + union + { + struct + { + uint32_t reserved : 8; + uint32_t boot_image_index : 4; + uint32_t instance : 4; + uint32_t boot_interface : 4; + uint32_t mode : 4; + uint32_t tag : 8; + } B; + uint32_t U; + } option; +} user_app_boot_invoke_option_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Run the Bootloader API to force into the ISP mode base on the user arg + * + * @param arg Indicates API prototype fields definition. Refer to the above user_app_boot_invoke_option_t structure + */ +void bootloader_user_entry(void *arg); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* FSL_RUN_BOOTLOADER_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/runbootloader/src/fsl_runbootloader.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/runbootloader/src/fsl_runbootloader.c new file mode 100644 index 0000000000..ebfe866f1e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/drivers/romapi/runbootloader/src/fsl_runbootloader.c @@ -0,0 +1,52 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_flash.h" +#include "fsl_flash_ffr.h" +#include "fsl_flexspi_nor_flash.h" +#include "fsl_runbootloader.h" + +/*! @brief Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.runBootloader" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1303fc00U) + +/*! + * @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct BootloaderTree +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + const uint32_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const uint32_t reserved0; /*!< reserved*/ + const uint32_t flashDriver; /*!< Internal Flash driver API.*/ + const uint32_t reserved1[5]; /*!< reserved*/ + const uint32_t nbootDriver; /*!< Please refer to "fsl_nboot.h" */ + const uint32_t flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t reserved2; /*!< reserved*/ + const uint32_t memoryInterface; /*!< Please refer to "fsl_mem_interface.h" */ +} bootloader_tree_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +void bootloader_user_entry(void *arg) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->runBootloader(arg); +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/fsl_device_registers.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/fsl_device_registers.h new file mode 100644 index 0000000000..f270e5a756 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/fsl_device_registers.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXN236VDF) || defined(CPU_MCXN236VNL)) + +#define MCXN236_SERIES + +/* CMSIS-style register definitions */ +#include "MCXN236.h" +/* CPU specific feature definitions */ +#include "MCXN236_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/gcc/startup_MCXN236.S b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/gcc/startup_MCXN236.S new file mode 100644 index 0000000000..31c4031a05 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/gcc/startup_MCXN236.S @@ -0,0 +1,1948 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MCXN236.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* MCXN236 */ +/* @version: 1.0 */ +/* @date: 2023-10-1 */ +/* @build: b240409 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2024 NXP */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long OR_IRQHandler /* OR IRQ*/ + .long EDMA_0_CH0_IRQHandler /* eDMA_0_CH0 error or transfer complete*/ + .long EDMA_0_CH1_IRQHandler /* eDMA_0_CH1 error or transfer complete*/ + .long EDMA_0_CH2_IRQHandler /* eDMA_0_CH2 error or transfer complete*/ + .long EDMA_0_CH3_IRQHandler /* eDMA_0_CH3 error or transfer complete*/ + .long EDMA_0_CH4_IRQHandler /* eDMA_0_CH4 error or transfer complete*/ + .long EDMA_0_CH5_IRQHandler /* eDMA_0_CH5 error or transfer complete*/ + .long EDMA_0_CH6_IRQHandler /* eDMA_0_CH6 error or transfer complete*/ + .long EDMA_0_CH7_IRQHandler /* eDMA_0_CH7 error or transfer complete*/ + .long EDMA_0_CH8_IRQHandler /* eDMA_0_CH8 error or transfer complete*/ + .long EDMA_0_CH9_IRQHandler /* eDMA_0_CH9 error or transfer complete*/ + .long EDMA_0_CH10_IRQHandler /* eDMA_0_CH10 error or transfer complete*/ + .long EDMA_0_CH11_IRQHandler /* eDMA_0_CH11 error or transfer complete*/ + .long EDMA_0_CH12_IRQHandler /* eDMA_0_CH12 error or transfer complete*/ + .long EDMA_0_CH13_IRQHandler /* eDMA_0_CH13 error or transfer complete*/ + .long EDMA_0_CH14_IRQHandler /* eDMA_0_CH14 error or transfer complete*/ + .long EDMA_0_CH15_IRQHandler /* eDMA_0_CH15 error or transfer complete*/ + .long GPIO00_IRQHandler /* GPIO0 interrupt 0*/ + .long GPIO01_IRQHandler /* GPIO0 interrupt 1*/ + .long GPIO10_IRQHandler /* GPIO1 interrupt 0*/ + .long GPIO11_IRQHandler /* GPIO1 interrupt 1*/ + .long GPIO20_IRQHandler /* GPIO2 interrupt 0*/ + .long GPIO21_IRQHandler /* GPIO2 interrupt 1*/ + .long GPIO30_IRQHandler /* GPIO3 interrupt 0*/ + .long GPIO31_IRQHandler /* GPIO3 interrupt 1*/ + .long GPIO40_IRQHandler /* GPIO4 interrupt 0*/ + .long GPIO41_IRQHandler /* GPIO4 interrupt 1*/ + .long GPIO50_IRQHandler /* GPIO5 interrupt 0*/ + .long GPIO51_IRQHandler /* GPIO5 interrupt 1*/ + .long UTICK0_IRQHandler /* Micro-Tick Timer interrupt*/ + .long MRT0_IRQHandler /* Multi-Rate Timer interrupt*/ + .long CTIMER0_IRQHandler /* Standard counter/timer 0 interrupt*/ + .long CTIMER1_IRQHandler /* Standard counter/timer 1 interrupt*/ + .long Reserved49_IRQHandler /* Reserved interrupt*/ + .long CTIMER2_IRQHandler /* Standard counter/timer 2 interrupt*/ + .long LP_FLEXCOMM0_IRQHandler /* LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM1_IRQHandler /* LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM2_IRQHandler /* LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM3_IRQHandler /* LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM4_IRQHandler /* LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM5_IRQHandler /* LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM6_IRQHandler /* LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long LP_FLEXCOMM7_IRQHandler /* LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt)*/ + .long Reserved59_IRQHandler /* Reserved interrupt*/ + .long Reserved60_IRQHandler /* Reserved interrupt*/ + .long ADC0_IRQHandler /* Analog-to-Digital Converter 0 - General Purpose interrupt*/ + .long ADC1_IRQHandler /* Analog-to-Digital Converter 1 - General Purpose interrupt*/ + .long PINT0_IRQHandler /* Pin Interrupt Pattern Match Interrupt*/ + .long PDM_EVENT_IRQHandler /* Microphone Interface interrupt */ + .long Reserved65_IRQHandler /* Reserved interrupt*/ + .long Reserved66_IRQHandler /* Reserved interrupt*/ + .long USB0_DCD_IRQHandler /* Universal Serial Bus - Device Charge Detect interrupt*/ + .long RTC_IRQHandler /* RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt)*/ + .long SMARTDMA_IRQHandler /* SmartDMA_IRQ*/ + .long Reserved70_IRQHandler /* Reserved interrupt*/ + .long CTIMER3_IRQHandler /* Standard counter/timer 3 interrupt*/ + .long CTIMER4_IRQHandler /* Standard counter/timer 4 interrupt*/ + .long OS_EVENT_IRQHandler /* OS event timer interrupt*/ + .long Reserved74_IRQHandler /* Reserved interrupt*/ + .long SAI0_IRQHandler /* Serial Audio Interface 0 interrupt*/ + .long SAI1_IRQHandler /* Serial Audio Interface 1 interrupt*/ + .long Reserved77_IRQHandler /* Reserved interrupt*/ + .long CAN0_IRQHandler /* Controller Area Network 0 interrupt*/ + .long CAN1_IRQHandler /* Controller Area Network 1 interrupt*/ + .long Reserved80_IRQHandler /* Reserved interrupt*/ + .long Reserved81_IRQHandler /* Reserved interrupt*/ + .long USB1_HS_PHY_IRQHandler /* USBHS DCD or USBHS Phy interrupt*/ + .long USB1_HS_IRQHandler /* USB High Speed OTG Controller interrupt */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* AHB Secure Controller hypervisor call interrupt*/ + .long Reserved85_IRQHandler /* Reserved interrupt*/ + .long Reserved86_IRQHandler /* Reserved interrupt*/ + .long Freqme_IRQHandler /* Frequency Measurement interrupt*/ + .long SEC_VIO_IRQHandler /* Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt)*/ + .long ELS_IRQHandler /* ELS interrupt*/ + .long PKC_IRQHandler /* PKC interrupt*/ + .long PUF_IRQHandler /* Physical Unclonable Function interrupt*/ + .long Reserved92_IRQHandler /* Reserved interrupt*/ + .long EDMA_1_CH0_IRQHandler /* eDMA_1_CH0 error or transfer complete*/ + .long EDMA_1_CH1_IRQHandler /* eDMA_1_CH1 error or transfer complete*/ + .long EDMA_1_CH2_IRQHandler /* eDMA_1_CH2 error or transfer complete*/ + .long EDMA_1_CH3_IRQHandler /* eDMA_1_CH3 error or transfer complete*/ + .long EDMA_1_CH4_IRQHandler /* eDMA_1_CH4 error or transfer complete*/ + .long EDMA_1_CH5_IRQHandler /* eDMA_1_CH5 error or transfer complete*/ + .long EDMA_1_CH6_IRQHandler /* eDMA_1_CH6 error or transfer complete*/ + .long EDMA_1_CH7_IRQHandler /* eDMA_1_CH7 error or transfer complete*/ + .long Reserved101_IRQHandler /* Reserved interrupt*/ + .long Reserved102_IRQHandler /* Reserved interrupt*/ + .long Reserved103_IRQHandler /* Reserved interrupt*/ + .long Reserved104_IRQHandler /* Reserved interrupt*/ + .long Reserved105_IRQHandler /* Reserved interrupt*/ + .long Reserved106_IRQHandler /* Reserved interrupt*/ + .long Reserved107_IRQHandler /* Reserved interrupt*/ + .long Reserved108_IRQHandler /* Reserved interrupt*/ + .long CDOG0_IRQHandler /* Code Watchdog Timer 0 interrupt*/ + .long CDOG1_IRQHandler /* Code Watchdog Timer 1 interrupt*/ + .long I3C0_IRQHandler /* Improved Inter Integrated Circuit interrupt 0*/ + .long I3C1_IRQHandler /* Improved Inter Integrated Circuit interrupt 1*/ + .long Reserved113_IRQHandler /* Reserved interrupt*/ + .long GDET_IRQHandler /* Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt*/ + .long VBAT0_IRQHandler /* VBAT interrupt( VBAT interrupt or digital tamper interrupt)*/ + .long EWM0_IRQHandler /* External Watchdog Monitor interrupt*/ + .long Reserved117_IRQHandler /* Reserved interrupt*/ + .long Reserved118_IRQHandler /* Reserved interrupt*/ + .long Reserved119_IRQHandler /* Reserved interrupt*/ + .long Reserved120_IRQHandler /* Reserved interrupt*/ + .long FLEXIO_IRQHandler /* Flexible Input/Output interrupt*/ + .long Reserved122_IRQHandler /* Reserved interrupt*/ + .long Reserved123_IRQHandler /* Reserved interrupt*/ + .long Reserved124_IRQHandler /* Reserved interrupt*/ + .long HSCMP0_IRQHandler /* High-Speed comparator0 interrupt*/ + .long HSCMP1_IRQHandler /* High-Speed comparator1 interrupt*/ + .long Reserved127_IRQHandler /* Reserved interrupt*/ + .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* FlexPWM0_reload_error interrupt*/ + .long FLEXPWM0_FAULT_IRQHandler /* FlexPWM0_fault interrupt*/ + .long FLEXPWM0_SUBMODULE0_IRQHandler /* FlexPWM0 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE1_IRQHandler /* FlexPWM0 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE2_IRQHandler /* FlexPWM0 Submodule 2 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE3_IRQHandler /* FlexPWM0 Submodule 3 capture/compare/reload interrupt*/ + .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* FlexPWM1_reload_error interrupt*/ + .long FLEXPWM1_FAULT_IRQHandler /* FlexPWM1_fault interrupt*/ + .long FLEXPWM1_SUBMODULE0_IRQHandler /* FlexPWM1 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE3_IRQHandler /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/ + .long QDC0_COMPARE_IRQHandler /* QDC0_Compare interrupt*/ + .long QDC0_HOME_IRQHandler /* QDC0_Home interrupt*/ + .long QDC0_WDG_SAB_IRQHandler /* QDC0_WDG_IRQ/SAB interrupt*/ + .long QDC0_IDX_IRQHandler /* QDC0_IDX interrupt*/ + .long QDC1_COMPARE_IRQHandler /* QDC1_Compare interrupt*/ + .long QDC1_HOME_IRQHandler /* QDC1_Home interrupt*/ + .long QDC1_WDG_SAB_IRQHandler /* QDC1_WDG_IRQ/SAB interrupt*/ + .long QDC1_IDX_IRQHandler /* QDC1_IDX interrupt*/ + .long ITRC0_IRQHandler /* Intrusion and Tamper Response Controller interrupt*/ + .long Reserved149_IRQHandler /* Reserved interrupt*/ + .long ELS_ERR_IRQHandler /* ELS error interrupt*/ + .long PKC_ERR_IRQHandler /* PKC error interrupt*/ + .long ERM_SINGLE_BIT_ERROR_IRQHandler /* ERM Single Bit error interrupt*/ + .long ERM_MULTI_BIT_ERROR_IRQHandler /* ERM Multi Bit error interrupt*/ + .long FMU0_IRQHandler /* Flash Management Unit interrupt*/ + .long Reserved155_IRQHandler /* Reserved interrupt*/ + .long Reserved156_IRQHandler /* Reserved interrupt*/ + .long Reserved157_IRQHandler /* Reserved interrupt*/ + .long Reserved158_IRQHandler /* Reserved interrupt*/ + .long LPTMR0_IRQHandler /* Low Power Timer 0 interrupt*/ + .long LPTMR1_IRQHandler /* Low Power Timer 1 interrupt*/ + .long SCG_IRQHandler /* System Clock Generator interrupt*/ + .long SPC_IRQHandler /* System Power Controller interrupt*/ + .long WUU_IRQHandler /* Wake Up Unit interrupt*/ + .long PORT_EFT_IRQHandler /* PORT0~5 EFT interrupt*/ + .long Reserved165_IRQHandler /* Reserved interrupt*/ + .long Reserved166_IRQHandler /* Reserved interrupt*/ + .long Reserved167_IRQHandler /* Reserved interrupt*/ + .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ + .long WWDT1_IRQHandler /* Windowed Watchdog Timer 1 interrupt*/ + .long CMC0_IRQHandler /* Core Mode Controller interrupt*/ + .long Reserved171_IRQHandler /* Reserved interrupt*/ + + .size __Vectors, . - __Vectors + + .text + .thumb + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#endif +#endif +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr r0, =__StackLimit + msr msplim, r0 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 + +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ +#ifndef __START +#ifdef __REDLIB__ +#define __START __main +#else +#define __START _start +#endif +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak OR_IRQHandler + .type OR_IRQHandler, %function +OR_IRQHandler: + ldr r0,=OR_DriverIRQHandler + bx r0 + .size OR_IRQHandler, . - OR_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH0_IRQHandler + .type EDMA_0_CH0_IRQHandler, %function +EDMA_0_CH0_IRQHandler: + ldr r0,=EDMA_0_CH0_DriverIRQHandler + bx r0 + .size EDMA_0_CH0_IRQHandler, . - EDMA_0_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH1_IRQHandler + .type EDMA_0_CH1_IRQHandler, %function +EDMA_0_CH1_IRQHandler: + ldr r0,=EDMA_0_CH1_DriverIRQHandler + bx r0 + .size EDMA_0_CH1_IRQHandler, . - EDMA_0_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH2_IRQHandler + .type EDMA_0_CH2_IRQHandler, %function +EDMA_0_CH2_IRQHandler: + ldr r0,=EDMA_0_CH2_DriverIRQHandler + bx r0 + .size EDMA_0_CH2_IRQHandler, . - EDMA_0_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH3_IRQHandler + .type EDMA_0_CH3_IRQHandler, %function +EDMA_0_CH3_IRQHandler: + ldr r0,=EDMA_0_CH3_DriverIRQHandler + bx r0 + .size EDMA_0_CH3_IRQHandler, . - EDMA_0_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH4_IRQHandler + .type EDMA_0_CH4_IRQHandler, %function +EDMA_0_CH4_IRQHandler: + ldr r0,=EDMA_0_CH4_DriverIRQHandler + bx r0 + .size EDMA_0_CH4_IRQHandler, . - EDMA_0_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH5_IRQHandler + .type EDMA_0_CH5_IRQHandler, %function +EDMA_0_CH5_IRQHandler: + ldr r0,=EDMA_0_CH5_DriverIRQHandler + bx r0 + .size EDMA_0_CH5_IRQHandler, . - EDMA_0_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH6_IRQHandler + .type EDMA_0_CH6_IRQHandler, %function +EDMA_0_CH6_IRQHandler: + ldr r0,=EDMA_0_CH6_DriverIRQHandler + bx r0 + .size EDMA_0_CH6_IRQHandler, . - EDMA_0_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH7_IRQHandler + .type EDMA_0_CH7_IRQHandler, %function +EDMA_0_CH7_IRQHandler: + ldr r0,=EDMA_0_CH7_DriverIRQHandler + bx r0 + .size EDMA_0_CH7_IRQHandler, . - EDMA_0_CH7_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH8_IRQHandler + .type EDMA_0_CH8_IRQHandler, %function +EDMA_0_CH8_IRQHandler: + ldr r0,=EDMA_0_CH8_DriverIRQHandler + bx r0 + .size EDMA_0_CH8_IRQHandler, . - EDMA_0_CH8_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH9_IRQHandler + .type EDMA_0_CH9_IRQHandler, %function +EDMA_0_CH9_IRQHandler: + ldr r0,=EDMA_0_CH9_DriverIRQHandler + bx r0 + .size EDMA_0_CH9_IRQHandler, . - EDMA_0_CH9_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH10_IRQHandler + .type EDMA_0_CH10_IRQHandler, %function +EDMA_0_CH10_IRQHandler: + ldr r0,=EDMA_0_CH10_DriverIRQHandler + bx r0 + .size EDMA_0_CH10_IRQHandler, . - EDMA_0_CH10_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH11_IRQHandler + .type EDMA_0_CH11_IRQHandler, %function +EDMA_0_CH11_IRQHandler: + ldr r0,=EDMA_0_CH11_DriverIRQHandler + bx r0 + .size EDMA_0_CH11_IRQHandler, . - EDMA_0_CH11_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH12_IRQHandler + .type EDMA_0_CH12_IRQHandler, %function +EDMA_0_CH12_IRQHandler: + ldr r0,=EDMA_0_CH12_DriverIRQHandler + bx r0 + .size EDMA_0_CH12_IRQHandler, . - EDMA_0_CH12_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH13_IRQHandler + .type EDMA_0_CH13_IRQHandler, %function +EDMA_0_CH13_IRQHandler: + ldr r0,=EDMA_0_CH13_DriverIRQHandler + bx r0 + .size EDMA_0_CH13_IRQHandler, . - EDMA_0_CH13_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH14_IRQHandler + .type EDMA_0_CH14_IRQHandler, %function +EDMA_0_CH14_IRQHandler: + ldr r0,=EDMA_0_CH14_DriverIRQHandler + bx r0 + .size EDMA_0_CH14_IRQHandler, . - EDMA_0_CH14_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_0_CH15_IRQHandler + .type EDMA_0_CH15_IRQHandler, %function +EDMA_0_CH15_IRQHandler: + ldr r0,=EDMA_0_CH15_DriverIRQHandler + bx r0 + .size EDMA_0_CH15_IRQHandler, . - EDMA_0_CH15_IRQHandler + + .align 1 + .thumb_func + .weak GPIO00_IRQHandler + .type GPIO00_IRQHandler, %function +GPIO00_IRQHandler: + ldr r0,=GPIO00_DriverIRQHandler + bx r0 + .size GPIO00_IRQHandler, . - GPIO00_IRQHandler + + .align 1 + .thumb_func + .weak GPIO01_IRQHandler + .type GPIO01_IRQHandler, %function +GPIO01_IRQHandler: + ldr r0,=GPIO01_DriverIRQHandler + bx r0 + .size GPIO01_IRQHandler, . - GPIO01_IRQHandler + + .align 1 + .thumb_func + .weak GPIO10_IRQHandler + .type GPIO10_IRQHandler, %function +GPIO10_IRQHandler: + ldr r0,=GPIO10_DriverIRQHandler + bx r0 + .size GPIO10_IRQHandler, . - GPIO10_IRQHandler + + .align 1 + .thumb_func + .weak GPIO11_IRQHandler + .type GPIO11_IRQHandler, %function +GPIO11_IRQHandler: + ldr r0,=GPIO11_DriverIRQHandler + bx r0 + .size GPIO11_IRQHandler, . - GPIO11_IRQHandler + + .align 1 + .thumb_func + .weak GPIO20_IRQHandler + .type GPIO20_IRQHandler, %function +GPIO20_IRQHandler: + ldr r0,=GPIO20_DriverIRQHandler + bx r0 + .size GPIO20_IRQHandler, . - GPIO20_IRQHandler + + .align 1 + .thumb_func + .weak GPIO21_IRQHandler + .type GPIO21_IRQHandler, %function +GPIO21_IRQHandler: + ldr r0,=GPIO21_DriverIRQHandler + bx r0 + .size GPIO21_IRQHandler, . - GPIO21_IRQHandler + + .align 1 + .thumb_func + .weak GPIO30_IRQHandler + .type GPIO30_IRQHandler, %function +GPIO30_IRQHandler: + ldr r0,=GPIO30_DriverIRQHandler + bx r0 + .size GPIO30_IRQHandler, . - GPIO30_IRQHandler + + .align 1 + .thumb_func + .weak GPIO31_IRQHandler + .type GPIO31_IRQHandler, %function +GPIO31_IRQHandler: + ldr r0,=GPIO31_DriverIRQHandler + bx r0 + .size GPIO31_IRQHandler, . - GPIO31_IRQHandler + + .align 1 + .thumb_func + .weak GPIO40_IRQHandler + .type GPIO40_IRQHandler, %function +GPIO40_IRQHandler: + ldr r0,=GPIO40_DriverIRQHandler + bx r0 + .size GPIO40_IRQHandler, . - GPIO40_IRQHandler + + .align 1 + .thumb_func + .weak GPIO41_IRQHandler + .type GPIO41_IRQHandler, %function +GPIO41_IRQHandler: + ldr r0,=GPIO41_DriverIRQHandler + bx r0 + .size GPIO41_IRQHandler, . - GPIO41_IRQHandler + + .align 1 + .thumb_func + .weak GPIO50_IRQHandler + .type GPIO50_IRQHandler, %function +GPIO50_IRQHandler: + ldr r0,=GPIO50_DriverIRQHandler + bx r0 + .size GPIO50_IRQHandler, . - GPIO50_IRQHandler + + .align 1 + .thumb_func + .weak GPIO51_IRQHandler + .type GPIO51_IRQHandler, %function +GPIO51_IRQHandler: + ldr r0,=GPIO51_DriverIRQHandler + bx r0 + .size GPIO51_IRQHandler, . - GPIO51_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved49_IRQHandler + .type Reserved49_IRQHandler, %function +Reserved49_IRQHandler: + ldr r0,=Reserved49_DriverIRQHandler + bx r0 + .size Reserved49_IRQHandler, . - Reserved49_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM0_IRQHandler + .type LP_FLEXCOMM0_IRQHandler, %function +LP_FLEXCOMM0_IRQHandler: + ldr r0,=LP_FLEXCOMM0_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM0_IRQHandler, . - LP_FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM1_IRQHandler + .type LP_FLEXCOMM1_IRQHandler, %function +LP_FLEXCOMM1_IRQHandler: + ldr r0,=LP_FLEXCOMM1_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM1_IRQHandler, . - LP_FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM2_IRQHandler + .type LP_FLEXCOMM2_IRQHandler, %function +LP_FLEXCOMM2_IRQHandler: + ldr r0,=LP_FLEXCOMM2_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM2_IRQHandler, . - LP_FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM3_IRQHandler + .type LP_FLEXCOMM3_IRQHandler, %function +LP_FLEXCOMM3_IRQHandler: + ldr r0,=LP_FLEXCOMM3_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM3_IRQHandler, . - LP_FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM4_IRQHandler + .type LP_FLEXCOMM4_IRQHandler, %function +LP_FLEXCOMM4_IRQHandler: + ldr r0,=LP_FLEXCOMM4_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM4_IRQHandler, . - LP_FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM5_IRQHandler + .type LP_FLEXCOMM5_IRQHandler, %function +LP_FLEXCOMM5_IRQHandler: + ldr r0,=LP_FLEXCOMM5_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM5_IRQHandler, . - LP_FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM6_IRQHandler + .type LP_FLEXCOMM6_IRQHandler, %function +LP_FLEXCOMM6_IRQHandler: + ldr r0,=LP_FLEXCOMM6_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM6_IRQHandler, . - LP_FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak LP_FLEXCOMM7_IRQHandler + .type LP_FLEXCOMM7_IRQHandler, %function +LP_FLEXCOMM7_IRQHandler: + ldr r0,=LP_FLEXCOMM7_DriverIRQHandler + bx r0 + .size LP_FLEXCOMM7_IRQHandler, . - LP_FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak ADC1_IRQHandler + .type ADC1_IRQHandler, %function +ADC1_IRQHandler: + ldr r0,=ADC1_DriverIRQHandler + bx r0 + .size ADC1_IRQHandler, . - ADC1_IRQHandler + + .align 1 + .thumb_func + .weak PINT0_IRQHandler + .type PINT0_IRQHandler, %function +PINT0_IRQHandler: + ldr r0,=PINT0_DriverIRQHandler + bx r0 + .size PINT0_IRQHandler, . - PINT0_IRQHandler + + .align 1 + .thumb_func + .weak PDM_EVENT_IRQHandler + .type PDM_EVENT_IRQHandler, %function +PDM_EVENT_IRQHandler: + ldr r0,=PDM_EVENT_DriverIRQHandler + bx r0 + .size PDM_EVENT_IRQHandler, . - PDM_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved65_IRQHandler + .type Reserved65_IRQHandler, %function +Reserved65_IRQHandler: + ldr r0,=Reserved65_DriverIRQHandler + bx r0 + .size Reserved65_IRQHandler, . - Reserved65_IRQHandler + + .align 1 + .thumb_func + .weak Reserved66_IRQHandler + .type Reserved66_IRQHandler, %function +Reserved66_IRQHandler: + ldr r0,=Reserved66_DriverIRQHandler + bx r0 + .size Reserved66_IRQHandler, . - Reserved66_IRQHandler + + .align 1 + .thumb_func + .weak USB0_DCD_IRQHandler + .type USB0_DCD_IRQHandler, %function +USB0_DCD_IRQHandler: + ldr r0,=USB0_DCD_DriverIRQHandler + bx r0 + .size USB0_DCD_IRQHandler, . - USB0_DCD_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak SMARTDMA_IRQHandler + .type SMARTDMA_IRQHandler, %function +SMARTDMA_IRQHandler: + ldr r0,=SMARTDMA_DriverIRQHandler + bx r0 + .size SMARTDMA_IRQHandler, . - SMARTDMA_IRQHandler + + .align 1 + .thumb_func + .weak Reserved70_IRQHandler + .type Reserved70_IRQHandler, %function +Reserved70_IRQHandler: + ldr r0,=Reserved70_DriverIRQHandler + bx r0 + .size Reserved70_IRQHandler, . - Reserved70_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved74_IRQHandler + .type Reserved74_IRQHandler, %function +Reserved74_IRQHandler: + ldr r0,=Reserved74_DriverIRQHandler + bx r0 + .size Reserved74_IRQHandler, . - Reserved74_IRQHandler + + .align 1 + .thumb_func + .weak SAI0_IRQHandler + .type SAI0_IRQHandler, %function +SAI0_IRQHandler: + ldr r0,=SAI0_DriverIRQHandler + bx r0 + .size SAI0_IRQHandler, . - SAI0_IRQHandler + + .align 1 + .thumb_func + .weak SAI1_IRQHandler + .type SAI1_IRQHandler, %function +SAI1_IRQHandler: + ldr r0,=SAI1_DriverIRQHandler + bx r0 + .size SAI1_IRQHandler, . - SAI1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved77_IRQHandler + .type Reserved77_IRQHandler, %function +Reserved77_IRQHandler: + ldr r0,=Reserved77_DriverIRQHandler + bx r0 + .size Reserved77_IRQHandler, . - Reserved77_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQHandler + .type CAN0_IRQHandler, %function +CAN0_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_IRQHandler, . - CAN0_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_IRQHandler + .type CAN1_IRQHandler, %function +CAN1_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_IRQHandler, . - CAN1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved80_IRQHandler + .type Reserved80_IRQHandler, %function +Reserved80_IRQHandler: + ldr r0,=Reserved80_DriverIRQHandler + bx r0 + .size Reserved80_IRQHandler, . - Reserved80_IRQHandler + + .align 1 + .thumb_func + .weak Reserved81_IRQHandler + .type Reserved81_IRQHandler, %function +Reserved81_IRQHandler: + ldr r0,=Reserved81_DriverIRQHandler + bx r0 + .size Reserved81_IRQHandler, . - Reserved81_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_PHY_IRQHandler + .type USB1_HS_PHY_IRQHandler, %function +USB1_HS_PHY_IRQHandler: + ldr r0,=USB1_HS_PHY_DriverIRQHandler + bx r0 + .size USB1_HS_PHY_IRQHandler, . - USB1_HS_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_HS_IRQHandler + .type USB1_HS_IRQHandler, %function +USB1_HS_IRQHandler: + ldr r0,=USB1_HS_DriverIRQHandler + bx r0 + .size USB1_HS_IRQHandler, . - USB1_HS_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak Reserved85_IRQHandler + .type Reserved85_IRQHandler, %function +Reserved85_IRQHandler: + ldr r0,=Reserved85_DriverIRQHandler + bx r0 + .size Reserved85_IRQHandler, . - Reserved85_IRQHandler + + .align 1 + .thumb_func + .weak Reserved86_IRQHandler + .type Reserved86_IRQHandler, %function +Reserved86_IRQHandler: + ldr r0,=Reserved86_DriverIRQHandler + bx r0 + .size Reserved86_IRQHandler, . - Reserved86_IRQHandler + + .align 1 + .thumb_func + .weak Freqme_IRQHandler + .type Freqme_IRQHandler, %function +Freqme_IRQHandler: + ldr r0,=Freqme_DriverIRQHandler + bx r0 + .size Freqme_IRQHandler, . - Freqme_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak ELS_IRQHandler + .type ELS_IRQHandler, %function +ELS_IRQHandler: + ldr r0,=ELS_DriverIRQHandler + bx r0 + .size ELS_IRQHandler, . - ELS_IRQHandler + + .align 1 + .thumb_func + .weak PKC_IRQHandler + .type PKC_IRQHandler, %function +PKC_IRQHandler: + ldr r0,=PKC_DriverIRQHandler + bx r0 + .size PKC_IRQHandler, . - PKC_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak Reserved92_IRQHandler + .type Reserved92_IRQHandler, %function +Reserved92_IRQHandler: + ldr r0,=Reserved92_DriverIRQHandler + bx r0 + .size Reserved92_IRQHandler, . - Reserved92_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH0_IRQHandler + .type EDMA_1_CH0_IRQHandler, %function +EDMA_1_CH0_IRQHandler: + ldr r0,=EDMA_1_CH0_DriverIRQHandler + bx r0 + .size EDMA_1_CH0_IRQHandler, . - EDMA_1_CH0_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH1_IRQHandler + .type EDMA_1_CH1_IRQHandler, %function +EDMA_1_CH1_IRQHandler: + ldr r0,=EDMA_1_CH1_DriverIRQHandler + bx r0 + .size EDMA_1_CH1_IRQHandler, . - EDMA_1_CH1_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH2_IRQHandler + .type EDMA_1_CH2_IRQHandler, %function +EDMA_1_CH2_IRQHandler: + ldr r0,=EDMA_1_CH2_DriverIRQHandler + bx r0 + .size EDMA_1_CH2_IRQHandler, . - EDMA_1_CH2_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH3_IRQHandler + .type EDMA_1_CH3_IRQHandler, %function +EDMA_1_CH3_IRQHandler: + ldr r0,=EDMA_1_CH3_DriverIRQHandler + bx r0 + .size EDMA_1_CH3_IRQHandler, . - EDMA_1_CH3_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH4_IRQHandler + .type EDMA_1_CH4_IRQHandler, %function +EDMA_1_CH4_IRQHandler: + ldr r0,=EDMA_1_CH4_DriverIRQHandler + bx r0 + .size EDMA_1_CH4_IRQHandler, . - EDMA_1_CH4_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH5_IRQHandler + .type EDMA_1_CH5_IRQHandler, %function +EDMA_1_CH5_IRQHandler: + ldr r0,=EDMA_1_CH5_DriverIRQHandler + bx r0 + .size EDMA_1_CH5_IRQHandler, . - EDMA_1_CH5_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH6_IRQHandler + .type EDMA_1_CH6_IRQHandler, %function +EDMA_1_CH6_IRQHandler: + ldr r0,=EDMA_1_CH6_DriverIRQHandler + bx r0 + .size EDMA_1_CH6_IRQHandler, . - EDMA_1_CH6_IRQHandler + + .align 1 + .thumb_func + .weak EDMA_1_CH7_IRQHandler + .type EDMA_1_CH7_IRQHandler, %function +EDMA_1_CH7_IRQHandler: + ldr r0,=EDMA_1_CH7_DriverIRQHandler + bx r0 + .size EDMA_1_CH7_IRQHandler, . - EDMA_1_CH7_IRQHandler + + .align 1 + .thumb_func + .weak Reserved101_IRQHandler + .type Reserved101_IRQHandler, %function +Reserved101_IRQHandler: + ldr r0,=Reserved101_DriverIRQHandler + bx r0 + .size Reserved101_IRQHandler, . - Reserved101_IRQHandler + + .align 1 + .thumb_func + .weak Reserved102_IRQHandler + .type Reserved102_IRQHandler, %function +Reserved102_IRQHandler: + ldr r0,=Reserved102_DriverIRQHandler + bx r0 + .size Reserved102_IRQHandler, . - Reserved102_IRQHandler + + .align 1 + .thumb_func + .weak Reserved103_IRQHandler + .type Reserved103_IRQHandler, %function +Reserved103_IRQHandler: + ldr r0,=Reserved103_DriverIRQHandler + bx r0 + .size Reserved103_IRQHandler, . - Reserved103_IRQHandler + + .align 1 + .thumb_func + .weak Reserved104_IRQHandler + .type Reserved104_IRQHandler, %function +Reserved104_IRQHandler: + ldr r0,=Reserved104_DriverIRQHandler + bx r0 + .size Reserved104_IRQHandler, . - Reserved104_IRQHandler + + .align 1 + .thumb_func + .weak Reserved105_IRQHandler + .type Reserved105_IRQHandler, %function +Reserved105_IRQHandler: + ldr r0,=Reserved105_DriverIRQHandler + bx r0 + .size Reserved105_IRQHandler, . - Reserved105_IRQHandler + + .align 1 + .thumb_func + .weak Reserved106_IRQHandler + .type Reserved106_IRQHandler, %function +Reserved106_IRQHandler: + ldr r0,=Reserved106_DriverIRQHandler + bx r0 + .size Reserved106_IRQHandler, . - Reserved106_IRQHandler + + .align 1 + .thumb_func + .weak Reserved107_IRQHandler + .type Reserved107_IRQHandler, %function +Reserved107_IRQHandler: + ldr r0,=Reserved107_DriverIRQHandler + bx r0 + .size Reserved107_IRQHandler, . - Reserved107_IRQHandler + + .align 1 + .thumb_func + .weak Reserved108_IRQHandler + .type Reserved108_IRQHandler, %function +Reserved108_IRQHandler: + ldr r0,=Reserved108_DriverIRQHandler + bx r0 + .size Reserved108_IRQHandler, . - Reserved108_IRQHandler + + .align 1 + .thumb_func + .weak CDOG0_IRQHandler + .type CDOG0_IRQHandler, %function +CDOG0_IRQHandler: + ldr r0,=CDOG0_DriverIRQHandler + bx r0 + .size CDOG0_IRQHandler, . - CDOG0_IRQHandler + + .align 1 + .thumb_func + .weak CDOG1_IRQHandler + .type CDOG1_IRQHandler, %function +CDOG1_IRQHandler: + ldr r0,=CDOG1_DriverIRQHandler + bx r0 + .size CDOG1_IRQHandler, . - CDOG1_IRQHandler + + .align 1 + .thumb_func + .weak I3C0_IRQHandler + .type I3C0_IRQHandler, %function +I3C0_IRQHandler: + ldr r0,=I3C0_DriverIRQHandler + bx r0 + .size I3C0_IRQHandler, . - I3C0_IRQHandler + + .align 1 + .thumb_func + .weak I3C1_IRQHandler + .type I3C1_IRQHandler, %function +I3C1_IRQHandler: + ldr r0,=I3C1_DriverIRQHandler + bx r0 + .size I3C1_IRQHandler, . - I3C1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved113_IRQHandler + .type Reserved113_IRQHandler, %function +Reserved113_IRQHandler: + ldr r0,=Reserved113_DriverIRQHandler + bx r0 + .size Reserved113_IRQHandler, . - Reserved113_IRQHandler + + .align 1 + .thumb_func + .weak GDET_IRQHandler + .type GDET_IRQHandler, %function +GDET_IRQHandler: + ldr r0,=GDET_DriverIRQHandler + bx r0 + .size GDET_IRQHandler, . - GDET_IRQHandler + + .align 1 + .thumb_func + .weak VBAT0_IRQHandler + .type VBAT0_IRQHandler, %function +VBAT0_IRQHandler: + ldr r0,=VBAT0_DriverIRQHandler + bx r0 + .size VBAT0_IRQHandler, . - VBAT0_IRQHandler + + .align 1 + .thumb_func + .weak EWM0_IRQHandler + .type EWM0_IRQHandler, %function +EWM0_IRQHandler: + ldr r0,=EWM0_DriverIRQHandler + bx r0 + .size EWM0_IRQHandler, . - EWM0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved117_IRQHandler + .type Reserved117_IRQHandler, %function +Reserved117_IRQHandler: + ldr r0,=Reserved117_DriverIRQHandler + bx r0 + .size Reserved117_IRQHandler, . - Reserved117_IRQHandler + + .align 1 + .thumb_func + .weak Reserved118_IRQHandler + .type Reserved118_IRQHandler, %function +Reserved118_IRQHandler: + ldr r0,=Reserved118_DriverIRQHandler + bx r0 + .size Reserved118_IRQHandler, . - Reserved118_IRQHandler + + .align 1 + .thumb_func + .weak Reserved119_IRQHandler + .type Reserved119_IRQHandler, %function +Reserved119_IRQHandler: + ldr r0,=Reserved119_DriverIRQHandler + bx r0 + .size Reserved119_IRQHandler, . - Reserved119_IRQHandler + + .align 1 + .thumb_func + .weak Reserved120_IRQHandler + .type Reserved120_IRQHandler, %function +Reserved120_IRQHandler: + ldr r0,=Reserved120_DriverIRQHandler + bx r0 + .size Reserved120_IRQHandler, . - Reserved120_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO_IRQHandler + .type FLEXIO_IRQHandler, %function +FLEXIO_IRQHandler: + ldr r0,=FLEXIO_DriverIRQHandler + bx r0 + .size FLEXIO_IRQHandler, . - FLEXIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved122_IRQHandler + .type Reserved122_IRQHandler, %function +Reserved122_IRQHandler: + ldr r0,=Reserved122_DriverIRQHandler + bx r0 + .size Reserved122_IRQHandler, . - Reserved122_IRQHandler + + .align 1 + .thumb_func + .weak Reserved123_IRQHandler + .type Reserved123_IRQHandler, %function +Reserved123_IRQHandler: + ldr r0,=Reserved123_DriverIRQHandler + bx r0 + .size Reserved123_IRQHandler, . - Reserved123_IRQHandler + + .align 1 + .thumb_func + .weak Reserved124_IRQHandler + .type Reserved124_IRQHandler, %function +Reserved124_IRQHandler: + ldr r0,=Reserved124_DriverIRQHandler + bx r0 + .size Reserved124_IRQHandler, . - Reserved124_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP0_IRQHandler + .type HSCMP0_IRQHandler, %function +HSCMP0_IRQHandler: + ldr r0,=HSCMP0_DriverIRQHandler + bx r0 + .size HSCMP0_IRQHandler, . - HSCMP0_IRQHandler + + .align 1 + .thumb_func + .weak HSCMP1_IRQHandler + .type HSCMP1_IRQHandler, %function +HSCMP1_IRQHandler: + ldr r0,=HSCMP1_DriverIRQHandler + bx r0 + .size HSCMP1_IRQHandler, . - HSCMP1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved127_IRQHandler + .type Reserved127_IRQHandler, %function +Reserved127_IRQHandler: + ldr r0,=Reserved127_DriverIRQHandler + bx r0 + .size Reserved127_IRQHandler, . - Reserved127_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD_ERROR_IRQHandler + .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function +FLEXPWM0_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_FAULT_IRQHandler + .type FLEXPWM0_FAULT_IRQHandler, %function +FLEXPWM0_FAULT_IRQHandler: + ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE0_IRQHandler + .type FLEXPWM0_SUBMODULE0_IRQHandler, %function +FLEXPWM0_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE0_IRQHandler, . - FLEXPWM0_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE1_IRQHandler + .type FLEXPWM0_SUBMODULE1_IRQHandler, %function +FLEXPWM0_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE1_IRQHandler, . - FLEXPWM0_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE2_IRQHandler + .type FLEXPWM0_SUBMODULE2_IRQHandler, %function +FLEXPWM0_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE2_IRQHandler, . - FLEXPWM0_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE3_IRQHandler + .type FLEXPWM0_SUBMODULE3_IRQHandler, %function +FLEXPWM0_SUBMODULE3_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE3_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE3_IRQHandler, . - FLEXPWM0_SUBMODULE3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD_ERROR_IRQHandler + .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function +FLEXPWM1_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_FAULT_IRQHandler + .type FLEXPWM1_FAULT_IRQHandler, %function +FLEXPWM1_FAULT_IRQHandler: + ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE0_IRQHandler + .type FLEXPWM1_SUBMODULE0_IRQHandler, %function +FLEXPWM1_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE0_IRQHandler, . - FLEXPWM1_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE1_IRQHandler + .type FLEXPWM1_SUBMODULE1_IRQHandler, %function +FLEXPWM1_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE1_IRQHandler, . - FLEXPWM1_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE2_IRQHandler + .type FLEXPWM1_SUBMODULE2_IRQHandler, %function +FLEXPWM1_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE2_IRQHandler, . - FLEXPWM1_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE3_IRQHandler + .type FLEXPWM1_SUBMODULE3_IRQHandler, %function +FLEXPWM1_SUBMODULE3_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE3_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE3_IRQHandler, . - FLEXPWM1_SUBMODULE3_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler + bx r0 + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler + bx r0 + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_WDG_SAB_IRQHandler + .type QDC0_WDG_SAB_IRQHandler, %function +QDC0_WDG_SAB_IRQHandler: + ldr r0,=QDC0_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_IDX_IRQHandler + .type QDC0_IDX_IRQHandler, %function +QDC0_IDX_IRQHandler: + ldr r0,=QDC0_IDX_DriverIRQHandler + bx r0 + .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler + bx r0 + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler + bx r0 + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_WDG_SAB_IRQHandler + .type QDC1_WDG_SAB_IRQHandler, %function +QDC1_WDG_SAB_IRQHandler: + ldr r0,=QDC1_WDG_SAB_DriverIRQHandler + bx r0 + .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_IDX_IRQHandler + .type QDC1_IDX_IRQHandler, %function +QDC1_IDX_IRQHandler: + ldr r0,=QDC1_IDX_DriverIRQHandler + bx r0 + .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler + + .align 1 + .thumb_func + .weak ITRC0_IRQHandler + .type ITRC0_IRQHandler, %function +ITRC0_IRQHandler: + ldr r0,=ITRC0_DriverIRQHandler + bx r0 + .size ITRC0_IRQHandler, . - ITRC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved149_IRQHandler + .type Reserved149_IRQHandler, %function +Reserved149_IRQHandler: + ldr r0,=Reserved149_DriverIRQHandler + bx r0 + .size Reserved149_IRQHandler, . - Reserved149_IRQHandler + + .align 1 + .thumb_func + .weak ELS_ERR_IRQHandler + .type ELS_ERR_IRQHandler, %function +ELS_ERR_IRQHandler: + ldr r0,=ELS_ERR_DriverIRQHandler + bx r0 + .size ELS_ERR_IRQHandler, . - ELS_ERR_IRQHandler + + .align 1 + .thumb_func + .weak PKC_ERR_IRQHandler + .type PKC_ERR_IRQHandler, %function +PKC_ERR_IRQHandler: + ldr r0,=PKC_ERR_DriverIRQHandler + bx r0 + .size PKC_ERR_IRQHandler, . - PKC_ERR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_SINGLE_BIT_ERROR_IRQHandler + .type ERM_SINGLE_BIT_ERROR_IRQHandler, %function +ERM_SINGLE_BIT_ERROR_IRQHandler: + ldr r0,=ERM_SINGLE_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_SINGLE_BIT_ERROR_IRQHandler, . - ERM_SINGLE_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak ERM_MULTI_BIT_ERROR_IRQHandler + .type ERM_MULTI_BIT_ERROR_IRQHandler, %function +ERM_MULTI_BIT_ERROR_IRQHandler: + ldr r0,=ERM_MULTI_BIT_ERROR_DriverIRQHandler + bx r0 + .size ERM_MULTI_BIT_ERROR_IRQHandler, . - ERM_MULTI_BIT_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FMU0_IRQHandler + .type FMU0_IRQHandler, %function +FMU0_IRQHandler: + ldr r0,=FMU0_DriverIRQHandler + bx r0 + .size FMU0_IRQHandler, . - FMU0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved155_IRQHandler + .type Reserved155_IRQHandler, %function +Reserved155_IRQHandler: + ldr r0,=Reserved155_DriverIRQHandler + bx r0 + .size Reserved155_IRQHandler, . - Reserved155_IRQHandler + + .align 1 + .thumb_func + .weak Reserved156_IRQHandler + .type Reserved156_IRQHandler, %function +Reserved156_IRQHandler: + ldr r0,=Reserved156_DriverIRQHandler + bx r0 + .size Reserved156_IRQHandler, . - Reserved156_IRQHandler + + .align 1 + .thumb_func + .weak Reserved157_IRQHandler + .type Reserved157_IRQHandler, %function +Reserved157_IRQHandler: + ldr r0,=Reserved157_DriverIRQHandler + bx r0 + .size Reserved157_IRQHandler, . - Reserved157_IRQHandler + + .align 1 + .thumb_func + .weak Reserved158_IRQHandler + .type Reserved158_IRQHandler, %function +Reserved158_IRQHandler: + ldr r0,=Reserved158_DriverIRQHandler + bx r0 + .size Reserved158_IRQHandler, . - Reserved158_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR0_IRQHandler + .type LPTMR0_IRQHandler, %function +LPTMR0_IRQHandler: + ldr r0,=LPTMR0_DriverIRQHandler + bx r0 + .size LPTMR0_IRQHandler, . - LPTMR0_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR1_IRQHandler + .type LPTMR1_IRQHandler, %function +LPTMR1_IRQHandler: + ldr r0,=LPTMR1_DriverIRQHandler + bx r0 + .size LPTMR1_IRQHandler, . - LPTMR1_IRQHandler + + .align 1 + .thumb_func + .weak SCG_IRQHandler + .type SCG_IRQHandler, %function +SCG_IRQHandler: + ldr r0,=SCG_DriverIRQHandler + bx r0 + .size SCG_IRQHandler, . - SCG_IRQHandler + + .align 1 + .thumb_func + .weak SPC_IRQHandler + .type SPC_IRQHandler, %function +SPC_IRQHandler: + ldr r0,=SPC_DriverIRQHandler + bx r0 + .size SPC_IRQHandler, . - SPC_IRQHandler + + .align 1 + .thumb_func + .weak WUU_IRQHandler + .type WUU_IRQHandler, %function +WUU_IRQHandler: + ldr r0,=WUU_DriverIRQHandler + bx r0 + .size WUU_IRQHandler, . - WUU_IRQHandler + + .align 1 + .thumb_func + .weak PORT_EFT_IRQHandler + .type PORT_EFT_IRQHandler, %function +PORT_EFT_IRQHandler: + ldr r0,=PORT_EFT_DriverIRQHandler + bx r0 + .size PORT_EFT_IRQHandler, . - PORT_EFT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved165_IRQHandler + .type Reserved165_IRQHandler, %function +Reserved165_IRQHandler: + ldr r0,=Reserved165_DriverIRQHandler + bx r0 + .size Reserved165_IRQHandler, . - Reserved165_IRQHandler + + .align 1 + .thumb_func + .weak Reserved166_IRQHandler + .type Reserved166_IRQHandler, %function +Reserved166_IRQHandler: + ldr r0,=Reserved166_DriverIRQHandler + bx r0 + .size Reserved166_IRQHandler, . - Reserved166_IRQHandler + + .align 1 + .thumb_func + .weak Reserved167_IRQHandler + .type Reserved167_IRQHandler, %function +Reserved167_IRQHandler: + ldr r0,=Reserved167_DriverIRQHandler + bx r0 + .size Reserved167_IRQHandler, . - Reserved167_IRQHandler + + .align 1 + .thumb_func + .weak WWDT0_IRQHandler + .type WWDT0_IRQHandler, %function +WWDT0_IRQHandler: + ldr r0,=WWDT0_DriverIRQHandler + bx r0 + .size WWDT0_IRQHandler, . - WWDT0_IRQHandler + + .align 1 + .thumb_func + .weak WWDT1_IRQHandler + .type WWDT1_IRQHandler, %function +WWDT1_IRQHandler: + ldr r0,=WWDT1_DriverIRQHandler + bx r0 + .size WWDT1_IRQHandler, . - WWDT1_IRQHandler + + .align 1 + .thumb_func + .weak CMC0_IRQHandler + .type CMC0_IRQHandler, %function +CMC0_IRQHandler: + ldr r0,=CMC0_DriverIRQHandler + bx r0 + .size CMC0_IRQHandler, . - CMC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved171_IRQHandler + .type Reserved171_IRQHandler, %function +Reserved171_IRQHandler: + ldr r0,=Reserved171_DriverIRQHandler + bx r0 + .size Reserved171_IRQHandler, . - Reserved171_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler OR_DriverIRQHandler + def_irq_handler EDMA_0_CH0_DriverIRQHandler + def_irq_handler EDMA_0_CH1_DriverIRQHandler + def_irq_handler EDMA_0_CH2_DriverIRQHandler + def_irq_handler EDMA_0_CH3_DriverIRQHandler + def_irq_handler EDMA_0_CH4_DriverIRQHandler + def_irq_handler EDMA_0_CH5_DriverIRQHandler + def_irq_handler EDMA_0_CH6_DriverIRQHandler + def_irq_handler EDMA_0_CH7_DriverIRQHandler + def_irq_handler EDMA_0_CH8_DriverIRQHandler + def_irq_handler EDMA_0_CH9_DriverIRQHandler + def_irq_handler EDMA_0_CH10_DriverIRQHandler + def_irq_handler EDMA_0_CH11_DriverIRQHandler + def_irq_handler EDMA_0_CH12_DriverIRQHandler + def_irq_handler EDMA_0_CH13_DriverIRQHandler + def_irq_handler EDMA_0_CH14_DriverIRQHandler + def_irq_handler EDMA_0_CH15_DriverIRQHandler + def_irq_handler GPIO00_DriverIRQHandler + def_irq_handler GPIO01_DriverIRQHandler + def_irq_handler GPIO10_DriverIRQHandler + def_irq_handler GPIO11_DriverIRQHandler + def_irq_handler GPIO20_DriverIRQHandler + def_irq_handler GPIO21_DriverIRQHandler + def_irq_handler GPIO30_DriverIRQHandler + def_irq_handler GPIO31_DriverIRQHandler + def_irq_handler GPIO40_DriverIRQHandler + def_irq_handler GPIO41_DriverIRQHandler + def_irq_handler GPIO50_DriverIRQHandler + def_irq_handler GPIO51_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler MRT0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler Reserved49_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM0_DriverIRQHandler + def_irq_handler LP_FLEXCOMM1_DriverIRQHandler + def_irq_handler LP_FLEXCOMM2_DriverIRQHandler + def_irq_handler LP_FLEXCOMM3_DriverIRQHandler + def_irq_handler LP_FLEXCOMM4_DriverIRQHandler + def_irq_handler LP_FLEXCOMM5_DriverIRQHandler + def_irq_handler LP_FLEXCOMM6_DriverIRQHandler + def_irq_handler LP_FLEXCOMM7_DriverIRQHandler + def_irq_handler Reserved59_DriverIRQHandler + def_irq_handler Reserved60_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler ADC1_DriverIRQHandler + def_irq_handler PINT0_DriverIRQHandler + def_irq_handler PDM_EVENT_DriverIRQHandler + def_irq_handler Reserved65_DriverIRQHandler + def_irq_handler Reserved66_DriverIRQHandler + def_irq_handler USB0_DCD_DriverIRQHandler + def_irq_handler RTC_DriverIRQHandler + def_irq_handler SMARTDMA_DriverIRQHandler + def_irq_handler Reserved70_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler Reserved74_DriverIRQHandler + def_irq_handler SAI0_DriverIRQHandler + def_irq_handler SAI1_DriverIRQHandler + def_irq_handler Reserved77_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler CAN1_DriverIRQHandler + def_irq_handler Reserved80_DriverIRQHandler + def_irq_handler Reserved81_DriverIRQHandler + def_irq_handler USB1_HS_PHY_DriverIRQHandler + def_irq_handler USB1_HS_DriverIRQHandler + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler + def_irq_handler Reserved85_DriverIRQHandler + def_irq_handler Reserved86_DriverIRQHandler + def_irq_handler Freqme_DriverIRQHandler + def_irq_handler SEC_VIO_DriverIRQHandler + def_irq_handler ELS_DriverIRQHandler + def_irq_handler PKC_DriverIRQHandler + def_irq_handler PUF_DriverIRQHandler + def_irq_handler Reserved92_DriverIRQHandler + def_irq_handler EDMA_1_CH0_DriverIRQHandler + def_irq_handler EDMA_1_CH1_DriverIRQHandler + def_irq_handler EDMA_1_CH2_DriverIRQHandler + def_irq_handler EDMA_1_CH3_DriverIRQHandler + def_irq_handler EDMA_1_CH4_DriverIRQHandler + def_irq_handler EDMA_1_CH5_DriverIRQHandler + def_irq_handler EDMA_1_CH6_DriverIRQHandler + def_irq_handler EDMA_1_CH7_DriverIRQHandler + def_irq_handler Reserved101_DriverIRQHandler + def_irq_handler Reserved102_DriverIRQHandler + def_irq_handler Reserved103_DriverIRQHandler + def_irq_handler Reserved104_DriverIRQHandler + def_irq_handler Reserved105_DriverIRQHandler + def_irq_handler Reserved106_DriverIRQHandler + def_irq_handler Reserved107_DriverIRQHandler + def_irq_handler Reserved108_DriverIRQHandler + def_irq_handler CDOG0_DriverIRQHandler + def_irq_handler CDOG1_DriverIRQHandler + def_irq_handler I3C0_DriverIRQHandler + def_irq_handler I3C1_DriverIRQHandler + def_irq_handler Reserved113_DriverIRQHandler + def_irq_handler GDET_DriverIRQHandler + def_irq_handler VBAT0_DriverIRQHandler + def_irq_handler EWM0_DriverIRQHandler + def_irq_handler Reserved117_DriverIRQHandler + def_irq_handler Reserved118_DriverIRQHandler + def_irq_handler Reserved119_DriverIRQHandler + def_irq_handler Reserved120_DriverIRQHandler + def_irq_handler FLEXIO_DriverIRQHandler + def_irq_handler Reserved122_DriverIRQHandler + def_irq_handler Reserved123_DriverIRQHandler + def_irq_handler Reserved124_DriverIRQHandler + def_irq_handler HSCMP0_DriverIRQHandler + def_irq_handler HSCMP1_DriverIRQHandler + def_irq_handler Reserved127_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE2_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE3_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE3_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WDG_SAB_DriverIRQHandler + def_irq_handler QDC0_IDX_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WDG_SAB_DriverIRQHandler + def_irq_handler QDC1_IDX_DriverIRQHandler + def_irq_handler ITRC0_DriverIRQHandler + def_irq_handler Reserved149_DriverIRQHandler + def_irq_handler ELS_ERR_DriverIRQHandler + def_irq_handler PKC_ERR_DriverIRQHandler + def_irq_handler ERM_SINGLE_BIT_ERROR_DriverIRQHandler + def_irq_handler ERM_MULTI_BIT_ERROR_DriverIRQHandler + def_irq_handler FMU0_DriverIRQHandler + def_irq_handler Reserved155_DriverIRQHandler + def_irq_handler Reserved156_DriverIRQHandler + def_irq_handler Reserved157_DriverIRQHandler + def_irq_handler Reserved158_DriverIRQHandler + def_irq_handler LPTMR0_DriverIRQHandler + def_irq_handler LPTMR1_DriverIRQHandler + def_irq_handler SCG_DriverIRQHandler + def_irq_handler SPC_DriverIRQHandler + def_irq_handler WUU_DriverIRQHandler + def_irq_handler PORT_EFT_DriverIRQHandler + def_irq_handler Reserved165_DriverIRQHandler + def_irq_handler Reserved166_DriverIRQHandler + def_irq_handler Reserved167_DriverIRQHandler + def_irq_handler WWDT0_DriverIRQHandler + def_irq_handler WWDT1_DriverIRQHandler + def_irq_handler CMC0_DriverIRQHandler + def_irq_handler Reserved171_DriverIRQHandler + + .end diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/iar/startup_MCXN236.s b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/iar/startup_MCXN236.s new file mode 100644 index 0000000000..5ecceee877 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/iar/startup_MCXN236.s @@ -0,0 +1,1556 @@ +; ------------------------------------------------------------------------- +; @file: startup_MCXN236.s +; @purpose: CMSIS Cortex-M33 Core Device Startup File +; MCXN236 +; @version: 1.0 +; @date: 2023-10-1 +; @build: b240409 +; ------------------------------------------------------------------------- +; +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2024 NXP +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD SecureFault_Handler ;Secure Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD OR_IRQHandler ;OR IRQ + DCD EDMA_0_CH0_IRQHandler ;eDMA_0_CH0 error or transfer complete + DCD EDMA_0_CH1_IRQHandler ;eDMA_0_CH1 error or transfer complete + DCD EDMA_0_CH2_IRQHandler ;eDMA_0_CH2 error or transfer complete + DCD EDMA_0_CH3_IRQHandler ;eDMA_0_CH3 error or transfer complete + DCD EDMA_0_CH4_IRQHandler ;eDMA_0_CH4 error or transfer complete + DCD EDMA_0_CH5_IRQHandler ;eDMA_0_CH5 error or transfer complete + DCD EDMA_0_CH6_IRQHandler ;eDMA_0_CH6 error or transfer complete + DCD EDMA_0_CH7_IRQHandler ;eDMA_0_CH7 error or transfer complete + DCD EDMA_0_CH8_IRQHandler ;eDMA_0_CH8 error or transfer complete + DCD EDMA_0_CH9_IRQHandler ;eDMA_0_CH9 error or transfer complete + DCD EDMA_0_CH10_IRQHandler ;eDMA_0_CH10 error or transfer complete + DCD EDMA_0_CH11_IRQHandler ;eDMA_0_CH11 error or transfer complete + DCD EDMA_0_CH12_IRQHandler ;eDMA_0_CH12 error or transfer complete + DCD EDMA_0_CH13_IRQHandler ;eDMA_0_CH13 error or transfer complete + DCD EDMA_0_CH14_IRQHandler ;eDMA_0_CH14 error or transfer complete + DCD EDMA_0_CH15_IRQHandler ;eDMA_0_CH15 error or transfer complete + DCD GPIO00_IRQHandler ;GPIO0 interrupt 0 + DCD GPIO01_IRQHandler ;GPIO0 interrupt 1 + DCD GPIO10_IRQHandler ;GPIO1 interrupt 0 + DCD GPIO11_IRQHandler ;GPIO1 interrupt 1 + DCD GPIO20_IRQHandler ;GPIO2 interrupt 0 + DCD GPIO21_IRQHandler ;GPIO2 interrupt 1 + DCD GPIO30_IRQHandler ;GPIO3 interrupt 0 + DCD GPIO31_IRQHandler ;GPIO3 interrupt 1 + DCD GPIO40_IRQHandler ;GPIO4 interrupt 0 + DCD GPIO41_IRQHandler ;GPIO4 interrupt 1 + DCD GPIO50_IRQHandler ;GPIO5 interrupt 0 + DCD GPIO51_IRQHandler ;GPIO5 interrupt 1 + DCD UTICK0_IRQHandler ;Micro-Tick Timer interrupt + DCD MRT0_IRQHandler ;Multi-Rate Timer interrupt + DCD CTIMER0_IRQHandler ;Standard counter/timer 0 interrupt + DCD CTIMER1_IRQHandler ;Standard counter/timer 1 interrupt + DCD Reserved49_IRQHandler ;Reserved interrupt + DCD CTIMER2_IRQHandler ;Standard counter/timer 2 interrupt + DCD LP_FLEXCOMM0_IRQHandler ;LP_FLEXCOMM0 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD LP_FLEXCOMM1_IRQHandler ;LP_FLEXCOMM1 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD LP_FLEXCOMM2_IRQHandler ;LP_FLEXCOMM2 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD LP_FLEXCOMM3_IRQHandler ;LP_FLEXCOMM3 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD LP_FLEXCOMM4_IRQHandler ;LP_FLEXCOMM4 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD LP_FLEXCOMM5_IRQHandler ;LP_FLEXCOMM5 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD LP_FLEXCOMM6_IRQHandler ;LP_FLEXCOMM6 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD LP_FLEXCOMM7_IRQHandler ;LP_FLEXCOMM7 (LPSPI interrupt or LPI2C interrupt or LPUART Receive/Transmit interrupt) + DCD Reserved59_IRQHandler ;Reserved interrupt + DCD Reserved60_IRQHandler ;Reserved interrupt + DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 - General Purpose interrupt + DCD ADC1_IRQHandler ;Analog-to-Digital Converter 1 - General Purpose interrupt + DCD PINT0_IRQHandler ;Pin Interrupt Pattern Match Interrupt + DCD PDM_EVENT_IRQHandler ;Microphone Interface interrupt + DCD Reserved65_IRQHandler ;Reserved interrupt + DCD Reserved66_IRQHandler ;Reserved interrupt + DCD USB0_DCD_IRQHandler ;Universal Serial Bus - Device Charge Detect interrupt + DCD RTC_IRQHandler ;RTC Subsystem interrupt (RTC interrupt or Wake timer interrupt) + DCD SMARTDMA_IRQHandler ;SmartDMA_IRQ + DCD Reserved70_IRQHandler ;Reserved interrupt + DCD CTIMER3_IRQHandler ;Standard counter/timer 3 interrupt + DCD CTIMER4_IRQHandler ;Standard counter/timer 4 interrupt + DCD OS_EVENT_IRQHandler ;OS event timer interrupt + DCD Reserved74_IRQHandler ;Reserved interrupt + DCD SAI0_IRQHandler ;Serial Audio Interface 0 interrupt + DCD SAI1_IRQHandler ;Serial Audio Interface 1 interrupt + DCD Reserved77_IRQHandler ;Reserved interrupt + DCD CAN0_IRQHandler ;Controller Area Network 0 interrupt + DCD CAN1_IRQHandler ;Controller Area Network 1 interrupt + DCD Reserved80_IRQHandler ;Reserved interrupt + DCD Reserved81_IRQHandler ;Reserved interrupt + DCD USB1_HS_PHY_IRQHandler ;USBHS DCD or USBHS Phy interrupt + DCD USB1_HS_IRQHandler ;USB High Speed OTG Controller interrupt + DCD SEC_HYPERVISOR_CALL_IRQHandler ;AHB Secure Controller hypervisor call interrupt + DCD Reserved85_IRQHandler ;Reserved interrupt + DCD Reserved86_IRQHandler ;Reserved interrupt + DCD Freqme_IRQHandler ;Frequency Measurement interrupt + DCD SEC_VIO_IRQHandler ;Secure violation interrupt (Memory Block Checker interrupt or secure AHB matrix violation interrupt) + DCD ELS_IRQHandler ;ELS interrupt + DCD PKC_IRQHandler ;PKC interrupt + DCD PUF_IRQHandler ;Physical Unclonable Function interrupt + DCD Reserved92_IRQHandler ;Reserved interrupt + DCD EDMA_1_CH0_IRQHandler ;eDMA_1_CH0 error or transfer complete + DCD EDMA_1_CH1_IRQHandler ;eDMA_1_CH1 error or transfer complete + DCD EDMA_1_CH2_IRQHandler ;eDMA_1_CH2 error or transfer complete + DCD EDMA_1_CH3_IRQHandler ;eDMA_1_CH3 error or transfer complete + DCD EDMA_1_CH4_IRQHandler ;eDMA_1_CH4 error or transfer complete + DCD EDMA_1_CH5_IRQHandler ;eDMA_1_CH5 error or transfer complete + DCD EDMA_1_CH6_IRQHandler ;eDMA_1_CH6 error or transfer complete + DCD EDMA_1_CH7_IRQHandler ;eDMA_1_CH7 error or transfer complete + DCD Reserved101_IRQHandler ;Reserved interrupt + DCD Reserved102_IRQHandler ;Reserved interrupt + DCD Reserved103_IRQHandler ;Reserved interrupt + DCD Reserved104_IRQHandler ;Reserved interrupt + DCD Reserved105_IRQHandler ;Reserved interrupt + DCD Reserved106_IRQHandler ;Reserved interrupt + DCD Reserved107_IRQHandler ;Reserved interrupt + DCD Reserved108_IRQHandler ;Reserved interrupt + DCD CDOG0_IRQHandler ;Code Watchdog Timer 0 interrupt + DCD CDOG1_IRQHandler ;Code Watchdog Timer 1 interrupt + DCD I3C0_IRQHandler ;Improved Inter Integrated Circuit interrupt 0 + DCD I3C1_IRQHandler ;Improved Inter Integrated Circuit interrupt 1 + DCD Reserved113_IRQHandler ;Reserved interrupt + DCD GDET_IRQHandler ;Digital Glitch Detect 0 interrupt or Digital Glitch Detect 1 interrupt + DCD VBAT0_IRQHandler ;VBAT interrupt( VBAT interrupt or digital tamper interrupt) + DCD EWM0_IRQHandler ;External Watchdog Monitor interrupt + DCD Reserved117_IRQHandler ;Reserved interrupt + DCD Reserved118_IRQHandler ;Reserved interrupt + DCD Reserved119_IRQHandler ;Reserved interrupt + DCD Reserved120_IRQHandler ;Reserved interrupt + DCD FLEXIO_IRQHandler ;Flexible Input/Output interrupt + DCD Reserved122_IRQHandler ;Reserved interrupt + DCD Reserved123_IRQHandler ;Reserved interrupt + DCD Reserved124_IRQHandler ;Reserved interrupt + DCD HSCMP0_IRQHandler ;High-Speed comparator0 interrupt + DCD HSCMP1_IRQHandler ;High-Speed comparator1 interrupt + DCD Reserved127_IRQHandler ;Reserved interrupt + DCD FLEXPWM0_RELOAD_ERROR_IRQHandler ;FlexPWM0_reload_error interrupt + DCD FLEXPWM0_FAULT_IRQHandler ;FlexPWM0_fault interrupt + DCD FLEXPWM0_SUBMODULE0_IRQHandler ;FlexPWM0 Submodule 0 capture/compare/reload interrupt + DCD FLEXPWM0_SUBMODULE1_IRQHandler ;FlexPWM0 Submodule 1 capture/compare/reload interrupt + DCD FLEXPWM0_SUBMODULE2_IRQHandler ;FlexPWM0 Submodule 2 capture/compare/reload interrupt + DCD FLEXPWM0_SUBMODULE3_IRQHandler ;FlexPWM0 Submodule 3 capture/compare/reload interrupt + DCD FLEXPWM1_RELOAD_ERROR_IRQHandler ;FlexPWM1_reload_error interrupt + DCD FLEXPWM1_FAULT_IRQHandler ;FlexPWM1_fault interrupt + DCD FLEXPWM1_SUBMODULE0_IRQHandler ;FlexPWM1 Submodule 0 capture/compare/reload interrupt + DCD FLEXPWM1_SUBMODULE1_IRQHandler ;FlexPWM1 Submodule 1 capture/compare/reload interrupt + DCD FLEXPWM1_SUBMODULE2_IRQHandler ;FlexPWM1 Submodule 2 capture/compare/reload interrupt + DCD FLEXPWM1_SUBMODULE3_IRQHandler ;FlexPWM1 Submodule 3 capture/compare/reload interrupt + DCD QDC0_COMPARE_IRQHandler ;QDC0_Compare interrupt + DCD QDC0_HOME_IRQHandler ;QDC0_Home interrupt + DCD QDC0_WDG_SAB_IRQHandler ;QDC0_WDG_IRQ/SAB interrupt + DCD QDC0_IDX_IRQHandler ;QDC0_IDX interrupt + DCD QDC1_COMPARE_IRQHandler ;QDC1_Compare interrupt + DCD QDC1_HOME_IRQHandler ;QDC1_Home interrupt + DCD QDC1_WDG_SAB_IRQHandler ;QDC1_WDG_IRQ/SAB interrupt + DCD QDC1_IDX_IRQHandler ;QDC1_IDX interrupt + DCD ITRC0_IRQHandler ;Intrusion and Tamper Response Controller interrupt + DCD Reserved149_IRQHandler ;Reserved interrupt + DCD ELS_ERR_IRQHandler ;ELS error interrupt + DCD PKC_ERR_IRQHandler ;PKC error interrupt + DCD ERM_SINGLE_BIT_ERROR_IRQHandler ;ERM Single Bit error interrupt + DCD ERM_MULTI_BIT_ERROR_IRQHandler ;ERM Multi Bit error interrupt + DCD FMU0_IRQHandler ;Flash Management Unit interrupt + DCD Reserved155_IRQHandler ;Reserved interrupt + DCD Reserved156_IRQHandler ;Reserved interrupt + DCD Reserved157_IRQHandler ;Reserved interrupt + DCD Reserved158_IRQHandler ;Reserved interrupt + DCD LPTMR0_IRQHandler ;Low Power Timer 0 interrupt + DCD LPTMR1_IRQHandler ;Low Power Timer 1 interrupt + DCD SCG_IRQHandler ;System Clock Generator interrupt + DCD SPC_IRQHandler ;System Power Controller interrupt + DCD WUU_IRQHandler ;Wake Up Unit interrupt + DCD PORT_EFT_IRQHandler ;PORT0~5 EFT interrupt + DCD Reserved165_IRQHandler ;Reserved interrupt + DCD Reserved166_IRQHandler ;Reserved interrupt + DCD Reserved167_IRQHandler ;Reserved interrupt + DCD WWDT0_IRQHandler ;Windowed Watchdog Timer 0 interrupt + DCD WWDT1_IRQHandler ;Windowed Watchdog Timer 1 interrupt + DCD CMC0_IRQHandler ;Core Mode Controller interrupt + DCD Reserved171_IRQHandler ;Reserved interrupt +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =sfb(CSTACK) + MSR MSPLIM, R0 + CPSIE I ; Unmask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK OR_IRQHandler + PUBWEAK OR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +OR_IRQHandler + LDR R0, =OR_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH0_IRQHandler + PUBWEAK EDMA_0_CH0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH0_IRQHandler + LDR R0, =EDMA_0_CH0_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH1_IRQHandler + PUBWEAK EDMA_0_CH1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH1_IRQHandler + LDR R0, =EDMA_0_CH1_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH2_IRQHandler + PUBWEAK EDMA_0_CH2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH2_IRQHandler + LDR R0, =EDMA_0_CH2_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH3_IRQHandler + PUBWEAK EDMA_0_CH3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH3_IRQHandler + LDR R0, =EDMA_0_CH3_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH4_IRQHandler + PUBWEAK EDMA_0_CH4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH4_IRQHandler + LDR R0, =EDMA_0_CH4_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH5_IRQHandler + PUBWEAK EDMA_0_CH5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH5_IRQHandler + LDR R0, =EDMA_0_CH5_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH6_IRQHandler + PUBWEAK EDMA_0_CH6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH6_IRQHandler + LDR R0, =EDMA_0_CH6_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH7_IRQHandler + PUBWEAK EDMA_0_CH7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH7_IRQHandler + LDR R0, =EDMA_0_CH7_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH8_IRQHandler + PUBWEAK EDMA_0_CH8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH8_IRQHandler + LDR R0, =EDMA_0_CH8_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH9_IRQHandler + PUBWEAK EDMA_0_CH9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH9_IRQHandler + LDR R0, =EDMA_0_CH9_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH10_IRQHandler + PUBWEAK EDMA_0_CH10_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH10_IRQHandler + LDR R0, =EDMA_0_CH10_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH11_IRQHandler + PUBWEAK EDMA_0_CH11_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH11_IRQHandler + LDR R0, =EDMA_0_CH11_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH12_IRQHandler + PUBWEAK EDMA_0_CH12_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH12_IRQHandler + LDR R0, =EDMA_0_CH12_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH13_IRQHandler + PUBWEAK EDMA_0_CH13_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH13_IRQHandler + LDR R0, =EDMA_0_CH13_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH14_IRQHandler + PUBWEAK EDMA_0_CH14_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH14_IRQHandler + LDR R0, =EDMA_0_CH14_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_0_CH15_IRQHandler + PUBWEAK EDMA_0_CH15_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_0_CH15_IRQHandler + LDR R0, =EDMA_0_CH15_DriverIRQHandler + BX R0 + + PUBWEAK GPIO00_IRQHandler + PUBWEAK GPIO00_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO00_IRQHandler + LDR R0, =GPIO00_DriverIRQHandler + BX R0 + + PUBWEAK GPIO01_IRQHandler + PUBWEAK GPIO01_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO01_IRQHandler + LDR R0, =GPIO01_DriverIRQHandler + BX R0 + + PUBWEAK GPIO10_IRQHandler + PUBWEAK GPIO10_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO10_IRQHandler + LDR R0, =GPIO10_DriverIRQHandler + BX R0 + + PUBWEAK GPIO11_IRQHandler + PUBWEAK GPIO11_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO11_IRQHandler + LDR R0, =GPIO11_DriverIRQHandler + BX R0 + + PUBWEAK GPIO20_IRQHandler + PUBWEAK GPIO20_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO20_IRQHandler + LDR R0, =GPIO20_DriverIRQHandler + BX R0 + + PUBWEAK GPIO21_IRQHandler + PUBWEAK GPIO21_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO21_IRQHandler + LDR R0, =GPIO21_DriverIRQHandler + BX R0 + + PUBWEAK GPIO30_IRQHandler + PUBWEAK GPIO30_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO30_IRQHandler + LDR R0, =GPIO30_DriverIRQHandler + BX R0 + + PUBWEAK GPIO31_IRQHandler + PUBWEAK GPIO31_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO31_IRQHandler + LDR R0, =GPIO31_DriverIRQHandler + BX R0 + + PUBWEAK GPIO40_IRQHandler + PUBWEAK GPIO40_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO40_IRQHandler + LDR R0, =GPIO40_DriverIRQHandler + BX R0 + + PUBWEAK GPIO41_IRQHandler + PUBWEAK GPIO41_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO41_IRQHandler + LDR R0, =GPIO41_DriverIRQHandler + BX R0 + + PUBWEAK GPIO50_IRQHandler + PUBWEAK GPIO50_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO50_IRQHandler + LDR R0, =GPIO50_DriverIRQHandler + BX R0 + + PUBWEAK GPIO51_IRQHandler + PUBWEAK GPIO51_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO51_IRQHandler + LDR R0, =GPIO51_DriverIRQHandler + BX R0 + + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + + PUBWEAK Reserved49_IRQHandler + PUBWEAK Reserved49_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved49_IRQHandler + LDR R0, =Reserved49_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM0_IRQHandler + PUBWEAK LP_FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM0_IRQHandler + LDR R0, =LP_FLEXCOMM0_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM1_IRQHandler + PUBWEAK LP_FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM1_IRQHandler + LDR R0, =LP_FLEXCOMM1_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM2_IRQHandler + PUBWEAK LP_FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM2_IRQHandler + LDR R0, =LP_FLEXCOMM2_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM3_IRQHandler + PUBWEAK LP_FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM3_IRQHandler + LDR R0, =LP_FLEXCOMM3_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM4_IRQHandler + PUBWEAK LP_FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM4_IRQHandler + LDR R0, =LP_FLEXCOMM4_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM5_IRQHandler + PUBWEAK LP_FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM5_IRQHandler + LDR R0, =LP_FLEXCOMM5_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM6_IRQHandler + PUBWEAK LP_FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM6_IRQHandler + LDR R0, =LP_FLEXCOMM6_DriverIRQHandler + BX R0 + + PUBWEAK LP_FLEXCOMM7_IRQHandler + PUBWEAK LP_FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LP_FLEXCOMM7_IRQHandler + LDR R0, =LP_FLEXCOMM7_DriverIRQHandler + BX R0 + + PUBWEAK Reserved59_IRQHandler + PUBWEAK Reserved59_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved59_IRQHandler + LDR R0, =Reserved59_DriverIRQHandler + BX R0 + + PUBWEAK Reserved60_IRQHandler + PUBWEAK Reserved60_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved60_IRQHandler + LDR R0, =Reserved60_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_IRQHandler + LDR R0, =ADC0_DriverIRQHandler + BX R0 + + PUBWEAK ADC1_IRQHandler + PUBWEAK ADC1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC1_IRQHandler + LDR R0, =ADC1_DriverIRQHandler + BX R0 + + PUBWEAK PINT0_IRQHandler + PUBWEAK PINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PINT0_IRQHandler + LDR R0, =PINT0_DriverIRQHandler + BX R0 + + PUBWEAK PDM_EVENT_IRQHandler + PUBWEAK PDM_EVENT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PDM_EVENT_IRQHandler + LDR R0, =PDM_EVENT_DriverIRQHandler + BX R0 + + PUBWEAK Reserved65_IRQHandler + PUBWEAK Reserved65_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved65_IRQHandler + LDR R0, =Reserved65_DriverIRQHandler + BX R0 + + PUBWEAK Reserved66_IRQHandler + PUBWEAK Reserved66_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved66_IRQHandler + LDR R0, =Reserved66_DriverIRQHandler + BX R0 + + PUBWEAK USB0_DCD_IRQHandler + PUBWEAK USB0_DCD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_DCD_IRQHandler + LDR R0, =USB0_DCD_DriverIRQHandler + BX R0 + + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + + PUBWEAK SMARTDMA_IRQHandler + PUBWEAK SMARTDMA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTDMA_IRQHandler + LDR R0, =SMARTDMA_DriverIRQHandler + BX R0 + + PUBWEAK Reserved70_IRQHandler + PUBWEAK Reserved70_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved70_IRQHandler + LDR R0, =Reserved70_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + + PUBWEAK OS_EVENT_IRQHandler + PUBWEAK OS_EVENT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +OS_EVENT_IRQHandler + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + + PUBWEAK Reserved74_IRQHandler + PUBWEAK Reserved74_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved74_IRQHandler + LDR R0, =Reserved74_DriverIRQHandler + BX R0 + + PUBWEAK SAI0_IRQHandler + PUBWEAK SAI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI0_IRQHandler + LDR R0, =SAI0_DriverIRQHandler + BX R0 + + PUBWEAK SAI1_IRQHandler + PUBWEAK SAI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI1_IRQHandler + LDR R0, =SAI1_DriverIRQHandler + BX R0 + + PUBWEAK Reserved77_IRQHandler + PUBWEAK Reserved77_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved77_IRQHandler + LDR R0, =Reserved77_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQHandler + PUBWEAK CAN0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQHandler + PUBWEAK CAN1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQHandler + LDR R0, =CAN1_DriverIRQHandler + BX R0 + + PUBWEAK Reserved80_IRQHandler + PUBWEAK Reserved80_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved80_IRQHandler + LDR R0, =Reserved80_DriverIRQHandler + BX R0 + + PUBWEAK Reserved81_IRQHandler + PUBWEAK Reserved81_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved81_IRQHandler + LDR R0, =Reserved81_DriverIRQHandler + BX R0 + + PUBWEAK USB1_HS_PHY_IRQHandler + PUBWEAK USB1_HS_PHY_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_HS_PHY_IRQHandler + LDR R0, =USB1_HS_PHY_DriverIRQHandler + BX R0 + + PUBWEAK USB1_HS_IRQHandler + PUBWEAK USB1_HS_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_HS_IRQHandler + LDR R0, =USB1_HS_DriverIRQHandler + BX R0 + + PUBWEAK SEC_HYPERVISOR_CALL_IRQHandler + PUBWEAK SEC_HYPERVISOR_CALL_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_HYPERVISOR_CALL_IRQHandler + LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler + BX R0 + + PUBWEAK Reserved85_IRQHandler + PUBWEAK Reserved85_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved85_IRQHandler + LDR R0, =Reserved85_DriverIRQHandler + BX R0 + + PUBWEAK Reserved86_IRQHandler + PUBWEAK Reserved86_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved86_IRQHandler + LDR R0, =Reserved86_DriverIRQHandler + BX R0 + + PUBWEAK Freqme_IRQHandler + PUBWEAK Freqme_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Freqme_IRQHandler + LDR R0, =Freqme_DriverIRQHandler + BX R0 + + PUBWEAK SEC_VIO_IRQHandler + PUBWEAK SEC_VIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SEC_VIO_IRQHandler + LDR R0, =SEC_VIO_DriverIRQHandler + BX R0 + + PUBWEAK ELS_IRQHandler + PUBWEAK ELS_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ELS_IRQHandler + LDR R0, =ELS_DriverIRQHandler + BX R0 + + PUBWEAK PKC_IRQHandler + PUBWEAK PKC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PKC_IRQHandler + LDR R0, =PKC_DriverIRQHandler + BX R0 + + PUBWEAK PUF_IRQHandler + PUBWEAK PUF_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PUF_IRQHandler + LDR R0, =PUF_DriverIRQHandler + BX R0 + + PUBWEAK Reserved92_IRQHandler + PUBWEAK Reserved92_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved92_IRQHandler + LDR R0, =Reserved92_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH0_IRQHandler + PUBWEAK EDMA_1_CH0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH0_IRQHandler + LDR R0, =EDMA_1_CH0_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH1_IRQHandler + PUBWEAK EDMA_1_CH1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH1_IRQHandler + LDR R0, =EDMA_1_CH1_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH2_IRQHandler + PUBWEAK EDMA_1_CH2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH2_IRQHandler + LDR R0, =EDMA_1_CH2_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH3_IRQHandler + PUBWEAK EDMA_1_CH3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH3_IRQHandler + LDR R0, =EDMA_1_CH3_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH4_IRQHandler + PUBWEAK EDMA_1_CH4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH4_IRQHandler + LDR R0, =EDMA_1_CH4_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH5_IRQHandler + PUBWEAK EDMA_1_CH5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH5_IRQHandler + LDR R0, =EDMA_1_CH5_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH6_IRQHandler + PUBWEAK EDMA_1_CH6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH6_IRQHandler + LDR R0, =EDMA_1_CH6_DriverIRQHandler + BX R0 + + PUBWEAK EDMA_1_CH7_IRQHandler + PUBWEAK EDMA_1_CH7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EDMA_1_CH7_IRQHandler + LDR R0, =EDMA_1_CH7_DriverIRQHandler + BX R0 + + PUBWEAK Reserved101_IRQHandler + PUBWEAK Reserved101_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved101_IRQHandler + LDR R0, =Reserved101_DriverIRQHandler + BX R0 + + PUBWEAK Reserved102_IRQHandler + PUBWEAK Reserved102_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved102_IRQHandler + LDR R0, =Reserved102_DriverIRQHandler + BX R0 + + PUBWEAK Reserved103_IRQHandler + PUBWEAK Reserved103_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved103_IRQHandler + LDR R0, =Reserved103_DriverIRQHandler + BX R0 + + PUBWEAK Reserved104_IRQHandler + PUBWEAK Reserved104_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved104_IRQHandler + LDR R0, =Reserved104_DriverIRQHandler + BX R0 + + PUBWEAK Reserved105_IRQHandler + PUBWEAK Reserved105_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved105_IRQHandler + LDR R0, =Reserved105_DriverIRQHandler + BX R0 + + PUBWEAK Reserved106_IRQHandler + PUBWEAK Reserved106_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved106_IRQHandler + LDR R0, =Reserved106_DriverIRQHandler + BX R0 + + PUBWEAK Reserved107_IRQHandler + PUBWEAK Reserved107_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved107_IRQHandler + LDR R0, =Reserved107_DriverIRQHandler + BX R0 + + PUBWEAK Reserved108_IRQHandler + PUBWEAK Reserved108_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved108_IRQHandler + LDR R0, =Reserved108_DriverIRQHandler + BX R0 + + PUBWEAK CDOG0_IRQHandler + PUBWEAK CDOG0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CDOG0_IRQHandler + LDR R0, =CDOG0_DriverIRQHandler + BX R0 + + PUBWEAK CDOG1_IRQHandler + PUBWEAK CDOG1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CDOG1_IRQHandler + LDR R0, =CDOG1_DriverIRQHandler + BX R0 + + PUBWEAK I3C0_IRQHandler + PUBWEAK I3C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I3C0_IRQHandler + LDR R0, =I3C0_DriverIRQHandler + BX R0 + + PUBWEAK I3C1_IRQHandler + PUBWEAK I3C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I3C1_IRQHandler + LDR R0, =I3C1_DriverIRQHandler + BX R0 + + PUBWEAK Reserved113_IRQHandler + PUBWEAK Reserved113_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved113_IRQHandler + LDR R0, =Reserved113_DriverIRQHandler + BX R0 + + PUBWEAK GDET_IRQHandler + PUBWEAK GDET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GDET_IRQHandler + LDR R0, =GDET_DriverIRQHandler + BX R0 + + PUBWEAK VBAT0_IRQHandler + PUBWEAK VBAT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +VBAT0_IRQHandler + LDR R0, =VBAT0_DriverIRQHandler + BX R0 + + PUBWEAK EWM0_IRQHandler + PUBWEAK EWM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EWM0_IRQHandler + LDR R0, =EWM0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved117_IRQHandler + PUBWEAK Reserved117_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved117_IRQHandler + LDR R0, =Reserved117_DriverIRQHandler + BX R0 + + PUBWEAK Reserved118_IRQHandler + PUBWEAK Reserved118_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved118_IRQHandler + LDR R0, =Reserved118_DriverIRQHandler + BX R0 + + PUBWEAK Reserved119_IRQHandler + PUBWEAK Reserved119_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved119_IRQHandler + LDR R0, =Reserved119_DriverIRQHandler + BX R0 + + PUBWEAK Reserved120_IRQHandler + PUBWEAK Reserved120_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved120_IRQHandler + LDR R0, =Reserved120_DriverIRQHandler + BX R0 + + PUBWEAK FLEXIO_IRQHandler + PUBWEAK FLEXIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO_IRQHandler + LDR R0, =FLEXIO_DriverIRQHandler + BX R0 + + PUBWEAK Reserved122_IRQHandler + PUBWEAK Reserved122_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved122_IRQHandler + LDR R0, =Reserved122_DriverIRQHandler + BX R0 + + PUBWEAK Reserved123_IRQHandler + PUBWEAK Reserved123_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved123_IRQHandler + LDR R0, =Reserved123_DriverIRQHandler + BX R0 + + PUBWEAK Reserved124_IRQHandler + PUBWEAK Reserved124_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved124_IRQHandler + LDR R0, =Reserved124_DriverIRQHandler + BX R0 + + PUBWEAK HSCMP0_IRQHandler + PUBWEAK HSCMP0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HSCMP0_IRQHandler + LDR R0, =HSCMP0_DriverIRQHandler + BX R0 + + PUBWEAK HSCMP1_IRQHandler + PUBWEAK HSCMP1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HSCMP1_IRQHandler + LDR R0, =HSCMP1_DriverIRQHandler + BX R0 + + PUBWEAK Reserved127_IRQHandler + PUBWEAK Reserved127_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved127_IRQHandler + LDR R0, =Reserved127_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_RELOAD_ERROR_IRQHandler + PUBWEAK FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_RELOAD_ERROR_IRQHandler + LDR R0, =FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_FAULT_IRQHandler + PUBWEAK FLEXPWM0_FAULT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_FAULT_IRQHandler + LDR R0, =FLEXPWM0_FAULT_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_SUBMODULE0_IRQHandler + PUBWEAK FLEXPWM0_SUBMODULE0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_SUBMODULE0_IRQHandler + LDR R0, =FLEXPWM0_SUBMODULE0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_SUBMODULE1_IRQHandler + PUBWEAK FLEXPWM0_SUBMODULE1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_SUBMODULE1_IRQHandler + LDR R0, =FLEXPWM0_SUBMODULE1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_SUBMODULE2_IRQHandler + PUBWEAK FLEXPWM0_SUBMODULE2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_SUBMODULE2_IRQHandler + LDR R0, =FLEXPWM0_SUBMODULE2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_SUBMODULE3_IRQHandler + PUBWEAK FLEXPWM0_SUBMODULE3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_SUBMODULE3_IRQHandler + LDR R0, =FLEXPWM0_SUBMODULE3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_RELOAD_ERROR_IRQHandler + PUBWEAK FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_RELOAD_ERROR_IRQHandler + LDR R0, =FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_FAULT_IRQHandler + PUBWEAK FLEXPWM1_FAULT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_FAULT_IRQHandler + LDR R0, =FLEXPWM1_FAULT_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_SUBMODULE0_IRQHandler + PUBWEAK FLEXPWM1_SUBMODULE0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_SUBMODULE0_IRQHandler + LDR R0, =FLEXPWM1_SUBMODULE0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_SUBMODULE1_IRQHandler + PUBWEAK FLEXPWM1_SUBMODULE1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_SUBMODULE1_IRQHandler + LDR R0, =FLEXPWM1_SUBMODULE1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_SUBMODULE2_IRQHandler + PUBWEAK FLEXPWM1_SUBMODULE2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_SUBMODULE2_IRQHandler + LDR R0, =FLEXPWM1_SUBMODULE2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_SUBMODULE3_IRQHandler + PUBWEAK FLEXPWM1_SUBMODULE3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_SUBMODULE3_IRQHandler + LDR R0, =FLEXPWM1_SUBMODULE3_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_COMPARE_IRQHandler + PUBWEAK QDC0_COMPARE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_COMPARE_IRQHandler + LDR R0, =QDC0_COMPARE_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_HOME_IRQHandler + PUBWEAK QDC0_HOME_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_HOME_IRQHandler + LDR R0, =QDC0_HOME_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_WDG_SAB_IRQHandler + PUBWEAK QDC0_WDG_SAB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_WDG_SAB_IRQHandler + LDR R0, =QDC0_WDG_SAB_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_IDX_IRQHandler + PUBWEAK QDC0_IDX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_IDX_IRQHandler + LDR R0, =QDC0_IDX_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_COMPARE_IRQHandler + PUBWEAK QDC1_COMPARE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_COMPARE_IRQHandler + LDR R0, =QDC1_COMPARE_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_HOME_IRQHandler + PUBWEAK QDC1_HOME_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_HOME_IRQHandler + LDR R0, =QDC1_HOME_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_WDG_SAB_IRQHandler + PUBWEAK QDC1_WDG_SAB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_WDG_SAB_IRQHandler + LDR R0, =QDC1_WDG_SAB_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_IDX_IRQHandler + PUBWEAK QDC1_IDX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_IDX_IRQHandler + LDR R0, =QDC1_IDX_DriverIRQHandler + BX R0 + + PUBWEAK ITRC0_IRQHandler + PUBWEAK ITRC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ITRC0_IRQHandler + LDR R0, =ITRC0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved149_IRQHandler + PUBWEAK Reserved149_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved149_IRQHandler + LDR R0, =Reserved149_DriverIRQHandler + BX R0 + + PUBWEAK ELS_ERR_IRQHandler + PUBWEAK ELS_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ELS_ERR_IRQHandler + LDR R0, =ELS_ERR_DriverIRQHandler + BX R0 + + PUBWEAK PKC_ERR_IRQHandler + PUBWEAK PKC_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PKC_ERR_IRQHandler + LDR R0, =PKC_ERR_DriverIRQHandler + BX R0 + + PUBWEAK ERM_SINGLE_BIT_ERROR_IRQHandler + PUBWEAK ERM_SINGLE_BIT_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ERM_SINGLE_BIT_ERROR_IRQHandler + LDR R0, =ERM_SINGLE_BIT_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK ERM_MULTI_BIT_ERROR_IRQHandler + PUBWEAK ERM_MULTI_BIT_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ERM_MULTI_BIT_ERROR_IRQHandler + LDR R0, =ERM_MULTI_BIT_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK FMU0_IRQHandler + PUBWEAK FMU0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FMU0_IRQHandler + LDR R0, =FMU0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved155_IRQHandler + PUBWEAK Reserved155_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved155_IRQHandler + LDR R0, =Reserved155_DriverIRQHandler + BX R0 + + PUBWEAK Reserved156_IRQHandler + PUBWEAK Reserved156_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved156_IRQHandler + LDR R0, =Reserved156_DriverIRQHandler + BX R0 + + PUBWEAK Reserved157_IRQHandler + PUBWEAK Reserved157_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved157_IRQHandler + LDR R0, =Reserved157_DriverIRQHandler + BX R0 + + PUBWEAK Reserved158_IRQHandler + PUBWEAK Reserved158_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved158_IRQHandler + LDR R0, =Reserved158_DriverIRQHandler + BX R0 + + PUBWEAK LPTMR0_IRQHandler + PUBWEAK LPTMR0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPTMR0_IRQHandler + LDR R0, =LPTMR0_DriverIRQHandler + BX R0 + + PUBWEAK LPTMR1_IRQHandler + PUBWEAK LPTMR1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPTMR1_IRQHandler + LDR R0, =LPTMR1_DriverIRQHandler + BX R0 + + PUBWEAK SCG_IRQHandler + PUBWEAK SCG_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCG_IRQHandler + LDR R0, =SCG_DriverIRQHandler + BX R0 + + PUBWEAK SPC_IRQHandler + PUBWEAK SPC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPC_IRQHandler + LDR R0, =SPC_DriverIRQHandler + BX R0 + + PUBWEAK WUU_IRQHandler + PUBWEAK WUU_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WUU_IRQHandler + LDR R0, =WUU_DriverIRQHandler + BX R0 + + PUBWEAK PORT_EFT_IRQHandler + PUBWEAK PORT_EFT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PORT_EFT_IRQHandler + LDR R0, =PORT_EFT_DriverIRQHandler + BX R0 + + PUBWEAK Reserved165_IRQHandler + PUBWEAK Reserved165_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved165_IRQHandler + LDR R0, =Reserved165_DriverIRQHandler + BX R0 + + PUBWEAK Reserved166_IRQHandler + PUBWEAK Reserved166_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved166_IRQHandler + LDR R0, =Reserved166_DriverIRQHandler + BX R0 + + PUBWEAK Reserved167_IRQHandler + PUBWEAK Reserved167_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved167_IRQHandler + LDR R0, =Reserved167_DriverIRQHandler + BX R0 + + PUBWEAK WWDT0_IRQHandler + PUBWEAK WWDT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WWDT0_IRQHandler + LDR R0, =WWDT0_DriverIRQHandler + BX R0 + + PUBWEAK WWDT1_IRQHandler + PUBWEAK WWDT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WWDT1_IRQHandler + LDR R0, =WWDT1_DriverIRQHandler + BX R0 + + PUBWEAK CMC0_IRQHandler + PUBWEAK CMC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CMC0_IRQHandler + LDR R0, =CMC0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved171_IRQHandler + PUBWEAK Reserved171_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved171_IRQHandler + LDR R0, =Reserved171_DriverIRQHandler + BX R0 + +OR_DriverIRQHandler +EDMA_0_CH0_DriverIRQHandler +EDMA_0_CH1_DriverIRQHandler +EDMA_0_CH2_DriverIRQHandler +EDMA_0_CH3_DriverIRQHandler +EDMA_0_CH4_DriverIRQHandler +EDMA_0_CH5_DriverIRQHandler +EDMA_0_CH6_DriverIRQHandler +EDMA_0_CH7_DriverIRQHandler +EDMA_0_CH8_DriverIRQHandler +EDMA_0_CH9_DriverIRQHandler +EDMA_0_CH10_DriverIRQHandler +EDMA_0_CH11_DriverIRQHandler +EDMA_0_CH12_DriverIRQHandler +EDMA_0_CH13_DriverIRQHandler +EDMA_0_CH14_DriverIRQHandler +EDMA_0_CH15_DriverIRQHandler +GPIO00_DriverIRQHandler +GPIO01_DriverIRQHandler +GPIO10_DriverIRQHandler +GPIO11_DriverIRQHandler +GPIO20_DriverIRQHandler +GPIO21_DriverIRQHandler +GPIO30_DriverIRQHandler +GPIO31_DriverIRQHandler +GPIO40_DriverIRQHandler +GPIO41_DriverIRQHandler +GPIO50_DriverIRQHandler +GPIO51_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +Reserved49_DriverIRQHandler +CTIMER2_DriverIRQHandler +LP_FLEXCOMM0_DriverIRQHandler +LP_FLEXCOMM1_DriverIRQHandler +LP_FLEXCOMM2_DriverIRQHandler +LP_FLEXCOMM3_DriverIRQHandler +LP_FLEXCOMM4_DriverIRQHandler +LP_FLEXCOMM5_DriverIRQHandler +LP_FLEXCOMM6_DriverIRQHandler +LP_FLEXCOMM7_DriverIRQHandler +Reserved59_DriverIRQHandler +Reserved60_DriverIRQHandler +ADC0_DriverIRQHandler +ADC1_DriverIRQHandler +PINT0_DriverIRQHandler +PDM_EVENT_DriverIRQHandler +Reserved65_DriverIRQHandler +Reserved66_DriverIRQHandler +USB0_DCD_DriverIRQHandler +RTC_DriverIRQHandler +SMARTDMA_DriverIRQHandler +Reserved70_DriverIRQHandler +CTIMER3_DriverIRQHandler +CTIMER4_DriverIRQHandler +OS_EVENT_DriverIRQHandler +Reserved74_DriverIRQHandler +SAI0_DriverIRQHandler +SAI1_DriverIRQHandler +Reserved77_DriverIRQHandler +CAN0_DriverIRQHandler +CAN1_DriverIRQHandler +Reserved80_DriverIRQHandler +Reserved81_DriverIRQHandler +USB1_HS_PHY_DriverIRQHandler +USB1_HS_DriverIRQHandler +SEC_HYPERVISOR_CALL_DriverIRQHandler +Reserved85_DriverIRQHandler +Reserved86_DriverIRQHandler +Freqme_DriverIRQHandler +SEC_VIO_DriverIRQHandler +ELS_DriverIRQHandler +PKC_DriverIRQHandler +PUF_DriverIRQHandler +Reserved92_DriverIRQHandler +EDMA_1_CH0_DriverIRQHandler +EDMA_1_CH1_DriverIRQHandler +EDMA_1_CH2_DriverIRQHandler +EDMA_1_CH3_DriverIRQHandler +EDMA_1_CH4_DriverIRQHandler +EDMA_1_CH5_DriverIRQHandler +EDMA_1_CH6_DriverIRQHandler +EDMA_1_CH7_DriverIRQHandler +Reserved101_DriverIRQHandler +Reserved102_DriverIRQHandler +Reserved103_DriverIRQHandler +Reserved104_DriverIRQHandler +Reserved105_DriverIRQHandler +Reserved106_DriverIRQHandler +Reserved107_DriverIRQHandler +Reserved108_DriverIRQHandler +CDOG0_DriverIRQHandler +CDOG1_DriverIRQHandler +I3C0_DriverIRQHandler +I3C1_DriverIRQHandler +Reserved113_DriverIRQHandler +GDET_DriverIRQHandler +VBAT0_DriverIRQHandler +EWM0_DriverIRQHandler +Reserved117_DriverIRQHandler +Reserved118_DriverIRQHandler +Reserved119_DriverIRQHandler +Reserved120_DriverIRQHandler +FLEXIO_DriverIRQHandler +Reserved122_DriverIRQHandler +Reserved123_DriverIRQHandler +Reserved124_DriverIRQHandler +HSCMP0_DriverIRQHandler +HSCMP1_DriverIRQHandler +Reserved127_DriverIRQHandler +FLEXPWM0_RELOAD_ERROR_DriverIRQHandler +FLEXPWM0_FAULT_DriverIRQHandler +FLEXPWM0_SUBMODULE0_DriverIRQHandler +FLEXPWM0_SUBMODULE1_DriverIRQHandler +FLEXPWM0_SUBMODULE2_DriverIRQHandler +FLEXPWM0_SUBMODULE3_DriverIRQHandler +FLEXPWM1_RELOAD_ERROR_DriverIRQHandler +FLEXPWM1_FAULT_DriverIRQHandler +FLEXPWM1_SUBMODULE0_DriverIRQHandler +FLEXPWM1_SUBMODULE1_DriverIRQHandler +FLEXPWM1_SUBMODULE2_DriverIRQHandler +FLEXPWM1_SUBMODULE3_DriverIRQHandler +QDC0_COMPARE_DriverIRQHandler +QDC0_HOME_DriverIRQHandler +QDC0_WDG_SAB_DriverIRQHandler +QDC0_IDX_DriverIRQHandler +QDC1_COMPARE_DriverIRQHandler +QDC1_HOME_DriverIRQHandler +QDC1_WDG_SAB_DriverIRQHandler +QDC1_IDX_DriverIRQHandler +ITRC0_DriverIRQHandler +Reserved149_DriverIRQHandler +ELS_ERR_DriverIRQHandler +PKC_ERR_DriverIRQHandler +ERM_SINGLE_BIT_ERROR_DriverIRQHandler +ERM_MULTI_BIT_ERROR_DriverIRQHandler +FMU0_DriverIRQHandler +Reserved155_DriverIRQHandler +Reserved156_DriverIRQHandler +Reserved157_DriverIRQHandler +Reserved158_DriverIRQHandler +LPTMR0_DriverIRQHandler +LPTMR1_DriverIRQHandler +SCG_DriverIRQHandler +SPC_DriverIRQHandler +WUU_DriverIRQHandler +PORT_EFT_DriverIRQHandler +Reserved165_DriverIRQHandler +Reserved166_DriverIRQHandler +Reserved167_DriverIRQHandler +WWDT0_DriverIRQHandler +WWDT1_DriverIRQHandler +CMC0_DriverIRQHandler +Reserved171_DriverIRQHandler +DefaultISR + B . + + END diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/system_MCXN236.c b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/system_MCXN236.c new file mode 100644 index 0000000000..11c0ff20f0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/system_MCXN236.c @@ -0,0 +1,128 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240307 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN236 + * @version 1.0 + * @date 2023-10-01 + * @brief Device specific configuration file for MCXN236 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + + SYSCON->ECC_ENABLE_CTRL = 0; /* disable RAM ECC to get max RAM size */ + + SYSCON->NVM_CTRL &= ~SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK; /* enables bus error on multi-bit ECC error for data */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + + /* enable the flash cache LPCAC */ + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Disable aGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN9_SELn(0x2)); + /* Disable aGDET interrupt and reset */ + SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_LOCK_MASK; + SPC0->GLITCH_DETECT_SC = 0x3C; + SPC0->GLITCH_DETECT_SC |= SPC_GLITCH_DETECT_SC_LOCK_MASK; + + /* Disable dGDET trigger the CHIP_RESET */ + ITRC0->OUT_SEL[4][0] = (ITRC0->OUT_SEL[4][0] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + ITRC0->OUT_SEL[4][1] = (ITRC0->OUT_SEL[4][1] & ~ ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn_MASK) | (ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN0_SELn(0x2)); + GDET0->GDET_ENABLE1 = 0; + GDET1->GDET_ENABLE1 = 0; + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/system_MCXN236.h b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/system_MCXN236.h new file mode 100644 index 0000000000..2406a9790a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/MCXN236/system_MCXN236.h @@ -0,0 +1,106 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2023-10-01 +** Build: b240307 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2023-10-01) +** Initial version based on RM 1.2 +** +** ################################################################### +*/ + +/*! + * @file MCXN236 + * @version 1.0 + * @date 2023-10-01 + * @brief Device specific configuration file for MCXN236 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXN236_H_ +#define _SYSTEM_MCXN236_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + + #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_144MHZ 144000000u /* FRO 144 MHz (fro_144m) */ + + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXN236_H_ */ diff --git a/bsp/nxp/mcx/mcxn/Libraries/MCXN236/SConscript b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/SConscript new file mode 100644 index 0000000000..e9bab825e0 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/Libraries/MCXN236/SConscript @@ -0,0 +1,62 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/../CMSIS/Core/Include', cwd + '/MCXN236', cwd + '/MCXN236/drivers'] +src = Split(''' + MCXN236/system_MCXN236.c + ''') + +if rtconfig.PLATFORM in ['gcc']: + src += ['MCXN236/gcc/startup_MCXN236.S'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += ['MCXN236/arm/startup_MCXN236.S'] +elif rtconfig.PLATFORM in ['iccarm']: + src += ['MCXN236/iar/startup_MCXN236.s'] + +src += ['MCXN236/drivers/fsl_cache_lpcac.c'] +src += ['MCXN236/drivers/fsl_cdog.c'] +src += ['MCXN236/drivers/fsl_clock.c'] +src += ['MCXN236/drivers/fsl_cmc.c'] +src += ['MCXN236/drivers/fsl_common.c'] +src += ['MCXN236/drivers/fsl_common_arm.c'] +src += ['MCXN236/drivers/fsl_crc.c'] +src += ['MCXN236/drivers/fsl_ctimer.c'] +src += ['MCXN236/drivers/fsl_edma.c'] +src += ['MCXN236/drivers/fsl_edma_soc.c'] +src += ['MCXN236/drivers/fsl_eim.c'] +src += ['MCXN236/drivers/fsl_erm.c'] +src += ['MCXN236/drivers/fsl_evtg.c'] +src += ['MCXN236/drivers/fsl_ewm.c'] +src += ['MCXN236/drivers/fsl_flexcan.c'] +src += ['MCXN236/drivers/fsl_flexcan_edma.c'] +src += ['MCXN236/drivers/fsl_flexio.c'] +src += ['MCXN236/drivers/fsl_flexio_i2c_master.c'] +src += ['MCXN236/drivers/fsl_flexio_mculcd.c'] +src += ['MCXN236/drivers/fsl_flexio_mculcd_edma.c'] +src += ['MCXN236/drivers/fsl_flexio_spi.c'] +src += ['MCXN236/drivers/fsl_flexio_spi_edma.c'] +src += ['MCXN236/drivers/fsl_flexio_uart.c'] +src += ['MCXN236/drivers/fsl_flexio_uart_edma.c'] +src += ['MCXN236/drivers/fsl_freqme.c'] +src += ['MCXN236/drivers/fsl_gpio.c'] +src += ['MCXN236/drivers/fsl_i3c.c'] +src += ['MCXN236/drivers/fsl_i3c_edma.c'] +src += ['MCXN236/drivers/fsl_irtc.c'] +src += ['MCXN236/drivers/fsl_lpadc.c'] +src += ['MCXN236/drivers/fsl_lpflexcomm.c'] +src += ['MCXN236/drivers/fsl_lpi2c.c'] +src += ['MCXN236/drivers/fsl_lpi2c_edma.c'] +src += ['MCXN236/drivers/fsl_lpspi.c'] +src += ['MCXN236/drivers/fsl_lpspi_edma.c'] +src += ['MCXN236/drivers/fsl_lptmr.c'] +src += ['MCXN236/drivers/fsl_lpuart.c'] +src += ['MCXN236/drivers/fsl_mrt.c'] +src += ['MCXN236/drivers/fsl_reset.c'] +src += ['MCXN236/drivers/fsl_spc.c'] +src += ['MCXN236/drivers/fsl_vref.c'] + + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/.config b/bsp/nxp/mcx/mcxn/frdm-mcxn236/.config new file mode 100644 index 0000000000..b330df9fd6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/.config @@ -0,0 +1,1113 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_MCX=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +CONFIG_RT_USING_HWTIMER=y + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +# CONFIG_ULOG_USING_ISR_LOG is not set +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +CONFIG_ULOG_OUTPUT_FLOAT=y +# CONFIG_ULOG_USING_COLOR is not set +# CONFIG_ULOG_OUTPUT_TIME is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_BACKEND_USING_FILE is not set +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +CONFIG_PKG_USING_RT_VSNPRINTF_FULL=y +CONFIG_PKG_RT_VSNPRINTF_FULL_PATH="/packages/system/enhanced-kservice/rt_vsnprintf_full" +# CONFIG_PKG_VSNPRINTF_SUPPORT_DECIMAL_SPECIFIERS is not set +# CONFIG_PKG_VSNPRINTF_SUPPORT_EXPONENTIAL_SPECIFIERS is not set +# CONFIG_PKG_VSNPRINTF_SUPPORT_WRITEBACK_SPECIFIER is not set +# CONFIG_PKG_VSNPRINTF_SUPPORT_LONG_LONG is not set +# CONFIG_PKG_VSNPRINTF_CHECK_FOR_NUL_IN_FORMAT_SPECIFIER is not set +# CONFIG_PKG_VSNPRINTF_SUPPORT_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_PKG_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_PKG_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_PKG_VSNPRINTF_DEFAULT_FLOAT_PRECISION=6 +CONFIG_PKG_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_PKG_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SPRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_SNPRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_PRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSPRINTF is not set +# CONFIG_RT_VSNPRINTF_FULL_REPLACING_VSNPRINTF is not set +CONFIG_PKG_USING_RT_VSNPRINTF_FULL_LATEST_VERSION=y +CONFIG_PKG_RT_VSNPRINTF_FULL_VER="latest" + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_MCXN947=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART4=y +CONFIG_BSP_USING_UART5=y +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_PWM is not set + +# +# Board extended module Drivers +# +# CONFIG_BSP_USING_RW007 is not set diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/Kconfig b/bsp/nxp/mcx/mcxn/frdm-mcxn236/Kconfig new file mode 100644 index 0000000000..8b6d987bce --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/Kconfig @@ -0,0 +1,27 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_MCX + bool + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../Libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/SConscript b/bsp/nxp/mcx/mcxn/frdm-mcxn236/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/SConstruct b/bsp/nxp/mcx/mcxn/frdm-mcxn236/SConstruct new file mode 100644 index 0000000000..ed0bfe11ff --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/SConstruct @@ -0,0 +1,67 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/Libraries'): + libraries_path_prefix = SDK_ROOT + '/Libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# include cmsis +objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/applications/SConscript b/bsp/nxp/mcx/mcxn/frdm-mcxn236/applications/SConscript new file mode 100644 index 0000000000..f11833c8d8 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/applications/main.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/applications/main.c new file mode 100644 index 0000000000..57aa27f628 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/applications/main.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-24 Magicoe first version + * 2020-01-10 Kevin/Karl Add PS demo + * 2020-09-21 supperthomas fix the main.c + * + */ + +#include +#include +#include "drv_pin.h" + +#define LEDB_PIN ((1*32)+2) +#define BUTTON_PIN ((0*32)+23) + +static void sw_pin_cb(void *args); + +int main(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__clang__) + rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif + + rt_pin_mode(LEDB_PIN, PIN_MODE_OUTPUT); /* Set GPIO as Output */ + + rt_pin_mode(BUTTON_PIN, PIN_MODE_INPUT_PULLUP); + rt_pin_attach_irq(BUTTON_PIN, PIN_IRQ_MODE_FALLING, sw_pin_cb, RT_NULL); + rt_pin_irq_enable(BUTTON_PIN, 1); + + rt_kprintf("MCXN236 HelloWorld\r\n"); + + +#ifdef RT_USING_SDIO + rt_thread_mdelay(2000); + if (dfs_mount("sd", "/", "elm", 0, NULL) == 0) + { + rt_kprintf("sd mounted to /\n"); + } + else + { + rt_kprintf("sd mount to / failed\n"); + } +#endif + + while (1) + { + rt_pin_write(LEDB_PIN, PIN_HIGH); /* Set GPIO output 1 */ + rt_thread_mdelay(500); /* Delay 500mS */ + rt_pin_write(LEDB_PIN, PIN_LOW); /* Set GPIO output 0 */ + rt_thread_mdelay(500); /* Delay 500mS */ + } +} + +static void sw_pin_cb(void *args) +{ + rt_kprintf("sw pressed\r\n"); +} + +// end file diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig new file mode 100644 index 0000000000..93452d780e --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/Kconfig @@ -0,0 +1,223 @@ +menu "Hardware Drivers Config" + +config SOC_MCXN947 + bool + select SOC_MCXN947_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + select RT_USING_DMA + default n + + config BSP_USING_PIN + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART4 + bool "Enable UART4" + default y + + config BSP_USING_UART5 + bool "Enable UART5" + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + endif + + menuconfig BSP_USING_I2C + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default y + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable Flexcomm0 I2C" + default y + config BSP_USING_I2C1 + bool "Enable Flexcomm1 I2C" + default y + endif + + menuconfig BSP_USING_SPI + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + select BSP_USING_PIN + default y + + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable Flexcomm1 as SPI" + default n + + config BSP_USING_SPI3 + bool "Enable Flexcomm3 as SPI" + default n + + config BSP_USING_SPI6 + bool "Enable Flexcomm6 as SPI" + default n + if BSP_USING_SPI6 + config BSP_USING_SPI6_SAMPLE + bool "Enable SPI6 BUS Sample" + default n + endif + + config BSP_USING_SPI7 + bool "Enable Flexcomm7 as SPI" + default n + + config BSP_USING_SPI8 + bool "Enable Flexcomm8 as High Speed SPI" + default y + endif + + menuconfig BSP_USING_ADC + config BSP_USING_ADC + bool "Enable ADC Channel" + select RT_USING_ADC + default y + + if BSP_USING_ADC + config BSP_USING_ADC0 + bool + default n + + config BSP_USING_ADC0_CH0 + bool "Enable ADC0 Channel0" + select BSP_USING_ADC0 + default y + + config BSP_USING_ADC0_CH1 + bool "Enable ADC0 Channel1" + select BSP_USING_ADC0 + default n + + config BSP_USING_ADC0_CH8 + bool "Enable ADC0 Channel8" + select BSP_USING_ADC0 + default n + + config BSP_USING_ADC0_CH13 + bool "Enable ADC0 Channel13" + select BSP_USING_ADC0 + default n + + config BSP_USING_ADC0_CH26 + bool "Enable ADC0 Channel26" + select BSP_USING_ADC0 + default n + + endif + + menuconfig BSP_USING_DAC + config BSP_USING_DAC + bool "Enable DAC Channel" + select RT_USING_DAC + default y + + if BSP_USING_DAC + config BSP_USING_DAC0 + bool "Enable DAC0 Channel" + default n + + config BSP_USING_DAC1 + bool "Enable DAC1 Channel" + default n + + config BSP_USING_DAC2 + bool "Enable DAC2 Channel" + default n + + endif + + config BSP_USING_SDIO + bool "Enable SDIO SD Card Interface" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default y + + config BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_USING_NETDEV + select RT_USING_SAL + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default y + + config BSP_USING_WDT + bool "Enable WatchDog" + select RT_USING_WDT + default n + + menuconfig BSP_USING_HWTIMER + config BSP_USING_HWTIMER + bool "Enable Timer" + select RT_USING_HWTIMER + default y + + menuconfig BSP_USING_PWM + config BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default y + + if BSP_USING_PWM + config BSP_USING_LEDG_PWM + bool "Enable on-board green LED as PWM output (pwm0, channel 3)" + default y + endif + +endmenu + + +menu "Board extended module Drivers" + menuconfig BSP_USING_RW007 + bool "Enable RW007" + default n + select BSP_USING_SPI + select BSP_USING_SPI1 + select PKG_USING_RW007 + select RT_USING_MEMPOOL + select RW007_NOT_USE_EXAMPLE_DRIVERS + + if BSP_USING_RW007 + config BOARD_RW007_SPI_BUS_NAME + string "RW007 BUS NAME" + default "spi1" + + config BOARD_RW007_CS_PIN + hex "CS pin index" + default 27 + + config BOARD_RW007_INT_BUSY_PIN + hex "INT/BUSY pin index" + default 10 + + config BOARD_RW007_RST_PIN + hex "RESET pin index" + default 28 + endif +endmenu + +endmenu diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/clock_config.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/clock_config.c new file mode 100644 index 0000000000..4834d2d305 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/clock_config.c @@ -0,0 +1,141 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MCXN947 +package_id: MCXN947VDF +mcu_data: ksdk2_0 +processor_version: 0.13.2 +board: MCX-N9XX-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + + +void BOARD_BootClockPLL150M(void) +{ + /*!< Enable SCG clock */ + CLOCK_EnableClock(kCLOCK_Scg); + + CLOCK_SetupExtClocking(24000000U); + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */ + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + /*!< Set up PLL0 */ + const pll_setup_t pll0Setup = { + .pllctrl = SCG_APLLCTRL_SOURCE(0U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(4U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(50), + .pllRate = 190000000U + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */ + + /* Configure FREQME clock */ + SYSCON->CLOCK_CTRL |= + SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK | SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK | + SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; /* Enable FRO 1M, 12M and HF to frequency measure module */ + CLOCK_EnableClock(kCLOCK_InputMux); + INPUTMUX->FREQMEAS_REF = INPUTMUX_FREQMEAS_REF_INP(2); + INPUTMUX->FREQMEAS_TAR = INPUTMUX_FREQMEAS_REF_INP(2); + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_PLLCLKDIV); /*!< Switch PLLCLKDIV to PLL0 */ + CLOCK_AttachClk(kPLL_DIV_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to PLL_DIV */ + CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0); /*!< Switch FLEXCAN0 to FRO_HF */ + CLOCK_AttachClk(kFRO_HF_to_FLEXCAN1); /*!< Switch FLEXCAN1 to FRO_HF */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivTraceClk, 1U); /*!< Set TRACECLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +} + + +void BOARD_BootClockPLL180M(void) +{ + /*!< Enable SCG clock */ + CLOCK_EnableClock(kCLOCK_Scg); + + CLOCK_SetupExtClocking(24000000U); + CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */ + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + /*!< Set up PLL0 */ + const pll_setup_t pll0Setup = { + .pllctrl = SCG_APLLCTRL_SOURCE(0U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U), + .pllndiv = SCG_APLLNDIV_NDIV(4U), + .pllpdiv = SCG_APLLPDIV_PDIV(1U), + .pllmdiv = SCG_APLLMDIV_MDIV(60), + .pllRate = 1800000000U + }; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */ + + /* Configure FREQME clock */ + SYSCON->CLOCK_CTRL |= + SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK | SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK | + SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; /* Enable FRO 1M, 12M and HF to frequency measure module */ + CLOCK_EnableClock(kCLOCK_InputMux); + INPUTMUX->FREQMEAS_REF = INPUTMUX_FREQMEAS_REF_INP(2); + INPUTMUX->FREQMEAS_TAR = INPUTMUX_FREQMEAS_REF_INP(2); + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_PLLCLKDIV); /*!< Switch PLLCLKDIV to PLL0 */ + CLOCK_AttachClk(kPLL_DIV_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to PLL_DIV */ + CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0); /*!< Switch FLEXCAN0 to FRO_HF */ + CLOCK_AttachClk(kFRO_HF_to_FLEXCAN1); /*!< Switch FLEXCAN1 to FRO_HF */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivTraceClk, 1U); /*!< Set TRACECLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK; +} + + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/clock_config.h b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/clock_config.h new file mode 100644 index 0000000000..c86a156eef --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/clock_config.h @@ -0,0 +1,167 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ +#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ +#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF144M ******************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */ +#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFROHF144M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF144M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U +#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + + +void BOARD_BootClockPLL150M(void); +void BOARD_BootClockPLL180M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ +#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/pin_mux.c new file mode 100644 index 0000000000..e9f7ca5f09 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/pin_mux.c @@ -0,0 +1,271 @@ +#include "rtconfig.h" + +#include "fsl_common.h" +#include "fsl_port.h" +#include "pin_mux.h" + + +void BOARD_InitBootPins(void) +{ + CLOCK_EnableClock(kCLOCK_Port0); + CLOCK_EnableClock(kCLOCK_Port1); + CLOCK_EnableClock(kCLOCK_Port2); + CLOCK_EnableClock(kCLOCK_Port3); + CLOCK_EnableClock(kCLOCK_Port4); + + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + CLOCK_EnableClock(kCLOCK_Gpio2); + CLOCK_EnableClock(kCLOCK_Gpio3); + CLOCK_EnableClock(kCLOCK_Gpio4); + + + + /* UART */ + PORT1->PCR[8] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* FC4_P0 */ + PORT1->PCR[9] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* FC4_P1 */ + + /* Mikro Bus UART */ +// PORT1->PCR[16] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* FC5_P0 */ +// PORT1->PCR[17] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* FC5_P1 */ + + PORT1->PCR[16] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_UART */ + PORT1->PCR[17] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_UART */ + + /* DAC */ + // PORT4->PCR[2] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(0); /* DAC0 */ + // PORT4->PCR[3] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(0); /* DAC1 */ + + /* MCX_RST UART */ + PORT4->PCR[2] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC2_UART */ + PORT4->PCR[3] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC2_UART */ + + + PORT0->PCR[6] = PORT_PCR_MUX(12) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* CLKOUT */ + +#ifdef BSP_USING_I2C1 + PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC1 I2C_SDA */ + PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC1 I2C_SCL */ +#endif + + PORT0->PCR[16] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC0 I2C_SDA */ + PORT0->PCR[17] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1) | PORT_PCR_SRE(0) | PORT_PCR_ODE(0); /* FC0 I2C_SCL */ + + +#ifdef BSP_USING_SPI1 + /* Arduino D11(P0_24), D12(P0_26), D13(P0_25) as SPI function, for RW007 MOSI, MISO, CLK */ + PORT0->PCR[24] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_24: FC1_0 */ + PORT0->PCR[26] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_26: FC1_2 */ + PORT0->PCR[25] = PORT_PCR_MUX(2) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_25: FC1_1 */ + + /* Arduino D8(P0_28), D9(P0_10), D10(P0_27) as GPIO function, for RW007 RST, INT, CS */ + /* drv_pin.c works well, follow lines just notice that pins we used as GPIO function */ + // PORT0->PCR[28] = PORT_PCR_MUX(0) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_28: P0_28 */ + // PORT0->PCR[10] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_10: P0_27 */ + PORT0->PCR[27] = PORT_PCR_MUX(0) | PORT_PCR_PS(1) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* P0_27: P0_27 */ +#endif + + /* PMOD */ + PORT1->PCR[0] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_0 SDO/D[0], FC3_SPI_MOSI */ + PORT1->PCR[1] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_1 SCK, FC3_SPI_CLK */ + PORT1->PCR[2] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_2 SDI/D[1], FC3_SPI_MISO */ + PORT1->PCR[3] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* CS */ +// PORT1->PCR[3] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_3 CS0 */ +// PORT1->PCR[4] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_4 D[3] */ +// PORT1->PCR[5] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC3_5 D[2] */ + + /* SPI */ + PORT3->PCR[8] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P0, MOSI */ + PORT3->PCR[9] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P2, MISO */ + PORT3->PCR[7] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P1, CLK */ + PORT3->PCR[0] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC7_P1, CS */ + + PORT1->PCR[8] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC4_UART */ + PORT1->PCR[9] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC4_UART */ + + + PORT1->PCR[10] = PORT_PCR_MUX(11) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* CAN0_TX */ + PORT1->PCR[11] = PORT_PCR_MUX(11) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* CAN0_RX */ + + + PORT1->PCR[12] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC3_0 SDO/D[0] */ + PORT1->PCR[13] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC3_1 SCK */ + PORT1->PCR[14] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC3_2 SDI/D[1] */ + PORT1->PCR[15] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC3_3 CS0 */ +// PORT1->PCR[16] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC3_4 D[3] */ +// PORT1->PCR[17] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC3_5 D[2] */ + +// PORT1->PCR[8] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_4 D[3] */ +// PORT1->PCR[9] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_5 D[2] */ + PORT1->PCR[4] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_0 SDO/D[0] */ + PORT1->PCR[5] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_1 SCK */ + PORT1->PCR[6] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_2 SDI/D[1] */ + PORT1->PCR[7] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* FC5_3 CS0 */ + + PORT2->PCR[2] = PORT_PCR_MUX(3) | PORT_PCR_PE(0) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* SDHC0_D1 */ + PORT2->PCR[3] = PORT_PCR_MUX(3) | PORT_PCR_PE(1) | PORT_PCR_PS(1) | PORT_PCR_IBE(1); /* SDHC0_D0 */ + PORT2->PCR[4] = PORT_PCR_MUX(3) | PORT_PCR_PE(0) | PORT_PCR_PS(0) | PORT_PCR_IBE(1); /* SDHC0_CLK */ + PORT2->PCR[5] = PORT_PCR_MUX(3) | PORT_PCR_PE(1) | PORT_PCR_PS(1) | PORT_PCR_IBE(1); /* SDHC0_CMD */ + PORT2->PCR[6] = PORT_PCR_MUX(3) | PORT_PCR_PE(1) | PORT_PCR_PS(1) | PORT_PCR_IBE(1); /* SDHC0_D3 */ + PORT2->PCR[7] = PORT_PCR_MUX(3) | PORT_PCR_PE(1) | PORT_PCR_PS(1) | PORT_PCR_IBE(1); /* SDHC0_D2 */ + + /* mikroBUS SPI6 */ + PORT3->PCR[20] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC6_P0 SDO/D[0], FC6_SPI_MOSI */ + PORT3->PCR[21] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC6_P1 SCK, FC6_SPI_CLK */ + PORT3->PCR[22] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC6_P2 SDI/D[1], FC3_SPI_MISO */ + PORT3->PCR[23] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* CS */ + + +// PORT1->PCR[20] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_0 */ +// PORT1->PCR[21] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_1 */ +// PORT1->PCR[22] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_2 */ +// PORT1->PCR[23] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_3 */ +// PORT1->PCR[0] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_4 */ +// PORT1->PCR[1] = PORT_PCR_MUX(3) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC4_5 */ + +// PORT4->PCR[0] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ANA_0, ADC0_A0 */ +// PORT4->PCR[1] = PORT_PCR_MUX(0) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ANA_1, ADC0_B0 */ + + PORT4->PCR[0] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC2_P0 I2C_SDA */ + PORT4->PCR[1] = PORT_PCR_MUX(2) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* FC2_P1 I2C_SCL */ + + /* FLEXIO */ + PORT0->PCR[ 9] = PORT_PCR_MUX(6) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; /* FLEXIO WR */ + PORT0->PCR[ 8] = PORT_PCR_MUX(6) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; /* FLEXIO RD */ + PORT0->PCR[12] = PORT_PCR_MUX(0) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; /* FLEXIO CS */ + PORT0->PCR[ 7] = PORT_PCR_MUX(0) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; /* FLEXIO RS */ + + PORT2->PCR[ 8] = PORT_PCR_MUX(FLEXIO_DATA0_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D0 */ + PORT2->PCR[ 9] = PORT_PCR_MUX(FLEXIO_DATA1_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D1 */ + PORT2->PCR[10] = PORT_PCR_MUX(FLEXIO_DATA2_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D2 */ + PORT2->PCR[11] = PORT_PCR_MUX(FLEXIO_DATA3_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D3 */ + PORT4->PCR[12] = PORT_PCR_MUX(FLEXIO_DATA4_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D4 */ + PORT4->PCR[13] = PORT_PCR_MUX(FLEXIO_DATA5_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D5 */ + PORT4->PCR[14] = PORT_PCR_MUX(FLEXIO_DATA6_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D6 */ + PORT4->PCR[15] = PORT_PCR_MUX(FLEXIO_DATA7_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D7 */ + PORT4->PCR[16] = PORT_PCR_MUX(FLEXIO_DATA8_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D8 */ + + +// PORT4->PCR[15] = PORT_PCR_MUX(11) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* CAN1 */ +// PORT4->PCR[16] = PORT_PCR_MUX(11) | PORT_PCR_PS(0) | PORT_PCR_PE(1) | PORT_PCR_IBE(1); /* CAN */ + + + PORT4->PCR[17] = PORT_PCR_MUX(FLEXIO_DATA9_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D9 */ + PORT4->PCR[18] = PORT_PCR_MUX(FLEXIO_DATA10_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D10 */ + PORT4->PCR[19] = PORT_PCR_MUX(FLEXIO_DATA11_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D11 */ + PORT4->PCR[20] = PORT_PCR_MUX(FLEXIO_DATA12_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D12 */ + PORT4->PCR[21] = PORT_PCR_MUX(FLEXIO_DATA13_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D13 */ + PORT4->PCR[22] = PORT_PCR_MUX(FLEXIO_DATA14_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D14 */ + PORT4->PCR[23] = PORT_PCR_MUX(FLEXIO_DATA15_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS(0); /* FXIO0_D15 */ + + + /* ENET */ + PORT1->PCR[13] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_RXDV */ + PORT1->PCR[14] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_RXD0 */ + PORT1->PCR[15] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_RXD1 */ + PORT1->PCR[20] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_MDC */ + PORT1->PCR[21] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_MDIO */ + PORT1->PCR[4] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_TX_CLK */ + PORT1->PCR[5] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_TXEN */ + PORT1->PCR[6] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_TXD0 */ + PORT1->PCR[7] = PORT_PCR_MUX(9) | PORT_PCR_PS(0) | PORT_PCR_PE(0) | PORT_PCR_IBE(1); /* ENET0_TXD1 */ + +} + + + +/* Configure port mux of FlexIO data pins */ +void FLEXIO_8080_Config_Data_Pin(void) +{ + +} + + +/* Configure FLEXIO_WR pin as FlexIO function */ +void FLEXIO_8080_Config_WR_FlexIO(void) +{ + // FLEXIO_WR_PORT->PCR[FLEXIO_WR_PIN] = PORT_PCR_MUX(FLEXIO_WR_PIN_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; +} + +/* Configure FLEXIO_WR pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_WR_GPIO(void) +{ + +} + +/* Configure FLEXIO_RD pin as FlexIO function */ +void FLEXIO_8080_Config_RD_FlexIO(void) +{ + // FLEXIO_RD_PORT->PCR[FLEXIO_RD_PIN] = PORT_PCR_MUX(FLEXIO_RD_PIN_MUX) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; +} + +/* Configure FLEXIO_RD pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_RD_GPIO(void) +{ +// FLEXIO_RD_GPIO->PSOR |= 1U << FLEXIO_RD_PIN; +// FLEXIO_RD_GPIO->PDDR |= 1U << FLEXIO_RD_PIN; +// FLEXIO_RD_PORT->PCR[FLEXIO_RD_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; +} + +/* Configure FLEXIO_CS pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_CS_GPIO(void) +{ + FLEXIO_CS_GPIO->PSOR |= 1U << FLEXIO_CS_PIN; + FLEXIO_CS_GPIO->PDDR |= 1U << FLEXIO_CS_PIN; +// FLEXIO_CS_PORT->PCR[FLEXIO_CS_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; +} + +/* Set FLEXIO_CS pin's level */ +void FLEXIO_8080_Set_CS_Pin(bool level) +{ + if(level) + { + FLEXIO_CS_GPIO->PSOR |= 1U << FLEXIO_CS_PIN; + } + else + { + FLEXIO_CS_GPIO->PCOR |= 1U << FLEXIO_CS_PIN; + } +} + +/* Configure RS pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_RS_GPIO(void) +{ + FLEXIO_RS_GPIO->PSOR |= 1U << FLEXIO_RS_PIN; + FLEXIO_RS_GPIO->PDDR |= 1U << FLEXIO_RS_PIN; +// FLEXIO_RS_PORT->PCR[FLEXIO_RS_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; +} + +/* Set RS pin's level */ +void FLEXIO_8080_Set_RS_Pin(bool level) +{ + if(level) + { + FLEXIO_RS_GPIO->PSOR |= 1U << FLEXIO_RS_PIN; + } + else + { + FLEXIO_RS_GPIO->PCOR |= 1U << FLEXIO_RS_PIN; + } +} + +/* Configure ReSet pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_ReSet_GPIO(void) +{ + FLEXIO_ReSet_GPIO->PSOR |= 1U << FLEXIO_ReSet_PIN; + FLEXIO_ReSet_GPIO->PDDR |= 1U << FLEXIO_ReSet_PIN; + FLEXIO_ReSet_PORT->PCR[FLEXIO_ReSet_PIN] = PORT_PCR_MUX(0U) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; +} + +/* Set ReSet pin's level */ +void FLEXIO_8080_Set_ReSet_Pin(bool level) +{ + if(level) + { + FLEXIO_ReSet_GPIO->PSOR |= 1U << FLEXIO_ReSet_PIN; + } + else + { + FLEXIO_ReSet_GPIO->PCOR |= 1U << FLEXIO_ReSet_PIN; + } +} diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/pin_mux.h b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/pin_mux.h new file mode 100644 index 0000000000..cf8440c889 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/MCUX_Config/board/pin_mux.h @@ -0,0 +1,160 @@ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + + +#if defined(__cplusplus) +extern "C" { +#endif + + +#define PCR_IBE_ibe1 0x01u /*!<@brief Input Buffer Enable: Enables */ + + + +#define FLEXIO_DATA0_FXIOD_INDEX 16U + +#define FLEXIO_DATA0_PORT PORT2 +#define FLEXIO_DATA0_PIN 8U +#define FLEXIO_DATA0_MUX 6U + +#define FLEXIO_DATA1_PORT PORT2 +#define FLEXIO_DATA1_PIN 9U +#define FLEXIO_DATA1_MUX 6U + +#define FLEXIO_DATA2_PORT PORT2 +#define FLEXIO_DATA2_PIN 10U +#define FLEXIO_DATA2_MUX 6U + +#define FLEXIO_DATA3_PORT PORT2 +#define FLEXIO_DATA3_PIN 11U +#define FLEXIO_DATA3_MUX 6U + +#define FLEXIO_DATA4_PORT PORT4 +#define FLEXIO_DATA4_PIN 12U +#define FLEXIO_DATA4_MUX 6U + +#define FLEXIO_DATA5_PORT PORT4 +#define FLEXIO_DATA5_PIN 13U +#define FLEXIO_DATA5_MUX 6U + +#define FLEXIO_DATA6_PORT PORT4 +#define FLEXIO_DATA6_PIN 14U +#define FLEXIO_DATA6_MUX 6U + +#define FLEXIO_DATA7_PORT PORT4 +#define FLEXIO_DATA7_PIN 15U +#define FLEXIO_DATA7_MUX 6U + +#define FLEXIO_DATA8_PORT PORT4 +#define FLEXIO_DATA8_PIN 16U +#define FLEXIO_DATA8_MUX 6U + +#define FLEXIO_DATA9_PORT PORT4 +#define FLEXIO_DATA9_PIN 17U +#define FLEXIO_DATA9_MUX 6U + +#define FLEXIO_DATA10_PORT PORT4 +#define FLEXIO_DATA10_PIN 18U +#define FLEXIO_DATA10_MUX 6U + +#define FLEXIO_DATA11_PORT PORT4 +#define FLEXIO_DATA11_PIN 19U +#define FLEXIO_DATA11_MUX 6U + +#define FLEXIO_DATA12_PORT PORT4 +#define FLEXIO_DATA12_PIN 20U +#define FLEXIO_DATA12_MUX 6U + +#define FLEXIO_DATA13_PORT PORT4 +#define FLEXIO_DATA13_PIN 21U +#define FLEXIO_DATA13_MUX 6U + +#define FLEXIO_DATA14_PORT PORT4 +#define FLEXIO_DATA14_PIN 22U +#define FLEXIO_DATA14_MUX 6U + +#define FLEXIO_DATA15_PORT PORT4 +#define FLEXIO_DATA15_PIN 23U +#define FLEXIO_DATA15_MUX 6U + +#define FLEXIO_WR_PIN_FXIOD_INDEX 1U /* WR pin */ +#define FLEXIO_WR_PORT PORT0 +#define FLEXIO_WR_PIN 9U +#define FLEXIO_WR_GPIO GPIO0 +#define FLEXIO_WR_PIN_MUX 6U + +#define FLEXIO_RD_PIN_FXIOD_INDEX 0U /* RD pin */ +#define FLEXIO_RD_PORT PORT0 +#define FLEXIO_RD_PIN 8U +#define FLEXIO_RD_GPIO GPIO0 +#define FLEXIO_RD_PIN_MUX 6U + +#define FLEXIO_CS_PORT PORT0 +#define FLEXIO_CS_PIN 12U /* CS pin */ +#define FLEXIO_CS_GPIO GPIO0 + +#define FLEXIO_RS_PORT PORT0 +#define FLEXIO_RS_PIN 7U /* RS pin */ +#define FLEXIO_RS_GPIO GPIO0 + +#define FLEXIO_ReSet_PORT PORT4 +#define FLEXIO_ReSet_PIN 7U /* RS pin */ +#define FLEXIO_ReSet_GPIO GPIO4 + +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +/* Configure port mux of FlexIO data pins */ +void FLEXIO_8080_Config_Data_Pin(void); + +/* Configure WR pin as FlexIO function */ +void FLEXIO_8080_Config_WR_FlexIO(void); + +/* Configure WR pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_WR_GPIO(void); + +/* Configure RD pin as FlexIO function */ +void FLEXIO_8080_Config_RD_FlexIO(void); + +/* Configure RD pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_RD_GPIO(void); + +/* Configure CS pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_CS_GPIO(void); + +/* Set CS pin's level */ +void FLEXIO_8080_Set_CS_Pin(bool level); + +/* Configure RS pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_RS_GPIO(void); + +/* Set RS pin's level */ +void FLEXIO_8080_Set_RS_Pin(bool level); + + +/* Configure ReSet pin as GPIO function and outputting high level */ +void FLEXIO_8080_Config_ReSet_GPIO(void); + +/* Set ReSet pin's level */ +void FLEXIO_8080_Set_ReSet_Pin(bool level); + +void LPSPI1_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/SConscript b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/SConscript new file mode 100644 index 0000000000..cb4107351f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/SConscript @@ -0,0 +1,27 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/board/clock_config.c +MCUX_Config/board/pin_mux.c +""") + +if GetDepend(['BSP_USING_SPI6_SAMPLE']): + src += Glob('ports/spi_sample.c') + +if GetDepend(['BSP_USING_RW007']): + src += Glob('ports/drv_spi_sample_rw007.c') + +if GetDepend(['RT_USING_SFUD']): + src += Glob('ports/drv_filesystem_spi_flash.c') + + +CPPPATH = [cwd, cwd + '/MCUX_Config/board'] +CPPDEFINES = ['DEBUG', 'CPU_MCXN236VDF'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/board.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/board.c new file mode 100644 index 0000000000..c7fd47bac4 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/board.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-01-29 yandld first implementation + */ + +#include +#include + +#include "board.h" +#include "clock_config.h" +#include "pin_mux.h" +#include "drv_uart.h" +#include "fsl_port.h" +#include "fsl_cache_lpcac.h" + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial board. + */ +void rt_hw_board_init() +{ + /* Hardware Initialization */ + BOARD_InitBootPins(); + L1CACHE_EnableCodeCache(); + + CLOCK_EnableClock(kCLOCK_Freqme); + CLOCK_EnableClock(kCLOCK_InputMux); + + CLOCK_EnableClock(kCLOCK_Port0); + CLOCK_EnableClock(kCLOCK_Port1); + CLOCK_EnableClock(kCLOCK_Port2); + CLOCK_EnableClock(kCLOCK_Port3); + CLOCK_EnableClock(kCLOCK_Port4); + + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + CLOCK_EnableClock(kCLOCK_Gpio2); + CLOCK_EnableClock(kCLOCK_Gpio3); + CLOCK_EnableClock(kCLOCK_Gpio4); + + CLOCK_EnableClock(kCLOCK_Pint); + CLOCK_EnableClock(kCLOCK_Flexcan0); + CLOCK_EnableClock(kCLOCK_Flexcan1); + + CLOCK_AttachClk(kFRO_HF_to_ADC0); + CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 1u); + + /* enable VREF */ + SPC0->ACTIVE_CFG1 |= 0xFFFFFFFF; + + CLOCK_EnableClock(kCLOCK_Dma0); + CLOCK_EnableClock(kCLOCK_Dma1); + + edma_config_t userConfig = {0}; + EDMA_GetDefaultConfig(&userConfig); + EDMA_Init(DMA0, &userConfig); + EDMA_Init(DMA1, &userConfig); + + /* This init has finished in secure side of TF-M */ + BOARD_InitBootClocks(); + + CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToAll); + + CLOCK_AttachClk(kPLL0_to_CTIMER0); + CLOCK_AttachClk(kPLL0_to_CTIMER1); + CLOCK_AttachClk(kPLL0_to_CTIMER2); + CLOCK_AttachClk(kPLL0_to_CTIMER3); + CLOCK_AttachClk(kPLL0_to_CTIMER4); + CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1u); + CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1u); + CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1u); + CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1u); + CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1u); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + + /*init uart device*/ + rt_hw_uart_init(); + +#if defined(BSP_USING_LEDG_PWM) && defined(BSP_USING_PWM) + PORT_SetPinMux(PORT0, 27, kPORT_MuxAlt4); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization board with RT-Thread Components */ + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)(HEAP_END)); +#endif +} + +/** + * This function will called when memory fault. + */ +void MemManage_Handler(void) +{ + extern void HardFault_Handler(void); + + rt_kprintf("Memory Fault!\n"); + HardFault_Handler(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/board.h b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/board.h new file mode 100644 index 0000000000..38ad39e8de --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/board.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + * 2013-12-18 Bernard porting to LPC4088 bsp + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#include + +#include + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_gpio.h" +#include "pin_mux.h" +#include "fsl_edma.h" + +// + +// +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_STACK$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void*)&Image$$ARM_LIB_STACK$$ZI$$Base) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__section_begin("HEAP")) +#define HEAP_END (__section_end("HEAP")) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +void rt_hw_board_init(void); + + +#endif + + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.icf b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.icf new file mode 100644 index 0000000000..2b270a923f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.icf @@ -0,0 +1,86 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2021-08-03 +** Build: b240320 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +define symbol usb_bdt_size = 0x0; +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x2000; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x000FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x20037FFF; + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04017FFF; + + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__] | + mem:[from m_sramx_start to m_sramx_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; +define block QACCESS_CODE { section CodeQuickAccess }; +define block QACCESS_DATA { section DataQuickAccess }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in DATA_region { block NCACHE_VAR }; +place in DATA_region { block QACCESS_CODE }; +place in DATA_region { block QACCESS_DATA }; diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.ld b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.ld new file mode 100644 index 0000000000..0c3cacbd9d --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.ld @@ -0,0 +1,205 @@ +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compiler: GNU C Compiler +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2021-08-03 +** Build: b240320 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x000FFC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00038000 + m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00018000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(NonCacheable.init) /* NonCacheable init section */ + *(NonCacheable) /* NonCacheable section */ + *(CodeQuickAccess) /* quick access code section */ + *(DataQuickAccess) /* quick access data section */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.scf b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.scf new file mode 100644 index 0000000000..36b28a9ff6 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/linker_scripts/MCXN236_flash.scf @@ -0,0 +1,80 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: MCXN236VDF +** MCXN236VNL +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: MCXN23XRM +** Version: rev. 1.0, 2021-08-03 +** Build: b240320 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* USB BDT size */ +#define usb_bdt_size 0x0 +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x000FFC00 + + +#define m_data_start 0x20000000 +#define m_data_size 0x00038000 + +#define m_sramx_start 0x04000000 +#define m_sramx_size 0x00018000 + + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + * (RamFunction) + * (NonCacheable.init) + * (*NonCacheable) + * (CodeQuickAccess) + * (DataQuickAccess) + } + + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_filesystem_spi_flash.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_filesystem_spi_flash.c new file mode 100644 index 0000000000..be61835796 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_filesystem_spi_flash.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-14 balanceTWK add sdcard port file + * 2021-02-26 Meco Man fix a bug that cannot use fatfs in the main thread at starting up + */ + +#include + +#if defined(BSP_USING_SPI7) && defined(RT_USING_SFUD) && defined(RT_USING_DFS) && defined(RT_USING_DFS_ELMFAT) +#include +#include "spi_flash_sfud.h" +#include "dfs_fs.h" +#include "dfs.h" +#include "dfs_file.h" + +#define DBG_TAG "spi-flash" +#define DBG_LVL DBG_INFO +#include + +#if DFS_FILESYSTEMS_MAX < 4 +#error "Please define DFS_FILESYSTEMS_MAX more than 4" +#endif +#if DFS_FILESYSTEM_TYPES_MAX < 4 +#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4" +#endif + + +#define DBG_TAG "app.filesystem_spi_flash" +#define DBG_LVL DBG_INFO +#include + + +#define W25Q64_SPI_DEVICE_NAME "spi70" +#define W25Q64_SPI_BUS_NAME "spi7" +#define W25Q64_SPI_FLASH_NAME "w25qxx" + +rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin); + +static int filesystem_mount(void) +{ + struct rt_spi_device *spi70 = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + + if(!spi70) + { + LOG_W("spi sample run failed! can't find %s device!\n","spi7"); + return -RT_ERROR; + } + + struct rt_spi_configuration cfg; + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_3 | RT_SPI_MSB; + cfg.max_hz = 50 * 1000 *1000; + rt_spi_configure(spi70, &cfg); + + /* legcy issue */ + + rt_hw_spi_device_attach(W25Q64_SPI_BUS_NAME, W25Q64_SPI_DEVICE_NAME, 96); + + if(RT_NULL == rt_sfud_flash_probe(W25Q64_SPI_FLASH_NAME, W25Q64_SPI_DEVICE_NAME)) + { + LOG_E("Flash sfud Failed!\n"); + return -RT_ERROR; + } + if(dfs_mount(W25Q64_SPI_FLASH_NAME, "/", "elm", 0, 0)) + { + LOG_E("dfs mount dev:%s failed!\n", W25Q64_SPI_FLASH_NAME); + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_APP_EXPORT(filesystem_mount); + +#endif /* BSP_USING_SPI7/RT_USING_SFUD/RT_USING_DFS/RT_USING_DFS_ELMFAT */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_fxas2100.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_fxas2100.c new file mode 100644 index 0000000000..d655665059 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_fxas2100.c @@ -0,0 +1,165 @@ + + +#include +#include + +#define FXAS2100_DEV_NAME ("fxas2100") +#define FXAS2100_I2C_DEV_NAME ("i2c2") +#define FXAS2100_CHIP_ADDR (0x20) + +// register addresses FXAS21002C_H_ +#define FXAS21002C_H_STATUS 0x00 +#define FXAS21002C_H_DR_STATUS 0x07 +#define FXAS21002C_H_F_STATUS 0x08 +#define FXAS21002C_H_OUT_X_MSB 0x01 +#define FXAS21002C_H_OUT_X_LSB 0x02 +#define FXAS21002C_H_OUT_Y_MSB 0x03 +#define FXAS21002C_H_OUT_Y_LSB 0x04 +#define FXAS21002C_H_OUT_Z_MSB 0x05 +#define FXAS21002C_H_OUT_Z_LSB 0x06 +#define FXAS21002C_H_F_SETUP 0x09 +#define FXAS21002C_H_F_EVENT 0x0A +#define FXAS21002C_H_INT_SRC_FLAG 0x0B +#define FXAS21002C_H_WHO_AM_I 0x0C +#define FXAS21002C_H_CTRL_REG0 0x0D +#define FXAS21002C_H_RT_CFG 0x0E +#define FXAS21002C_H_RT_SRC 0x0F +#define FXAS21002C_H_RT_THS 0x10 +#define FXAS21002C_H_RT_COUNT 0x11 +#define FXAS21002C_H_TEMP 0x12 +#define FXAS21002C_H_CTRL_REG1 0x13 +#define FXAS21002C_H_CTRL_REG2 0x14 +#define FXAS21002C_H_CTRL_REG3 0x15 + +#define DBG_TAG "drv.fxas2100" +#define DBG_LVL DBG_LOG +#include + + + +typedef struct +{ + struct rt_device parent; + struct rt_i2c_bus_device *bus; + uint8_t i2c_addr; +}fxas2100_t; + + +static uint8_t fxos_read_reg(fxas2100_t *dev, uint8_t reg_addr) +{ + uint8_t val; + + rt_i2c_master_send(dev->bus, dev->i2c_addr, RT_I2C_WR, ®_addr, 1); + rt_i2c_master_recv(dev->bus, dev->i2c_addr, RT_I2C_RD, &val, 1); + return val; +} + + +static void fxos_write_reg(fxas2100_t *dev, uint8_t reg_addr, uint8_t val) +{ + uint8_t buf[2]; + buf[0] = reg_addr; + buf[1] = val; + + rt_i2c_master_send(dev->bus, dev->i2c_addr, RT_I2C_WR, buf, 2); +} + + + +static rt_err_t fxas2100_open(rt_device_t dev, rt_uint16_t oflag) +{ + int i; + uint8_t val; + + fxas2100_t *fxas2100 = (fxas2100_t *)dev; + + for(i=0; i<5; i++) + { + val = fxos_read_reg(fxas2100, 0x0C); + + if(val == 0xD7) + { + LOG_D("fxas2100 found, id:0x%X", val); + /* stand by */ + val = fxos_read_reg(fxas2100, FXAS21002C_H_CTRL_REG1); + fxos_write_reg(fxas2100, FXAS21002C_H_CTRL_REG1, val & ~(0x03)); + + // Disable FIFO, route FIFO and rate threshold interrupts to INT2, enable data ready interrupt, route to INT1 + // Active HIGH, push-pull output driver on interrupts + fxos_write_reg(fxas2100, FXAS21002C_H_CTRL_REG2, 0x0E); + fxos_write_reg(fxas2100, FXAS21002C_H_CTRL_REG0, 0x80); + + // Set up rate threshold detection; at max rate threshold = FSR; rate threshold = THS*FSR/128 + fxos_write_reg(fxas2100, FXAS21002C_H_RT_CFG, 0x07); // enable rate threshold detection on all axes + fxos_write_reg(fxas2100, FXAS21002C_H_RT_THS, 0x00 | 0x0D); // unsigned 7-bit THS, set to one-tenth FSR; set clearing debounce counter + fxos_write_reg(fxas2100, FXAS21002C_H_RT_COUNT, 0x04); // set to 4 (can set up to 255) + + val = fxos_read_reg(fxas2100, FXAS21002C_H_CTRL_REG1); + fxos_write_reg(fxas2100, FXAS21002C_H_CTRL_REG1, val & ~(0x03)); // Clear bits 0 and 1; standby mode + fxos_write_reg(fxas2100, FXAS21002C_H_CTRL_REG1, val | 0x02); // Set bit 1 to 1, active mode; data acquisition enabled + return RT_EOK; + } + else + { + LOG_D("fxas2100 cannot found, id:0x%X", val); + } + + } + + return RT_ERROR; +} + + +static rt_ssize_t fxas2100_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + fxas2100_t *fxas2100 = (fxas2100_t *)dev; + + uint8_t buf[12]; + buf[0] = FXAS21002C_H_OUT_X_MSB; + + rt_i2c_master_send(fxas2100->bus, fxas2100->i2c_addr, RT_I2C_WR, buf, 1); + rt_i2c_master_recv(fxas2100->bus, fxas2100->i2c_addr, RT_I2C_RD, buf, 6); + + + int16_t idata[3]; + idata[0] = (int16_t)((((int16_t)buf[0] << 8) | buf[1])); + idata[1] = (int16_t)((((int16_t)buf[2] << 8) | buf[3])); + idata[2] = (int16_t)((((int16_t)buf[4] << 8) | buf[5])); + + float *out_buf = buffer; + + out_buf[0] = (float)idata[0] *(2000.0F/32768.0F); + out_buf[1] = (float)idata[1] *(2000.0F/32768.0F); + out_buf[2] = (float)idata[2] *(2000.0F/32768.0F); +} + + +int rt_hw_fxas2100_init(void) +{ + static fxas2100_t fxas2100; + struct rt_i2c_bus_device *bus; + + bus = rt_i2c_bus_device_find(FXAS2100_I2C_DEV_NAME); + if (bus == RT_NULL) + { + return RT_ENOSYS; + } + + fxas2100.parent.type = RT_Device_Class_Sensor; + fxas2100.parent.rx_indicate = RT_NULL; + fxas2100.parent.tx_complete = RT_NULL; + fxas2100.parent.init = RT_NULL; + fxas2100.parent.open = fxas2100_open; + fxas2100.parent.close = RT_NULL; + fxas2100.parent.read = fxas2100_read; + fxas2100.parent.write = RT_NULL; + fxas2100.parent.user_data = RT_NULL; + + fxas2100.bus = bus; + fxas2100.i2c_addr = FXAS2100_CHIP_ADDR; + + rt_device_register(&fxas2100.parent, FXAS2100_DEV_NAME, RT_DEVICE_FLAG_RDWR); + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_fxas2100_init); diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_fxos8700.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_fxos8700.c new file mode 100644 index 0000000000..85ee1a1476 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_fxos8700.c @@ -0,0 +1,199 @@ + + +#include +#include + +#define FXOS8700_DEV_NAME ("fxos8700") +#define FXOS8700_I2C_DEV_NAME ("i2c2") +#define FXOS8700_CHIP_ADDR (0x1E) + + +#define DBG_TAG "drv.fxos8700" +#define DBG_LVL DBG_LOG +#include + + + + +#define CTRL_REG1 0x2A +#define XYZ_DATA_CFG_REG 0x0E +#define M_CTRL_REG1 0x5B +#define F_SETUP_REG 0x09 +#define M_CTRL_REG2 0x5C +#define OUT_X_MSB_REG 0x01 +#define OUT_X_LSB_REG 0x02 +#define OUT_Y_MSB_REG 0x03 +#define OUT_Y_LSB_REG 0x04 +#define OUT_Z_MSB_REG 0x05 +#define OUT_Z_LSB_REG 0x06 + + +#define F_MODE_DISABLED 0x00 +#define ASLP_RATE1_MASK 0x80 +#define ASLP_RATE0_MASK 0x40 +#define DR2_MASK 0x20 +#define DR1_MASK 0x10 +#define DR0_MASK 0x08 +#define LNOISE_MASK 0x04 +#define FREAD_MASK 0x02 +#define ACTIVE_MASK 0x01 +#define ASLP_RATE_MASK 0xC0 +#define DR_MASK 0x38 +#define M_HYB_AUTOINC_MASK 0x20 +#define M_MAXMIN_DIS_MASK 0x10 +#define M_MAXMIN_DIS_THS_MASK 0x08 +#define M_MAXMIN_RST_MASK 0x04 +#define M_RST_CNT1_MASK 0x02 +#define M_RST_CNT0_MASK 0x01 + +#define M_ACAL_MASK 0x80 +#define M_RST_MASK 0x40 +#define M_OST_MASK 0x20 +#define M_OSR2_MASK 0x10 +#define M_OSR1_MASK 0x08 +#define M_OSR0_MASK 0x04 +#define M_HMS1_MASK 0x02 +#define M_HMS0_MASK 0x01 +#define M_OSR_MASK 0x1C +#define M_HMS_MASK 0x03 + + +typedef struct +{ + struct rt_device parent; + struct rt_i2c_bus_device *bus; + uint8_t i2c_addr; +}fxos8700_t; + + +static uint8_t fxos_read_reg(fxos8700_t *dev, uint8_t reg_addr) +{ + uint8_t val; + + rt_i2c_master_send(dev->bus, dev->i2c_addr, RT_I2C_WR, ®_addr, 1); + rt_i2c_master_recv(dev->bus, dev->i2c_addr, RT_I2C_RD, &val, 1); + return val; +} + + +static void fxos_write_reg(fxos8700_t *dev, uint8_t reg_addr, uint8_t val) +{ + uint8_t buf[2]; + buf[0] = reg_addr; + buf[1] = val; + + rt_i2c_master_send(dev->bus, dev->i2c_addr, RT_I2C_WR, buf, 2); +} + + + +static rt_err_t fxos8700_open(rt_device_t dev, rt_uint16_t oflag) +{ + int i; + uint8_t val; + + fxos8700_t *fxos8700 = (fxos8700_t *)dev; + + for(i=0; i<5; i++) + { + val = fxos_read_reg(fxos8700, 0x0D); + + if(val == 0xC7) + { + LOG_D("fxos8700 found, id:0x%X", val); + + /* reset */ + // fxos_write_reg(instance, gChipAddr, CTRL_REG2, RST_MASK); + /* wait for a bit */ + for (i = 0; i < 0xFFFF; i++) + { + __asm("NOP"); + } + + /* setup auto sleep with FFMT trigger */ + /* go to standby */ + val = fxos_read_reg(fxos8700, CTRL_REG1); + fxos_write_reg(fxos8700, CTRL_REG1, val & (uint8_t)~ACTIVE_MASK); + + /* Disable the FIFO */ + fxos_write_reg(fxos8700, F_SETUP_REG, F_MODE_DISABLED); + + /* set up Mag OSR and Hybrid mode using M_CTRL_REG1, use default for Acc */ + fxos_write_reg(fxos8700, M_CTRL_REG1, (M_RST_MASK | M_OSR_MASK | M_HMS_MASK)); + + /* Enable hyrid mode auto increment using M_CTRL_REG2 */ + fxos_write_reg(fxos8700, M_CTRL_REG2, (M_HYB_AUTOINC_MASK)); + + fxos_write_reg(fxos8700, XYZ_DATA_CFG_REG, 0x02); + + val = fxos_read_reg(fxos8700, CTRL_REG1); + fxos_write_reg(fxos8700, CTRL_REG1, val | LNOISE_MASK); + fxos_write_reg(fxos8700, CTRL_REG1, val | ACTIVE_MASK | LNOISE_MASK); + return RT_EOK; + } + else + { + LOG_D("fxos8700 cannot found, id:0x%X", val); + } + + } + + return RT_ERROR; +} + + + +static rt_ssize_t fxos8700_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + fxos8700_t *fxos8700 = (fxos8700_t *)dev; + + uint8_t buf[12]; + buf[0] = OUT_X_MSB_REG; + + rt_i2c_master_send(fxos8700->bus, fxos8700->i2c_addr, RT_I2C_WR, buf, 1); + rt_i2c_master_recv(fxos8700->bus, fxos8700->i2c_addr, RT_I2C_RD, buf, 12); + + + int16_t iacc[3]; + iacc[0] = (int16_t)((((int16_t)buf[0] << 8) | buf[1])); + iacc[1] = (int16_t)((((int16_t)buf[2] << 8) | buf[3])); + iacc[2] = (int16_t)((((int16_t)buf[4] << 8) | buf[5])); + + float *out_buf = buffer; + + out_buf[0] = (float)iacc[0] / 4096; + out_buf[1] = (float)iacc[1] / 4096; + out_buf[2] = (float)iacc[2] / 4096; + return 3*4; +} + + +int rt_hw_fxos8700_init(void) +{ + static fxos8700_t fxos8700; + struct rt_i2c_bus_device *bus; + + bus = rt_i2c_bus_device_find(FXOS8700_I2C_DEV_NAME); + if (bus == RT_NULL) + { + return RT_ENOSYS; + } + + fxos8700.parent.type = RT_Device_Class_Sensor; + fxos8700.parent.rx_indicate = RT_NULL; + fxos8700.parent.tx_complete = RT_NULL; + fxos8700.parent.init = RT_NULL; + fxos8700.parent.open = fxos8700_open; + fxos8700.parent.close = RT_NULL; + fxos8700.parent.read = fxos8700_read; + fxos8700.parent.write = RT_NULL; + fxos8700.parent.user_data = RT_NULL; + + fxos8700.bus = bus; + fxos8700.i2c_addr = FXOS8700_CHIP_ADDR; + + rt_device_register(&fxos8700.parent, FXOS8700_DEV_NAME, RT_DEVICE_FLAG_RDWR); + return RT_EOK; +} + +INIT_DEVICE_EXPORT(rt_hw_fxos8700_init); diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_spi_sample_rw007.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_spi_sample_rw007.c new file mode 100644 index 0000000000..9f34ffba5c --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/drv_spi_sample_rw007.c @@ -0,0 +1,68 @@ +#include + +#ifdef BSP_USING_RW007 +#include +#include +#include +#include + +extern void spi_wifi_isr(int vector); + +static void rw007_gpio_init(void) +{ + /* Configure IO */ + rt_pin_mode(BOARD_RW007_RST_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN); + + /* Reset rw007 and config mode */ + rt_pin_write(BOARD_RW007_RST_PIN, PIN_LOW); + + rt_thread_delay(rt_tick_from_millisecond(1)); + rt_pin_write(BOARD_RW007_RST_PIN, PIN_HIGH); + + /* Wait rw007 ready(exit busy stat) */ + while (!(BOARD_RW007_INT_BUSY_PIN)) + { + rt_thread_delay(5); + } + + rt_thread_delay(rt_tick_from_millisecond(200)); + rt_pin_mode(BOARD_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP); +} + +extern rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin); + +int wifi_spi_device_init(void) +{ + char sn_version[32]; + uint32_t cs_pin = BOARD_RW007_CS_PIN; + + rw007_gpio_init(); + rt_hw_spi_device_attach(BOARD_RW007_SPI_BUS_NAME, "rw007", cs_pin); + rt_hw_wifi_init("rw007"); + + rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION); + rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP); + + rw007_sn_get(sn_version); + rt_kprintf("\nrw007 sn: [%s]\n", sn_version); + rw007_version_get(sn_version); + rt_kprintf("rw007 ver: [%s]\n\n", sn_version); + + return 0; +} +INIT_APP_EXPORT(wifi_spi_device_init); + +static void int_wifi_irq(void *p) +{ + ((void)p); + spi_wifi_isr(0); +} + +void spi_wifi_hw_init(void) +{ + rt_pin_attach_irq(BOARD_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0); + rt_pin_irq_enable(BOARD_RW007_INT_BUSY_PIN, RT_TRUE); +} + +#endif \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/spi_sample.c b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/spi_sample.c new file mode 100644 index 0000000000..e2bc2ce932 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/board/ports/spi_sample.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-07-19 Rbbb666 first version + * 2024-03-30 xhackerustc 2nd version for FRDM-MCXN947 + */ + +#include "board.h" + +#include + +#define SPI_NAME "spi60" +#define CS_PIN (3*32+23) +static struct rt_spi_device *spi_dev; + +/* attach spi device */ +static int rt_spi_device_init(void) +{ + struct rt_spi_configuration cfg; + + rt_hw_spi_device_attach("spi6", SPI_NAME, CS_PIN); + + cfg.data_width = 8; + cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS; + cfg.max_hz = 1 *1000 *1000; + + spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME); + + if (RT_NULL == spi_dev) + { + rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME); + return -RT_ERROR; + } + + rt_spi_configure(spi_dev, &cfg); + + return RT_EOK; +} +INIT_APP_EXPORT(rt_spi_device_init); + +/* spi loopback mode test case */ +static int spi_sample(int argc, char **argv) +{ + rt_uint8_t t_buf[32], r_buf[32]; + int i = 0; + static struct rt_spi_message msg1; + + for (i = 0; i < sizeof(t_buf); i++) + { + t_buf[i] = i; + } + + msg1.send_buf = &t_buf; + msg1.recv_buf = &r_buf; + msg1.length = sizeof(t_buf); + msg1.cs_take = 1; + msg1.cs_release = 1; + msg1.next = RT_NULL; + + rt_spi_transfer_message(spi_dev, &msg1); + + rt_kprintf("spi rbuf : "); + for (i = 0; i < sizeof(r_buf); i++) + { + rt_kprintf("%x ", r_buf[i]); + } + + rt_kprintf("\nspi loopback mode test over!\n"); + + return RT_EOK; +} +MSH_CMD_EXPORT(spi_sample, spi loopback test); diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewd b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewd new file mode 100644 index 0000000000..5c2533da8a --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.ewd @@ -0,0 +1,3276 @@ + + + 4 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-frdm-mcxn947 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + CMSIS_AGDI_V8M + -X"" -O206 -S9 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN4 -FF0MCXN9XX_2048.FLM -FS00 -FL0200000 -FP0($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048.FLM) -FF1MCXN9XX_2048_S.FLM -FS110000000 -FL1200000 -FP1($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048_S.FLM) -FF2MCXN9XX_W25Q64.FLM -FS280000000 -FL2800000 -FP2($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64.FLM) -FF3MCXN9XX_W25Q64_S.FLM -FS390000000 -FL3800000 -FP3($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64_S.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN4 -FF0MCXN9XX_2048 -FS00 -FL0200000 -FF1MCXN9XX_2048_S -FS110000000 -FL1200000 -FF2MCXN9XX_W25Q64 -FS280000000 -FL2800000 -FF3MCXN9XX_W25Q64_S -FS390000000 -FL3800000 -FP0($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048.FLM) -FP1($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048_S.FLM) -FP2($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64.FLM) -FP3($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64_S.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx new file mode 100644 index 0000000000..eb0a4e2380 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/project.uvprojx @@ -0,0 +1,1469 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
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$$Device:MCXN947VDF$MCXN947_cm33_core0.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x3000000 + 0x40000 + + + 1 + 0x30060000 + 0x8000 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x100000 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+ + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\MCXN947_cm33_core0_flash.scf + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\..\..\components\libc\compilers\common\cwchar.c + + + + + DeviceDrivers + + + device.c + 1 + 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+ + + fsl_usdhc.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_usdhc.c + + + + + fsl_erm.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_erm.c + + + + + fsl_dac14.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_dac14.c + + + + + fsl_gpio.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_gpio.c + + + + + fsl_lpi2c.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_lpi2c.c + + + + + fsl_flexspi.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_flexspi.c + + + + + fsl_flexspi_edma.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_flexspi_edma.c + + + + + fsl_ewm.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_ewm.c + + + + + system_MCXN947_cm33_core0.c + 1 + ..\Libraries\MCXN947\MCXN947\system_MCXN947_cm33_core0.c + + + + + fsl_spc.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_spc.c + + + + + fsl_flexio_i2c_master.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_flexio_i2c_master.c + + + + + fsl_ctimer.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_ctimer.c + + + + + fsl_flexio_uart.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_flexio_uart.c + + + + + fsl_enc.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_enc.c + + + + + fsl_i3c.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_i3c.c + + + + + fsl_cache_lpcac.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_cache_lpcac.c + + + + + fsl_enet.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_enet.c + + + + + fsl_lpflexcomm.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_lpflexcomm.c + + + + + fsl_flexio.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_flexio.c + + + + + fsl_edma_soc.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_edma_soc.c + + + + + fsl_evtg.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_evtg.c + + + + + fsl_itrc.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_itrc.c + + + + + fsl_cache.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_cache.c + + + + + fsl_eim.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_eim.c + + + + + fsl_cdog.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_cdog.c + + + + + fsl_flexio_spi.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_flexio_spi.c + + + + + fsl_common.c + 1 + ..\Libraries\MCXN947\MCXN947\drivers\fsl_common.c + + + + + Utilities + + + ulog.c + 1 + ..\..\..\..\..\components\utilities\ulog\ulog.c + + + + + console_be.c + 1 + ..\..\..\..\..\components\utilities\ulog\backend\console_be.c + + + + + + + + + + + + + + + template + 1 + + + + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.h b/bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.h new file mode 100644 index 0000000000..cd974c0c51 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.h @@ -0,0 +1,290 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_MCX + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice optimization */ + + +/* klibc optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart4" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_HWTIMER + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + +#define RT_USING_ULOG +#define ULOG_OUTPUT_LVL_D +#define ULOG_OUTPUT_LVL 7 +#define ULOG_ASSERT_ENABLE +#define ULOG_LINE_BUF_SIZE 128 + +/* log format */ + +#define ULOG_OUTPUT_FLOAT +#define ULOG_OUTPUT_LEVEL +#define ULOG_OUTPUT_TAG +#define ULOG_BACKEND_USING_CONSOLE + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + +#define PKG_USING_RT_VSNPRINTF_FULL +#define PKG_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define PKG_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define PKG_VSNPRINTF_DEFAULT_FLOAT_PRECISION 6 +#define PKG_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define PKG_VSNPRINTF_LOG10_TAYLOR_TERMS 4 +#define PKG_USING_RT_VSNPRINTF_FULL_LATEST_VERSION + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers Config */ + +#define SOC_MCXN947 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_PIN +#define BSP_USING_UART +#define BSP_USING_UART4 +#define BSP_USING_UART5 +#define BSP_USING_UART2 + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.py b/bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.py new file mode 100644 index 0000000000..a6cfb63a48 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/rtconfig.py @@ -0,0 +1,198 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' +BOARD_NAME = 'lpcxpresso' +BSP_LIBRARY_TYPE = 'MCXN236' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'D:\Program Files\IAR Systems\Embedded Workbench 9.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS' + LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--defsym=__heap_size__=0x10000,--gc-sections,-Map=rtthread.map,--print-memory-usage -Tboard/linker_scripts/MCXN947_cm33_core0_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti' + CXXFLAGS += CFLAGS + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./LPC55S69_cm33_core0_flash.scf" ' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M33 ' + CFLAGS = ' --target=arm-arm-none-eabi' + CFLAGS += ' -mcpu=' + CPU + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/MCXN947_cm33_core0_flash.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), '..', 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.ewp b/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.ewp new file mode 100644 index 0000000000..e3ab020500 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.ewp @@ -0,0 +1,2172 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvoptx b/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvoptx new file mode 100644 index 0000000000..8c8f6ed470 --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-frdm-mcxn947 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI_V8M.DLL + + + + 0 + CMSIS_AGDI_V8M + -X"" -O206 -S9 -C0 -P00000000 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN4 -FF0MCXN9XX_2048.FLM -FS00 -FL0200000 -FP0($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048.FLM) -FF1MCXN9XX_2048_S.FLM -FS110000000 -FL1200000 -FP1($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048_S.FLM) -FF2MCXN9XX_W25Q64.FLM -FS280000000 -FL2800000 -FP2($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64.FLM) -FF3MCXN9XX_W25Q64_S.FLM -FS390000000 -FL3800000 -FP3($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64_S.FLM) + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN4 -FF0MCXN9XX_2048 -FS00 -FL0200000 -FF1MCXN9XX_2048_S -FS110000000 -FL1200000 -FF2MCXN9XX_W25Q64 -FS280000000 -FL2800000 -FF3MCXN9XX_W25Q64_S -FS390000000 -FL3800000 -FP0($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048.FLM) -FP1($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_2048_S.FLM) -FP2($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64.FLM) -FP3($$Device:MCXN947VDF$devices\MCXN947\arm\MCXN9XX_W25Q64_S.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvprojx b/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvprojx new file mode 100644 index 0000000000..97a09e1c3f --- /dev/null +++ b/bsp/nxp/mcx/mcxn/frdm-mcxn236/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-frdm-mcxn947 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + MCXN947VDF:cm33_core0 + NXP + NXP.MCXN947_DFP.17.0.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x060000) IRAM2(0x20060000,0x8000) IROM(0x03000000,0x040000) IROM2(0x13000000,0x040000) XRAM(0x30060000,0x8000) XRAM2(0x04000000,0x018000) XRAM3(0x14000000,0x018000) XROM(0x00000000,0x100000) XROM2(0x00100000,0x100000) XROM3(0x10000000,0x100000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN4 -FF0MCXN9XX_2048 -FS00 -FL0200000 -FF1MCXN9XX_2048_S -FS110000000 -FL1200000 -FF2MCXN9XX_W25Q64 -FS280000000 -FL2800000 -FF3MCXN9XX_W25Q64_S -FS390000000 -FL3800000 -FP0($$Device:MCXN947VDF$arm\MCXN9XX_2048.FLM) -FP1($$Device:MCXN947VDF$arm\MCXN9XX_2048_S.FLM) -FP2($$Device:MCXN947VDF$arm\MCXN9XX_W25Q64.FLM) -FP3($$Device:MCXN947VDF$arm\MCXN9XX_W25Q64_S.FLM)) + 0 + $$Device:MCXN947VDF$fsl_device_registers.h + + + + + + + + + + $$Device:MCXN947VDF$MCXN947_cm33_core0.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 2 + 0 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x60000 + + + 1 + 0x3000000 + 0x40000 + + + 1 + 0x30060000 + 0x8000 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x100000 + 0x100000 + + + 1 + 0x10000000 + 0x100000 + + + 1 + 0x3000000 + 0x40000 + + + 1 + 0x13000000 + 0x40000 + + + 0 + 0x30060000 + 0x8000 + + + 0 + 0x4000000 + 0x18000 + + + 0 + 0x14000000 + 0x18000 + + + 0 + 0x20000000 + 0x60000 + + + 0 + 0x20060000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_MCXN947VDF_cm33_core0, ARM_MATH_CM33, RT_USING_ARM_LIBC + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\MCXN947_cm33_core0_flash.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + + + + + + + + + + + template + 1 + + + + + -- Gitee