From 4155d65d21c0aa46fdb87b653320cb3943d0b1fb Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Fri, 30 Sep 2022 19:37:24 +0800
Subject: [PATCH 01/14] =?UTF-8?q?=E6=B7=BB=E5=8A=A0=20cortex=5Fa=20ASID=20?=
 =?UTF-8?q?=E6=94=AF=E6=8C=81=E3=80=82?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 components/lwp/lwp.h            |  7 +++-
 components/lwp/lwp_pid.c        | 11 +++++++
 components/lwp/lwp_user_mm.c    | 57 +++++++++++++++++++++++++++++++++
 libcpu/arm/cortex-a/start_gcc.S | 25 +++++++++++++--
 4 files changed, 96 insertions(+), 4 deletions(-)

diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h
index 319802570d..27f3be2c94 100644
--- a/components/lwp/lwp.h
+++ b/components/lwp/lwp.h
@@ -120,6 +120,11 @@ struct rt_lwp
     char working_directory[DFS_PATH_MAX];
     int debug;
     uint32_t bak_first_ins;
+
+    #ifdef RT_LWP_ENABLE_ASID
+    uint64_t generation;
+    unsigned asid;
+    #endif
 };
 
 struct rt_lwp *lwp_self(void);
@@ -293,6 +298,6 @@ rt_channel_t gdb_server_channel(void);
 int dbg_step_type(void);
 void dbg_attach_req(void *pc);
 int dbg_check_suspend(void);
-void rt_hw_set_process_id(int pid);
+void set_process_id(int pid);
 
 #endif
diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c
index b6e3b67ae3..e2ad0ca5ff 100644
--- a/components/lwp/lwp_pid.c
+++ b/components/lwp/lwp_pid.c
@@ -336,11 +336,18 @@ struct rt_lwp* lwp_new(void)
     }
     lwp->pid = pid;
     lwp_pid_set_lwp(pid, lwp);
+
+    #ifdef RT_LWP_ENABLE_ASID
+    lwp->generation = 0;
+    lwp->asid = 0;
+    #endif
+
 out:
     rt_hw_interrupt_enable(level);
     return lwp;
 }
 
+extern void remove_asid(unsigned asid);
 void lwp_free(struct rt_lwp* lwp)
 {
     rt_base_t level;
@@ -411,6 +418,10 @@ void lwp_free(struct rt_lwp* lwp)
     lwp_unmap_user_space(lwp);
 #endif
 
+#ifdef RT_LWP_ENABLE_ASID
+    remove_asid(lwp->asid);
+#endif
+
     level = rt_hw_interrupt_disable();
     /* for children */
     while (lwp->first_child)
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index f812ebcedc..f1f169b9d3 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -29,7 +29,59 @@ int lwp_user_space_init(struct rt_lwp *lwp)
     return arch_user_space_init(lwp);
 }
 
+#ifdef RT_LWP_ENABLE_ASID
+#define MAX_ASID (1 << MAX_ASID_BITS)
+static uint64_t global_generation = 1;
+static char asid_valid_bitmap[MAX_ASID];
+static unsigned get_update_asid(struct rt_lwp *l)
+{
+    if (l == RT_NULL)
+    {
+        // kernel thread
+        return 0;
+    }
+
+    if (l->generation == global_generation)
+    {
+        return l->asid;
+    }
+
+    for (unsigned i = 1; i < MAX_ASID; i++)
+    {
+        if (asid_valid_bitmap[i] == 0)
+        {
+            asid_valid_bitmap[i] = 1;
+            l->generation = global_generation;
+            l->asid = i;
+            return i;
+        }
+    }
+
+    global_generation++;
+    memset(asid_valid_bitmap, 0, MAX_ASID * sizeof(char));
+
+    asid_valid_bitmap[i] = 1;
+    l->generation = global_generation;
+    l->asid = i;
+
+    // invalidate all TLB entries
+    asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(0)); 
+
+    return 1;
+}
+
+void remove_asid(uint64_t generation, unsigned asid)
+{
+    if (generation == global_generation)
+    {
+        asid_valid_bitmap[asid] = 0;
+    }
+}
+
+void rt_hw_mmu_switch(void *mtable, unsigned char asid);
+#else
 void rt_hw_mmu_switch(void *mtable);
+#endif
 void *rt_hw_mmu_tbl_get(void);
 void lwp_mmu_switch(struct rt_thread *thread)
 {
@@ -49,7 +101,12 @@ void lwp_mmu_switch(struct rt_thread *thread)
     pre_mmu_table = rt_hw_mmu_tbl_get();
     if (pre_mmu_table != new_mmu_table)
     {
+        #ifdef RT_LWP_ENABLE_ASID
+        unsigned asid = get_update_asid(l);
+        rt_hw_mmu_switch(new_mmu_table, asid);
+        #else
         rt_hw_mmu_switch(new_mmu_table);
+        #endif
     }
 }
 
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 35494ce04a..c0a02554e1 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -267,6 +267,24 @@ rt_hw_set_process_id:
     MCR p15, 0, r0, c13, c0, 1
     mov pc, lr
 
+#ifdef RT_LWP_ENABLE_ASID
+.global rt_hw_mmu_switch
+rt_hw_mmu_switch:
+    orr r0, #0x18
+    mcr p15, 0, r0, c2, c0, 0    /* ttbr0   write r0 to ttbr0*/
+
+    and r2, r1, #0xff
+    mov r1, r1, LSL #0x8
+    orr r1, r1, r2                /* r1 = (asid << 8) | (asid & 0xFFUL) */
+    mcr p15, 0, r1, c13, c0, 1    /* set contextid = r1*/ 
+
+    mcr p15, 0, r0, c7, c5, 0    /* iciallu */
+    mcr p15, 0, r0, c7, c5, 6    /* bpiall */
+
+    dsb
+    isb
+    mov pc, lr
+#else
 .global rt_hw_mmu_switch
 rt_hw_mmu_switch:
     orr r0, #0x18
@@ -281,6 +299,7 @@ rt_hw_mmu_switch:
     dsb
     isb
     mov pc, lr
+#endif
 .global rt_hw_mmu_tbl_get
 rt_hw_mmu_tbl_get:
     mrc p15, 0, r0, c2, c0, 0    /* ttbr0 */
@@ -604,8 +623,8 @@ vector_resv:
     b       .
 
 #ifdef RT_USING_SMP
-.global rt_hw_clz
-rt_hw_clz:
+.global rt_clz
+rt_clz:
     clz r0, r0
     bx lr
 
@@ -622,7 +641,7 @@ rt_secondary_cpu_entry:
 after_enable_mmu_n:
     ldr     r0, =MMUTable
     add     r0, r5
-    bl      rt_hw_mmu_switch
+    bl      switch_mmu
 #endif
 
 #ifdef RT_USING_FPU
-- 
Gitee


From e2b138a8165c8c535588ccff41b2d441e3ca208e Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Fri, 30 Sep 2022 23:16:15 +0800
Subject: [PATCH 02/14] fix error

---
 components/lwp/lwp_pid.c     | 4 ++--
 components/lwp/lwp_user_mm.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c
index e2ad0ca5ff..0103b2758f 100644
--- a/components/lwp/lwp_pid.c
+++ b/components/lwp/lwp_pid.c
@@ -347,7 +347,7 @@ out:
     return lwp;
 }
 
-extern void remove_asid(unsigned asid);
+extern void remove_asid(uint64_t generation, unsigned asid);
 void lwp_free(struct rt_lwp* lwp)
 {
     rt_base_t level;
@@ -419,7 +419,7 @@ void lwp_free(struct rt_lwp* lwp)
 #endif
 
 #ifdef RT_LWP_ENABLE_ASID
-    remove_asid(lwp->asid);
+    remove_asid(lwp->generation, lwp->asid);
 #endif
 
     level = rt_hw_interrupt_disable();
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index f1f169b9d3..840bb9fcd8 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -60,9 +60,9 @@ static unsigned get_update_asid(struct rt_lwp *l)
     global_generation++;
     memset(asid_valid_bitmap, 0, MAX_ASID * sizeof(char));
 
-    asid_valid_bitmap[i] = 1;
+    asid_valid_bitmap[1] = 1;
     l->generation = global_generation;
-    l->asid = i;
+    l->asid = 1;
 
     // invalidate all TLB entries
     asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(0)); 
-- 
Gitee


From 8e028f1267a7e66e8e7bc36018716f4384f1bbb6 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Fri, 30 Sep 2022 23:21:41 +0800
Subject: [PATCH 03/14] =?UTF-8?q?=E6=9B=B4=E6=94=B9=E9=94=99=E8=AF=AF=20sw?=
 =?UTF-8?q?itch=5Fmmu=E5=BA=94=E4=B8=BArt=5Fhw=5Fmmu=5Fswitch?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/arm/cortex-a/start_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index c0a02554e1..c89ec1a156 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -641,7 +641,7 @@ rt_secondary_cpu_entry:
 after_enable_mmu_n:
     ldr     r0, =MMUTable
     add     r0, r5
-    bl      switch_mmu
+    bl      rt_hw_mmu_switch
 #endif
 
 #ifdef RT_USING_FPU
-- 
Gitee


From 49765803c700f625b00ee56bbf3aff6797a0ed0f Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Tue, 4 Oct 2022 15:55:32 +0800
Subject: [PATCH 04/14] =?UTF-8?q?=E6=8C=89=E6=8C=87=E4=BB=A4=E9=9B=86?=
 =?UTF-8?q?=E6=89=8B=E5=86=8C=E7=9A=84=E8=AF=B4=E6=98=8E=EF=BC=8C=E4=BF=AE?=
 =?UTF-8?q?=E6=94=B9ASID=E5=92=8CTTBR=E7=9A=84=E5=90=8C=E6=AD=A5=E6=9B=B4?=
 =?UTF-8?q?=E6=96=B0=E3=80=82?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/arm/cortex-a/start_gcc.S | 40 ++++++++++++++++++++++++++++++---
 1 file changed, 37 insertions(+), 3 deletions(-)

diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index c89ec1a156..56822109ef 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -176,7 +176,11 @@ bss_loop:
 #ifdef RT_USING_USERSPACE
     ldr r0, =MMUTable     /* vaddr    */
     add r0, r5            /* to paddr */
+#ifdef RT_LWP_ENABLE_ASID
+    bl  rt_hw_mmu_switch_kernel
+#else
     bl  rt_hw_mmu_switch
+#endif
 #else
     bl rt_hw_mmu_init
 #endif
@@ -270,13 +274,19 @@ rt_hw_set_process_id:
 #ifdef RT_LWP_ENABLE_ASID
 .global rt_hw_mmu_switch
 rt_hw_mmu_switch:
+    mov r3, #0
+    mcr p15, 0, r3, c13, c0, 1   /* set contextid = 0, for synchronization*/ 
+    isb
+    
     orr r0, #0x18
     mcr p15, 0, r0, c2, c0, 0    /* ttbr0   write r0 to ttbr0*/
+    isb
 
-    and r2, r1, #0xff
-    mov r1, r1, LSL #0x8
-    orr r1, r1, r2                /* r1 = (asid << 8) | (asid & 0xFFUL) */
+    mov r1, r1, LSL #0x8         
+    and r2, r2, #0xff             
+    orr r1, r1, r2                /* contextid.PROCID = pid, contextid.ASID = asid*/
     mcr p15, 0, r1, c13, c0, 1    /* set contextid = r1*/ 
+    isb
 
     mcr p15, 0, r0, c7, c5, 0    /* iciallu */
     mcr p15, 0, r0, c7, c5, 6    /* bpiall */
@@ -284,6 +294,25 @@ rt_hw_mmu_switch:
     dsb
     isb
     mov pc, lr
+
+.global rt_hw_mmu_switch_kernel
+rt_hw_mmu_switch_kernel:
+    orr r0, #0x18
+    mcr p15, 0, r0, c2, c0, 0    /* ttbr0 */
+
+    /*  The nG bit of tlb entries of kernel is 0, 
+        so no need to update ASID, 
+        neither to flush TLB
+    */
+    ; mov r0, #0
+    ; mcr p15, 0, r0, c8, c7, 0
+    mcr p15, 0, r0, c7, c5, 0    /* iciallu */
+    mcr p15, 0, r0, c7, c5, 6    /* bpiall */
+
+    dsb
+    isb
+    mov pc, lr
+
 #else
 .global rt_hw_mmu_switch
 rt_hw_mmu_switch:
@@ -300,6 +329,7 @@ rt_hw_mmu_switch:
     isb
     mov pc, lr
 #endif
+
 .global rt_hw_mmu_tbl_get
 rt_hw_mmu_tbl_get:
     mrc p15, 0, r0, c2, c0, 0    /* ttbr0 */
@@ -641,8 +671,12 @@ rt_secondary_cpu_entry:
 after_enable_mmu_n:
     ldr     r0, =MMUTable
     add     r0, r5
+#ifdef RT_LWP_ENABLE_ASID
+    bl      rt_hw_mmu_switch_kernel
+#else
     bl      rt_hw_mmu_switch
 #endif
+#endif
 
 #ifdef RT_USING_FPU
     mov r4, #0xfffffff
-- 
Gitee


From 63ec9e3f670ec47a67fd897ec67e65bc7e91988e Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Tue, 4 Oct 2022 15:57:24 +0800
Subject: [PATCH 05/14] =?UTF-8?q?=E8=AE=BE=E7=BD=AEtlb=E8=A1=A8=E9=A1=B9nG?=
 =?UTF-8?q?=E4=BD=8D=E5=B9=B6=E5=9C=A8mmu=5Fswitch=E6=97=B6=E5=8C=BA?=
 =?UTF-8?q?=E5=88=86=E5=86=85=E6=A0=B8=E5=92=8C=E7=94=A8=E6=88=B7=E8=BF=9B?=
 =?UTF-8?q?=E7=A8=8B=E7=9A=84tlb=E8=A1=A8=E9=A1=B9=E3=80=82?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 bsp/imx6ull-artpi-smart/rtconfig.h |  4 ++++
 components/lwp/lwp_user_mm.c       | 22 ++++++++++++----------
 libcpu/arm/cortex-a/mmu.h          | 19 ++++++++++---------
 3 files changed, 26 insertions(+), 19 deletions(-)

diff --git a/bsp/imx6ull-artpi-smart/rtconfig.h b/bsp/imx6ull-artpi-smart/rtconfig.h
index 0a7f63177b..8f040ba07b 100644
--- a/bsp/imx6ull-artpi-smart/rtconfig.h
+++ b/bsp/imx6ull-artpi-smart/rtconfig.h
@@ -395,4 +395,8 @@
 
 #define BSP_USING_USB_DEVICE
 
+/* enable ASID */
+// #define RT_LWP_ENABLE_ASID
+// #define MAX_ASID_BITS 8
+
 #endif
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index 840bb9fcd8..8536348b76 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -35,12 +35,6 @@ static uint64_t global_generation = 1;
 static char asid_valid_bitmap[MAX_ASID];
 static unsigned get_update_asid(struct rt_lwp *l)
 {
-    if (l == RT_NULL)
-    {
-        // kernel thread
-        return 0;
-    }
-
     if (l->generation == global_generation)
     {
         return l->asid;
@@ -65,7 +59,7 @@ static unsigned get_update_asid(struct rt_lwp *l)
     l->asid = 1;
 
     // invalidate all TLB entries
-    asm volatile("mcr p15, 0, %0, c8, c7, 0"::"r"(0)); 
+    asm volatile ("mcr p15, 0, r0, c8, c7, 0\ndsb\nisb" ::: "memory");
 
     return 1;
 }
@@ -78,7 +72,8 @@ void remove_asid(uint64_t generation, unsigned asid)
     }
 }
 
-void rt_hw_mmu_switch(void *mtable, unsigned char asid);
+void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned char asid);
+void rt_hw_mmu_switch_kernel(void *mtable);
 #else
 void rt_hw_mmu_switch(void *mtable);
 #endif
@@ -102,8 +97,15 @@ void lwp_mmu_switch(struct rt_thread *thread)
     if (pre_mmu_table != new_mmu_table)
     {
         #ifdef RT_LWP_ENABLE_ASID
-        unsigned asid = get_update_asid(l);
-        rt_hw_mmu_switch(new_mmu_table, asid);
+        if (l)
+        {
+            unsigned asid = get_update_asid(l);
+            rt_hw_mmu_switch(new_mmu_table, l->pid, asid);
+        }
+        else 
+        {
+            rt_hw_mmu_switch_kernel(new_mmu_table);
+        }
         #else
         rt_hw_mmu_switch(new_mmu_table);
         #endif
diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h
index a018d292c6..3ffcc61d71 100644
--- a/libcpu/arm/cortex-a/mmu.h
+++ b/libcpu/arm/cortex-a/mmu.h
@@ -61,15 +61,16 @@ struct mem_desc
 #define MMU_MAP_MTBL_TEX(x)   (x<<6)
 #define MMU_MAP_MTBL_AP2(x)   (x<<9)
 #define MMU_MAP_MTBL_SHARE    (1<<10)
-
-#define MMU_MAP_K_RO          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_K_RWCB        (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_K_RW          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_K_DEVICE      (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_RO          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_RWCB        (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_RW          (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
-#define MMU_MAP_U_DEVICE      (MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_MTBL_NG(x)    (x<<11)
+
+#define MMU_MAP_K_RO          (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(1)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_RWCB        (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_RW          (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_K_DEVICE      (MMU_MAP_MTBL_NG(0))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(1)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RO          (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(2)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RWCB        (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_C|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_RW          (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_SHARE)
+#define MMU_MAP_U_DEVICE      (MMU_MAP_MTBL_NG(1))|(MMU_MAP_MTBL_A|MMU_MAP_MTBL_AP2(0)|MMU_MAP_MTBL_AP01(3)|MMU_MAP_MTBL_TEX(0)|MMU_MAP_MTBL_B|MMU_MAP_MTBL_SHARE)
 
 #define ARCH_SECTION_SHIFT  20
 #define ARCH_SECTION_SIZE   (1 << ARCH_SECTION_SHIFT)
-- 
Gitee


From dd471d340860adb8422032844e8ddaeaa4345348 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Thu, 20 Oct 2022 22:30:40 +0800
Subject: [PATCH 06/14] =?UTF-8?q?=E5=88=A0=E9=99=A4=E6=8E=A7=E5=88=B6ASID?=
 =?UTF-8?q?=E5=BC=80=E5=90=AF=E7=9A=84=E5=AE=8FRT=5FLWP=5FENABLE=5FASID?=
 =?UTF-8?q?=EF=BC=8C=E9=BB=98=E8=AE=A4=E5=BC=80=E5=90=AFASID?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 bsp/imx6ull-artpi-smart/rtconfig.h |  4 ----
 components/lwp/lwp.h               |  2 --
 components/lwp/lwp_pid.c           |  4 ----
 components/lwp/lwp_user_mm.c       |  9 +--------
 libcpu/arm/cortex-a/start_gcc.S    | 28 ----------------------------
 5 files changed, 1 insertion(+), 46 deletions(-)

diff --git a/bsp/imx6ull-artpi-smart/rtconfig.h b/bsp/imx6ull-artpi-smart/rtconfig.h
index 8f040ba07b..0a7f63177b 100644
--- a/bsp/imx6ull-artpi-smart/rtconfig.h
+++ b/bsp/imx6ull-artpi-smart/rtconfig.h
@@ -395,8 +395,4 @@
 
 #define BSP_USING_USB_DEVICE
 
-/* enable ASID */
-// #define RT_LWP_ENABLE_ASID
-// #define MAX_ASID_BITS 8
-
 #endif
diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h
index 27f3be2c94..db0dd6b382 100644
--- a/components/lwp/lwp.h
+++ b/components/lwp/lwp.h
@@ -121,10 +121,8 @@ struct rt_lwp
     int debug;
     uint32_t bak_first_ins;
 
-    #ifdef RT_LWP_ENABLE_ASID
     uint64_t generation;
     unsigned asid;
-    #endif
 };
 
 struct rt_lwp *lwp_self(void);
diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c
index 0103b2758f..0312856048 100644
--- a/components/lwp/lwp_pid.c
+++ b/components/lwp/lwp_pid.c
@@ -337,10 +337,8 @@ struct rt_lwp* lwp_new(void)
     lwp->pid = pid;
     lwp_pid_set_lwp(pid, lwp);
 
-    #ifdef RT_LWP_ENABLE_ASID
     lwp->generation = 0;
     lwp->asid = 0;
-    #endif
 
 out:
     rt_hw_interrupt_enable(level);
@@ -418,9 +416,7 @@ void lwp_free(struct rt_lwp* lwp)
     lwp_unmap_user_space(lwp);
 #endif
 
-#ifdef RT_LWP_ENABLE_ASID
     remove_asid(lwp->generation, lwp->asid);
-#endif
 
     level = rt_hw_interrupt_disable();
     /* for children */
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index 8536348b76..26902f4428 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -29,7 +29,7 @@ int lwp_user_space_init(struct rt_lwp *lwp)
     return arch_user_space_init(lwp);
 }
 
-#ifdef RT_LWP_ENABLE_ASID
+#define MAX_ASID_BITS 8
 #define MAX_ASID (1 << MAX_ASID_BITS)
 static uint64_t global_generation = 1;
 static char asid_valid_bitmap[MAX_ASID];
@@ -74,9 +74,6 @@ void remove_asid(uint64_t generation, unsigned asid)
 
 void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned char asid);
 void rt_hw_mmu_switch_kernel(void *mtable);
-#else
-void rt_hw_mmu_switch(void *mtable);
-#endif
 void *rt_hw_mmu_tbl_get(void);
 void lwp_mmu_switch(struct rt_thread *thread)
 {
@@ -96,7 +93,6 @@ void lwp_mmu_switch(struct rt_thread *thread)
     pre_mmu_table = rt_hw_mmu_tbl_get();
     if (pre_mmu_table != new_mmu_table)
     {
-        #ifdef RT_LWP_ENABLE_ASID
         if (l)
         {
             unsigned asid = get_update_asid(l);
@@ -106,9 +102,6 @@ void lwp_mmu_switch(struct rt_thread *thread)
         {
             rt_hw_mmu_switch_kernel(new_mmu_table);
         }
-        #else
-        rt_hw_mmu_switch(new_mmu_table);
-        #endif
     }
 }
 
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 56822109ef..79b62ccf1d 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -176,11 +176,7 @@ bss_loop:
 #ifdef RT_USING_USERSPACE
     ldr r0, =MMUTable     /* vaddr    */
     add r0, r5            /* to paddr */
-#ifdef RT_LWP_ENABLE_ASID
     bl  rt_hw_mmu_switch_kernel
-#else
-    bl  rt_hw_mmu_switch
-#endif
 #else
     bl rt_hw_mmu_init
 #endif
@@ -271,7 +267,6 @@ rt_hw_set_process_id:
     MCR p15, 0, r0, c13, c0, 1
     mov pc, lr
 
-#ifdef RT_LWP_ENABLE_ASID
 .global rt_hw_mmu_switch
 rt_hw_mmu_switch:
     mov r3, #0
@@ -304,31 +299,12 @@ rt_hw_mmu_switch_kernel:
         so no need to update ASID, 
         neither to flush TLB
     */
-    ; mov r0, #0
-    ; mcr p15, 0, r0, c8, c7, 0
-    mcr p15, 0, r0, c7, c5, 0    /* iciallu */
-    mcr p15, 0, r0, c7, c5, 6    /* bpiall */
-
-    dsb
-    isb
-    mov pc, lr
-
-#else
-.global rt_hw_mmu_switch
-rt_hw_mmu_switch:
-    orr r0, #0x18
-    mcr p15, 0, r0, c2, c0, 0    /* ttbr0 */
-
-    /* invalid tlb */
-    mov r0, #0
-    mcr p15, 0, r0, c8, c7, 0
     mcr p15, 0, r0, c7, c5, 0    /* iciallu */
     mcr p15, 0, r0, c7, c5, 6    /* bpiall */
 
     dsb
     isb
     mov pc, lr
-#endif
 
 .global rt_hw_mmu_tbl_get
 rt_hw_mmu_tbl_get:
@@ -671,11 +647,7 @@ rt_secondary_cpu_entry:
 after_enable_mmu_n:
     ldr     r0, =MMUTable
     add     r0, r5
-#ifdef RT_LWP_ENABLE_ASID
     bl      rt_hw_mmu_switch_kernel
-#else
-    bl      rt_hw_mmu_switch
-#endif
 #endif
 
 #ifdef RT_USING_FPU
-- 
Gitee


From 24b0fd0c1965eaf81c1848a588e9e87766d2fd37 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Thu, 20 Oct 2022 23:40:59 +0800
Subject: [PATCH 07/14] =?UTF-8?q?=E6=95=B4=E7=90=86=E4=BB=A3=E7=A0=81?=
 =?UTF-8?q?=EF=BC=8C=E5=8E=BB=E9=99=A4lwp=E4=B8=AD=E6=9E=B6=E6=9E=84?=
 =?UTF-8?q?=E7=9B=B8=E5=85=B3=E7=9A=84=E5=AE=9E=E7=8E=B0=EF=BC=8C=E7=A7=BB?=
 =?UTF-8?q?=E5=88=B0arch=E4=B8=AD?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 .../lwp/arch/aarch64/cortex-a/lwp_arch.c      | 11 ++++
 .../lwp/arch/aarch64/cortex-a/lwp_arch.h      |  3 +
 components/lwp/arch/arm/cortex-a/lwp_arch.c   | 49 ++++++++++++++++
 components/lwp/arch/arm/cortex-a/lwp_arch.h   |  3 +
 components/lwp/arch/risc-v/rv64/lwp_arch.c    | 11 ++++
 components/lwp/arch/risc-v/rv64/lwp_arch.h    |  3 +
 components/lwp/arch/x86/i386/lwp_arch.c       | 11 ++++
 components/lwp/arch/x86/i386/lwp_arch.h       |  3 +
 components/lwp/lwp_pid.c                      |  3 +-
 components/lwp/lwp_user_mm.c                  | 56 +------------------
 10 files changed, 98 insertions(+), 55 deletions(-)

diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c
index c5f4cebdb9..5202e3fc32 100644
--- a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c
+++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c
@@ -74,4 +74,15 @@ int arch_expand_user_stack(void *addr)
     return ret;
 }
 
+unsigned int arch_get_asid(struct rt_lwp *lwp)
+{
+    // TODO
+    return 0;
+}
+
+void arch_remove_asid(struct rt_lwp *lwp)
+{
+    // TODO
+}
+
 #endif
diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.h b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h
index 87354b2752..38b3d7968f 100644
--- a/components/lwp/arch/aarch64/cortex-a/lwp_arch.h
+++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h
@@ -41,6 +41,9 @@ rt_inline void icache_invalid_all(void)
     asm volatile ("ic ialluis\n\tisb sy":::"memory");
 }
 
+unsigned int arch_get_asid(struct rt_lwp *lwp);
+void arch_remove_asid(struct rt_lwp *lwp);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.c b/components/lwp/arch/arm/cortex-a/lwp_arch.c
index 0d0d0cf39f..6f12ddf1a5 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_arch.c
+++ b/components/lwp/arch/arm/cortex-a/lwp_arch.c
@@ -87,4 +87,53 @@ int arch_expand_user_stack(void *addr)
     return ret;
 }
 
+
+#define MAX_ASID_BITS 8
+#define MAX_ASID (1 << MAX_ASID_BITS)
+static uint64_t global_generation = 1;
+static char asid_valid_bitmap[MAX_ASID];
+unsigned int arch_get_asid(struct rt_lwp *lwp)
+{
+    if (lwp == RT_NULL)
+    {
+        // kernel
+        return 0;
+    }
+
+    if (lwp->generation == global_generation)
+    {
+        return lwp->asid;
+    }
+
+    for (unsigned i = 1; i < MAX_ASID; i++)
+    {
+        if (asid_valid_bitmap[i] == 0)
+        {
+            asid_valid_bitmap[i] = 1;
+            lwp->generation = global_generation;
+            lwp->asid = i;
+            return i;
+        }
+    }
+
+    global_generation++;
+    memset(asid_valid_bitmap, 0, MAX_ASID * sizeof(char));
+
+    asid_valid_bitmap[1] = 1;
+    lwp->generation = global_generation;
+    lwp->asid = 1;
+
+    rt_hw_cpu_tlb_invalidate();
+
+    return 1;
+}
+
+void arch_remove_asid(struct rt_lwp *lwp)
+{
+    if (lwp->generation == global_generation)
+    {
+        asid_valid_bitmap[lwp->asid] = 0;
+    }
+}
+
 #endif
diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.h b/components/lwp/arch/arm/cortex-a/lwp_arch.h
index 69fa42fc2a..c3095450b2 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_arch.h
+++ b/components/lwp/arch/arm/cortex-a/lwp_arch.h
@@ -43,6 +43,9 @@ rt_inline void icache_invalid_all(void)
     asm volatile ("mcr p15, 0, r0, c7, c5, 0\ndsb\nisb":::"memory");//iciallu
 }
 
+unsigned int arch_get_asid(struct rt_lwp *lwp);
+void arch_remove_asid(struct rt_lwp *lwp);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.c b/components/lwp/arch/risc-v/rv64/lwp_arch.c
index ef3fc3c17c..57a5c0699f 100644
--- a/components/lwp/arch/risc-v/rv64/lwp_arch.c
+++ b/components/lwp/arch/risc-v/rv64/lwp_arch.c
@@ -238,4 +238,15 @@ void lwp_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_
      */
 }
 
+unsigned int arch_get_asid(struct rt_lwp *lwp)
+{
+    // TODO
+    return 0;
+}
+
+void arch_remove_asid(struct rt_lwp *lwp)
+{
+    // TODO
+}
+
 #endif
diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.h b/components/lwp/arch/risc-v/rv64/lwp_arch.h
index 2a633d422c..a22780c522 100644
--- a/components/lwp/arch/risc-v/rv64/lwp_arch.h
+++ b/components/lwp/arch/risc-v/rv64/lwp_arch.h
@@ -66,6 +66,9 @@ rt_inline void icache_invalid_all(void)
     //TODO:
 }
 
+unsigned int arch_get_asid(struct rt_lwp *lwp);
+void arch_remove_asid(struct rt_lwp *lwp);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/lwp/arch/x86/i386/lwp_arch.c b/components/lwp/arch/x86/i386/lwp_arch.c
index 5682059559..a7d2f115ac 100644
--- a/components/lwp/arch/x86/i386/lwp_arch.c
+++ b/components/lwp/arch/x86/i386/lwp_arch.c
@@ -368,4 +368,15 @@ void lwp_signal_do_return(rt_hw_stack_frame_t *frame)
 }
 #endif /* RT_USING_SIGNALS */
 
+unsigned int arch_get_asid(struct rt_lwp *lwp)
+{
+    // TODO
+    return 0;
+}
+
+void arch_remove_asid(struct rt_lwp *lwp)
+{
+    // TODO
+}
+
 #endif  /* RT_USING_USERSPACE */
diff --git a/components/lwp/arch/x86/i386/lwp_arch.h b/components/lwp/arch/x86/i386/lwp_arch.h
index a9b1d54533..2a70a1160b 100644
--- a/components/lwp/arch/x86/i386/lwp_arch.h
+++ b/components/lwp/arch/x86/i386/lwp_arch.h
@@ -45,6 +45,9 @@ rt_inline unsigned long rt_hw_ffz(unsigned long x)
     return __builtin_ffs(~x) - 1;
 }
 
+unsigned int arch_get_asid(struct rt_lwp *lwp);
+void arch_remove_asid(struct rt_lwp *lwp);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c
index 0312856048..a88252418a 100644
--- a/components/lwp/lwp_pid.c
+++ b/components/lwp/lwp_pid.c
@@ -345,7 +345,6 @@ out:
     return lwp;
 }
 
-extern void remove_asid(uint64_t generation, unsigned asid);
 void lwp_free(struct rt_lwp* lwp)
 {
     rt_base_t level;
@@ -416,7 +415,7 @@ void lwp_free(struct rt_lwp* lwp)
     lwp_unmap_user_space(lwp);
 #endif
 
-    remove_asid(lwp->generation, lwp->asid);
+    arch_remove_asid(lwp);
 
     level = rt_hw_interrupt_disable();
     /* for children */
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index 26902f4428..138225023b 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -29,51 +29,7 @@ int lwp_user_space_init(struct rt_lwp *lwp)
     return arch_user_space_init(lwp);
 }
 
-#define MAX_ASID_BITS 8
-#define MAX_ASID (1 << MAX_ASID_BITS)
-static uint64_t global_generation = 1;
-static char asid_valid_bitmap[MAX_ASID];
-static unsigned get_update_asid(struct rt_lwp *l)
-{
-    if (l->generation == global_generation)
-    {
-        return l->asid;
-    }
-
-    for (unsigned i = 1; i < MAX_ASID; i++)
-    {
-        if (asid_valid_bitmap[i] == 0)
-        {
-            asid_valid_bitmap[i] = 1;
-            l->generation = global_generation;
-            l->asid = i;
-            return i;
-        }
-    }
-
-    global_generation++;
-    memset(asid_valid_bitmap, 0, MAX_ASID * sizeof(char));
-
-    asid_valid_bitmap[1] = 1;
-    l->generation = global_generation;
-    l->asid = 1;
-
-    // invalidate all TLB entries
-    asm volatile ("mcr p15, 0, r0, c8, c7, 0\ndsb\nisb" ::: "memory");
-
-    return 1;
-}
-
-void remove_asid(uint64_t generation, unsigned asid)
-{
-    if (generation == global_generation)
-    {
-        asid_valid_bitmap[asid] = 0;
-    }
-}
-
 void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned char asid);
-void rt_hw_mmu_switch_kernel(void *mtable);
 void *rt_hw_mmu_tbl_get(void);
 void lwp_mmu_switch(struct rt_thread *thread)
 {
@@ -93,15 +49,9 @@ void lwp_mmu_switch(struct rt_thread *thread)
     pre_mmu_table = rt_hw_mmu_tbl_get();
     if (pre_mmu_table != new_mmu_table)
     {
-        if (l)
-        {
-            unsigned asid = get_update_asid(l);
-            rt_hw_mmu_switch(new_mmu_table, l->pid, asid);
-        }
-        else 
-        {
-            rt_hw_mmu_switch_kernel(new_mmu_table);
-        }
+        unsigned int asid = arch_get_asid(l);
+        pid_t pid = l ? l->pid : 0; 
+        rt_hw_mmu_switch(new_mmu_table, pid, asid);
     }
 }
 
-- 
Gitee


From d14daf5fe295f17c62b5f28a9a7db5471b3252d4 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Fri, 21 Oct 2022 09:34:36 +0800
Subject: [PATCH 08/14] =?UTF-8?q?=E4=BD=BF=E7=94=A8=E5=AE=8F=E5=BC=80?=
 =?UTF-8?q?=E5=85=B3=E6=8E=A7=E5=88=B6ASID=E5=BC=80=E5=90=AF?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 components/lwp/Kconfig                        |  4 ++++
 .../lwp/arch/aarch64/cortex-a/lwp_arch.c      | 11 ----------
 .../lwp/arch/aarch64/cortex-a/lwp_arch.h      |  3 ---
 components/lwp/arch/risc-v/rv64/lwp_arch.c    | 11 ----------
 components/lwp/arch/risc-v/rv64/lwp_arch.h    |  3 ---
 components/lwp/arch/x86/i386/lwp_arch.c       | 11 ----------
 components/lwp/arch/x86/i386/lwp_arch.h       |  3 ---
 components/lwp/lwp_user_mm.c                  |  8 ++++++--
 libcpu/arm/cortex-a/start_gcc.S               | 20 ++-----------------
 9 files changed, 12 insertions(+), 62 deletions(-)

diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig
index da62bb0c64..8d36b2d7b6 100644
--- a/components/lwp/Kconfig
+++ b/components/lwp/Kconfig
@@ -34,6 +34,10 @@ if RT_USING_LWP
         int "The maximum number of lwp thread id"
         default 64
 
+    config LWP_ENABLE_ASID
+        bool "The switch of ASID feature"
+        default n
+
     if ARCH_MM_MMU
         config RT_LWP_SHM_MAX_NR
             int "The maximum number of shared memory"
diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c
index 5202e3fc32..c5f4cebdb9 100644
--- a/components/lwp/arch/aarch64/cortex-a/lwp_arch.c
+++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.c
@@ -74,15 +74,4 @@ int arch_expand_user_stack(void *addr)
     return ret;
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp)
-{
-    // TODO
-    return 0;
-}
-
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    // TODO
-}
-
 #endif
diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_arch.h b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h
index 38b3d7968f..87354b2752 100644
--- a/components/lwp/arch/aarch64/cortex-a/lwp_arch.h
+++ b/components/lwp/arch/aarch64/cortex-a/lwp_arch.h
@@ -41,9 +41,6 @@ rt_inline void icache_invalid_all(void)
     asm volatile ("ic ialluis\n\tisb sy":::"memory");
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.c b/components/lwp/arch/risc-v/rv64/lwp_arch.c
index 57a5c0699f..ef3fc3c17c 100644
--- a/components/lwp/arch/risc-v/rv64/lwp_arch.c
+++ b/components/lwp/arch/risc-v/rv64/lwp_arch.c
@@ -238,15 +238,4 @@ void lwp_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_
      */
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp)
-{
-    // TODO
-    return 0;
-}
-
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    // TODO
-}
-
 #endif
diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.h b/components/lwp/arch/risc-v/rv64/lwp_arch.h
index a22780c522..2a633d422c 100644
--- a/components/lwp/arch/risc-v/rv64/lwp_arch.h
+++ b/components/lwp/arch/risc-v/rv64/lwp_arch.h
@@ -66,9 +66,6 @@ rt_inline void icache_invalid_all(void)
     //TODO:
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/lwp/arch/x86/i386/lwp_arch.c b/components/lwp/arch/x86/i386/lwp_arch.c
index a7d2f115ac..5682059559 100644
--- a/components/lwp/arch/x86/i386/lwp_arch.c
+++ b/components/lwp/arch/x86/i386/lwp_arch.c
@@ -368,15 +368,4 @@ void lwp_signal_do_return(rt_hw_stack_frame_t *frame)
 }
 #endif /* RT_USING_SIGNALS */
 
-unsigned int arch_get_asid(struct rt_lwp *lwp)
-{
-    // TODO
-    return 0;
-}
-
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    // TODO
-}
-
 #endif  /* RT_USING_USERSPACE */
diff --git a/components/lwp/arch/x86/i386/lwp_arch.h b/components/lwp/arch/x86/i386/lwp_arch.h
index 2a70a1160b..a9b1d54533 100644
--- a/components/lwp/arch/x86/i386/lwp_arch.h
+++ b/components/lwp/arch/x86/i386/lwp_arch.h
@@ -45,9 +45,6 @@ rt_inline unsigned long rt_hw_ffz(unsigned long x)
     return __builtin_ffs(~x) - 1;
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index 138225023b..9948839ca5 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -35,6 +35,8 @@ void lwp_mmu_switch(struct rt_thread *thread)
 {
     struct rt_lwp *l = RT_NULL;
     void *pre_mmu_table = RT_NULL, *new_mmu_table = RT_NULL;
+    unsigned int asid = 0; 
+    pid_t pid = 0; 
 
     if (thread->lwp)
     {
@@ -49,8 +51,10 @@ void lwp_mmu_switch(struct rt_thread *thread)
     pre_mmu_table = rt_hw_mmu_tbl_get();
     if (pre_mmu_table != new_mmu_table)
     {
-        unsigned int asid = arch_get_asid(l);
-        pid_t pid = l ? l->pid : 0; 
+#ifdef LWP_ENABLE_ASID
+        asid = arch_get_asid(l);
+#endif
+        pid = l ? l->pid : 0; 
         rt_hw_mmu_switch(new_mmu_table, pid, asid);
     }
 }
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 79b62ccf1d..81826476fc 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -176,7 +176,7 @@ bss_loop:
 #ifdef RT_USING_USERSPACE
     ldr r0, =MMUTable     /* vaddr    */
     add r0, r5            /* to paddr */
-    bl  rt_hw_mmu_switch_kernel
+    bl  rt_hw_mmu_switch
 #else
     bl rt_hw_mmu_init
 #endif
@@ -290,22 +290,6 @@ rt_hw_mmu_switch:
     isb
     mov pc, lr
 
-.global rt_hw_mmu_switch_kernel
-rt_hw_mmu_switch_kernel:
-    orr r0, #0x18
-    mcr p15, 0, r0, c2, c0, 0    /* ttbr0 */
-
-    /*  The nG bit of tlb entries of kernel is 0, 
-        so no need to update ASID, 
-        neither to flush TLB
-    */
-    mcr p15, 0, r0, c7, c5, 0    /* iciallu */
-    mcr p15, 0, r0, c7, c5, 6    /* bpiall */
-
-    dsb
-    isb
-    mov pc, lr
-
 .global rt_hw_mmu_tbl_get
 rt_hw_mmu_tbl_get:
     mrc p15, 0, r0, c2, c0, 0    /* ttbr0 */
@@ -647,7 +631,7 @@ rt_secondary_cpu_entry:
 after_enable_mmu_n:
     ldr     r0, =MMUTable
     add     r0, r5
-    bl      rt_hw_mmu_switch_kernel
+    bl      rt_hw_mmu_switch
 #endif
 
 #ifdef RT_USING_FPU
-- 
Gitee


From fa944d8e3d3b3c866544f6fedb7d55f9d5b27dc4 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Fri, 21 Oct 2022 09:40:43 +0800
Subject: [PATCH 09/14] fix unsigned to unsigned int

---
 components/lwp/lwp.h     | 2 +-
 components/lwp/lwp_pid.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h
index db0dd6b382..96041dd782 100644
--- a/components/lwp/lwp.h
+++ b/components/lwp/lwp.h
@@ -122,7 +122,7 @@ struct rt_lwp
     uint32_t bak_first_ins;
 
     uint64_t generation;
-    unsigned asid;
+    unsigned int asid;
 };
 
 struct rt_lwp *lwp_self(void);
diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c
index a88252418a..745a1071fe 100644
--- a/components/lwp/lwp_pid.c
+++ b/components/lwp/lwp_pid.c
@@ -415,7 +415,9 @@ void lwp_free(struct rt_lwp* lwp)
     lwp_unmap_user_space(lwp);
 #endif
 
+#ifdef LWP_ENABLE_ASID
     arch_remove_asid(lwp);
+#endif
 
     level = rt_hw_interrupt_disable();
     /* for children */
-- 
Gitee


From 2866a08d60aae40e25c0bd38161cfba230127130 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Fri, 21 Oct 2022 09:54:25 +0800
Subject: [PATCH 10/14] fix asid switch in start_gcc.S

---
 libcpu/arm/cortex-a/start_gcc.S | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 81826476fc..14ce7363f4 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -274,14 +274,19 @@ rt_hw_mmu_switch:
     isb
     
     orr r0, #0x18
-    mcr p15, 0, r0, c2, c0, 0    /* ttbr0   write r0 to ttbr0*/
-    isb
+    mcr p15, 0, r0, c2, c0, 0    /* ttbr0 */
 
+#ifdef LWP_ENABLE_ASID
+    isb
     mov r1, r1, LSL #0x8         
     and r2, r2, #0xff             
     orr r1, r1, r2                /* contextid.PROCID = pid, contextid.ASID = asid*/
     mcr p15, 0, r1, c13, c0, 1    /* set contextid = r1*/ 
     isb
+#else
+    mov r0, #0
+    mcr p15, 0, r0, c8, c7, 0
+#endif
 
     mcr p15, 0, r0, c7, c5, 0    /* iciallu */
     mcr p15, 0, r0, c7, c5, 6    /* bpiall */
-- 
Gitee


From 6c2fda1fa6f71f6fff755b696cd1a2cb5662ccb4 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Thu, 27 Oct 2022 13:23:14 +0800
Subject: [PATCH 11/14] =?UTF-8?q?rt=5Fhw=5Fmmu=5Fswitch=E4=B8=8D=E5=90=8C?=
 =?UTF-8?q?=E6=9E=B6=E6=9E=84=E5=AE=B6=E5=8F=A3=E4=B8=8D=E4=B8=80=E8=87=B4?=
 =?UTF-8?q?=E7=9A=84=E9=97=AE=E9=A2=98=E3=80=82=E5=88=A0=E9=99=A4remove=5F?=
 =?UTF-8?q?asid=E5=87=BD=E6=95=B0=E3=80=82?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 components/lwp/arch/arm/cortex-a/lwp_arch.c | 20 +++++++++-----------
 components/lwp/arch/arm/cortex-a/lwp_arch.h |  1 -
 components/lwp/lwp_pid.c                    |  6 ++----
 components/lwp/lwp_user_mm.c                | 14 ++++++++------
 4 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.c b/components/lwp/arch/arm/cortex-a/lwp_arch.c
index 6f12ddf1a5..9bf18f61d6 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_arch.c
+++ b/components/lwp/arch/arm/cortex-a/lwp_arch.c
@@ -105,6 +105,12 @@ unsigned int arch_get_asid(struct rt_lwp *lwp)
         return lwp->asid;
     }
 
+    if (lwp->asid && !asid_valid_bitmap[lwp->asid])
+    {
+        asid_valid_bitmap[lwp->asid] = 1;
+        return lwp->asid;
+    }
+
     for (unsigned i = 1; i < MAX_ASID; i++)
     {
         if (asid_valid_bitmap[i] == 0)
@@ -112,7 +118,7 @@ unsigned int arch_get_asid(struct rt_lwp *lwp)
             asid_valid_bitmap[i] = 1;
             lwp->generation = global_generation;
             lwp->asid = i;
-            return i;
+            return lwp->asid;
         }
     }
 
@@ -123,17 +129,9 @@ unsigned int arch_get_asid(struct rt_lwp *lwp)
     lwp->generation = global_generation;
     lwp->asid = 1;
 
-    rt_hw_cpu_tlb_invalidate();
-
-    return 1;
-}
+    asm volatile ("mcr p15, 0, r0, c8, c7, 0\ndsb\nisb" ::: "memory");
 
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    if (lwp->generation == global_generation)
-    {
-        asid_valid_bitmap[lwp->asid] = 0;
-    }
+    return lwp->asid;
 }
 
 #endif
diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.h b/components/lwp/arch/arm/cortex-a/lwp_arch.h
index c3095450b2..18e4e0b369 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_arch.h
+++ b/components/lwp/arch/arm/cortex-a/lwp_arch.h
@@ -44,7 +44,6 @@ rt_inline void icache_invalid_all(void)
 }
 
 unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
 
 #ifdef __cplusplus
 }
diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c
index 745a1071fe..809339f68f 100644
--- a/components/lwp/lwp_pid.c
+++ b/components/lwp/lwp_pid.c
@@ -337,8 +337,10 @@ struct rt_lwp* lwp_new(void)
     lwp->pid = pid;
     lwp_pid_set_lwp(pid, lwp);
 
+#ifdef LWP_ENABLE_ASID
     lwp->generation = 0;
     lwp->asid = 0;
+#endif
 
 out:
     rt_hw_interrupt_enable(level);
@@ -415,10 +417,6 @@ void lwp_free(struct rt_lwp* lwp)
     lwp_unmap_user_space(lwp);
 #endif
 
-#ifdef LWP_ENABLE_ASID
-    arch_remove_asid(lwp);
-#endif
-
     level = rt_hw_interrupt_disable();
     /* for children */
     while (lwp->first_child)
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index 9948839ca5..73097d814b 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -29,14 +29,16 @@ int lwp_user_space_init(struct rt_lwp *lwp)
     return arch_user_space_init(lwp);
 }
 
-void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned char asid);
+#ifdef LWP_ENABLE_ASID
+void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned int asid);
+#else
+void rt_hw_mmu_switch(void *mtable);
+#endif
 void *rt_hw_mmu_tbl_get(void);
 void lwp_mmu_switch(struct rt_thread *thread)
 {
     struct rt_lwp *l = RT_NULL;
     void *pre_mmu_table = RT_NULL, *new_mmu_table = RT_NULL;
-    unsigned int asid = 0; 
-    pid_t pid = 0; 
 
     if (thread->lwp)
     {
@@ -52,10 +54,10 @@ void lwp_mmu_switch(struct rt_thread *thread)
     if (pre_mmu_table != new_mmu_table)
     {
 #ifdef LWP_ENABLE_ASID
-        asid = arch_get_asid(l);
+        rt_hw_mmu_switch(new_mmu_table, l ? l->pid : 0, arch_get_asid(l));
+#else
+        rt_hw_mmu_switch(new_mmu_table);
 #endif
-        pid = l ? l->pid : 0; 
-        rt_hw_mmu_switch(new_mmu_table, pid, asid);
     }
 }
 
-- 
Gitee


From 071511de4f4f925d7105e52b4d0a286cecf31c8b Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Thu, 27 Oct 2022 13:23:14 +0800
Subject: [PATCH 12/14] =?UTF-8?q?rt=5Fhw=5Fmmu=5Fswitch=E4=B8=8D=E5=90=8C?=
 =?UTF-8?q?=E6=9E=B6=E6=9E=84=E6=8E=A5=E5=8F=A3=E4=B8=8D=E4=B8=80=E8=87=B4?=
 =?UTF-8?q?=E7=9A=84=E9=97=AE=E9=A2=98=E3=80=82=E5=88=A0=E9=99=A4remove=5F?=
 =?UTF-8?q?asid=E5=87=BD=E6=95=B0=E3=80=82?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

ff#
---
 components/lwp/arch/arm/cortex-a/lwp_arch.c | 20 +++++++++-----------
 components/lwp/arch/arm/cortex-a/lwp_arch.h |  1 -
 components/lwp/lwp_pid.c                    |  6 ++----
 components/lwp/lwp_user_mm.c                | 14 ++++++++------
 4 files changed, 19 insertions(+), 22 deletions(-)

diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.c b/components/lwp/arch/arm/cortex-a/lwp_arch.c
index 6f12ddf1a5..9bf18f61d6 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_arch.c
+++ b/components/lwp/arch/arm/cortex-a/lwp_arch.c
@@ -105,6 +105,12 @@ unsigned int arch_get_asid(struct rt_lwp *lwp)
         return lwp->asid;
     }
 
+    if (lwp->asid && !asid_valid_bitmap[lwp->asid])
+    {
+        asid_valid_bitmap[lwp->asid] = 1;
+        return lwp->asid;
+    }
+
     for (unsigned i = 1; i < MAX_ASID; i++)
     {
         if (asid_valid_bitmap[i] == 0)
@@ -112,7 +118,7 @@ unsigned int arch_get_asid(struct rt_lwp *lwp)
             asid_valid_bitmap[i] = 1;
             lwp->generation = global_generation;
             lwp->asid = i;
-            return i;
+            return lwp->asid;
         }
     }
 
@@ -123,17 +129,9 @@ unsigned int arch_get_asid(struct rt_lwp *lwp)
     lwp->generation = global_generation;
     lwp->asid = 1;
 
-    rt_hw_cpu_tlb_invalidate();
-
-    return 1;
-}
+    asm volatile ("mcr p15, 0, r0, c8, c7, 0\ndsb\nisb" ::: "memory");
 
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    if (lwp->generation == global_generation)
-    {
-        asid_valid_bitmap[lwp->asid] = 0;
-    }
+    return lwp->asid;
 }
 
 #endif
diff --git a/components/lwp/arch/arm/cortex-a/lwp_arch.h b/components/lwp/arch/arm/cortex-a/lwp_arch.h
index c3095450b2..18e4e0b369 100644
--- a/components/lwp/arch/arm/cortex-a/lwp_arch.h
+++ b/components/lwp/arch/arm/cortex-a/lwp_arch.h
@@ -44,7 +44,6 @@ rt_inline void icache_invalid_all(void)
 }
 
 unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
 
 #ifdef __cplusplus
 }
diff --git a/components/lwp/lwp_pid.c b/components/lwp/lwp_pid.c
index 745a1071fe..809339f68f 100644
--- a/components/lwp/lwp_pid.c
+++ b/components/lwp/lwp_pid.c
@@ -337,8 +337,10 @@ struct rt_lwp* lwp_new(void)
     lwp->pid = pid;
     lwp_pid_set_lwp(pid, lwp);
 
+#ifdef LWP_ENABLE_ASID
     lwp->generation = 0;
     lwp->asid = 0;
+#endif
 
 out:
     rt_hw_interrupt_enable(level);
@@ -415,10 +417,6 @@ void lwp_free(struct rt_lwp* lwp)
     lwp_unmap_user_space(lwp);
 #endif
 
-#ifdef LWP_ENABLE_ASID
-    arch_remove_asid(lwp);
-#endif
-
     level = rt_hw_interrupt_disable();
     /* for children */
     while (lwp->first_child)
diff --git a/components/lwp/lwp_user_mm.c b/components/lwp/lwp_user_mm.c
index 9948839ca5..73097d814b 100644
--- a/components/lwp/lwp_user_mm.c
+++ b/components/lwp/lwp_user_mm.c
@@ -29,14 +29,16 @@ int lwp_user_space_init(struct rt_lwp *lwp)
     return arch_user_space_init(lwp);
 }
 
-void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned char asid);
+#ifdef LWP_ENABLE_ASID
+void rt_hw_mmu_switch(void *mtable, unsigned int pid, unsigned int asid);
+#else
+void rt_hw_mmu_switch(void *mtable);
+#endif
 void *rt_hw_mmu_tbl_get(void);
 void lwp_mmu_switch(struct rt_thread *thread)
 {
     struct rt_lwp *l = RT_NULL;
     void *pre_mmu_table = RT_NULL, *new_mmu_table = RT_NULL;
-    unsigned int asid = 0; 
-    pid_t pid = 0; 
 
     if (thread->lwp)
     {
@@ -52,10 +54,10 @@ void lwp_mmu_switch(struct rt_thread *thread)
     if (pre_mmu_table != new_mmu_table)
     {
 #ifdef LWP_ENABLE_ASID
-        asid = arch_get_asid(l);
+        rt_hw_mmu_switch(new_mmu_table, l ? l->pid : 0, arch_get_asid(l));
+#else
+        rt_hw_mmu_switch(new_mmu_table);
 #endif
-        pid = l ? l->pid : 0; 
-        rt_hw_mmu_switch(new_mmu_table, pid, asid);
     }
 }
 
-- 
Gitee


From d33b1cc655f031de138cbdf3f43838dd8bbce829 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Thu, 27 Oct 2022 23:32:45 +0800
Subject: [PATCH 13/14] =?UTF-8?q?=E5=88=A0=E9=99=A4start=5Fgcc=E4=B8=AD?=
 =?UTF-8?q?=E7=9A=84ASID=E5=AE=8F=E5=BC=80=E5=85=B3?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 libcpu/arm/cortex-a/start_gcc.S | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 14ce7363f4..512474abb9 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -276,17 +276,12 @@ rt_hw_mmu_switch:
     orr r0, #0x18
     mcr p15, 0, r0, c2, c0, 0    /* ttbr0 */
 
-#ifdef LWP_ENABLE_ASID
     isb
     mov r1, r1, LSL #0x8         
     and r2, r2, #0xff             
     orr r1, r1, r2                /* contextid.PROCID = pid, contextid.ASID = asid*/
     mcr p15, 0, r1, c13, c0, 1    /* set contextid = r1*/ 
     isb
-#else
-    mov r0, #0
-    mcr p15, 0, r0, c8, c7, 0
-#endif
 
     mcr p15, 0, r0, c7, c5, 0    /* iciallu */
     mcr p15, 0, r0, c7, c5, 6    /* bpiall */
-- 
Gitee


From 55d56cf730fbcc473b20abf22df416dbd1b2bd55 Mon Sep 17 00:00:00 2001
From: chenhy0106 <1002138131@qq.com>
Date: Fri, 28 Oct 2022 16:52:26 +0800
Subject: [PATCH 14/14] =?UTF-8?q?=E4=BF=9D=E7=95=99rt=5Fhw=E5=89=8D?=
 =?UTF-8?q?=E7=BC=80=E3=80=82=E8=B0=83=E6=95=B4KConfig?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 components/lwp/Kconfig          | 3 ++-
 components/lwp/lwp.h            | 4 +++-
 libcpu/arm/cortex-a/start_gcc.S | 5 ++---
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig
index 8d36b2d7b6..c4178c8274 100644
--- a/components/lwp/Kconfig
+++ b/components/lwp/Kconfig
@@ -36,7 +36,8 @@ if RT_USING_LWP
 
     config LWP_ENABLE_ASID
         bool "The switch of ASID feature"
-        default n
+        depends on ARCH_ARM_CORTEX_A
+        default y
 
     if ARCH_MM_MMU
         config RT_LWP_SHM_MAX_NR
diff --git a/components/lwp/lwp.h b/components/lwp/lwp.h
index 96041dd782..2725f0b838 100644
--- a/components/lwp/lwp.h
+++ b/components/lwp/lwp.h
@@ -121,8 +121,10 @@ struct rt_lwp
     int debug;
     uint32_t bak_first_ins;
 
+#ifdef LWP_ENABLE_ASID
     uint64_t generation;
     unsigned int asid;
+#endif
 };
 
 struct rt_lwp *lwp_self(void);
@@ -296,6 +298,6 @@ rt_channel_t gdb_server_channel(void);
 int dbg_step_type(void);
 void dbg_attach_req(void *pc);
 int dbg_check_suspend(void);
-void set_process_id(int pid);
+void rt_hw_set_process_id(int pid);
 
 #endif
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 512474abb9..9e652f0240 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -289,7 +289,6 @@ rt_hw_mmu_switch:
     dsb
     isb
     mov pc, lr
-
 .global rt_hw_mmu_tbl_get
 rt_hw_mmu_tbl_get:
     mrc p15, 0, r0, c2, c0, 0    /* ttbr0 */
@@ -613,8 +612,8 @@ vector_resv:
     b       .
 
 #ifdef RT_USING_SMP
-.global rt_clz
-rt_clz:
+.global rt_hw_clz
+rt_hw_clz:
     clz r0, r0
     bx lr
 
-- 
Gitee