From eaf064d61adade5663597a62306c1f9d851c6be8 Mon Sep 17 00:00:00 2001 From: shaojinchun Date: Mon, 14 Feb 2022 09:27:37 +0800 Subject: [PATCH] =?UTF-8?q?=E5=90=88=E5=B9=B6lwp=5Fcheck=5Fdebug=E5=92=8Cl?= =?UTF-8?q?wp=5Fcheck=5Fexit=E5=8A=9F=E8=83=BD=E5=88=B0=E5=8D=95=E4=B8=80l?= =?UTF-8?q?wp=5Fcheck=5Fdebug=E5=87=BD=E6=95=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../lwp/arch/aarch64/cortex-a/lwp_gcc.S | 58 ++----------------- components/lwp/arch/arm/cortex-a/lwp_gcc.S | 19 +++--- libcpu/aarch64/common/context_gcc.S | 10 ++-- libcpu/arm/cortex-a/context_gcc.S | 1 - libcpu/arm/cortex-a/start_gcc.S | 3 +- 5 files changed, 18 insertions(+), 73 deletions(-) diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S index 3a64d71412..ef15f104ec 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S @@ -371,56 +371,6 @@ ret_to_user: 1: eret -.global lwp_check_exit -lwp_check_exit: - SAVE_FPU sp - stp x0, x1, [sp, #-0x10]! - stp x2, x3, [sp, #-0x10]! - stp x4, x5, [sp, #-0x10]! - stp x6, x7, [sp, #-0x10]! - stp x10, x11, [sp, #-0x10]! - stp x12, x13, [sp, #-0x10]! - stp x14, x15, [sp, #-0x10]! - stp x16, x17, [sp, #-0x10]! - stp x18, x19, [sp, #-0x10]! - stp x20, x21, [sp, #-0x10]! - stp x22, x23, [sp, #-0x10]! - stp x24, x25, [sp, #-0x10]! - stp x26, x27, [sp, #-0x10]! - stp x28, x29, [sp, #-0x10]! - mrs x0, fpcr - mrs x1, fpsr - stp x0, x1, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! - - bl lwp_check_exit_request - cmp x0, xzr - bne 1f - ldp x29, x30, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - msr fpcr, x0 - msr fpsr, x1 - ldp x28, x29, [sp], #0x10 - ldp x26, x27, [sp], #0x10 - ldp x24, x25, [sp], #0x10 - ldp x22, x23, [sp], #0x10 - ldp x20, x21, [sp], #0x10 - ldp x18, x19, [sp], #0x10 - ldp x16, x17, [sp], #0x10 - ldp x14, x15, [sp], #0x10 - ldp x12, x13, [sp], #0x10 - ldp x10, x11, [sp], #0x10 - ldp x6, x7, [sp], #0x10 - ldp x4, x5, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - RESTORE_FPU sp - - br x30 -1: - mov x0, xzr - b sys_exit - /* struct rt_hw_exp_stack { @@ -493,9 +443,13 @@ lwp_check_debug: stp x0, x1, [sp, #-0x10]! stp x29, x30, [sp, #-0x10]! + bl lwp_check_exit_request + cbz x0, 1f + mov x0, xzr + b sys_exit +1: bl dbg_check_suspend - cmp w0, wzr - beq lwp_check_debug_quit + cbz w0, lwp_check_debug_quit mrs x2, sp_el0 sub x2, x2, #8 diff --git a/components/lwp/arch/arm/cortex-a/lwp_gcc.S b/components/lwp/arch/arm/cortex-a/lwp_gcc.S index 6284442c89..81d1418c3e 100644 --- a/components/lwp/arch/arm/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/arm/cortex-a/lwp_gcc.S @@ -208,18 +208,6 @@ ret_to_user: movs pc, lr #ifdef RT_USING_LWP -.global lwp_check_exit -lwp_check_exit: - push {r0 - r12, lr} - bl lwp_check_exit_request - cmp r0, #0 - beq 1f - mov r0, #0 - bl sys_exit -1: - pop {r0 - r12, pc} -#endif - .global lwp_check_debug lwp_check_debug: ldr r0, =rt_dbg_ops @@ -229,6 +217,12 @@ lwp_check_debug: bx lr 1: push {r0 - r12, lr} + bl lwp_check_exit_request + cmp r0, #0 + beq 2f + mov r0, #0 + bl sys_exit +2: bl dbg_check_suspend cmp r0, #0 beq lwp_check_debug_quit @@ -342,6 +336,7 @@ lwp_thread_return: mov r0, #0 mov r7, #0x01 svc #0 +#endif .global check_vfp check_vfp: diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S index 1c0b5711df..afb92b30a5 100644 --- a/libcpu/aarch64/common/context_gcc.S +++ b/libcpu/aarch64/common/context_gcc.S @@ -145,8 +145,7 @@ rt_hw_get_gtimer_frq: MOV SP, X0 #ifdef RT_USING_LWP - bl lwp_check_debug - BL lwp_check_exit + BL lwp_check_debug #endif LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ @@ -188,11 +187,8 @@ rt_hw_get_gtimer_frq: #ifdef RT_USING_LWP bl lwp_check_debug - bl lwp_check_exit #endif - BL lwp_check_exit - BL rt_thread_self MOV X19, X0 BL lwp_mmu_switch @@ -235,7 +231,9 @@ rt_hw_get_gtimer_frq: .macro RESTORE_CONTEXT_WITHOUT_MMU_SWITCH /* the SP is already ok */ - BL lwp_check_exit +#ifdef RT_USING_LWP + bl lwp_check_debug +#endif LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S index 9549129c0d..f537f003cf 100644 --- a/libcpu/arm/cortex-a/context_gcc.S +++ b/libcpu/arm/cortex-a/context_gcc.S @@ -248,7 +248,6 @@ rt_hw_context_switch_exit: #ifdef RT_USING_LWP bl lwp_check_debug - bl lwp_check_exit #endif #ifdef RT_USING_LWP diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 28dd4be3a9..3e4083d7f0 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -407,7 +407,7 @@ vector_irq: mrs r4, spsr sub r5, lr, #4 cps #Mode_SVC - bl lwp_check_exit + bl lwp_check_debug and r6, r4, #0x1f cmp r6, #0x10 bne 1f @@ -507,7 +507,6 @@ rt_hw_context_switch_interrupt_do: #ifdef RT_USING_LWP bl lwp_check_debug - bl lwp_check_exit #endif #ifdef RT_USING_LWP -- Gitee