From f9a3cba0811d50654e200d0e220f20eebdf95841 Mon Sep 17 00:00:00 2001 From: shaojinchun Date: Fri, 11 Feb 2022 19:29:05 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=AD=A3=E5=9C=A8=E6=B2=A1=E6=9C=89?= =?UTF-8?q?=E5=AE=9A=E4=B9=89lwp=E6=97=B6=E7=BC=96=E8=AF=91=E5=87=BA?= =?UTF-8?q?=E9=94=99=E7=9A=84=E9=97=AE=E9=A2=98?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/aarch64/common/context_gcc.S | 4 +++- libcpu/arm/cortex-a/context_gcc.S | 3 +-- libcpu/arm/cortex-a/start_gcc.S | 3 +-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S index 36bb2adcac..1c0b5711df 100644 --- a/libcpu/aarch64/common/context_gcc.S +++ b/libcpu/aarch64/common/context_gcc.S @@ -144,9 +144,10 @@ rt_hw_get_gtimer_frq: /* Set the SP to point to the stack of the task being restored. */ MOV SP, X0 +#ifdef RT_USING_LWP bl lwp_check_debug - BL lwp_check_exit +#endif LDP X2, X3, [SP], #0x10 /* SPSR and ELR. */ @@ -186,6 +187,7 @@ rt_hw_get_gtimer_frq: MOV SP, X0 #ifdef RT_USING_LWP + bl lwp_check_debug bl lwp_check_exit #endif diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S index a64790b584..9549129c0d 100644 --- a/libcpu/arm/cortex-a/context_gcc.S +++ b/libcpu/arm/cortex-a/context_gcc.S @@ -246,9 +246,8 @@ rt_hw_context_switch_exit: ldmfd sp!, {r1} msr spsr_cxsf, r1 /* original mode */ - bl lwp_check_debug - #ifdef RT_USING_LWP + bl lwp_check_debug bl lwp_check_exit #endif diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index c20f2fa13d..28dd4be3a9 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -505,9 +505,8 @@ rt_hw_context_switch_interrupt_do: ldmfd sp!, {r4} /* pop new task's cpsr to spsr */ msr spsr_cxsf, r4 - bl lwp_check_debug - #ifdef RT_USING_LWP + bl lwp_check_debug bl lwp_check_exit #endif -- Gitee